espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-02 04:04:31 +02:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'bugfix/lightsleep_reslove_crash' into 'master'

Browse Source 
Fix reboot or crash when enable lightsleep on esp32s2

Closes WIFI-2248

See merge request espressif/esp-idf!10327
This commit is contained in:
Jiang Jiang Jian
2020-09-09 18:39:42 +08:00
parent 5db977c512 aa43ed8bb8
commit b5e9047e47
3 changed files with 17 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
components/esp_system/CMakeLists.txt
View File

@@ -22,3 +22,8 @@ set_source_files_properties(
startup.c startup.c
PROPERTIES COMPILE_FLAGS PROPERTIES COMPILE_FLAGS
-fno-stack-protector) -fno-stack-protector)
if(NOT CMAKE_BUILD_EARLY_EXPANSION)
set_source_files_properties("${CMAKE_CURRENT_LIST_DIR}/sleep_modes.c" PROPERTIES
COMPILE_FLAGS "-fno-jump-tables -fno-tree-switch-conversion")
endif()

12
components/esp_system/sleep_modes.c
View File

@@ -71,10 +71,10 @@
#endif #endif
#if defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS) || defined(CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS) #if defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS) || defined(CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS)
#define LIGHT_SLEEP_TIME_OVERHEAD_US (650 + 30 * 240 / DEFAULT_CPU_FREQ_MHZ) #define LIGHT_SLEEP_TIME_OVERHEAD_US (1650 + 30 * 240 / DEFAULT_CPU_FREQ_MHZ)
#define DEEP_SLEEP_TIME_OVERHEAD_US (650 + 100 * 240 / DEFAULT_CPU_FREQ_MHZ) #define DEEP_SLEEP_TIME_OVERHEAD_US (650 + 100 * 240 / DEFAULT_CPU_FREQ_MHZ)
#else #else
#define LIGHT_SLEEP_TIME_OVERHEAD_US (250 + 30 * 240 / DEFAULT_CPU_FREQ_MHZ) #define LIGHT_SLEEP_TIME_OVERHEAD_US (1250 + 30 * 240 / DEFAULT_CPU_FREQ_MHZ)
#define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / DEFAULT_CPU_FREQ_MHZ) #define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / DEFAULT_CPU_FREQ_MHZ)
#endif #endif
@@ -232,11 +232,9 @@ static void IRAM_ATTR resume_uarts(void)
REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON); REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON);
#elif CONFIG_IDF_TARGET_ESP32S2 #elif CONFIG_IDF_TARGET_ESP32S2
if (periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) { if (periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) {
REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON); REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF);
REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_SW_FLOW_CON_EN | UART_FORCE_XOFF); REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON);
while (REG_GET_FIELD(UART_FSM_STATUS_REG(i), UART_ST_UTX_OUT) != 0) { REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_SW_FLOW_CON_EN | UART_FORCE_XON);
;
}
} }
#endif #endif
} }

7
components/esp_system/startup.c
View File

@@ -370,10 +370,17 @@ IRAM_ATTR ESP_SYSTEM_INIT_FN(init_components0, BIT(0))
esp_pm_impl_init(); esp_pm_impl_init();
#ifdef CONFIG_PM_DFS_INIT_AUTO #ifdef CONFIG_PM_DFS_INIT_AUTO
int xtal_freq = (int) rtc_clk_xtal_freq_get(); int xtal_freq = (int) rtc_clk_xtal_freq_get();
#ifdef CONFIG_IDF_TARGET_ESP32
esp_pm_config_esp32_t cfg = { esp_pm_config_esp32_t cfg = {
.max_freq_mhz = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ, .max_freq_mhz = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ,
.min_freq_mhz = xtal_freq, .min_freq_mhz = xtal_freq,
}; };
#else
esp_pm_config_esp32s2_t cfg = {
.max_freq_mhz = CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ,
.min_freq_mhz = xtal_freq,
};
#endif
esp_pm_configure(&cfg); esp_pm_configure(&cfg);
#endif //CONFIG_PM_DFS_INIT_AUTO #endif //CONFIG_PM_DFS_INIT_AUTO
#endif //CONFIG_PM_ENABLE #endif //CONFIG_PM_ENABLE