From b6076491eeb10010e333a7d50aa7e0531f75db82 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Thu, 24 Oct 2024 14:38:13 +0800 Subject: [PATCH] fix(esp_hw_support): disable unused clock sources after rtc clock switching complete --- components/esp_system/port/soc/esp32c6/clk.c | 11 ++++++++++- components/esp_system/port/soc/esp32h2/clk.c | 11 ++++++++++- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c index 606ec40d61..eaeaa7a648 100644 --- a/components/esp_system/port/soc/esp32c6/clk.c +++ b/components/esp_system/port/soc/esp32c6/clk.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -163,6 +163,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) } rtc_clk_slow_src_set(rtc_slow_clk_src); + // Disable unused clock sources after clock source switching is complete. + // Regardless of the clock source selection, the internal 136K clock source will always keep on. + if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { + rtc_clk_32k_enable(false); + } + if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) { + rtc_clk_rc32k_enable(false); + } + if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. * Improve calibration routine to wait until the frequency is stable. diff --git a/components/esp_system/port/soc/esp32h2/clk.c b/components/esp_system/port/soc/esp32h2/clk.c index 39a781b648..4a6634d177 100644 --- a/components/esp_system/port/soc/esp32h2/clk.c +++ b/components/esp_system/port/soc/esp32h2/clk.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -165,6 +165,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src) } rtc_clk_slow_src_set(rtc_slow_clk_src); + // Disable unused clock sources after clock source switching is complete. + // Regardless of the clock source selection, the internal 136K clock source will always keep on. + if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) { + rtc_clk_32k_enable(false); + } + if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) { + rtc_clk_rc32k_enable(false); + } + if (SLOW_CLK_CAL_CYCLES > 0) { /* TODO: 32k XTAL oscillator has some frequency drift at startup. * Improve calibration routine to wait until the frequency is stable.