diff --git a/components/esp_hw_support/include/esp_private/esp_memprot_internal.h b/components/esp_hw_support/include/esp_private/esp_memprot_internal.h index f7a7349fb2..8a000c1aa8 100644 --- a/components/esp_hw_support/include/esp_private/esp_memprot_internal.h +++ b/components/esp_hw_support/include/esp_private/esp_memprot_internal.h @@ -21,12 +21,12 @@ extern "C" { /** * @brief Convert Memprot low level errors to esp_err_t */ -esp_err_t esp_mprot_ll_err_to_esp_err(const memprot_ll_err_t err); +esp_err_t esp_mprot_ll_err_to_esp_err(const memprot_hal_err_t err); /** * @brief Convert Memprot low level PMS World IDs to esp_mprot_pms_world_t */ -esp_mprot_pms_world_t esp_mprot_ll_world_to_hl_world(const memprot_ll_world_t world); +esp_mprot_pms_world_t esp_mprot_ll_world_to_hl_world(const memprot_hal_world_t world); /** * @brief Converts operation type to string, no combination of operations allowed diff --git a/components/esp_hw_support/include/soc/esp32s3/soc_memprot_types.h b/components/esp_hw_support/include/soc/esp32s3/soc_memprot_types.h index 8902a54ee3..a5e2351a6c 100644 --- a/components/esp_hw_support/include/soc/esp32s3/soc_memprot_types.h +++ b/components/esp_hw_support/include/soc/esp32s3/soc_memprot_types.h @@ -86,8 +86,7 @@ typedef struct { .invoke_panic_handler = true, \ .lock_feature = true, \ .split_addr = NULL, \ - /* .mem_type_mask = MEMPROT_TYPE_ALL, \ - unless IDF-5208 gets merged */ \ - .mem_type_mask = MEMPROT_TYPE_IRAM0_SRAM | MEMPROT_TYPE_DRAM0_SRAM, \ + .mem_type_mask = MEMPROT_TYPE_ALL, \ .target_cpu_count = 2, \ .target_cpu = {PRO_CPU_NUM, APP_CPU_NUM} \ } @@ -102,9 +101,8 @@ typedef struct { #define ESP_MEMPROT_DEFAULT_CONFIG() { \ .invoke_panic_handler = true, \ .lock_feature = true, \ - .split_addr = NULL, \ - /* .mem_type_mask = MEMPROT_TYPE_ALL, \ - unless IDF-5208 gets merged */ \ - .mem_type_mask = MEMPROT_TYPE_IRAM0_SRAM | MEMPROT_TYPE_DRAM0_SRAM, \ + .split_addr = NULL, \ + .mem_type_mask = MEMPROT_TYPE_ALL, \ .target_cpu_count = 1, \ .target_cpu = {PRO_CPU_NUM} \ } diff --git a/components/esp_hw_support/port/esp32c3/esp_memprot.c b/components/esp_hw_support/port/esp32c3/esp_memprot.c index 1566c100a0..547e31a6f7 100644 --- a/components/esp_hw_support/port/esp32c3/esp_memprot.c +++ b/components/esp_hw_support/port/esp32c3/esp_memprot.c @@ -62,7 +62,7 @@ esp_err_t esp_mprot_set_split_addr(const esp_mprot_mem_t mem_type, const esp_mpr case MEMPROT_TYPE_IRAM0_RTCFAST: if (line_type == MEMPROT_SPLIT_ADDR_MAIN) { /* so far only WORLD_0 is supported */ - return esp_mprot_ll_err_to_esp_err(memprot_ll_set_rtcfast_split_line(line_addr, MEMP_LL_WORLD_0)); + return esp_mprot_ll_err_to_esp_err(memprot_ll_set_rtcfast_split_line(line_addr, MEMP_HAL_WORLD_0)); } else { return ESP_ERR_MEMPROT_SPLIT_ADDR_INVALID; } @@ -107,7 +107,7 @@ esp_err_t esp_mprot_get_split_addr(const esp_mprot_mem_t mem_type, const esp_mpr case MEMPROT_TYPE_IRAM0_RTCFAST: if (line_type == MEMPROT_SPLIT_ADDR_MAIN) { /* so far only WORLD_0 is supported */ - return esp_mprot_ll_err_to_esp_err(memprot_ll_get_rtcfast_split_line(MEMP_LL_WORLD_0, line_addr)); + return esp_mprot_ll_err_to_esp_err(memprot_ll_get_rtcfast_split_line(MEMP_HAL_WORLD_0, line_addr)); } else { return ESP_ERR_MEMPROT_SPLIT_ADDR_INVALID; } @@ -256,10 +256,10 @@ esp_err_t esp_mprot_set_pms_area(const esp_mprot_pms_area_t area_type, const uin memprot_ll_dram0_set_pms_area_3(r, w); break; case MEMPROT_PMS_AREA_IRAM0_RTCFAST_LO: - memprot_ll_rtcfast_set_pms_area(r, w, x, MEMP_LL_WORLD_0, MEMP_LL_AREA_LOW); + memprot_ll_rtcfast_set_pms_area(r, w, x, MEMP_HAL_WORLD_0, MEMP_HAL_AREA_LOW); break; case MEMPROT_PMS_AREA_IRAM0_RTCFAST_HI: - memprot_ll_rtcfast_set_pms_area(r, w, x, MEMP_LL_WORLD_0, MEMP_LL_AREA_HIGH); + memprot_ll_rtcfast_set_pms_area(r, w, x, MEMP_HAL_WORLD_0, MEMP_HAL_AREA_HIGH); break; default: return ESP_ERR_NOT_SUPPORTED; @@ -304,10 +304,10 @@ esp_err_t esp_mprot_get_pms_area(const esp_mprot_pms_area_t area_type, uint32_t memprot_ll_dram0_get_pms_area_3(&r, &w); break; case MEMPROT_PMS_AREA_IRAM0_RTCFAST_LO: - memprot_ll_rtcfast_get_pms_area(&r, &w, &x, MEMP_LL_WORLD_0, MEMP_LL_AREA_LOW); + memprot_ll_rtcfast_get_pms_area(&r, &w, &x, MEMP_HAL_WORLD_0, MEMP_HAL_AREA_LOW); break; case MEMPROT_PMS_AREA_IRAM0_RTCFAST_HI: - memprot_ll_rtcfast_get_pms_area(&r, &w, &x, MEMP_LL_WORLD_0, MEMP_LL_AREA_HIGH); + memprot_ll_rtcfast_get_pms_area(&r, &w, &x, MEMP_HAL_WORLD_0, MEMP_HAL_AREA_HIGH); break; default: return ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID; @@ -786,7 +786,7 @@ esp_err_t esp_mprot_dump_configuration(char **dump_info_string) uint32_t offset = strlen(*dump_info_string); void *line_RTC = NULL; - esp_err_t err = esp_mprot_ll_err_to_esp_err(memprot_ll_get_rtcfast_split_line(MEMP_LL_WORLD_0, &line_RTC)); + esp_err_t err = esp_mprot_ll_err_to_esp_err(memprot_ll_get_rtcfast_split_line(MEMP_HAL_WORLD_0, &line_RTC)); if (err != ESP_OK) { sprintf((*dump_info_string + offset), " RTCFAST:\n line main: N/A (world=0) - %s\n", esp_err_to_name(err)); } else { @@ -828,7 +828,7 @@ esp_err_t esp_mprot_dump_configuration(char **dump_info_string) bool arl0rtc, awl0rtc, axl0rtc; bool arh0rtc, awh0rtc, axh0rtc; - err = esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_get_pms_area(&arl0rtc, &awl0rtc, &axl0rtc, MEMP_LL_WORLD_0, MEMP_LL_AREA_LOW)); + err = esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_get_pms_area(&arl0rtc, &awl0rtc, &axl0rtc, MEMP_HAL_WORLD_0, MEMP_HAL_AREA_LOW)); if (err != ESP_OK) { sprintf((*dump_info_string + offset), " area low: N/A - %s\n", esp_err_to_name(err)); } else { @@ -837,7 +837,7 @@ esp_err_t esp_mprot_dump_configuration(char **dump_info_string) offset = strlen(*dump_info_string); - err = esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_get_pms_area(&arh0rtc, &awh0rtc, &axh0rtc, MEMP_LL_WORLD_0, MEMP_LL_AREA_HIGH)); + err = esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_get_pms_area(&arh0rtc, &awh0rtc, &axh0rtc, MEMP_HAL_WORLD_0, MEMP_HAL_AREA_HIGH)); if (err != ESP_OK) { sprintf((*dump_info_string + offset), " area high: N/A - %s\n", esp_err_to_name(err)); } else { diff --git a/components/esp_hw_support/port/esp32s2/memprot.c b/components/esp_hw_support/port/esp32s2/memprot.c index 544c256228..ab9c69070d 100644 --- a/components/esp_hw_support/port/esp32s2/memprot.c +++ b/components/esp_hw_support/port/esp32s2/memprot.c @@ -25,14 +25,14 @@ extern int _data_start; extern int _rtc_text_end; extern int _rtc_dummy_end; -static inline esp_err_t esp_memprot_ll_err_to_esp_err(memprot_ll_err_t err) +static inline esp_err_t esp_memprot_ll_err_to_esp_err(memprot_hal_err_t err) { switch (err) { - case MEMP_LL_OK: return ESP_OK; - case MEMP_LL_FAIL: return ESP_FAIL; - case MEMP_LL_ERR_SPLIT_ADDR_INVALID: return ESP_ERR_INVALID_STATE; - case MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED: return ESP_ERR_INVALID_SIZE; - case MEMP_LL_ERR_UNI_BLOCK_INVALID: return ESP_ERR_NOT_FOUND; + case MEMP_HAL_OK: return ESP_OK; + case MEMP_HAL_FAIL: return ESP_FAIL; + case MEMP_HAL_ERR_SPLIT_ADDR_INVALID: return ESP_ERR_INVALID_STATE; + case MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED: return ESP_ERR_INVALID_SIZE; + case MEMP_HAL_ERR_UNI_BLOCK_INVALID: return ESP_ERR_NOT_FOUND; default: return ESP_FAIL; } diff --git a/components/esp_hw_support/port/esp32s3/esp_memprot.c b/components/esp_hw_support/port/esp32s3/esp_memprot.c index 717c75ff77..9a71437c49 100644 --- a/components/esp_hw_support/port/esp32s3/esp_memprot.c +++ b/components/esp_hw_support/port/esp32s3/esp_memprot.c @@ -124,7 +124,7 @@ esp_err_t esp_mprot_set_split_addr(const esp_mprot_mem_t mem_type, const esp_mpr if (line_type == MEMPROT_SPLIT_ADDR_MAIN) { /* so far only WORLD_0 is supported */ esp_err_t err; ESP_MEMPROT_ERR_CHECK(err, esp_mprot_cpuid_valid(core)) - ESP_MEMPROT_ERR_CHECK(err, esp_mprot_ll_err_to_esp_err(memprot_ll_set_rtcfast_split_line(core, line_addr, MEMP_LL_WORLD_0))) + ESP_MEMPROT_ERR_CHECK(err, esp_mprot_ll_err_to_esp_err(memprot_ll_set_rtcfast_split_line(core, line_addr, MEMP_HAL_WORLD_0))) return ESP_OK; } else { return ESP_ERR_MEMPROT_SPLIT_ADDR_INVALID; @@ -171,7 +171,7 @@ esp_err_t esp_mprot_get_split_addr(const esp_mprot_mem_t mem_type, const esp_mpr if (line_type == MEMPROT_SPLIT_ADDR_MAIN) { /* so far only WORLD_0 is supported */ esp_err_t err; ESP_MEMPROT_ERR_CHECK(err, esp_mprot_cpuid_valid(core)) - ESP_MEMPROT_ERR_CHECK(err, esp_mprot_ll_err_to_esp_err(memprot_ll_get_rtcfast_split_line(core, MEMP_LL_WORLD_0, *line_addr))) + ESP_MEMPROT_ERR_CHECK(err, esp_mprot_ll_err_to_esp_err(memprot_ll_get_rtcfast_split_line(core, MEMP_HAL_WORLD_0, *line_addr))) } else { return ESP_ERR_MEMPROT_SPLIT_ADDR_INVALID; } @@ -328,11 +328,11 @@ esp_err_t esp_mprot_set_pms_area(const esp_mprot_pms_area_t area_type, const uin break; case MEMPROT_PMS_AREA_IRAM0_RTCFAST_LO: ESP_MEMPROT_ERR_CHECK(err, esp_mprot_cpuid_valid(core)) - ESP_MEMPROT_ERR_CHECK(err, esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_set_pms_area(core, r, w, x, MEMP_LL_WORLD_0, MEMP_LL_AREA_LOW))) + ESP_MEMPROT_ERR_CHECK(err, esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_set_pms_area(core, r, w, x, MEMP_HAL_WORLD_0, MEMP_HAL_AREA_LOW))) break; case MEMPROT_PMS_AREA_IRAM0_RTCFAST_HI: ESP_MEMPROT_ERR_CHECK(err, esp_mprot_cpuid_valid(core)) - ESP_MEMPROT_ERR_CHECK(err, esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_set_pms_area(core, r, w, x, MEMP_LL_WORLD_0, MEMP_LL_AREA_HIGH))) + ESP_MEMPROT_ERR_CHECK(err, esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_set_pms_area(core, r, w, x, MEMP_HAL_WORLD_0, MEMP_HAL_AREA_HIGH))) break; default: return ESP_ERR_NOT_SUPPORTED; @@ -379,11 +379,11 @@ esp_err_t esp_mprot_get_pms_area(const esp_mprot_pms_area_t area_type, uint32_t break; case MEMPROT_PMS_AREA_IRAM0_RTCFAST_LO: ESP_MEMPROT_ERR_CHECK(err, esp_mprot_cpuid_valid(core)) - ESP_MEMPROT_ERR_CHECK(err, esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_get_pms_area(core, &r, &w, &x, MEMP_LL_WORLD_0, MEMP_LL_AREA_LOW))) + ESP_MEMPROT_ERR_CHECK(err, esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_get_pms_area(core, &r, &w, &x, MEMP_HAL_WORLD_0, MEMP_HAL_AREA_LOW))) break; case MEMPROT_PMS_AREA_IRAM0_RTCFAST_HI: ESP_MEMPROT_ERR_CHECK(err, esp_mprot_cpuid_valid(core)) - ESP_MEMPROT_ERR_CHECK(err, esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_get_pms_area(core, &r, &w, &x, MEMP_LL_WORLD_0, MEMP_LL_AREA_HIGH))) + ESP_MEMPROT_ERR_CHECK(err, esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_get_pms_area(core, &r, &w, &x, MEMP_HAL_WORLD_0, MEMP_HAL_AREA_HIGH))) break; default: return ESP_ERR_MEMPROT_MEMORY_TYPE_INVALID; @@ -1259,7 +1259,7 @@ esp_err_t esp_mprot_dump_configuration(char **dump_info_string) offset = strlen(*dump_info_string); void *line_RTC = NULL; - esp_err_t err = esp_mprot_ll_err_to_esp_err(memprot_ll_get_rtcfast_split_line(PRO_CPU_NUM, MEMP_LL_WORLD_0, &line_RTC)); + esp_err_t err = esp_mprot_ll_err_to_esp_err(memprot_ll_get_rtcfast_split_line(PRO_CPU_NUM, MEMP_HAL_WORLD_0, &line_RTC)); if (err != ESP_OK) { sprintf((*dump_info_string + offset), " RTCFAST:\n line main: N/A (world=0) - %s\n", esp_err_to_name(err)); } else { @@ -1301,7 +1301,7 @@ esp_err_t esp_mprot_dump_configuration(char **dump_info_string) bool arl0rtc, awl0rtc, axl0rtc; bool arh0rtc, awh0rtc, axh0rtc; - err = esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_get_pms_area(PRO_CPU_NUM, &arl0rtc, &awl0rtc, &axl0rtc, MEMP_LL_WORLD_0, MEMP_LL_AREA_LOW)); + err = esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_get_pms_area(PRO_CPU_NUM, &arl0rtc, &awl0rtc, &axl0rtc, MEMP_HAL_WORLD_0, MEMP_HAL_AREA_LOW)); if (err != ESP_OK) { sprintf((*dump_info_string + offset), " area low: N/A - %s\n", esp_err_to_name(err)); } else { @@ -1310,7 +1310,7 @@ esp_err_t esp_mprot_dump_configuration(char **dump_info_string) offset = strlen(*dump_info_string); - err = esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_get_pms_area(PRO_CPU_NUM, &arh0rtc, &awh0rtc, &axh0rtc, MEMP_LL_WORLD_0, MEMP_LL_AREA_HIGH)); + err = esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_get_pms_area(PRO_CPU_NUM, &arh0rtc, &awh0rtc, &axh0rtc, MEMP_HAL_WORLD_0, MEMP_HAL_AREA_HIGH)); if (err != ESP_OK) { sprintf((*dump_info_string + offset), " area high: N/A - %s\n", esp_err_to_name(err)); } else { @@ -1328,7 +1328,7 @@ esp_err_t esp_mprot_dump_configuration(char **dump_info_string) offset = strlen(*dump_info_string); - err = esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_get_pms_area(APP_CPU_NUM, &arl0rtc, &awl0rtc, &axl0rtc, MEMP_LL_WORLD_0, MEMP_LL_AREA_LOW)); + err = esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_get_pms_area(APP_CPU_NUM, &arl0rtc, &awl0rtc, &axl0rtc, MEMP_HAL_WORLD_0, MEMP_HAL_AREA_LOW)); if (err != ESP_OK) { sprintf((*dump_info_string + offset), " area low: N/A - %s\n", esp_err_to_name(err)); } else { @@ -1337,7 +1337,7 @@ esp_err_t esp_mprot_dump_configuration(char **dump_info_string) offset = strlen(*dump_info_string); - err = esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_get_pms_area(APP_CPU_NUM, &arh0rtc, &awh0rtc, &axh0rtc, MEMP_LL_WORLD_0, MEMP_LL_AREA_HIGH)); + err = esp_mprot_ll_err_to_esp_err(memprot_ll_rtcfast_get_pms_area(APP_CPU_NUM, &arh0rtc, &awh0rtc, &axh0rtc, MEMP_HAL_WORLD_0, MEMP_HAL_AREA_HIGH)); if (err != ESP_OK) { sprintf((*dump_info_string + offset), " area high: N/A - %s\n", esp_err_to_name(err)); } else { diff --git a/components/esp_hw_support/port/esp_memprot_conv.c b/components/esp_hw_support/port/esp_memprot_conv.c index e3d4557306..665b771dd7 100644 --- a/components/esp_hw_support/port/esp_memprot_conv.c +++ b/components/esp_hw_support/port/esp_memprot_conv.c @@ -8,26 +8,26 @@ #include "hal/memprot_types.h" #include "esp_memprot_types.h" -esp_err_t esp_mprot_ll_err_to_esp_err(const memprot_ll_err_t err) +esp_err_t esp_mprot_ll_err_to_esp_err(const memprot_hal_err_t err) { switch (err) { - case MEMP_LL_OK: return ESP_OK; - case MEMP_LL_ERR_SPLIT_ADDR_OUT_OF_RANGE: return ESP_ERR_MEMPROT_SPLIT_ADDR_OUT_OF_RANGE; - case MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED: return ESP_ERR_MEMPROT_SPLIT_ADDR_UNALIGNED; - case MEMP_LL_ERR_UNI_BLOCK_INVALID: return ESP_ERR_MEMPROT_UNIMGMT_BLOCK_INVALID; - case MEMP_LL_ERR_WORLD_INVALID: return ESP_ERR_MEMPROT_WORLD_INVALID; - case MEMP_LL_ERR_AREA_INVALID: return ESP_ERR_MEMPROT_AREA_INVALID; + case MEMP_HAL_OK: return ESP_OK; + case MEMP_HAL_ERR_SPLIT_ADDR_OUT_OF_RANGE: return ESP_ERR_MEMPROT_SPLIT_ADDR_OUT_OF_RANGE; + case MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED: return ESP_ERR_MEMPROT_SPLIT_ADDR_UNALIGNED; + case MEMP_HAL_ERR_UNI_BLOCK_INVALID: return ESP_ERR_MEMPROT_UNIMGMT_BLOCK_INVALID; + case MEMP_HAL_ERR_WORLD_INVALID: return ESP_ERR_MEMPROT_WORLD_INVALID; + case MEMP_HAL_ERR_AREA_INVALID: return ESP_ERR_MEMPROT_AREA_INVALID; default: return ESP_FAIL; } } -esp_mprot_pms_world_t esp_mprot_ll_world_to_hl_world(const memprot_ll_world_t world) +esp_mprot_pms_world_t esp_mprot_ll_world_to_hl_world(const memprot_hal_world_t world) { switch (world) { - case MEMP_LL_WORLD_NONE: return MEMPROT_PMS_WORLD_NONE; - case MEMP_LL_WORLD_0: return MEMPROT_PMS_WORLD_0; - case MEMP_LL_WORLD_1: return MEMPROT_PMS_WORLD_1; + case MEMP_HAL_WORLD_NONE: return MEMPROT_PMS_WORLD_NONE; + case MEMP_HAL_WORLD_0: return MEMPROT_PMS_WORLD_0; + case MEMP_HAL_WORLD_1: return MEMPROT_PMS_WORLD_1; default: return MEMPROT_PMS_WORLD_INVALID; } diff --git a/components/esp_system/port/arch/riscv/panic_arch.c b/components/esp_system/port/arch/riscv/panic_arch.c index 9ad4aba0ee..3afa68ae6e 100644 --- a/components/esp_system/port/arch/riscv/panic_arch.c +++ b/components/esp_system/port/arch/riscv/panic_arch.c @@ -160,9 +160,11 @@ static inline void print_cache_err_details(const void *frame) static esp_memp_intr_source_t s_memp_intr = {MEMPROT_TYPE_INVALID, -1}; #define PRINT_MEMPROT_ERROR(err) \ - panic_print_str("N/A (error "); \ - panic_print_str(esp_err_to_name(err)); \ - panic_print_str(")") + do { \ + panic_print_str("N/A (error "); \ + panic_print_str(esp_err_to_name(err)); \ + panic_print_str(")"); \ + } while(0) static inline void print_memprot_err_details(const void *frame __attribute__((unused))) { diff --git a/components/hal/esp32c3/include/hal/memprot_ll.h b/components/hal/esp32c3/include/hal/memprot_ll.h index 0312a91f3d..77227351ee 100644 --- a/components/hal/esp32c3/include/hal/memprot_ll.h +++ b/components/hal/esp32c3/include/hal/memprot_ll.h @@ -61,16 +61,16 @@ static inline uint32_t memprot_ll_iram0_get_intr_source_num(void) * 1. IRAM0/DRAM0 split-lines must be aligned to 512B boundaries (PMS module restriction) * 2. split address must fall into appropriate IRAM0/DRAM0 region */ -static inline memprot_ll_err_t memprot_ll_set_iram0_split_line(const void *line_addr, uint32_t sensitive_reg) +static inline memprot_hal_err_t memprot_ll_set_iram0_split_line(const void *line_addr, uint32_t sensitive_reg) { uint32_t addr = (uint32_t)line_addr; if (addr < IRAM0_SRAM_LEVEL_1_LOW || addr > IRAM0_SRAM_LEVEL_3_HIGH) { - return MEMP_LL_ERR_SPLIT_ADDR_OUT_OF_RANGE; + return MEMP_HAL_ERR_SPLIT_ADDR_OUT_OF_RANGE; } if (addr % 0x200 != 0) { - return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED; + return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED; } uint32_t category[3] = {0}; @@ -95,21 +95,21 @@ static inline memprot_ll_err_t memprot_ll_set_iram0_split_line(const void *line_ REG_WRITE(sensitive_reg, reg_cfg); - return MEMP_LL_OK; + return MEMP_HAL_OK; } /* can be both IRAM0/DRAM0 address */ -static inline memprot_ll_err_t memprot_ll_set_iram0_split_line_main_I_D(const void *line_addr) +static inline memprot_hal_err_t memprot_ll_set_iram0_split_line_main_I_D(const void *line_addr) { return memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG); } -static inline memprot_ll_err_t memprot_ll_set_iram0_split_line_I_0(const void *line_addr) +static inline memprot_hal_err_t memprot_ll_set_iram0_split_line_I_0(const void *line_addr) { return memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG); } -static inline memprot_ll_err_t memprot_ll_set_iram0_split_line_I_1(const void *line_addr) +static inline memprot_hal_err_t memprot_ll_set_iram0_split_line_I_1(const void *line_addr) { return memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG); } @@ -343,59 +343,59 @@ static inline uint32_t memprot_ll_rtcfast_get_splitaddr_register(void) * 2. RTCFAST split-line must be aligned to 4B boundaries (PMS stores 11 bits of 13-bit offset in 8kB RTCFAST region) * 3. RTCFAST has weird section structure (text -> dummy (!) -> force -> data) - .dummy section seems to have wrong mapping (it doesn't fall inline with .rtctext) */ -static inline memprot_ll_err_t memprot_ll_set_rtcfast_split_line(const void *line_addr, memprot_ll_world_t world) +static inline memprot_hal_err_t memprot_ll_set_rtcfast_split_line(const void *line_addr, memprot_hal_world_t world) { uint32_t addr = (uint32_t)line_addr; uint32_t mask; if (addr < SOC_RTC_IRAM_LOW || addr >= SOC_RTC_IRAM_HIGH) { - return MEMP_LL_ERR_SPLIT_ADDR_OUT_OF_RANGE; + return MEMP_HAL_ERR_SPLIT_ADDR_OUT_OF_RANGE; } if (addr % 0x4 != 0) { - return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED; + return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED; } switch (world) { - case MEMP_LL_WORLD_0: + case MEMP_HAL_WORLD_0: mask = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M; break; - case MEMP_LL_WORLD_1: + case MEMP_HAL_WORLD_1: mask = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M; break; default: - return MEMP_LL_ERR_WORLD_INVALID; + return MEMP_HAL_ERR_WORLD_INVALID; } //offset bits to store are the same width for both worlds -> using SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V CLEAR_PERI_REG_MASK(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG, mask); REG_SET_BITS(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG, mask, (addr >> 2) & SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V); - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_get_rtcfast_split_line(memprot_ll_world_t world, void **line_addr) +static inline memprot_hal_err_t memprot_ll_get_rtcfast_split_line(memprot_hal_world_t world, void **line_addr) { uint32_t reg_addr = REG_READ(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG); uint32_t mask = 0; uint32_t shift = 0; switch (world) { - case MEMP_LL_WORLD_0: + case MEMP_HAL_WORLD_0: mask = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M; shift = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S; break; - case MEMP_LL_WORLD_1: + case MEMP_HAL_WORLD_1: mask = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M; shift = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S; break; default: - return MEMP_LL_ERR_WORLD_INVALID; + return MEMP_HAL_ERR_WORLD_INVALID; } *line_addr = (void *)((((reg_addr & mask) >> shift) << 2) + SOC_RTC_IRAM_LOW); - return MEMP_LL_OK; + return MEMP_HAL_OK; } /////////////////////////////////// @@ -418,48 +418,48 @@ static inline uint32_t memprot_ll_rtcfast_set_permissions(bool r, bool w, bool x return permissions; } -static inline memprot_ll_err_t memprot_ll_rtcfast_set_pms_area(bool r, bool w, bool x, memprot_ll_world_t world, memprot_ll_area_t area) +static inline memprot_hal_err_t memprot_ll_rtcfast_set_pms_area(bool r, bool w, bool x, memprot_hal_world_t world, memprot_hal_area_t area) { uint32_t bits = 0; uint32_t mask = 0; switch (world) { - case MEMP_LL_WORLD_0: { + case MEMP_HAL_WORLD_0: { switch (area) { - case MEMP_LL_AREA_LOW: + case MEMP_HAL_AREA_LOW: bits = memprot_ll_rtcfast_set_permissions(r, w, x) << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S; mask = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M; break; - case MEMP_LL_AREA_HIGH: + case MEMP_HAL_AREA_HIGH: bits = memprot_ll_rtcfast_set_permissions(r, w, x) << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S; mask = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M; break; default: - return MEMP_LL_ERR_AREA_INVALID; + return MEMP_HAL_ERR_AREA_INVALID; } } break; - case MEMP_LL_WORLD_1: { + case MEMP_HAL_WORLD_1: { switch (area) { - case MEMP_LL_AREA_LOW: + case MEMP_HAL_AREA_LOW: bits = memprot_ll_rtcfast_set_permissions(r, w, x) << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S; mask = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M; break; - case MEMP_LL_AREA_HIGH: + case MEMP_HAL_AREA_HIGH: bits = memprot_ll_rtcfast_set_permissions(r, w, x) << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S; mask = SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M; break; default: - return MEMP_LL_ERR_AREA_INVALID; + return MEMP_HAL_ERR_AREA_INVALID; } } break; default: - return MEMP_LL_ERR_WORLD_INVALID; + return MEMP_HAL_ERR_WORLD_INVALID; } CLEAR_PERI_REG_MASK(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, mask); REG_SET_BITS(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, bits, mask); - return MEMP_LL_OK; + return MEMP_HAL_OK; } static inline void memprot_ll_rtcfast_get_permissions(uint32_t perms, bool *r, bool *w, bool *x) @@ -469,42 +469,42 @@ static inline void memprot_ll_rtcfast_get_permissions(uint32_t perms, bool *r, b *x = perms & SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F; } -static inline memprot_ll_err_t memprot_ll_rtcfast_get_pms_area(bool *r, bool *w, bool *x, memprot_ll_world_t world, memprot_ll_area_t area) +static inline memprot_hal_err_t memprot_ll_rtcfast_get_pms_area(bool *r, bool *w, bool *x, memprot_hal_world_t world, memprot_hal_area_t area) { uint32_t permissions = 0; switch (world) { - case MEMP_LL_WORLD_0: { + case MEMP_HAL_WORLD_0: { switch (area) { - case MEMP_LL_AREA_LOW: + case MEMP_HAL_AREA_LOW: permissions = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L); break; - case MEMP_LL_AREA_HIGH: + case MEMP_HAL_AREA_HIGH: permissions = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H); break; default: - return MEMP_LL_ERR_AREA_INVALID; + return MEMP_HAL_ERR_AREA_INVALID; } } break; - case MEMP_LL_WORLD_1: { + case MEMP_HAL_WORLD_1: { switch (area) { - case MEMP_LL_AREA_LOW: + case MEMP_HAL_AREA_LOW: permissions = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L); break; - case MEMP_LL_AREA_HIGH: + case MEMP_HAL_AREA_HIGH: permissions = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H); break; default: - return MEMP_LL_ERR_AREA_INVALID; + return MEMP_HAL_ERR_AREA_INVALID; } } break; default: - return MEMP_LL_ERR_WORLD_INVALID; + return MEMP_HAL_ERR_WORLD_INVALID; } memprot_ll_rtcfast_get_permissions(permissions, r, w, x); - return MEMP_LL_OK; + return MEMP_HAL_OK; } static inline uint32_t memprot_ll_rtcfast_get_permission_register(void) @@ -601,17 +601,17 @@ static inline uint32_t memprot_ll_dram0_get_intr_source_num(void) /////////////////////////////////// // DRAM0 - SPLIT LINES -static inline memprot_ll_err_t memprot_ll_set_dram0_split_line(const void *line_addr, uint32_t sensitive_reg) +static inline memprot_hal_err_t memprot_ll_set_dram0_split_line(const void *line_addr, uint32_t sensitive_reg) { uint32_t addr = (uint32_t)line_addr; //sanity check: split address required above unified mgmt region & 32bit aligned if (addr < DRAM0_SRAM_LEVEL_1_LOW || addr > DRAM0_SRAM_LEVEL_3_HIGH) { - return MEMP_LL_ERR_SPLIT_ADDR_OUT_OF_RANGE; + return MEMP_HAL_ERR_SPLIT_ADDR_OUT_OF_RANGE; } //split-line must be divisible by 512 (PMS module restriction) if (addr % 0x200 != 0) { - return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED; + return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED; } uint32_t category[3] = {0}; @@ -636,15 +636,15 @@ static inline memprot_ll_err_t memprot_ll_set_dram0_split_line(const void *line_ REG_WRITE(sensitive_reg, reg_cfg); - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_set_dram0_split_line_D_0(const void *line_addr) +static inline memprot_hal_err_t memprot_ll_set_dram0_split_line_D_0(const void *line_addr) { return memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG); } -static inline memprot_ll_err_t memprot_ll_set_dram0_split_line_D_1(const void *line_addr) +static inline memprot_hal_err_t memprot_ll_set_dram0_split_line_D_1(const void *line_addr) { return memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG); } diff --git a/components/hal/esp32s2/include/hal/memprot_ll.h b/components/hal/esp32s2/include/hal/memprot_ll.h index ac4becdaca..da2ad85415 100644 --- a/components/hal/esp32s2/include/hal/memprot_ll.h +++ b/components/hal/esp32s2/include/hal/memprot_ll.h @@ -270,16 +270,16 @@ static inline uint32_t memprot_ll_iram0_sram_get_perm_split_reg(void) return DPORT_READ_PERI_REG(DPORT_PMS_PRO_IRAM0_2_REG); } -static inline memprot_ll_err_t memprot_ll_iram0_sram_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx) +static inline memprot_hal_err_t memprot_ll_iram0_sram_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx) { uint32_t addr = (uint32_t)split_addr; //sanity check: split address required above unified mgmt region & 32bit aligned if (addr > IRAM0_SRAM_SPL_BLOCK_HIGH) { - return MEMP_LL_ERR_SPLIT_ADDR_INVALID; + return MEMP_HAL_ERR_SPLIT_ADDR_INVALID; } if (addr % 0x4 != 0) { - return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED; + return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED; } //find possible split.address in low region blocks @@ -303,7 +303,7 @@ static inline memprot_ll_err_t memprot_ll_iram0_sram_set_prot(uint32_t *split_ad for (int x = 0; x < IRAM0_SRAM_TOTAL_UNI_BLOCKS; x++) { if (!memprot_ll_iram0_sram_get_uni_block_sgnf_bits(x, &write_bit, &read_bit, &exec_bit)) { - return MEMP_LL_ERR_UNI_BLOCK_INVALID; + return MEMP_HAL_ERR_UNI_BLOCK_INVALID; } if (x <= uni_blocks_low) { if (lw) { @@ -360,7 +360,7 @@ static inline memprot_ll_err_t memprot_ll_iram0_sram_set_prot(uint32_t *split_ad DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_IRAM0_1_REG, uni_block_perm); DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_IRAM0_2_REG, (uint32_t)(reg_split_addr | permission_mask)); - return MEMP_LL_OK; + return MEMP_HAL_OK; } static inline void memprot_ll_iram0_sram_get_split_sgnf_bits(bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx) @@ -417,16 +417,16 @@ static inline uint32_t memprot_ll_iram0_rtcfast_get_perm_split_reg(void) return DPORT_READ_PERI_REG(DPORT_PMS_PRO_IRAM0_3_REG); } -static inline memprot_ll_err_t memprot_ll_iram0_rtcfast_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx) +static inline memprot_hal_err_t memprot_ll_iram0_rtcfast_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx) { uint32_t addr = (uint32_t)split_addr; //32bit aligned if (addr < IRAM0_RTCFAST_ADDRESS_LOW || addr > IRAM0_RTCFAST_ADDRESS_HIGH) { - return MEMP_LL_ERR_SPLIT_ADDR_INVALID; + return MEMP_HAL_ERR_SPLIT_ADDR_INVALID; } if (addr % 0x4 != 0) { - return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED; + return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED; } //conf reg [10:0] @@ -456,7 +456,7 @@ static inline memprot_ll_err_t memprot_ll_iram0_rtcfast_set_prot(uint32_t *split //write IRAM0 RTCFAST cfg register DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_IRAM0_3_REG, reg_split_addr | permission_mask); - return MEMP_LL_OK; + return MEMP_HAL_OK; } static inline void memprot_ll_iram0_rtcfast_get_split_sgnf_bits(bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx) @@ -612,12 +612,12 @@ static inline bool memprot_ll_dram0_sram_get_uni_block_sgnf_bits(uint32_t block, return true; } -static inline memprot_ll_err_t memprot_ll_dram0_sram_set_uni_block_perm(uint32_t block, bool write_perm, bool read_perm) +static inline memprot_hal_err_t memprot_ll_dram0_sram_set_uni_block_perm(uint32_t block, bool write_perm, bool read_perm) { //get block-specific WR flags offset within the conf.register uint32_t write_bit_offset, read_bit_offset; if (!memprot_ll_dram0_sram_get_uni_block_sgnf_bits(block, &write_bit_offset, &read_bit_offset)) { - return MEMP_LL_ERR_UNI_BLOCK_INVALID; + return MEMP_HAL_ERR_UNI_BLOCK_INVALID; } //set/reset required flags @@ -633,7 +633,7 @@ static inline memprot_ll_err_t memprot_ll_dram0_sram_set_uni_block_perm(uint32_t DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_1_REG, read_bit_offset); } - return MEMP_LL_OK; + return MEMP_HAL_OK; } static inline bool memprot_ll_dram0_sram_get_uni_block_read_bit(uint32_t block, uint32_t *read_bit) @@ -686,16 +686,16 @@ static inline uint32_t memprot_ll_dram0_sram_get_perm_reg(void) return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DRAM0_1_REG); } -static inline memprot_ll_err_t memprot_ll_dram0_sram_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr) +static inline memprot_hal_err_t memprot_ll_dram0_sram_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr) { uint32_t addr = (uint32_t)split_addr; //low boundary check provided by LD script. see comment in memprot_ll_iram0_sram_set_prot() if (addr > DRAM0_SRAM_SPL_BLOCK_HIGH) { - return MEMP_LL_ERR_SPLIT_ADDR_INVALID; + return MEMP_HAL_ERR_SPLIT_ADDR_INVALID; } if (addr % 0x4 != 0) { - return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED; + return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED; } //set low region @@ -717,7 +717,7 @@ static inline memprot_ll_err_t memprot_ll_dram0_sram_set_prot(uint32_t *split_ad uint32_t write_bit, read_bit, uni_block_perm = 0; for (int x = 0; x < DRAM0_SRAM_TOTAL_UNI_BLOCKS; x++) { if (!memprot_ll_dram0_sram_get_uni_block_sgnf_bits(x, &write_bit, &read_bit)) { - return MEMP_LL_ERR_UNI_BLOCK_INVALID; + return MEMP_HAL_ERR_UNI_BLOCK_INVALID; } if (x <= uni_blocks_low) { if (lw) { @@ -757,7 +757,7 @@ static inline memprot_ll_err_t memprot_ll_dram0_sram_set_prot(uint32_t *split_ad //write DRAM0 SRAM cfg register DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_DRAM0_1_REG, reg_split_addr | permission_mask | uni_block_perm); - return MEMP_LL_OK; + return MEMP_HAL_OK; } static inline void memprot_ll_dram0_sram_get_split_sgnf_bits(bool *lw, bool *lr, bool *hw, bool *hr) @@ -801,16 +801,16 @@ static inline bool memprot_ll_dram0_rtcfast_is_intr_mine(void) return false; } -static inline memprot_ll_err_t memprot_ll_dram0_rtcfast_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr) +static inline memprot_hal_err_t memprot_ll_dram0_rtcfast_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr) { uint32_t addr = (uint32_t)split_addr; //addr: 32bit aligned, inside corresponding range if (addr < DRAM0_RTCFAST_ADDRESS_LOW || addr > DRAM0_RTCFAST_ADDRESS_HIGH) { - return MEMP_LL_ERR_SPLIT_ADDR_INVALID; + return MEMP_HAL_ERR_SPLIT_ADDR_INVALID; } if (addr % 0x4 != 0) { - return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED; + return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED; } //conf reg [10:0] @@ -834,7 +834,7 @@ static inline memprot_ll_err_t memprot_ll_dram0_rtcfast_set_prot(uint32_t *split //write DRAM0 RTC FAST cfg register DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_DRAM0_2_REG, reg_split_addr | permission_mask); - return MEMP_LL_OK; + return MEMP_HAL_OK; } static inline void memprot_ll_dram0_rtcfast_get_split_sgnf_bits(bool *lw, bool *lr, bool *hw, bool *hr) diff --git a/components/hal/esp32s2/include/hal/memprot_peri_ll.h b/components/hal/esp32s2/include/hal/memprot_peri_ll.h index 4611f7a35d..f38bdee1f1 100644 --- a/components/hal/esp32s2/include/hal/memprot_peri_ll.h +++ b/components/hal/esp32s2/include/hal/memprot_peri_ll.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -124,16 +116,16 @@ static inline bool memprot_ll_peri1_rtcslow_is_intr_mine(void) return false; } -static inline memprot_ll_err_t memprot_ll_peri1_rtcslow_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr) +static inline memprot_hal_err_t memprot_ll_peri1_rtcslow_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr) { uint32_t addr = (uint32_t)split_addr; //check corresponding range fit & aligment to 32bit boundaries if (addr < PERI1_RTCSLOW_ADDRESS_LOW || addr > PERI1_RTCSLOW_ADDRESS_HIGH) { - return MEMP_LL_ERR_SPLIT_ADDR_INVALID; + return MEMP_HAL_ERR_SPLIT_ADDR_INVALID; } if (addr % 0x4 != 0) { - return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED; + return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED; } uint32_t reg_split_addr = PERI1_RTCSLOW_ADDR_TO_CONF_REG(addr); @@ -156,7 +148,7 @@ static inline memprot_ll_err_t memprot_ll_peri1_rtcslow_set_prot(uint32_t *split //write PERIBUS1 RTC SLOW cfg register DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_DPORT_1_REG, reg_split_addr | permission_mask); - return MEMP_LL_OK; + return MEMP_HAL_OK; } static inline void memprot_ll_peri1_rtcslow_get_split_sgnf_bits(bool *lw, bool *lr, bool *hw, bool *hr) @@ -282,16 +274,16 @@ static inline bool memprot_ll_peri2_rtcslow_0_is_intr_mine(void) return false; } -static inline memprot_ll_err_t memprot_ll_peri2_rtcslow_0_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx) +static inline memprot_hal_err_t memprot_ll_peri2_rtcslow_0_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx) { uint32_t addr = (uint32_t)split_addr; //check corresponding range fit & aligment to 32bit boundaries if (addr < PERI2_RTCSLOW_0_ADDRESS_LOW || addr > PERI2_RTCSLOW_0_ADDRESS_HIGH) { - return MEMP_LL_ERR_SPLIT_ADDR_INVALID; + return MEMP_HAL_ERR_SPLIT_ADDR_INVALID; } if (addr % 0x4 != 0) { - return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED; + return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED; } uint32_t reg_split_addr = PERI2_RTCSLOW_0_ADDR_TO_CONF_REG(addr); @@ -320,7 +312,7 @@ static inline memprot_ll_err_t memprot_ll_peri2_rtcslow_0_set_prot(uint32_t *spl //write PERIBUS1 RTC SLOW cfg register DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_AHB_1_REG, reg_split_addr | permission_mask); - return MEMP_LL_OK; + return MEMP_HAL_OK; } static inline void memprot_ll_peri2_rtcslow_0_get_split_sgnf_bits(bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx) @@ -370,16 +362,16 @@ static inline bool memprot_ll_peri2_rtcslow_1_is_intr_mine(void) return false; } -static inline memprot_ll_err_t memprot_ll_peri2_rtcslow_1_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx) +static inline memprot_hal_err_t memprot_ll_peri2_rtcslow_1_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx) { uint32_t addr = (uint32_t)split_addr; //check corresponding range fit & aligment to 32bit boundaries if (addr < PERI2_RTCSLOW_1_ADDRESS_LOW || addr > PERI2_RTCSLOW_1_ADDRESS_HIGH) { - return MEMP_LL_ERR_SPLIT_ADDR_INVALID; + return MEMP_HAL_ERR_SPLIT_ADDR_INVALID; } if (addr % 0x4 != 0) { - return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED; + return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED; } uint32_t reg_split_addr = PERI2_RTCSLOW_1_ADDR_TO_CONF_REG(addr); @@ -408,7 +400,7 @@ static inline memprot_ll_err_t memprot_ll_peri2_rtcslow_1_set_prot(uint32_t *spl //write PERIBUS1 RTC SLOW cfg register DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_AHB_2_REG, reg_split_addr | permission_mask); - return MEMP_LL_OK; + return MEMP_HAL_OK; } static inline void memprot_ll_peri2_rtcslow_1_get_split_sgnf_bits(bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx) diff --git a/components/hal/esp32s3/include/hal/memprot_ll.h b/components/hal/esp32s3/include/hal/memprot_ll.h index ad8297864a..748591b5d7 100644 --- a/components/hal/esp32s3/include/hal/memprot_ll.h +++ b/components/hal/esp32s3/include/hal/memprot_ll.h @@ -9,6 +9,7 @@ #include "soc/ext_mem_defs.h" #include "soc/memprot_defs.h" #include "hal/memprot_types.h" +#include "soc/sensitive_reg.h" /* Uncomment to enable MPS debug assertions on false register writes. * It irregularly happens the PMS registers cannot be written which causes unpredictable malfunction of the Memprot feature @@ -61,19 +62,19 @@ static inline void *memprot_ll_get_split_addr_from_reg(const uint32_t regval, co uint32_t level_off = 0; do { - if (reg_val.cat0 == MEMP_LL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; + if (reg_val.cat0 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; level_off += I_D_SRAM_SEGMENT_SIZE/2; - if (reg_val.cat1 == MEMP_LL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; + if (reg_val.cat1 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; level_off += I_D_SRAM_SEGMENT_SIZE; - if (reg_val.cat2 == MEMP_LL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; + if (reg_val.cat2 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; level_off += I_D_SRAM_SEGMENT_SIZE; - if (reg_val.cat3 == MEMP_LL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; + if (reg_val.cat3 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; level_off += I_D_SRAM_SEGMENT_SIZE; - if (reg_val.cat4 == MEMP_LL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; + if (reg_val.cat4 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; level_off += I_D_SRAM_SEGMENT_SIZE; - if (reg_val.cat5 == MEMP_LL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; + if (reg_val.cat5 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; level_off += I_D_SRAM_SEGMENT_SIZE; - if (reg_val.cat6 == MEMP_LL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; + if (reg_val.cat6 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break; return NULL; //wrong configuration } while(0); @@ -83,7 +84,7 @@ static inline void *memprot_ll_get_split_addr_from_reg(const uint32_t regval, co /* ****************************************************************************************************** * *** IRAM0 *** * ******************************************************************************************************/ -static inline memprot_ll_err_t memprot_ll_iram0_get_intr_source_num(const int core, uint32_t* src_num) +static inline memprot_hal_err_t memprot_ll_iram0_get_intr_source_num(const int core, uint32_t* src_num) { switch (core) { case PRO_CPU_NUM: @@ -93,10 +94,10 @@ static inline memprot_ll_err_t memprot_ll_iram0_get_intr_source_num(const int co *src_num = ETS_CORE1_IRAM0_PMS_INTR_SOURCE; break; default: - return MEMP_LL_FAIL; + return MEMP_HAL_FAIL; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } /////////////////////////////////// @@ -119,13 +120,13 @@ static inline uint32_t memprot_ll_get_iram0_split_line_main_I_1_regval(void) static inline void memprot_ll_prepare_iram0_split_line_regval(const uint32_t addr, uint32_t* regval) { //set category bits for given split line - uint32_t cat[7] = {[0 ... 6]=MEMP_LL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA}; + uint32_t cat[7] = {[0 ... 6]=MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA}; for (size_t x=0; x<7; x++) { if (addr <= sram_rg3_level_hlimits[x]) { - cat[x] = MEMP_LL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA; + cat[x] = MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA; break; } else { - cat[x] = MEMP_LL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_BELOW_SA; + cat[x] = MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_BELOW_SA; } } @@ -149,13 +150,13 @@ static inline void memprot_ll_prepare_iram0_split_line_regval(const uint32_t add } // all the split lines registers have the same layout -static inline memprot_ll_err_t memprot_ll_set_iram0_split_line(const void *line_addr, const uint32_t sensitive_reg) +static inline memprot_hal_err_t memprot_ll_set_iram0_split_line(const void *line_addr, const uint32_t sensitive_reg) { uint32_t addr = (uint32_t)line_addr; //sanity check - MEMP_LL_CHECK_IRAM_ADDR_IN_RANGE(addr) - MEMP_LL_CHECK_SPLIT_ADDR_ALIGNED(addr) + MEMP_HAL_CHECK_IRAM_ADDR_IN_RANGE(addr) + MEMP_HAL_CHECK_SPLIT_ADDR_ALIGNED(addr) uint32_t regval; memprot_ll_prepare_iram0_split_line_regval(addr, ®val); @@ -165,22 +166,22 @@ static inline memprot_ll_err_t memprot_ll_set_iram0_split_line(const void *line_ HAL_ASSERT((REG_READ(sensitive_reg) == regval) && "Value not stored to required register"); #endif - return MEMP_LL_OK; + return MEMP_HAL_OK; } // set the main I/D splitting address - can be defined within either IRAM0 or DRAM0 range (IRAM0 preferred as the Memprot API stereotype) -static inline memprot_ll_err_t memprot_ll_set_iram0_split_line_main_I_D(const void *line_addr) +static inline memprot_hal_err_t memprot_ll_set_iram0_split_line_main_I_D(const void *line_addr) { return memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG); } // set auxiliary split lines (IRAM0 range address required) -static inline memprot_ll_err_t memprot_ll_set_iram0_split_line_I_0(const void *line_addr) +static inline memprot_hal_err_t memprot_ll_set_iram0_split_line_I_0(const void *line_addr) { return memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG); } -static inline memprot_ll_err_t memprot_ll_set_iram0_split_line_I_1(const void *line_addr) +static inline memprot_hal_err_t memprot_ll_set_iram0_split_line_I_1(const void *line_addr) { return memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG); } @@ -323,7 +324,7 @@ static inline void memprot_ll_iram0_get_pms_area_3(bool *r, bool *w, bool *x) // IRAM0 - MONITOR // lock -static inline memprot_ll_err_t memprot_ll_iram0_set_monitor_lock(const int core) +static inline memprot_hal_err_t memprot_ll_iram0_set_monitor_lock(const int core) { switch (core) { case PRO_CPU_NUM: @@ -339,13 +340,13 @@ static inline memprot_ll_err_t memprot_ll_iram0_set_monitor_lock(const int core) #endif break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_lock(const int core, bool* locked) +static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_lock(const int core, bool* locked) { switch (core) { case PRO_CPU_NUM: @@ -355,14 +356,14 @@ static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_lock(const int core, *locked = REG_READ(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG) == 1; break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } // interrupt enable/clear -static inline memprot_ll_err_t memprot_ll_iram0_set_monitor_en(const int core, const bool enable) +static inline memprot_hal_err_t memprot_ll_iram0_set_monitor_en(const int core, const bool enable) { switch (core) { case PRO_CPU_NUM: @@ -392,13 +393,13 @@ static inline memprot_ll_err_t memprot_ll_iram0_set_monitor_en(const int core, c } break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_en(const int core, bool* enabled) +static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_en(const int core, bool* enabled) { switch (core) { case PRO_CPU_NUM: @@ -408,13 +409,13 @@ static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_en(const int core, b *enabled = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN) == 1; break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_iram0_set_monitor_intrclr(const int core) +static inline memprot_hal_err_t memprot_ll_iram0_set_monitor_intrclr(const int core) { switch (core) { case PRO_CPU_NUM: @@ -430,13 +431,13 @@ static inline memprot_ll_err_t memprot_ll_iram0_set_monitor_intrclr(const int co #endif break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_iram0_reset_monitor_intrclr(const int core) +static inline memprot_hal_err_t memprot_ll_iram0_reset_monitor_intrclr(const int core) { switch (core) { case PRO_CPU_NUM: @@ -452,13 +453,13 @@ static inline memprot_ll_err_t memprot_ll_iram0_reset_monitor_intrclr(const int #endif break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_intrclr(const int core, bool* cleared) +static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_intrclr(const int core, bool* cleared) { switch (core) { case PRO_CPU_NUM: @@ -468,13 +469,13 @@ static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_intrclr(const int co *cleared = REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR) > 0; break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_enable_register(const int core, uint32_t* regval) +static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_enable_register(const int core, uint32_t* regval) { switch (core) { case PRO_CPU_NUM: @@ -484,14 +485,14 @@ static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_enable_register(cons *regval = REG_READ(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } // permission violation status -static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_status_intr(const int core, uint32_t* regval) +static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_intr(const int core, uint32_t* regval) { switch (core) { case PRO_CPU_NUM: @@ -501,13 +502,13 @@ static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_status_intr(const in *regval = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_status_fault_wr(const int core, uint32_t* regval) +static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_fault_wr(const int core, uint32_t* regval) { switch (core) { case PRO_CPU_NUM: @@ -517,13 +518,13 @@ static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_status_fault_wr(cons *regval = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_status_fault_loadstore(const int core, uint32_t* regval) +static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_fault_loadstore(const int core, uint32_t* regval) { switch (core) { case PRO_CPU_NUM: @@ -533,13 +534,13 @@ static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_status_fault_loadsto *regval = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_status_fault_world(const int core, uint32_t* regval) +static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_fault_world(const int core, uint32_t* regval) { switch (core) { case PRO_CPU_NUM: @@ -549,13 +550,13 @@ static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_status_fault_world(c *regval = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_status_fault_addr(const int core, void** addr) +static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_fault_addr(const int core, void** addr) { uint32_t reg_off; @@ -567,15 +568,15 @@ static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_status_fault_addr(co reg_off = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } *addr = (void*)(reg_off > 0 ? (reg_off << I_D_FAULT_ADDR_SHIFT) + IRAM0_ADDRESS_LOW : 0); - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_status_register(const int core, uint32_t* regval) +static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_register(const int core, uint32_t* regval) { switch (core) { case PRO_CPU_NUM: @@ -585,10 +586,10 @@ static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_status_register(cons *regval = REG_READ(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } @@ -596,7 +597,7 @@ static inline memprot_ll_err_t memprot_ll_iram0_get_monitor_status_register(cons * *** RTC_FAST *** */ -static inline memprot_ll_err_t memprot_ll_rtcfast_get_intr_source_num(const int core, uint32_t* src_num) +static inline memprot_hal_err_t memprot_ll_rtcfast_get_intr_source_num(const int core, uint32_t* src_num) { switch (core) { case PRO_CPU_NUM: @@ -606,15 +607,15 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_get_intr_source_num(const int *src_num = ETS_CORE1_PIF_PMS_INTR_SOURCE; break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } //shared PIF PMS lock //!!!: use after ALL the constraints have been set -static inline memprot_ll_err_t memprot_ll_set_pif_constraint_lock(const int core) +static inline memprot_hal_err_t memprot_ll_set_pif_constraint_lock(const int core) { switch (core) { case PRO_CPU_NUM: @@ -630,13 +631,13 @@ static inline memprot_ll_err_t memprot_ll_set_pif_constraint_lock(const int core #endif break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_get_pif_constraint_lock(const int core, bool* locked) +static inline memprot_hal_err_t memprot_ll_get_pif_constraint_lock(const int core, bool* locked) { switch (core) { case PRO_CPU_NUM: @@ -646,13 +647,13 @@ static inline memprot_ll_err_t memprot_ll_get_pif_constraint_lock(const int core *locked = REG_READ(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG) == 1; break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_rtcfast_get_splitaddr_register(const int core, uint32_t* regval) +static inline memprot_hal_err_t memprot_ll_rtcfast_get_splitaddr_register(const int core, uint32_t* regval) { switch (core) { case PRO_CPU_NUM: @@ -662,46 +663,46 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_get_splitaddr_register(const i *regval = REG_READ(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_REG); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } /* ******************************** * IRAM0 RTCFAST - SPLIT LINES */ -static inline memprot_ll_err_t memprot_ll_set_rtcfast_split_line(const int core, const void *line_addr, const memprot_ll_world_t world) +static inline memprot_hal_err_t memprot_ll_set_rtcfast_split_line(const int core, const void *line_addr, const memprot_hal_world_t world) { uint32_t addr = (uint32_t)line_addr; if (addr < SOC_RTC_IRAM_LOW || addr >= SOC_RTC_IRAM_HIGH) { - return MEMP_LL_ERR_SPLIT_ADDR_OUT_OF_RANGE; + return MEMP_HAL_ERR_SPLIT_ADDR_OUT_OF_RANGE; } if (addr % 0x4 != 0) { - return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED; + return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED; } if (core != PRO_CPU_NUM && core != APP_CPU_NUM) { - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } uint32_t mask; uint32_t val; switch (world) { - case MEMP_LL_WORLD_0: + case MEMP_HAL_WORLD_0: mask = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M; val = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V; break; - case MEMP_LL_WORLD_1: + case MEMP_HAL_WORLD_1: mask = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M; val = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V; break; default: - return MEMP_LL_ERR_WORLD_INVALID; + return MEMP_HAL_ERR_WORLD_INVALID; } uint32_t reg = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_REG; @@ -715,36 +716,36 @@ static inline memprot_ll_err_t memprot_ll_set_rtcfast_split_line(const int core, uint32_t expected = REG_READ(reg) & mask; HAL_ASSERT((expected == ((addr >> 2) & val)) && "Value not stored to required register"); #endif - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_get_rtcfast_split_line(const int core, const memprot_ll_world_t world, void **line_addr) +static inline memprot_hal_err_t memprot_ll_get_rtcfast_split_line(const int core, const memprot_hal_world_t world, void **line_addr) { if (core != PRO_CPU_NUM && core != APP_CPU_NUM) { - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } uint32_t mask; uint32_t shift; switch (world) { - case MEMP_LL_WORLD_0: + case MEMP_HAL_WORLD_0: mask = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M; shift = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S; break; - case MEMP_LL_WORLD_1: + case MEMP_HAL_WORLD_1: mask = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M; shift = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S; break; default: - return MEMP_LL_ERR_WORLD_INVALID; + return MEMP_HAL_ERR_WORLD_INVALID; } uint32_t reg_addr = REG_READ(core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_REG); *line_addr = (void *)((((reg_addr & mask) >> shift) << 2) + SOC_RTC_IRAM_LOW); - return MEMP_LL_OK; + return MEMP_HAL_OK; } /////////////////////////////////// @@ -767,46 +768,46 @@ static inline uint32_t memprot_ll_rtcfast_set_permissions(const bool r, const bo return permissions; } -static inline memprot_ll_err_t memprot_ll_rtcfast_set_pms_area(const int core, const bool r, const bool w, const bool x, const memprot_ll_world_t world, const memprot_ll_area_t area) +static inline memprot_hal_err_t memprot_ll_rtcfast_set_pms_area(const int core, const bool r, const bool w, const bool x, const memprot_hal_world_t world, const memprot_hal_area_t area) { if (core != PRO_CPU_NUM && core != APP_CPU_NUM) { - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } uint32_t bits; uint32_t mask; switch (world) { - case MEMP_LL_WORLD_0: { + case MEMP_HAL_WORLD_0: { switch (area) { - case MEMP_LL_AREA_LOW: + case MEMP_HAL_AREA_LOW: bits = memprot_ll_rtcfast_set_permissions(r, w, x) << (core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S); mask = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M; break; - case MEMP_LL_AREA_HIGH: + case MEMP_HAL_AREA_HIGH: bits = memprot_ll_rtcfast_set_permissions(r, w, x) << (core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S); mask = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M; break; default: - return MEMP_LL_ERR_AREA_INVALID; + return MEMP_HAL_ERR_AREA_INVALID; } } break; - case MEMP_LL_WORLD_1: { + case MEMP_HAL_WORLD_1: { switch (area) { - case MEMP_LL_AREA_LOW: + case MEMP_HAL_AREA_LOW: bits = memprot_ll_rtcfast_set_permissions(r, w, x) << (core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S); mask = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M; break; - case MEMP_LL_AREA_HIGH: + case MEMP_HAL_AREA_HIGH: bits = memprot_ll_rtcfast_set_permissions(r, w, x) << (core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S); mask = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M; break; default: - return MEMP_LL_ERR_AREA_INVALID; + return MEMP_HAL_ERR_AREA_INVALID; } } break; default: - return MEMP_LL_ERR_WORLD_INVALID; + return MEMP_HAL_ERR_WORLD_INVALID; } uint32_t reg = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG; @@ -821,7 +822,7 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_set_pms_area(const int core, c HAL_ASSERT((expected == bits) && "Value not stored to required register"); #endif - return MEMP_LL_OK; + return MEMP_HAL_OK; } static inline void memprot_ll_rtcfast_get_permissions(const uint32_t perms, bool *r, bool *w, bool *x) @@ -831,25 +832,25 @@ static inline void memprot_ll_rtcfast_get_permissions(const uint32_t perms, bool *x = perms & SENSITIVE_CORE_X_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F; } -static inline memprot_ll_err_t memprot_ll_rtcfast_get_pms_area(const int core, bool *r, bool *w, bool *x, const memprot_ll_world_t world, const memprot_ll_area_t area) +static inline memprot_hal_err_t memprot_ll_rtcfast_get_pms_area(const int core, bool *r, bool *w, bool *x, const memprot_hal_world_t world, const memprot_hal_area_t area) { if (core != PRO_CPU_NUM && core != APP_CPU_NUM) { - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } uint32_t permissions = 0; switch (world) { - case MEMP_LL_WORLD_0: { + case MEMP_HAL_WORLD_0: { switch (area) { - case MEMP_LL_AREA_LOW: + case MEMP_HAL_AREA_LOW: if (core == PRO_CPU_NUM) { permissions = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L); } else { permissions = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L); } break; - case MEMP_LL_AREA_HIGH: + case MEMP_HAL_AREA_HIGH: if (core == PRO_CPU_NUM) { permissions = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H); } else { @@ -857,19 +858,19 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_get_pms_area(const int core, b } break; default: - return MEMP_LL_ERR_AREA_INVALID; + return MEMP_HAL_ERR_AREA_INVALID; } } break; - case MEMP_LL_WORLD_1: { + case MEMP_HAL_WORLD_1: { switch (area) { - case MEMP_LL_AREA_LOW: + case MEMP_HAL_AREA_LOW: if (core == PRO_CPU_NUM) { permissions = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L); } else { permissions = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L); } break; - case MEMP_LL_AREA_HIGH: + case MEMP_HAL_AREA_HIGH: if (core == PRO_CPU_NUM) { permissions = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H); } else { @@ -877,19 +878,19 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_get_pms_area(const int core, b } break; default: - return MEMP_LL_ERR_AREA_INVALID; + return MEMP_HAL_ERR_AREA_INVALID; } } break; default: - return MEMP_LL_ERR_WORLD_INVALID; + return MEMP_HAL_ERR_WORLD_INVALID; } memprot_ll_rtcfast_get_permissions(permissions, r, w, x); - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_rtcfast_get_permission_register(const int core, uint32_t* regval) +static inline memprot_hal_err_t memprot_ll_rtcfast_get_permission_register(const int core, uint32_t* regval) { switch (core) { case PRO_CPU_NUM: @@ -899,17 +900,17 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_get_permission_register(const *regval = REG_READ(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } /////////////////////////////////// // RTC_FAST - MONITOR // lock -static inline memprot_ll_err_t memprot_ll_rtcfast_set_monitor_lock(const int core) +static inline memprot_hal_err_t memprot_ll_rtcfast_set_monitor_lock(const int core) { switch (core) { case PRO_CPU_NUM: @@ -925,13 +926,13 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_set_monitor_lock(const int cor #endif break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_rtcfast_get_monitor_lock(const int core, bool* locked) +static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_lock(const int core, bool* locked) { switch (core) { case PRO_CPU_NUM: @@ -941,14 +942,14 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_get_monitor_lock(const int cor *locked = REG_READ(SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG) == 1; break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } // interrupt enable/clear -static inline memprot_ll_err_t memprot_ll_rtcfast_set_monitor_en(const int core, const bool enable) +static inline memprot_hal_err_t memprot_ll_rtcfast_set_monitor_en(const int core, const bool enable) { switch (core) { case PRO_CPU_NUM: @@ -978,13 +979,13 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_set_monitor_en(const int core, } break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_rtcfast_get_monitor_en(const int core, bool* enabled) +static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_en(const int core, bool* enabled) { switch (core) { case PRO_CPU_NUM: @@ -994,13 +995,13 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_get_monitor_en(const int core, *enabled = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN) > 0; break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_rtcfast_get_monitor_intrclr(const int core, bool* cleared) +static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_intrclr(const int core, bool* cleared) { switch (core) { case PRO_CPU_NUM: @@ -1010,13 +1011,13 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_get_monitor_intrclr(const int *cleared = REG_GET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR) > 0; break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_rtcfast_set_monitor_intrclr(const int core) +static inline memprot_hal_err_t memprot_ll_rtcfast_set_monitor_intrclr(const int core) { switch (core) { case PRO_CPU_NUM: @@ -1032,13 +1033,13 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_set_monitor_intrclr(const int #endif break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_rtcfast_reset_monitor_intrclr(const int core) +static inline memprot_hal_err_t memprot_ll_rtcfast_reset_monitor_intrclr(const int core) { switch (core) { case PRO_CPU_NUM: @@ -1054,13 +1055,13 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_reset_monitor_intrclr(const in #endif break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_rtcfast_get_monitor_register(const int core, uint32_t* regval) +static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_register(const int core, uint32_t* regval) { switch (core) { case PRO_CPU_NUM: @@ -1070,14 +1071,14 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_get_monitor_register(const int *regval = REG_READ(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } // permission violation status -static inline memprot_ll_err_t memprot_ll_rtcfast_get_monitor_status_intr(const int core, uint32_t* regval) +static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_intr(const int core, uint32_t* regval) { switch (core) { case PRO_CPU_NUM: @@ -1087,13 +1088,13 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_get_monitor_status_intr(const *regval = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_rtcfast_get_monitor_status_fault_addr(const int core, void** addr) +static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_fault_addr(const int core, void** addr) { switch (core) { case PRO_CPU_NUM: @@ -1103,13 +1104,13 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_get_monitor_status_fault_addr( *addr = (void*)REG_READ(SENSITIVE_CORE_1_PIF_PMS_MONITOR_3_REG); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_rtcfast_get_monitor_status_fault_world(const int core, uint32_t* regval) +static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_fault_world(const int core, uint32_t* regval) { switch (core) { case PRO_CPU_NUM: @@ -1119,13 +1120,13 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_get_monitor_status_fault_world *regval = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_rtcfast_get_monitor_status_fault_loadstore(const int core, uint32_t* regval) +static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_fault_loadstore(const int core, uint32_t* regval) { switch (core) { case PRO_CPU_NUM: @@ -1135,13 +1136,13 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_get_monitor_status_fault_loads *regval = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_rtcfast_get_monitor_status_fault_wr(const int core, uint32_t* regval) +static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_fault_wr(const int core, uint32_t* regval) { switch (core) { case PRO_CPU_NUM: @@ -1151,10 +1152,10 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_get_monitor_status_fault_wr(co *regval = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } @@ -1162,7 +1163,7 @@ static inline memprot_ll_err_t memprot_ll_rtcfast_get_monitor_status_fault_wr(co * *** DRAM0 *** * ******************************************************************************************************/ -static inline memprot_ll_err_t memprot_ll_dram0_get_intr_source_num(const int core, uint32_t* src_num) +static inline memprot_hal_err_t memprot_ll_dram0_get_intr_source_num(const int core, uint32_t* src_num) { switch (core) { case PRO_CPU_NUM: @@ -1172,10 +1173,10 @@ static inline memprot_ll_err_t memprot_ll_dram0_get_intr_source_num(const int co *src_num = ETS_CORE1_DRAM0_PMS_INTR_SOURCE; break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } /////////////////////////////////// @@ -1193,13 +1194,13 @@ static inline uint32_t memprot_ll_get_dram0_split_line_main_D_1_regval(void) static inline void memprot_ll_prepare_dram0_split_line_regval(const uint32_t addr, uint32_t* regval) { //set category bits for given split line - uint32_t cat[7] = {[0 ... 6]=MEMP_LL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA}; + uint32_t cat[7] = {[0 ... 6]=MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA}; for (size_t x=0; x<7; x++) { if (addr <= MAP_IRAM_TO_DRAM(sram_rg3_level_hlimits[x])) { - cat[x] = MEMP_LL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA; + cat[x] = MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA; break; } else { - cat[x] = MEMP_LL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_BELOW_SA; + cat[x] = MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_BELOW_SA; } } @@ -1223,13 +1224,13 @@ static inline void memprot_ll_prepare_dram0_split_line_regval(const uint32_t add *regval = cfg_reg_val.val; } -static inline memprot_ll_err_t memprot_ll_set_dram0_split_line(const void *line_addr, const uint32_t sensitive_reg) +static inline memprot_hal_err_t memprot_ll_set_dram0_split_line(const void *line_addr, const uint32_t sensitive_reg) { uint32_t addr = (uint32_t)line_addr; //sanity check - MEMP_LL_CHECK_DRAM_ADDR_IN_RANGE(addr) - MEMP_LL_CHECK_SPLIT_ADDR_ALIGNED(addr) + MEMP_HAL_CHECK_DRAM_ADDR_IN_RANGE(addr) + MEMP_HAL_CHECK_SPLIT_ADDR_ALIGNED(addr) uint32_t regval; memprot_ll_prepare_dram0_split_line_regval(addr, ®val); @@ -1239,15 +1240,15 @@ static inline memprot_ll_err_t memprot_ll_set_dram0_split_line(const void *line_ HAL_ASSERT((REG_READ(sensitive_reg) == regval) && "Value not stored to required register"); #endif - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_set_dram0_split_line_D_0(const void *line_addr) +static inline memprot_hal_err_t memprot_ll_set_dram0_split_line_D_0(const void *line_addr) { return memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG); } -static inline memprot_ll_err_t memprot_ll_set_dram0_split_line_D_1(const void *line_addr) +static inline memprot_hal_err_t memprot_ll_set_dram0_split_line_D_1(const void *line_addr) { return memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG); } @@ -1374,7 +1375,7 @@ static inline void memprot_ll_dram0_get_pms_area_3(bool *r, bool *w) // DRAM0 - MONITOR // lock -static inline memprot_ll_err_t memprot_ll_dram0_set_monitor_lock(const int core) +static inline memprot_hal_err_t memprot_ll_dram0_set_monitor_lock(const int core) { switch (core) { case PRO_CPU_NUM: @@ -1390,13 +1391,13 @@ static inline memprot_ll_err_t memprot_ll_dram0_set_monitor_lock(const int core) #endif break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_dram0_get_monitor_lock(const int core, bool* locked) +static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_lock(const int core, bool* locked) { switch (core) { case PRO_CPU_NUM: @@ -1406,14 +1407,14 @@ static inline memprot_ll_err_t memprot_ll_dram0_get_monitor_lock(const int core, *locked = REG_READ(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG) == 1; break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } // interrupt enable/clear -static inline memprot_ll_err_t memprot_ll_dram0_set_monitor_en(const int core, const bool enable) +static inline memprot_hal_err_t memprot_ll_dram0_set_monitor_en(const int core, const bool enable) { switch (core) { case PRO_CPU_NUM: @@ -1443,13 +1444,13 @@ static inline memprot_ll_err_t memprot_ll_dram0_set_monitor_en(const int core, c } break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_dram0_get_monitor_en(const int core, bool* enabled) +static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_en(const int core, bool* enabled) { switch (core) { case PRO_CPU_NUM: @@ -1459,13 +1460,13 @@ static inline memprot_ll_err_t memprot_ll_dram0_get_monitor_en(const int core, b *enabled = REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN) > 0; break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_dram0_set_monitor_intrclr(const int core) +static inline memprot_hal_err_t memprot_ll_dram0_set_monitor_intrclr(const int core) { switch (core) { case PRO_CPU_NUM: @@ -1481,13 +1482,13 @@ static inline memprot_ll_err_t memprot_ll_dram0_set_monitor_intrclr(const int co #endif break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_dram0_reset_monitor_intrclr(const int core) +static inline memprot_hal_err_t memprot_ll_dram0_reset_monitor_intrclr(const int core) { switch (core) { case PRO_CPU_NUM: @@ -1503,13 +1504,13 @@ static inline memprot_ll_err_t memprot_ll_dram0_reset_monitor_intrclr(const int #endif break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_dram0_get_monitor_intrclr(const int core, bool* cleared) +static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_intrclr(const int core, bool* cleared) { switch (core) { case PRO_CPU_NUM: @@ -1519,13 +1520,13 @@ static inline memprot_ll_err_t memprot_ll_dram0_get_monitor_intrclr(const int co *cleared = REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR) > 0; break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_dram0_get_monitor_enable_register(const int core, uint32_t* regval) +static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_enable_register(const int core, uint32_t* regval) { switch (core) { case PRO_CPU_NUM: @@ -1535,14 +1536,14 @@ static inline memprot_ll_err_t memprot_ll_dram0_get_monitor_enable_register(cons *regval = REG_READ(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } // permission violation status -static inline memprot_ll_err_t memprot_ll_dram0_get_monitor_status_intr(const int core, uint32_t* regval) +static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_intr(const int core, uint32_t* regval) { switch (core) { case PRO_CPU_NUM: @@ -1552,13 +1553,13 @@ static inline memprot_ll_err_t memprot_ll_dram0_get_monitor_status_intr(const in *regval = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_dram0_get_monitor_status_fault_world(const int core, uint32_t* regval) +static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_fault_world(const int core, uint32_t* regval) { switch (core) { case PRO_CPU_NUM: @@ -1568,13 +1569,13 @@ static inline memprot_ll_err_t memprot_ll_dram0_get_monitor_status_fault_world(c *regval = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_dram0_get_monitor_status_fault_addr(const int core, void** addr) +static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_fault_addr(const int core, void** addr) { uint32_t reg_off; @@ -1586,15 +1587,15 @@ static inline memprot_ll_err_t memprot_ll_dram0_get_monitor_status_fault_addr(co reg_off = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } *addr = (void*)(reg_off > 0 ? (reg_off << I_D_FAULT_ADDR_SHIFT) + IRAM0_ADDRESS_LOW : 0); - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_dram0_get_monitor_status_fault_wr(const int core, uint32_t* regval) +static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_fault_wr(const int core, uint32_t* regval) { switch (core) { case PRO_CPU_NUM: @@ -1604,13 +1605,13 @@ static inline memprot_ll_err_t memprot_ll_dram0_get_monitor_status_fault_wr(cons *regval = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_3_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } -static inline memprot_ll_err_t memprot_ll_dram0_get_monitor_status_fault_byte_en(const int core, uint32_t* regval) +static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_fault_byte_en(const int core, uint32_t* regval) { switch (core) { case PRO_CPU_NUM: @@ -1620,10 +1621,10 @@ static inline memprot_ll_err_t memprot_ll_dram0_get_monitor_status_fault_byte_en *regval = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN); break; default: - return MEMP_LL_ERR_CORE_INVALID; + return MEMP_HAL_ERR_CORE_INVALID; } - return MEMP_LL_OK; + return MEMP_HAL_OK; } #ifdef __cplusplus diff --git a/components/hal/include/hal/memprot_types.h b/components/hal/include/hal/memprot_types.h index e76c0300e6..21e2c43060 100644 --- a/components/hal/include/hal/memprot_types.h +++ b/components/hal/include/hal/memprot_types.h @@ -18,49 +18,49 @@ extern "C" { * */ typedef enum { - MEMP_LL_OK = 0, - MEMP_LL_ERR_SPLIT_ADDR_OUT_OF_RANGE = 2, - MEMP_LL_ERR_SPLIT_ADDR_INVALID = 2, /* temporary duplicate for S2 builds */ - MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED = 3, - MEMP_LL_ERR_UNI_BLOCK_INVALID = 4, - MEMP_LL_ERR_AREA_INVALID = 5, - MEMP_LL_ERR_WORLD_INVALID = 6, - MEMP_LL_ERR_CORE_INVALID = 7, - MEMP_LL_FAIL = -1, -} memprot_ll_err_t; + MEMP_HAL_OK = 0, + MEMP_HAL_ERR_SPLIT_ADDR_OUT_OF_RANGE = 2, + MEMP_HAL_ERR_SPLIT_ADDR_INVALID = 2, /* temporary duplicate for S2 builds */ + MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED = 3, + MEMP_HAL_ERR_UNI_BLOCK_INVALID = 4, + MEMP_HAL_ERR_AREA_INVALID = 5, + MEMP_HAL_ERR_WORLD_INVALID = 6, + MEMP_HAL_ERR_CORE_INVALID = 7, + MEMP_HAL_FAIL = -1, +} memprot_hal_err_t; /** * @brief Memprot LL PMS World IDs * */ typedef enum { - MEMP_LL_WORLD_NONE = 0x00, - MEMP_LL_WORLD_0 = 0x01, - MEMP_LL_WORLD_1 = 0x10 -} memprot_ll_world_t; + MEMP_HAL_WORLD_NONE = 0x00, + MEMP_HAL_WORLD_0 = 0x01, + MEMP_HAL_WORLD_1 = 0x10 +} memprot_hal_world_t; /** * @brief Memprot LL PMS Area IDs * */ typedef enum { - MEMP_LL_AREA_NONE = 0, - MEMP_LL_AREA_LOW = 1, - MEMP_LL_AREA_HIGH = 2 -} memprot_ll_area_t; + MEMP_HAL_AREA_NONE = 0, + MEMP_HAL_AREA_LOW = 1, + MEMP_HAL_AREA_HIGH = 2 +} memprot_hal_area_t; //auxiliary macros & defines #define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) #define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET) #define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET) -#define MEMP_LL_CHECK_IRAM_ADDR_IN_RANGE(x) if (x < SOC_DIRAM_IRAM_LOW || x >= SOC_DIRAM_IRAM_HIGH) { return MEMP_LL_ERR_SPLIT_ADDR_OUT_OF_RANGE; } -#define MEMP_LL_CHECK_DRAM_ADDR_IN_RANGE(x) if (x < SOC_DIRAM_DRAM_LOW || x >= SOC_DIRAM_DRAM_HIGH) { return MEMP_LL_ERR_SPLIT_ADDR_OUT_OF_RANGE; } -#define MEMP_LL_CHECK_SPLIT_ADDR_ALIGNED(x) if (x % I_D_SPLIT_LINE_ALIGN != 0) { return MEMP_LL_ERR_SPLIT_ADDR_UNALIGNED; } +#define MEMP_HAL_CHECK_IRAM_ADDR_IN_RANGE(x) if (x < SOC_DIRAM_IRAM_LOW || x >= SOC_DIRAM_IRAM_HIGH) { return MEMP_HAL_ERR_SPLIT_ADDR_OUT_OF_RANGE; } +#define MEMP_HAL_CHECK_DRAM_ADDR_IN_RANGE(x) if (x < SOC_DIRAM_DRAM_LOW || x >= SOC_DIRAM_DRAM_HIGH) { return MEMP_HAL_ERR_SPLIT_ADDR_OUT_OF_RANGE; } +#define MEMP_HAL_CHECK_SPLIT_ADDR_ALIGNED(x) if (x % I_D_SPLIT_LINE_ALIGN != 0) { return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED; } -#define MEMP_LL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_BELOW_SA 0x0 //0b00 -#define MEMP_LL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA 0x2 //0b10 -#define MEMP_LL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA 0x3 //0b11 +#define MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_BELOW_SA 0x0 //0b00 +#define MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA 0x2 //0b10 +#define MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA 0x3 //0b11 #ifdef __cplusplus } diff --git a/components/soc/esp32s3/include/soc/memprot_defs.h b/components/soc/esp32s3/include/soc/memprot_defs.h index b9c705ad06..1aa97de167 100644 --- a/components/soc/esp32s3/include/soc/memprot_defs.h +++ b/components/soc/esp32s3/include/soc/memprot_defs.h @@ -6,22 +6,31 @@ #pragma once -#include "soc/sensitive_reg.h" +#include #ifdef __cplusplus extern "C" { #endif +/* + * PMS register configuration structure for I/D splitting address. + * Category bits define the splitting address being below, inside or above specific memory level range: + * - for details of ESP32S3 memory layout, see 725_mem_map.* documents + * - for category bits settings, see MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS* + * (components/hal/include/hal/memprot_types.h) + * - for details on assembling full splitting address + * see function memprot_ll_get_split_addr_from_reg() (components/hal/esp32s3/include/hal/memprot_ll.h) + */ typedef union { struct { - uint32_t cat0 : 2; - uint32_t cat1 : 2; - uint32_t cat2 : 2; - uint32_t cat3 : 2; - uint32_t cat4 : 2; - uint32_t cat5 : 2; - uint32_t cat6 : 2; - uint32_t splitaddr : 8; + uint32_t cat0 : 2; /**< category bits - level 2 */ + uint32_t cat1 : 2; /**< category bits - level 3 */ + uint32_t cat2 : 2; /**< category bits - level 4 */ + uint32_t cat3 : 2; /**< category bits - level 5 */ + uint32_t cat4 : 2; /**< category bits - level 6 */ + uint32_t cat5 : 2; /**< category bits - level 7 */ + uint32_t cat6 : 2; /**< category bits - level 8 */ + uint32_t splitaddr : 8; /**< splitting address significant bits */ uint32_t reserved : 10; }; uint32_t val; diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index d3faf1a6d7..10fa64fa8d 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -777,7 +777,6 @@ components/hal/esp32s2/include/hal/aes_ll.h components/hal/esp32s2/include/hal/crypto_dma_ll.h components/hal/esp32s2/include/hal/dac_hal.h components/hal/esp32s2/include/hal/dedic_gpio_ll.h -components/hal/esp32s2/include/hal/memprot_peri_ll.h components/hal/esp32s2/include/hal/mpu_ll.h components/hal/esp32s2/include/hal/rtc_io_ll.h components/hal/esp32s2/include/hal/sha_ll.h diff --git a/tools/test_apps/system/memprot/main/esp32s3/test_memprot_main.c b/tools/test_apps/system/memprot/main/esp32s3/test_memprot_main.c index 09068fe58b..6e24230435 100644 --- a/tools/test_apps/system/memprot/main/esp32s3/test_memprot_main.c +++ b/tools/test_apps/system/memprot/main/esp32s3/test_memprot_main.c @@ -9,6 +9,7 @@ #include "esp_attr.h" #include "hal/memprot_types.h" #include "soc/memprot_defs.h" +#include "soc/sensitive_reg.h" #include "esp_private/esp_memprot_internal.h" #include "esp_memprot.h" #include "esp_rom_sys.h" @@ -94,7 +95,9 @@ slli a2, a2, 1 ret.n */ -static uint8_t s_fnc_buff[] = {0xf0, 0x22, 0x11, 0x0d, 0xf0, 0x00, 0x00, 0x00}; + +/* disabled unless IDF-5519 gets merged */ +//static uint8_t s_fnc_buff[] = {0xf0, 0x22, 0x11, 0x0d, 0xf0, 0x00, 0x00, 0x00}; typedef int (*fnc_ptr)(int); //testing buffers @@ -492,6 +495,7 @@ static void test_mprot_write(esp_mprot_mem_t mem_type, const int core) esp_mprot_monitor_clear_intr(mem_type, core); } +#if 0 /* disabled unless IDF-5519 gets merged */ static void test_mprot_exec(esp_mprot_mem_t mem_type, const int core) { if (!(mem_type & MEMPROT_TYPE_IRAM0_ANY)) { @@ -614,13 +618,14 @@ static void test_mprot_exec(esp_mprot_mem_t mem_type, const int core) esp_mprot_monitor_clear_intr(mem_type, core); } +#endif // testing per-CPU tasks esp_memp_config_t memp_cfg = { .invoke_panic_handler = false, .lock_feature = false, .split_addr = NULL, - .mem_type_mask = MEMPROT_TYPE_IRAM0_SRAM | MEMPROT_TYPE_DRAM0_SRAM, + .mem_type_mask = MEMPROT_TYPE_ALL, #if portNUM_PROCESSORS > 1 .target_cpu_count = 2, .target_cpu = {PRO_CPU_NUM, APP_CPU_NUM} @@ -642,7 +647,7 @@ static void task_on_CPU(void *arg) if (memp_cfg.mem_type_mask & MEMPROT_TYPE_IRAM0_SRAM) { test_mprot_read(MEMPROT_TYPE_IRAM0_SRAM, ctx->core); test_mprot_write(MEMPROT_TYPE_IRAM0_SRAM, ctx->core); - /* temporarily disabled */ + /* disabled unless IDF-5519 gets merged */ //test_mprot_exec(MEMPROT_TYPE_IRAM0_SRAM, ctx->core); } @@ -654,7 +659,8 @@ static void task_on_CPU(void *arg) if (memp_cfg.mem_type_mask & MEMPROT_TYPE_IRAM0_RTCFAST) { test_mprot_read(MEMPROT_TYPE_IRAM0_RTCFAST, ctx->core); test_mprot_write(MEMPROT_TYPE_IRAM0_RTCFAST, ctx->core); - test_mprot_exec(MEMPROT_TYPE_IRAM0_RTCFAST, ctx->core); + /* disabled unless IDF-5519 gets merged */ + //test_mprot_exec(MEMPROT_TYPE_IRAM0_RTCFAST, ctx->core); } xSemaphoreGive(ctx->sem);