Merge branch 'bringup/esp32h2_deep_sleep_for_rebase_v5.1' into 'release/v5.1'

esp32h2: support deep_sleep(backport v5.1)

See merge request espressif/esp-idf!24962

components/hal/esp32h2/include/hal/lp_aon_hal.h

@@ -0,0 +1,17 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "hal/lp_aon_ll.h"
+
+#define rtc_hal_ext1_get_wakeup_status()                    lp_aon_ll_ext1_get_wakeup_status()
+#define rtc_hal_ext1_clear_wakeup_status()                  lp_aon_ll_ext1_clear_wakeup_status()
+#define rtc_hal_ext1_set_wakeup_pins(mask, mode)            lp_aon_ll_ext1_set_wakeup_pins(mask, mode)
+#define rtc_hal_ext1_clear_wakeup_pins()                    lp_aon_ll_ext1_clear_wakeup_pins()
+#define rtc_hal_ext1_get_wakeup_pins()                      lp_aon_ll_ext1_get_wakeup_pins()
+
+#define lp_aon_hal_inform_wakeup_type(dslp)                 lp_aon_ll_inform_wakeup_type(dslp)

components/hal/esp32h2/include/hal/lp_aon_ll.h

@@ -0,0 +1,97 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for ESP32-H2 LP_AON register operations
+
+#pragma once
+
+#include <stdlib.h>
+#include "soc/soc.h"
+#include "soc/lp_aon_struct.h"
+#include "hal/misc.h"
+#include "esp32h2/rom/rtc.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Get ext1 wakeup source status
+ * @return  The lower 8 bits of the returned value are the bitmap of
+ *          the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
+ */
+static inline  uint32_t lp_aon_ll_ext1_get_wakeup_status(void)
+{
+    return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status);
+}
+
+/**
+ * @brief Clear the ext1 wakeup source status
+ */
+static inline void lp_aon_ll_ext1_clear_wakeup_status(void)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_status_clr, 1);
+}
+
+/**
+ * @brief Set the wake-up LP_IO of the ext1 wake-up source
+ * @param mask wakeup LP_IO bitmap, bit 0~7 corresponds to LP_IO 0~7
+ * @param mode 0: Wake the chip when any of the selected GPIOs go low
+ *             1: Wake the chip when any of the selected GPIOs go high
+ */
+static inline  void lp_aon_ll_ext1_set_wakeup_pins(uint32_t mask, int mode)
+{
+    uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
+    wakeup_sel_mask |= mask;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, wakeup_sel_mask);
+
+    uint32_t wakeup_level_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv);
+    if (mode) {
+        wakeup_level_mask |= mask;
+    } else {
+        wakeup_level_mask &= ~mask;
+    }
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, wakeup_level_mask);
+}
+
+/**
+ * @brief Clear all ext1 wakup-source setting
+ */
+static inline  void lp_aon_ll_ext1_clear_wakeup_pins(void)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, 0);
+}
+
+/**
+ * @brief Get ext1 wakeup source setting
+ * @return  The lower 8 bits of the returned value are the bitmap of
+ *          the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
+ */
+static inline  uint32_t lp_aon_ll_ext1_get_wakeup_pins(void)
+{
+    return HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
+}
+
+
+/**
+ *  @brief ROM obtains the wake-up type through LP_AON_STORE9_REG[0].
+ *         Set the flag to inform
+ * @param true: deepsleep      false: lightsleep
+ */
+static inline  void lp_aon_ll_inform_wakeup_type(bool dslp)
+{
+    if (dslp) {
+        REG_SET_BIT(SLEEP_MODE_REG, BIT(0));    /* Tell rom to run deep sleep wake stub */
+
+    } else {
+        REG_CLR_BIT(SLEEP_MODE_REG, BIT(0));    /* Tell rom to run light sleep wake stub */
+    }
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/rtc_io_ll.h

@@ -0,0 +1,104 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The ll is not public api, don't use in application code.
+ * See readme.md in hal/readme.md
+ ******************************************************************************/
+
+#pragma once
+
+#include "soc/lp_aon_struct.h"
+#include "soc/pmu_struct.h"
+#include "hal/misc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RTCIO_LL_GPIO_NUM_OFFSET    7 // rtcio 0-7 correspond to gpio 7-14
+
+typedef enum {
+    RTCIO_FUNC_RTC = 0x0,         /*!< The pin controlled by RTC module. */
+    RTCIO_FUNC_DIGITAL = 0x1,     /*!< The pin controlled by DIGITAL module. */
+} rtcio_ll_func_t;
+
+/**
+ * @brief Select the rtcio function.
+ *
+ * @note The RTC function must be selected before the pad analog function is enabled.
+ *
+ * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
+ * @param func Select pin function.
+ */
+static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
+{
+    if (func == RTCIO_FUNC_RTC) {
+        // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
+        uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel);
+        sel_mask |= BIT(rtcio_num);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask);
+    } else if (func == RTCIO_FUNC_DIGITAL) {
+        // Clear the bit to use digital GPIO module
+        uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel);
+        sel_mask &= ~BIT(rtcio_num);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask);
+    }
+}
+
+/**
+ * Enable force hold function for an RTC IO pad.
+ *
+ * Enabling HOLD function will cause the pad to lock current status, such as,
+ * input/output enable, input/output value, function, drive strength values.
+ * This function is useful when going into light or deep sleep mode to prevent
+ * the pin configuration from changing.
+ *
+ * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
+ */
+static inline void rtcio_ll_force_hold_enable(int rtcio_num)
+{
+    LP_AON.gpio_hold0.gpio_hold0 |= BIT(rtcio_num + RTCIO_LL_GPIO_NUM_OFFSET);
+}
+
+/**
+ * Disable hold function on an RTC IO pad
+ *
+ * @note If disable the pad hold, the status of pad maybe changed in sleep mode.
+ * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
+ */
+static inline void rtcio_ll_force_hold_disable(int rtcio_num)
+{
+    LP_AON.gpio_hold0.gpio_hold0 &= ~BIT(rtcio_num + RTCIO_LL_GPIO_NUM_OFFSET);
+}
+
+/**
+ * Enable force hold function for all RTC IO pads
+ *
+ * Enabling HOLD function will cause the pad to lock current status, such as,
+ * input/output enable, input/output value, function, drive strength values.
+ * This function is useful when going into light or deep sleep mode to prevent
+ * the pin configuration from changing.
+ */
+static inline void rtcio_ll_force_hold_all(void)
+{
+    PMU.imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;
+}
+
+/**
+ * Disable hold function fon all RTC IO pads
+ *
+ * @note If disable the pad hold, the status of pad maybe changed in sleep mode.
+ */
+static inline void rtcio_ll_force_unhold_all(void)
+{
+    PMU.imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;
+}
+
+#ifdef __cplusplus
+}
+#endif