From b765ad43cf614085728946801eddf460375aaf59 Mon Sep 17 00:00:00 2001 From: "C.S.M" Date: Fri, 18 Jul 2025 14:22:27 +0800 Subject: [PATCH] feat(spi_flash): Add flash suspend support on esp32h21, esp32h4 --- .../src/bootloader_flash_config_esp32h4.c | 7 +- .../hal/esp32h21/include/hal/cache_ll.h | 13 ++++ .../esp32h21/include/hal/spimem_flash_ll.h | 73 +++++++++++++++++++ components/hal/esp32h4/include/hal/mspi_ll.h | 1 + .../hal/esp32h4/include/hal/spimem_flash_ll.h | 73 +++++++++++++++++++ .../esp32h21/include/soc/Kconfig.soc_caps.in | 16 +--- .../soc/esp32h21/include/soc/soc_caps.h | 6 +- .../esp32h4/include/soc/Kconfig.soc_caps.in | 16 +--- components/soc/esp32h4/include/soc/soc_caps.h | 6 +- .../spi_flash/esp32h4/Kconfig.flash_freq | 2 - components/spi_flash/spi_flash_chip_gd.c | 3 +- .../test_apps/flash_suspend/README.md | 4 +- .../flash_suspend/main/test_flash_suspend.c | 3 + 13 files changed, 181 insertions(+), 42 deletions(-) diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h4.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h4.c index 10e54d2c3d..3afc95aa48 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h4.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h4.c @@ -85,12 +85,13 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv) esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); } -static void IRAM_ATTR bootloader_flash_clock_init(void) +static void IRAM_ATTR bootloader_mspi_clock_init(void) { // // To raise the MSPI clock to 64MHz, needs to enable the 64MHz clock source, which is XTAL_X2_CLK // // (FPGA image fixed MSPI0/1 clock to 64MHz) // clk_ll_xtal_x2_enable(); // _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_PLL_F64M); + // IDF-13632 _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_PLL_F48M); } @@ -195,7 +196,7 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr) static void IRAM_ATTR bootloader_init_flash_configure(void) { - bootloader_flash_clock_init(); + bootloader_mspi_clock_init(); bootloader_configure_spi_pins(1); bootloader_flash_cs_timing_config(); } @@ -278,7 +279,7 @@ void bootloader_flash_hardware_init(void) bootloader_configure_spi_pins(1); bootloader_flash_set_spi_mode(&hdr); bootloader_flash_clock_config(&hdr); - bootloader_flash_clock_init(); + bootloader_mspi_clock_init(); bootloader_flash_cs_timing_config(); bootloader_spi_flash_resume(); diff --git a/components/hal/esp32h21/include/hal/cache_ll.h b/components/hal/esp32h21/include/hal/cache_ll.h index 5a47166b53..8152391a9a 100644 --- a/components/hal/esp32h21/include/hal/cache_ll.h +++ b/components/hal/esp32h21/include/hal/cache_ll.h @@ -128,6 +128,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t Cache_Invalidate_Addr(vaddr, size); } +/** + * @brief Invalidate all + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + Cache_Invalidate_ICache_All(); +} + /** * @brief Freeze Cache * diff --git a/components/hal/esp32h21/include/hal/spimem_flash_ll.h b/components/hal/esp32h21/include/hal/spimem_flash_ll.h index 92f150b56a..c616afe49d 100644 --- a/components/hal/esp32h21/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32h21/include/hal/spimem_flash_ll.h @@ -725,6 +725,79 @@ static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_ dev->user2.val = user2_reg; } + +#define SPIMEM_FLASH_LL_SUSPEND_END_INTR SPI_MEM_PES_END_INT_ENA_M +#define SPIMEM_FLASH_LL_INTERRUPT_SOURCE ETS_MSPI_INTR_SOURCE + +/** + * @brief Get the address of the interrupt status register. + * + * This function returns a pointer to the interrupt status register of the SPI memory device. + * + * @param[in] dev Pointer to the SPI memory device structure. + * @return volatile void* Pointer to the interrupt status register. + */ +static inline volatile void *spimem_flash_ll_get_interrupt_status_reg(spi_mem_dev_t *dev) +{ + return &dev->int_st; +} + +/** + * @brief Clear specific interrupt status bits. + * + * This function clears the specified interrupt bits in the interrupt clear register of the SPI memory device. + * + * @param[in] dev Pointer to the SPI memory device structure. + * @param[in] mask Bitmask specifying which interrupt bits to clear. + */ +__attribute__((always_inline)) +static inline void spimem_flash_ll_clear_intr_mask(spi_mem_dev_t *dev, uint32_t mask) +{ + dev->int_clr.val = mask; +} + +/** + * @brief Enable specific interrupt bits. + * + * This function enables the specified interrupts in the interrupt enable register of the SPI memory device. + * + * @param[in] dev Pointer to the SPI memory device structure. + * @param[in] mask Bitmask specifying which interrupt bits to enable. + */ +__attribute__((always_inline)) +static inline void spimem_flash_ll_enable_intr_mask(spi_mem_dev_t *dev, uint32_t mask) +{ + dev->int_ena.val |= mask; +} + +/** + * @brief Disable specific interrupt bits. + * + * This function disables the specified interrupts in the interrupt enable register of the SPI memory device. + * + * @param[in] dev Pointer to the SPI memory device structure. + * @param[in] mask Bitmask specifying which interrupt bits to disable. + */ +__attribute__((always_inline)) +static inline void spimem_flash_ll_disable_intr_mask(spi_mem_dev_t *dev, uint32_t mask) +{ + dev->int_ena.val &= (~mask); +} + +/** + * @brief Get the current interrupt status. + * + * This function retrieves the current interrupt status from the interrupt status register of the SPI memory device. + * + * @param[in] dev Pointer to the SPI memory device structure. + * @param[out] intr_status Pointer to a variable where the interrupt status will be stored. + */ +__attribute__((always_inline)) +static inline void spimem_flash_ll_get_intr_mask(spi_mem_dev_t *dev, uint32_t *intr_status) +{ + *intr_status = dev->int_st.val; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h4/include/hal/mspi_ll.h b/components/hal/esp32h4/include/hal/mspi_ll.h index cb52b979e3..df1face1d5 100644 --- a/components/hal/esp32h4/include/hal/mspi_ll.h +++ b/components/hal/esp32h4/include/hal/mspi_ll.h @@ -56,6 +56,7 @@ static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_perip // case FLASH_CLK_SRC_PLL_F64M: // PCR.mspi_clk_conf.mspi_func_clk_sel = 2; // break; + // TODO: [ESP32H4] IDF-13632, support 64M case FLASH_CLK_SRC_PLL_F48M: PCR.mspi_clk_conf.mspi_func_clk_sel = 3; break; diff --git a/components/hal/esp32h4/include/hal/spimem_flash_ll.h b/components/hal/esp32h4/include/hal/spimem_flash_ll.h index 75a5604294..6e5ab23312 100644 --- a/components/hal/esp32h4/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32h4/include/hal/spimem_flash_ll.h @@ -724,6 +724,79 @@ static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_ dev->user2.val = user2_reg; } + +#define SPIMEM_FLASH_LL_SUSPEND_END_INTR SPI_MEM_PES_END_INT_ENA_M +#define SPIMEM_FLASH_LL_INTERRUPT_SOURCE ETS_MSPI_INTR_SOURCE + +/** + * @brief Get the address of the interrupt status register. + * + * This function returns a pointer to the interrupt status register of the SPI memory device. + * + * @param[in] dev Pointer to the SPI memory device structure. + * @return volatile void* Pointer to the interrupt status register. + */ +static inline volatile void *spimem_flash_ll_get_interrupt_status_reg(spi_mem_dev_t *dev) +{ + return &dev->int_st; +} + +/** + * @brief Clear specific interrupt status bits. + * + * This function clears the specified interrupt bits in the interrupt clear register of the SPI memory device. + * + * @param[in] dev Pointer to the SPI memory device structure. + * @param[in] mask Bitmask specifying which interrupt bits to clear. + */ +__attribute__((always_inline)) +static inline void spimem_flash_ll_clear_intr_mask(spi_mem_dev_t *dev, uint32_t mask) +{ + dev->int_clr.val = mask; +} + +/** + * @brief Enable specific interrupt bits. + * + * This function enables the specified interrupts in the interrupt enable register of the SPI memory device. + * + * @param[in] dev Pointer to the SPI memory device structure. + * @param[in] mask Bitmask specifying which interrupt bits to enable. + */ +__attribute__((always_inline)) +static inline void spimem_flash_ll_enable_intr_mask(spi_mem_dev_t *dev, uint32_t mask) +{ + dev->int_ena.val |= mask; +} + +/** + * @brief Disable specific interrupt bits. + * + * This function disables the specified interrupts in the interrupt enable register of the SPI memory device. + * + * @param[in] dev Pointer to the SPI memory device structure. + * @param[in] mask Bitmask specifying which interrupt bits to disable. + */ +__attribute__((always_inline)) +static inline void spimem_flash_ll_disable_intr_mask(spi_mem_dev_t *dev, uint32_t mask) +{ + dev->int_ena.val &= (~mask); +} + +/** + * @brief Get the current interrupt status. + * + * This function retrieves the current interrupt status from the interrupt status register of the SPI memory device. + * + * @param[in] dev Pointer to the SPI memory device structure. + * @param[out] intr_status Pointer to a variable where the interrupt status will be stored. + */ +__attribute__((always_inline)) +static inline void spimem_flash_ll_get_intr_mask(spi_mem_dev_t *dev, uint32_t *intr_status) +{ + *intr_status = dev->int_st.val; +} + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in index 4d7459a3d0..ac6207ccb1 100644 --- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -567,6 +567,10 @@ config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE bool default y +config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND + bool + default y + config SOC_SPI_MEM_SUPPORT_AUTO_RESUME bool default y @@ -587,18 +591,6 @@ config SOC_SPI_MEM_SUPPORT_WRAP bool default y -config SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED - bool - default y - config SOC_SYSTIMER_COUNTER_NUM int default 2 diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h index 4c3ee38c25..aca845d3ec 100644 --- a/components/soc/esp32h21/include/soc/soc_caps.h +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -415,17 +415,13 @@ /*-------------------------- SPI MEM CAPS ---------------------------------------*/ #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) -// #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) //TODO: [ESP32H21] IDF-11526 +#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) #define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) #define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) #define SOC_SPI_MEM_SUPPORT_WRAP (1) -#define SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED 1 - /*-------------------------- SYSTIMER CAPS ----------------------------------*/ #define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units #define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index 8d3fc80a47..3e869c3af5 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -335,6 +335,10 @@ config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE bool default y +config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND + bool + default y + config SOC_SPI_MEM_SUPPORT_AUTO_RESUME bool default y @@ -355,18 +359,6 @@ config SOC_SPI_MEM_SUPPORT_WRAP bool default y -config SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED - bool - default y - -config SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED - bool - default y - config SOC_SYSTIMER_COUNTER_NUM int default 2 diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index 201f60311d..0a0776ddf7 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -407,17 +407,13 @@ /*-------------------------- SPI MEM CAPS ---------------------------------------*/ #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) -// #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) // TODO: [ESP32H4] IDF-12290 +#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) #define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) #define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) #define SOC_SPI_MEM_SUPPORT_WRAP (1) -#define SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED 1 -#define SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED 1 - /*-------------------------- SYSTIMER CAPS ----------------------------------*/ #define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units #define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units diff --git a/components/spi_flash/esp32h4/Kconfig.flash_freq b/components/spi_flash/esp32h4/Kconfig.flash_freq index 4100aa4b8f..a24b915877 100644 --- a/components/spi_flash/esp32h4/Kconfig.flash_freq +++ b/components/spi_flash/esp32h4/Kconfig.flash_freq @@ -5,6 +5,4 @@ choice ESPTOOLPY_FLASHFREQ bool "48 MHz" config ESPTOOLPY_FLASHFREQ_24M bool "24 MHz" - config ESPTOOLPY_FLASHFREQ_12M - bool "12 MHz" endchoice diff --git a/components/spi_flash/spi_flash_chip_gd.c b/components/spi_flash/spi_flash_chip_gd.c index 313800ef8e..b12223f607 100644 --- a/components/spi_flash/spi_flash_chip_gd.c +++ b/components/spi_flash/spi_flash_chip_gd.c @@ -73,6 +73,7 @@ esp_err_t spi_flash_chip_gd_detect_size(esp_flash_t *chip, uint32_t *size) #define FLASH_SIZE_MASK 0xFF #define GD25Q_PRODUCT_ID 0x4000 #define GD25LQ_PRODUCT_ID 0x6000 +#define GD25UF_PRODUCT_ID 0x8300 #define WRSR_16B_REQUIRED(chip_id) (((chip_id) & FLASH_ID_MASK) == GD25LQ_PRODUCT_ID || \ ((chip_id) & FLASH_SIZE_MASK) <= 0x15) @@ -88,7 +89,7 @@ esp_err_t spi_flash_chip_gd_probe(esp_flash_t *chip, uint32_t flash_id) } uint32_t product_id = flash_id & FLASH_ID_MASK; - if (product_id != GD25Q_PRODUCT_ID && product_id != GD25LQ_PRODUCT_ID) { + if (product_id != GD25Q_PRODUCT_ID && product_id != GD25LQ_PRODUCT_ID && product_id != GD25UF_PRODUCT_ID) { return ESP_ERR_NOT_FOUND; } diff --git a/components/spi_flash/test_apps/flash_suspend/README.md b/components/spi_flash/test_apps/flash_suspend/README.md index 38905dfdce..9b75252329 100644 --- a/components/spi_flash/test_apps/flash_suspend/README.md +++ b/components/spi_flash/test_apps/flash_suspend/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | diff --git a/components/spi_flash/test_apps/flash_suspend/main/test_flash_suspend.c b/components/spi_flash/test_apps/flash_suspend/main/test_flash_suspend.c index a7a517b177..52be91feb4 100644 --- a/components/spi_flash/test_apps/flash_suspend/main/test_flash_suspend.c +++ b/components/spi_flash/test_apps/flash_suspend/main/test_flash_suspend.c @@ -23,6 +23,7 @@ #include "esp_flash.h" #include "hal/gpio_hal.h" #include "rom/cache.h" +#include "hal/cache_ll.h" #include "test_utils.h" @@ -77,6 +78,8 @@ static bool IRAM_ATTR gptimer_alarm_suspend_cb(gptimer_handle_t timer, const gpt #endif #if CONFIG_IDF_TARGET_ESP32P4 Cache_Invalidate_All(CACHE_MAP_L2_CACHE); +#elif CONFIG_IDF_TARGET_ESP32H4 + cache_ll_invalidate_all(CACHE_LL_LEVEL_ALL, CACHE_TYPE_ALL, CACHE_LL_ID_ALL); #elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 Cache_Invalidate_All(); #else