mirror of
https://github.com/espressif/esp-idf.git
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feat(efuse): Updates efuse table for esp32c5
This commit is contained in:
Konstantin Kondrashov
committed by
BOT
BOT
parent
ce822125e7
commit
b7cbf82c14
@@ -262,14 +262,14 @@ extern "C" {
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#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U
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#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20
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/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0;
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* Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
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* Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
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*/
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#define EFUSE_USB_DREFH 0x00000003U
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#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
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#define EFUSE_USB_DREFH_V 0x00000003U
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#define EFUSE_USB_DREFH_S 21
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/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0;
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* Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
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* Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
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*/
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#define EFUSE_USB_DREFL 0x00000003U
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#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
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@@ -693,32 +693,123 @@ extern "C" {
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* Represents rd_mac_sys
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*/
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#define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE_BASE + 0x4c)
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/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [13:0]; default: 0;
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* Reserved.
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/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [3:0]; default: 0;
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* Minor chip version
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*/
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#define EFUSE_MAC_RESERVED_0 0x00003FFFU
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#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S)
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#define EFUSE_MAC_RESERVED_0_V 0x00003FFFU
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#define EFUSE_MAC_RESERVED_0_S 0
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/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [31:14]; default: 0;
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* Reserved.
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#define EFUSE_WAFER_VERSION_MINOR 0x0000000FU
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#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
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#define EFUSE_WAFER_VERSION_MINOR_V 0x0000000FU
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#define EFUSE_WAFER_VERSION_MINOR_S 0
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/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [5:4]; default: 0;
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* Minor chip version
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*/
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#define EFUSE_MAC_RESERVED_1 0x0003FFFFU
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#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S)
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#define EFUSE_MAC_RESERVED_1_V 0x0003FFFFU
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#define EFUSE_MAC_RESERVED_1_S 14
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#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U
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#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
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#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U
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#define EFUSE_WAFER_VERSION_MAJOR_S 4
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/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [6]; default: 0;
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* Disables check of wafer version major
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*/
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#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(6))
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#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
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#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U
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#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 6
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/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0;
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* Disables check of blk version major
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*/
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#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(7))
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#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
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#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U
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#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 7
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/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [10:8]; default: 0;
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* BLK_VERSION_MINOR of BLOCK2
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*/
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#define EFUSE_BLK_VERSION_MINOR 0x00000007U
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#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
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#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U
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#define EFUSE_BLK_VERSION_MINOR_S 8
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/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [12:11]; default: 0;
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* BLK_VERSION_MAJOR of BLOCK2
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*/
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#define EFUSE_BLK_VERSION_MAJOR 0x00000003U
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#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
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#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U
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#define EFUSE_BLK_VERSION_MAJOR_S 11
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/** EFUSE_FLASH_CAP : R; bitpos: [15:13]; default: 0;
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* Flash capacity
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*/
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#define EFUSE_FLASH_CAP 0x00000007U
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#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
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#define EFUSE_FLASH_CAP_V 0x00000007U
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#define EFUSE_FLASH_CAP_S 13
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/** EFUSE_FLASH_VENDOR : R; bitpos: [18:16]; default: 0;
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* Flash vendor
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*/
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#define EFUSE_FLASH_VENDOR 0x00000007U
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#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
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#define EFUSE_FLASH_VENDOR_V 0x00000007U
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#define EFUSE_FLASH_VENDOR_S 16
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/** EFUSE_PSRAM_CAP : R; bitpos: [21:19]; default: 0;
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* Psram capacity
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*/
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#define EFUSE_PSRAM_CAP 0x00000007U
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#define EFUSE_PSRAM_CAP_M (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S)
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#define EFUSE_PSRAM_CAP_V 0x00000007U
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#define EFUSE_PSRAM_CAP_S 19
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/** EFUSE_PSRAM_VENDOR : R; bitpos: [23:22]; default: 0;
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* Psram vendor
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*/
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#define EFUSE_PSRAM_VENDOR 0x00000003U
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#define EFUSE_PSRAM_VENDOR_M (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S)
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#define EFUSE_PSRAM_VENDOR_V 0x00000003U
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#define EFUSE_PSRAM_VENDOR_S 22
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/** EFUSE_TEMP : R; bitpos: [25:24]; default: 0;
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* Temp (die embedded inside)
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*/
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#define EFUSE_TEMP 0x00000003U
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#define EFUSE_TEMP_M (EFUSE_TEMP_V << EFUSE_TEMP_S)
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#define EFUSE_TEMP_V 0x00000003U
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#define EFUSE_TEMP_S 24
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/** EFUSE_PKG_VERSION : R; bitpos: [28:26]; default: 0;
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* Package version
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*/
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#define EFUSE_PKG_VERSION 0x00000007U
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#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
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#define EFUSE_PKG_VERSION_V 0x00000007U
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#define EFUSE_PKG_VERSION_S 26
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/** EFUSE_PA_TRIM_VERSION : R; bitpos: [31:29]; default: 0;
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* PADC CAL PA trim version
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*/
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#define EFUSE_PA_TRIM_VERSION 0x00000007U
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#define EFUSE_PA_TRIM_VERSION_M (EFUSE_PA_TRIM_VERSION_V << EFUSE_PA_TRIM_VERSION_S)
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#define EFUSE_PA_TRIM_VERSION_V 0x00000007U
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#define EFUSE_PA_TRIM_VERSION_S 29
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/** EFUSE_RD_MAC_SYS3_REG register
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* Represents rd_mac_sys
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*/
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#define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x50)
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/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0;
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* Reserved.
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/** EFUSE_TRIM_N_BIAS : R; bitpos: [4:0]; default: 0;
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* PADC CAL N bias
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*/
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#define EFUSE_MAC_RESERVED_2 0x0003FFFFU
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#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S)
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#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU
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#define EFUSE_MAC_RESERVED_2_S 0
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#define EFUSE_TRIM_N_BIAS 0x0000001FU
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#define EFUSE_TRIM_N_BIAS_M (EFUSE_TRIM_N_BIAS_V << EFUSE_TRIM_N_BIAS_S)
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#define EFUSE_TRIM_N_BIAS_V 0x0000001FU
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#define EFUSE_TRIM_N_BIAS_S 0
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/** EFUSE_TRIM_P_BIAS : R; bitpos: [9:5]; default: 0;
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* PADC CAL P bias
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*/
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#define EFUSE_TRIM_P_BIAS 0x0000001FU
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#define EFUSE_TRIM_P_BIAS_M (EFUSE_TRIM_P_BIAS_V << EFUSE_TRIM_P_BIAS_S)
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#define EFUSE_TRIM_P_BIAS_V 0x0000001FU
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#define EFUSE_TRIM_P_BIAS_S 5
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/** EFUSE_RESERVED_1_106 : R; bitpos: [17:10]; default: 0;
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* reserved
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*/
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#define EFUSE_RESERVED_1_106 0x000000FFU
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#define EFUSE_RESERVED_1_106_M (EFUSE_RESERVED_1_106_V << EFUSE_RESERVED_1_106_S)
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#define EFUSE_RESERVED_1_106_V 0x000000FFU
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#define EFUSE_RESERVED_1_106_S 10
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/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
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* Represents the first 14-bit of zeroth part of system data.
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*/
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@@ -755,61 +846,75 @@ extern "C" {
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* Represents rd_sys_part1_data0
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*/
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#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
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/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0;
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* Represents the zeroth 32-bit of first part of system data.
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/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
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* Optional unique 128-bit ID
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*/
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#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S)
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#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_0_S 0
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#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU
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#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
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#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU
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#define EFUSE_OPTIONAL_UNIQUE_ID_S 0
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/** EFUSE_RD_SYS_PART1_DATA1_REG register
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* Represents rd_sys_part1_data1
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*/
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#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
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/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0;
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* Represents the zeroth 32-bit of first part of system data.
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/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
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* Optional unique 128-bit ID
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*/
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#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S)
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#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_1_S 0
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#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU
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#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
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#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU
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#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0
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/** EFUSE_RD_SYS_PART1_DATA2_REG register
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* Represents rd_sys_part1_data2
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*/
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#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
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/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0;
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* Represents the zeroth 32-bit of first part of system data.
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/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
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* Optional unique 128-bit ID
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*/
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#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S)
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#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_2_S 0
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#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU
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#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
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#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU
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#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0
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/** EFUSE_RD_SYS_PART1_DATA3_REG register
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* Represents rd_sys_part1_data3
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*/
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#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
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/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0;
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* Represents the zeroth 32-bit of first part of system data.
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/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
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* Optional unique 128-bit ID
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*/
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#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S)
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#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_3_S 0
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#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU
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#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
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#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU
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#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0
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/** EFUSE_RD_SYS_PART1_DATA4_REG register
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* Represents rd_sys_part1_data4
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*/
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#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
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/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
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* Represents the zeroth 32-bit of first part of system data.
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/** EFUSE_RESERVED_2_128 : R; bitpos: [8:0]; default: 0;
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* reserved
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*/
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#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
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#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_4_S 0
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#define EFUSE_RESERVED_2_128 0x000001FFU
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#define EFUSE_RESERVED_2_128_M (EFUSE_RESERVED_2_128_V << EFUSE_RESERVED_2_128_S)
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#define EFUSE_RESERVED_2_128_V 0x000001FFU
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#define EFUSE_RESERVED_2_128_S 0
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/** EFUSE_OCODE : R; bitpos: [16:9]; default: 0;
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* ADC OCode
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*/
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#define EFUSE_OCODE 0x000000FFU
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#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S)
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#define EFUSE_OCODE_V 0x000000FFU
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#define EFUSE_OCODE_S 9
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/** EFUSE_RESERVED_2_145 : R; bitpos: [31:17]; default: 0;
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* reserved
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*/
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#define EFUSE_RESERVED_2_145 0x00007FFFU
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#define EFUSE_RESERVED_2_145_M (EFUSE_RESERVED_2_145_V << EFUSE_RESERVED_2_145_S)
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#define EFUSE_RESERVED_2_145_V 0x00007FFFU
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#define EFUSE_RESERVED_2_145_S 17
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/** EFUSE_RD_SYS_PART1_DATA5_REG register
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* Represents rd_sys_part1_data5
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@@ -2247,7 +2352,7 @@ extern "C" {
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#define EFUSE_CLK_EN_S 16
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/** EFUSE_CONF_REG register
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* eFuse operation mode configuraiton register
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* eFuse operation mode configuration register
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*/
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#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
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/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
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@@ -241,11 +241,11 @@ typedef union {
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*/
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uint32_t dis_download_manual_encrypt:1;
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/** usb_drefh : RO; bitpos: [22:21]; default: 0;
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* Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
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* Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
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*/
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uint32_t usb_drefh:2;
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/** usb_drefl : RO; bitpos: [24:23]; default: 0;
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* Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
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* Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
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*/
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uint32_t usb_drefl:2;
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/** usb_exchg_pins : RO; bitpos: [25]; default: 0;
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@@ -546,14 +546,58 @@ typedef union {
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*/
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typedef union {
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struct {
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/** mac_reserved_0 : RO; bitpos: [13:0]; default: 0;
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* Reserved.
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/** wafer_version_minor : R; bitpos: [3:0]; default: 0;
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* Minor chip version
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*/
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uint32_t mac_reserved_0:14;
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/** mac_reserved_1 : RO; bitpos: [31:14]; default: 0;
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* Reserved.
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uint32_t wafer_version_minor:4;
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/** wafer_version_major : R; bitpos: [5:4]; default: 0;
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* Minor chip version
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*/
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uint32_t mac_reserved_1:18;
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uint32_t wafer_version_major:2;
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/** disable_wafer_version_major : R; bitpos: [6]; default: 0;
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* Disables check of wafer version major
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*/
|
||||
uint32_t disable_wafer_version_major:1;
|
||||
/** disable_blk_version_major : R; bitpos: [7]; default: 0;
|
||||
* Disables check of blk version major
|
||||
*/
|
||||
uint32_t disable_blk_version_major:1;
|
||||
/** blk_version_minor : R; bitpos: [10:8]; default: 0;
|
||||
* BLK_VERSION_MINOR of BLOCK2
|
||||
*/
|
||||
uint32_t blk_version_minor:3;
|
||||
/** blk_version_major : R; bitpos: [12:11]; default: 0;
|
||||
* BLK_VERSION_MAJOR of BLOCK2
|
||||
*/
|
||||
uint32_t blk_version_major:2;
|
||||
/** flash_cap : R; bitpos: [15:13]; default: 0;
|
||||
* Flash capacity
|
||||
*/
|
||||
uint32_t flash_cap:3;
|
||||
/** flash_vendor : R; bitpos: [18:16]; default: 0;
|
||||
* Flash vendor
|
||||
*/
|
||||
uint32_t flash_vendor:3;
|
||||
/** psram_cap : R; bitpos: [21:19]; default: 0;
|
||||
* Psram capacity
|
||||
*/
|
||||
uint32_t psram_cap:3;
|
||||
/** psram_vendor : R; bitpos: [23:22]; default: 0;
|
||||
* Psram vendor
|
||||
*/
|
||||
uint32_t psram_vendor:2;
|
||||
/** temp : R; bitpos: [25:24]; default: 0;
|
||||
* Temp (die embedded inside)
|
||||
*/
|
||||
uint32_t temp:2;
|
||||
/** pkg_version : R; bitpos: [28:26]; default: 0;
|
||||
* Package version
|
||||
*/
|
||||
uint32_t pkg_version:3;
|
||||
/** pa_trim_version : R; bitpos: [31:29]; default: 0;
|
||||
* PADC CAL PA trim version
|
||||
*/
|
||||
uint32_t pa_trim_version:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_mac_sys2_reg_t;
|
||||
@@ -563,10 +607,18 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** mac_reserved_2 : RO; bitpos: [17:0]; default: 0;
|
||||
* Reserved.
|
||||
/** trim_n_bias : R; bitpos: [4:0]; default: 0;
|
||||
* PADC CAL N bias
|
||||
*/
|
||||
uint32_t mac_reserved_2:18;
|
||||
uint32_t trim_n_bias:5;
|
||||
/** trim_p_bias : R; bitpos: [9:5]; default: 0;
|
||||
* PADC CAL P bias
|
||||
*/
|
||||
uint32_t trim_p_bias:5;
|
||||
/** reserved_1_106 : R; bitpos: [17:10]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_1_106:8;
|
||||
/** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
|
||||
* Represents the first 14-bit of zeroth part of system data.
|
||||
*/
|
||||
@@ -608,10 +660,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** optional_unique_id : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
uint32_t sys_data_part1_0:32;
|
||||
uint32_t optional_unique_id:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data0_reg_t;
|
||||
@@ -621,10 +673,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
uint32_t sys_data_part1_1:32;
|
||||
uint32_t optional_unique_id_1:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data1_reg_t;
|
||||
@@ -634,10 +686,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
uint32_t sys_data_part1_2:32;
|
||||
uint32_t optional_unique_id_2:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data2_reg_t;
|
||||
@@ -647,10 +699,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
uint32_t sys_data_part1_3:32;
|
||||
uint32_t optional_unique_id_3:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data3_reg_t;
|
||||
@@ -660,10 +712,18 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** reserved_2_128 : R; bitpos: [8:0]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t sys_data_part1_4:32;
|
||||
uint32_t reserved_2_128:9;
|
||||
/** ocode : R; bitpos: [16:9]; default: 0;
|
||||
* ADC OCode
|
||||
*/
|
||||
uint32_t ocode:8;
|
||||
/** reserved_2_145 : R; bitpos: [31:17]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_2_145:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data4_reg_t;
|
||||
@@ -1993,7 +2053,7 @@ typedef union {
|
||||
} efuse_clk_reg_t;
|
||||
|
||||
/** Type of conf register
|
||||
* eFuse operation mode configuraiton register
|
||||
* eFuse operation mode configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
|
||||
@@ -263,14 +263,14 @@ extern "C" {
|
||||
#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U
|
||||
#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20
|
||||
/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0;
|
||||
* Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
|
||||
* Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
|
||||
*/
|
||||
#define EFUSE_USB_DREFH 0x00000003U
|
||||
#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
|
||||
#define EFUSE_USB_DREFH_V 0x00000003U
|
||||
#define EFUSE_USB_DREFH_S 21
|
||||
/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0;
|
||||
* Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
|
||||
* Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
|
||||
*/
|
||||
#define EFUSE_USB_DREFL 0x00000003U
|
||||
#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
|
||||
@@ -694,32 +694,123 @@ extern "C" {
|
||||
* Represents rd_mac_sys
|
||||
*/
|
||||
#define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE_BASE + 0x4c)
|
||||
/** EFUSE_MAC_RESERVED_0 : RO; bitpos: [13:0]; default: 0;
|
||||
* Reserved.
|
||||
/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [3:0]; default: 0;
|
||||
* Minor chip version
|
||||
*/
|
||||
#define EFUSE_MAC_RESERVED_0 0x00003FFFU
|
||||
#define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S)
|
||||
#define EFUSE_MAC_RESERVED_0_V 0x00003FFFU
|
||||
#define EFUSE_MAC_RESERVED_0_S 0
|
||||
/** EFUSE_MAC_RESERVED_1 : RO; bitpos: [31:14]; default: 0;
|
||||
* Reserved.
|
||||
#define EFUSE_WAFER_VERSION_MINOR 0x0000000FU
|
||||
#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
|
||||
#define EFUSE_WAFER_VERSION_MINOR_V 0x0000000FU
|
||||
#define EFUSE_WAFER_VERSION_MINOR_S 0
|
||||
/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [5:4]; default: 0;
|
||||
* Minor chip version
|
||||
*/
|
||||
#define EFUSE_MAC_RESERVED_1 0x0003FFFFU
|
||||
#define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S)
|
||||
#define EFUSE_MAC_RESERVED_1_V 0x0003FFFFU
|
||||
#define EFUSE_MAC_RESERVED_1_S 14
|
||||
#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U
|
||||
#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
|
||||
#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U
|
||||
#define EFUSE_WAFER_VERSION_MAJOR_S 4
|
||||
/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [6]; default: 0;
|
||||
* Disables check of wafer version major
|
||||
*/
|
||||
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(6))
|
||||
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
|
||||
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U
|
||||
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 6
|
||||
/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0;
|
||||
* Disables check of blk version major
|
||||
*/
|
||||
#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(7))
|
||||
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
|
||||
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U
|
||||
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 7
|
||||
/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [10:8]; default: 0;
|
||||
* BLK_VERSION_MINOR of BLOCK2
|
||||
*/
|
||||
#define EFUSE_BLK_VERSION_MINOR 0x00000007U
|
||||
#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
|
||||
#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U
|
||||
#define EFUSE_BLK_VERSION_MINOR_S 8
|
||||
/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [12:11]; default: 0;
|
||||
* BLK_VERSION_MAJOR of BLOCK2
|
||||
*/
|
||||
#define EFUSE_BLK_VERSION_MAJOR 0x00000003U
|
||||
#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
|
||||
#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U
|
||||
#define EFUSE_BLK_VERSION_MAJOR_S 11
|
||||
/** EFUSE_FLASH_CAP : R; bitpos: [15:13]; default: 0;
|
||||
* Flash capacity
|
||||
*/
|
||||
#define EFUSE_FLASH_CAP 0x00000007U
|
||||
#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
|
||||
#define EFUSE_FLASH_CAP_V 0x00000007U
|
||||
#define EFUSE_FLASH_CAP_S 13
|
||||
/** EFUSE_FLASH_VENDOR : R; bitpos: [18:16]; default: 0;
|
||||
* Flash vendor
|
||||
*/
|
||||
#define EFUSE_FLASH_VENDOR 0x00000007U
|
||||
#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
|
||||
#define EFUSE_FLASH_VENDOR_V 0x00000007U
|
||||
#define EFUSE_FLASH_VENDOR_S 16
|
||||
/** EFUSE_PSRAM_CAP : R; bitpos: [21:19]; default: 0;
|
||||
* Psram capacity
|
||||
*/
|
||||
#define EFUSE_PSRAM_CAP 0x00000007U
|
||||
#define EFUSE_PSRAM_CAP_M (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S)
|
||||
#define EFUSE_PSRAM_CAP_V 0x00000007U
|
||||
#define EFUSE_PSRAM_CAP_S 19
|
||||
/** EFUSE_PSRAM_VENDOR : R; bitpos: [23:22]; default: 0;
|
||||
* Psram vendor
|
||||
*/
|
||||
#define EFUSE_PSRAM_VENDOR 0x00000003U
|
||||
#define EFUSE_PSRAM_VENDOR_M (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S)
|
||||
#define EFUSE_PSRAM_VENDOR_V 0x00000003U
|
||||
#define EFUSE_PSRAM_VENDOR_S 22
|
||||
/** EFUSE_TEMP : R; bitpos: [25:24]; default: 0;
|
||||
* Temp (die embedded inside)
|
||||
*/
|
||||
#define EFUSE_TEMP 0x00000003U
|
||||
#define EFUSE_TEMP_M (EFUSE_TEMP_V << EFUSE_TEMP_S)
|
||||
#define EFUSE_TEMP_V 0x00000003U
|
||||
#define EFUSE_TEMP_S 24
|
||||
/** EFUSE_PKG_VERSION : R; bitpos: [28:26]; default: 0;
|
||||
* Package version
|
||||
*/
|
||||
#define EFUSE_PKG_VERSION 0x00000007U
|
||||
#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
|
||||
#define EFUSE_PKG_VERSION_V 0x00000007U
|
||||
#define EFUSE_PKG_VERSION_S 26
|
||||
/** EFUSE_PA_TRIM_VERSION : R; bitpos: [31:29]; default: 0;
|
||||
* PADC CAL PA trim version
|
||||
*/
|
||||
#define EFUSE_PA_TRIM_VERSION 0x00000007U
|
||||
#define EFUSE_PA_TRIM_VERSION_M (EFUSE_PA_TRIM_VERSION_V << EFUSE_PA_TRIM_VERSION_S)
|
||||
#define EFUSE_PA_TRIM_VERSION_V 0x00000007U
|
||||
#define EFUSE_PA_TRIM_VERSION_S 29
|
||||
|
||||
/** EFUSE_RD_MAC_SYS3_REG register
|
||||
* Represents rd_mac_sys
|
||||
*/
|
||||
#define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x50)
|
||||
/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0;
|
||||
* Reserved.
|
||||
/** EFUSE_TRIM_N_BIAS : R; bitpos: [4:0]; default: 0;
|
||||
* PADC CAL N bias
|
||||
*/
|
||||
#define EFUSE_MAC_RESERVED_2 0x0003FFFFU
|
||||
#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S)
|
||||
#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU
|
||||
#define EFUSE_MAC_RESERVED_2_S 0
|
||||
#define EFUSE_TRIM_N_BIAS 0x0000001FU
|
||||
#define EFUSE_TRIM_N_BIAS_M (EFUSE_TRIM_N_BIAS_V << EFUSE_TRIM_N_BIAS_S)
|
||||
#define EFUSE_TRIM_N_BIAS_V 0x0000001FU
|
||||
#define EFUSE_TRIM_N_BIAS_S 0
|
||||
/** EFUSE_TRIM_P_BIAS : R; bitpos: [9:5]; default: 0;
|
||||
* PADC CAL P bias
|
||||
*/
|
||||
#define EFUSE_TRIM_P_BIAS 0x0000001FU
|
||||
#define EFUSE_TRIM_P_BIAS_M (EFUSE_TRIM_P_BIAS_V << EFUSE_TRIM_P_BIAS_S)
|
||||
#define EFUSE_TRIM_P_BIAS_V 0x0000001FU
|
||||
#define EFUSE_TRIM_P_BIAS_S 5
|
||||
/** EFUSE_RESERVED_1_106 : R; bitpos: [17:10]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_1_106 0x000000FFU
|
||||
#define EFUSE_RESERVED_1_106_M (EFUSE_RESERVED_1_106_V << EFUSE_RESERVED_1_106_S)
|
||||
#define EFUSE_RESERVED_1_106_V 0x000000FFU
|
||||
#define EFUSE_RESERVED_1_106_S 10
|
||||
/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
|
||||
* Represents the first 14-bit of zeroth part of system data.
|
||||
*/
|
||||
@@ -756,61 +847,75 @@ extern "C" {
|
||||
* Represents rd_sys_part1_data0
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
|
||||
/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S)
|
||||
#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_0_S 0
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_S 0
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA1_REG register
|
||||
* Represents rd_sys_part1_data1
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
|
||||
/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S)
|
||||
#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_1_S 0
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA2_REG register
|
||||
* Represents rd_sys_part1_data2
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
|
||||
/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S)
|
||||
#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_2_S 0
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA3_REG register
|
||||
* Represents rd_sys_part1_data3
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
|
||||
/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S)
|
||||
#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_3_S 0
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU
|
||||
#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA4_REG register
|
||||
* Represents rd_sys_part1_data4
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
|
||||
/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_RESERVED_2_128 : R; bitpos: [8:0]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
|
||||
#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_4_S 0
|
||||
#define EFUSE_RESERVED_2_128 0x000001FFU
|
||||
#define EFUSE_RESERVED_2_128_M (EFUSE_RESERVED_2_128_V << EFUSE_RESERVED_2_128_S)
|
||||
#define EFUSE_RESERVED_2_128_V 0x000001FFU
|
||||
#define EFUSE_RESERVED_2_128_S 0
|
||||
/** EFUSE_OCODE : R; bitpos: [16:9]; default: 0;
|
||||
* ADC OCode
|
||||
*/
|
||||
#define EFUSE_OCODE 0x000000FFU
|
||||
#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S)
|
||||
#define EFUSE_OCODE_V 0x000000FFU
|
||||
#define EFUSE_OCODE_S 9
|
||||
/** EFUSE_RESERVED_2_145 : R; bitpos: [31:17]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_2_145 0x00007FFFU
|
||||
#define EFUSE_RESERVED_2_145_M (EFUSE_RESERVED_2_145_V << EFUSE_RESERVED_2_145_S)
|
||||
#define EFUSE_RESERVED_2_145_V 0x00007FFFU
|
||||
#define EFUSE_RESERVED_2_145_S 17
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA5_REG register
|
||||
* Represents rd_sys_part1_data5
|
||||
@@ -2259,7 +2364,7 @@ extern "C" {
|
||||
#define EFUSE_CLK_EN_S 16
|
||||
|
||||
/** EFUSE_CONF_REG register
|
||||
* eFuse operation mode configuraiton register
|
||||
* eFuse operation mode configuration register
|
||||
*/
|
||||
#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
|
||||
/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
|
||||
|
||||
@@ -241,11 +241,11 @@ typedef union {
|
||||
*/
|
||||
uint32_t dis_download_manual_encrypt:1;
|
||||
/** usb_drefh : RO; bitpos: [22:21]; default: 0;
|
||||
* Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
|
||||
* Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
|
||||
*/
|
||||
uint32_t usb_drefh:2;
|
||||
/** usb_drefl : RO; bitpos: [24:23]; default: 0;
|
||||
* Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
|
||||
* Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
|
||||
*/
|
||||
uint32_t usb_drefl:2;
|
||||
/** usb_exchg_pins : RO; bitpos: [25]; default: 0;
|
||||
@@ -546,14 +546,58 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** mac_reserved_0 : RO; bitpos: [13:0]; default: 0;
|
||||
* Reserved.
|
||||
/** wafer_version_minor : R; bitpos: [3:0]; default: 0;
|
||||
* Minor chip version
|
||||
*/
|
||||
uint32_t mac_reserved_0:14;
|
||||
/** mac_reserved_1 : RO; bitpos: [31:14]; default: 0;
|
||||
* Reserved.
|
||||
uint32_t wafer_version_minor:4;
|
||||
/** wafer_version_major : R; bitpos: [5:4]; default: 0;
|
||||
* Minor chip version
|
||||
*/
|
||||
uint32_t mac_reserved_1:18;
|
||||
uint32_t wafer_version_major:2;
|
||||
/** disable_wafer_version_major : R; bitpos: [6]; default: 0;
|
||||
* Disables check of wafer version major
|
||||
*/
|
||||
uint32_t disable_wafer_version_major:1;
|
||||
/** disable_blk_version_major : R; bitpos: [7]; default: 0;
|
||||
* Disables check of blk version major
|
||||
*/
|
||||
uint32_t disable_blk_version_major:1;
|
||||
/** blk_version_minor : R; bitpos: [10:8]; default: 0;
|
||||
* BLK_VERSION_MINOR of BLOCK2
|
||||
*/
|
||||
uint32_t blk_version_minor:3;
|
||||
/** blk_version_major : R; bitpos: [12:11]; default: 0;
|
||||
* BLK_VERSION_MAJOR of BLOCK2
|
||||
*/
|
||||
uint32_t blk_version_major:2;
|
||||
/** flash_cap : R; bitpos: [15:13]; default: 0;
|
||||
* Flash capacity
|
||||
*/
|
||||
uint32_t flash_cap:3;
|
||||
/** flash_vendor : R; bitpos: [18:16]; default: 0;
|
||||
* Flash vendor
|
||||
*/
|
||||
uint32_t flash_vendor:3;
|
||||
/** psram_cap : R; bitpos: [21:19]; default: 0;
|
||||
* Psram capacity
|
||||
*/
|
||||
uint32_t psram_cap:3;
|
||||
/** psram_vendor : R; bitpos: [23:22]; default: 0;
|
||||
* Psram vendor
|
||||
*/
|
||||
uint32_t psram_vendor:2;
|
||||
/** temp : R; bitpos: [25:24]; default: 0;
|
||||
* Temp (die embedded inside)
|
||||
*/
|
||||
uint32_t temp:2;
|
||||
/** pkg_version : R; bitpos: [28:26]; default: 0;
|
||||
* Package version
|
||||
*/
|
||||
uint32_t pkg_version:3;
|
||||
/** pa_trim_version : R; bitpos: [31:29]; default: 0;
|
||||
* PADC CAL PA trim version
|
||||
*/
|
||||
uint32_t pa_trim_version:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_mac_sys2_reg_t;
|
||||
@@ -563,10 +607,18 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** mac_reserved_2 : RO; bitpos: [17:0]; default: 0;
|
||||
* Reserved.
|
||||
/** trim_n_bias : R; bitpos: [4:0]; default: 0;
|
||||
* PADC CAL N bias
|
||||
*/
|
||||
uint32_t mac_reserved_2:18;
|
||||
uint32_t trim_n_bias:5;
|
||||
/** trim_p_bias : R; bitpos: [9:5]; default: 0;
|
||||
* PADC CAL P bias
|
||||
*/
|
||||
uint32_t trim_p_bias:5;
|
||||
/** reserved_1_106 : R; bitpos: [17:10]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_1_106:8;
|
||||
/** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
|
||||
* Represents the first 14-bit of zeroth part of system data.
|
||||
*/
|
||||
@@ -608,10 +660,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** optional_unique_id : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
uint32_t sys_data_part1_0:32;
|
||||
uint32_t optional_unique_id:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data0_reg_t;
|
||||
@@ -621,10 +673,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
uint32_t sys_data_part1_1:32;
|
||||
uint32_t optional_unique_id_1:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data1_reg_t;
|
||||
@@ -634,10 +686,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
uint32_t sys_data_part1_2:32;
|
||||
uint32_t optional_unique_id_2:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data2_reg_t;
|
||||
@@ -647,10 +699,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
|
||||
* Optional unique 128-bit ID
|
||||
*/
|
||||
uint32_t sys_data_part1_3:32;
|
||||
uint32_t optional_unique_id_3:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data3_reg_t;
|
||||
@@ -660,10 +712,18 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** reserved_2_128 : R; bitpos: [8:0]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t sys_data_part1_4:32;
|
||||
uint32_t reserved_2_128:9;
|
||||
/** ocode : R; bitpos: [16:9]; default: 0;
|
||||
* ADC OCode
|
||||
*/
|
||||
uint32_t ocode:8;
|
||||
/** reserved_2_145 : R; bitpos: [31:17]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_2_145:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data4_reg_t;
|
||||
@@ -2013,7 +2073,7 @@ typedef union {
|
||||
|
||||
/** Group: EFUSE Configure Registers */
|
||||
/** Type of conf register
|
||||
* eFuse operation mode configuraiton register
|
||||
* eFuse operation mode configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
@@ -4229,7 +4289,7 @@ typedef union {
|
||||
} efuse_apb2otp_blk10_w10_reg_t;
|
||||
|
||||
|
||||
/** Group: EFUSE_APB2OTP Function Enable Singal */
|
||||
/** Group: EFUSE_APB2OTP Function Enable Signal */
|
||||
/** Type of apb2otp_en register
|
||||
* eFuse apb2otp enable configuration register.
|
||||
*/
|
||||
|
||||
Reference in New Issue
Block a user