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efuse: Fix make/cmake build systems and docs
This commit is contained in:
Konstantin Kondrashov
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b8141f3ad8
@@ -32,7 +32,7 @@ The component has API functions for reading and writing fields. Access to the fi
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CSV files:
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* common (`esp_efuse_table.csv`) - contains efuse fields are used inside the IDF field. C-source generation should be done manually when changing this file (run command 'make efuse_common_table' or `idf.py efuse_common_table`). Note that changes to this file can lead to incorrect IDF operation. Changes are not desirable!
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* custom - (may be absent, selected through :envvar:`CONFIG_EFUSE_CUSTOM_TABLE`) contains efuse fields that are used by the user in their application. C-source generation will be done automatically when changing this file.
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* custom - (may be absent, selected through :envvar:`CONFIG_EFUSE_CUSTOM_TABLE`) contains efuse fields that are used by the user in their application. C-source generation should be done manually when changing this file (run command 'make efuse_custom_table' or `idf.py efuse_custom_table`).
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Description CSV file
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@@ -49,7 +49,7 @@ Table header:
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Individual params in csv file the following meanings:
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field_name
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Name of field. The prefix `ESP_EFUSE_` will be added to the name, and this field name will be available in the code. This name will be used to access the fields. The name must be unique for all fields. If the line has an empty name, then this line is combined with the previous field. This allows you to set an arbitrary order of bits in the field, and expand the field as well.
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Name of field. The prefix `ESP_EFUSE_` will be added to the name, and this field name will be available in the code. This name will be used to access the fields. The name must be unique for all fields. If the line has an empty name, then this line is combined with the previous field. This allows you to set an arbitrary order of bits in the field, and expand the field as well (see ``MAC_FACTORY`` field in the common table).
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efuse_block
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Block number. It determines where the efuse bits will be placed for this field. Available EFUSE_BLK0..EFUSE_BLK3.
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@@ -87,7 +87,8 @@ The tool is designed to generate C-source files from CSV file and validate field
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To generate a `common` files, use the following command 'make efuse_common_table' or `idf.py efuse_common_table` or:
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::
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cd ~/esp/esp-idf/components/efuse/
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./efuse_table_gen.py esp32/esp_efuse_table.csv
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After generation in the folder `esp32` create:
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@@ -95,10 +96,11 @@ After generation in the folder `esp32` create:
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* `esp_efuse_table.c` file.
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* In `include` folder `esp_efuse_table.c` file.
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To generate custom files, you need to build the project, the build system tracks changes in the csv file and starts the regeneration of the C-source files itself. In this case, the tool will be called with the following parameters:
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To generate a `custom` files, use the following command 'make efuse_custom_table' or `idf.py efuse_custom_table` or:
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::
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cd ~/esp/esp-idf/components/efuse/
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./efuse_table_gen.py esp32/esp_efuse_table.csv PROJECT_PATH/main/esp_efuse_custom_table.csv
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After generation in the folder PROJECT_PATH/main create:
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@@ -113,6 +115,37 @@ To use the generated fields, you need to include two files:
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#include "esp_efuse.h"
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#include "esp_efuse_table.h" or "esp_efuse_custom_table.h"
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Support coding scheme
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---------------------
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eFuse have three coding schemes:
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* ``None`` (value 0).
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* ``3/4`` (value 1).
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* ``Repeat`` (value 2).
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The coding scheme affects only EFUSE_BLK1, EFUSE_BLK2 and EFUSE_BLK3 blocks. EUSE_BLK0 block always has a coding scheme ``None``.
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Coding changes the number of bits that can be written into a block, the block length is constant 256, some of these bits are used for encoding and are not used.
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When using a coding scheme, the length of the payload that can be written is limited (for more detailes ``20.3.1.3 System Parameter coding_scheme``):
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* None 256 bits.
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* 3/4 192 bits.
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* Repeat 128 bits.
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You can find out the coding scheme of your chip:
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* run a ``espefuse.py -p COM4 summary`` command.
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* from ``esptool`` utility logs (during flashing).
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* calling the function in the code :cpp:func:`esp_efuse_get_coding_scheme` for the EFUSE_BLK3 block.
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eFuse tables must always comply with the coding scheme in the chip. There is an :envvar:`EFUSE_CODE_SCHEME_SELECTOR` option to select the coding type for tables in a Kconfig. When generating source files, if your tables do not follow the coding scheme, an error message will be displayed. Adjust the length or offset fields.
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If your program was compiled with ``None`` encoding and ``3/4`` is used in the chip, then the ``ESP_ERR_CODING`` error may occur when calling the efuse API (the field is outside the block boundaries). If the field matches the new block boundaries, then the API will work without errors.
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Also, 3/4 coding scheme imposes restrictions on writing bits belonging to one coding unit. The whole block with a length of 256 bits is divided into 4 coding units, and in each coding unit there are 6 bytes of useful data and 2 service bytes. These 2 service bytes contain the checksum of the previous 6 data bytes.
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It turns out that only one field can be written into one coding unit. Repeated rewriting in one coding unit is prohibited. But if the record was made in advance or through a :cpp:func:`esp_efuse_write_block` function, then reading the fields belonging to one coding unit is possible.
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eFuse API
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---------
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@@ -124,6 +157,10 @@ Access to the fields is via a pointer to the description structure. API function
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* :cpp:func:`esp_efuse_write_field_cnt` - writes a required count of bits as "1".
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* :cpp:func:`esp_efuse_get_field_size` - returns the number of bits by the field name.
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* :cpp:func:`esp_efuse_read_reg` - returns value of efuse register.
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* :cpp:func:`esp_efuse_write_reg` - writes value to efuse register.
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* :cpp:func:`esp_efuse_get_coding_scheme` - returns efuse coding scheme for blocks.
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* :cpp:func:`esp_efuse_read_block` - reads key to efuse block starting at the offset and the required size.
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* :cpp:func:`esp_efuse_write_block` - writes key to efuse block starting at the offset and the required size.
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For frequently used fields, special functions are made, like this :cpp:func:`esp_efuse_get_chip_ver`, :cpp:func:`esp_efuse_get_pkg_ver`.
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@@ -131,53 +168,55 @@ For frequently used fields, special functions are made, like this :cpp:func:`esp
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How add a new field
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-------------------
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1. Find a free bits for field. Show `efuse_table.csv` file or run the next command:
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1. Find a free bits for field. Show `esp_efuse_table.csv` file or run ``make show_efuse_table`` or ``idf.py show_efuse_table`` or the next command:
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::
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$ ./efuse_table_gen.py --info esp32/esp_efuse_table.csv
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Sorted efuse table:
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#1 WR_DIS_FLASH_CRYPT_CNT EFUSE_BLK0 2 1
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#2 WR_DIS_BLK1 EFUSE_BLK0 7 1
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#3 WR_DIS_BLK2 EFUSE_BLK0 8 1
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#4 WR_DIS_BLK3 EFUSE_BLK0 9 1
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#5 RD_DIS_BLK1 EFUSE_BLK0 16 1
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#6 RD_DIS_BLK2 EFUSE_BLK0 17 1
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#7 RD_DIS_BLK3 EFUSE_BLK0 18 1
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#8 FLASH_CRYPT_CNT EFUSE_BLK0 20 8
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#9 MAC_FACTORY EFUSE_BLK0 32 8
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#10 MAC_FACTORY EFUSE_BLK0 40 8
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#11 MAC_FACTORY EFUSE_BLK0 48 8
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#12 MAC_FACTORY EFUSE_BLK0 56 8
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#13 MAC_FACTORY EFUSE_BLK0 64 8
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#14 MAC_FACTORY EFUSE_BLK0 72 8
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#15 MAC_FACTORY_CRC EFUSE_BLK0 80 8
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#16 CHIP_VER_DIS_APP_CPU EFUSE_BLK0 96 1
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#17 CHIP_VER_DIS_BT EFUSE_BLK0 97 1
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#18 CHIP_VER_PKG EFUSE_BLK0 105 3
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#19 CHIP_CPU_FREQ_LOW EFUSE_BLK0 108 1
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#20 CHIP_CPU_FREQ_RATED EFUSE_BLK0 109 1
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#21 CHIP_VER_REV1 EFUSE_BLK0 111 1
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#22 ADC_VREF_AND_SDIO_DREF EFUSE_BLK0 136 6
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#23 XPD_SDIO_REG EFUSE_BLK0 142 1
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#24 SDIO_TIEH EFUSE_BLK0 143 1
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#25 SDIO_FORCE EFUSE_BLK0 144 1
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#26 ENCRYPT_CONFIG EFUSE_BLK0 188 4
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#27 CONSOLE_DEBUG_DISABLE EFUSE_BLK0 194 1
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#28 ABS_DONE_0 EFUSE_BLK0 196 1
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#29 DISABLE_JTAG EFUSE_BLK0 198 1
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#30 DISABLE_DL_ENCRYPT EFUSE_BLK0 199 1
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#31 DISABLE_DL_DECRYPT EFUSE_BLK0 200 1
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#32 DISABLE_DL_CACHE EFUSE_BLK0 201 1
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#33 ENCRYPT_FLASH_KEY EFUSE_BLK1 0 256
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#34 SECURE_BOOT_KEY EFUSE_BLK2 0 256
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#35 MAC_CUSTOM_CRC EFUSE_BLK3 0 8
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#36 MAC_CUSTOM EFUSE_BLK3 8 48
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#37 ADC1_TP_LOW EFUSE_BLK3 96 7
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#38 ADC1_TP_HIGH EFUSE_BLK3 103 9
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#39 ADC2_TP_LOW EFUSE_BLK3 112 7
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#40 ADC2_TP_HIGH EFUSE_BLK3 119 9
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#41 MAC_CUSTOM_VER EFUSE_BLK3 184 8
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eFuse coding scheme: NONE
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# field_name efuse_block bit_start bit_count
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1 WR_DIS_FLASH_CRYPT_CNT EFUSE_BLK0 2 1
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2 WR_DIS_BLK1 EFUSE_BLK0 7 1
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3 WR_DIS_BLK2 EFUSE_BLK0 8 1
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4 WR_DIS_BLK3 EFUSE_BLK0 9 1
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5 RD_DIS_BLK1 EFUSE_BLK0 16 1
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6 RD_DIS_BLK2 EFUSE_BLK0 17 1
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7 RD_DIS_BLK3 EFUSE_BLK0 18 1
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8 FLASH_CRYPT_CNT EFUSE_BLK0 20 8
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9 MAC_FACTORY EFUSE_BLK0 32 8
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10 MAC_FACTORY EFUSE_BLK0 40 8
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11 MAC_FACTORY EFUSE_BLK0 48 8
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12 MAC_FACTORY EFUSE_BLK0 56 8
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13 MAC_FACTORY EFUSE_BLK0 64 8
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14 MAC_FACTORY EFUSE_BLK0 72 8
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15 MAC_FACTORY_CRC EFUSE_BLK0 80 8
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16 CHIP_VER_DIS_APP_CPU EFUSE_BLK0 96 1
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17 CHIP_VER_DIS_BT EFUSE_BLK0 97 1
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18 CHIP_VER_PKG EFUSE_BLK0 105 3
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19 CHIP_CPU_FREQ_LOW EFUSE_BLK0 108 1
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20 CHIP_CPU_FREQ_RATED EFUSE_BLK0 109 1
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21 CHIP_VER_REV1 EFUSE_BLK0 111 1
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22 ADC_VREF_AND_SDIO_DREF EFUSE_BLK0 136 6
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23 XPD_SDIO_REG EFUSE_BLK0 142 1
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24 SDIO_TIEH EFUSE_BLK0 143 1
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25 SDIO_FORCE EFUSE_BLK0 144 1
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26 ENCRYPT_CONFIG EFUSE_BLK0 188 4
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27 CONSOLE_DEBUG_DISABLE EFUSE_BLK0 194 1
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28 ABS_DONE_0 EFUSE_BLK0 196 1
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29 DISABLE_JTAG EFUSE_BLK0 198 1
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30 DISABLE_DL_ENCRYPT EFUSE_BLK0 199 1
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31 DISABLE_DL_DECRYPT EFUSE_BLK0 200 1
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32 DISABLE_DL_CACHE EFUSE_BLK0 201 1
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33 ENCRYPT_FLASH_KEY EFUSE_BLK1 0 256
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34 SECURE_BOOT_KEY EFUSE_BLK2 0 256
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35 MAC_CUSTOM_CRC EFUSE_BLK3 0 8
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36 MAC_CUSTOM EFUSE_BLK3 8 48
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37 ADC1_TP_LOW EFUSE_BLK3 96 7
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38 ADC1_TP_HIGH EFUSE_BLK3 103 9
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39 ADC2_TP_LOW EFUSE_BLK3 112 7
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40 ADC2_TP_HIGH EFUSE_BLK3 119 9
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41 SECURE_VERSION EFUSE_BLK3 128 32
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42 MAC_CUSTOM_VER EFUSE_BLK3 184 8
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Used bits in efuse table:
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EFUSE_BLK0
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@@ -190,18 +229,19 @@ How add a new field
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[0 255]
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EFUSE_BLK3
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[0 55] [96 127] [184 191]
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[0 55] [96 159] [184 191]
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Note: Not printed ranges are free for using.
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Note: Not printed ranges are free for using. (bits in EFUSE_BLK0 are reserved for Espressif)
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Parsing efuse CSV input file esp32/esp_efuse_table.csv ...
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Parsing efuse CSV input file C:/msys32/home/virtpc/esp/esp-idf/components/efuse/esp32/esp_efuse_table.csv ...
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Verifying efuse table...
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The number of bits not included in square brackets is free. All fields are checked for overlapping.
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The number of bits not included in square brackets is free (bits in EFUSE_BLK0 are reserved for Espressif). All fields are checked for overlapping.
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2. Fill a line for field: field_name, efuse_block, bit_start, bit_count, comment.
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3. Run a command `make show_efuse_table` to check and generate header file.
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3. Run a ``show_efuse_table`` command to check efuse table. To generate source files run ``efuse_common_table`` or ``efuse_custom_table`` command.
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Debug efuse & Unit tests
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------------------------
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@@ -213,13 +253,13 @@ esptool have an useful tool for reading/writing ESP32 efuse bits - `espefuse.py
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::
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espefuse.py -p COM4 summary
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espefuse.py v2.3.1
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Connecting........_
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Security fuses:
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FLASH_CRYPT_CNT Flash encryption mode counter = 0 R/W (0x4)
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FLASH_CRYPT_CNT Flash encryption mode counter = 0 R/W (0x0)
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FLASH_CRYPT_CONFIG Flash encryption config (key tweak bits) = 0 R/W (0x0)
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CONSOLE_DEBUG_DISABLE Disable ROM BASIC interpreter fallback = 0 R/W (0x0)
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CONSOLE_DEBUG_DISABLE Disable ROM BASIC interpreter fallback = 1 R/W (0x1)
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ABS_DONE_0 secure boot enabled for bootloader = 0 R/W (0x0)
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ABS_DONE_1 secure boot abstract 1 locked = 0 R/W (0x0)
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JTAG_DISABLE Disable JTAG = 0 R/W (0x0)
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@@ -231,12 +271,12 @@ esptool have an useful tool for reading/writing ESP32 efuse bits - `espefuse.py
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BLK2 Secure boot key
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= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
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BLK3 Variable Block 3
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= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
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= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fa 87 02 91 00 00 00 00 00 00 00 00 00 00 00 00 R/W
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Efuse fuses:
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WR_DIS Efuse write disable mask = 0 R/W (0x0)
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RD_DIS Efuse read disablemask = 0 R/W (0x0)
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CODING_SCHEME Efuse variable block length scheme = 0 R/W (0x0)
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CODING_SCHEME Efuse variable block length scheme = 1 R/W (0x1) (3/4)
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KEY_STATUS Usage of efuse block 3 (reserved) = 0 R/W (0x0)
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Config fuses:
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@@ -252,14 +292,18 @@ esptool have an useful tool for reading/writing ESP32 efuse bits - `espefuse.py
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Identity fuses:
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MAC MAC Address
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= 24:0a:c4:03:bb:68 (CRC 82 OK) R/W
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CHIP_VER_REV1 Silicon Revision 1 = 0 R/W (0x0)
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CHIP_VERSION Reserved for future chip versions = 0 R/W (0x0)
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= 84:0d:8e:18:8e:44 (CRC ad OK) R/W
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CHIP_VER_REV1 Silicon Revision 1 = 1 R/W (0x1)
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CHIP_VERSION Reserved for future chip versions = 2 R/W (0x2)
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CHIP_PACKAGE Chip package identifier = 0 R/W (0x0)
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Calibration fuses:
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BLK3_PART_RESERVE BLOCK3 partially served for ADC calibration data = 0 R/W (0x0)
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ADC_VREF Voltage reference calibration = 1100 R/W (0x0)
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BLK3_PART_RESERVE BLOCK3 partially served for ADC calibration data = 1 R/W (0x1)
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ADC_VREF Voltage reference calibration = 1114 R/W (0x2)
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ADC1_TP_LOW ADC1 150mV reading = 346 R/W (0x11)
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ADC1_TP_HIGH ADC1 850mV reading = 3285 R/W (0x5)
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ADC2_TP_LOW ADC2 150mV reading = 449 R/W (0x7)
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ADC2_TP_HIGH ADC2 850mV reading = 3362 R/W (0x1f5)
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Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V).
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