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https://github.com/espressif/esp-idf.git
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Merge branch 'fix/fix_ota_slowclock_switching_v5.3' into 'release/v5.3'
fix(esp_hw_support): fix rtc slow clock missing after the OTA app changes the slow clock source (v5.3) See merge request espressif/esp-idf!34474
This commit is contained in:
@ -367,21 +367,14 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
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/** LP system default parameter */
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/** LP system default parameter */
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#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
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# define PMU_SLOW_CLK_USE_EXT_XTAL (1)
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#else
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# define PMU_SLOW_CLK_USE_EXT_XTAL (0)
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#endif
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#define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
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#define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
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.dig_power = { \
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.dig_power = { \
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.mem_dslp = 0, \
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.mem_dslp = 0, \
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.peri_pd_en = 0, \
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.peri_pd_en = 0, \
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}, \
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}, \
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.clk_power = { \
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.clk_power = { \
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.xpd_xtal32k = PMU_SLOW_CLK_USE_EXT_XTAL, \
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.xpd_xtal32k = 1, \
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.xpd_rc32k = 0, \
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.xpd_rc32k = 1, \
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.xpd_fosc = 1, \
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.xpd_fosc = 1, \
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.pd_osc = 0 \
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.pd_osc = 0 \
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} \
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} \
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@ -366,21 +366,14 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
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/** LP system default parameter */
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/** LP system default parameter */
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#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
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# define PMU_SLOW_CLK_USE_EXT_XTAL (1)
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#else
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# define PMU_SLOW_CLK_USE_EXT_XTAL (0)
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#endif
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#define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
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#define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
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.dig_power = { \
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.dig_power = { \
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.mem_dslp = 0, \
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.mem_dslp = 0, \
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.peri_pd_en = 0, \
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.peri_pd_en = 0, \
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}, \
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}, \
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.clk_power = { \
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.clk_power = { \
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.xpd_xtal32k = PMU_SLOW_CLK_USE_EXT_XTAL, \
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.xpd_xtal32k = 1, \
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.xpd_rc32k = 0, \
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.xpd_rc32k = 1, \
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.xpd_fosc = 1, \
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.xpd_fosc = 1, \
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.pd_osc = 0 \
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.pd_osc = 0 \
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} \
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} \
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@ -178,6 +178,12 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
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}
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}
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rtc_clk_slow_src_set(rtc_slow_clk_src);
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rtc_clk_slow_src_set(rtc_slow_clk_src);
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// Disable unused clock sources after clock source switching is complete.
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// Regardless of the clock source selection, the internal 136K clock source will always keep on.
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if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
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rtc_clk_32k_enable(false);
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}
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if (SLOW_CLK_CAL_CYCLES > 0) {
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if (SLOW_CLK_CAL_CYCLES > 0) {
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/* TODO: 32k XTAL oscillator has some frequency drift at startup.
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/* TODO: 32k XTAL oscillator has some frequency drift at startup.
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* Improve calibration routine to wait until the frequency is stable.
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* Improve calibration routine to wait until the frequency is stable.
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@ -185,6 +185,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
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}
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}
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rtc_clk_slow_src_set(rtc_slow_clk_src);
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rtc_clk_slow_src_set(rtc_slow_clk_src);
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// Disable unused clock sources after clock source switching is complete.
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// Regardless of the clock source selection, the internal 136K clock source will always keep on.
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if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
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rtc_clk_32k_enable(false);
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}
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if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
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rtc_clk_rc32k_enable(false);
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}
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if (SLOW_CLK_CAL_CYCLES > 0) {
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if (SLOW_CLK_CAL_CYCLES > 0) {
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/* TODO: 32k XTAL oscillator has some frequency drift at startup.
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/* TODO: 32k XTAL oscillator has some frequency drift at startup.
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* Improve calibration routine to wait until the frequency is stable.
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* Improve calibration routine to wait until the frequency is stable.
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@ -156,6 +156,12 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
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}
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}
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rtc_clk_slow_src_set(rtc_slow_clk_src);
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rtc_clk_slow_src_set(rtc_slow_clk_src);
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// Disable unused clock sources after clock source switching is complete.
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// Regardless of the clock source selection, the internal 136K clock source will always keep on.
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if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
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rtc_clk_32k_enable(false);
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}
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if (SLOW_CLK_CAL_CYCLES > 0) {
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if (SLOW_CLK_CAL_CYCLES > 0) {
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/* TODO: 32k XTAL oscillator has some frequency drift at startup.
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/* TODO: 32k XTAL oscillator has some frequency drift at startup.
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* Improve calibration routine to wait until the frequency is stable.
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* Improve calibration routine to wait until the frequency is stable.
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@ -187,6 +187,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
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}
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}
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rtc_clk_slow_src_set(rtc_slow_clk_src);
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rtc_clk_slow_src_set(rtc_slow_clk_src);
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// Disable unused clock sources after clock source switching is complete.
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// Regardless of the clock source selection, the internal 136K clock source will always keep on.
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if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
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rtc_clk_32k_enable(false);
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}
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if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
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rtc_clk_rc32k_enable(false);
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}
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if (SLOW_CLK_CAL_CYCLES > 0) {
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if (SLOW_CLK_CAL_CYCLES > 0) {
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/* TODO: 32k XTAL oscillator has some frequency drift at startup.
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/* TODO: 32k XTAL oscillator has some frequency drift at startup.
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* Improve calibration routine to wait until the frequency is stable.
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* Improve calibration routine to wait until the frequency is stable.
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@ -151,6 +151,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
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}
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}
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rtc_clk_slow_src_set(rtc_slow_clk_src);
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rtc_clk_slow_src_set(rtc_slow_clk_src);
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// Disable unused clock sources after clock source switching is complete.
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// Regardless of the clock source selection, the internal 136K clock source will always keep on.
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if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
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rtc_clk_32k_enable(false);
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}
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if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
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rtc_clk_rc32k_enable(false);
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}
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if (SLOW_CLK_CAL_CYCLES > 0) {
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if (SLOW_CLK_CAL_CYCLES > 0) {
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/* TODO: 32k XTAL oscillator has some frequency drift at startup.
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/* TODO: 32k XTAL oscillator has some frequency drift at startup.
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* Improve calibration routine to wait until the frequency is stable.
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* Improve calibration routine to wait until the frequency is stable.
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