Merge branch 'fix/fix_ota_slowclock_switching_v5.3' into 'release/v5.3'

fix(esp_hw_support): fix rtc slow clock missing after the OTA app changes the slow clock source (v5.3)

See merge request espressif/esp-idf!34474
This commit is contained in:
Jiang Jiang Jian
2024-11-08 16:34:22 +08:00
7 changed files with 43 additions and 18 deletions

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@ -367,21 +367,14 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
/** LP system default parameter */ /** LP system default parameter */
#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
# define PMU_SLOW_CLK_USE_EXT_XTAL (1)
#else
# define PMU_SLOW_CLK_USE_EXT_XTAL (0)
#endif
#define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \ #define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
.dig_power = { \ .dig_power = { \
.mem_dslp = 0, \ .mem_dslp = 0, \
.peri_pd_en = 0, \ .peri_pd_en = 0, \
}, \ }, \
.clk_power = { \ .clk_power = { \
.xpd_xtal32k = PMU_SLOW_CLK_USE_EXT_XTAL, \ .xpd_xtal32k = 1, \
.xpd_rc32k = 0, \ .xpd_rc32k = 1, \
.xpd_fosc = 1, \ .xpd_fosc = 1, \
.pd_osc = 0 \ .pd_osc = 0 \
} \ } \

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@ -366,21 +366,14 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
/** LP system default parameter */ /** LP system default parameter */
#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
# define PMU_SLOW_CLK_USE_EXT_XTAL (1)
#else
# define PMU_SLOW_CLK_USE_EXT_XTAL (0)
#endif
#define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \ #define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
.dig_power = { \ .dig_power = { \
.mem_dslp = 0, \ .mem_dslp = 0, \
.peri_pd_en = 0, \ .peri_pd_en = 0, \
}, \ }, \
.clk_power = { \ .clk_power = { \
.xpd_xtal32k = PMU_SLOW_CLK_USE_EXT_XTAL, \ .xpd_xtal32k = 1, \
.xpd_rc32k = 0, \ .xpd_rc32k = 1, \
.xpd_fosc = 1, \ .xpd_fosc = 1, \
.pd_osc = 0 \ .pd_osc = 0 \
} \ } \

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@ -178,6 +178,12 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
} }
rtc_clk_slow_src_set(rtc_slow_clk_src); rtc_clk_slow_src_set(rtc_slow_clk_src);
// Disable unused clock sources after clock source switching is complete.
// Regardless of the clock source selection, the internal 136K clock source will always keep on.
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
rtc_clk_32k_enable(false);
}
if (SLOW_CLK_CAL_CYCLES > 0) { if (SLOW_CLK_CAL_CYCLES > 0) {
/* TODO: 32k XTAL oscillator has some frequency drift at startup. /* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable. * Improve calibration routine to wait until the frequency is stable.

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@ -185,6 +185,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
} }
rtc_clk_slow_src_set(rtc_slow_clk_src); rtc_clk_slow_src_set(rtc_slow_clk_src);
// Disable unused clock sources after clock source switching is complete.
// Regardless of the clock source selection, the internal 136K clock source will always keep on.
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
rtc_clk_32k_enable(false);
}
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
rtc_clk_rc32k_enable(false);
}
if (SLOW_CLK_CAL_CYCLES > 0) { if (SLOW_CLK_CAL_CYCLES > 0) {
/* TODO: 32k XTAL oscillator has some frequency drift at startup. /* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable. * Improve calibration routine to wait until the frequency is stable.

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@ -156,6 +156,12 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
} }
rtc_clk_slow_src_set(rtc_slow_clk_src); rtc_clk_slow_src_set(rtc_slow_clk_src);
// Disable unused clock sources after clock source switching is complete.
// Regardless of the clock source selection, the internal 136K clock source will always keep on.
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
rtc_clk_32k_enable(false);
}
if (SLOW_CLK_CAL_CYCLES > 0) { if (SLOW_CLK_CAL_CYCLES > 0) {
/* TODO: 32k XTAL oscillator has some frequency drift at startup. /* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable. * Improve calibration routine to wait until the frequency is stable.

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@ -187,6 +187,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
} }
rtc_clk_slow_src_set(rtc_slow_clk_src); rtc_clk_slow_src_set(rtc_slow_clk_src);
// Disable unused clock sources after clock source switching is complete.
// Regardless of the clock source selection, the internal 136K clock source will always keep on.
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
rtc_clk_32k_enable(false);
}
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
rtc_clk_rc32k_enable(false);
}
if (SLOW_CLK_CAL_CYCLES > 0) { if (SLOW_CLK_CAL_CYCLES > 0) {
/* TODO: 32k XTAL oscillator has some frequency drift at startup. /* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable. * Improve calibration routine to wait until the frequency is stable.

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@ -151,6 +151,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
} }
rtc_clk_slow_src_set(rtc_slow_clk_src); rtc_clk_slow_src_set(rtc_slow_clk_src);
// Disable unused clock sources after clock source switching is complete.
// Regardless of the clock source selection, the internal 136K clock source will always keep on.
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(false);
}
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
rtc_clk_rc32k_enable(false);
}
if (SLOW_CLK_CAL_CYCLES > 0) { if (SLOW_CLK_CAL_CYCLES > 0) {
/* TODO: 32k XTAL oscillator has some frequency drift at startup. /* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable. * Improve calibration routine to wait until the frequency is stable.