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Merge branch 'bugfix/rtcio_increase_size' into 'master'

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sleep: fixed ext1 cannot wakeup via RTCIO >= 18 issue

Closes IDF-4526 and IDF-4505

See merge request espressif/esp-idf!16617
This commit is contained in:
Michael (XIAO Xufeng)
2022-01-06 03:03:58 +00:00
parent d29755b7d5 46f8d868d3
commit b84abb1b17
7 changed files with 34 additions and 10 deletions
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5
components/esp_hw_support/sleep_modes.c
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@@ -143,7 +143,7 @@ typedef struct {
uint64_t sleep_duration;
uint32_t wakeup_triggers : 15;
uint32_t ext1_trigger_mode : 1;
uint32_t ext1_rtc_gpio_mask : 18;
uint32_t ext1_rtc_gpio_mask : 22; //22 is the maximum RTCIO number in all chips
uint32_t ext0_trigger_level : 1;
uint32_t ext0_rtc_gpio_num : 5;
uint32_t gpio_wakeup_mask : 6;
@@ -155,6 +155,9 @@ typedef struct {
uint64_t rtc_ticks_at_sleep_start;
} sleep_config_t;
_Static_assert(22 >= SOC_RTCIO_PIN_COUNT, "Chip has more RTCIOs than 22, should increase ext1_rtc_gpio_mask field size");
static sleep_config_t s_config = {
.pd_options = {
ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO,

4
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
View File

@@ -388,8 +388,8 @@ config SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM
default 108
config SOC_RTCIO_PIN_COUNT
bool
default n
int
default 0
config SOC_RSA_MAX_BIT_LEN
int

2
components/soc/esp32c3/include/soc/soc_caps.h
View File

@@ -193,7 +193,7 @@
/*-------------------------- RTCIO CAPS --------------------------------------*/
/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported
* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
#define SOC_RTCIO_PIN_COUNT 0
#define SOC_RTCIO_PIN_COUNT (0U)
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (3072)

4
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@@ -368,8 +368,8 @@ config SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM
default 108
config SOC_RTCIO_PIN_COUNT
bool
default n
int
default 0
config SOC_RSA_MAX_BIT_LEN
int

2
components/soc/esp32h2/include/soc/soc_caps.h
View File

@@ -187,7 +187,7 @@
/*-------------------------- RTCIO CAPS --------------------------------------*/
/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported
* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
#define SOC_RTCIO_PIN_COUNT 0
#define SOC_RTCIO_PIN_COUNT (0U)
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (3072)

4
components/soc/esp8684/include/soc/Kconfig.soc_caps.in
View File

@@ -279,6 +279,10 @@ config SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM
int
default 108
config SOC_RTCIO_PIN_COUNT
int
default 0
config SOC_RSA_MAX_BIT_LEN
int
default 3072

23
components/soc/esp8684/include/soc/soc_caps.h
View File

@@ -3,13 +3,28 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
// The long term plan is to have a single soc_caps.h for each peripheral.
// During the refactoring and multichip support development process, we
// seperate these information into periph_caps.h for each peripheral and
// include them here.
/*
* These defines are parsed and imported as kconfig variables via the script
* `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
*
* If this file is changed the script will automatically run the script
* and generate the kconfig variables as part of the pre-commit hooks.
*
* It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32c3/include/soc/'`
*
* For more information see `tools/gen_soc_caps_kconfig/README.md`
*
*/
#pragma once
/*-------------------------- COMMON CAPS ---------------------------------------*/
#define SOC_CPU_CORES_NUM 1
#define SOC_ADC_SUPPORTED 1
#define SOC_DEDICATED_GPIO_SUPPORTED 1
@@ -17,8 +32,6 @@
#define SOC_BT_SUPPORTED 0 // Enable during bringup, IDF-4357
#define SOC_WIFI_SUPPORTED 0 // Enable during bringup, IDF-3905
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
/*-------------------------- COMMON CAPS ---------------------------------------*/
#define SOC_SUPPORTS_SECURE_DL_MODE 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
@@ -144,6 +157,11 @@
#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
/*-------------------------- RTCIO CAPS --------------------------------------*/
/* No dedicated RTCIO subsystem on ESP8684. RTC functions are still supported
* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
#define SOC_RTCIO_PIN_COUNT (0U)
/*--------------------------- RSA CAPS ---------------------------------------*/
#define SOC_RSA_MAX_BIT_LEN (3072)
@@ -227,7 +245,6 @@
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP8684 has 2 UARTs
#define SOC_UART_NUM (2)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */