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esp_system: support esp32c2 reset reason

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This commit is contained in:
songruojing
2022-02-15 12:07:43 +08:00
parent 2522277dfe
commit b860fa96e0
6 changed files with 45 additions and 56 deletions
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23
components/esp_rom/include/esp32c2/rom/rtc.h
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@@ -14,6 +14,7 @@
#include "soc/soc.h" #include "soc/soc.h"
#include "soc/rtc_cntl_reg.h" #include "soc/rtc_cntl_reg.h"
#include "soc/reset_reasons.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@@ -77,9 +78,7 @@ typedef enum {
POWERON_RESET = 1, /**<1, Vbat power on reset*/ POWERON_RESET = 1, /**<1, Vbat power on reset*/
RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core*/ RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core*/
DEEPSLEEP_RESET = 5, /**<3, Deep Sleep reset digital core*/ DEEPSLEEP_RESET = 5, /**<3, Deep Sleep reset digital core*/
SDIO_RESET = 6, /**<6, Reset by SLC module, reset digital core*/
TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/ TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/
RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/ RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/ INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/
TG0WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/ TG0WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/
@@ -87,10 +86,28 @@ typedef enum {
RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/ RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/ RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/ RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
TG1WDT_CPU_RESET = 17, /**<11, Time Group1 reset CPU*/
SUPER_WDT_RESET = 18, /**<11, super watchdog reset digital core and rtc module*/ SUPER_WDT_RESET = 18, /**<11, super watchdog reset digital core and rtc module*/
GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
EFUSE_RESET = 20, /**<20, efuse reset digital core*/
JTAG_RESET = 24, /**<24, jtag reset CPU*/
} RESET_REASON; } RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
_Static_assert((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
_Static_assert((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
_Static_assert((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
_Static_assert((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
_Static_assert((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
_Static_assert((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
_Static_assert((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
_Static_assert((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
_Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
_Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
_Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
_Static_assert((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
_Static_assert((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
_Static_assert((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU0_JTAG, "JTAG_RESET != RESET_REASON_CPU0_JTAG");
typedef enum { typedef enum {
NO_SLEEP = 0, NO_SLEEP = 0,
EXT_EVENT0_TRIG = BIT0, EXT_EVENT0_TRIG = BIT0,

19
components/esp_rom/include/esp32s2/rom/rtc.h
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@@ -1,16 +1,8 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_RTC_H_ #ifndef _ROM_RTC_H_
#define _ROM_RTC_H_ #define _ROM_RTC_H_
@@ -111,6 +103,7 @@ _Static_assert((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RT
_Static_assert((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT"); _Static_assert((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
_Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT"); _Static_assert((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
_Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT"); _Static_assert((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
_Static_assert((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
_Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT"); _Static_assert((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
_Static_assert((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH"); _Static_assert((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");

21
components/esp_system/port/soc/esp32c2/clk.c
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@@ -198,28 +198,13 @@ __attribute__((weak)) void esp_perip_clk_init(void)
uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0; uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
uint32_t common_perip_clk1 = 0; uint32_t common_perip_clk1 = 0;
#if CONFIG_FREERTOS_UNICORE soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
soc_reset_reason_t rst_reas[1];
#else
soc_reset_reason_t rst_reas[2];
#endif
rst_reas[0] = esp_rom_get_reset_reason(0);
#if !CONFIG_FREERTOS_UNICORE
rst_reas[1] = esp_rom_get_reset_reason(1);
#endif
/* For reason that only reset CPU, do not disable the clocks /* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset. * that have been enabled before reset.
*/ */
/* For reason that only reset CPU, do not disable the clocks if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW ||
* that have been enabled before reset. rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_JTAG) {
*/
if ((rst_reas[0] >= RESET_REASON_CPU0_MWDT0 && rst_reas[0] <= RESET_REASON_CPU0_RTC_WDT && rst_reas[0] != RESET_REASON_SYS_BROWN_OUT)
#if !CONFIG_FREERTOS_UNICORE
|| (rst_reas[1] >= RESET_REASON_CPU0_RTC_WDT && rst_reas[1] <= RESET_REASON_CPU0_RTC_WDT)
#endif
) {
common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG); common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG); hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG); wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG);

34
components/esp_system/port/soc/esp32c2/reset_reason.c
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@@ -5,24 +5,23 @@
*/ */
#include "esp_system.h" #include "esp_system.h"
#include "esp32c2/rom/rtc.h" #include "esp_rom_sys.h"
#include "esp_private/system_internal.h" #include "esp_private/system_internal.h"
#include "soc/rtc_periph.h" #include "soc/rtc_periph.h"
#include "esp32c2/rom/rtc.h" #include "esp32c2/rom/rtc.h"
#include "esp_rom_sys.h"
static void esp_reset_reason_clear_hint(void); static void esp_reset_reason_clear_hint(void);
static esp_reset_reason_t s_reset_reason; static esp_reset_reason_t s_reset_reason;
static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_reset_reason_t reset_reason_hint) static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, esp_reset_reason_t reset_reason_hint)
{ {
switch (rtc_reset_reason) { switch (rtc_reset_reason) {
case POWERON_RESET: case RESET_REASON_CHIP_POWER_ON:
return ESP_RST_POWERON; return ESP_RST_POWERON;
case RTC_SW_CPU_RESET: case RESET_REASON_CPU0_SW:
case RTC_SW_SYS_RESET: case RESET_REASON_CORE_SW:
if (reset_reason_hint == ESP_RST_PANIC || if (reset_reason_hint == ESP_RST_PANIC ||
reset_reason_hint == ESP_RST_BROWNOUT || reset_reason_hint == ESP_RST_BROWNOUT ||
reset_reason_hint == ESP_RST_TASK_WDT || reset_reason_hint == ESP_RST_TASK_WDT ||
@@ -31,26 +30,22 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re
} }
return ESP_RST_SW; return ESP_RST_SW;
case DEEPSLEEP_RESET: case RESET_REASON_CORE_DEEP_SLEEP:
return ESP_RST_DEEPSLEEP; return ESP_RST_DEEPSLEEP;
case TG0WDT_SYS_RESET: case RESET_REASON_CORE_MWDT0:
return ESP_RST_TASK_WDT; return ESP_RST_TASK_WDT;
case TG1WDT_SYS_RESET: case RESET_REASON_CORE_RTC_WDT:
return ESP_RST_INT_WDT; case RESET_REASON_SYS_RTC_WDT:
case RESET_REASON_SYS_SUPER_WDT:
case RTCWDT_SYS_RESET: case RESET_REASON_CPU0_RTC_WDT:
case RTCWDT_RTC_RESET: case RESET_REASON_CPU0_MWDT0:
case SUPER_WDT_RESET:
case RTCWDT_CPU_RESET: /* unused */
case TG0WDT_CPU_RESET: /* unused */
return ESP_RST_WDT; return ESP_RST_WDT;
case RTCWDT_BROWN_OUT_RESET: case RESET_REASON_SYS_BROWN_OUT:
return ESP_RST_BROWNOUT; return ESP_RST_BROWNOUT;
case INTRUSION_RESET: /* unused */
default: default:
return ESP_RST_UNKNOWN; return ESP_RST_UNKNOWN;
} }
@@ -59,8 +54,7 @@ static esp_reset_reason_t get_reset_reason(RESET_REASON rtc_reset_reason, esp_re
static void __attribute__((constructor)) esp_reset_reason_init(void) static void __attribute__((constructor)) esp_reset_reason_init(void)
{ {
esp_reset_reason_t hint = esp_reset_reason_get_hint(); esp_reset_reason_t hint = esp_reset_reason_get_hint();
s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), s_reset_reason = get_reset_reason(esp_rom_get_reset_reason(PRO_CPU_NUM), hint);
hint);
if (hint != ESP_RST_UNKNOWN) { if (hint != ESP_RST_UNKNOWN) {
esp_reset_reason_clear_hint(); esp_reset_reason_clear_hint();
} }

3
components/soc/esp32c2/include/soc/reset_reasons.h
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@@ -38,8 +38,9 @@ typedef enum {
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core
RESET_REASON_JTAG_RESET = 0x18, RESET_REASON_CPU0_JTAG = 0x18, // JTAG resets the CPU 0
} soc_reset_reason_t; } soc_reset_reason_t;

1
tools/ci/check_copyright_ignore.txt
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@@ -656,7 +656,6 @@ components/esp_rom/include/esp32s2/rom/md5_hash.h
components/esp_rom/include/esp32s2/rom/miniz.h components/esp_rom/include/esp32s2/rom/miniz.h
components/esp_rom/include/esp32s2/rom/opi_flash.h components/esp_rom/include/esp32s2/rom/opi_flash.h
components/esp_rom/include/esp32s2/rom/rsa_pss.h components/esp_rom/include/esp32s2/rom/rsa_pss.h
components/esp_rom/include/esp32s2/rom/rtc.h
components/esp_rom/include/esp32s2/rom/sha.h components/esp_rom/include/esp32s2/rom/sha.h
components/esp_rom/include/esp32s2/rom/uart.h components/esp_rom/include/esp32s2/rom/uart.h
components/esp_rom/include/esp32s2/rom/usb/cdc_acm.h components/esp_rom/include/esp32s2/rom/usb/cdc_acm.h