diff --git a/components/bootloader_support/src/bootloader_random_esp32c5.c b/components/bootloader_support/src/bootloader_random_esp32c5.c
index 0aabb1d4a8..a67deb34d9 100644
--- a/components/bootloader_support/src/bootloader_random_esp32c5.c
+++ b/components/bootloader_support/src/bootloader_random_esp32c5.c
@@ -57,8 +57,8 @@ void bootloader_random_enable(void)
 
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x08);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x66);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_MSB, 0x08);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_LSB, 0x66);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0x08);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0x66);
 
     // create patterns and set them in pattern table
     uint32_t pattern_one = (SAR2_CHANNEL << 2) | SAR2_ATTEN; // we want channel 9 with max attenuation
@@ -90,8 +90,8 @@ void bootloader_random_disable(void)
     // Revert ADC I2C configuration and initial voltage source setting
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x60);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x0);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_MSB, 0x60);
-    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_LSB, 0x0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0x60);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0x0);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_PERIF_ADDR, 0);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_EN_TOUT_ADDR, 0);
diff --git a/components/efuse/esp32c5/esp_efuse_rtc_calib.c b/components/efuse/esp32c5/esp_efuse_rtc_calib.c
index 98b6e836f3..d736107d0f 100644
--- a/components/efuse/esp32c5/esp_efuse_rtc_calib.c
+++ b/components/efuse/esp32c5/esp_efuse_rtc_calib.c
@@ -20,30 +20,129 @@
 int esp_efuse_rtc_calib_get_ver(void)
 {
     uint32_t cali_version = 0;
-    // TODO: [ESP32C5] IDF-8702
-    abort();
+    uint32_t blk_ver = efuse_hal_blk_version();
+    if ((blk_ver >= 1) && (blk_ver < 100)) {
+        cali_version = ESP_EFUSE_ADC_CALIB_VER1;
+    } else {
+        ESP_LOGW("eFuse", "calibration efuse version does not match, set default version to 0");
+    }
 
     return cali_version;
 }
 
 uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten)
 {
-    // TODO: [ESP32C5] IDF-8702
-    abort();
-    return 0;
+    /* Version validation should be guaranteed in the caller */
+    assert(atten >=0 && atten < 4);
+    assert(adc_unit == 0);
+
+    const esp_efuse_desc_t** init_code_efuse;
+    if (atten == 0) {
+        init_code_efuse = ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0;
+    } else if (atten == 1) {
+        init_code_efuse = ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1;
+    } else if (atten == 2) {
+        init_code_efuse = ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2;
+    } else {
+        init_code_efuse = ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3;
+    }
+
+    int init_code_size = esp_efuse_get_field_size(init_code_efuse);
+    assert(init_code_size == 10);
+
+    uint32_t init_code = 0;
+    ESP_ERROR_CHECK(esp_efuse_read_field_blob(init_code_efuse, &init_code, init_code_size));
+
+    return init_code + 1400;    // version 1 logic
+
 }
 
 int esp_efuse_rtc_calib_get_chan_compens(int version, uint32_t adc_unit, uint32_t adc_channel, int atten)
 {
-    // TODO: [ESP32C5] IDF-8702
-    abort();
-    return 0;
+    /* Version validation should be guaranteed in the caller */
+    assert(atten < 4);
+    assert(adc_channel < SOC_ADC_CHANNEL_NUM(adc_unit));
+    assert(adc_unit == 0);
+
+    const esp_efuse_desc_t** chan_diff_efuse = NULL;
+    switch (adc_channel) {
+        case 0:
+            chan_diff_efuse = ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF;
+            break;
+        case 1:
+            chan_diff_efuse = ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF;
+            break;
+        case 2:
+            chan_diff_efuse = ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF;
+            break;
+        case 3:
+            chan_diff_efuse = ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF;
+            break;
+        case 4:
+            chan_diff_efuse = ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF;
+            break;
+        case 5:
+            chan_diff_efuse = ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF;
+            break;
+        default:
+            assert(false);
+            break;
+    }
+
+    int chan_diff_size = esp_efuse_get_field_size(chan_diff_efuse);
+    assert(chan_diff_size == 4);
+    uint32_t chan_diff = 0;
+    ESP_ERROR_CHECK(esp_efuse_read_field_blob(chan_diff_efuse, &chan_diff, chan_diff_size));
+
+    return RTC_CALIB_GET_SIGNED_VAL(chan_diff, 3) * (4 - atten);
 }
 
 esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, uint32_t adc_unit, int atten, uint32_t* out_digi, uint32_t* out_vol_mv)
 {
-    // TODO: [ESP32C5] IDF-8702
-    abort();
+    assert(adc_unit == 0);
+
+    const esp_efuse_desc_t** cal_vol_adc1_efuse[4] = {
+        ESP_EFUSE_ADC1_HI_DOUT_ATTEN0,
+        ESP_EFUSE_ADC1_HI_DOUT_ATTEN1,
+        ESP_EFUSE_ADC1_HI_DOUT_ATTEN2,
+        ESP_EFUSE_ADC1_HI_DOUT_ATTEN3,
+    };
+
+    const uint32_t input_vout_mv[1][4] = {
+        {600,  800,  1200, 2300}, // Calibration V1 coefficients
+    };
+
+    if ((version < ESP_EFUSE_ADC_CALIB_VER_MIN) ||
+        (version > ESP_EFUSE_ADC_CALIB_VER_MAX)) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    if (atten >= 4 || atten < 0) {
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    assert(cal_vol_adc1_efuse[atten][0]->bit_count == 10);
+
+    uint32_t cal_vol = 0;
+    esp_err_t ret = ESP_OK;
+    ret = esp_efuse_read_field_blob(cal_vol_adc1_efuse[atten], &cal_vol, cal_vol_adc1_efuse[atten][0]->bit_count);
+
+    if (ret != ESP_OK) {
+        return ret;
+    }
+    uint32_t chk_offset;
+    if (atten == 0) {
+        chk_offset = 2250;
+    } else if (atten == 1) {
+        chk_offset = 2250;
+    } else if (atten == 2) {
+        chk_offset = 2300;
+    } else {
+        chk_offset = 2300;
+    }
+
+    *out_digi = chk_offset + RTC_CALIB_GET_SIGNED_VAL(cal_vol, 9);
+    *out_vol_mv = input_vout_mv[VER2IDX(version)][atten];
+
     return ESP_OK;
 }
 
diff --git a/components/efuse/esp32c5/include/esp_efuse_rtc_calib.h b/components/efuse/esp32c5/include/esp_efuse_rtc_calib.h
index 392a09d49a..9d28078921 100644
--- a/components/efuse/esp32c5/include/esp_efuse_rtc_calib.h
+++ b/components/efuse/esp32c5/include/esp_efuse_rtc_calib.h
@@ -11,14 +11,12 @@
 extern "C" {
 #endif
 
-// TODO: [ESP32C5] IDF-8702
-
 //This is the ADC calibration value version burnt in efuse
 #define ESP_EFUSE_ADC_CALIB_VER1     1
-#define ESP_EFUSE_ADC_CALIB_VER2     2
 #define ESP_EFUSE_ADC_CALIB_VER_MIN  ESP_EFUSE_ADC_CALIB_VER1
-#define ESP_EFUSE_ADC_CALIB_VER_MAX  ESP_EFUSE_ADC_CALIB_VER2
+#define ESP_EFUSE_ADC_CALIB_VER_MAX  ESP_EFUSE_ADC_CALIB_VER1
 #define VER2IDX(ver)    ((ver) - 1)    // Version number to index number of the array
+
 /**
  * @brief Get the RTC calibration efuse version
  *
diff --git a/components/esp_adc/esp32c5/curve_fitting_coefficients.c b/components/esp_adc/esp32c5/curve_fitting_coefficients.c
new file mode 100644
index 0000000000..49c6dcefd3
--- /dev/null
+++ b/components/esp_adc/esp32c5/curve_fitting_coefficients.c
@@ -0,0 +1,60 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <stdint.h>
+#include "esp_efuse_rtc_calib.h"
+#include "../curve_fitting_coefficients.h"
+
+#define COEFF_VERSION_NUM  1 // Currently C5 has one versions of curve calibration schemes
+#define COEFF_GROUP_NUM    4
+#define TERM_MAX           3
+
+/**
+ * @note Error Calculation
+ * Coefficients for calculating the reading voltage error.
+ * Four sets of coefficients for atten0 ~ atten3 respectively.
+ *
+ * For each item, first element is the Coefficient, second element is the Multiple. (Coefficient / Multiple) is the real coefficient.
+ *
+ * @note {0,0} stands for unused item
+ * @note In case of the overflow, these coefficients are recorded as Absolute Value
+ * @note For atten0 ~ 3, error = (K0 * X^0) + (K1 * X^1)
+ * @note Above formula is rewritten from the original documentation, please note that the coefficients are re-ordered.
+ */
+const static uint64_t adc1_error_coef_atten[COEFF_VERSION_NUM][COEFF_GROUP_NUM][TERM_MAX][2] = {
+    /* Coefficients of calibration version 1 */
+    {
+        {{2941017829027464,     1e16}, {7368674918527,   1e16}, {0, 0}},   //atten0
+        {{3224276125615327,     1e16}, {5325658467636,   1e16}, {0, 0}},   //atten1
+        {{3307554632960901,    1e16}, {409244304226,    1e15}, {0, 0}},   //atten2
+        {{1463642578413965,    1e15}, {3349642363147,   1e15}, {11676836451, 1e16}},   //atten3
+    },
+};
+
+/**
+ * Term sign ADC1
+ */
+const static int32_t adc1_error_sign[COEFF_VERSION_NUM][COEFF_GROUP_NUM][TERM_MAX] = {
+    /* Coefficient sign of calibration version 1 */
+    {
+        {1,  -1,  0}, //atten0
+        {1,  -1,  0}, //atten1
+        {1,  -1,  0}, //atten2
+        {1,  -1,  1}, //atten3
+    },
+};
+
+void curve_fitting_get_second_step_coeff(const adc_cali_curve_fitting_config_t *config, cali_chars_second_step_t *ctx)
+{
+    uint32_t adc_calib_ver = esp_efuse_rtc_calib_get_ver();
+    assert((adc_calib_ver >= ESP_EFUSE_ADC_CALIB_VER_MIN) &&
+           (adc_calib_ver <= ESP_EFUSE_ADC_CALIB_VER_MAX));
+
+    ctx->term_num = 2;
+    ctx->coeff = adc1_error_coef_atten[VER2IDX(adc_calib_ver)][config->atten];
+    ctx->sign = adc1_error_sign[VER2IDX(adc_calib_ver)][config->atten];
+}
diff --git a/components/esp_adc/esp32c5/include/adc_cali_schemes.h b/components/esp_adc/esp32c5/include/adc_cali_schemes.h
index 99d231939c..7f0172d895 100644
--- a/components/esp_adc/esp32c5/include/adc_cali_schemes.h
+++ b/components/esp_adc/esp32c5/include/adc_cali_schemes.h
@@ -12,5 +12,4 @@
  * @brief Supported calibration schemes
  */
 
-// TODO: [ESP32C5] IDF-8702
-// #define ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED    1
+#define ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED    1
diff --git a/components/hal/esp32c5/include/hal/adc_ll.h b/components/hal/esp32c5/include/hal/adc_ll.h
index e32a879fff..e451607122 100644
--- a/components/hal/esp32c5/include/hal/adc_ll.h
+++ b/components/hal/esp32c5/include/hal/adc_ll.h
@@ -788,6 +788,66 @@ static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t chann
     return (adc_atten_t)APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten;
 }
 
+
+/*---------------------------------------------------------------
+                    Calibration
+---------------------------------------------------------------*/
+
+/**
+ * @brief Set common calibration configuration. Should be shared with other parts (PWDET).
+ */
+__attribute__((always_inline))
+static inline void adc_ll_calibration_init(adc_unit_t adc_n)
+{
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 4);
+}
+
+/**
+ * Configure the registers for ADC calibration. You need to call the ``adc_ll_calibration_finish`` interface to resume after calibration.
+ *
+ * @note  Different ADC units and different attenuation options use different calibration data (initial data).
+ *
+ * @param adc_n ADC index number.
+ * @param internal_gnd true:  Disconnect from the IO port and use the internal GND as the calibration voltage.
+ *                     false: Use IO external voltage as calibration voltage.
+ */
+static inline void adc_ll_calibration_prepare(adc_unit_t adc_n, bool internal_gnd)
+{
+    /* Enable/disable internal connect GND (for calibration). */
+    if (internal_gnd) {
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1);
+    } else {
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
+    }
+}
+
+/**
+ * Resume register status after calibration.
+ *
+ * @param adc_n ADC index number.
+ */
+static inline void adc_ll_calibration_finish(adc_unit_t adc_n)
+{
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
+}
+
+/**
+ * Set the calibration result to ADC.
+ *
+ * @note  Different ADC units and different attenuation options use different calibration data (initial data).
+ *
+ * @param adc_n ADC index number.
+ */
+__attribute__((always_inline))
+static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param)
+{
+    uint8_t msb = param >> 8;
+    uint8_t lsb = param & 0xFF;
+
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
index 2f31666c0e..5b6829fa78 100644
--- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
@@ -351,6 +351,14 @@ config SOC_ADC_RTC_MAX_BITWIDTH
     int
     default 12
 
+config SOC_ADC_CALIBRATION_V1_SUPPORTED
+    bool
+    default y
+
+config SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED
+    bool
+    default y
+
 config SOC_ADC_TEMPERATURE_SHARE_INTR
     bool
     default y
diff --git a/components/soc/esp32c5/include/soc/regi2c_saradc.h b/components/soc/esp32c5/include/soc/regi2c_saradc.h
index 7fa3ff4602..0328d31b93 100644
--- a/components/soc/esp32c5/include/soc/regi2c_saradc.h
+++ b/components/soc/esp32c5/include/soc/regi2c_saradc.h
@@ -15,85 +15,93 @@
  * function in adc_ll.h.
  */
 
-#define I2C_SAR_ADC            0X69
-#define I2C_SAR_ADC_HOSTID     0
+#define I2C_SAR_ADC                              0x69
+#define I2C_SAR_ADC_HOSTID                       0
 
-#define I2C_SAR_ADC_SAR1_INIT_CODE_LSB      0x0
-#define I2C_SAR_ADC_SAR1_INIT_CODE_LSB_MSB  0x7
-#define I2C_SAR_ADC_SAR1_INIT_CODE_LSB_LSB  0x0
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR           0x0
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB       0x7
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB       0x0
 
-#define I2C_SAR_ADC_SAR1_INIT_CODE_MSB      0x1
-#define I2C_SAR_ADC_SAR1_INIT_CODE_MSB_MSB  0x3
-#define I2C_SAR_ADC_SAR1_INIT_CODE_MSB_LSB  0x0
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR          0x1
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB      0x3
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB      0x0
 
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR          0x2
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB      0x2
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB      0x0
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR               0x2
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB           0x2
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB           0x0
 
-#define ADC_SAR1_DREF_ADDR                  0x2
-#define ADC_SAR1_DREF_ADDR_MSB              0x6
-#define ADC_SAR1_DREF_ADDR_LSB              0x4
+#define ADC_SAR1_DREF_ADDR                       0x2
+#define ADC_SAR1_DREF_ADDR_MSB                   0x6
+#define ADC_SAR1_DREF_ADDR_LSB                   0x4
 
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR      0x3
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB  0x7
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB  0x0
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR           0x3
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB       0x7
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB       0x0
 
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR     0x4
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR          0x4
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB      0x3
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB      0x0
 
-#define ADC_SAR2_SAMPLE_CYCLE_ADDR          0x5
-#define ADC_SAR2_SAMPLE_CYCLE_ADDR_MSB      0x2
-#define ADC_SAR2_SAMPLE_CYCLE_ADDR_LSB      0x0
+#define ADC_SAR2_SAMPLE_CYCLE_ADDR               0x5
+#define ADC_SAR2_SAMPLE_CYCLE_ADDR_MSB           0x2
+#define ADC_SAR2_SAMPLE_CYCLE_ADDR_LSB           0x0
 
-#define ADC_SAR2_DREF_ADDR                  0x5
-#define ADC_SAR2_DREF_ADDR_MSB              0x6
-#define ADC_SAR2_DREF_ADDR_LSB              0x4
+#define ADC_SAR2_DREF_ADDR                       0x5
+#define ADC_SAR2_DREF_ADDR_MSB                   0x6
+#define ADC_SAR2_DREF_ADDR_LSB                   0x4
 
-#define I2C_SARADC_TSENS_DAC                0x6
-#define I2C_SARADC_TSENS_DAC_MSB            0x3
-#define I2C_SARADC_TSENS_DAC_LSB            0x0
+#define I2C_SARADC_TSENS_DAC                     0x6
+#define I2C_SARADC_TSENS_DAC_MSB                 0x3
+#define I2C_SARADC_TSENS_DAC_LSB                 0x0
 
-#define ADC_SARADC_DTEST_RTC_ADDR           0x7
-#define ADC_SARADC_DTEST_RTC_ADDR_MSB       0x1
-#define ADC_SARADC_DTEST_RTC_ADDR_LSB       0x0
+#define ADC_SARADC_DTEST_RTC_ADDR                0x7
+#define ADC_SARADC_DTEST_RTC_ADDR_MSB            0x1
+#define ADC_SARADC_DTEST_RTC_ADDR_LSB            0x0
 
-#define ADC_SARADC_ENT_TSENS_ADDR           0x7
-#define ADC_SARADC_ENT_TSENS_ADDR_MSB       0x2
-#define ADC_SARADC_ENT_TSENS_ADDR_LSB       0x2
+#define ADC_SARADC_ENT_TSENS_ADDR                0x7
+#define ADC_SARADC_ENT_TSENS_ADDR_MSB            0x2
+#define ADC_SARADC_ENT_TSENS_ADDR_LSB            0x2
 
-#define ADC_SARADC1_EN_TOUT_SAR1_BUS_ADDR   0x7
-#define ADC_SARADC1_EN_TOUT_SAR1_BUS_ADDR_MSB 0x4
-#define ADC_SARADC1_EN_TOUT_SAR1_BUS_ADDR_LSB 0x4
+#define ADC_SARADC1_EN_TOUT_SAR1_BUS_ADDR        0x7
+#define ADC_SARADC1_EN_TOUT_SAR1_BUS_ADDR_MSB    0x4
+#define ADC_SARADC1_EN_TOUT_SAR1_BUS_ADDR_LSB    0x4
 
-#define ADC_SARADC2_EN_TOUT_SAR2_BUS_ADDR   0x7
-#define ADC_SARADC2_EN_TOUT_SAR2_BUS_ADDR_MSB 0x5
-#define ADC_SARADC2_EN_TOUT_SAR2_BUS_ADDR_LSB 0x5
+#define ADC_SARADC2_EN_TOUT_SAR2_BUS_ADDR        0x7
+#define ADC_SARADC2_EN_TOUT_SAR2_BUS_ADDR_MSB    0x5
+#define ADC_SARADC2_EN_TOUT_SAR2_BUS_ADDR_LSB    0x5
 
-#define ADC_SARADC_ENT_PERIF_ADDR           0x7
-#define ADC_SARADC_ENT_PERIF_ADDR_MSB       0x6
-#define ADC_SARADC_ENT_PERIF_ADDR_LSB       0x6
+#define ADC_SARADC_ENT_PERIF_ADDR                0x7
+#define ADC_SARADC_ENT_PERIF_ADDR_MSB            0x6
+#define ADC_SARADC_ENT_PERIF_ADDR_LSB            0x6
 
-#define ADC_SARADC1_EN_TOUT_ADDR            0x8
-#define ADC_SARADC1_EN_TOUT_ADDR_MSB        0x0
-#define ADC_SARADC1_EN_TOUT_ADDR_LSB        0x0
+#define ADC_SARADC1_EN_TOUT_ADDR                 0x8
+#define ADC_SARADC1_EN_TOUT_ADDR_MSB             0x0
+#define ADC_SARADC1_EN_TOUT_ADDR_LSB             0x0
 
-#define ADC_SARADC2_EN_TOUT_ADDR            0x8
-#define ADC_SARADC2_EN_TOUT_ADDR_MSB        0x2
-#define ADC_SARADC2_EN_TOUT_ADDR_LSB        0x2
+#define ADC_SARADC2_EN_TOUT_ADDR                 0x8
+#define ADC_SARADC2_EN_TOUT_ADDR_MSB             0x2
+#define ADC_SARADC2_EN_TOUT_ADDR_LSB             0x2
 
-#define POWER_GLITCH_DREF_VDET_PERIF         11
-#define POWER_GLITCH_DREF_VDET_PERIF_MSB     2
-#define POWER_GLITCH_DREF_VDET_PERIF_LSB     0
+#define ADC_SAR1_ENCAL_GND_ADDR                  0x8
+#define ADC_SAR1_ENCAL_GND_ADDR_MSB              0x1
+#define ADC_SAR1_ENCAL_GND_ADDR_LSB              0x1
 
-#define POWER_GLITCH_DREF_VDET_VDDPST        11
-#define POWER_GLITCH_DREF_VDET_VDDPST_MSB    6
-#define POWER_GLITCH_DREF_VDET_VDDPST_LSB    4
+#define ADC_SAR2_ENCAL_GND_ADDR                  0x8
+#define ADC_SAR2_ENCAL_GND_ADDR_MSB              0x3
+#define ADC_SAR2_ENCAL_GND_ADDR_LSB              0x3
 
-#define POWER_GLITCH_DREF_VDET_XTAL          12
-#define POWER_GLITCH_DREF_VDET_XTAL_MSB      2
-#define POWER_GLITCH_DREF_VDET_XTAL_LSB      0
+#define POWER_GLITCH_DREF_VDET_PERIF             11
+#define POWER_GLITCH_DREF_VDET_PERIF_MSB         2
+#define POWER_GLITCH_DREF_VDET_PERIF_LSB         0
 
-#define POWER_GLITCH_DREF_VDET_PLL           12
-#define POWER_GLITCH_DREF_VDET_PLL_MSB       6
-#define POWER_GLITCH_DREF_VDET_PLL_LSB       4
+#define POWER_GLITCH_DREF_VDET_VDDPST            11
+#define POWER_GLITCH_DREF_VDET_VDDPST_MSB        6
+#define POWER_GLITCH_DREF_VDET_VDDPST_LSB        4
+
+#define POWER_GLITCH_DREF_VDET_XTAL              12
+#define POWER_GLITCH_DREF_VDET_XTAL_MSB          2
+#define POWER_GLITCH_DREF_VDET_XTAL_LSB          0
+
+#define POWER_GLITCH_DREF_VDET_PLL               12
+#define POWER_GLITCH_DREF_VDET_PLL_MSB           6
+#define POWER_GLITCH_DREF_VDET_PLL_LSB           4
diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h
index 4a49a812d7..e618ea5315 100644
--- a/components/soc/esp32c5/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/include/soc/soc_caps.h
@@ -130,9 +130,8 @@
 #define SOC_ADC_RTC_MAX_BITWIDTH                (12)
 
 /*!< Calibration */
-// #define SOC_ADC_CALIBRATION_V1_SUPPORTED        (1) /*!< support HW offset calibration version 1*/
-// #define SOC_ADC_SELF_HW_CALI_SUPPORTED          (1) /*!< support HW offset self calibration */
-// #define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */
+#define SOC_ADC_CALIBRATION_V1_SUPPORTED        (1) /*!< support HW offset calibration version 1*/
+#define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED    (1) /*!< support channel compensation to the HW offset calibration */
 
 /*!< Interrupt */
 #define SOC_ADC_TEMPERATURE_SHARE_INTR          (1)
diff --git a/docs/docs_not_updated/esp32c5.txt b/docs/docs_not_updated/esp32c5.txt
index 908fdf5f51..ad52183126 100644
--- a/docs/docs_not_updated/esp32c5.txt
+++ b/docs/docs_not_updated/esp32c5.txt
@@ -29,7 +29,6 @@ api-reference/peripherals/touch_element.rst
 api-reference/peripherals/lcd.rst
 api-reference/peripherals/spi_features.rst
 api-reference/peripherals/touch_pad.rst
-api-reference/peripherals/adc_calibration.rst
 api-reference/peripherals/sd_pullup_requirements.rst
 api-reference/peripherals/index.rst
 api-reference/peripherals/sdmmc_host.rst
diff --git a/docs/en/api-reference/peripherals/adc_calibration.rst b/docs/en/api-reference/peripherals/adc_calibration.rst
index 831805e664..cbb6e1bc23 100644
--- a/docs/en/api-reference/peripherals/adc_calibration.rst
+++ b/docs/en/api-reference/peripherals/adc_calibration.rst
@@ -82,7 +82,7 @@ If you use your custom ADC calibration schemes, you could either modify this fun
         ESP_ERROR_CHECK(adc_cali_delete_scheme_line_fitting(handle));
 
 
-.. only:: esp32c3 or esp32s3 or esp32c6 or esp32h2
+.. only:: esp32c3 or esp32s3 or esp32c6 or esp32h2 or esp32c5
 
     ADC Calibration Curve Fitting Scheme
     ````````````````````````````````````
@@ -97,7 +97,7 @@ If you use your custom ADC calibration schemes, you could either modify this fun
         -  :cpp:member:`adc_cali_curve_fitting_config_t::atten`, ADC attenuation that your ADC raw results use.
         -  :cpp:member:`adc_cali_curve_fitting_config_t::bitwidth`, bit width of ADC raw result.
 
-    .. only:: esp32c6 or esp32h2
+    .. only:: esp32c6 or esp32h2 or esp32c5
 
         -  :cpp:member:`adc_cali_curve_fitting_config_t::unit_id`, the ADC that your ADC raw results are from.
         -  :cpp:member:`adc_cali_curve_fitting_config_t::chan`, the ADC channel that your ADC raw results are from. The calibration scheme not only differs by attenuation but is also related to the channels.