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fix(esp_hw_support): fix unused OSC source deinit breaks XTAL32K configuration

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This commit is contained in:
wuzhenghui
2025-04-10 20:29:07 +08:00
parent 54c4606111
commit ba88b91e28
8 changed files with 12 additions and 32 deletions
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3
components/esp_system/port/soc/esp32/clk.c
View File

@ -92,12 +92,9 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
}
rtc_clk_slow_src_set(rtc_slow_clk_src);
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
if (slow_clk == SLOW_CLK_32K_XTAL) {
rtc_clk_32k_enable(false);
} else if (slow_clk == SLOW_CLK_32K_EXT_OSC) {
rtc_clk_32k_disable_external();
}
}
if (SLOW_CLK_CAL_CYCLES > 0) {
/* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable.

3
components/esp_system/port/soc/esp32c3/clk.c
View File

@ -177,12 +177,9 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
}
rtc_clk_slow_src_set(rtc_slow_clk_src);
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
if (slow_clk == SLOW_CLK_32K_XTAL) {
rtc_clk_32k_enable(false);
} else if (slow_clk == SLOW_CLK_32K_EXT_OSC) {
rtc_clk_32k_disable_external();
}
}
if (SLOW_CLK_CAL_CYCLES > 0) {
/* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable.

4
components/esp_system/port/soc/esp32c5/clk.c
View File

@ -169,10 +169,8 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
rtc_clk_slow_src_set(rtc_slow_clk_src);
// Disable unused clock sources after clock source switching is complete.
// Regardless of the clock source selection, the internal 136K clock source will always keep on.
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
if ((rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K) && (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW)) {
rtc_clk_32k_enable(false);
}
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
rtc_clk_32k_disable_external();
}
if (SLOW_CLK_CAL_CYCLES > 0) {

4
components/esp_system/port/soc/esp32c6/clk.c
View File

@ -187,10 +187,8 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
rtc_clk_slow_src_set(rtc_slow_clk_src);
// Disable unused clock sources after clock source switching is complete.
// Regardless of the clock source selection, the internal 136K clock source will always keep on.
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
if ((rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K) && (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW)) {
rtc_clk_32k_enable(false);
}
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
rtc_clk_32k_disable_external();
}
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {

4
components/esp_system/port/soc/esp32c61/clk.c
View File

@ -150,10 +150,8 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
rtc_clk_slow_src_set(rtc_slow_clk_src);
// Disable unused clock sources after clock source switching is complete.
// Regardless of the clock source selection, the internal 136K clock source will always keep on.
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
if ((rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K) && (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW)) {
rtc_clk_32k_enable(false);
}
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
rtc_clk_32k_disable_external();
}
if (SLOW_CLK_CAL_CYCLES > 0) {

4
components/esp_system/port/soc/esp32h2/clk.c
View File

@ -185,10 +185,8 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
rtc_clk_slow_src_set(rtc_slow_clk_src);
// Disable unused clock sources after clock source switching is complete.
// Regardless of the clock source selection, the internal 136K clock source will always keep on.
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
if ((rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K) && (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW)) {
rtc_clk_32k_enable(false);
}
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
rtc_clk_32k_disable_external();
}
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {

3
components/esp_system/port/soc/esp32s2/clk.c
View File

@ -180,12 +180,9 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
}
rtc_clk_slow_src_set(rtc_slow_clk_src);
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
if (slow_clk == SLOW_CLK_32K_XTAL) {
rtc_clk_32k_enable(false);
} else if (slow_clk == SLOW_CLK_32K_EXT_OSC) {
rtc_clk_32k_disable_external();
}
}
if (SLOW_CLK_CAL_CYCLES > 0) {
/* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable.

3
components/esp_system/port/soc/esp32s3/clk.c
View File

@ -178,12 +178,9 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
}
rtc_clk_slow_src_set(rtc_slow_clk_src);
if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
if (slow_clk == SLOW_CLK_32K_XTAL) {
rtc_clk_32k_enable(false);
} else if (slow_clk == SLOW_CLK_32K_EXT_OSC) {
rtc_clk_32k_disable_external();
}
}
if (SLOW_CLK_CAL_CYCLES > 0) {
/* TODO: 32k XTAL oscillator has some frequency drift at startup.
* Improve calibration routine to wait until the frequency is stable.