From bb0dac0a72ee7b3bcdced3505c80275f3675f5e6 Mon Sep 17 00:00:00 2001 From: "chaijie@espressif.com" Date: Mon, 13 Jan 2025 19:56:43 +0800 Subject: [PATCH] fix(esp32): Fixed qa program may fail issue when cpu 240m (v5.3) --- components/esp_hw_support/port/esp32/include/soc/rtc.h | 7 ++----- components/esp_hw_support/port/esp32/rtc_clk.c | 1 + 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/components/esp_hw_support/port/esp32/include/soc/rtc.h b/components/esp_hw_support/port/esp32/include/soc/rtc.h index 4bddde227c..9e250a9659 100644 --- a/components/esp_hw_support/port/esp32/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32/include/soc/rtc.h @@ -66,16 +66,13 @@ extern "C" { /* Core voltage needs to be increased in two cases: * 1. running at 240 MHz * 2. running with 80MHz Flash frequency - * - * There is a record in efuse which indicates the proper voltage for these two cases. */ -#define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - efuse_ll_get_vol_level_hp_inv()) #ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M -#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_HP_VOLT +#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V25 #else #define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10 #endif -#define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT +#define DIG_DBIAS_240M RTC_CNTL_DBIAS_1V25 #define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 #define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 diff --git a/components/esp_hw_support/port/esp32/rtc_clk.c b/components/esp_hw_support/port/esp32/rtc_clk.c index 8749102291..9a11540301 100644 --- a/components/esp_hw_support/port/esp32/rtc_clk.c +++ b/components/esp_hw_support/port/esp32/rtc_clk.c @@ -395,6 +395,7 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) rtc_clk_apb_freq_update(80 * MHZ); esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz); rtc_clk_wait_for_slow_cycle(); + esp_rom_delay_us(30); } void rtc_clk_cpu_freq_set_xtal(void)