diff --git a/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c index 5d15ff99b2..d0b5f1a730 100644 --- a/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c @@ -81,7 +81,9 @@ bool clock_domain_pd_allowed(void) * necessary to check the state of CLOCK_MODEM to determine MODEM domain on * or off. The clock and reset of digital peripherals are managed through * PCR, with TOP domain similar to MODEM domain. */ +#if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED sleep_retention_module_bitmap_t modem_clk_dep_modules = (sleep_retention_module_bitmap_t){ .bitmap = { 0 } }; +#endif #if SOC_WIFI_SUPPORTED modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_WIFI_MAC >> 5] |= BIT(SLEEP_RETENTION_MODULE_WIFI_MAC % 32); modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_WIFI_BB >> 5] |= BIT(SLEEP_RETENTION_MODULE_WIFI_BB % 32); diff --git a/components/esp_hw_support/port/esp32c61/Kconfig.hw_support b/components/esp_hw_support/port/esp32c61/Kconfig.hw_support index 7cb0fe1f89..71e247da35 100644 --- a/components/esp_hw_support/port/esp32c61/Kconfig.hw_support +++ b/components/esp_hw_support/port/esp32c61/Kconfig.hw_support @@ -1,6 +1,6 @@ choice ESP32C61_REV_MIN prompt "Minimum Supported ESP32-C61 Revision" - default ESP32C61_REV_MIN_0 + default ESP32C61_REV_MIN_100 help Required minimum chip revision. ESP-IDF will check for it and reject to boot if the chip revision fails the check. @@ -9,13 +9,13 @@ choice ESP32C61_REV_MIN The complied binary will only support chips above this revision, this will also help to reduce binary size. - config ESP32C61_REV_MIN_0 - bool "Rev v0.0" + config ESP32C61_REV_MIN_100 + bool "Rev v1.0" endchoice config ESP32C61_REV_MIN_FULL int - default 0 if ESP32C61_REV_MIN_0 + default 100 if ESP32C61_REV_MIN_100 config ESP_REV_MIN_FULL int @@ -25,7 +25,7 @@ config ESP_REV_MIN_FULL # MAX Revision # - comment "Maximum Supported ESP32-C61 Revision (Rev v0.99)" + comment "Maximum Supported ESP32-C61 Revision (Rev v1.99)" # Maximum revision that IDF supports. # It can not be changed by user. # Only Espressif can change it when a new version will be supported in IDF. @@ -33,7 +33,7 @@ config ESP_REV_MIN_FULL config ESP32C61_REV_MAX_FULL int - default 99 + default 199 # keep in sync the "Maximum Supported Revision" description with this value config ESP_REV_MAX_FULL @@ -53,6 +53,6 @@ config ESP_EFUSE_BLOCK_REV_MIN_FULL config ESP_EFUSE_BLOCK_REV_MAX_FULL int - default 99 + default 199 comment "Maximum Supported ESP32-C61 eFuse Block Revision (eFuse Block Rev v0.99)" # The revision in the comment must correspond to the default value of ESP_EFUSE_BLOCK_REV_MAX_FULL diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index 6a811e4158..e8d5d862c7 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -67,10 +67,6 @@ if(CONFIG_ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG OR CONFIG_ESP_ROM_HAS_CACHE_WRITEBAC list(APPEND sources "patches/esp_rom_cache_esp32s2_esp32s3.c") endif() -if(CONFIG_ESP_ROM_CACHE_WB_INVLD_LOW_RANGE) - list(APPEND sources "patches/esp_rom_cache_esp32c61.c") -endif() - if(CONFIG_ESP_ROM_HAS_CACHE_WRITEBACK_BUG) list(APPEND sources "patches/esp_rom_cache_writeback_esp32s3.S") endif() diff --git a/components/esp_rom/esp32c61/Kconfig.soc_caps.in b/components/esp_rom/esp32c61/Kconfig.soc_caps.in index c3d7974600..277f27d598 100644 --- a/components/esp_rom/esp32c61/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c61/Kconfig.soc_caps.in @@ -107,10 +107,6 @@ config ESP_ROM_HAS_OUTPUT_PUTC_FUNC bool default y -config ESP_ROM_CACHE_WB_INVLD_LOW_RANGE - bool - default y - config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY bool default y diff --git a/components/esp_rom/esp32c61/esp_rom_caps.h b/components/esp_rom/esp32c61/esp_rom_caps.h index 72a5220656..c94e743dde 100644 --- a/components/esp_rom/esp32c61/esp_rom_caps.h +++ b/components/esp_rom/esp32c61/esp_rom_caps.h @@ -32,5 +32,4 @@ #define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions #define ESP_ROM_USB_OTG_NUM (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage. #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) -#define ESP_ROM_CACHE_WB_INVLD_LOW_RANGE (1) // ROM `Cache_WriteBack_Addr` and `Cache_Invalidate_Addr` can only access low vaddr parts #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access. diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.coexist.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.coexist.ld index 0bc6336107..2977468580 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.coexist.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.coexist.ld @@ -1,14 +1,10 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -/* ROM function interface esp32c61.rom.coexist.ld for esp32c61 - * - * - * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457 - * - * Compatible with ROM where ECO version equal or greater to 0. + +/* ROM function interface * * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. */ @@ -35,7 +31,7 @@ coex_hw_timer_set = 0x40000a64; coex_schm_interval_set = 0x40000a68; coex_schm_lock = 0x40000a6c; coex_schm_unlock = 0x40000a70; -/*coex_status_get = 0x40000a74;*/ +coex_status_get = 0x40000a74; coex_wifi_release = 0x40000a78; esp_coex_ble_conn_dynamic_prio_get = 0x40000a7c; /* Data (.data, .bss, .rodata) */ diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.ld index 645b536924..390992ee54 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.ld @@ -1,14 +1,10 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -/* ROM function interface esp32c61.rom.ld for esp32c61 - * - * - * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457 - * - * Compatible with ROM where ECO version equal or greater to 0. + +/* ROM function interface * * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. */ @@ -54,8 +50,6 @@ software_reset_cpu = 0x40000098; ets_clk_assist_debug_clock_enable = 0x4000009c; clear_super_wdt_reset_flag = 0x400000a0; disable_default_watchdog = 0x400000a4; -esp_rom_set_rtc_wake_addr = 0x400000a8; -esp_rom_get_rtc_wake_addr = 0x400000ac; send_packet = 0x400000b0; recv_packet = 0x400000b4; GetUartDevice = 0x400000b8; @@ -192,9 +186,9 @@ MMU_Set_Page_Mode = 0x40000624; MMU_Get_Page_Mode = 0x40000628; Cache_Sync_Items = 0x4000062c; Cache_Op_Addr = 0x40000630; -/*Cache_Invalidate_Addr = 0x40000634; rom version API has issue that unable to access higher vaddr range, use IDF patch */ +Cache_Invalidate_Addr = 0x40000634; Cache_Clean_Addr = 0x40000638; -/*Cache_WriteBack_Addr = 0x4000063c; rom version API has issue that unable to access higher vaddr range, use IDF patch */ +Cache_WriteBack_Addr = 0x4000063c; Cache_WriteBack_Invalidate_Addr = 0x40000640; Cache_Invalidate_All = 0x40000644; Cache_Clean_All = 0x40000648; @@ -369,7 +363,6 @@ ets_efuse_jtag_disabled = 0x400007fc; ets_efuse_usb_print_is_disabled = 0x40000800; ets_efuse_usb_download_mode_disabled = 0x40000804; ets_efuse_usb_device_disabled = 0x40000808; -ets_efuse_secure_boot_fast_wake_enabled = 0x4000080c; /*************************************** @@ -393,3 +386,60 @@ usb_serial_device_rx_one_char = 0x40000a20; usb_serial_device_rx_one_char_block = 0x40000a24; usb_serial_device_tx_flush = 0x40000a28; usb_serial_device_tx_one_char = 0x40000a2c; + + +/*************************************** + Group lldesc + ***************************************/ + +/* Functions */ +lldesc_build_chain = 0x400014dc; + + +/*************************************** + Group sip + ***************************************/ + +/* Functions */ +sip_after_tx_complete = 0x400014e0; +sip_alloc_to_host_evt = 0x400014e4; +sip_download_begin = 0x400014e8; +sip_get_ptr = 0x400014ec; +sip_get_state = 0x400014f0; +sip_init_attach = 0x400014f4; +sip_install_rx_ctrl_cb = 0x400014f8; +sip_install_rx_data_cb = 0x400014fc; +sip_is_active = 0x40001500; +sip_post_init = 0x40001504; +sip_reclaim_from_host_cmd = 0x40001508; +sip_reclaim_tx_data_pkt = 0x4000150c; +sip_send = 0x40001510; +sip_to_host_chain_append = 0x40001514; +sip_to_host_evt_send_done = 0x40001518; + + +/*************************************** + Group slc + ***************************************/ + +/* Functions */ +slc_add_credits = 0x4000151c; +slc_enable = 0x40001520; +slc_from_host_chain_fetch = 0x40001524; +slc_from_host_chain_recycle = 0x40001528; +slc_has_pkt_to_host = 0x4000152c; +slc_init_attach = 0x40001530; +slc_init_credit = 0x40001534; +slc_reattach = 0x40001538; +slc_send_to_host_chain = 0x4000153c; +slc_set_host_io_max_window = 0x40001540; +slc_to_host_chain_recycle = 0x40001544; + + +/*************************************** + Group recovery_bootloader + ***************************************/ + +/* Functions */ +ets_get_bootloader_offset = 0x40001548; +ets_set_bootloader_offset = 0x4000154c; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld index a864189192..1ca0e76803 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld @@ -1,14 +1,10 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -/* ROM function interface esp32c61.rom.net80211.ld for esp32c61 - * - * - * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457 - * - * Compatible with ROM where ECO version equal or greater to 0. + +/* ROM function interface * * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. */ @@ -40,7 +36,7 @@ ieee80211_encap_esfbuf = 0x40000ac8; ieee80211_is_tx_allowed = 0x40000acc; ieee80211_output_pending_eb = 0x40000ad0; ieee80211_output_process = 0x40000ad4; -/*ieee80211_set_tx_desc = 0x40000ad8;*/ +ieee80211_set_tx_desc = 0x40000ad8; ieee80211_classify = 0x40000adc; ieee80211_copy_eb_header = 0x40000ae0; ieee80211_recycle_cache_eb = 0x40000ae4; @@ -60,12 +56,12 @@ ieee80211_find_ext_elem = 0x40000b18; ieee80211_find_ie = 0x40000b1c; ieee80211_find_ext_ie = 0x40000b20; ieee80211_merge_mbssid_profile = 0x40000b24; -/*ieee80211_encap_esfbuf_htc = 0x40000b28;*/ +ieee80211_encap_esfbuf_htc = 0x40000b28; wifi_get_macaddr = 0x40000b2c; wifi_rf_phy_disable = 0x40000b30; wifi_rf_phy_enable = 0x40000b34; wifi_is_started = 0x40000b38; -/*sta_input = 0x40000b3c;*/ +sta_input = 0x40000b3c; sta_rx_eapol = 0x40000b40; sta_reset_beacon_timeout = 0x40000b44; sta_get_beacon_timeout = 0x40000b48; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.phy.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.phy.ld index d7ab643c47..43dc22b800 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.phy.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.phy.ld @@ -21,293 +21,8 @@ phy_param_addr = 0x4000104c; chip762_phyrom_version = 0x40001050; chip762_phyrom_version_num = 0x40001054; -phy_get_rc_dout = 0x40001058; -phy_rc_cal = 0x4000105c; -phy_abs_temp = 0x40001060; -phy_set_chan_cal_interp = 0x40001064; -phy_loopback_mode_en = 0x40001068; -phy_get_data_sat = 0x4000106c; -phy_byte_to_word = 0x40001070; -phy_bb_bss_cbw40 = 0x40001074; -phy_set_chan_reg = 0x40001078; -phy_i2c_master_reset = 0x4000107c; -phy_chan14_mic_enable = 0x40001080; -phy_chan14_mic_cfg = 0x40001084; -phy_freq_module_resetn = 0x40001088; -phy_freq_chan_en_sw = 0x4000108c; -phy_write_chan_freq = 0x40001090; -phy_get_freq_mem_param = 0x40001094; -phy_get_freq_mem_addr = 0x40001098; -phy_wr_rf_freq_mem = 0x4000109c; -phy_read_rf_freq_mem = 0x400010a0; -phy_freq_i2c_mem_write = 0x400010a4; -phy_freq_reg_init = 0x400010a8; -phy_freq_num_get_data = 0x400010ac; -phy_freq_i2c_num_addr = 0x400010b0; -phy_freq_i2c_write_set = 0x400010b4; -phy_pll_dac_mem_update = 0x400010b8; -phy_pll_cap_mem_update = 0x400010bc; -phy_get_rf_freq_cap = 0x400010c0; -phy_get_rf_freq_init = 0x400010c4; -phy_freq_get_i2c_data = 0x400010c8; -phy_freq_i2c_data_write = 0x400010cc; -phy_set_chan_freq_hw_init = 0x400010d0; -phy_en_hw_set_freq = 0x400010d4; -phy_dis_hw_set_freq = 0x400010d8; -phy_wait_freq_set_busy = 0x400010dc; -phy_set_chan_freq_sw_start = 0x400010e0; -phy_wait_i2c_sdm_stable = 0x400010e4; -phy_reg_init = 0x400010e8; -phy_xpd_rf = 0x400010ec; -phy_close_rf = 0x400010f0; -phy_get_mac_addr = 0x400010f4; -phy_set_mac_data = 0x400010f8; -phy_rfcal_data_sub = 0x400010fc; -phy_rf_cal_data_recovery = 0x40001100; -phy_rf_cal_data_backup = 0x40001104; -phy_rfcal_data_check = 0x40001108; -phy_pwdet_reg_init = 0x4000110c; -phy_pwdet_sar2_init = 0x40001110; -phy_en_pwdet = 0x40001114; -phy_get_sar_sig_ref = 0x40001118; -phy_pwdet_tone_start = 0x4000111c; -phy_get_tone_sar_dout = 0x40001120; -phy_get_fm_sar_dout = 0x40001124; -phy_txtone_linear_pwr = 0x40001128; -phy_linear_to_db = 0x4000112c; -phy_get_power_db = 0x40001130; -phy_meas_tone_pwr_db = 0x40001134; -phy_pwdet_wait_idle = 0x40001138; -phy_pkdet_vol_start = 0x4000113c; -phy_read_sar_dout = 0x40001140; -phy_read_sar2_code = 0x40001144; -phy_get_sar2_vol = 0x40001148; -phy_get_pll_vol = 0x4000114c; -phy_tx_pwctrl_bg_init = 0x40001150; -phy_set_most_tpw = 0x40001154; -phy_get_most_tpw = 0x40001158; -phy_tx_state_out = 0x4000115c; -phy_ant_dft_cfg = 0x40001160; -phy_ant_wifitx_cfg = 0x40001164; -phy_ant_wifirx_cfg = 0x40001168; -phy_ant_bttx_cfg = 0x4000116c; -phy_ant_btrx_cfg = 0x40001170; -phy_chan_dump_cfg = 0x40001174; -phy_enable_low_rate = 0x40001178; -phy_disable_low_rate = 0x4000117c; -phy_is_low_rate_enabled = 0x40001180; -phy_dig_reg_backup = 0x40001184; -phy_chan_filt_set = 0x40001188; -phy_rx11blr_cfg = 0x4000118c; -phy_set_cca = 0x40001190; -phy_set_rx_sense = 0x40001194; -phy_rx_gain_force = 0x40001198; -phy_mhz2ieee = 0x4000119c; -phy_chan_to_freq = 0x400011a0; -phy_restart_cal = 0x400011a4; -phy_write_rfpll_sdm = 0x400011a8; -phy_wait_rfpll_cal_end = 0x400011ac; -phy_rfpll_set_freq = 0x400011b0; -phy_set_rf_freq_offset = 0x400011b4; -phy_set_rfpll_freq = 0x400011b8; -phy_set_channel_rfpll_freq = 0x400011bc; -phy_rfpll_cap_correct = 0x400011c0; -phy_rfpll_cap_init_cal = 0x400011c4; -phy_set_freq = 0x400011c8; -phy_write_pll_cap = 0x400011cc; -phy_read_pll_cap = 0x400011d0; -phy_chip_set_chan_misc = 0x400011d4; -phy_freq_set_reg = 0x400011d8; -phy_rfpll_chgp_cal = 0x400011dc; -phy_gen_rx_gain_table = 0x400011e0; -phy_get_rxbb_dc = 0x400011e4; -phy_wr_rx_gain_mem = 0x400011e8; -phy_rfpll_cap_track = 0x400011ec; -phy_param_track = 0x400011f0; -phy_txpwr_correct = 0x400011f4; -phy_txpwr_cal_track = 0x400011f8; -phy_bt_track_tx_power = 0x400011fc; -phy_wifi_track_tx_power = 0x40001200; -phy_bt_txdc_cal = 0x40001204; -phy_bt_txiq_cal = 0x40001208; -phy_txdc_cal_pwdet = 0x4000120c; -phy_txdc_cal = 0x40001210; -phy_txiq_get_mis_pwr = 0x40001214; -phy_txiq_cover = 0x40001218; -phy_rfcal_txiq = 0x4000121c; -phy_get_power_atten = 0x40001220; -phy_pwdet_ref_code = 0x40001224; -phy_pwdet_code_cal = 0x40001228; -phy_rfcal_txcap = 0x4000122c; -phy_tx_cap_init = 0x40001230; -phy_rfcal_pwrctrl = 0x40001234; -phy_tx_pwctrl_init_cal = 0x40001238; -phy_tx_pwctrl_init = 0x4000123c; -phy_bt_tx_pwctrl_init = 0x40001240; -phy_i2c_enter_critical_ = 0x40001244; -phy_i2c_exit_critical_ = 0x40001248; -phy_i2c_clk_sel = 0x4000124c; -phy_get_i2c_read_mask_ = 0x40001250; -phy_get_i2c_mst0_mask = 0x40001254; -phy_get_i2c_hostid_ = 0x40001258; -phy_chip_i2c_readReg_org = 0x4000125c; -phy_chip_i2c_readReg = 0x40001260; -phy_i2c_paral_set_mst0 = 0x40001264; -phy_i2c_paral_set_read = 0x40001268; -phy_i2c_paral_read = 0x4000126c; -phy_i2c_paral_write = 0x40001270; -phy_i2c_paral_write_num = 0x40001274; -phy_i2c_paral_write_mask = 0x40001278; -phy_i2c_readReg = 0x4000127c; -phy_chip_i2c_writeReg = 0x40001280; -phy_i2c_writeReg = 0x40001284; -phy_i2c_readReg_Mask = 0x40001288; -phy_i2c_writeReg_Mask = 0x4000128c; -phy_set_txcap_reg = 0x40001290; -phy_i2c_sar2_init_code = 0x40001294; -phy_test_filter_band_set = 0x40001298; -phy_filter_dcap_set = 0x4000129c; -phy_i2c_init1 = 0x400012a0; -phy_i2c_init2 = 0x400012a4; -phy_bias_reg_set = 0x400012a8; -phy_i2c_rc_cal_set = 0x400012ac; -phy_i2c_bbpll_set = 0x400012b0; -phy_adc_rate_set = 0x400012b4; -phy_dac_rate_set = 0x400012b8; -phy_encode_i2c_master = 0x400012bc; -phy_i2c_master_fill = 0x400012c0; -phy_i2c_master_mem_txcap = 0x400012c4; -/* phy_i2c_master_cmd_mem_init = 0x400012c8; */ -/* phy_i2c_master_mem_cfg = 0x400012cc; */ -phy_pbus_force_mode = 0x400012d0; -phy_pbus_rd_addr = 0x400012d4; -phy_pbus_rd_shift = 0x400012d8; -phy_pbus_force_test = 0x400012dc; -phy_pbus_rd = 0x400012e0; -phy_pbus_debugmode = 0x400012e4; -phy_pbus_workmode = 0x400012e8; -phy_pbus_set_rxgain = 0x400012ec; -phy_pbus_xpd_rx_off = 0x400012f0; -phy_pbus_xpd_rx_on = 0x400012f4; -phy_pbus_xpd_tx_off = 0x400012f8; -phy_pbus_xpd_tx_on = 0x400012fc; -phy_pbus_set_dco = 0x40001300; -phy_set_loopback_gain = 0x40001304; -phy_txcal_debuge_mode_ = 0x40001308; -phy_txcal_work_mode = 0x4000130c; -phy_pbus_clear_reg = 0x40001310; -phy_save_pbus_reg = 0x40001314; -phy_write_pbus_mem = 0x40001318; -phy_set_pbus_mem = 0x4000131c; -phy_disable_agc = 0x40001320; -phy_enable_agc = 0x40001324; -phy_disable_cca = 0x40001328; -phy_enable_cca = 0x4000132c; -phy_write_gain_mem = 0x40001330; -phy_bb_bss_cbw40_dig = 0x40001334; -phy_mac_tx_chan_offset = 0x40001338; -phy_rx_11b_opt = 0x4000133c; -phy_tx_paon_set = 0x40001340; -phy_i2cmst_reg_init = 0x40001344; -phy_bt_gain_offset = 0x40001348; -phy_fe_reg_init = 0x4000134c; -phy_mac_enable_bb = 0x40001350; -phy_bb_wdg_cfg = 0x40001354; -phy_fe_txrx_reset = 0x40001358; -phy_set_rx_comp_ = 0x4000135c; -phy_agc_reg_init = 0x40001360; -phy_btbb_wifi_bb_cfg2 = 0x40001364; -phy_bb_reg_init = 0x40001368; -phy_open_i2c_xpd = 0x4000136c; -phy_force_txrx_off = 0x40001370; -phy_txiq_set_reg = 0x40001374; -phy_rxiq_set_reg = 0x40001378; -phy_set_txclk_en = 0x4000137c; -phy_set_rxclk_en = 0x40001380; -phy_start_tx_tone_step = 0x40001384; -phy_stop_tx_tone = 0x40001388; -phy_bb_wdg_test_en = 0x4000138c; -phy_noise_floor_auto_set = 0x40001390; -phy_read_hw_noisefloor = 0x40001394; -phy_iq_corr_enable = 0x40001398; -phy_wifi_agc_sat_gain = 0x4000139c; -phy_bbpll_cal = 0x400013a0; -phy_ant_init = 0x400013a4; -phy_wifi_fbw_sel = 0x400013a8; -phy_bt_filter_reg = 0x400013ac; -phy_rx_sense_set = 0x400013b0; -phy_tx_state_set = 0x400013b4; -phy_close_pa = 0x400013b8; -phy_freq_correct = 0x400013bc; -phy_set_pbus_reg = 0x400013c0; -phy_wifi_rifs_mode_en = 0x400013c4; -phy_nrx_freq_set = 0x400013c8; -phy_fe_adc_on = 0x400013cc; -phy_force_pwr_index = 0x400013d0; -phy_fft_scale_force = 0x400013d4; -phy_force_rx_gain = 0x400013d8; -phy_wifi_enable_set = 0x400013dc; -phy_bb_wdt_rst_enable = 0x400013e0; -phy_bb_wdt_int_enable = 0x400013e4; -phy_bb_wdt_timeout_clear = 0x400013e8; -phy_bb_wdt_get_status = 0x400013ec; -phy_iq_est_enable = 0x400013f0; -phy_iq_est_disable = 0x400013f4; -phy_dc_iq_est = 0x400013f8; -phy_set_cal_rxdc = 0x400013fc; -phy_rxiq_get_mis = 0x40001400; -phy_rxiq_cover_mg_mp = 0x40001404; -phy_rfcal_rxiq = 0x40001408; -phy_get_rfcal_rxiq_data = 0x4000140c; -phy_get_dco_comp = 0x40001410; -phy_pbus_rx_dco_cal = 0x40001414; -phy_rxdc_est_min = 0x40001418; -phy_pbus_rx_dco_cal_1step = 0x4000141c; -phy_get_iq_value = 0x40001420; -phy_set_lb_txiq = 0x40001424; -phy_set_rx_gain_cal_iq = 0x40001428; -phy_set_rx_gain_cal_dc = 0x4000142c; -phy_spur_reg_write_one_tone = 0x40001430; -phy_spur_cal = 0x40001434; -phy_spur_coef_cfg = 0x40001438; -phy_bb_gain_index = 0x4000143c; -phy_rfrx_gain_index = 0x40001440; -phy_set_tsens_power_ = 0x40001444; -phy_set_tsens_range_ = 0x40001448; -phy_get_tsens_value_ = 0x4000144c; -phy_tsens_read_init = 0x40001450; -phy_code_to_temp = 0x40001454; -phy_tsens_dac_to_index = 0x40001458; -phy_tsens_dac_cal = 0x4000145c; -phy_tsens_code_read = 0x40001460; -phy_tsens_temp_read = 0x40001464; -phy_tsens_temp_read_local = 0x40001468; -phy_temp_to_power = 0x4000146c; -phy_txbbgain_to_index = 0x40001470; -phy_index_to_txbbgain = 0x40001474; -phy_bt_index_to_bb = 0x40001478; -phy_bt_bb_to_index = 0x4000147c; -phy_bt_get_tx_gain = 0x40001480; -phy_dig_gain_check = 0x40001484; -phy_wifi_get_tx_gain = 0x40001488; -phy_wifi_11g_rate_chg = 0x4000148c; -phy_set_tx_gain_mem = 0x40001490; -phy_get_rate_fcc_index = 0x40001494; -phy_get_chan_target_power = 0x40001498; -phy_get_tx_gain_value = 0x4000149c; -phy_wifi_get_target_power = 0x400014a0; -phy_wifi_get_tx_tab_ = 0x400014a4; -phy_wifi_set_tx_gain = 0x400014a8; -phy_bt_get_tx_tab_ = 0x400014ac; -phy_bt_set_tx_gain = 0x400014b0; -phy_bt_tx_gain_init = 0x400014b4; -phy_rate_to_index = 0x400014b8; -phy_get_target_pwr = 0x400014bc; -phy_get_max_pwr = 0x400014c0; -phy_get_pwr_index = 0x400014c4; -phy_chip_set_chan_ana = 0x400014d4; -phy_get_romfuncs = 0x400014d8; + /* Data (.data, .bss, .rodata) */ phy_param_rom = 0x4084fc6c; -rom_phyFuns = 0x4084fb84; +rom_phyFuns = 0x4084fc68; rom_phyFuns_eco2 = 0x4084fc68; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld index 2fb70a00f3..0ba656880b 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld @@ -1,14 +1,10 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -/* ROM function interface esp32c61.rom.pp.ld for esp32c61 - * - * - * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457 - * - * Compatible with ROM where ECO version equal or greater to 0. + +/* ROM function interface * * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. */ @@ -27,14 +23,14 @@ esf_buf_recycle = 0x40000b64; GetAccess = 0x40000b68; hal_mac_is_low_rate_enabled = 0x40000b6c; hal_mac_tx_get_blockack = 0x40000b70; -/*hal_mac_tx_set_ppdu = 0x40000b74;*/ +hal_mac_tx_set_ppdu = 0x40000b74; hal_mac_tx_clr_mplen = 0x40000b78; hal_mac_get_txq_state = 0x40000b7c; hal_mac_clr_txq_state = 0x40000b80; hal_mac_get_txq_complete = 0x40000b84; hal_mac_deinit_twt_tx = 0x40000b88; hal_mac_is_dma_enable = 0x40000b8c; -/*hal_he_get_bss_color = 0x40000b90;*/ +hal_he_get_bss_color = 0x40000b90; hal_he_set_ersu = 0x40000b94; hal_he_get_mplen_addr_start = 0x40000b98; hal_he_get_mplen_addr_end = 0x40000b9c; @@ -53,11 +49,6 @@ hal_tsf_get_tbttstart = 0x40000bcc; hal_get_tsf_time = 0x40000bd0; hal_get_sta_tsf = 0x40000bd4; tsf_hal_get_tbtt_interval = 0x40000bd8; -tsf_hal_get_time = 0x400014cc; -/*pm_get_tbtt_count = 0x400014c8;*/ -tsf_hal_get_counter_value = 0x400014d0; -dbg_hal_check_clr_mplen_bitmap = 0x40000bdc; -dbg_hal_check_set_mplen_bitmap = 0x40000be0; ic_get_trc = 0x40000be4; ic_mac_deinit = 0x40000be8; ic_mac_init = 0x40000bec; @@ -81,7 +72,7 @@ lmacRecycleMPDU = 0x40000c30; lmacRxDone = 0x40000c34; lmacSetTxFrame = 0x40000c38; lmacTxDone = 0x40000c3c; -/*lmacTxFrame = 0x40000c40;*/ +lmacTxFrame = 0x40000c40; lmacDisableTransmit = 0x40000c44; lmacDiscardFrameExchangeSequence = 0x40000c48; lmacProcessCollision = 0x40000c4c; @@ -105,7 +96,7 @@ mac_tx_set_plcp1 = 0x40000c90; mac_tx_set_plcp2 = 0x40000c94; mac_tx_set_len = 0x40000c98; mac_tx_set_htsig = 0x40000c9c; -/*mac_tx_set_hesig = 0x40000ca0;*/ +mac_tx_set_hesig = 0x40000ca0; mac_tx_set_tb = 0x40000ca4; mac_tx_set_mplen = 0x40000ca8; mac_tx_set_txop_q = 0x40000cac; @@ -116,14 +107,14 @@ pm_disable_sleep_delay_timer = 0x40000cbc; pm_dream = 0x40000cc0; pm_mac_wakeup = 0x40000cc4; pm_mac_sleep = 0x40000cc8; -/*pm_enable_active_timer = 0x40000ccc;*/ +pm_enable_active_timer = 0x40000ccc; pm_enable_sleep_delay_timer = 0x40000cd0; pm_local_tsf_process = 0x40000cd4; -//pm_set_beacon_filter = 0x40000cd8; -/*pm_is_in_wifi_slice_threshold = 0x40000cdc;*/ +pm_set_beacon_filter = 0x40000cd8; +pm_is_in_wifi_slice_threshold = 0x40000cdc; pm_is_waked = 0x40000ce0; -//pm_keep_alive = 0x40000ce4; -/*pm_on_beacon_rx = 0x40000ce8;*/ +pm_keep_alive = 0x40000ce4; +pm_on_beacon_rx = 0x40000ce8; pm_on_data_rx = 0x40000cec; pm_on_data_tx = 0x40000cf0; pm_on_tbtt = 0x40000cf4; @@ -133,38 +124,38 @@ pm_on_isr_set_twt_target = 0x40000d00; pm_on_isr_twt_wake = 0x40000d04; pm_on_tsf_timer = 0x40000d08; pm_on_twt_force_tx = 0x40000d0c; -/*pm_parse_beacon = 0x40000d10;*/ -/*pm_process_tim = 0x40000d14;*/ +pm_parse_beacon = 0x40000d10; +pm_process_tim = 0x40000d14; pm_rx_beacon_process = 0x40000d18; pm_rx_data_process = 0x40000d1c; pm_sleep = 0x40000d20; pm_sleep_for = 0x40000d24; -/*pm_tbtt_process = 0x40000d28;*/ +pm_tbtt_process = 0x40000d28; pm_tx_data_done_process = 0x40000d2c; pm_allow_tx = 0x40000d30; pm_extend_tbtt_adaptive_servo = 0x40000d34; pm_scale_listen_interval = 0x40000d38; pm_parse_mbssid_element = 0x40000d3c; pm_disconnected_wake = 0x40000d40; -/*pm_tx_data_process = 0x40000d44;*/ +pm_tx_data_process = 0x40000d44; pm_is_twt_awake = 0x40000d48; pm_enable_twt_keep_alive = 0x40000d4c; pm_twt_on_tsf_timer = 0x40000d50; -/*pm_twt_process = 0x40000d54;*/ +pm_twt_process = 0x40000d54; pm_is_twt_start = 0x40000d58; pm_twt_set_target_wdev_time = 0x40000d5c; pm_twt_set_target_tsf = 0x40000d60; pm_enable_twt_keep_alive_timer = 0x40000d64; -/*pm_mac_try_enable_modem_state = 0x40000d68;*/ +pm_mac_try_enable_modem_state = 0x40000d68; pm_beacon_monitor_tbtt_timeout_process = 0x40000d6c; pm_update_next_tbtt = 0x40000d70; pm_twt_disallow_tx = 0x40000d74; pm_clear_wakeup_signal = 0x40000d78; -/*pm_mac_disable_tsf_tbtt_soc_wakeup = 0x40000d7c; +pm_mac_disable_tsf_tbtt_soc_wakeup = 0x40000d7c; pm_mac_disable_tsf_tbtt_modem_wakeup = 0x40000d80; -//pm_mac_enable_tsf_tbtt_soc_wakeup = 0x40000d84; -//pm_mac_enable_tsf_tbtt_modem_wakeup = 0x40000d88; -//pm_mac_modem_params_rt_update = 0x40000d8c;*/ +pm_mac_enable_tsf_tbtt_soc_wakeup = 0x40000d84; +pm_mac_enable_tsf_tbtt_modem_wakeup = 0x40000d88; +pm_mac_modem_params_rt_update = 0x40000d8c; pm_update_at_next_beacon = 0x40000d90; pm_get_null_max_tx_time = 0x40000d94; pm_coex_schm_overall_period_get = 0x40000d98; @@ -184,17 +175,17 @@ ppEmptyDelimiterLength = 0x40000dcc; ppEnqueueRxq = 0x40000dd0; ppEnqueueTxDone = 0x40000dd4; ppGetTxframe = 0x40000dd8; -/*ppMapTxQueue = 0x40000ddc;*/ +ppMapTxQueue = 0x40000ddc; ppProcTxSecFrame = 0x40000de0; ppProcessRxPktHdr = 0x40000de4; -/*ppProcessTxQ = 0x40000de8;*/ +ppProcessTxQ = 0x40000de8; ppRecordBarRRC = 0x40000dec; ppRecycleAmpdu = 0x40000df0; ppRecycleRxPkt = 0x40000df4; ppResortTxAMPDU = 0x40000df8; ppResumeTxAMPDU = 0x40000dfc; ppRxFragmentProc = 0x40000e00; -/*ppRxPkt = 0x40000e04;*/ +ppRxPkt = 0x40000e04; ppRxProtoProc = 0x40000e08; ppSearchTxQueue = 0x40000e0c; ppSearchTxframe = 0x40000e10; @@ -214,7 +205,7 @@ ppMapWaitTxq = 0x40000e44; ppProcessWaitingQueue = 0x40000e48; ppDisableQueue = 0x40000e4c; ppCheckTxRTS = 0x40000e50; -/*ppProcessLifeTime = 0x40000e54;*/ +ppProcessLifeTime = 0x40000e54; ppProcTxCallback = 0x40000e58; ppCalPreFecPaddingFactor = 0x40000e5c; ppCalDeliNum = 0x40000e60; @@ -228,7 +219,7 @@ pp_coex_tx_release = 0x40000e7c; ppAdd2AMPDUTail = 0x40000e80; ppDirectRecycleAmpdu = 0x40000e84; ppRegressAmpdu = 0x40000e88; -/*pp_timer_do_process = 0x40000e8c;*/ +pp_timer_do_process = 0x40000e8c; rcGetAmpduSched = 0x40000e90; rcUpdateRxDone = 0x40000e94; rc_get_trc = 0x40000e98; @@ -238,7 +229,7 @@ rcampduuprate = 0x40000ea4; rcClearCurAMPDUSched = 0x40000ea8; rcClearCurSched = 0x40000eac; rcClearCurStat = 0x40000eb0; -/* rcGetSched = 0x40000eb4;*/ +rcGetSched = 0x40000eb4; rcLowerSched = 0x40000eb8; rcSetTxAmpduLimit = 0x40000ebc; rcTxUpdatePer = 0x40000ec0; @@ -278,7 +269,7 @@ wdev_mac_special_reg_store = 0x40000f44; wdev_mac_wakeup = 0x40000f48; wdev_mac_sleep = 0x40000f4c; wDev_ProcessFiq = 0x40000f50; -/*wDev_ProcessRxSucData = 0x40000f54;*/ +wDev_ProcessRxSucData = 0x40000f54; wdevProcessRxSucDataAll = 0x40000f58; wdev_csi_len_align = 0x40000f5c; wDev_IndicateBeaconMemoryFrame = 0x40000f60; @@ -290,8 +281,6 @@ wdev_process_tsf_timer = 0x40000f74; wdev_process_beacon_filter = 0x40000f78; wdev_process_mac_modem_beacon_miss = 0x40000f7c; config_is_cache_tx_buf_enabled = 0x40000f80; -config_get_wifi_feature_capabilities = 0x40000f84; -config_get_wifi_ampdu_tx_hetb_tid_limit = 0x40000f88; esp_test_disable_tx_statistics = 0x40000f8c; esp_test_enable_tx_statistics = 0x40000f90; esp_test_clr_tx_statistics = 0x40000f94; @@ -451,3 +440,33 @@ g_pp_timer_info_ptr = 0x4084fc98; g_rts_threshold_bytes_ptr = 0x4084fc94; g_he_max_apep_length_tab_ptr = 0x4084fc90; s_tbttstart = 0x4084fc88; + + +/*************************************** + Group rom_pp + ***************************************/ + +/* Functions */ +pm_get_tbtt_count = 0x400014c8; +tsf_hal_get_time = 0x400014cc; +tsf_hal_get_counter_value = 0x400014d0; + +/*************************************** + Group rom_pp + ***************************************/ + +/* Functions */ +pm_save_tbtt_info = 0x40001550; +pm_beacon_offset_is_enabled = 0x40001554; +pm_beacon_offset_is_sampling = 0x40001558; +pm_beacon_offset_add_total_counter = 0x4000155c; +pm_beacon_offset_add_loss_counter = 0x40001560; +pm_beacon_offset_check = 0x40001564; +pm_beacon_offset_get_average = 0x40001568; +pm_beacon_offset_get_expect = 0x4000156c; +pm_beacon_offset_get_params = 0x40001570; +pm_beacon_monitor_tbtt_stop = 0x40001574; +pm_enable_max_idle_timer = 0x40001578; +/* Data (.data, .bss, .rodata) */ +s_pm_beacon_offset_ptr = 0x4084fc64; +s_pm_beacon_offset_config_ptr = 0x4084fc60; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.rvfp.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.rvfp.ld index 272c33c464..48e0ee2269 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.rvfp.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.rvfp.ld @@ -1,14 +1,10 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -/* ROM function interface esp32c61.rom.rvfp.ld for esp32c61 - * - * - * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457 - * - * Compatible with ROM where ECO version equal or greater to 0. + +/* ROM function interface * * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. */ @@ -61,9 +57,10 @@ __muldf3 = 0x40000a14; __nedf2 = 0x40000a18; __subdf3 = 0x40000a1c; + /*************************************** Group libgcc -***************************************/ + ***************************************/ /* Functions */ __divsf3 = 0x40000828; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld index 9f260f5ecd..9c61433ef0 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,9 +9,8 @@ ***************************************/ /* Functions */ -/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */ -/* systimer_hal_init = 0x400003d0; */ -/* systimer_hal_deinit = 0x400003d4; */ +systimer_hal_init = 0x400003d0; +systimer_hal_deinit = 0x400003d4; systimer_hal_set_tick_rate_ops = 0x400003d8; systimer_hal_get_counter_value = 0x400003dc; systimer_hal_get_time = 0x400003e0; diff --git a/components/esp_rom/linker.lf b/components/esp_rom/linker.lf index e856312648..944abe90a8 100644 --- a/components/esp_rom/linker.lf +++ b/components/esp_rom/linker.lf @@ -9,8 +9,6 @@ entries: esp_rom_cache_esp32s2_esp32s3 (noflash) if ESP_ROM_HAS_CACHE_WRITEBACK_BUG = y: esp_rom_cache_writeback_esp32s3 (noflash) - if ESP_ROM_CACHE_WB_INVLD_LOW_RANGE = y: - esp_rom_cache_esp32c61 (noflash) if HEAP_TLSF_USE_ROM_IMPL = y && (ESP_ROM_TLSF_CHECK_PATCH = y || HEAP_TLSF_CHECK_PATCH = y): esp_rom_tlsf (noflash) if SOC_SYSTIMER_SUPPORTED = y: diff --git a/components/esp_rom/patches/esp_rom_cache_esp32c61.c b/components/esp_rom/patches/esp_rom_cache_esp32c61.c deleted file mode 100644 index 6fddfb7500..0000000000 --- a/components/esp_rom/patches/esp_rom_cache_esp32c61.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include "sdkconfig.h" -#include "esp_rom_caps.h" -#include "soc/soc_caps.h" -#include "soc/cache_reg.h" -#include "soc/cache_struct.h" -#include "soc/ext_mem_defs.h" -#include "hal/assert.h" -#include "esp32c61/rom/cache.h" - -#include "esp_rom_sys.h" - -#define CACHE_MAX_SYNC_NUM ((CACHE_SYNC_SIZE + 1) >> 1) - -/** - * @brief Sync Cache items - * - * @param type sync type - * @param addr address - * @param bytes bytes to be synced - */ -__attribute__((always_inline)) -static inline void s_cache_sync_items(uint32_t type, uint32_t addr, uint32_t bytes) -{ - REG_WRITE(CACHE_SYNC_ADDR_REG, addr); - REG_SET_FIELD(CACHE_SYNC_SIZE_REG, CACHE_SYNC_SIZE, bytes); - REG_SET_BIT(CACHE_SYNC_CTRL_REG, type); - while (!REG_GET_BIT(CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE)) - ; -} - -int Cache_Invalidate_Addr(uint32_t vaddr, uint32_t size) -{ - uint32_t plus = 0; - uint32_t cache_line_size = 32; - uint32_t cache_max_sync_size = CACHE_MAX_SYNC_NUM; - if (size == 0) { - HAL_ASSERT(false); - } - //aligned start address to cache line size - plus = vaddr & (cache_line_size - 1); - vaddr -= plus; - //make the length fit the start address - size += plus; - //aligned the length to cache line size(0->0) - size = (size + cache_line_size - 1) & ~(cache_line_size - 1); - - while (size > 0) { - //aligned to cache_max_sync_size, (0->cache_max_sync_size) - uint32_t this_size = ((vaddr + cache_max_sync_size) & ~(cache_max_sync_size - 1)) - vaddr; - if (this_size > size) { - this_size = size; - } - s_cache_sync_items(CACHE_SYNC_INVALIDATE, vaddr, this_size); - vaddr += this_size; - size -= this_size; - } - - return 0; -} - -int Cache_WriteBack_Addr(uint32_t vaddr, uint32_t size) -{ - uint32_t plus = 0; - uint32_t cache_line_size = 32; - uint32_t cache_max_sync_size = CACHE_MAX_SYNC_NUM; - if (size == 0) { - HAL_ASSERT(false); - } - //aligned start address to cache line size - plus = vaddr & (cache_line_size - 1); - vaddr -= plus; - //make the length fit the start address - size += plus; - //aligned the length to cache line size(0->0) - size = (size + cache_line_size - 1) & ~(cache_line_size - 1); - - while (size > 0) { - //aligned to cache_max_sync_size, (0->cache_max_sync_size) - uint32_t this_size = ((vaddr + cache_max_sync_size) & ~(cache_max_sync_size - 1)) - vaddr; - if (this_size > size) { - this_size = size; - } - s_cache_sync_items(CACHE_SYNC_WRITEBACK, vaddr, this_size); - vaddr += this_size; - size -= this_size; - } - - return 0; -} diff --git a/components/esp_rom/patches/esp_rom_systimer.c b/components/esp_rom/patches/esp_rom_systimer.c index df08c91aed..52f193560f 100644 --- a/components/esp_rom/patches/esp_rom_systimer.c +++ b/components/esp_rom/patches/esp_rom_systimer.c @@ -64,7 +64,7 @@ void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t co } #endif // CONFIG_IDF_TARGET_ESP32C2 && (CONFIG_ESP32C2_REV_MIN_FULL < 200) -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4 +#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4 void systimer_hal_init(systimer_hal_context_t *hal) { hal->dev = &SYSTIMER; @@ -78,6 +78,6 @@ void systimer_hal_deinit(systimer_hal_context_t *hal) systimer_ll_enable_clock(hal->dev, false); hal->dev = NULL; } -#endif // CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4 +#endif // CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4 #endif // CONFIG_HAL_SYSTIMER_USE_ROM_IMPL diff --git a/components/esp_wifi/test_apps/bin_size_apsta/README.md b/components/esp_wifi/test_apps/bin_size_apsta/README.md index 1c35092948..0c839f750c 100644 --- a/components/esp_wifi/test_apps/bin_size_apsta/README.md +++ b/components/esp_wifi/test_apps/bin_size_apsta/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_wifi/test_apps/wifi_connect/README.md b/components/esp_wifi/test_apps/wifi_connect/README.md index 1c35092948..0c839f750c 100644 --- a/components/esp_wifi/test_apps/wifi_connect/README.md +++ b/components/esp_wifi/test_apps/wifi_connect/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_wifi/test_apps/wifi_function/README.md b/components/esp_wifi/test_apps/wifi_function/README.md index aa42f91b6b..097edbf0c4 100644 --- a/components/esp_wifi/test_apps/wifi_function/README.md +++ b/components/esp_wifi/test_apps/wifi_function/README.md @@ -1,3 +1,3 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/esp_wifi/test_apps/wifi_nvs_config/README.md b/components/esp_wifi/test_apps/wifi_nvs_config/README.md index 1c35092948..0c839f750c 100644 --- a/components/esp_wifi/test_apps/wifi_nvs_config/README.md +++ b/components/esp_wifi/test_apps/wifi_nvs_config/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/hal/esp32c61/include/hal/gpio_ll.h b/components/hal/esp32c61/include/hal/gpio_ll.h index d8c3603db8..11048e7d56 100644 --- a/components/hal/esp32c61/include/hal/gpio_ll.h +++ b/components/hal/esp32c61/include/hal/gpio_ll.h @@ -38,7 +38,7 @@ extern "C" { #define GPIO_LL_PRO_CPU_INTR_ENA (BIT(0)) #define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(1)) -#define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTR_SOURCE +#define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTERRUPT_PRO_SOURCE /** * @brief Get the configuration for an IO diff --git a/components/hal/esp32c61/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32c61/include/hal/usb_serial_jtag_ll.h index ba16f6f8a3..66f01baeb3 100644 --- a/components/hal/esp32c61/include/hal/usb_serial_jtag_ll.h +++ b/components/hal/esp32c61/include/hal/usb_serial_jtag_ll.h @@ -116,7 +116,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len) int i; for (i = 0; i < (int)rd_len; i++) { if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break; - buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte; + buf[i] = USB_SERIAL_JTAG.ep1.val; } return i; } @@ -135,7 +135,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w int i; for (i = 0; i < (int)wr_len; i++) { if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break; - USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i]; + USB_SERIAL_JTAG.ep1.val = buf[i]; } return i; } diff --git a/components/soc/esp32c61/gdma_periph.c b/components/soc/esp32c61/gdma_periph.c index 57f237677f..c6487bf660 100644 --- a/components/soc/esp32c61/gdma_periph.c +++ b/components/soc/esp32c61/gdma_periph.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,8 +30,8 @@ const gdma_signal_conn_t gdma_periph_signals = { AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_PRI_CH0_REG AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG + AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG + AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG @@ -40,7 +40,7 @@ const gdma_signal_conn_t gdma_periph_signals = { #define G0P0_RETENTION_REGS_CNT_0 13 #define G0P0_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH0_REG #define G0P0_RETENTION_REGS_CNT_1 12 -#define G0P0_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG +#define G0P0_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG static const uint32_t g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0}; static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0}; static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { @@ -68,8 +68,8 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_PRI_CH1_REG AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG + AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG + AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG @@ -78,7 +78,7 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { #define G0P1_RETENTION_REGS_CNT_0 13 #define G0P1_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH1_REG #define G0P1_RETENTION_REGS_CNT_1 12 -#define G0P1_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG +#define G0P1_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG static const uint32_t g0p1_regs_map0[4] = {0x81001, 0x0, 0xc00604c0, 0x604}; static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0}; static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 6dfcfb6605..123eae8110 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -31,10 +31,6 @@ config SOC_GPTIMER_SUPPORTED bool default y -config SOC_BT_SUPPORTED - bool - default y - config SOC_USB_SERIAL_JTAG_SUPPORTED bool default y @@ -47,14 +43,6 @@ config SOC_TEMP_SENSOR_SUPPORTED bool default y -config SOC_PHY_SUPPORTED - bool - default y - -config SOC_WIFI_SUPPORTED - bool - default y - config SOC_SUPPORTS_SECURE_DL_MODE bool default y @@ -1214,83 +1202,3 @@ config SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION config SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN bool default y - -config SOC_WIFI_HW_TSF - bool - default y - -config SOC_WIFI_FTM_SUPPORT - bool - default n - -config SOC_WIFI_GCMP_SUPPORT - bool - default y - -config SOC_WIFI_WAPI_SUPPORT - bool - default y - -config SOC_WIFI_CSI_SUPPORT - bool - default y - -config SOC_WIFI_MESH_SUPPORT - bool - default y - -config SOC_WIFI_HE_SUPPORT - bool - default y - -config SOC_WIFI_MAC_VERSION_NUM - int - default 3 - -config SOC_WIFI_NAN_SUPPORT - bool - default y - -config SOC_BLE_SUPPORTED - bool - default y - -config SOC_BLE_MESH_SUPPORTED - bool - default y - -config SOC_ESP_NIMBLE_CONTROLLER - bool - default y - -config SOC_BLE_50_SUPPORTED - bool - default y - -config SOC_BLE_DEVICE_PRIVACY_SUPPORTED - bool - default y - -config SOC_BLE_POWER_CONTROL_SUPPORTED - bool - default y - -config SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED - bool - default y - -config SOC_BLUFI_SUPPORTED - bool - default y - -config SOC_BLE_MULTI_CONN_OPTIMIZATION - bool - default y - -config SOC_BLE_CTE_SUPPORTED - bool - default y - -config SOC_PHY_COMBO_MODULE - bool - default y diff --git a/components/soc/esp32c61/include/soc/gpio_sig_map.h b/components/soc/esp32c61/include/soc/gpio_sig_map.h index 10eb7cec7a..7eb822bffe 100644 --- a/components/soc/esp32c61/include/soc/gpio_sig_map.h +++ b/components/soc/esp32c61/include/soc/gpio_sig_map.h @@ -1,12 +1,11 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once -// version date 2310090 #define EXT_ADC_START_IDX 0 #define LEDC_LS_SIG_OUT0_IDX 0 #define LEDC_LS_SIG_OUT1_IDX 1 @@ -141,6 +140,7 @@ #define GPIO_TASK_MATRIX_OUT2_IDX 120 #define GPIO_EVENT_MATRIX_IN3_IDX 121 #define GPIO_TASK_MATRIX_OUT3_IDX 121 +#define SDIO_TOHOST_INT_OUT_IDX 124 #define CLK_OUT_OUT1_IDX 126 #define CLK_OUT_OUT2_IDX 127 #define CLK_OUT_OUT3_IDX 128 @@ -176,5 +176,5 @@ #define MODEM_DIAG29_IDX 158 #define MODEM_DIAG30_IDX 159 #define MODEM_DIAG31_IDX 160 - +// version date 2310090 #define SIG_GPIO_OUT_IDX 256 diff --git a/components/soc/esp32c61/include/soc/interrupt_reg.h b/components/soc/esp32c61/include/soc/interrupt_reg.h index 7dffc583d0..d94be8a2ae 100644 --- a/components/soc/esp32c61/include/soc/interrupt_reg.h +++ b/components/soc/esp32c61/include/soc/interrupt_reg.h @@ -14,5 +14,3 @@ #define INTERRUPT_CURRENT_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG) #define INTERRUPT_CORE0_CPU_INT_THRESH_REG INTERRUPT_CURRENT_CORE_INT_THRESH_REG - -#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTMTX_BASE diff --git a/components/soc/esp32c61/include/soc/interrupts.h b/components/soc/esp32c61/include/soc/interrupts.h index ab18526851..97a33ee181 100644 --- a/components/soc/esp32c61/include/soc/interrupts.h +++ b/components/soc/esp32c61/include/soc/interrupts.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -35,15 +35,15 @@ typedef enum { ETS_LP_WDT_INTR_SOURCE, ETS_LP_PERI_TIMEOUT_INTR_SOURCE, ETS_LP_APM_M0_INTR_SOURCE, - ETS_FROM_CPU_INTR0_SOURCE, - ETS_FROM_CPU_INTR1_SOURCE, - ETS_FROM_CPU_INTR2_SOURCE, - ETS_FROM_CPU_INTR3_SOURCE, + ETS_CPU_INTR_FROM_CPU_0_SOURCE, + ETS_CPU_INTR_FROM_CPU_1_SOURCE, + ETS_CPU_INTR_FROM_CPU_2_SOURCE, + ETS_CPU_INTR_FROM_CPU_3_SOURCE, ETS_ASSIST_DEBUG_INTR_SOURCE, ETS_TRACE_INTR_SOURCE, ETS_CACHE_INTR_SOURCE, ETS_CPU_PERI_TIMEOUT_INTR_SOURCE, - ETS_GPIO_INTR_SOURCE, + ETS_GPIO_INTERRUPT_PRO_SOURCE, ETS_GPIO_INTERRUPT_EXT_SOURCE, ETS_PAU_INTR_SOURCE, ETS_HP_PERI_TIMEOUT_INTR_SOURCE, @@ -52,6 +52,8 @@ typedef enum { ETS_HP_APM_M1_INTR_SOURCE, ETS_HP_APM_M2_INTR_SOURCE, ETS_HP_APM_M3_INTR_SOURCE, + ETS_CPU_APM_M0_INTR_SOURCE, + ETS_CPU_APM_M1_INTR_SOURCE, ETS_MSPI_INTR_SOURCE, ETS_I2S0_INTR_SOURCE, ETS_UART0_INTR_SOURCE, @@ -62,16 +64,18 @@ typedef enum { ETS_I2C_EXT0_INTR_SOURCE, ETS_TG0_T0_INTR_SOURCE, ETS_TG0_T1_INTR_SOURCE, - ETS_TG0_WDT_LEVEL_INTR_SOURCE, + ETS_TG0_WDT_INTR_SOURCE, ETS_TG1_T0_INTR_SOURCE, ETS_TG1_T1_INTR_SOURCE, - ETS_TG1_WDT_LEVEL_INTR_SOURCE, + ETS_TG1_WDT_INTR_SOURCE, ETS_SYSTIMER_TARGET0_INTR_SOURCE, ETS_SYSTIMER_TARGET1_INTR_SOURCE, ETS_SYSTIMER_TARGET2_INTR_SOURCE, - ETS_APB_ADC_INTR_SOURCE = 53, + ETS_APB_ADC_INTR_SOURCE, ETS_TEMPERATURE_SENSOR_INTR_SOURCE = ETS_APB_ADC_INTR_SOURCE, - ETS_DMA_IN_CH0_INTR_SOURCE = 54, + ETS_SLC0_INTR_SOURCE, + ETS_SLC1_INTR_SOURCE, + ETS_DMA_IN_CH0_INTR_SOURCE, ETS_DMA_IN_CH1_INTR_SOURCE, ETS_DMA_OUT_CH0_INTR_SOURCE, ETS_DMA_OUT_CH1_INTR_SOURCE, diff --git a/components/soc/esp32c61/include/soc/pmu_icg_mapping.h b/components/soc/esp32c61/include/soc/pmu_icg_mapping.h index a71ee0a8da..7133c630e3 100644 --- a/components/soc/esp32c61/include/soc/pmu_icg_mapping.h +++ b/components/soc/esp32c61/include/soc/pmu_icg_mapping.h @@ -1,10 +1,11 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once + #define PMU_ICG_APB_ENA_SEC 0 #define PMU_ICG_APB_ENA_GDMA 1 #define PMU_ICG_APB_ENA_SPI2 2 @@ -35,6 +36,7 @@ #define PMU_ICG_FUNC_ENA_I2S_TX 7 #define PMU_ICG_FUNC_ENA_REGDMA 8 #define PMU_ICG_FUNC_ENA_MEM_MONITOR 10 +#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11 #define PMU_ICG_FUNC_ENA_TSENS 12 #define PMU_ICG_FUNC_ENA_TG1 13 #define PMU_ICG_FUNC_ENA_TG0 14 diff --git a/components/soc/esp32c61/include/soc/soc.h b/components/soc/esp32c61/include/soc/soc.h index bf56d907e3..a961fc8ff5 100644 --- a/components/soc/esp32c61/include/soc/soc.h +++ b/components/soc/esp32c61/include/soc/soc.h @@ -22,9 +22,7 @@ #define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C61 #define REG_TIMG_BASE(i) (DR_REG_TIMG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 #define REG_SPI_MEM_BASE(i) (DR_REG_MSPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 -#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C61 #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C61 -#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTMTX_BASE //Registers Operation {{ #define ETS_UNCACHED_ADDR(addr) (addr) diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index 499c1bda59..489c91b559 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -24,13 +24,13 @@ #define SOC_GDMA_SUPPORTED 1 #define SOC_AHB_GDMA_SUPPORTED 1 #define SOC_GPTIMER_SUPPORTED 1 -#define SOC_BT_SUPPORTED 1 +// #define SOC_BT_SUPPORTED 1 // TODO: IDF-13139, re-enable for c61 eco3 // \#define SOC_IEEE802154_SUPPORTED 1 #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 #define SOC_TEMP_SENSOR_SUPPORTED 1 -#define SOC_PHY_SUPPORTED 1 -#define SOC_WIFI_SUPPORTED 1 +// #define SOC_PHY_SUPPORTED 1 //TODO: IDF-13141, re-open for c61 eco3 +// #define SOC_WIFI_SUPPORTED 1 //TODO: IDF-13138, re-open on c61 eco3 #define SOC_SUPPORTS_SECURE_DL_MODE 1 #define SOC_EFUSE_KEY_PURPOSE_FIELD 1 #define SOC_EFUSE_SUPPORTED 1 @@ -498,30 +498,32 @@ #define SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN (1) /*------------------------------------ WI-FI CAPS ------------------------------------*/ -#define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */ -#define SOC_WIFI_FTM_SUPPORT (0) /*!< Support FTM */ -#define SOC_WIFI_GCMP_SUPPORT (1) /*!< Support GCMP(GCMP128 and GCMP256) */ -#define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */ -#define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */ -#define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */ -#define SOC_WIFI_HE_SUPPORT (1) /*!< Support Wi-Fi 6 */ -#define SOC_WIFI_MAC_VERSION_NUM (3) /*!< Wi-Fi MAC version num is 3 */ -#define SOC_WIFI_NAN_SUPPORT (1) /*!< Support WIFI Aware (NAN) */ +//TODO: IDF-13138, re-open on c61 eco3 +// #define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */ +// #define SOC_WIFI_FTM_SUPPORT (0) /*!< Support FTM */ +// #define SOC_WIFI_GCMP_SUPPORT (1) /*!< Support GCMP(GCMP128 and GCMP256) */ +// #define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */ +// #define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */ +// #define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */ +// #define SOC_WIFI_HE_SUPPORT (1) /*!< Support Wi-Fi 6 */ +// #define SOC_WIFI_MAC_VERSION_NUM (3) /*!< Wi-Fi MAC version num is 3 */ +// #define SOC_WIFI_NAN_SUPPORT (1) /*!< Support WIFI Aware (NAN) */ -/*---------------------------------- Bluetooth CAPS ----------------------------------*/ -#define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */ -#define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */ -#define SOC_ESP_NIMBLE_CONTROLLER (1) /*!< Support BLE EMBEDDED controller V1 */ -#define SOC_BLE_50_SUPPORTED (1) /*!< Support Bluetooth 5.0 */ -#define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (1) /*!< Support BLE device privacy mode */ -#define SOC_BLE_POWER_CONTROL_SUPPORTED (1) /*!< Support Bluetooth Power Control */ -#define SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED (1) /*!< Support For BLE Periodic Adv Enhancements */ -#define SOC_BLUFI_SUPPORTED (1) /*!< Support BLUFI */ -#define SOC_BLE_MULTI_CONN_OPTIMIZATION (1) /*!< Support multiple connections optimization */ -#define SOC_BLE_CTE_SUPPORTED (1) /*!< Support Bluetooth LE Constant Tone Extension (CTE) */ +// /*---------------------------------- Bluetooth CAPS ----------------------------------*/ +// TODO: IDF-13139, re-enable for c61 eco3 +// #define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */ +// #define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */ +// #define SOC_ESP_NIMBLE_CONTROLLER (1) /*!< Support BLE EMBEDDED controller V1 */ +// #define SOC_BLE_50_SUPPORTED (1) /*!< Support Bluetooth 5.0 */ +// #define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (1) /*!< Support BLE device privacy mode */ +// #define SOC_BLE_POWER_CONTROL_SUPPORTED (1) /*!< Support Bluetooth Power Control */ +// #define SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED (1) /*!< Support For BLE Periodic Adv Enhancements */ +// #define SOC_BLUFI_SUPPORTED (1) /*!< Support BLUFI */ +// #define SOC_BLE_MULTI_CONN_OPTIMIZATION (1) /*!< Support multiple connections optimization */ +// #define SOC_BLE_CTE_SUPPORTED (1) /*!< Support Bluetooth LE Constant Tone Extension (CTE) */ /*------------------------------------- PHY CAPS -------------------------------------*/ -#define SOC_PHY_COMBO_MODULE (1) /*!< Support Wi-Fi, BLE and 15.4*/ +// #define SOC_PHY_COMBO_MODULE (1) /*!< Support Wi-Fi, BLE and 15.4*/ /*------------------------------------- No Reset CAPS -------------------------------------*/ // \#define SOC_CAPS_NO_RESET_BY_ANA_BOD (1) //TODO: [ESP32C61] IDF-9254 diff --git a/components/soc/esp32c61/include/soc/system_intr.h b/components/soc/esp32c61/include/soc/system_intr.h index 9289296b49..b1d0bf0939 100644 --- a/components/soc/esp32c61/include/soc/system_intr.h +++ b/components/soc/esp32c61/include/soc/system_intr.h @@ -8,10 +8,10 @@ #include "soc/interrupts.h" // Maps misc system interrupt to hardware interrupt names -#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_FROM_CPU_INTR0_SOURCE -#define SYS_CPU_INTR_FROM_CPU_1_SOURCE ETS_FROM_CPU_INTR1_SOURCE -#define SYS_CPU_INTR_FROM_CPU_2_SOURCE ETS_FROM_CPU_INTR2_SOURCE -#define SYS_CPU_INTR_FROM_CPU_3_SOURCE ETS_FROM_CPU_INTR3_SOURCE +#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_CPU_INTR_FROM_CPU_0_SOURCE +#define SYS_CPU_INTR_FROM_CPU_1_SOURCE ETS_CPU_INTR_FROM_CPU_1_SOURCE +#define SYS_CPU_INTR_FROM_CPU_2_SOURCE ETS_CPU_INTR_FROM_CPU_2_SOURCE +#define SYS_CPU_INTR_FROM_CPU_3_SOURCE ETS_CPU_INTR_FROM_CPU_3_SOURCE -#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE -#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE +#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_INTR_SOURCE +#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_INTR_SOURCE diff --git a/components/soc/esp32c61/interrupts.c b/components/soc/esp32c61/interrupts.c index 8ed40cbd50..a0b2e378b9 100644 --- a/components/soc/esp32c61/interrupts.c +++ b/components/soc/esp32c61/interrupts.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -43,30 +43,34 @@ const char *const esp_isr_names[] = { [33] = "HP_APM_M1", [34] = "HP_APM_M2", [35] = "HP_APM_M3", - [36] = "MSPI", - [37] = "I2S1", - [38] = "UART0", - [39] = "UART1", - [40] = "UART2", - [41] = "LEDC", - [42] = "USB", - [43] = "I2C_EXT0", - [44] = "TG0_T0", - [45] = "TG0_T1", - [46] = "TG0_WDT", - [47] = "TG1_T0", - [48] = "TG1_T1", - [49] = "TG1_WDT", - [50] = "SYSTIMER_TARGET0", - [51] = "SYSTIMER_TARGET1", - [52] = "SYSTIMER_TARGET2", - [53] = "APB_ADC", - [54] = "DMA_IN_CH0", - [55] = "DMA_IN_CH1", - [56] = "DMA_OUT_CH0", - [57] = "DMA_OUT_CH1", - [58] = "GPSPI2", - [59] = "SHA", - [60] = "ECC", - [61] = "ECDSA", + [36] = "CPU_APM_M0", + [37] = "CPU_APM_M1", + [38] = "MSPI", + [39] = "I2S0", + [40] = "UART0", + [41] = "UART1", + [42] = "UART2", + [43] = "LEDC", + [44] = "USB", + [45] = "I2C_EXT0", + [46] = "TG0_T0", + [47] = "TG0_T1", + [48] = "TG0_WDT", + [49] = "TG1_T0", + [50] = "TG1_T1", + [51] = "TG1_WDT", + [52] = "SYSTIMER_TARGET0", + [53] = "SYSTIMER_TARGET1", + [54] = "SYSTIMER_TARGET2", + [55] = "APB_ADC", + [56] = "SLC0", + [57] = "SLC1", + [58] = "DMA_IN_CH0", + [59] = "DMA_IN_CH1", + [60] = "DMA_OUT_CH0", + [61] = "DMA_OUT_CH1", + [62] = "GPSPI2", + [63] = "SHA", + [64] = "ECC", + [65] = "ECDSA", }; diff --git a/components/soc/esp32c61/ld/esp32c61.peripherals.ld b/components/soc/esp32c61/ld/esp32c61.peripherals.ld index 6dc1a45c3d..9acd0c257d 100644 --- a/components/soc/esp32c61/ld/esp32c61.peripherals.ld +++ b/components/soc/esp32c61/ld/esp32c61.peripherals.ld @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -20,8 +20,10 @@ PROVIDE ( ADC = 0x6000E000 ); PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 ); PROVIDE ( INTMTX = 0x60010000 ); PROVIDE ( SOC_ETM = 0x60013000 ); -PROVIDE ( PVT_MONITOR = 0x60019000 ); -PROVIDE ( PSRAM_MEM_MONITOR = 0x6001A000 ); +PROVIDE ( HINF = 0x60016000 ); +PROVIDE ( SLC = 0x60017000 ); +PROVIDE ( HOST = 0x60018000 ); +PROVIDE ( PVT = 0x60019000 ); PROVIDE ( AHB_DMA = 0x60080000 ); PROVIDE ( GPSPI2 = 0x60081000 ); PROVIDE ( SHA = 0x60089000 ); @@ -31,19 +33,15 @@ PROVIDE ( IO_MUX = 0x60090000 ); PROVIDE ( GPIO = 0x60091000 ); PROVIDE ( GPIO_EXT = 0x60091e00 ); PROVIDE ( GPIO_ETM = 0x60091f18 ); -PROVIDE ( TCM_MEM_MONITOR = 0x60092000 ); +PROVIDE ( MEM_MONITOR = 0x60092000 ); PROVIDE ( PAU = 0x60093000 ); PROVIDE ( HP_SYSTEM = 0x60095000 ); PROVIDE ( PCR = 0x60096000 ); PROVIDE ( TEE = 0x60098000 ); PROVIDE ( HP_APM = 0x60099000 ); -PROVIDE ( MISC = 0x6009F000 ); PROVIDE ( MODEM_SYSCON = 0x600A9C00 ); PROVIDE ( MODEM_LPCON = 0x600AF000 ); -PROVIDE ( MODEM0 = 0x600A0000 ); -PROVIDE ( MODEM1 = 0x600AC000 ); -PROVIDE ( MODEM_PWR0 = 0x600AD000 ); -PROVIDE ( MODEM_PWR1 = 0x600AF000 ); +PROVIDE ( CPU_APM_REG = 0x6009A000 ); PROVIDE ( PMU = 0x600B0000 ); PROVIDE ( LP_CLKRST = 0x600B0400 ); PROVIDE ( LP_TIMER = 0x600B0C00 ); @@ -56,7 +54,7 @@ PROVIDE ( LP_APM = 0x600B3800 ); PROVIDE ( LP_IO_MUX = 0x600B4000 ); PROVIDE ( LP_GPIO = 0x600B4400 ); PROVIDE ( EFUSE0 = 0x600B4800 ); -PROVIDE ( EFUSE1 = 0x600B4C00 ); +PROVIDE ( OTP_DEBUG = 0x600B4C00 ); PROVIDE ( TRACE = 0x600C0000 ); PROVIDE ( BUS_MONITOR = 0x600C2000 ); PROVIDE ( INTPRI = 0x600C5000 ); diff --git a/components/soc/esp32c61/register/soc/ahb_dma_reg.h b/components/soc/esp32c61/register/soc/ahb_dma_reg.h index 1fdb0969fa..c1a6e9375d 100644 --- a/components/soc/esp32c61/register/soc/ahb_dma_reg.h +++ b/components/soc/esp32c61/register/soc/ahb_dma_reg.h @@ -1,7 +1,7 @@ /** - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -12,826 +12,957 @@ extern "C" { #endif /** AHB_DMA_IN_INT_RAW_CH0_REG register - * RX channel 0 raw interrupt status register + * Raw interrupt status of RX channel 0 */ #define AHB_DMA_IN_INT_RAW_CH0_REG (DR_REG_AHB_DMA_BASE + 0x0) /** AHB_DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DONE_CH0_INT. + * The raw interrupt status of AHB_DMA_IN_DONE_CH0_INT */ #define AHB_DMA_IN_DONE_CH0_INT_RAW (BIT(0)) #define AHB_DMA_IN_DONE_CH0_INT_RAW_M (AHB_DMA_IN_DONE_CH0_INT_RAW_V << AHB_DMA_IN_DONE_CH0_INT_RAW_S) #define AHB_DMA_IN_DONE_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DONE_CH0_INT_RAW_S 0 /** AHB_DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT. + * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT */ #define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_M (AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_S) #define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_S 1 /** AHB_DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT. + * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT */ #define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_M (AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_S) #define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_S 2 /** AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT. + * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT */ #define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_S) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT. + * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 4 /** AHB_DMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT. + * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT */ #define AHB_DMA_INFIFO_OVF_CH0_INT_RAW (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_M (AHB_DMA_INFIFO_OVF_CH0_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH0_INT_RAW_S) #define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_S 5 /** AHB_DMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT. + * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT */ #define AHB_DMA_INFIFO_UDF_CH0_INT_RAW (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_M (AHB_DMA_INFIFO_UDF_CH0_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH0_INT_RAW_S) #define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_S 7 /** AHB_DMA_IN_INT_ST_CH0_REG register - * RX channel 0 masked interrupt status register + * Masked interrupt status of RX channel 0 */ #define AHB_DMA_IN_INT_ST_CH0_REG (DR_REG_AHB_DMA_BASE + 0x4) /** AHB_DMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DONE_CH0_INT. + * The masked interrupt status of AHB_DMA_IN_DONE_CH0_INT */ #define AHB_DMA_IN_DONE_CH0_INT_ST (BIT(0)) #define AHB_DMA_IN_DONE_CH0_INT_ST_M (AHB_DMA_IN_DONE_CH0_INT_ST_V << AHB_DMA_IN_DONE_CH0_INT_ST_S) #define AHB_DMA_IN_DONE_CH0_INT_ST_V 0x00000001U #define AHB_DMA_IN_DONE_CH0_INT_ST_S 0 /** AHB_DMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT. + * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT */ #define AHB_DMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_M (AHB_DMA_IN_SUC_EOF_CH0_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH0_INT_ST_S) #define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_S 1 /** AHB_DMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT. + * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT */ #define AHB_DMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_M (AHB_DMA_IN_ERR_EOF_CH0_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH0_INT_ST_S) #define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_S 2 /** AHB_DMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT. + * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT */ #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_S) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT. + * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S 4 /** AHB_DMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT. + * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT */ #define AHB_DMA_INFIFO_OVF_CH0_INT_ST (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH0_INT_ST_M (AHB_DMA_INFIFO_OVF_CH0_INT_ST_V << AHB_DMA_INFIFO_OVF_CH0_INT_ST_S) #define AHB_DMA_INFIFO_OVF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH0_INT_ST_S 5 /** AHB_DMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT. + * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT */ #define AHB_DMA_INFIFO_UDF_CH0_INT_ST (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH0_INT_ST_M (AHB_DMA_INFIFO_UDF_CH0_INT_ST_V << AHB_DMA_INFIFO_UDF_CH0_INT_ST_S) #define AHB_DMA_INFIFO_UDF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH0_INT_ST_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_S 7 /** AHB_DMA_IN_INT_ENA_CH0_REG register - * RX channel 0 interrupt enable register + * Interrupt enable bits of RX channel 0 */ #define AHB_DMA_IN_INT_ENA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x8) /** AHB_DMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_IN_DONE_CH0_INT. + * Write 1 to enable AHB_DMA_IN_DONE_CH0_INT */ #define AHB_DMA_IN_DONE_CH0_INT_ENA (BIT(0)) #define AHB_DMA_IN_DONE_CH0_INT_ENA_M (AHB_DMA_IN_DONE_CH0_INT_ENA_V << AHB_DMA_IN_DONE_CH0_INT_ENA_S) #define AHB_DMA_IN_DONE_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DONE_CH0_INT_ENA_S 0 /** AHB_DMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH0_INT. + * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH0_INT */ #define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_M (AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_S) #define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_S 1 /** AHB_DMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH0_INT. + * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH0_INT */ #define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_M (AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_S) #define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_S 2 /** AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH0_INT. + * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH0_INT */ #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_S) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH0_INT. + * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH0_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 4 /** AHB_DMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_OVF_CH0_INT. + * Write 1 to enable AHB_DMA_INFIFO_OVF_CH0_INT */ #define AHB_DMA_INFIFO_OVF_CH0_INT_ENA (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_M (AHB_DMA_INFIFO_OVF_CH0_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH0_INT_ENA_S) #define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_S 5 /** AHB_DMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_UDF_CH0_INT. + * Write 1 to enable AHB_DMA_INFIFO_UDF_CH0_INT */ #define AHB_DMA_INFIFO_UDF_CH0_INT_ENA (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_M (AHB_DMA_INFIFO_UDF_CH0_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH0_INT_ENA_S) #define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA : R/W; bitpos: [7]; default: 0; + * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH0_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_S 7 /** AHB_DMA_IN_INT_CLR_CH0_REG register - * RX channel 0 interrupt clear register + * Interrupt clear bits of RX channel 0 */ #define AHB_DMA_IN_INT_CLR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xc) /** AHB_DMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_IN_DONE_CH0_INT. + * Write 1 to clear AHB_DMA_IN_DONE_CH0_INT */ #define AHB_DMA_IN_DONE_CH0_INT_CLR (BIT(0)) #define AHB_DMA_IN_DONE_CH0_INT_CLR_M (AHB_DMA_IN_DONE_CH0_INT_CLR_V << AHB_DMA_IN_DONE_CH0_INT_CLR_S) #define AHB_DMA_IN_DONE_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DONE_CH0_INT_CLR_S 0 /** AHB_DMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH0_INT. + * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH0_INT */ #define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_M (AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_S) #define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_S 1 /** AHB_DMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH0_INT. + * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH0_INT */ #define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_M (AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_S) #define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_S 2 /** AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH0_INT. + * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH0_INT */ #define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_M (AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_S) #define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH0_INT. + * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH0_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S) #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 4 /** AHB_DMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_OVF_CH0_INT. + * Write 1 to clear AHB_DMA_INFIFO_OVF_CH0_INT */ #define AHB_DMA_INFIFO_OVF_CH0_INT_CLR (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_M (AHB_DMA_INFIFO_OVF_CH0_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH0_INT_CLR_S) #define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_S 5 /** AHB_DMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_UDF_CH0_INT. + * Write 1 to clear AHB_DMA_INFIFO_UDF_CH0_INT */ #define AHB_DMA_INFIFO_UDF_CH0_INT_CLR (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_M (AHB_DMA_INFIFO_UDF_CH0_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH0_INT_CLR_S) #define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR : WT; bitpos: [7]; default: 0; + * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH0_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_S 7 /** AHB_DMA_IN_INT_RAW_CH1_REG register - * RX channel 1 raw interrupt status register + * Raw interrupt status of RX channel 1 */ #define AHB_DMA_IN_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x10) /** AHB_DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DONE_CH1_INT. + * The raw interrupt status of AHB_DMA_IN_DONE_CH1_INT */ #define AHB_DMA_IN_DONE_CH1_INT_RAW (BIT(0)) #define AHB_DMA_IN_DONE_CH1_INT_RAW_M (AHB_DMA_IN_DONE_CH1_INT_RAW_V << AHB_DMA_IN_DONE_CH1_INT_RAW_S) #define AHB_DMA_IN_DONE_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DONE_CH1_INT_RAW_S 0 /** AHB_DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT. + * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT */ #define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_M (AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_S) #define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_S 1 /** AHB_DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT. + * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT */ #define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_M (AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_S) #define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_S 2 /** AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT. + * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT */ #define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_S) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT. + * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 4 /** AHB_DMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT. + * The raw interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT */ #define AHB_DMA_INFIFO_OVF_CH1_INT_RAW (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_M (AHB_DMA_INFIFO_OVF_CH1_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH1_INT_RAW_S) #define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_S 5 /** AHB_DMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT. + * The raw interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT */ #define AHB_DMA_INFIFO_UDF_CH1_INT_RAW (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_M (AHB_DMA_INFIFO_UDF_CH1_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH1_INT_RAW_S) #define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_S 7 /** AHB_DMA_IN_INT_ST_CH1_REG register - * RX channel 1 masked interrupt status register + * Masked interrupt status of RX channel 1 */ #define AHB_DMA_IN_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x14) /** AHB_DMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DONE_CH1_INT. + * The masked interrupt status of AHB_DMA_IN_DONE_CH1_INT */ #define AHB_DMA_IN_DONE_CH1_INT_ST (BIT(0)) #define AHB_DMA_IN_DONE_CH1_INT_ST_M (AHB_DMA_IN_DONE_CH1_INT_ST_V << AHB_DMA_IN_DONE_CH1_INT_ST_S) #define AHB_DMA_IN_DONE_CH1_INT_ST_V 0x00000001U #define AHB_DMA_IN_DONE_CH1_INT_ST_S 0 /** AHB_DMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT. + * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT */ #define AHB_DMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_M (AHB_DMA_IN_SUC_EOF_CH1_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH1_INT_ST_S) #define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_S 1 /** AHB_DMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT. + * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT */ #define AHB_DMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_M (AHB_DMA_IN_ERR_EOF_CH1_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH1_INT_ST_S) #define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_S 2 /** AHB_DMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT. + * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT */ #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_S) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT. + * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S 4 /** AHB_DMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT. + * The masked interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT */ #define AHB_DMA_INFIFO_OVF_CH1_INT_ST (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH1_INT_ST_M (AHB_DMA_INFIFO_OVF_CH1_INT_ST_V << AHB_DMA_INFIFO_OVF_CH1_INT_ST_S) #define AHB_DMA_INFIFO_OVF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH1_INT_ST_S 5 /** AHB_DMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT. + * The masked interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT */ #define AHB_DMA_INFIFO_UDF_CH1_INT_ST (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH1_INT_ST_M (AHB_DMA_INFIFO_UDF_CH1_INT_ST_V << AHB_DMA_INFIFO_UDF_CH1_INT_ST_S) #define AHB_DMA_INFIFO_UDF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH1_INT_ST_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_S 7 /** AHB_DMA_IN_INT_ENA_CH1_REG register - * RX channel 1 interrupt enable register + * Interrupt enable bits of RX channel 1 */ #define AHB_DMA_IN_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x18) /** AHB_DMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_IN_DONE_CH1_INT. + * Write 1 to enable AHB_DMA_IN_DONE_CH1_INT */ #define AHB_DMA_IN_DONE_CH1_INT_ENA (BIT(0)) #define AHB_DMA_IN_DONE_CH1_INT_ENA_M (AHB_DMA_IN_DONE_CH1_INT_ENA_V << AHB_DMA_IN_DONE_CH1_INT_ENA_S) #define AHB_DMA_IN_DONE_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DONE_CH1_INT_ENA_S 0 /** AHB_DMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH1_INT. + * Write 1 to enable AHB_DMA_IN_SUC_EOF_CH1_INT */ #define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_M (AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_S) #define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_S 1 /** AHB_DMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH1_INT. + * Write 1 to enable AHB_DMA_IN_ERR_EOF_CH1_INT */ #define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_M (AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_S) #define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_S 2 /** AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH1_INT. + * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH1_INT */ #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_S) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH1_INT. + * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH1_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 4 /** AHB_DMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_OVF_CH1_INT. + * Write 1 to enable AHB_DMA_INFIFO_OVF_CH1_INT */ #define AHB_DMA_INFIFO_OVF_CH1_INT_ENA (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_M (AHB_DMA_INFIFO_OVF_CH1_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH1_INT_ENA_S) #define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_S 5 /** AHB_DMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_UDF_CH1_INT. + * Write 1 to enable AHB_DMA_INFIFO_UDF_CH1_INT */ #define AHB_DMA_INFIFO_UDF_CH1_INT_ENA (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_M (AHB_DMA_INFIFO_UDF_CH1_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH1_INT_ENA_S) #define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA : R/W; bitpos: [7]; default: 0; + * Write 1 to enable AHB_DMA_IN_RESP_ERR_CH1_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_S 7 /** AHB_DMA_IN_INT_CLR_CH1_REG register - * RX channel 1 interrupt clear register + * Interrupt clear bits of RX channel 1 */ #define AHB_DMA_IN_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1c) /** AHB_DMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_IN_DONE_CH1_INT. + * Write 1 to clear AHB_DMA_IN_DONE_CH1_INT */ #define AHB_DMA_IN_DONE_CH1_INT_CLR (BIT(0)) #define AHB_DMA_IN_DONE_CH1_INT_CLR_M (AHB_DMA_IN_DONE_CH1_INT_CLR_V << AHB_DMA_IN_DONE_CH1_INT_CLR_S) #define AHB_DMA_IN_DONE_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DONE_CH1_INT_CLR_S 0 /** AHB_DMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH1_INT. + * Write 1 to clear AHB_DMA_IN_SUC_EOF_CH1_INT */ #define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) #define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_M (AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_S) #define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_S 1 /** AHB_DMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH1_INT. + * Write 1 to clear AHB_DMA_IN_ERR_EOF_CH1_INT */ #define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) #define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_M (AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_S) #define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_S 2 /** AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH1_INT. + * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH1_INT */ #define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(3)) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_M (AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_S) #define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_S 3 /** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH1_INT. + * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH1_INT */ #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(4)) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S) #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 4 /** AHB_DMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_OVF_CH1_INT. + * Write 1 to clear AHB_DMA_INFIFO_OVF_CH1_INT */ #define AHB_DMA_INFIFO_OVF_CH1_INT_CLR (BIT(5)) #define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_M (AHB_DMA_INFIFO_OVF_CH1_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH1_INT_CLR_S) #define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_S 5 /** AHB_DMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_UDF_CH1_INT. + * Write 1 to clear AHB_DMA_INFIFO_UDF_CH1_INT */ #define AHB_DMA_INFIFO_UDF_CH1_INT_CLR (BIT(6)) #define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_M (AHB_DMA_INFIFO_UDF_CH1_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH1_INT_CLR_S) #define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_S 6 +/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR : WT; bitpos: [7]; default: 0; + * Write 1 to clear AHB_DMA_IN_RESP_ERR_CH1_INT + */ +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR (BIT(7)) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_M (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_S) +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_V 0x00000001U +#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_S 7 /** AHB_DMA_OUT_INT_RAW_CH0_REG register - * TX channel 0 raw interrupt status register + * //Raw interrupt status of TX channel 0 */ #define AHB_DMA_OUT_INT_RAW_CH0_REG (DR_REG_AHB_DMA_BASE + 0x30) /** AHB_DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DONE_CH0_INT. + * The raw interrupt status of AHB_DMA_OUT_DONE_CH0_INT */ #define AHB_DMA_OUT_DONE_CH0_INT_RAW (BIT(0)) #define AHB_DMA_OUT_DONE_CH0_INT_RAW_M (AHB_DMA_OUT_DONE_CH0_INT_RAW_V << AHB_DMA_OUT_DONE_CH0_INT_RAW_S) #define AHB_DMA_OUT_DONE_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_DONE_CH0_INT_RAW_S 0 /** AHB_DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_EOF_CH0_INT. + * The raw interrupt status of AHB_DMA_OUT_EOF_CH0_INT */ #define AHB_DMA_OUT_EOF_CH0_INT_RAW (BIT(1)) #define AHB_DMA_OUT_EOF_CH0_INT_RAW_M (AHB_DMA_OUT_EOF_CH0_INT_RAW_V << AHB_DMA_OUT_EOF_CH0_INT_RAW_S) #define AHB_DMA_OUT_EOF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_EOF_CH0_INT_RAW_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT. + * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT. + * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 3 /** AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT. + * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT */ #define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_S) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_S 4 /** AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT. + * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT */ #define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_S) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_S 6 /** AHB_DMA_OUT_INT_ST_CH0_REG register - * TX channel 0 masked interrupt status register + * Masked interrupt status of TX channel 0 */ #define AHB_DMA_OUT_INT_ST_CH0_REG (DR_REG_AHB_DMA_BASE + 0x34) /** AHB_DMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DONE_CH0_INT. + * The masked interrupt status of AHB_DMA_OUT_DONE_CH0_INT */ #define AHB_DMA_OUT_DONE_CH0_INT_ST (BIT(0)) #define AHB_DMA_OUT_DONE_CH0_INT_ST_M (AHB_DMA_OUT_DONE_CH0_INT_ST_V << AHB_DMA_OUT_DONE_CH0_INT_ST_S) #define AHB_DMA_OUT_DONE_CH0_INT_ST_V 0x00000001U #define AHB_DMA_OUT_DONE_CH0_INT_ST_S 0 /** AHB_DMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_EOF_CH0_INT. + * The masked interrupt status of AHB_DMA_OUT_EOF_CH0_INT */ #define AHB_DMA_OUT_EOF_CH0_INT_ST (BIT(1)) #define AHB_DMA_OUT_EOF_CH0_INT_ST_M (AHB_DMA_OUT_EOF_CH0_INT_ST_V << AHB_DMA_OUT_EOF_CH0_INT_ST_S) #define AHB_DMA_OUT_EOF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_OUT_EOF_CH0_INT_ST_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT. + * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_S) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT. + * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S 3 /** AHB_DMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT. + * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT */ #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_S) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_S 4 /** AHB_DMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT. + * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT */ #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_S) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_S 6 /** AHB_DMA_OUT_INT_ENA_CH0_REG register - * TX channel 0 interrupt enable register + * Interrupt enable bits of TX channel 0 */ #define AHB_DMA_OUT_INT_ENA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x38) /** AHB_DMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DONE_CH0_INT. + * Write 1 to enable AHB_DMA_OUT_DONE_CH0_INT */ #define AHB_DMA_OUT_DONE_CH0_INT_ENA (BIT(0)) #define AHB_DMA_OUT_DONE_CH0_INT_ENA_M (AHB_DMA_OUT_DONE_CH0_INT_ENA_V << AHB_DMA_OUT_DONE_CH0_INT_ENA_S) #define AHB_DMA_OUT_DONE_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_DONE_CH0_INT_ENA_S 0 /** AHB_DMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_OUT_EOF_CH0_INT. + * Write 1 to enable AHB_DMA_OUT_EOF_CH0_INT */ #define AHB_DMA_OUT_EOF_CH0_INT_ENA (BIT(1)) #define AHB_DMA_OUT_EOF_CH0_INT_ENA_M (AHB_DMA_OUT_EOF_CH0_INT_ENA_V << AHB_DMA_OUT_EOF_CH0_INT_ENA_S) #define AHB_DMA_OUT_EOF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_EOF_CH0_INT_ENA_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH0_INT. + * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH0_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH0_INT. + * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH0_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 3 /** AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH0_INT. + * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH0_INT */ #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_S) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_S 4 /** AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH0_INT. + * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH0_INT */ #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_S) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH0_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_S 6 /** AHB_DMA_OUT_INT_CLR_CH0_REG register - * TX channel 0 interrupt clear register + * Interrupt clear bits of TX channel 0 */ #define AHB_DMA_OUT_INT_CLR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3c) /** AHB_DMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DONE_CH0_INT. + * Write 1 to clear AHB_DMA_OUT_DONE_CH0_INT */ #define AHB_DMA_OUT_DONE_CH0_INT_CLR (BIT(0)) #define AHB_DMA_OUT_DONE_CH0_INT_CLR_M (AHB_DMA_OUT_DONE_CH0_INT_CLR_V << AHB_DMA_OUT_DONE_CH0_INT_CLR_S) #define AHB_DMA_OUT_DONE_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_DONE_CH0_INT_CLR_S 0 /** AHB_DMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_OUT_EOF_CH0_INT. + * Write 1 to clear AHB_DMA_OUT_EOF_CH0_INT */ #define AHB_DMA_OUT_EOF_CH0_INT_CLR (BIT(1)) #define AHB_DMA_OUT_EOF_CH0_INT_CLR_M (AHB_DMA_OUT_EOF_CH0_INT_CLR_V << AHB_DMA_OUT_EOF_CH0_INT_CLR_S) #define AHB_DMA_OUT_EOF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_EOF_CH0_INT_CLR_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH0_INT. + * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH0_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_M (AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S) #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH0_INT. + * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH0_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S) #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 3 /** AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH0_INT. + * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH0_INT */ #define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_M (AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_S) #define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_S 4 /** AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH0_INT. + * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH0_INT */ #define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_M (AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_S) #define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH0_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_S 6 /** AHB_DMA_OUT_INT_RAW_CH1_REG register - * TX channel 1 raw interrupt status register + * //Raw interrupt status of TX channel 1 */ #define AHB_DMA_OUT_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x40) /** AHB_DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DONE_CH1_INT. + * The raw interrupt status of AHB_DMA_OUT_DONE_CH1_INT */ #define AHB_DMA_OUT_DONE_CH1_INT_RAW (BIT(0)) #define AHB_DMA_OUT_DONE_CH1_INT_RAW_M (AHB_DMA_OUT_DONE_CH1_INT_RAW_V << AHB_DMA_OUT_DONE_CH1_INT_RAW_S) #define AHB_DMA_OUT_DONE_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_DONE_CH1_INT_RAW_S 0 /** AHB_DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_EOF_CH1_INT. + * The raw interrupt status of AHB_DMA_OUT_EOF_CH1_INT */ #define AHB_DMA_OUT_EOF_CH1_INT_RAW (BIT(1)) #define AHB_DMA_OUT_EOF_CH1_INT_RAW_M (AHB_DMA_OUT_EOF_CH1_INT_RAW_V << AHB_DMA_OUT_EOF_CH1_INT_RAW_S) #define AHB_DMA_OUT_EOF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_EOF_CH1_INT_RAW_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT. + * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT. + * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 3 /** AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT. + * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT */ #define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_S) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_S 4 /** AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT. + * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT */ #define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_S) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_S 6 /** AHB_DMA_OUT_INT_ST_CH1_REG register - * TX channel 1 masked interrupt status register + * Masked interrupt status of TX channel 1 */ #define AHB_DMA_OUT_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x44) /** AHB_DMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DONE_CH1_INT. + * The masked interrupt status of AHB_DMA_OUT_DONE_CH1_INT */ #define AHB_DMA_OUT_DONE_CH1_INT_ST (BIT(0)) #define AHB_DMA_OUT_DONE_CH1_INT_ST_M (AHB_DMA_OUT_DONE_CH1_INT_ST_V << AHB_DMA_OUT_DONE_CH1_INT_ST_S) #define AHB_DMA_OUT_DONE_CH1_INT_ST_V 0x00000001U #define AHB_DMA_OUT_DONE_CH1_INT_ST_S 0 /** AHB_DMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_EOF_CH1_INT. + * The masked interrupt status of AHB_DMA_OUT_EOF_CH1_INT */ #define AHB_DMA_OUT_EOF_CH1_INT_ST (BIT(1)) #define AHB_DMA_OUT_EOF_CH1_INT_ST_M (AHB_DMA_OUT_EOF_CH1_INT_ST_V << AHB_DMA_OUT_EOF_CH1_INT_ST_S) #define AHB_DMA_OUT_EOF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_OUT_EOF_CH1_INT_ST_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT. + * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_S) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT. + * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S 3 /** AHB_DMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT. + * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT */ #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_S) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_S 4 /** AHB_DMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT. + * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT */ #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_S) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_S 6 /** AHB_DMA_OUT_INT_ENA_CH1_REG register - * TX channel 1 interrupt enable register + * Interrupt enable bits of TX channel 1 */ #define AHB_DMA_OUT_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x48) /** AHB_DMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DONE_CH1_INT. + * Write 1 to enable AHB_DMA_OUT_DONE_CH1_INT */ #define AHB_DMA_OUT_DONE_CH1_INT_ENA (BIT(0)) #define AHB_DMA_OUT_DONE_CH1_INT_ENA_M (AHB_DMA_OUT_DONE_CH1_INT_ENA_V << AHB_DMA_OUT_DONE_CH1_INT_ENA_S) #define AHB_DMA_OUT_DONE_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_DONE_CH1_INT_ENA_S 0 /** AHB_DMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_OUT_EOF_CH1_INT. + * Write 1 to enable AHB_DMA_OUT_EOF_CH1_INT */ #define AHB_DMA_OUT_EOF_CH1_INT_ENA (BIT(1)) #define AHB_DMA_OUT_EOF_CH1_INT_ENA_M (AHB_DMA_OUT_EOF_CH1_INT_ENA_V << AHB_DMA_OUT_EOF_CH1_INT_ENA_S) #define AHB_DMA_OUT_EOF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_EOF_CH1_INT_ENA_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH1_INT. + * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH1_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH1_INT. + * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH1_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 3 /** AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH1_INT. + * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH1_INT */ #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_S) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_S 4 /** AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH1_INT. + * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH1_INT */ #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_S) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH1_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_S 6 /** AHB_DMA_OUT_INT_CLR_CH1_REG register - * TX channel 1 interrupt clear register + * Interrupt clear bits of TX channel 1 */ #define AHB_DMA_OUT_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x4c) /** AHB_DMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DONE_CH1_INT. + * Write 1 to clear AHB_DMA_OUT_DONE_CH1_INT */ #define AHB_DMA_OUT_DONE_CH1_INT_CLR (BIT(0)) #define AHB_DMA_OUT_DONE_CH1_INT_CLR_M (AHB_DMA_OUT_DONE_CH1_INT_CLR_V << AHB_DMA_OUT_DONE_CH1_INT_CLR_S) #define AHB_DMA_OUT_DONE_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_DONE_CH1_INT_CLR_S 0 /** AHB_DMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_OUT_EOF_CH1_INT. + * Write 1 to clear AHB_DMA_OUT_EOF_CH1_INT */ #define AHB_DMA_OUT_EOF_CH1_INT_CLR (BIT(1)) #define AHB_DMA_OUT_EOF_CH1_INT_CLR_M (AHB_DMA_OUT_EOF_CH1_INT_CLR_V << AHB_DMA_OUT_EOF_CH1_INT_CLR_S) #define AHB_DMA_OUT_EOF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_EOF_CH1_INT_CLR_S 1 /** AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH1_INT. + * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH1_INT */ #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(2)) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_M (AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S) #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S 2 /** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH1_INT. + * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH1_INT */ #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(3)) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S) #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 3 /** AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH1_INT. + * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH1_INT */ #define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR (BIT(4)) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_M (AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_S) #define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_S 4 /** AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH1_INT. + * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH1_INT */ #define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR (BIT(5)) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_M (AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_S) #define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_V 0x00000001U #define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_S 5 +/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH1_INT + */ +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR (BIT(6)) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_M (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_S) +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_V 0x00000001U +#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_S 6 + +/** AHB_DMA_AHB_TEST_REG register + * only for test + */ +#define AHB_DMA_AHB_TEST_REG (DR_REG_AHB_DMA_BASE + 0x60) +/** AHB_DMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; + * reserved + */ +#define AHB_DMA_AHB_TESTMODE 0x00000007U +#define AHB_DMA_AHB_TESTMODE_M (AHB_DMA_AHB_TESTMODE_V << AHB_DMA_AHB_TESTMODE_S) +#define AHB_DMA_AHB_TESTMODE_V 0x00000007U +#define AHB_DMA_AHB_TESTMODE_S 0 +/** AHB_DMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; + * reserved + */ +#define AHB_DMA_AHB_TESTADDR 0x00000003U +#define AHB_DMA_AHB_TESTADDR_M (AHB_DMA_AHB_TESTADDR_V << AHB_DMA_AHB_TESTADDR_S) +#define AHB_DMA_AHB_TESTADDR_V 0x00000003U +#define AHB_DMA_AHB_TESTADDR_S 4 /** AHB_DMA_MISC_CONF_REG register - * Miscellaneous register + * reserved */ #define AHB_DMA_MISC_CONF_REG (DR_REG_AHB_DMA_BASE + 0x64) /** AHB_DMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset the internal AHB FSM. + * Write 1 and then 0 to reset the internal AHB FSM */ #define AHB_DMA_AHBM_RST_INTER (BIT(0)) #define AHB_DMA_AHBM_RST_INTER_M (AHB_DMA_AHBM_RST_INTER_V << AHB_DMA_AHBM_RST_INTER_S) #define AHB_DMA_AHBM_RST_INTER_V 0x00000001U #define AHB_DMA_AHBM_RST_INTER_S 0 /** AHB_DMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0; - * Configures whether to disable the priority arbitration. + * Configures whether to disable the fixed-priority channel arbitration. * 0: Enable * 1: Disable */ @@ -840,9 +971,9 @@ extern "C" { #define AHB_DMA_ARB_PRI_DIS_V 0x00000001U #define AHB_DMA_ARB_PRI_DIS_S 2 /** AHB_DMA_CLK_EN : R/W; bitpos: [3]; default: 0; - * Configures AHB DMA clock gating. - * 0: Support clock only when the application writes registers - * 1: Always force the clock on for registers + * Configures clock gating. + * 0: Support clock only when the application writes registers. + * 1: Always force the clock on for registers. */ #define AHB_DMA_CLK_EN (BIT(3)) #define AHB_DMA_CLK_EN_M (AHB_DMA_CLK_EN_V << AHB_DMA_CLK_EN_S) @@ -853,8 +984,8 @@ extern "C" { * Version control register */ #define AHB_DMA_DATE_REG (DR_REG_AHB_DMA_BASE + 0x68) -/** AHB_DMA_DATE : R/W; bitpos: [31:0]; default: 36770448; - * Version control register. +/** AHB_DMA_DATE : R/W; bitpos: [31:0]; default: 2410220; + * Version control register */ #define AHB_DMA_DATE 0xFFFFFFFFU #define AHB_DMA_DATE_M (AHB_DMA_DATE_V << AHB_DMA_DATE_S) @@ -866,14 +997,14 @@ extern "C" { */ #define AHB_DMA_IN_CONF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0x70) /** AHB_DMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset RX channel 0 FSM and RX FIFO pointer. + * Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer. */ #define AHB_DMA_IN_RST_CH0 (BIT(0)) #define AHB_DMA_IN_RST_CH0_M (AHB_DMA_IN_RST_CH0_V << AHB_DMA_IN_RST_CH0_S) #define AHB_DMA_IN_RST_CH0_V 0x00000001U #define AHB_DMA_IN_RST_CH0_S 0 /** AHB_DMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; - * Configures the owner bit value for inlink write-back. + * reserved */ #define AHB_DMA_IN_LOOP_TEST_CH0 (BIT(1)) #define AHB_DMA_IN_LOOP_TEST_CH0_M (AHB_DMA_IN_LOOP_TEST_CH0_V << AHB_DMA_IN_LOOP_TEST_CH0_S) @@ -908,11 +1039,11 @@ extern "C" { #define AHB_DMA_IN_ETM_EN_CH0_V 0x00000001U #define AHB_DMA_IN_ETM_EN_CH0_S 5 /** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [7:6]; default: 0; - * Configures maximum burst length for RX channel0. - * 0: SINGLE - * 1: INCR4 - * 2: INCR8 - * 3: Reserved + * Configures max burst size for Rx channel0. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 */ #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0 0x00000003U #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_S) @@ -934,7 +1065,7 @@ extern "C" { #define AHB_DMA_IN_CHECK_OWNER_CH0_S 12 /** AHB_DMA_INFIFO_STATUS_CH0_REG register - * RX channel 0 FIFO status + * Receive FIFO status of RX channel 0 */ #define AHB_DMA_INFIFO_STATUS_CH0_REG (DR_REG_AHB_DMA_BASE + 0x78) /** AHB_DMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1; @@ -956,42 +1087,42 @@ extern "C" { #define AHB_DMA_INFIFO_EMPTY_CH0_V 0x00000001U #define AHB_DMA_INFIFO_EMPTY_CH0_S 1 /** AHB_DMA_INFIFO_CNT_CH0 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 RX FIFO for RX channel 0. + * Represents the number of data bytes in L1 RX FIFO for RX channel 0 */ #define AHB_DMA_INFIFO_CNT_CH0 0x0000007FU #define AHB_DMA_INFIFO_CNT_CH0_M (AHB_DMA_INFIFO_CNT_CH0_V << AHB_DMA_INFIFO_CNT_CH0_S) #define AHB_DMA_INFIFO_CNT_CH0_V 0x0000007FU #define AHB_DMA_INFIFO_CNT_CH0_S 8 /** AHB_DMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_IN_REMAIN_UNDER_1B_CH0 (BIT(23)) #define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_1B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH0_S) #define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_S 23 /** AHB_DMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_IN_REMAIN_UNDER_2B_CH0 (BIT(24)) #define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_2B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH0_S) #define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_S 24 /** AHB_DMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_IN_REMAIN_UNDER_3B_CH0 (BIT(25)) #define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_3B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH0_S) #define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_S 25 /** AHB_DMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_IN_REMAIN_UNDER_4B_CH0 (BIT(26)) #define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_M (AHB_DMA_IN_REMAIN_UNDER_4B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH0_S) #define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_S 26 /** AHB_DMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0; - * Reserved. + * reserved */ #define AHB_DMA_IN_BUF_HUNGRY_CH0 (BIT(27)) #define AHB_DMA_IN_BUF_HUNGRY_CH0_M (AHB_DMA_IN_BUF_HUNGRY_CH0_V << AHB_DMA_IN_BUF_HUNGRY_CH0_S) @@ -999,18 +1130,18 @@ extern "C" { #define AHB_DMA_IN_BUF_HUNGRY_CH0_S 27 /** AHB_DMA_IN_POP_CH0_REG register - * Pop control register of RX channel 0 + * Receive FIFO status of RX channel 0 */ #define AHB_DMA_IN_POP_CH0_REG (DR_REG_AHB_DMA_BASE + 0x7c) /** AHB_DMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048; - * Represents the data popped from AHB DMA RX FIFO. + * Represents the data popped from AHB_DMA FIFO. */ #define AHB_DMA_INFIFO_RDATA_CH0 0x00000FFFU #define AHB_DMA_INFIFO_RDATA_CH0_M (AHB_DMA_INFIFO_RDATA_CH0_V << AHB_DMA_INFIFO_RDATA_CH0_S) #define AHB_DMA_INFIFO_RDATA_CH0_V 0x00000FFFU #define AHB_DMA_INFIFO_RDATA_CH0_S 0 /** AHB_DMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0; - * Configures whether to pop data from AHB DMA RX FIFO. + * Configures whether to pop data from AHB_DMA FIFO. * 0: Invalid. No effect * 1: Pop */ @@ -1020,21 +1151,22 @@ extern "C" { #define AHB_DMA_INFIFO_POP_CH0_S 12 /** AHB_DMA_IN_LINK_CH0_REG register - * Linked list descriptor configuration and control register of RX channel 0 + * Receive FIFO status of RX channel 0 */ #define AHB_DMA_IN_LINK_CH0_REG (DR_REG_AHB_DMA_BASE + 0x80) /** AHB_DMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [0]; default: 1; - * Configures whether to return to the current receive descriptor's address when there - * are some errors in current receiving data. + * Configures whether to return to current receive descriptor's address when there are + * some errors in current receiving data. * 0: Not return * 1: Return + * . */ #define AHB_DMA_INLINK_AUTO_RET_CH0 (BIT(0)) #define AHB_DMA_INLINK_AUTO_RET_CH0_M (AHB_DMA_INLINK_AUTO_RET_CH0_V << AHB_DMA_INLINK_AUTO_RET_CH0_S) #define AHB_DMA_INLINK_AUTO_RET_CH0_V 0x00000001U #define AHB_DMA_INLINK_AUTO_RET_CH0_S 0 /** AHB_DMA_INLINK_STOP_CH0 : WT; bitpos: [1]; default: 0; - * Configures whether to stop RX channel 0 from receiving data. + * Configures whether to stop AHB_DMA's RX channel 0 from receiving data. * 0: Invalid. No effect * 1: Stop */ @@ -1043,7 +1175,7 @@ extern "C" { #define AHB_DMA_INLINK_STOP_CH0_V 0x00000001U #define AHB_DMA_INLINK_STOP_CH0_S 1 /** AHB_DMA_INLINK_START_CH0 : WT; bitpos: [2]; default: 0; - * Configures whether to enable RX channel 0 for data transfer. + * Configures whether to enable AHB_DMA's RX channel 0 for data transfer. * 0: Disable * 1: Enable */ @@ -1052,7 +1184,7 @@ extern "C" { #define AHB_DMA_INLINK_START_CH0_V 0x00000001U #define AHB_DMA_INLINK_START_CH0_S 2 /** AHB_DMA_INLINK_RESTART_CH0 : WT; bitpos: [3]; default: 0; - * Configures whether to restart RX channel 0 for AHB DMA transfer. + * Configures whether to restart RX channel 0 for AHB_DMA transfer. * 0: Invalid. No effect * 1: Restart */ @@ -1071,28 +1203,26 @@ extern "C" { #define AHB_DMA_INLINK_PARK_CH0_S 4 /** AHB_DMA_IN_STATE_CH0_REG register - * RX channel 0 status + * Receive status of RX channel 0 */ #define AHB_DMA_IN_STATE_CH0_REG (DR_REG_AHB_DMA_BASE + 0x84) /** AHB_DMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the next receive descriptor address that is - * pre-read (but not processed yet). If the current receive descriptor is the last - * descriptor, then this field represents the address of the current receive - * descriptor. + * reserved */ #define AHB_DMA_INLINK_DSCR_ADDR_CH0 0x0003FFFFU #define AHB_DMA_INLINK_DSCR_ADDR_CH0_M (AHB_DMA_INLINK_DSCR_ADDR_CH0_V << AHB_DMA_INLINK_DSCR_ADDR_CH0_S) #define AHB_DMA_INLINK_DSCR_ADDR_CH0_V 0x0003FFFFU #define AHB_DMA_INLINK_DSCR_ADDR_CH0_S 0 /** AHB_DMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; - * Reserved. + * reserved */ #define AHB_DMA_IN_DSCR_STATE_CH0 0x00000003U #define AHB_DMA_IN_DSCR_STATE_CH0_M (AHB_DMA_IN_DSCR_STATE_CH0_V << AHB_DMA_IN_DSCR_STATE_CH0_S) #define AHB_DMA_IN_DSCR_STATE_CH0_V 0x00000003U #define AHB_DMA_IN_DSCR_STATE_CH0_S 18 /** AHB_DMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; - * Reserved. + * Represents the address of the lower 18 bits of the next receive descriptor to be + * processed. */ #define AHB_DMA_IN_STATE_CH0 0x00000007U #define AHB_DMA_IN_STATE_CH0_M (AHB_DMA_IN_STATE_CH0_V << AHB_DMA_IN_STATE_CH0_S) @@ -1126,13 +1256,12 @@ extern "C" { #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 /** AHB_DMA_IN_DSCR_CH0_REG register - * Address of the next receive descriptor pointed by the current pre-read receive - * descriptor on RX channel 0 + * Current receive descriptor address of RX channel 0 */ #define AHB_DMA_IN_DSCR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x90) /** AHB_DMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; * Represents the address of the next receive descriptor x+1 pointed by the current - * receive descriptor that is pre-read. + * receive descriptor that has already been fetched. */ #define AHB_DMA_INLINK_DSCR_CH0 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_CH0_M (AHB_DMA_INLINK_DSCR_CH0_V << AHB_DMA_INLINK_DSCR_CH0_S) @@ -1140,11 +1269,12 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_CH0_S 0 /** AHB_DMA_IN_DSCR_BF0_CH0_REG register - * Address of the current pre-read receive descriptor on RX channel 0 + * The last receive descriptor address of RX channel 0 */ #define AHB_DMA_IN_DSCR_BF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0x94) /** AHB_DMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current receive descriptor x that is pre-read. + * Represents the address of the current receive descriptor x that has already been + * fetched. */ #define AHB_DMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_BF0_CH0_M (AHB_DMA_INLINK_DSCR_BF0_CH0_V << AHB_DMA_INLINK_DSCR_BF0_CH0_S) @@ -1152,25 +1282,25 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_BF0_CH0_S 0 /** AHB_DMA_IN_DSCR_BF1_CH0_REG register - * Address of the previous pre-read receive descriptor on RX channel 0 + * The second-to-last receive descriptor address of RX channel 0 */ #define AHB_DMA_IN_DSCR_BF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0x98) /** AHB_DMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous receive descriptor x-1 that is pre-read. + * Represents the address of the previous receive descriptor x-1 that has already been + * fetched. */ #define AHB_DMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_BF1_CH0_M (AHB_DMA_INLINK_DSCR_BF1_CH0_V << AHB_DMA_INLINK_DSCR_BF1_CH0_S) #define AHB_DMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_BF1_CH0_S 0 -/** AHB_DMA_IN_PRI_CH0_REG register +/** AHB_DMA_IN_PERI_CH0_REG register * Priority register of RX channel 0 */ -#define AHB_DMA_IN_PRI_CH0_REG (DR_REG_AHB_DMA_BASE + 0x9c) +#define AHB_DMA_IN_PERI_CH0_REG (DR_REG_AHB_DMA_BASE + 0x9c) /** AHB_DMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of RX channel 0. The larger the value, the higher the - * priority. - * Value range: 0 ~ 5 + * Configures the priority of RX channel 0.The larger of the value, the higher of the + * priority.. */ #define AHB_DMA_RX_PRI_CH0 0x0000000FU #define AHB_DMA_RX_PRI_CH0_M (AHB_DMA_RX_PRI_CH0_V << AHB_DMA_RX_PRI_CH0_S) @@ -1184,14 +1314,13 @@ extern "C" { /** AHB_DMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; * Configures the peripheral connected to RX channel 0. * 0: Dummy - * 1: GP-SPI + * 1: SPI2 * 2: Dummy - * 3: I2S + * 3: I2S0 * 4 ~ 6: Dummy * 7: SHA - * 8: ADC - * 9 ~ 15: Dummy - * 16 ~ 63: Invalid + * 8: ADC_DAC + * 9~15: Dummy */ #define AHB_DMA_PERI_IN_SEL_CH0 0x0000003FU #define AHB_DMA_PERI_IN_SEL_CH0_M (AHB_DMA_PERI_IN_SEL_CH0_V << AHB_DMA_PERI_IN_SEL_CH0_S) @@ -1199,11 +1328,11 @@ extern "C" { #define AHB_DMA_PERI_IN_SEL_CH0_S 0 /** AHB_DMA_IN_DONE_DES_ADDR_CH0_REG register - * Address of the completed inlink descriptor on RX channel 0 + * RX_done Inlink descriptor address of RX channel 0 */ #define AHB_DMA_IN_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xb0) /** AHB_DMA_IN_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the inlink descriptor when this descriptor is completed. + * Represents the address of the inlink descriptor when this descriptor is completed . */ #define AHB_DMA_IN_DONE_DES_ADDR_CH0 0xFFFFFFFFU #define AHB_DMA_IN_DONE_DES_ADDR_CH0_M (AHB_DMA_IN_DONE_DES_ADDR_CH0_V << AHB_DMA_IN_DONE_DES_ADDR_CH0_S) @@ -1215,7 +1344,7 @@ extern "C" { */ #define AHB_DMA_OUT_CONF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd0) /** AHB_DMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0; - * Configures the reset state of TX channel 0 FSM and TX FIFO pointer. + * Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer. * 0: Release reset * 1: Reset */ @@ -1224,7 +1353,7 @@ extern "C" { #define AHB_DMA_OUT_RST_CH0_V 0x00000001U #define AHB_DMA_OUT_RST_CH0_S 0 /** AHB_DMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; - * Configures the owner bit value for outlink write-back. + * reserved */ #define AHB_DMA_OUT_LOOP_TEST_CH0 (BIT(1)) #define AHB_DMA_OUT_LOOP_TEST_CH0_M (AHB_DMA_OUT_LOOP_TEST_CH0_V << AHB_DMA_OUT_LOOP_TEST_CH0_S) @@ -1243,9 +1372,9 @@ extern "C" { /** AHB_DMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1; * Configures when to generate EOF flag. * 0: EOF flag for TX channel 0 is generated when data to be transmitted has been - * pushed into FIFO in AHB DMA. + * pushed into FIFO in AHB_DMA. * 1: EOF flag for TX channel 0 is generated when data to be transmitted has been - * popped from FIFO in AHB DMA. + * popped from FIFO in AHB_DMA. */ #define AHB_DMA_OUT_EOF_MODE_CH0 (BIT(3)) #define AHB_DMA_OUT_EOF_MODE_CH0_M (AHB_DMA_OUT_EOF_MODE_CH0_V << AHB_DMA_OUT_EOF_MODE_CH0_S) @@ -1271,11 +1400,11 @@ extern "C" { #define AHB_DMA_OUT_ETM_EN_CH0_V 0x00000001U #define AHB_DMA_OUT_ETM_EN_CH0_S 6 /** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [9:8]; default: 0; - * Configures maximum burst length for TX channel0. - * 0: SINGLE - * 1: INCR4 - * 2: INCR8 - * 3: Reserved + * Configures max burst size for TX channel0. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 */ #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0 0x00000003U #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_S) @@ -1297,7 +1426,7 @@ extern "C" { #define AHB_DMA_OUT_CHECK_OWNER_CH0_S 12 /** AHB_DMA_OUTFIFO_STATUS_CH0_REG register - * TX channel 0 FIFO status + * Receive FIFO status of RX channel 0 */ #define AHB_DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd8) /** AHB_DMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0; @@ -1319,35 +1448,35 @@ extern "C" { #define AHB_DMA_OUTFIFO_EMPTY_CH0_V 0x00000001U #define AHB_DMA_OUTFIFO_EMPTY_CH0_S 1 /** AHB_DMA_OUTFIFO_CNT_CH0 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 TX FIFO for TX channel 0. + * Represents the number of data bytes in L1 TX FIFO for TX channel 0 */ #define AHB_DMA_OUTFIFO_CNT_CH0 0x0000007FU #define AHB_DMA_OUTFIFO_CNT_CH0_M (AHB_DMA_OUTFIFO_CNT_CH0_V << AHB_DMA_OUTFIFO_CNT_CH0_S) #define AHB_DMA_OUTFIFO_CNT_CH0_V 0x0000007FU #define AHB_DMA_OUTFIFO_CNT_CH0_S 8 /** AHB_DMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0 (BIT(23)) #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_S) #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_S 23 /** AHB_DMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0 (BIT(24)) #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_S) #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_S 24 /** AHB_DMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0 (BIT(25)) #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_S) #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_S 25 /** AHB_DMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0 (BIT(26)) #define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_M (AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_S) @@ -1359,16 +1488,16 @@ extern "C" { */ #define AHB_DMA_OUT_PUSH_CH0_REG (DR_REG_AHB_DMA_BASE + 0xdc) /** AHB_DMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0; - * Represents the data that need to be pushed into AHB DMA TX FIFO. + * Configures whether to push data into AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Push */ #define AHB_DMA_OUTFIFO_WDATA_CH0 0x000001FFU #define AHB_DMA_OUTFIFO_WDATA_CH0_M (AHB_DMA_OUTFIFO_WDATA_CH0_V << AHB_DMA_OUTFIFO_WDATA_CH0_S) #define AHB_DMA_OUTFIFO_WDATA_CH0_V 0x000001FFU #define AHB_DMA_OUTFIFO_WDATA_CH0_S 0 /** AHB_DMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0; - * Configures whether to push data into AHB DMA TX FIFO. - * 0: Invalid. No effect - * 1: Push + * Configures the data that need to be pushed into AHB_DMA FIFO. */ #define AHB_DMA_OUTFIFO_PUSH_CH0 (BIT(9)) #define AHB_DMA_OUTFIFO_PUSH_CH0_M (AHB_DMA_OUTFIFO_PUSH_CH0_V << AHB_DMA_OUTFIFO_PUSH_CH0_S) @@ -1376,11 +1505,11 @@ extern "C" { #define AHB_DMA_OUTFIFO_PUSH_CH0_S 9 /** AHB_DMA_OUT_LINK_CH0_REG register - * Linked list descriptor configuration and control register of TX channel 0 + * Push control register of TX channel 0 */ #define AHB_DMA_OUT_LINK_CH0_REG (DR_REG_AHB_DMA_BASE + 0xe0) /** AHB_DMA_OUTLINK_STOP_CH0 : WT; bitpos: [0]; default: 0; - * Configures whether to stop TX channel 0 from transmitting data. + * Configures whether to stop AHB_DMA's TX channel 0 from transmitting data. * 0: Invalid. No effect * 1: Stop */ @@ -1389,7 +1518,7 @@ extern "C" { #define AHB_DMA_OUTLINK_STOP_CH0_V 0x00000001U #define AHB_DMA_OUTLINK_STOP_CH0_S 0 /** AHB_DMA_OUTLINK_START_CH0 : WT; bitpos: [1]; default: 0; - * Configures whether to enable TX channel 0 for data transfer. + * Configures whether to enable AHB_DMA's TX channel 0 for data transfer. * 0: Disable * 1: Enable */ @@ -1398,7 +1527,7 @@ extern "C" { #define AHB_DMA_OUTLINK_START_CH0_V 0x00000001U #define AHB_DMA_OUTLINK_START_CH0_S 1 /** AHB_DMA_OUTLINK_RESTART_CH0 : WT; bitpos: [2]; default: 0; - * Configures whether to restart TX channel 0 for AHB DMA transfer. + * Configures whether to restart TX channel 0 for AHB_DMA transfer. * 0: Invalid. No effect * 1: Restart */ @@ -1417,28 +1546,26 @@ extern "C" { #define AHB_DMA_OUTLINK_PARK_CH0_S 3 /** AHB_DMA_OUT_STATE_CH0_REG register - * TX channel 0 status + * Transmit status of TX channel 0 */ #define AHB_DMA_OUT_STATE_CH0_REG (DR_REG_AHB_DMA_BASE + 0xe4) /** AHB_DMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the next transmit descriptor address that is - * pre-read (but not processed yet). If the current transmit descriptor is the last - * descriptor, then this field represents the address of the current transmit - * descriptor. + * Represents the lower 18 bits of the address of the next transmit descriptor to be + * processed. */ #define AHB_DMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFFU #define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_M (AHB_DMA_OUTLINK_DSCR_ADDR_CH0_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH0_S) #define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFFU #define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_S 0 /** AHB_DMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; - * Reserved. + * reserved */ #define AHB_DMA_OUT_DSCR_STATE_CH0 0x00000003U #define AHB_DMA_OUT_DSCR_STATE_CH0_M (AHB_DMA_OUT_DSCR_STATE_CH0_V << AHB_DMA_OUT_DSCR_STATE_CH0_S) #define AHB_DMA_OUT_DSCR_STATE_CH0_V 0x00000003U #define AHB_DMA_OUT_DSCR_STATE_CH0_S 18 /** AHB_DMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; - * Reserved. + * reserved */ #define AHB_DMA_OUT_STATE_CH0 0x00000007U #define AHB_DMA_OUT_STATE_CH0_M (AHB_DMA_OUT_STATE_CH0_V << AHB_DMA_OUT_STATE_CH0_S) @@ -1472,13 +1599,12 @@ extern "C" { #define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 /** AHB_DMA_OUT_DSCR_CH0_REG register - * Address of the next transmit descriptor pointed by the current pre-read transmit - * descriptor on TX channel 0 + * Current transmit descriptor address of TX channel 0 */ #define AHB_DMA_OUT_DSCR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf0) /** AHB_DMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; * Represents the address of the next transmit descriptor y+1 pointed by the current - * transmit descriptor that is pre-read. + * transmit descriptor that has already been fetched. */ #define AHB_DMA_OUTLINK_DSCR_CH0 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_CH0_M (AHB_DMA_OUTLINK_DSCR_CH0_V << AHB_DMA_OUTLINK_DSCR_CH0_S) @@ -1486,11 +1612,12 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_CH0_S 0 /** AHB_DMA_OUT_DSCR_BF0_CH0_REG register - * Address of the current pre-read transmit descriptor on TX channel 0 + * The last transmit descriptor address of TX channel 0 */ #define AHB_DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf4) /** AHB_DMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current transmit descriptor y that is pre-read. + * Represents the address of the current transmit descriptor y that has already been + * fetched. */ #define AHB_DMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_BF0_CH0_M (AHB_DMA_OUTLINK_DSCR_BF0_CH0_V << AHB_DMA_OUTLINK_DSCR_BF0_CH0_S) @@ -1498,25 +1625,25 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_BF0_CH0_S 0 /** AHB_DMA_OUT_DSCR_BF1_CH0_REG register - * Address of the previous pre-read transmit descriptor on TX channel 0 + * The second-to-last transmit descriptor address of TX channel 0 */ #define AHB_DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf8) /** AHB_DMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous transmit descriptor y-1 that is pre-read. + * Represents the address of the previous transmit descriptor y-1 that has already + * been fetched. */ #define AHB_DMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_BF1_CH0_M (AHB_DMA_OUTLINK_DSCR_BF1_CH0_V << AHB_DMA_OUTLINK_DSCR_BF1_CH0_S) #define AHB_DMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_BF1_CH0_S 0 -/** AHB_DMA_OUT_PRI_CH0_REG register +/** AHB_DMA_OUT_PERI_CH0_REG register * Priority register of TX channel 0 */ -#define AHB_DMA_OUT_PRI_CH0_REG (DR_REG_AHB_DMA_BASE + 0xfc) +#define AHB_DMA_OUT_PERI_CH0_REG (DR_REG_AHB_DMA_BASE + 0xfc) /** AHB_DMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of TX channel 0. The larger the value, the higher the - * priority. - * Value range: 0 ~ 5 + * Configures the priority of TX channel 0.The larger of the value, the higher of the + * priority.. */ #define AHB_DMA_TX_PRI_CH0 0x0000000FU #define AHB_DMA_TX_PRI_CH0_M (AHB_DMA_TX_PRI_CH0_V << AHB_DMA_TX_PRI_CH0_S) @@ -1530,14 +1657,13 @@ extern "C" { /** AHB_DMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; * Configures the peripheral connected to TX channel 0. * 0: Dummy - * 1: GP-SPI + * 1: SPI2 * 2: Dummy - * 3: I2S + * 3: I2S0 * 4 ~ 6: Dummy * 7: SHA - * 8: ADC - * 9 ~ 15: Dummy - * 16 ~ 63: Invalid + * 8: ADC_DAC + * 9~15: Dummy */ #define AHB_DMA_PERI_OUT_SEL_CH0 0x0000003FU #define AHB_DMA_PERI_OUT_SEL_CH0_M (AHB_DMA_PERI_OUT_SEL_CH0_V << AHB_DMA_PERI_OUT_SEL_CH0_S) @@ -1545,7 +1671,7 @@ extern "C" { #define AHB_DMA_PERI_OUT_SEL_CH0_S 0 /** AHB_DMA_OUT_DONE_DES_ADDR_CH0_REG register - * Address of the completed outlink descriptor on TX channel 0 + * TX done outlink descriptor address of TX channel 0 */ #define AHB_DMA_OUT_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x110) /** AHB_DMA_OUT_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; @@ -1561,14 +1687,14 @@ extern "C" { */ #define AHB_DMA_IN_CONF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x130) /** AHB_DMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset RX channel 1 FSM and RX FIFO pointer. + * Write 1 and then 0 to reset AHB_DMA channel 1 RX FSM and RX FIFO pointer. */ #define AHB_DMA_IN_RST_CH1 (BIT(0)) #define AHB_DMA_IN_RST_CH1_M (AHB_DMA_IN_RST_CH1_V << AHB_DMA_IN_RST_CH1_S) #define AHB_DMA_IN_RST_CH1_V 0x00000001U #define AHB_DMA_IN_RST_CH1_S 0 /** AHB_DMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; - * Configures the owner bit value for inlink write-back. + * reserved */ #define AHB_DMA_IN_LOOP_TEST_CH1 (BIT(1)) #define AHB_DMA_IN_LOOP_TEST_CH1_M (AHB_DMA_IN_LOOP_TEST_CH1_V << AHB_DMA_IN_LOOP_TEST_CH1_S) @@ -1603,11 +1729,11 @@ extern "C" { #define AHB_DMA_IN_ETM_EN_CH1_V 0x00000001U #define AHB_DMA_IN_ETM_EN_CH1_S 5 /** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [7:6]; default: 0; - * Configures maximum burst length for RX channel1. - * 0: SINGLE - * 1: INCR4 - * 2: INCR8 - * 3: Reserved + * Configures max burst size for Rx channel1. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 */ #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1 0x00000003U #define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_M (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_S) @@ -1629,7 +1755,7 @@ extern "C" { #define AHB_DMA_IN_CHECK_OWNER_CH1_S 12 /** AHB_DMA_INFIFO_STATUS_CH1_REG register - * RX channel 1 FIFO status + * Receive FIFO status of RX channel 1 */ #define AHB_DMA_INFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x138) /** AHB_DMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1; @@ -1651,42 +1777,42 @@ extern "C" { #define AHB_DMA_INFIFO_EMPTY_CH1_V 0x00000001U #define AHB_DMA_INFIFO_EMPTY_CH1_S 1 /** AHB_DMA_INFIFO_CNT_CH1 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 RX FIFO for RX channel 1. + * Represents the number of data bytes in L1 RX FIFO for RX channel 1 */ #define AHB_DMA_INFIFO_CNT_CH1 0x0000007FU #define AHB_DMA_INFIFO_CNT_CH1_M (AHB_DMA_INFIFO_CNT_CH1_V << AHB_DMA_INFIFO_CNT_CH1_S) #define AHB_DMA_INFIFO_CNT_CH1_V 0x0000007FU #define AHB_DMA_INFIFO_CNT_CH1_S 8 /** AHB_DMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_IN_REMAIN_UNDER_1B_CH1 (BIT(23)) #define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_1B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH1_S) #define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_S 23 /** AHB_DMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_IN_REMAIN_UNDER_2B_CH1 (BIT(24)) #define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_2B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH1_S) #define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_S 24 /** AHB_DMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_IN_REMAIN_UNDER_3B_CH1 (BIT(25)) #define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_3B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH1_S) #define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_S 25 /** AHB_DMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_IN_REMAIN_UNDER_4B_CH1 (BIT(26)) #define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_M (AHB_DMA_IN_REMAIN_UNDER_4B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH1_S) #define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_V 0x00000001U #define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_S 26 /** AHB_DMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0; - * Reserved. + * reserved */ #define AHB_DMA_IN_BUF_HUNGRY_CH1 (BIT(27)) #define AHB_DMA_IN_BUF_HUNGRY_CH1_M (AHB_DMA_IN_BUF_HUNGRY_CH1_V << AHB_DMA_IN_BUF_HUNGRY_CH1_S) @@ -1694,18 +1820,18 @@ extern "C" { #define AHB_DMA_IN_BUF_HUNGRY_CH1_S 27 /** AHB_DMA_IN_POP_CH1_REG register - * Pop control register of RX channel 1 + * Receive FIFO status of RX channel 1 */ #define AHB_DMA_IN_POP_CH1_REG (DR_REG_AHB_DMA_BASE + 0x13c) /** AHB_DMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048; - * Represents the data popped from AHB DMA RX FIFO. + * Represents the data popped from AHB_DMA FIFO. */ #define AHB_DMA_INFIFO_RDATA_CH1 0x00000FFFU #define AHB_DMA_INFIFO_RDATA_CH1_M (AHB_DMA_INFIFO_RDATA_CH1_V << AHB_DMA_INFIFO_RDATA_CH1_S) #define AHB_DMA_INFIFO_RDATA_CH1_V 0x00000FFFU #define AHB_DMA_INFIFO_RDATA_CH1_S 0 /** AHB_DMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0; - * Configures whether to pop data from AHB DMA RX FIFO. + * Configures whether to pop data from AHB_DMA FIFO. * 0: Invalid. No effect * 1: Pop */ @@ -1715,21 +1841,22 @@ extern "C" { #define AHB_DMA_INFIFO_POP_CH1_S 12 /** AHB_DMA_IN_LINK_CH1_REG register - * Linked list descriptor configuration and control register of RX channel 1 + * Receive FIFO status of RX channel 1 */ #define AHB_DMA_IN_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x140) /** AHB_DMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [0]; default: 1; - * Configures whether to return to the current receive descriptor's address when there - * are some errors in current receiving data. + * Configures whether to return to current receive descriptor's address when there are + * some errors in current receiving data. * 0: Not return * 1: Return + * . */ #define AHB_DMA_INLINK_AUTO_RET_CH1 (BIT(0)) #define AHB_DMA_INLINK_AUTO_RET_CH1_M (AHB_DMA_INLINK_AUTO_RET_CH1_V << AHB_DMA_INLINK_AUTO_RET_CH1_S) #define AHB_DMA_INLINK_AUTO_RET_CH1_V 0x00000001U #define AHB_DMA_INLINK_AUTO_RET_CH1_S 0 /** AHB_DMA_INLINK_STOP_CH1 : WT; bitpos: [1]; default: 0; - * Configures whether to stop RX channel 1 from receiving data. + * Configures whether to stop AHB_DMA's RX channel 1 from receiving data. * 0: Invalid. No effect * 1: Stop */ @@ -1738,7 +1865,7 @@ extern "C" { #define AHB_DMA_INLINK_STOP_CH1_V 0x00000001U #define AHB_DMA_INLINK_STOP_CH1_S 1 /** AHB_DMA_INLINK_START_CH1 : WT; bitpos: [2]; default: 0; - * Configures whether to enable RX channel 1 for data transfer. + * Configures whether to enable AHB_DMA's RX channel 1 for data transfer. * 0: Disable * 1: Enable */ @@ -1747,7 +1874,7 @@ extern "C" { #define AHB_DMA_INLINK_START_CH1_V 0x00000001U #define AHB_DMA_INLINK_START_CH1_S 2 /** AHB_DMA_INLINK_RESTART_CH1 : WT; bitpos: [3]; default: 0; - * Configures whether to restart RX channel 1 for AHB DMA transfer. + * Configures whether to restart RX channel 1 for AHB_DMA transfer. * 0: Invalid. No effect * 1: Restart */ @@ -1766,28 +1893,26 @@ extern "C" { #define AHB_DMA_INLINK_PARK_CH1_S 4 /** AHB_DMA_IN_STATE_CH1_REG register - * RX channel 1 status + * Receive status of RX channel 1 */ #define AHB_DMA_IN_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x144) /** AHB_DMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the next receive descriptor address that is - * pre-read (but not processed yet). If the current receive descriptor is the last - * descriptor, then this field represents the address of the current receive - * descriptor. + * reserved */ #define AHB_DMA_INLINK_DSCR_ADDR_CH1 0x0003FFFFU #define AHB_DMA_INLINK_DSCR_ADDR_CH1_M (AHB_DMA_INLINK_DSCR_ADDR_CH1_V << AHB_DMA_INLINK_DSCR_ADDR_CH1_S) #define AHB_DMA_INLINK_DSCR_ADDR_CH1_V 0x0003FFFFU #define AHB_DMA_INLINK_DSCR_ADDR_CH1_S 0 /** AHB_DMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; - * Reserved. + * reserved */ #define AHB_DMA_IN_DSCR_STATE_CH1 0x00000003U #define AHB_DMA_IN_DSCR_STATE_CH1_M (AHB_DMA_IN_DSCR_STATE_CH1_V << AHB_DMA_IN_DSCR_STATE_CH1_S) #define AHB_DMA_IN_DSCR_STATE_CH1_V 0x00000003U #define AHB_DMA_IN_DSCR_STATE_CH1_S 18 /** AHB_DMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; - * Reserved. + * Represents the address of the lower 18 bits of the next receive descriptor to be + * processed. */ #define AHB_DMA_IN_STATE_CH1 0x00000007U #define AHB_DMA_IN_STATE_CH1_M (AHB_DMA_IN_STATE_CH1_V << AHB_DMA_IN_STATE_CH1_S) @@ -1821,13 +1946,12 @@ extern "C" { #define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 /** AHB_DMA_IN_DSCR_CH1_REG register - * Address of the next receive descriptor pointed by the current pre-read receive - * descriptor on RX channel 1 + * Current receive descriptor address of RX channel 1 */ #define AHB_DMA_IN_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x150) /** AHB_DMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; * Represents the address of the next receive descriptor x+1 pointed by the current - * receive descriptor that is pre-read. + * receive descriptor that has already been fetched. */ #define AHB_DMA_INLINK_DSCR_CH1 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_CH1_M (AHB_DMA_INLINK_DSCR_CH1_V << AHB_DMA_INLINK_DSCR_CH1_S) @@ -1835,11 +1959,12 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_CH1_S 0 /** AHB_DMA_IN_DSCR_BF0_CH1_REG register - * Address of the current pre-read receive descriptor on RX channel 1 + * The last receive descriptor address of RX channel 1 */ #define AHB_DMA_IN_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x154) /** AHB_DMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current receive descriptor x that is pre-read. + * Represents the address of the current receive descriptor x that has already been + * fetched. */ #define AHB_DMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_BF0_CH1_M (AHB_DMA_INLINK_DSCR_BF0_CH1_V << AHB_DMA_INLINK_DSCR_BF0_CH1_S) @@ -1847,25 +1972,25 @@ extern "C" { #define AHB_DMA_INLINK_DSCR_BF0_CH1_S 0 /** AHB_DMA_IN_DSCR_BF1_CH1_REG register - * Address of the previous pre-read receive descriptor on RX channel 1 + * The second-to-last receive descriptor address of RX channel 1 */ #define AHB_DMA_IN_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x158) /** AHB_DMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous receive descriptor x-1 that is pre-read. + * Represents the address of the previous receive descriptor x-1 that has already been + * fetched. */ #define AHB_DMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_BF1_CH1_M (AHB_DMA_INLINK_DSCR_BF1_CH1_V << AHB_DMA_INLINK_DSCR_BF1_CH1_S) #define AHB_DMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU #define AHB_DMA_INLINK_DSCR_BF1_CH1_S 0 -/** AHB_DMA_IN_PRI_CH1_REG register +/** AHB_DMA_IN_PERI_CH1_REG register * Priority register of RX channel 1 */ -#define AHB_DMA_IN_PRI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x15c) +#define AHB_DMA_IN_PERI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x15c) /** AHB_DMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of RX channel 1. The larger the value, the higher the - * priority. - * Value range: 0 ~ 5 + * Configures the priority of RX channel 1.The larger of the value, the higher of the + * priority.. */ #define AHB_DMA_RX_PRI_CH1 0x0000000FU #define AHB_DMA_RX_PRI_CH1_M (AHB_DMA_RX_PRI_CH1_V << AHB_DMA_RX_PRI_CH1_S) @@ -1879,14 +2004,13 @@ extern "C" { /** AHB_DMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; * Configures the peripheral connected to RX channel 1. * 0: Dummy - * 1: GP-SPI + * 1: SPI2 * 2: Dummy - * 3: I2S + * 3: I2S0 * 4 ~ 6: Dummy * 7: SHA - * 8: ADC - * 9 ~ 15: Dummy - * 16 ~ 63: Invalid + * 8: ADC_DAC + * 9~15: Dummy */ #define AHB_DMA_PERI_IN_SEL_CH1 0x0000003FU #define AHB_DMA_PERI_IN_SEL_CH1_M (AHB_DMA_PERI_IN_SEL_CH1_V << AHB_DMA_PERI_IN_SEL_CH1_S) @@ -1894,11 +2018,11 @@ extern "C" { #define AHB_DMA_PERI_IN_SEL_CH1_S 0 /** AHB_DMA_IN_DONE_DES_ADDR_CH1_REG register - * Address of the completed inlink descriptor on RX channel 1 + * RX_done Inlink descriptor address of RX channel 1 */ #define AHB_DMA_IN_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x170) /** AHB_DMA_IN_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the inlink descriptor when this descriptor is completed. + * Represents the address of the inlink descriptor when this descriptor is completed . */ #define AHB_DMA_IN_DONE_DES_ADDR_CH1 0xFFFFFFFFU #define AHB_DMA_IN_DONE_DES_ADDR_CH1_M (AHB_DMA_IN_DONE_DES_ADDR_CH1_V << AHB_DMA_IN_DONE_DES_ADDR_CH1_S) @@ -1910,7 +2034,7 @@ extern "C" { */ #define AHB_DMA_OUT_CONF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x190) /** AHB_DMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0; - * Configures the reset state of TX channel 1 FSM and TX FIFO pointer. + * Configures the reset state of AHB_DMA channel 1 TX FSM and TX FIFO pointer. * 0: Release reset * 1: Reset */ @@ -1919,7 +2043,7 @@ extern "C" { #define AHB_DMA_OUT_RST_CH1_V 0x00000001U #define AHB_DMA_OUT_RST_CH1_S 0 /** AHB_DMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; - * Configures the owner bit value for outlink write-back. + * reserved */ #define AHB_DMA_OUT_LOOP_TEST_CH1 (BIT(1)) #define AHB_DMA_OUT_LOOP_TEST_CH1_M (AHB_DMA_OUT_LOOP_TEST_CH1_V << AHB_DMA_OUT_LOOP_TEST_CH1_S) @@ -1938,9 +2062,9 @@ extern "C" { /** AHB_DMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1; * Configures when to generate EOF flag. * 0: EOF flag for TX channel 1 is generated when data to be transmitted has been - * pushed into FIFO in AHB DMA. + * pushed into FIFO in AHB_DMA. * 1: EOF flag for TX channel 1 is generated when data to be transmitted has been - * popped from FIFO in AHB DMA. + * popped from FIFO in AHB_DMA. */ #define AHB_DMA_OUT_EOF_MODE_CH1 (BIT(3)) #define AHB_DMA_OUT_EOF_MODE_CH1_M (AHB_DMA_OUT_EOF_MODE_CH1_V << AHB_DMA_OUT_EOF_MODE_CH1_S) @@ -1966,11 +2090,11 @@ extern "C" { #define AHB_DMA_OUT_ETM_EN_CH1_V 0x00000001U #define AHB_DMA_OUT_ETM_EN_CH1_S 6 /** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [9:8]; default: 0; - * Configures maximum burst length for TX channel1. - * 0: SINGLE - * 1: INCR4 - * 2: INCR8 - * 3: Reserved + * Configures max burst size for TX channel1. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 */ #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1 0x00000003U #define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_M (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_S) @@ -1992,7 +2116,7 @@ extern "C" { #define AHB_DMA_OUT_CHECK_OWNER_CH1_S 12 /** AHB_DMA_OUTFIFO_STATUS_CH1_REG register - * TX channel 1 FIFO status + * Receive FIFO status of RX channel 1 */ #define AHB_DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x198) /** AHB_DMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0; @@ -2014,35 +2138,35 @@ extern "C" { #define AHB_DMA_OUTFIFO_EMPTY_CH1_V 0x00000001U #define AHB_DMA_OUTFIFO_EMPTY_CH1_S 1 /** AHB_DMA_OUTFIFO_CNT_CH1 : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 TX FIFO for TX channel 1. + * Represents the number of data bytes in L1 TX FIFO for TX channel 1 */ #define AHB_DMA_OUTFIFO_CNT_CH1 0x0000007FU #define AHB_DMA_OUTFIFO_CNT_CH1_M (AHB_DMA_OUTFIFO_CNT_CH1_V << AHB_DMA_OUTFIFO_CNT_CH1_S) #define AHB_DMA_OUTFIFO_CNT_CH1_V 0x0000007FU #define AHB_DMA_OUTFIFO_CNT_CH1_S 8 /** AHB_DMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1 (BIT(23)) #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_S) #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_S 23 /** AHB_DMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1 (BIT(24)) #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_S) #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_S 24 /** AHB_DMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1 (BIT(25)) #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_S) #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_V 0x00000001U #define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_S 25 /** AHB_DMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; - * Reserved. + * reserved */ #define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1 (BIT(26)) #define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_M (AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_S) @@ -2054,16 +2178,16 @@ extern "C" { */ #define AHB_DMA_OUT_PUSH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x19c) /** AHB_DMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0; - * Represents the data that need to be pushed into AHB DMA TX FIFO. + * Configures whether to push data into AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Push */ #define AHB_DMA_OUTFIFO_WDATA_CH1 0x000001FFU #define AHB_DMA_OUTFIFO_WDATA_CH1_M (AHB_DMA_OUTFIFO_WDATA_CH1_V << AHB_DMA_OUTFIFO_WDATA_CH1_S) #define AHB_DMA_OUTFIFO_WDATA_CH1_V 0x000001FFU #define AHB_DMA_OUTFIFO_WDATA_CH1_S 0 /** AHB_DMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0; - * Configures whether to push data into AHB DMA TX FIFO. - * 0: Invalid. No effect - * 1: Push + * Configures the data that need to be pushed into AHB_DMA FIFO. */ #define AHB_DMA_OUTFIFO_PUSH_CH1 (BIT(9)) #define AHB_DMA_OUTFIFO_PUSH_CH1_M (AHB_DMA_OUTFIFO_PUSH_CH1_V << AHB_DMA_OUTFIFO_PUSH_CH1_S) @@ -2071,11 +2195,11 @@ extern "C" { #define AHB_DMA_OUTFIFO_PUSH_CH1_S 9 /** AHB_DMA_OUT_LINK_CH1_REG register - * Linked list descriptor configuration and control register of TX channel 1 + * Push control register of TX channel 1 */ #define AHB_DMA_OUT_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a0) /** AHB_DMA_OUTLINK_STOP_CH1 : WT; bitpos: [0]; default: 0; - * Configures whether to stop TX channel 1 from transmitting data. + * Configures whether to stop AHB_DMA's TX channel 1 from transmitting data. * 0: Invalid. No effect * 1: Stop */ @@ -2084,7 +2208,7 @@ extern "C" { #define AHB_DMA_OUTLINK_STOP_CH1_V 0x00000001U #define AHB_DMA_OUTLINK_STOP_CH1_S 0 /** AHB_DMA_OUTLINK_START_CH1 : WT; bitpos: [1]; default: 0; - * Configures whether to enable TX channel 1 for data transfer. + * Configures whether to enable AHB_DMA's TX channel 1 for data transfer. * 0: Disable * 1: Enable */ @@ -2093,7 +2217,7 @@ extern "C" { #define AHB_DMA_OUTLINK_START_CH1_V 0x00000001U #define AHB_DMA_OUTLINK_START_CH1_S 1 /** AHB_DMA_OUTLINK_RESTART_CH1 : WT; bitpos: [2]; default: 0; - * Configures whether to restart TX channel 1 for AHB DMA transfer. + * Configures whether to restart TX channel 1 for AHB_DMA transfer. * 0: Invalid. No effect * 1: Restart */ @@ -2112,28 +2236,26 @@ extern "C" { #define AHB_DMA_OUTLINK_PARK_CH1_S 3 /** AHB_DMA_OUT_STATE_CH1_REG register - * TX channel 1 status + * Transmit status of TX channel 1 */ #define AHB_DMA_OUT_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a4) /** AHB_DMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the next transmit descriptor address that is - * pre-read (but not processed yet). If the current transmit descriptor is the last - * descriptor, then this field represents the address of the current transmit - * descriptor. + * Represents the lower 18 bits of the address of the next transmit descriptor to be + * processed. */ #define AHB_DMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFFU #define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_M (AHB_DMA_OUTLINK_DSCR_ADDR_CH1_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH1_S) #define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_V 0x0003FFFFU #define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_S 0 /** AHB_DMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; - * Reserved. + * reserved */ #define AHB_DMA_OUT_DSCR_STATE_CH1 0x00000003U #define AHB_DMA_OUT_DSCR_STATE_CH1_M (AHB_DMA_OUT_DSCR_STATE_CH1_V << AHB_DMA_OUT_DSCR_STATE_CH1_S) #define AHB_DMA_OUT_DSCR_STATE_CH1_V 0x00000003U #define AHB_DMA_OUT_DSCR_STATE_CH1_S 18 /** AHB_DMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0; - * Reserved. + * reserved */ #define AHB_DMA_OUT_STATE_CH1 0x00000007U #define AHB_DMA_OUT_STATE_CH1_M (AHB_DMA_OUT_STATE_CH1_V << AHB_DMA_OUT_STATE_CH1_S) @@ -2167,13 +2289,12 @@ extern "C" { #define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 /** AHB_DMA_OUT_DSCR_CH1_REG register - * Address of the next transmit descriptor pointed by the current pre-read transmit - * descriptor on TX channel 1 + * Current transmit descriptor address of TX channel 1 */ #define AHB_DMA_OUT_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b0) /** AHB_DMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; * Represents the address of the next transmit descriptor y+1 pointed by the current - * transmit descriptor that is pre-read. + * transmit descriptor that has already been fetched. */ #define AHB_DMA_OUTLINK_DSCR_CH1 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_CH1_M (AHB_DMA_OUTLINK_DSCR_CH1_V << AHB_DMA_OUTLINK_DSCR_CH1_S) @@ -2181,11 +2302,12 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_CH1_S 0 /** AHB_DMA_OUT_DSCR_BF0_CH1_REG register - * Address of the current pre-read transmit descriptor on TX channel 1 + * The last transmit descriptor address of TX channel 1 */ #define AHB_DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b4) /** AHB_DMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current transmit descriptor y that is pre-read. + * Represents the address of the current transmit descriptor y that has already been + * fetched. */ #define AHB_DMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_BF0_CH1_M (AHB_DMA_OUTLINK_DSCR_BF0_CH1_V << AHB_DMA_OUTLINK_DSCR_BF0_CH1_S) @@ -2193,25 +2315,25 @@ extern "C" { #define AHB_DMA_OUTLINK_DSCR_BF0_CH1_S 0 /** AHB_DMA_OUT_DSCR_BF1_CH1_REG register - * Address of the previous pre-read transmit descriptor on TX channel 1 + * The second-to-last transmit descriptor address of TX channel 1 */ #define AHB_DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b8) /** AHB_DMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous transmit descriptor y-1 that is pre-read. + * Represents the address of the previous transmit descriptor y-1 that has already + * been fetched. */ #define AHB_DMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_BF1_CH1_M (AHB_DMA_OUTLINK_DSCR_BF1_CH1_V << AHB_DMA_OUTLINK_DSCR_BF1_CH1_S) #define AHB_DMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFFU #define AHB_DMA_OUTLINK_DSCR_BF1_CH1_S 0 -/** AHB_DMA_OUT_PRI_CH1_REG register +/** AHB_DMA_OUT_PERI_CH1_REG register * Priority register of TX channel 1 */ -#define AHB_DMA_OUT_PRI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1bc) +#define AHB_DMA_OUT_PERI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1bc) /** AHB_DMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of TX channel 1. The larger the value, the higher the - * priority. - * Value range: 0 ~ 5 + * Configures the priority of TX channel 1.The larger of the value, the higher of the + * priority.. */ #define AHB_DMA_TX_PRI_CH1 0x0000000FU #define AHB_DMA_TX_PRI_CH1_M (AHB_DMA_TX_PRI_CH1_V << AHB_DMA_TX_PRI_CH1_S) @@ -2225,14 +2347,13 @@ extern "C" { /** AHB_DMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; * Configures the peripheral connected to TX channel 1. * 0: Dummy - * 1: GP-SPI + * 1: SPI2 * 2: Dummy - * 3: I2S + * 3: I2S0 * 4 ~ 6: Dummy * 7: SHA - * 8: ADC - * 9 ~ 15: Dummy - * 16 ~ 63: Invalid + * 8: ADC_DAC + * 9~15: Dummy */ #define AHB_DMA_PERI_OUT_SEL_CH1 0x0000003FU #define AHB_DMA_PERI_OUT_SEL_CH1_M (AHB_DMA_PERI_OUT_SEL_CH1_V << AHB_DMA_PERI_OUT_SEL_CH1_S) @@ -2240,7 +2361,7 @@ extern "C" { #define AHB_DMA_PERI_OUT_SEL_CH1_S 0 /** AHB_DMA_OUT_DONE_DES_ADDR_CH1_REG register - * Address of the completed outlink descriptor on TX channel 1 + * TX done outlink descriptor address of TX channel 1 */ #define AHB_DMA_OUT_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1d0) /** AHB_DMA_OUT_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; @@ -2251,120 +2372,108 @@ extern "C" { #define AHB_DMA_OUT_DONE_DES_ADDR_CH1_V 0xFFFFFFFFU #define AHB_DMA_OUT_DONE_DES_ADDR_CH1_S 0 -/** AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG register +/** AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG register * TX channel 0 arbitration weight configuration register */ -#define AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2dc) -/** AHB_DMA_TX_CH_ARB_WEIGH_CH0 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight (i.e the number of tokens) of TX channel0. - * Value range: 0 ~ 15. +#define AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2dc) +/** AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of TX channel0 */ -#define AHB_DMA_TX_CH_ARB_WEIGH_CH0 0x0000000FU -#define AHB_DMA_TX_CH_ARB_WEIGH_CH0_M (AHB_DMA_TX_CH_ARB_WEIGH_CH0_V << AHB_DMA_TX_CH_ARB_WEIGH_CH0_S) -#define AHB_DMA_TX_CH_ARB_WEIGH_CH0_V 0x0000000FU -#define AHB_DMA_TX_CH_ARB_WEIGH_CH0_S 0 +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0 0x0000000FU +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_M (AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_V << AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_S) +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_V 0x0000000FU +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_S 0 -/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG register +/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG register * TX channel 0 weight arbitration optimization enable register */ -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2e0) -/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight optimization for TX channel 0. - * 0: Disable - * 1: Enable +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2e0) +/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [0]; default: 0; + * reserved */ -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0 (BIT(0)) -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_M (AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_V << AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_S) -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_V 0x00000001U -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_S 0 +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0 (BIT(0)) +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_M (AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_V << AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_S) +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_V 0x00000001U +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_S 0 -/** AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG register +/** AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG register * TX channel 1 arbitration weight configuration register */ -#define AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x304) -/** AHB_DMA_TX_CH_ARB_WEIGH_CH1 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight (i.e the number of tokens) of TX channel1. - * Value range: 0 ~ 15. +#define AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG (DR_REG_AHB_DMA_BASE + 0x304) +/** AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of TX channel1 */ -#define AHB_DMA_TX_CH_ARB_WEIGH_CH1 0x0000000FU -#define AHB_DMA_TX_CH_ARB_WEIGH_CH1_M (AHB_DMA_TX_CH_ARB_WEIGH_CH1_V << AHB_DMA_TX_CH_ARB_WEIGH_CH1_S) -#define AHB_DMA_TX_CH_ARB_WEIGH_CH1_V 0x0000000FU -#define AHB_DMA_TX_CH_ARB_WEIGH_CH1_S 0 +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1 0x0000000FU +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_M (AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_V << AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_S) +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_V 0x0000000FU +#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_S 0 -/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG register +/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG register * TX channel 1 weight arbitration optimization enable register */ -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x308) -/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight optimization for TX channel 1. - * 0: Disable - * 1: Enable +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x308) +/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [0]; default: 0; + * reserved */ -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1 (BIT(0)) -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_M (AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_V << AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_S) -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_V 0x00000001U -#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_S 0 +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1 (BIT(0)) +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_M (AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_V << AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_S) +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_V 0x00000001U +#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_S 0 -/** AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG register +/** AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG register * RX channel 0 arbitration weight configuration register */ -#define AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG (DR_REG_AHB_DMA_BASE + 0x354) -/** AHB_DMA_RX_CH_ARB_WEIGH_CH0 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight (i.e the number of tokens) of RX channel0. - * Value range: 0 ~ 15. +#define AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG (DR_REG_AHB_DMA_BASE + 0x354) +/** AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of RX channel0 */ -#define AHB_DMA_RX_CH_ARB_WEIGH_CH0 0x0000000FU -#define AHB_DMA_RX_CH_ARB_WEIGH_CH0_M (AHB_DMA_RX_CH_ARB_WEIGH_CH0_V << AHB_DMA_RX_CH_ARB_WEIGH_CH0_S) -#define AHB_DMA_RX_CH_ARB_WEIGH_CH0_V 0x0000000FU -#define AHB_DMA_RX_CH_ARB_WEIGH_CH0_S 0 +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0 0x0000000FU +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_M (AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_V << AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_S) +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_V 0x0000000FU +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_S 0 -/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG register +/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG register * RX channel 0 weight arbitration optimization enable register */ -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x358) -/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight optimization for RX channel 0. - * 0: Disable - * 1: Enable +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x358) +/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [0]; default: 0; + * reserved */ -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0 (BIT(0)) -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_M (AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_V << AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_S) -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_V 0x00000001U -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_S 0 +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0 (BIT(0)) +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_M (AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_V << AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_S) +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_V 0x00000001U +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_S 0 -/** AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG register +/** AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG register * RX channel 1 arbitration weight configuration register */ -#define AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x37c) -/** AHB_DMA_RX_CH_ARB_WEIGH_CH1 : R/W; bitpos: [3:0]; default: 0; - * Configures the weight (i.e the number of tokens) of RX channel1. - * Value range: 0 ~ 15. +#define AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG (DR_REG_AHB_DMA_BASE + 0x37c) +/** AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of RX channel1 */ -#define AHB_DMA_RX_CH_ARB_WEIGH_CH1 0x0000000FU -#define AHB_DMA_RX_CH_ARB_WEIGH_CH1_M (AHB_DMA_RX_CH_ARB_WEIGH_CH1_V << AHB_DMA_RX_CH_ARB_WEIGH_CH1_S) -#define AHB_DMA_RX_CH_ARB_WEIGH_CH1_V 0x0000000FU -#define AHB_DMA_RX_CH_ARB_WEIGH_CH1_S 0 +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1 0x0000000FU +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_M (AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_V << AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_S) +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_V 0x0000000FU +#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_S 0 -/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG register +/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG register * RX channel 1 weight arbitration optimization enable register */ -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x380) -/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight optimization for RX channel 1. - * 0: Disable - * 1: Enable +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x380) +/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [0]; default: 0; + * reserved */ -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1 (BIT(0)) -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_M (AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_V << AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_S) -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_V 0x00000001U -#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_S 0 +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1 (BIT(0)) +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_M (AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_V << AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_S) +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_V 0x00000001U +#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_S 0 /** AHB_DMA_IN_LINK_ADDR_CH0_REG register - * Linked list descriptor configuration register of RX channel 0 + * Link list descriptor address configuration of RX channel 0 */ #define AHB_DMA_IN_LINK_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3ac) /** AHB_DMA_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; - * Represents the first receive descriptor's address. + * Configures the 32 bits of the first receive descriptor's address */ #define AHB_DMA_INLINK_ADDR_CH0 0xFFFFFFFFU #define AHB_DMA_INLINK_ADDR_CH0_M (AHB_DMA_INLINK_ADDR_CH0_V << AHB_DMA_INLINK_ADDR_CH0_S) @@ -2372,11 +2481,11 @@ extern "C" { #define AHB_DMA_INLINK_ADDR_CH0_S 0 /** AHB_DMA_IN_LINK_ADDR_CH1_REG register - * Linked list descriptor configuration register of RX channel 1 + * Link list descriptor address configuration of RX channel 1 */ #define AHB_DMA_IN_LINK_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x3b0) /** AHB_DMA_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; - * Represents the first receive descriptor's address. + * Configures the 32 bits of the first receive descriptor's address */ #define AHB_DMA_INLINK_ADDR_CH1 0xFFFFFFFFU #define AHB_DMA_INLINK_ADDR_CH1_M (AHB_DMA_INLINK_ADDR_CH1_V << AHB_DMA_INLINK_ADDR_CH1_S) @@ -2384,11 +2493,11 @@ extern "C" { #define AHB_DMA_INLINK_ADDR_CH1_S 0 /** AHB_DMA_OUT_LINK_ADDR_CH0_REG register - * Linked list descriptor configuration register of TX channel 0 + * Link list descriptor address configuration of TX channel 0 */ #define AHB_DMA_OUT_LINK_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3b8) /** AHB_DMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0; - * Represents the first transmit descriptor's address. + * Configures the 32 bits of the first receive descriptor's address. */ #define AHB_DMA_OUTLINK_ADDR_CH0 0xFFFFFFFFU #define AHB_DMA_OUTLINK_ADDR_CH0_M (AHB_DMA_OUTLINK_ADDR_CH0_V << AHB_DMA_OUTLINK_ADDR_CH0_S) @@ -2396,11 +2505,11 @@ extern "C" { #define AHB_DMA_OUTLINK_ADDR_CH0_S 0 /** AHB_DMA_OUT_LINK_ADDR_CH1_REG register - * Linked list descriptor configuration register of TX channel 1 + * Link list descriptor address configuration of TX channel 1 */ #define AHB_DMA_OUT_LINK_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x3bc) /** AHB_DMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0; - * Represents the first transmit descriptor's address. + * Configures the 32 bits of the first receive descriptor's address. */ #define AHB_DMA_OUTLINK_ADDR_CH1 0xFFFFFFFFU #define AHB_DMA_OUTLINK_ADDR_CH1_M (AHB_DMA_OUTLINK_ADDR_CH1_V << AHB_DMA_OUTLINK_ADDR_CH1_S) @@ -2412,7 +2521,7 @@ extern "C" { */ #define AHB_DMA_INTR_MEM_START_ADDR_REG (DR_REG_AHB_DMA_BASE + 0x3c4) /** AHB_DMA_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; - * Configures the start address of accessible address space. + * Accessible address space start address configuration register */ #define AHB_DMA_ACCESS_INTR_MEM_START_ADDR 0xFFFFFFFFU #define AHB_DMA_ACCESS_INTR_MEM_START_ADDR_M (AHB_DMA_ACCESS_INTR_MEM_START_ADDR_V << AHB_DMA_ACCESS_INTR_MEM_START_ADDR_S) @@ -2483,6 +2592,139 @@ extern "C" { #define AHB_DMA_WEIGHT_EN_RX_V 0x00000001U #define AHB_DMA_WEIGHT_EN_RX_S 0 +/** AHB_DMA_ARB_TIMEOUT_REG register + * TX arbitration timeout configuration register + */ +#define AHB_DMA_ARB_TIMEOUT_REG (DR_REG_AHB_DMA_BASE + 0x3dc) +/** AHB_DMA_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0; + * Configures the time slot. Measurement unit: AHB bus clock cycle. + */ +#define AHB_DMA_ARB_TIMEOUT_NUM 0x0000FFFFU +#define AHB_DMA_ARB_TIMEOUT_NUM_M (AHB_DMA_ARB_TIMEOUT_NUM_V << AHB_DMA_ARB_TIMEOUT_NUM_S) +#define AHB_DMA_ARB_TIMEOUT_NUM_V 0x0000FFFFU +#define AHB_DMA_ARB_TIMEOUT_NUM_S 0 + +/** AHB_DMA_WEIGHT_EN_REG register + * TX weight arbitration enable register + */ +#define AHB_DMA_WEIGHT_EN_REG (DR_REG_AHB_DMA_BASE + 0x400) +/** AHB_DMA_WEIGHT_EN : R/W; bitpos: [0]; default: 0; + * Configures whether to enable weight arbitration. + * 0: Disable + * 1: Enable + */ +#define AHB_DMA_WEIGHT_EN (BIT(0)) +#define AHB_DMA_WEIGHT_EN_M (AHB_DMA_WEIGHT_EN_V << AHB_DMA_WEIGHT_EN_S) +#define AHB_DMA_WEIGHT_EN_V 0x00000001U +#define AHB_DMA_WEIGHT_EN_S 0 + +/** AHB_DMA_MODULE_CLK_EN_REG register + * Module clock force on register + */ +#define AHB_DMA_MODULE_CLK_EN_REG (DR_REG_AHB_DMA_BASE + 0x404) +/** AHB_DMA_AHB_APB_SYNC_CLK_EN : R/W; bitpos: [1:0]; default: 3; + * Configures whether to force on ahb_apb_sync 1~0 module clock. For bit n: + * 0 : Not force on ahb_apb_sync n clock + * 1 : Force on ahb_apb_sync n clock + */ +#define AHB_DMA_AHB_APB_SYNC_CLK_EN 0x00000003U +#define AHB_DMA_AHB_APB_SYNC_CLK_EN_M (AHB_DMA_AHB_APB_SYNC_CLK_EN_V << AHB_DMA_AHB_APB_SYNC_CLK_EN_S) +#define AHB_DMA_AHB_APB_SYNC_CLK_EN_V 0x00000003U +#define AHB_DMA_AHB_APB_SYNC_CLK_EN_S 0 +/** AHB_DMA_OUT_DSCR_CLK_EN : R/W; bitpos: [3:2]; default: 7; + * Configures whether to force on out_dscr 1~0 module clock. For bit n: + * 0 : Not force on out_dscr n clock + * 1 : Force on out_dscr n clock + */ +#define AHB_DMA_OUT_DSCR_CLK_EN 0x00000003U +#define AHB_DMA_OUT_DSCR_CLK_EN_M (AHB_DMA_OUT_DSCR_CLK_EN_V << AHB_DMA_OUT_DSCR_CLK_EN_S) +#define AHB_DMA_OUT_DSCR_CLK_EN_V 0x00000003U +#define AHB_DMA_OUT_DSCR_CLK_EN_S 2 +/** AHB_DMA_OUT_CTRL_CLK_EN : R/W; bitpos: [5:4]; default: 7; + * Configures whether to force on out_ctrl 1~0 module clock. For bit n: + * 0 : Not force on out_ctrl n clock + * 1 : Force on out_ctrl n clock + */ +#define AHB_DMA_OUT_CTRL_CLK_EN 0x00000003U +#define AHB_DMA_OUT_CTRL_CLK_EN_M (AHB_DMA_OUT_CTRL_CLK_EN_V << AHB_DMA_OUT_CTRL_CLK_EN_S) +#define AHB_DMA_OUT_CTRL_CLK_EN_V 0x00000003U +#define AHB_DMA_OUT_CTRL_CLK_EN_S 4 +/** AHB_DMA_IN_DSCR_CLK_EN : R/W; bitpos: [7:6]; default: 7; + * Configures whether to force on in_dscr 1~0 module clock. For bit n: + * 0 : Not force on in_dscr n clock + * 1 : Force on in_dscr n clock + */ +#define AHB_DMA_IN_DSCR_CLK_EN 0x00000003U +#define AHB_DMA_IN_DSCR_CLK_EN_M (AHB_DMA_IN_DSCR_CLK_EN_V << AHB_DMA_IN_DSCR_CLK_EN_S) +#define AHB_DMA_IN_DSCR_CLK_EN_V 0x00000003U +#define AHB_DMA_IN_DSCR_CLK_EN_S 6 +/** AHB_DMA_IN_CTRL_CLK_EN : R/W; bitpos: [9:8]; default: 7; + * Configures whether to force on in_ctrl 1~0 module clock. For bit n: + * 0 : Not force on in_ctrl n clock + * 1 : Force on in_ctrl n clock + */ +#define AHB_DMA_IN_CTRL_CLK_EN 0x00000003U +#define AHB_DMA_IN_CTRL_CLK_EN_M (AHB_DMA_IN_CTRL_CLK_EN_V << AHB_DMA_IN_CTRL_CLK_EN_S) +#define AHB_DMA_IN_CTRL_CLK_EN_V 0x00000003U +#define AHB_DMA_IN_CTRL_CLK_EN_S 8 +/** AHB_DMA_CMD_ARB_CLK_EN : R/W; bitpos: [27]; default: 0; + * Configures whether to force on cmd_arb module clock. + * 0 : Not force on cmd_arb clock + * 1 : Force on cmd_arb clock + */ +#define AHB_DMA_CMD_ARB_CLK_EN (BIT(27)) +#define AHB_DMA_CMD_ARB_CLK_EN_M (AHB_DMA_CMD_ARB_CLK_EN_V << AHB_DMA_CMD_ARB_CLK_EN_S) +#define AHB_DMA_CMD_ARB_CLK_EN_V 0x00000001U +#define AHB_DMA_CMD_ARB_CLK_EN_S 27 +/** AHB_DMA_AHBINF_CLK_EN : R/W; bitpos: [28]; default: 0; + * Configures whether to force on ahbinf module clock. + * 0 : Not force on ahbinf clock + * 1 : Force on ahbinf clock + */ +#define AHB_DMA_AHBINF_CLK_EN (BIT(28)) +#define AHB_DMA_AHBINF_CLK_EN_M (AHB_DMA_AHBINF_CLK_EN_V << AHB_DMA_AHBINF_CLK_EN_S) +#define AHB_DMA_AHBINF_CLK_EN_V 0x00000001U +#define AHB_DMA_AHBINF_CLK_EN_S 28 + +/** AHB_DMA_AHBINF_RESP_ERR_STATUS0_REG register + * AHB response error status 0 register + */ +#define AHB_DMA_AHBINF_RESP_ERR_STATUS0_REG (DR_REG_AHB_DMA_BASE + 0x408) +/** AHB_DMA_AHBINF_RESP_ERR_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents the address of the AHB response error. + */ +#define AHB_DMA_AHBINF_RESP_ERR_ADDR 0xFFFFFFFFU +#define AHB_DMA_AHBINF_RESP_ERR_ADDR_M (AHB_DMA_AHBINF_RESP_ERR_ADDR_V << AHB_DMA_AHBINF_RESP_ERR_ADDR_S) +#define AHB_DMA_AHBINF_RESP_ERR_ADDR_V 0xFFFFFFFFU +#define AHB_DMA_AHBINF_RESP_ERR_ADDR_S 0 + +/** AHB_DMA_AHBINF_RESP_ERR_STATUS1_REG register + * AHB response error status 1 register + */ +#define AHB_DMA_AHBINF_RESP_ERR_STATUS1_REG (DR_REG_AHB_DMA_BASE + 0x40c) +/** AHB_DMA_AHBINF_RESP_ERR_WR : RO; bitpos: [0]; default: 0; + * Represents the AHB response error is write request. + */ +#define AHB_DMA_AHBINF_RESP_ERR_WR (BIT(0)) +#define AHB_DMA_AHBINF_RESP_ERR_WR_M (AHB_DMA_AHBINF_RESP_ERR_WR_V << AHB_DMA_AHBINF_RESP_ERR_WR_S) +#define AHB_DMA_AHBINF_RESP_ERR_WR_V 0x00000001U +#define AHB_DMA_AHBINF_RESP_ERR_WR_S 0 +/** AHB_DMA_AHBINF_RESP_ERR_ID : RO; bitpos: [4:1]; default: 15; + * Represents the AHB response error request id. + */ +#define AHB_DMA_AHBINF_RESP_ERR_ID 0x0000000FU +#define AHB_DMA_AHBINF_RESP_ERR_ID_M (AHB_DMA_AHBINF_RESP_ERR_ID_V << AHB_DMA_AHBINF_RESP_ERR_ID_S) +#define AHB_DMA_AHBINF_RESP_ERR_ID_V 0x0000000FU +#define AHB_DMA_AHBINF_RESP_ERR_ID_S 1 +/** AHB_DMA_AHBINF_RESP_ERR_CH_ID : RO; bitpos: [6:5]; default: 0; + * Represents the AHB response error request channel id.bit[1]=1:TX channel. + * bit[1]=0:RX channel. + */ +#define AHB_DMA_AHBINF_RESP_ERR_CH_ID 0x00000003U +#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_M (AHB_DMA_AHBINF_RESP_ERR_CH_ID_V << AHB_DMA_AHBINF_RESP_ERR_CH_ID_S) +#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_V 0x00000003U +#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_S 5 + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32c61/register/soc/ahb_dma_struct.h b/components/soc/esp32c61/register/soc/ahb_dma_struct.h index 13a4972de7..8223aa558e 100644 --- a/components/soc/esp32c61/register/soc/ahb_dma_struct.h +++ b/components/soc/esp32c61/register/soc/ahb_dma_struct.h @@ -1,7 +1,7 @@ /** - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -12,315 +12,366 @@ extern "C" { /** Group: Interrupt Registers */ /** Type of in_int_raw_chn register - * RX channel n raw interrupt status register + * Raw interrupt status of RX channel 0 */ typedef union { struct { /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DONE_CHn_INT. + * The raw interrupt status of AHB_DMA_IN_DONE_CHn_INT */ uint32_t in_done_chn_int_raw:1; /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CHn_INT. + * The raw interrupt status of AHB_DMA_IN_SUC_EOF_CHn_INT */ uint32_t in_suc_eof_chn_int_raw:1; /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CHn_INT. + * The raw interrupt status of AHB_DMA_IN_ERR_EOF_CHn_INT */ uint32_t in_err_eof_chn_int_raw:1; /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CHn_INT. + * The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CHn_INT */ uint32_t in_dscr_err_chn_int_raw:1; /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CHn_INT. + * The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CHn_INT */ uint32_t in_dscr_empty_chn_int_raw:1; /** infifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_OVF_CHn_INT. + * The raw interrupt status of AHB_DMA_INFIFO_OVF_CHn_INT */ uint32_t infifo_ovf_chn_int_raw:1; /** infifo_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt status of AHB_DMA_INFIFO_UDF_CHn_INT. + * The raw interrupt status of AHB_DMA_INFIFO_UDF_CHn_INT */ uint32_t infifo_udf_chn_int_raw:1; - uint32_t reserved_7:25; + /** in_ahbinf_resp_err_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt status of AHB_DMA_IN_RESP_ERR_CHn_INT + */ + uint32_t in_ahbinf_resp_err_chn_int_raw:1; + uint32_t reserved_8:24; }; uint32_t val; } ahb_dma_in_int_raw_chn_reg_t; + +/** Group: Status Registers */ /** Type of in_int_st_chn register - * RX channel n masked interrupt status register + * Masked interrupt status of RX channel 0 */ typedef union { struct { /** in_done_chn_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DONE_CHn_INT. + * The masked interrupt status of AHB_DMA_IN_DONE_CHn_INT */ uint32_t in_done_chn_int_st:1; /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CHn_INT. + * The masked interrupt status of AHB_DMA_IN_SUC_EOF_CHn_INT */ uint32_t in_suc_eof_chn_int_st:1; /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CHn_INT. + * The masked interrupt status of AHB_DMA_IN_ERR_EOF_CHn_INT */ uint32_t in_err_eof_chn_int_st:1; /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CHn_INT. + * The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CHn_INT */ uint32_t in_dscr_err_chn_int_st:1; /** in_dscr_empty_chn_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CHn_INT. + * The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CHn_INT */ uint32_t in_dscr_empty_chn_int_st:1; /** infifo_ovf_chn_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_OVF_CHn_INT. + * The masked interrupt status of AHB_DMA_INFIFO_OVF_CHn_INT */ uint32_t infifo_ovf_chn_int_st:1; /** infifo_udf_chn_int_st : RO; bitpos: [6]; default: 0; - * The masked interrupt status of AHB_DMA_INFIFO_UDF_CHn_INT. + * The masked interrupt status of AHB_DMA_INFIFO_UDF_CHn_INT */ uint32_t infifo_udf_chn_int_st:1; - uint32_t reserved_7:25; + /** in_ahbinf_resp_err_chn_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status of AHB_DMA_IN_RESP_ERR_CHn_INT + */ + uint32_t in_ahbinf_resp_err_chn_int_st:1; + uint32_t reserved_8:24; }; uint32_t val; } ahb_dma_in_int_st_chn_reg_t; /** Type of in_int_ena_chn register - * RX channel n interrupt enable register + * Interrupt enable bits of RX channel 0 */ typedef union { struct { /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_IN_DONE_CHn_INT. + * Write 1 to enable AHB_DMA_IN_DONE_CHn_INT */ uint32_t in_done_chn_int_ena:1; /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_IN_SUC_EOF_CHn_INT. + * Write 1 to enable AHB_DMA_IN_SUC_EOF_CHn_INT */ uint32_t in_suc_eof_chn_int_ena:1; /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_IN_ERR_EOF_CHn_INT. + * Write 1 to enable AHB_DMA_IN_ERR_EOF_CHn_INT */ uint32_t in_err_eof_chn_int_ena:1; /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CHn_INT. + * Write 1 to enable AHB_DMA_IN_DSCR_ERR_CHn_INT */ uint32_t in_dscr_err_chn_int_ena:1; /** in_dscr_empty_chn_int_ena : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CHn_INT. + * Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CHn_INT */ uint32_t in_dscr_empty_chn_int_ena:1; /** infifo_ovf_chn_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_OVF_CHn_INT. + * Write 1 to enable AHB_DMA_INFIFO_OVF_CHn_INT */ uint32_t infifo_ovf_chn_int_ena:1; /** infifo_udf_chn_int_ena : R/W; bitpos: [6]; default: 0; - * Write 1 to enable AHB_DMA_INFIFO_UDF_CHn_INT. + * Write 1 to enable AHB_DMA_INFIFO_UDF_CHn_INT */ uint32_t infifo_udf_chn_int_ena:1; - uint32_t reserved_7:25; + /** in_ahbinf_resp_err_chn_int_ena : R/W; bitpos: [7]; default: 0; + * Write 1 to enable AHB_DMA_IN_RESP_ERR_CHn_INT + */ + uint32_t in_ahbinf_resp_err_chn_int_ena:1; + uint32_t reserved_8:24; }; uint32_t val; } ahb_dma_in_int_ena_chn_reg_t; /** Type of in_int_clr_chn register - * RX channel n interrupt clear register + * Interrupt clear bits of RX channel 0 */ typedef union { struct { /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_IN_DONE_CHn_INT. + * Write 1 to clear AHB_DMA_IN_DONE_CHn_INT */ uint32_t in_done_chn_int_clr:1; /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_IN_SUC_EOF_CHn_INT. + * Write 1 to clear AHB_DMA_IN_SUC_EOF_CHn_INT */ uint32_t in_suc_eof_chn_int_clr:1; /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_IN_ERR_EOF_CHn_INT. + * Write 1 to clear AHB_DMA_IN_ERR_EOF_CHn_INT */ uint32_t in_err_eof_chn_int_clr:1; /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CHn_INT. + * Write 1 to clear AHB_DMA_IN_DSCR_ERR_CHn_INT */ uint32_t in_dscr_err_chn_int_clr:1; /** in_dscr_empty_chn_int_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CHn_INT. + * Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CHn_INT */ uint32_t in_dscr_empty_chn_int_clr:1; /** infifo_ovf_chn_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_OVF_CHn_INT. + * Write 1 to clear AHB_DMA_INFIFO_OVF_CHn_INT */ uint32_t infifo_ovf_chn_int_clr:1; /** infifo_udf_chn_int_clr : WT; bitpos: [6]; default: 0; - * Write 1 to clear AHB_DMA_INFIFO_UDF_CHn_INT. + * Write 1 to clear AHB_DMA_INFIFO_UDF_CHn_INT */ uint32_t infifo_udf_chn_int_clr:1; - uint32_t reserved_7:25; + /** in_ahbinf_resp_err_chn_int_clr : WT; bitpos: [7]; default: 0; + * Write 1 to clear AHB_DMA_IN_RESP_ERR_CHn_INT + */ + uint32_t in_ahbinf_resp_err_chn_int_clr:1; + uint32_t reserved_8:24; }; uint32_t val; } ahb_dma_in_int_clr_chn_reg_t; /** Type of out_int_raw_chn register - * TX channel n raw interrupt status register + * //Raw interrupt status of TX channel 0 */ typedef union { struct { /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DONE_CHn_INT. + * The raw interrupt status of AHB_DMA_OUT_DONE_CHn_INT */ uint32_t out_done_chn_int_raw:1; /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_EOF_CHn_INT. + * The raw interrupt status of AHB_DMA_OUT_EOF_CHn_INT */ uint32_t out_eof_chn_int_raw:1; /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CHn_INT. + * The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CHn_INT */ uint32_t out_dscr_err_chn_int_raw:1; /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CHn_INT. + * The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CHn_INT */ uint32_t out_total_eof_chn_int_raw:1; /** outfifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CHn_INT. + * The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CHn_INT */ uint32_t outfifo_ovf_chn_int_raw:1; /** outfifo_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CHn_INT. + * The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CHn_INT */ uint32_t outfifo_udf_chn_int_raw:1; - uint32_t reserved_6:26; + /** out_ahbinf_resp_err_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CHn_INT + */ + uint32_t out_ahbinf_resp_err_chn_int_raw:1; + uint32_t reserved_7:25; }; uint32_t val; } ahb_dma_out_int_raw_chn_reg_t; /** Type of out_int_st_chn register - * TX channel n masked interrupt status register + * Masked interrupt status of TX channel 0 */ typedef union { struct { /** out_done_chn_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DONE_CHn_INT. + * The masked interrupt status of AHB_DMA_OUT_DONE_CHn_INT */ uint32_t out_done_chn_int_st:1; /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_EOF_CHn_INT. + * The masked interrupt status of AHB_DMA_OUT_EOF_CHn_INT */ uint32_t out_eof_chn_int_st:1; /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CHn_INT. + * The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CHn_INT */ uint32_t out_dscr_err_chn_int_st:1; /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CHn_INT. + * The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CHn_INT */ uint32_t out_total_eof_chn_int_st:1; /** outfifo_ovf_chn_int_st : RO; bitpos: [4]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CHn_INT. + * The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CHn_INT */ uint32_t outfifo_ovf_chn_int_st:1; /** outfifo_udf_chn_int_st : RO; bitpos: [5]; default: 0; - * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CHn_INT. + * The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CHn_INT */ uint32_t outfifo_udf_chn_int_st:1; - uint32_t reserved_6:26; + /** out_ahbinf_resp_err_chn_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CHn_INT + */ + uint32_t out_ahbinf_resp_err_chn_int_st:1; + uint32_t reserved_7:25; }; uint32_t val; } ahb_dma_out_int_st_chn_reg_t; /** Type of out_int_ena_chn register - * TX channel n interrupt enable register + * Interrupt enable bits of TX channel 0 */ typedef union { struct { /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DONE_CHn_INT. + * Write 1 to enable AHB_DMA_OUT_DONE_CHn_INT */ uint32_t out_done_chn_int_ena:1; /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0; - * Write 1 to enable AHB_DMA_OUT_EOF_CHn_INT. + * Write 1 to enable AHB_DMA_OUT_EOF_CHn_INT */ uint32_t out_eof_chn_int_ena:1; /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0; - * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CHn_INT. + * Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CHn_INT */ uint32_t out_dscr_err_chn_int_ena:1; /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0; - * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CHn_INT. + * Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CHn_INT */ uint32_t out_total_eof_chn_int_ena:1; /** outfifo_ovf_chn_int_ena : R/W; bitpos: [4]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CHn_INT. + * Write 1 to enable AHB_DMA_OUTFIFO_OVF_CHn_INT */ uint32_t outfifo_ovf_chn_int_ena:1; /** outfifo_udf_chn_int_ena : R/W; bitpos: [5]; default: 0; - * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CHn_INT. + * Write 1 to enable AHB_DMA_OUTFIFO_UDF_CHn_INT */ uint32_t outfifo_udf_chn_int_ena:1; - uint32_t reserved_6:26; + /** out_ahbinf_resp_err_chn_int_ena : R/W; bitpos: [6]; default: 0; + * Write 1 to enable AHB_DMA_OUT_RESP_ERR_CHn_INT + */ + uint32_t out_ahbinf_resp_err_chn_int_ena:1; + uint32_t reserved_7:25; }; uint32_t val; } ahb_dma_out_int_ena_chn_reg_t; /** Type of out_int_clr_chn register - * TX channel n interrupt clear register + * Interrupt clear bits of TX channel 0 */ typedef union { struct { /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DONE_CHn_INT. + * Write 1 to clear AHB_DMA_OUT_DONE_CHn_INT */ uint32_t out_done_chn_int_clr:1; /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0; - * Write 1 to clear AHB_DMA_OUT_EOF_CHn_INT. + * Write 1 to clear AHB_DMA_OUT_EOF_CHn_INT */ uint32_t out_eof_chn_int_clr:1; /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0; - * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CHn_INT. + * Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CHn_INT */ uint32_t out_dscr_err_chn_int_clr:1; /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0; - * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CHn_INT. + * Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CHn_INT */ uint32_t out_total_eof_chn_int_clr:1; /** outfifo_ovf_chn_int_clr : WT; bitpos: [4]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CHn_INT. + * Write 1 to clear AHB_DMA_OUTFIFO_OVF_CHn_INT */ uint32_t outfifo_ovf_chn_int_clr:1; /** outfifo_udf_chn_int_clr : WT; bitpos: [5]; default: 0; - * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CHn_INT. + * Write 1 to clear AHB_DMA_OUTFIFO_UDF_CHn_INT */ uint32_t outfifo_udf_chn_int_clr:1; - uint32_t reserved_6:26; + /** out_ahbinf_resp_err_chn_int_clr : WT; bitpos: [6]; default: 0; + * Write 1 to clear AHB_DMA_OUT_RESP_ERR_CHn_INT + */ + uint32_t out_ahbinf_resp_err_chn_int_clr:1; + uint32_t reserved_7:25; }; uint32_t val; } ahb_dma_out_int_clr_chn_reg_t; +/** Type of ahb_test register + * only for test + */ +typedef union { + struct { + /** ahb_testmode : R/W; bitpos: [2:0]; default: 0; + * reserved + */ + uint32_t ahb_testmode:3; + uint32_t reserved_3:1; + /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0; + * reserved + */ + uint32_t ahb_testaddr:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} ahb_dma_ahb_test_reg_t; -/** Group: Configuration Registers */ /** Type of misc_conf register - * Miscellaneous register + * reserved */ typedef union { struct { /** ahbm_rst_inter : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset the internal AHB FSM. + * Write 1 and then 0 to reset the internal AHB FSM */ uint32_t ahbm_rst_inter:1; uint32_t reserved_1:1; /** arb_pri_dis : R/W; bitpos: [2]; default: 0; - * Configures whether to disable the priority arbitration. + * Configures whether to disable the fixed-priority channel arbitration. * 0: Enable * 1: Disable */ uint32_t arb_pri_dis:1; /** clk_en : R/W; bitpos: [3]; default: 0; - * Configures AHB DMA clock gating. - * 0: Support clock only when the application writes registers - * 1: Always force the clock on for registers + * Configures clock gating. + * 0: Support clock only when the application writes registers. + * 1: Always force the clock on for registers. */ uint32_t clk_en:1; uint32_t reserved_4:28; @@ -328,21 +379,34 @@ typedef union { uint32_t val; } ahb_dma_misc_conf_reg_t; +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 2410220; + * Version control register + */ + uint32_t date:32; + }; + uint32_t val; +} ahb_dma_date_reg_t; + /** Type of in_conf0_chn register - * Configuration register 0 of RX channel n + * Configuration register 0 of RX channel 0 */ typedef union { struct { /** in_rst_chn : R/W; bitpos: [0]; default: 0; - * Write 1 and then 0 to reset RX channel n FSM and RX FIFO pointer. + * Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer. */ uint32_t in_rst_chn:1; /** in_loop_test_chn : R/W; bitpos: [1]; default: 0; - * Configures the owner bit value for inlink write-back. + * reserved */ uint32_t in_loop_test_chn:1; /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0; - * Configures whether to enable INCR burst transfer for RX channel n to read + * Configures whether to enable INCR burst transfer for RX channel 0 to read * descriptors. * 0: Disable * 1: Enable @@ -356,17 +420,17 @@ typedef union { */ uint32_t mem_trans_en_chn:1; /** in_etm_en_chn : R/W; bitpos: [5]; default: 0; - * Configures whether to enable ETM control for RX channeln. + * Configures whether to enable ETM control for RX channel0. * 0: Disable * 1: Enable */ uint32_t in_etm_en_chn:1; /** in_data_burst_mode_sel_chn : R/W; bitpos: [7:6]; default: 0; - * Configures maximum burst length for RX channeln. - * 0: SINGLE - * 1: INCR4 - * 2: INCR8 - * 3: Reserved + * Configures max burst size for Rx channel0. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 */ uint32_t in_data_burst_mode_sel_chn:2; uint32_t reserved_8:24; @@ -375,13 +439,13 @@ typedef union { } ahb_dma_in_conf0_chn_reg_t; /** Type of in_conf1_chn register - * Configuration register 1 of RX channel n + * Configuration register 1 of RX channel 0 */ typedef union { struct { uint32_t reserved_0:12; /** in_check_owner_chn : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for RX channel n. + * Configures whether to enable owner bit check for RX channel 0. * 0: Disable * 1: Enable */ @@ -391,17 +455,65 @@ typedef union { uint32_t val; } ahb_dma_in_conf1_chn_reg_t; +/** Type of infifo_status_chn register + * Receive FIFO status of RX channel 0 + */ +typedef union { + struct { + /** infifo_full_chn : RO; bitpos: [0]; default: 1; + * Represents whether L1 RX FIFO is full. + * 0: Not Full + * 1: Full + */ + uint32_t infifo_full_chn:1; + /** infifo_empty_chn : RO; bitpos: [1]; default: 1; + * Represents whether L1 RX FIFO is empty. + * 0: Not empty + * 1: Empty + */ + uint32_t infifo_empty_chn:1; + uint32_t reserved_2:6; + /** infifo_cnt_chn : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 RX FIFO for RX channel 0 + */ + uint32_t infifo_cnt_chn:7; + uint32_t reserved_15:8; + /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t in_remain_under_1b_chn:1; + /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t in_remain_under_2b_chn:1; + /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t in_remain_under_3b_chn:1; + /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t in_remain_under_4b_chn:1; + /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0; + * reserved + */ + uint32_t in_buf_hungry_chn:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} ahb_dma_infifo_status_chn_reg_t; + /** Type of in_pop_chn register - * Pop control register of RX channel n + * Receive FIFO status of RX channel 0 */ typedef union { struct { /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048; - * Represents the data popped from AHB DMA RX FIFO. + * Represents the data popped from AHB_DMA FIFO. */ uint32_t infifo_rdata_chn:12; /** infifo_pop_chn : WT; bitpos: [12]; default: 0; - * Configures whether to pop data from AHB DMA RX FIFO. + * Configures whether to pop data from AHB_DMA FIFO. * 0: Invalid. No effect * 1: Pop */ @@ -412,31 +524,32 @@ typedef union { } ahb_dma_in_pop_chn_reg_t; /** Type of in_link_chn register - * Linked list descriptor configuration and control register of RX channel n + * Receive FIFO status of RX channel 0 */ typedef union { struct { /** inlink_auto_ret_chn : R/W; bitpos: [0]; default: 1; - * Configures whether to return to the current receive descriptor's address when there - * are some errors in current receiving data. + * Configures whether to return to current receive descriptor's address when there are + * some errors in current receiving data. * 0: Not return * 1: Return + * . */ uint32_t inlink_auto_ret_chn:1; /** inlink_stop_chn : WT; bitpos: [1]; default: 0; - * Configures whether to stop RX channel n from receiving data. + * Configures whether to stop AHB_DMA's RX channel 0 from receiving data. * 0: Invalid. No effect * 1: Stop */ uint32_t inlink_stop_chn:1; /** inlink_start_chn : WT; bitpos: [2]; default: 0; - * Configures whether to enable RX channel n for data transfer. + * Configures whether to enable AHB_DMA's RX channel 0 for data transfer. * 0: Disable * 1: Enable */ uint32_t inlink_start_chn:1; /** inlink_restart_chn : WT; bitpos: [3]; default: 0; - * Configures whether to restart RX channel n for AHB DMA transfer. + * Configures whether to restart RX channel 0 for AHB_DMA transfer. * 0: Invalid. No effect * 1: Restart */ @@ -452,19 +565,162 @@ typedef union { uint32_t val; } ahb_dma_in_link_chn_reg_t; +/** Type of in_state_chn register + * Receive status of RX channel 0 + */ +typedef union { + struct { + /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * reserved + */ + uint32_t inlink_dscr_addr_chn:18; + /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t in_dscr_state_chn:2; + /** in_state_chn : RO; bitpos: [22:20]; default: 0; + * Represents the address of the lower 18 bits of the next receive descriptor to be + * processed. + */ + uint32_t in_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} ahb_dma_in_state_chn_reg_t; + +/** Type of in_suc_eof_des_addr_chn register + * Receive descriptor address when EOF occurs on RX channel 0 + */ +typedef union { + struct { + /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t in_suc_eof_des_addr_chn:32; + }; + uint32_t val; +} ahb_dma_in_suc_eof_des_addr_chn_reg_t; + +/** Type of in_err_eof_des_addr_chn register + * Receive descriptor address when errors occur of RX channel 0 + */ +typedef union { + struct { + /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the receive descriptor when there are some errors in the + * currently received data. + */ + uint32_t in_err_eof_des_addr_chn:32; + }; + uint32_t val; +} ahb_dma_in_err_eof_des_addr_chn_reg_t; + +/** Type of in_dscr_chn register + * Current receive descriptor address of RX channel 0 + */ +typedef union { + struct { + /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next receive descriptor x+1 pointed by the current + * receive descriptor that has already been fetched. + */ + uint32_t inlink_dscr_chn:32; + }; + uint32_t val; +} ahb_dma_in_dscr_chn_reg_t; + +/** Type of in_dscr_bf0_chn register + * The last receive descriptor address of RX channel 0 + */ +typedef union { + struct { + /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current receive descriptor x that has already been + * fetched. + */ + uint32_t inlink_dscr_bf0_chn:32; + }; + uint32_t val; +} ahb_dma_in_dscr_bf0_chn_reg_t; + +/** Type of in_dscr_bf1_chn register + * The second-to-last receive descriptor address of RX channel 0 + */ +typedef union { + struct { + /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous receive descriptor x-1 that has already been + * fetched. + */ + uint32_t inlink_dscr_bf1_chn:32; + }; + uint32_t val; +} ahb_dma_in_dscr_bf1_chn_reg_t; + +/** Type of in_peri_chn register + * Priority register of RX channel 0 + */ +typedef union { + struct { + /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of RX channel 0.The larger of the value, the higher of the + * priority.. + */ + uint32_t rx_pri_chn:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_in_peri_chn_reg_t; + +/** Type of in_peri_sel_chn register + * Peripheral selection register of RX channel 0 + */ +typedef union { + struct { + /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to RX channel 0. + * 0: Dummy + * 1: SPI2 + * 2: Dummy + * 3: I2S0 + * 4 ~ 6: Dummy + * 7: SHA + * 8: ADC_DAC + * 9~15: Dummy + */ + uint32_t peri_in_sel_chn:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} ahb_dma_in_peri_sel_chn_reg_t; + +/** Type of in_done_des_addr_ch0 register + * RX_done Inlink descriptor address of RX channel 0 + */ +typedef union { + struct { + /** in_done_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the inlink descriptor when this descriptor is completed . + */ + uint32_t in_done_des_addr_ch0:32; + }; + uint32_t val; +} ahb_dma_in_done_des_addr_ch0_reg_t; + /** Type of out_conf0_chn register - * Configuration register 0 of TX channel n + * Configuration register 0 of TX channel 0 */ typedef union { struct { /** out_rst_chn : R/W; bitpos: [0]; default: 0; - * Configures the reset state of TX channel n FSM and TX FIFO pointer. + * Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer. * 0: Release reset * 1: Reset */ uint32_t out_rst_chn:1; /** out_loop_test_chn : R/W; bitpos: [1]; default: 0; - * Configures the owner bit value for outlink write-back. + * reserved */ uint32_t out_loop_test_chn:1; /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0; @@ -476,14 +732,14 @@ typedef union { uint32_t out_auto_wrback_chn:1; /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1; * Configures when to generate EOF flag. - * 0: EOF flag for TX channel n is generated when data to be transmitted has been - * pushed into FIFO in AHB DMA. - * 1: EOF flag for TX channel n is generated when data to be transmitted has been - * popped from FIFO in AHB DMA. + * 0: EOF flag for TX channel 0 is generated when data to be transmitted has been + * pushed into FIFO in AHB_DMA. + * 1: EOF flag for TX channel 0 is generated when data to be transmitted has been + * popped from FIFO in AHB_DMA. */ uint32_t out_eof_mode_chn:1; /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0; - * Configures whether to enable INCR burst transfer for TX channel n reading + * Configures whether to enable INCR burst transfer for TX channel 0 reading * descriptors. * 0: Disable * 1: Enable @@ -491,18 +747,18 @@ typedef union { uint32_t outdscr_burst_en_chn:1; uint32_t reserved_5:1; /** out_etm_en_chn : R/W; bitpos: [6]; default: 0; - * Configures whether to enable ETM control for TX channel n. + * Configures whether to enable ETM control for TX channel 0. * 0: Disable * 1: Enable */ uint32_t out_etm_en_chn:1; uint32_t reserved_7:1; /** out_data_burst_mode_sel_chn : R/W; bitpos: [9:8]; default: 0; - * Configures maximum burst length for TX channeln. - * 0: SINGLE - * 1: INCR4 - * 2: INCR8 - * 3: Reserved + * Configures max burst size for TX channel0. + * 2'b00: single + * 2'b01: incr4 + * 2'b10: incr8 + * 2'b11: incr16 */ uint32_t out_data_burst_mode_sel_chn:2; uint32_t reserved_10:22; @@ -511,13 +767,13 @@ typedef union { } ahb_dma_out_conf0_chn_reg_t; /** Type of out_conf1_chn register - * Configuration register 1 of TX channel n + * Configuration register 1 of TX channel 0 */ typedef union { struct { uint32_t reserved_0:12; /** out_check_owner_chn : R/W; bitpos: [12]; default: 0; - * Configures whether to enable owner bit check for TX channel n. + * Configures whether to enable owner bit check for TX channel 0. * 0: Disable * 1: Enable */ @@ -527,19 +783,63 @@ typedef union { uint32_t val; } ahb_dma_out_conf1_chn_reg_t; +/** Type of outfifo_status_chn register + * Receive FIFO status of RX channel 0 + */ +typedef union { + struct { + /** outfifo_full_chn : RO; bitpos: [0]; default: 0; + * Represents whether L1 TX FIFO is full. + * 0: Not Full + * 1: Full + */ + uint32_t outfifo_full_chn:1; + /** outfifo_empty_chn : RO; bitpos: [1]; default: 1; + * Represents whether L1 TX FIFO is empty. + * 0: Not empty + * 1: Empty + */ + uint32_t outfifo_empty_chn:1; + uint32_t reserved_2:6; + /** outfifo_cnt_chn : RO; bitpos: [14:8]; default: 0; + * Represents the number of data bytes in L1 TX FIFO for TX channel 0 + */ + uint32_t outfifo_cnt_chn:7; + uint32_t reserved_15:8; + /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1; + * reserved + */ + uint32_t out_remain_under_1b_chn:1; + /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1; + * reserved + */ + uint32_t out_remain_under_2b_chn:1; + /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1; + * reserved + */ + uint32_t out_remain_under_3b_chn:1; + /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1; + * reserved + */ + uint32_t out_remain_under_4b_chn:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} ahb_dma_outfifo_status_chn_reg_t; + /** Type of out_push_chn register - * Push control register of TX channel n + * Push control register of TX channel 0 */ typedef union { struct { /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0; - * Represents the data that need to be pushed into AHB DMA TX FIFO. + * Configures whether to push data into AHB_DMA FIFO. + * 0: Invalid. No effect + * 1: Push */ uint32_t outfifo_wdata_chn:9; /** outfifo_push_chn : WT; bitpos: [9]; default: 0; - * Configures whether to push data into AHB DMA TX FIFO. - * 0: Invalid. No effect - * 1: Push + * Configures the data that need to be pushed into AHB_DMA FIFO. */ uint32_t outfifo_push_chn:1; uint32_t reserved_10:22; @@ -548,24 +848,24 @@ typedef union { } ahb_dma_out_push_chn_reg_t; /** Type of out_link_chn register - * Linked list descriptor configuration and control register of TX channel n + * Push control register of TX channel 0 */ typedef union { struct { /** outlink_stop_chn : WT; bitpos: [0]; default: 0; - * Configures whether to stop TX channel n from transmitting data. + * Configures whether to stop AHB_DMA's TX channel 0 from transmitting data. * 0: Invalid. No effect * 1: Stop */ uint32_t outlink_stop_chn:1; /** outlink_start_chn : WT; bitpos: [1]; default: 0; - * Configures whether to enable TX channel n for data transfer. + * Configures whether to enable AHB_DMA's TX channel 0 for data transfer. * 0: Disable * 1: Enable */ uint32_t outlink_start_chn:1; /** outlink_restart_chn : WT; bitpos: [2]; default: 0; - * Configures whether to restart TX channel n for AHB DMA transfer. + * Configures whether to restart TX channel 0 for AHB_DMA transfer. * 0: Invalid. No effect * 1: Restart */ @@ -581,75 +881,294 @@ typedef union { uint32_t val; } ahb_dma_out_link_chn_reg_t; -/** Type of tx_ch_arb_weigh_chn register - * TX channel n arbitration weight configuration register +/** Type of out_state_chn register + * Transmit status of TX channel 0 */ typedef union { struct { - /** tx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0; - * Configures the weight (i.e the number of tokens) of TX channeln. - * Value range: 0 ~ 15. + /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; + * Represents the lower 18 bits of the address of the next transmit descriptor to be + * processed. */ - uint32_t tx_ch_arb_weigh_chn:4; + uint32_t outlink_dscr_addr_chn:18; + /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0; + * reserved + */ + uint32_t out_dscr_state_chn:2; + /** out_state_chn : RO; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t out_state_chn:3; + uint32_t reserved_23:9; + }; + uint32_t val; +} ahb_dma_out_state_chn_reg_t; + +/** Type of out_eof_des_addr_chn register + * Transmit descriptor address when EOF occurs on TX channel 0 + */ +typedef union { + struct { + /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor when the EOF bit in this + * descriptor is 1. + */ + uint32_t out_eof_des_addr_chn:32; + }; + uint32_t val; +} ahb_dma_out_eof_des_addr_chn_reg_t; + +/** Type of out_eof_bfr_des_addr_chn register + * The last transmit descriptor address when EOF occurs on TX channel 0 + */ +typedef union { + struct { + /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the transmit descriptor before the last transmit + * descriptor. + */ + uint32_t out_eof_bfr_des_addr_chn:32; + }; + uint32_t val; +} ahb_dma_out_eof_bfr_des_addr_chn_reg_t; + +/** Type of out_dscr_chn register + * Current transmit descriptor address of TX channel 0 + */ +typedef union { + struct { + /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the next transmit descriptor y+1 pointed by the current + * transmit descriptor that has already been fetched. + */ + uint32_t outlink_dscr_chn:32; + }; + uint32_t val; +} ahb_dma_out_dscr_chn_reg_t; + +/** Type of out_dscr_bf0_chn register + * The last transmit descriptor address of TX channel 0 + */ +typedef union { + struct { + /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the current transmit descriptor y that has already been + * fetched. + */ + uint32_t outlink_dscr_bf0_chn:32; + }; + uint32_t val; +} ahb_dma_out_dscr_bf0_chn_reg_t; + +/** Type of out_dscr_bf1_chn register + * The second-to-last transmit descriptor address of TX channel 0 + */ +typedef union { + struct { + /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; + * Represents the address of the previous transmit descriptor y-1 that has already + * been fetched. + */ + uint32_t outlink_dscr_bf1_chn:32; + }; + uint32_t val; +} ahb_dma_out_dscr_bf1_chn_reg_t; + +/** Type of out_peri_chn register + * Priority register of TX channel 0 + */ +typedef union { + struct { + /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0; + * Configures the priority of TX channel 0.The larger of the value, the higher of the + * priority.. + */ + uint32_t tx_pri_chn:4; uint32_t reserved_4:28; }; uint32_t val; -} ahb_dma_tx_ch_arb_weigh_chn_reg_t; +} ahb_dma_out_peri_chn_reg_t; -/** Type of tx_arb_weigh_opt_dir_chn register - * TX channel n weight arbitration optimization enable register +/** Type of out_peri_sel_chn register + * Peripheral selection register of TX channel 0 */ typedef union { struct { - /** tx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight optimization for TX channel n. - * 0: Disable - * 1: Enable + /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63; + * Configures the peripheral connected to TX channel 0. + * 0: Dummy + * 1: SPI2 + * 2: Dummy + * 3: I2S0 + * 4 ~ 6: Dummy + * 7: SHA + * 8: ADC_DAC + * 9~15: Dummy */ - uint32_t tx_arb_weigh_opt_dir_chn:1; - uint32_t reserved_1:31; + uint32_t peri_out_sel_chn:6; + uint32_t reserved_6:26; }; uint32_t val; -} ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t; +} ahb_dma_out_peri_sel_chn_reg_t; -/** Type of rx_ch_arb_weigh_chn register - * RX channel n arbitration weight configuration register +/** Type of out_done_des_addr_ch0 register + * TX done outlink descriptor address of TX channel 0 */ typedef union { struct { - /** rx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0; - * Configures the weight (i.e the number of tokens) of RX channeln. - * Value range: 0 ~ 15. + /** out_done_des_addr_ch0 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the outlink descriptor when this descriptor is completed. */ - uint32_t rx_ch_arb_weigh_chn:4; + uint32_t out_done_des_addr_ch0:32; + }; + uint32_t val; +} ahb_dma_out_done_des_addr_ch0_reg_t; + +/** Type of in_done_des_addr_ch1 register + * RX_done Inlink descriptor address of RX channel 1 + */ +typedef union { + struct { + /** in_done_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the inlink descriptor when this descriptor is completed . + */ + uint32_t in_done_des_addr_ch1:32; + }; + uint32_t val; +} ahb_dma_in_done_des_addr_ch1_reg_t; + +/** Type of out_done_des_addr_ch1 register + * TX done outlink descriptor address of TX channel 1 + */ +typedef union { + struct { + /** out_done_des_addr_ch1 : RO; bitpos: [31:0]; default: 0; + * Represents the address of the outlink descriptor when this descriptor is completed. + */ + uint32_t out_done_des_addr_ch1:32; + }; + uint32_t val; +} ahb_dma_out_done_des_addr_ch1_reg_t; + +/** Type of tx_ch_arb_weight_ch0 register + * TX channel 0 arbitration weight configuration register + */ +typedef union { + struct { + /** tx_arb_weight_value_ch0 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of TX channel0 + */ + uint32_t tx_arb_weight_value_ch0:4; uint32_t reserved_4:28; }; uint32_t val; -} ahb_dma_rx_ch_arb_weigh_chn_reg_t; +} ahb_dma_tx_ch_arb_weight_ch0_reg_t; -/** Type of rx_arb_weigh_opt_dir_chn register - * RX channel n weight arbitration optimization enable register +/** Type of tx_arb_weight_opt_dir_ch0 register + * TX channel 0 weight arbitration optimization enable register */ typedef union { struct { - /** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0; - * Configures whether to enable weight optimization for RX channel n. - * 0: Disable - * 1: Enable + /** tx_arb_weight_opt_dis_ch0 : R/W; bitpos: [0]; default: 0; + * reserved */ - uint32_t rx_arb_weigh_opt_dir_chn:1; + uint32_t tx_arb_weight_opt_dis_ch0:1; uint32_t reserved_1:31; }; uint32_t val; -} ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t; +} ahb_dma_tx_arb_weight_opt_dir_ch0_reg_t; + +/** Type of tx_ch_arb_weight_ch1 register + * TX channel 1 arbitration weight configuration register + */ +typedef union { + struct { + /** tx_arb_weight_value_ch1 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of TX channel1 + */ + uint32_t tx_arb_weight_value_ch1:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_tx_ch_arb_weight_ch1_reg_t; + +/** Type of tx_arb_weight_opt_dir_ch1 register + * TX channel 1 weight arbitration optimization enable register + */ +typedef union { + struct { + /** tx_arb_weight_opt_dis_ch1 : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t tx_arb_weight_opt_dis_ch1:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ahb_dma_tx_arb_weight_opt_dir_ch1_reg_t; + +/** Type of rx_ch_arb_weight_ch0 register + * RX channel 0 arbitration weight configuration register + */ +typedef union { + struct { + /** rx_arb_weight_value_ch0 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of RX channel0 + */ + uint32_t rx_arb_weight_value_ch0:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_rx_ch_arb_weight_ch0_reg_t; + +/** Type of rx_arb_weight_opt_dir_ch0 register + * RX channel 0 weight arbitration optimization enable register + */ +typedef union { + struct { + /** rx_arb_weight_opt_dis_ch0 : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t rx_arb_weight_opt_dis_ch0:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ahb_dma_rx_arb_weight_opt_dir_ch0_reg_t; + +/** Type of rx_ch_arb_weight_ch1 register + * RX channel 1 arbitration weight configuration register + */ +typedef union { + struct { + /** rx_arb_weight_value_ch1 : R/W; bitpos: [3:0]; default: 0; + * Configures the weight(i.e the number of tokens) of RX channel1 + */ + uint32_t rx_arb_weight_value_ch1:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} ahb_dma_rx_ch_arb_weight_ch1_reg_t; + +/** Type of rx_arb_weight_opt_dir_ch1 register + * RX channel 1 weight arbitration optimization enable register + */ +typedef union { + struct { + /** rx_arb_weight_opt_dis_ch1 : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t rx_arb_weight_opt_dis_ch1:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ahb_dma_rx_arb_weight_opt_dir_ch1_reg_t; /** Type of in_link_addr_chn register - * Linked list descriptor configuration register of RX channel n + * Link list descriptor address configuration of RX channel 0 */ typedef union { struct { /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0; - * Represents the first receive descriptor's address. + * Configures the 32 bits of the first receive descriptor's address */ uint32_t inlink_addr_chn:32; }; @@ -657,25 +1176,26 @@ typedef union { } ahb_dma_in_link_addr_chn_reg_t; /** Type of out_link_addr_chn register - * Linked list descriptor configuration register of TX channel n + * Link list descriptor address configuration of TX channel 0 */ typedef union { struct { /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0; - * Represents the first transmit descriptor's address. + * Configures the 32 bits of the first receive descriptor's address. */ uint32_t outlink_addr_chn:32; }; uint32_t val; } ahb_dma_out_link_addr_chn_reg_t; + /** Type of intr_mem_start_addr register * Accessible address space start address configuration register */ typedef union { struct { /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 0; - * Configures the start address of accessible address space. + * Accessible address space start address configuration register */ uint32_t access_intr_mem_start_addr:32; }; @@ -695,6 +1215,127 @@ typedef union { uint32_t val; } ahb_dma_intr_mem_end_addr_reg_t; +/** Type of arb_timeout register + * TX arbitration timeout configuration register + */ +typedef union { + struct { + /** arb_timeout_num : R/W; bitpos: [15:0]; default: 0; + * Configures the time slot. Measurement unit: AHB bus clock cycle. + */ + uint32_t arb_timeout_num:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} ahb_dma_arb_timeout_reg_t; + +/** Type of weight_en register + * TX weight arbitration enable register + */ +typedef union { + struct { + /** weight_en : R/W; bitpos: [0]; default: 0; + * Configures whether to enable weight arbitration. + * 0: Disable + * 1: Enable + */ + uint32_t weight_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ahb_dma_weight_en_reg_t; + +/** Type of module_clk_en register + * Module clock force on register + */ +typedef union { + struct { + /** ahb_apb_sync_clk_en : R/W; bitpos: [1:0]; default: 3; + * Configures whether to force on ahb_apb_sync 1~0 module clock. For bit n: + * 0 : Not force on ahb_apb_sync n clock + * 1 : Force on ahb_apb_sync n clock + */ + uint32_t ahb_apb_sync_clk_en:2; + /** out_dscr_clk_en : R/W; bitpos: [3:2]; default: 7; + * Configures whether to force on out_dscr 1~0 module clock. For bit n: + * 0 : Not force on out_dscr n clock + * 1 : Force on out_dscr n clock + */ + uint32_t out_dscr_clk_en:2; + /** out_ctrl_clk_en : R/W; bitpos: [5:4]; default: 7; + * Configures whether to force on out_ctrl 1~0 module clock. For bit n: + * 0 : Not force on out_ctrl n clock + * 1 : Force on out_ctrl n clock + */ + uint32_t out_ctrl_clk_en:2; + /** in_dscr_clk_en : R/W; bitpos: [7:6]; default: 7; + * Configures whether to force on in_dscr 1~0 module clock. For bit n: + * 0 : Not force on in_dscr n clock + * 1 : Force on in_dscr n clock + */ + uint32_t in_dscr_clk_en:2; + /** in_ctrl_clk_en : R/W; bitpos: [9:8]; default: 7; + * Configures whether to force on in_ctrl 1~0 module clock. For bit n: + * 0 : Not force on in_ctrl n clock + * 1 : Force on in_ctrl n clock + */ + uint32_t in_ctrl_clk_en:2; + uint32_t reserved_10:17; + /** cmd_arb_clk_en : R/W; bitpos: [27]; default: 0; + * Configures whether to force on cmd_arb module clock. + * 0 : Not force on cmd_arb clock + * 1 : Force on cmd_arb clock + */ + uint32_t cmd_arb_clk_en:1; + /** ahbinf_clk_en : R/W; bitpos: [28]; default: 0; + * Configures whether to force on ahbinf module clock. + * 0 : Not force on ahbinf clock + * 1 : Force on ahbinf clock + */ + uint32_t ahbinf_clk_en:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} ahb_dma_module_clk_en_reg_t; + +/** Type of ahbinf_resp_err_status0 register + * AHB response error status 0 register + */ +typedef union { + struct { + /** ahbinf_resp_err_addr : RO; bitpos: [31:0]; default: 0; + * Represents the address of the AHB response error. + */ + uint32_t ahbinf_resp_err_addr:32; + }; + uint32_t val; +} ahb_dma_ahbinf_resp_err_status0_reg_t; + +/** Type of ahbinf_resp_err_status1 register + * AHB response error status 1 register + */ +typedef union { + struct { + /** ahbinf_resp_err_wr : RO; bitpos: [0]; default: 0; + * Represents the AHB response error is write request. + */ + uint32_t ahbinf_resp_err_wr:1; + /** ahbinf_resp_err_id : RO; bitpos: [4:1]; default: 15; + * Represents the AHB response error request id. + */ + uint32_t ahbinf_resp_err_id:4; + /** ahbinf_resp_err_ch_id : RO; bitpos: [6:5]; default: 0; + * Represents the AHB response error request channel id.bit[1]=1:TX channel. + * bit[1]=0:RX channel. + */ + uint32_t ahbinf_resp_err_ch_id:2; + uint32_t reserved_7:25; + }; + uint32_t val; +} ahb_dma_ahbinf_resp_err_status1_reg_t; + + +/** Group: Configuration Registers */ /** Type of arb_timeout_tx register * TX arbitration timeout configuration register */ @@ -755,411 +1396,6 @@ typedef union { uint32_t val; } ahb_dma_weight_en_rx_reg_t; - -/** Group: Version Registers */ -/** Type of date register - * Version control register - */ -typedef union { - struct { - /** date : R/W; bitpos: [31:0]; default: 36770448; - * Version control register. - */ - uint32_t date:32; - }; - uint32_t val; -} ahb_dma_date_reg_t; - - -/** Group: Status Registers */ -/** Type of infifo_status_chn register - * RX channel n FIFO status - */ -typedef union { - struct { - /** infifo_full_chn : RO; bitpos: [0]; default: 1; - * Represents whether L1 RX FIFO is full. - * 0: Not Full - * 1: Full - */ - uint32_t infifo_full_chn:1; - /** infifo_empty_chn : RO; bitpos: [1]; default: 1; - * Represents whether L1 RX FIFO is empty. - * 0: Not empty - * 1: Empty - */ - uint32_t infifo_empty_chn:1; - uint32_t reserved_2:6; - /** infifo_cnt_chn : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 RX FIFO for RX channel n. - */ - uint32_t infifo_cnt_chn:7; - uint32_t reserved_15:8; - /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1; - * Reserved. - */ - uint32_t in_remain_under_1b_chn:1; - /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1; - * Reserved. - */ - uint32_t in_remain_under_2b_chn:1; - /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1; - * Reserved. - */ - uint32_t in_remain_under_3b_chn:1; - /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1; - * Reserved. - */ - uint32_t in_remain_under_4b_chn:1; - /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0; - * Reserved. - */ - uint32_t in_buf_hungry_chn:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} ahb_dma_infifo_status_chn_reg_t; - -/** Type of in_state_chn register - * RX channel n status - */ -typedef union { - struct { - /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the next receive descriptor address that is - * pre-read (but not processed yet). If the current receive descriptor is the last - * descriptor, then this field represents the address of the current receive - * descriptor. - */ - uint32_t inlink_dscr_addr_chn:18; - /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0; - * Reserved. - */ - uint32_t in_dscr_state_chn:2; - /** in_state_chn : RO; bitpos: [22:20]; default: 0; - * Reserved. - */ - uint32_t in_state_chn:3; - uint32_t reserved_23:9; - }; - uint32_t val; -} ahb_dma_in_state_chn_reg_t; - -/** Type of in_suc_eof_des_addr_chn register - * Receive descriptor address when EOF occurs on RX channel n - */ -typedef union { - struct { - /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t in_suc_eof_des_addr_chn:32; - }; - uint32_t val; -} ahb_dma_in_suc_eof_des_addr_chn_reg_t; - -/** Type of in_err_eof_des_addr_chn register - * Receive descriptor address when errors occur of RX channel n - */ -typedef union { - struct { - /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * Represents the address of the receive descriptor when there are some errors in the - * currently received data. - */ - uint32_t in_err_eof_des_addr_chn:32; - }; - uint32_t val; -} ahb_dma_in_err_eof_des_addr_chn_reg_t; - -/** Type of in_dscr_chn register - * Address of the next receive descriptor pointed by the current pre-read receive - * descriptor on RX channel n - */ -typedef union { - struct { - /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next receive descriptor x+1 pointed by the current - * receive descriptor that is pre-read. - */ - uint32_t inlink_dscr_chn:32; - }; - uint32_t val; -} ahb_dma_in_dscr_chn_reg_t; - -/** Type of in_dscr_bf0_chn register - * Address of the current pre-read receive descriptor on RX channel n - */ -typedef union { - struct { - /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current receive descriptor x that is pre-read. - */ - uint32_t inlink_dscr_bf0_chn:32; - }; - uint32_t val; -} ahb_dma_in_dscr_bf0_chn_reg_t; - -/** Type of in_dscr_bf1_chn register - * Address of the previous pre-read receive descriptor on RX channel n - */ -typedef union { - struct { - /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous receive descriptor x-1 that is pre-read. - */ - uint32_t inlink_dscr_bf1_chn:32; - }; - uint32_t val; -} ahb_dma_in_dscr_bf1_chn_reg_t; - -/** Type of in_done_des_addr_chn register - * Address of the completed inlink descriptor on RX channel n - */ -typedef union { - struct { - /** in_done_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * Represents the address of the inlink descriptor when this descriptor is completed. - */ - uint32_t in_done_des_addr_chn:32; - }; - uint32_t val; -} ahb_dma_in_done_des_addr_chn_reg_t; - -/** Type of outfifo_status_chn register - * TX channel n FIFO status - */ -typedef union { - struct { - /** outfifo_full_chn : RO; bitpos: [0]; default: 0; - * Represents whether L1 TX FIFO is full. - * 0: Not Full - * 1: Full - */ - uint32_t outfifo_full_chn:1; - /** outfifo_empty_chn : RO; bitpos: [1]; default: 1; - * Represents whether L1 TX FIFO is empty. - * 0: Not empty - * 1: Empty - */ - uint32_t outfifo_empty_chn:1; - uint32_t reserved_2:6; - /** outfifo_cnt_chn : RO; bitpos: [14:8]; default: 0; - * Represents the number of data bytes in L1 TX FIFO for TX channel n. - */ - uint32_t outfifo_cnt_chn:7; - uint32_t reserved_15:8; - /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1; - * Reserved. - */ - uint32_t out_remain_under_1b_chn:1; - /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1; - * Reserved. - */ - uint32_t out_remain_under_2b_chn:1; - /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1; - * Reserved. - */ - uint32_t out_remain_under_3b_chn:1; - /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1; - * Reserved. - */ - uint32_t out_remain_under_4b_chn:1; - uint32_t reserved_27:5; - }; - uint32_t val; -} ahb_dma_outfifo_status_chn_reg_t; - -/** Type of out_state_chn register - * TX channel n status - */ -typedef union { - struct { - /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0; - * Represents the lower 18 bits of the next transmit descriptor address that is - * pre-read (but not processed yet). If the current transmit descriptor is the last - * descriptor, then this field represents the address of the current transmit - * descriptor. - */ - uint32_t outlink_dscr_addr_chn:18; - /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0; - * Reserved. - */ - uint32_t out_dscr_state_chn:2; - /** out_state_chn : RO; bitpos: [22:20]; default: 0; - * Reserved. - */ - uint32_t out_state_chn:3; - uint32_t reserved_23:9; - }; - uint32_t val; -} ahb_dma_out_state_chn_reg_t; - -/** Type of out_eof_des_addr_chn register - * Transmit descriptor address when EOF occurs on TX channel n - */ -typedef union { - struct { - /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor when the EOF bit in this - * descriptor is 1. - */ - uint32_t out_eof_des_addr_chn:32; - }; - uint32_t val; -} ahb_dma_out_eof_des_addr_chn_reg_t; - -/** Type of out_eof_bfr_des_addr_chn register - * The last transmit descriptor address when EOF occurs on TX channel n - */ -typedef union { - struct { - /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * Represents the address of the transmit descriptor before the last transmit - * descriptor. - */ - uint32_t out_eof_bfr_des_addr_chn:32; - }; - uint32_t val; -} ahb_dma_out_eof_bfr_des_addr_chn_reg_t; - -/** Type of out_dscr_chn register - * Address of the next transmit descriptor pointed by the current pre-read transmit - * descriptor on TX channel n - */ -typedef union { - struct { - /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0; - * Represents the address of the next transmit descriptor y+1 pointed by the current - * transmit descriptor that is pre-read. - */ - uint32_t outlink_dscr_chn:32; - }; - uint32_t val; -} ahb_dma_out_dscr_chn_reg_t; - -/** Type of out_dscr_bf0_chn register - * Address of the current pre-read transmit descriptor on TX channel n - */ -typedef union { - struct { - /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0; - * Represents the address of the current transmit descriptor y that is pre-read. - */ - uint32_t outlink_dscr_bf0_chn:32; - }; - uint32_t val; -} ahb_dma_out_dscr_bf0_chn_reg_t; - -/** Type of out_dscr_bf1_chn register - * Address of the previous pre-read transmit descriptor on TX channel n - */ -typedef union { - struct { - /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0; - * Represents the address of the previous transmit descriptor y-1 that is pre-read. - */ - uint32_t outlink_dscr_bf1_chn:32; - }; - uint32_t val; -} ahb_dma_out_dscr_bf1_chn_reg_t; - -/** Type of out_done_des_addr_chn register - * Address of the completed outlink descriptor on TX channel n - */ -typedef union { - struct { - /** out_done_des_addr_chn : RO; bitpos: [31:0]; default: 0; - * Represents the address of the outlink descriptor when this descriptor is completed. - */ - uint32_t out_done_des_addr_chn:32; - }; - uint32_t val; -} ahb_dma_out_done_des_addr_chn_reg_t; - - -/** Group: Priority Registers */ -/** Type of in_pri_chn register - * Priority register of RX channel n - */ -typedef union { - struct { - /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of RX channel n. The larger the value, the higher the - * priority. - * Value range: 0 ~ 5 - */ - uint32_t rx_pri_chn:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_in_pri_chn_reg_t; - -/** Type of out_pri_chn register - * Priority register of TX channel n - */ -typedef union { - struct { - /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0; - * Configures the priority of TX channel n. The larger the value, the higher the - * priority. - * Value range: 0 ~ 5 - */ - uint32_t tx_pri_chn:4; - uint32_t reserved_4:28; - }; - uint32_t val; -} ahb_dma_out_pri_chn_reg_t; - - -/** Group: Peripheral Selection Registers */ -/** Type of in_peri_sel_chn register - * Peripheral selection register of RX channel n - */ -typedef union { - struct { - /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to RX channel n. - * 0: Dummy - * 1: GP-SPI - * 2: Dummy - * 3: I2S - * 4 ~ 6: Dummy - * 7: SHA - * 8: ADC - * 9 ~ 15: Dummy - * 16 ~ 63: Invalid - */ - uint32_t peri_in_sel_chn:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} ahb_dma_in_peri_sel_chn_reg_t; - -/** Type of out_peri_sel_chn register - * Peripheral selection register of TX channel n - */ -typedef union { - struct { - /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63; - * Configures the peripheral connected to TX channel n. - * 0: Dummy - * 1: GP-SPI - * 2: Dummy - * 3: I2S - * 4 ~ 6: Dummy - * 7: SHA - * 8: ADC - * 9 ~ 15: Dummy - * 16 ~ 63: Invalid - */ - uint32_t peri_out_sel_chn:6; - uint32_t reserved_6:26; - }; - uint32_t val; -} ahb_dma_out_peri_sel_chn_reg_t; - typedef struct { volatile ahb_dma_in_int_raw_chn_reg_t raw; volatile ahb_dma_in_int_st_chn_reg_t st; @@ -1174,7 +1410,6 @@ typedef struct { volatile ahb_dma_out_int_clr_chn_reg_t clr; } ahb_dma_out_int_chn_reg_t; - typedef struct { volatile ahb_dma_in_conf0_chn_reg_t in_conf0; volatile ahb_dma_in_conf1_chn_reg_t in_conf1; @@ -1187,8 +1422,10 @@ typedef struct { volatile ahb_dma_in_dscr_chn_reg_t in_dscr; volatile ahb_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0; volatile ahb_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1; - volatile ahb_dma_in_pri_chn_reg_t in_pri; + volatile ahb_dma_in_peri_chn_reg_t in_pri; volatile ahb_dma_in_peri_sel_chn_reg_t in_peri_sel; + uint32_t reserved_0a4[3]; + volatile ahb_dma_in_done_des_addr_ch0_reg_t in_done_des_addr_ch0; } ahb_dma_in_chn_reg_t; typedef struct { @@ -1203,46 +1440,41 @@ typedef struct { volatile ahb_dma_out_dscr_chn_reg_t out_dscr; volatile ahb_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0; volatile ahb_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1; - volatile ahb_dma_out_pri_chn_reg_t out_pri; + volatile ahb_dma_out_peri_chn_reg_t out_pri; volatile ahb_dma_out_peri_sel_chn_reg_t out_peri_sel; + uint32_t reserved_104[3]; + volatile ahb_dma_out_done_des_addr_ch0_reg_t out_done_des_addr_ch0; } ahb_dma_out_chn_reg_t; typedef struct { volatile ahb_dma_in_chn_reg_t in; - uint32_t reserved_0a4[3]; - volatile ahb_dma_in_done_des_addr_chn_reg_t in_done_des_addr_ch0; - uint32_t reserved_0b4[7]; + uint32_t reserved_in[7]; volatile ahb_dma_out_chn_reg_t out; - uint32_t reserved_104[3]; - volatile ahb_dma_out_done_des_addr_chn_reg_t out_done_des_addr_ch0; - uint32_t reserved_114[7]; + uint32_t reserved_out[7]; } ahb_dma_chn_reg_t; -typedef struct { - uint32_t reserved[8]; - ahb_dma_tx_ch_arb_weigh_chn_reg_t ch_arb_weigh; - ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt; -} ahb_dma_out_crc_arb_chn_reg_t; - -typedef struct { - uint32_t reserved[8]; - ahb_dma_rx_ch_arb_weigh_chn_reg_t ch_arb_weigh; - ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt; -} ahb_dma_in_crc_arb_chn_reg_t; - typedef struct { volatile ahb_dma_in_int_chn_reg_t in_intr[2]; uint32_t reserved_020[4]; volatile ahb_dma_out_int_chn_reg_t out_intr[2]; - uint32_t reserved_050[5]; + uint32_t reserved_050[4]; + volatile ahb_dma_ahb_test_reg_t ahb_test; volatile ahb_dma_misc_conf_reg_t misc_conf; volatile ahb_dma_date_reg_t date; uint32_t reserved_06c; volatile ahb_dma_chn_reg_t channel[2]; - uint32_t reserved_1d4[51]; - volatile ahb_dma_out_crc_arb_chn_reg_t out_crc_arb[2]; - uint32_t reserved_30c[10]; - volatile ahb_dma_in_crc_arb_chn_reg_t in_crc_arb[2]; + uint32_t reserved_1db[59]; + volatile ahb_dma_tx_ch_arb_weight_ch0_reg_t tx_ch_arb_weight_ch0; + volatile ahb_dma_tx_arb_weight_opt_dir_ch0_reg_t tx_arb_weight_opt_dir_ch0; + uint32_t reserved_2e4[8]; + volatile ahb_dma_tx_ch_arb_weight_ch1_reg_t tx_ch_arb_weight_ch1; + volatile ahb_dma_tx_arb_weight_opt_dir_ch1_reg_t tx_arb_weight_opt_dir_ch1; + uint32_t reserved_30c[18]; + volatile ahb_dma_rx_ch_arb_weight_ch0_reg_t rx_ch_arb_weight_ch0; + volatile ahb_dma_rx_arb_weight_opt_dir_ch0_reg_t rx_arb_weight_opt_dir_ch0; + uint32_t reserved_35c[8]; + volatile ahb_dma_rx_ch_arb_weight_ch1_reg_t rx_ch_arb_weight_ch1; + volatile ahb_dma_rx_arb_weight_opt_dir_ch1_reg_t rx_arb_weight_opt_dir_ch1; uint32_t reserved_384[10]; volatile ahb_dma_in_link_addr_chn_reg_t in_link_addr[2]; uint32_t reserved_3b4; @@ -1254,12 +1486,18 @@ typedef struct { volatile ahb_dma_arb_timeout_rx_reg_t arb_timeout_rx; volatile ahb_dma_weight_en_tx_reg_t weight_en_tx; volatile ahb_dma_weight_en_rx_reg_t weight_en_rx; + volatile ahb_dma_arb_timeout_reg_t arb_timeout; + uint32_t reserved_3e0[8]; + volatile ahb_dma_weight_en_reg_t weight_en; + volatile ahb_dma_module_clk_en_reg_t module_clk_en; + volatile ahb_dma_ahbinf_resp_err_status0_reg_t ahbinf_resp_err_status0; + volatile ahb_dma_ahbinf_resp_err_status1_reg_t ahbinf_resp_err_status1; } ahb_dma_dev_t; extern ahb_dma_dev_t AHB_DMA; #ifndef __cplusplus -_Static_assert(sizeof(ahb_dma_dev_t) == 0x3dc, "Invalid size of ahb_dma_dev_t structure"); +_Static_assert(sizeof(ahb_dma_dev_t) == 0x410, "Invalid size of ahb_dma_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32c61/register/soc/cpu_apm_reg.h b/components/soc/esp32c61/register/soc/cpu_apm_reg.h new file mode 100644 index 0000000000..10ca7c64e3 --- /dev/null +++ b/components/soc/esp32c61/register/soc/cpu_apm_reg.h @@ -0,0 +1,1242 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** CPU_APM_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define CPU_APM_REGION_FILTER_EN_REG (DR_REG_CPU_BASE + 0x0) +/** CPU_APM_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1; + * Configure bit $n (0-7) to enable region $n. + * 0: disable + * 1: enable + */ +#define CPU_APM_REGION_FILTER_EN 0x000000FFU +#define CPU_APM_REGION_FILTER_EN_M (CPU_APM_REGION_FILTER_EN_V << CPU_APM_REGION_FILTER_EN_S) +#define CPU_APM_REGION_FILTER_EN_V 0x000000FFU +#define CPU_APM_REGION_FILTER_EN_S 0 + +/** CPU_APM_REGION0_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION0_ADDR_START_REG (DR_REG_CPU_BASE + 0x4) +/** CPU_APM_REGION0_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 0. + */ +#define CPU_APM_REGION0_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION0_ADDR_START_L_M (CPU_APM_REGION0_ADDR_START_L_V << CPU_APM_REGION0_ADDR_START_L_S) +#define CPU_APM_REGION0_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION0_ADDR_START_L_S 0 +/** CPU_APM_REGION0_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 0. + */ +#define CPU_APM_REGION0_ADDR_START 0x0000007FU +#define CPU_APM_REGION0_ADDR_START_M (CPU_APM_REGION0_ADDR_START_V << CPU_APM_REGION0_ADDR_START_S) +#define CPU_APM_REGION0_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION0_ADDR_START_S 12 +/** CPU_APM_REGION0_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 0. + */ +#define CPU_APM_REGION0_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION0_ADDR_START_H_M (CPU_APM_REGION0_ADDR_START_H_V << CPU_APM_REGION0_ADDR_START_H_S) +#define CPU_APM_REGION0_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION0_ADDR_START_H_S 19 + +/** CPU_APM_REGION0_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION0_ADDR_END_REG (DR_REG_CPU_BASE + 0x8) +/** CPU_APM_REGION0_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 0. + */ +#define CPU_APM_REGION0_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION0_ADDR_END_L_M (CPU_APM_REGION0_ADDR_END_L_V << CPU_APM_REGION0_ADDR_END_L_S) +#define CPU_APM_REGION0_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION0_ADDR_END_L_S 0 +/** CPU_APM_REGION0_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 0. + */ +#define CPU_APM_REGION0_ADDR_END 0x0000007FU +#define CPU_APM_REGION0_ADDR_END_M (CPU_APM_REGION0_ADDR_END_V << CPU_APM_REGION0_ADDR_END_S) +#define CPU_APM_REGION0_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION0_ADDR_END_S 12 +/** CPU_APM_REGION0_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 0. + */ +#define CPU_APM_REGION0_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION0_ADDR_END_H_M (CPU_APM_REGION0_ADDR_END_H_V << CPU_APM_REGION0_ADDR_END_H_S) +#define CPU_APM_REGION0_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION0_ADDR_END_H_S 19 + +/** CPU_APM_REGION0_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION0_ATTR_REG (DR_REG_CPU_BASE + 0xc) +/** CPU_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 0. + */ +#define CPU_APM_REGION0_R0_X (BIT(0)) +#define CPU_APM_REGION0_R0_X_M (CPU_APM_REGION0_R0_X_V << CPU_APM_REGION0_R0_X_S) +#define CPU_APM_REGION0_R0_X_V 0x00000001U +#define CPU_APM_REGION0_R0_X_S 0 +/** CPU_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 0. + */ +#define CPU_APM_REGION0_R0_W (BIT(1)) +#define CPU_APM_REGION0_R0_W_M (CPU_APM_REGION0_R0_W_V << CPU_APM_REGION0_R0_W_S) +#define CPU_APM_REGION0_R0_W_V 0x00000001U +#define CPU_APM_REGION0_R0_W_S 1 +/** CPU_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 0. + */ +#define CPU_APM_REGION0_R0_R (BIT(2)) +#define CPU_APM_REGION0_R0_R_M (CPU_APM_REGION0_R0_R_V << CPU_APM_REGION0_R0_R_S) +#define CPU_APM_REGION0_R0_R_V 0x00000001U +#define CPU_APM_REGION0_R0_R_S 2 +/** CPU_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 0. + */ +#define CPU_APM_REGION0_R1_X (BIT(4)) +#define CPU_APM_REGION0_R1_X_M (CPU_APM_REGION0_R1_X_V << CPU_APM_REGION0_R1_X_S) +#define CPU_APM_REGION0_R1_X_V 0x00000001U +#define CPU_APM_REGION0_R1_X_S 4 +/** CPU_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 0. + */ +#define CPU_APM_REGION0_R1_W (BIT(5)) +#define CPU_APM_REGION0_R1_W_M (CPU_APM_REGION0_R1_W_V << CPU_APM_REGION0_R1_W_S) +#define CPU_APM_REGION0_R1_W_V 0x00000001U +#define CPU_APM_REGION0_R1_W_S 5 +/** CPU_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 0. + */ +#define CPU_APM_REGION0_R1_R (BIT(6)) +#define CPU_APM_REGION0_R1_R_M (CPU_APM_REGION0_R1_R_V << CPU_APM_REGION0_R1_R_S) +#define CPU_APM_REGION0_R1_R_V 0x00000001U +#define CPU_APM_REGION0_R1_R_S 6 +/** CPU_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 0. + */ +#define CPU_APM_REGION0_R2_X (BIT(8)) +#define CPU_APM_REGION0_R2_X_M (CPU_APM_REGION0_R2_X_V << CPU_APM_REGION0_R2_X_S) +#define CPU_APM_REGION0_R2_X_V 0x00000001U +#define CPU_APM_REGION0_R2_X_S 8 +/** CPU_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 0. + */ +#define CPU_APM_REGION0_R2_W (BIT(9)) +#define CPU_APM_REGION0_R2_W_M (CPU_APM_REGION0_R2_W_V << CPU_APM_REGION0_R2_W_S) +#define CPU_APM_REGION0_R2_W_V 0x00000001U +#define CPU_APM_REGION0_R2_W_S 9 +/** CPU_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 0. + */ +#define CPU_APM_REGION0_R2_R (BIT(10)) +#define CPU_APM_REGION0_R2_R_M (CPU_APM_REGION0_R2_R_V << CPU_APM_REGION0_R2_R_S) +#define CPU_APM_REGION0_R2_R_V 0x00000001U +#define CPU_APM_REGION0_R2_R_S 10 +/** CPU_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION0_LOCK (BIT(11)) +#define CPU_APM_REGION0_LOCK_M (CPU_APM_REGION0_LOCK_V << CPU_APM_REGION0_LOCK_S) +#define CPU_APM_REGION0_LOCK_V 0x00000001U +#define CPU_APM_REGION0_LOCK_S 11 + +/** CPU_APM_REGION1_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION1_ADDR_START_REG (DR_REG_CPU_BASE + 0x10) +/** CPU_APM_REGION1_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 1. + */ +#define CPU_APM_REGION1_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION1_ADDR_START_L_M (CPU_APM_REGION1_ADDR_START_L_V << CPU_APM_REGION1_ADDR_START_L_S) +#define CPU_APM_REGION1_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION1_ADDR_START_L_S 0 +/** CPU_APM_REGION1_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 1. + */ +#define CPU_APM_REGION1_ADDR_START 0x0000007FU +#define CPU_APM_REGION1_ADDR_START_M (CPU_APM_REGION1_ADDR_START_V << CPU_APM_REGION1_ADDR_START_S) +#define CPU_APM_REGION1_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION1_ADDR_START_S 12 +/** CPU_APM_REGION1_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 1. + */ +#define CPU_APM_REGION1_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION1_ADDR_START_H_M (CPU_APM_REGION1_ADDR_START_H_V << CPU_APM_REGION1_ADDR_START_H_S) +#define CPU_APM_REGION1_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION1_ADDR_START_H_S 19 + +/** CPU_APM_REGION1_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION1_ADDR_END_REG (DR_REG_CPU_BASE + 0x14) +/** CPU_APM_REGION1_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 1. + */ +#define CPU_APM_REGION1_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION1_ADDR_END_L_M (CPU_APM_REGION1_ADDR_END_L_V << CPU_APM_REGION1_ADDR_END_L_S) +#define CPU_APM_REGION1_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION1_ADDR_END_L_S 0 +/** CPU_APM_REGION1_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 1. + */ +#define CPU_APM_REGION1_ADDR_END 0x0000007FU +#define CPU_APM_REGION1_ADDR_END_M (CPU_APM_REGION1_ADDR_END_V << CPU_APM_REGION1_ADDR_END_S) +#define CPU_APM_REGION1_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION1_ADDR_END_S 12 +/** CPU_APM_REGION1_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 1. + */ +#define CPU_APM_REGION1_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION1_ADDR_END_H_M (CPU_APM_REGION1_ADDR_END_H_V << CPU_APM_REGION1_ADDR_END_H_S) +#define CPU_APM_REGION1_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION1_ADDR_END_H_S 19 + +/** CPU_APM_REGION1_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION1_ATTR_REG (DR_REG_CPU_BASE + 0x18) +/** CPU_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 1. + */ +#define CPU_APM_REGION1_R0_X (BIT(0)) +#define CPU_APM_REGION1_R0_X_M (CPU_APM_REGION1_R0_X_V << CPU_APM_REGION1_R0_X_S) +#define CPU_APM_REGION1_R0_X_V 0x00000001U +#define CPU_APM_REGION1_R0_X_S 0 +/** CPU_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 1. + */ +#define CPU_APM_REGION1_R0_W (BIT(1)) +#define CPU_APM_REGION1_R0_W_M (CPU_APM_REGION1_R0_W_V << CPU_APM_REGION1_R0_W_S) +#define CPU_APM_REGION1_R0_W_V 0x00000001U +#define CPU_APM_REGION1_R0_W_S 1 +/** CPU_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 1. + */ +#define CPU_APM_REGION1_R0_R (BIT(2)) +#define CPU_APM_REGION1_R0_R_M (CPU_APM_REGION1_R0_R_V << CPU_APM_REGION1_R0_R_S) +#define CPU_APM_REGION1_R0_R_V 0x00000001U +#define CPU_APM_REGION1_R0_R_S 2 +/** CPU_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 1. + */ +#define CPU_APM_REGION1_R1_X (BIT(4)) +#define CPU_APM_REGION1_R1_X_M (CPU_APM_REGION1_R1_X_V << CPU_APM_REGION1_R1_X_S) +#define CPU_APM_REGION1_R1_X_V 0x00000001U +#define CPU_APM_REGION1_R1_X_S 4 +/** CPU_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 1. + */ +#define CPU_APM_REGION1_R1_W (BIT(5)) +#define CPU_APM_REGION1_R1_W_M (CPU_APM_REGION1_R1_W_V << CPU_APM_REGION1_R1_W_S) +#define CPU_APM_REGION1_R1_W_V 0x00000001U +#define CPU_APM_REGION1_R1_W_S 5 +/** CPU_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 1. + */ +#define CPU_APM_REGION1_R1_R (BIT(6)) +#define CPU_APM_REGION1_R1_R_M (CPU_APM_REGION1_R1_R_V << CPU_APM_REGION1_R1_R_S) +#define CPU_APM_REGION1_R1_R_V 0x00000001U +#define CPU_APM_REGION1_R1_R_S 6 +/** CPU_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 1. + */ +#define CPU_APM_REGION1_R2_X (BIT(8)) +#define CPU_APM_REGION1_R2_X_M (CPU_APM_REGION1_R2_X_V << CPU_APM_REGION1_R2_X_S) +#define CPU_APM_REGION1_R2_X_V 0x00000001U +#define CPU_APM_REGION1_R2_X_S 8 +/** CPU_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 1. + */ +#define CPU_APM_REGION1_R2_W (BIT(9)) +#define CPU_APM_REGION1_R2_W_M (CPU_APM_REGION1_R2_W_V << CPU_APM_REGION1_R2_W_S) +#define CPU_APM_REGION1_R2_W_V 0x00000001U +#define CPU_APM_REGION1_R2_W_S 9 +/** CPU_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 1. + */ +#define CPU_APM_REGION1_R2_R (BIT(10)) +#define CPU_APM_REGION1_R2_R_M (CPU_APM_REGION1_R2_R_V << CPU_APM_REGION1_R2_R_S) +#define CPU_APM_REGION1_R2_R_V 0x00000001U +#define CPU_APM_REGION1_R2_R_S 10 +/** CPU_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION1_LOCK (BIT(11)) +#define CPU_APM_REGION1_LOCK_M (CPU_APM_REGION1_LOCK_V << CPU_APM_REGION1_LOCK_S) +#define CPU_APM_REGION1_LOCK_V 0x00000001U +#define CPU_APM_REGION1_LOCK_S 11 + +/** CPU_APM_REGION2_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION2_ADDR_START_REG (DR_REG_CPU_BASE + 0x1c) +/** CPU_APM_REGION2_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 2. + */ +#define CPU_APM_REGION2_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION2_ADDR_START_L_M (CPU_APM_REGION2_ADDR_START_L_V << CPU_APM_REGION2_ADDR_START_L_S) +#define CPU_APM_REGION2_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION2_ADDR_START_L_S 0 +/** CPU_APM_REGION2_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 2. + */ +#define CPU_APM_REGION2_ADDR_START 0x0000007FU +#define CPU_APM_REGION2_ADDR_START_M (CPU_APM_REGION2_ADDR_START_V << CPU_APM_REGION2_ADDR_START_S) +#define CPU_APM_REGION2_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION2_ADDR_START_S 12 +/** CPU_APM_REGION2_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 2. + */ +#define CPU_APM_REGION2_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION2_ADDR_START_H_M (CPU_APM_REGION2_ADDR_START_H_V << CPU_APM_REGION2_ADDR_START_H_S) +#define CPU_APM_REGION2_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION2_ADDR_START_H_S 19 + +/** CPU_APM_REGION2_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION2_ADDR_END_REG (DR_REG_CPU_BASE + 0x20) +/** CPU_APM_REGION2_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 2. + */ +#define CPU_APM_REGION2_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION2_ADDR_END_L_M (CPU_APM_REGION2_ADDR_END_L_V << CPU_APM_REGION2_ADDR_END_L_S) +#define CPU_APM_REGION2_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION2_ADDR_END_L_S 0 +/** CPU_APM_REGION2_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 2. + */ +#define CPU_APM_REGION2_ADDR_END 0x0000007FU +#define CPU_APM_REGION2_ADDR_END_M (CPU_APM_REGION2_ADDR_END_V << CPU_APM_REGION2_ADDR_END_S) +#define CPU_APM_REGION2_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION2_ADDR_END_S 12 +/** CPU_APM_REGION2_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 2. + */ +#define CPU_APM_REGION2_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION2_ADDR_END_H_M (CPU_APM_REGION2_ADDR_END_H_V << CPU_APM_REGION2_ADDR_END_H_S) +#define CPU_APM_REGION2_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION2_ADDR_END_H_S 19 + +/** CPU_APM_REGION2_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION2_ATTR_REG (DR_REG_CPU_BASE + 0x24) +/** CPU_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 2. + */ +#define CPU_APM_REGION2_R0_X (BIT(0)) +#define CPU_APM_REGION2_R0_X_M (CPU_APM_REGION2_R0_X_V << CPU_APM_REGION2_R0_X_S) +#define CPU_APM_REGION2_R0_X_V 0x00000001U +#define CPU_APM_REGION2_R0_X_S 0 +/** CPU_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 2. + */ +#define CPU_APM_REGION2_R0_W (BIT(1)) +#define CPU_APM_REGION2_R0_W_M (CPU_APM_REGION2_R0_W_V << CPU_APM_REGION2_R0_W_S) +#define CPU_APM_REGION2_R0_W_V 0x00000001U +#define CPU_APM_REGION2_R0_W_S 1 +/** CPU_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 2. + */ +#define CPU_APM_REGION2_R0_R (BIT(2)) +#define CPU_APM_REGION2_R0_R_M (CPU_APM_REGION2_R0_R_V << CPU_APM_REGION2_R0_R_S) +#define CPU_APM_REGION2_R0_R_V 0x00000001U +#define CPU_APM_REGION2_R0_R_S 2 +/** CPU_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 2. + */ +#define CPU_APM_REGION2_R1_X (BIT(4)) +#define CPU_APM_REGION2_R1_X_M (CPU_APM_REGION2_R1_X_V << CPU_APM_REGION2_R1_X_S) +#define CPU_APM_REGION2_R1_X_V 0x00000001U +#define CPU_APM_REGION2_R1_X_S 4 +/** CPU_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 2. + */ +#define CPU_APM_REGION2_R1_W (BIT(5)) +#define CPU_APM_REGION2_R1_W_M (CPU_APM_REGION2_R1_W_V << CPU_APM_REGION2_R1_W_S) +#define CPU_APM_REGION2_R1_W_V 0x00000001U +#define CPU_APM_REGION2_R1_W_S 5 +/** CPU_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 2. + */ +#define CPU_APM_REGION2_R1_R (BIT(6)) +#define CPU_APM_REGION2_R1_R_M (CPU_APM_REGION2_R1_R_V << CPU_APM_REGION2_R1_R_S) +#define CPU_APM_REGION2_R1_R_V 0x00000001U +#define CPU_APM_REGION2_R1_R_S 6 +/** CPU_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 2. + */ +#define CPU_APM_REGION2_R2_X (BIT(8)) +#define CPU_APM_REGION2_R2_X_M (CPU_APM_REGION2_R2_X_V << CPU_APM_REGION2_R2_X_S) +#define CPU_APM_REGION2_R2_X_V 0x00000001U +#define CPU_APM_REGION2_R2_X_S 8 +/** CPU_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 2. + */ +#define CPU_APM_REGION2_R2_W (BIT(9)) +#define CPU_APM_REGION2_R2_W_M (CPU_APM_REGION2_R2_W_V << CPU_APM_REGION2_R2_W_S) +#define CPU_APM_REGION2_R2_W_V 0x00000001U +#define CPU_APM_REGION2_R2_W_S 9 +/** CPU_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 2. + */ +#define CPU_APM_REGION2_R2_R (BIT(10)) +#define CPU_APM_REGION2_R2_R_M (CPU_APM_REGION2_R2_R_V << CPU_APM_REGION2_R2_R_S) +#define CPU_APM_REGION2_R2_R_V 0x00000001U +#define CPU_APM_REGION2_R2_R_S 10 +/** CPU_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION2_LOCK (BIT(11)) +#define CPU_APM_REGION2_LOCK_M (CPU_APM_REGION2_LOCK_V << CPU_APM_REGION2_LOCK_S) +#define CPU_APM_REGION2_LOCK_V 0x00000001U +#define CPU_APM_REGION2_LOCK_S 11 + +/** CPU_APM_REGION3_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION3_ADDR_START_REG (DR_REG_CPU_BASE + 0x28) +/** CPU_APM_REGION3_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 3. + */ +#define CPU_APM_REGION3_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION3_ADDR_START_L_M (CPU_APM_REGION3_ADDR_START_L_V << CPU_APM_REGION3_ADDR_START_L_S) +#define CPU_APM_REGION3_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION3_ADDR_START_L_S 0 +/** CPU_APM_REGION3_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 3. + */ +#define CPU_APM_REGION3_ADDR_START 0x0000007FU +#define CPU_APM_REGION3_ADDR_START_M (CPU_APM_REGION3_ADDR_START_V << CPU_APM_REGION3_ADDR_START_S) +#define CPU_APM_REGION3_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION3_ADDR_START_S 12 +/** CPU_APM_REGION3_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 3. + */ +#define CPU_APM_REGION3_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION3_ADDR_START_H_M (CPU_APM_REGION3_ADDR_START_H_V << CPU_APM_REGION3_ADDR_START_H_S) +#define CPU_APM_REGION3_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION3_ADDR_START_H_S 19 + +/** CPU_APM_REGION3_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION3_ADDR_END_REG (DR_REG_CPU_BASE + 0x2c) +/** CPU_APM_REGION3_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 3. + */ +#define CPU_APM_REGION3_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION3_ADDR_END_L_M (CPU_APM_REGION3_ADDR_END_L_V << CPU_APM_REGION3_ADDR_END_L_S) +#define CPU_APM_REGION3_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION3_ADDR_END_L_S 0 +/** CPU_APM_REGION3_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 3. + */ +#define CPU_APM_REGION3_ADDR_END 0x0000007FU +#define CPU_APM_REGION3_ADDR_END_M (CPU_APM_REGION3_ADDR_END_V << CPU_APM_REGION3_ADDR_END_S) +#define CPU_APM_REGION3_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION3_ADDR_END_S 12 +/** CPU_APM_REGION3_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 3. + */ +#define CPU_APM_REGION3_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION3_ADDR_END_H_M (CPU_APM_REGION3_ADDR_END_H_V << CPU_APM_REGION3_ADDR_END_H_S) +#define CPU_APM_REGION3_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION3_ADDR_END_H_S 19 + +/** CPU_APM_REGION3_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION3_ATTR_REG (DR_REG_CPU_BASE + 0x30) +/** CPU_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 3. + */ +#define CPU_APM_REGION3_R0_X (BIT(0)) +#define CPU_APM_REGION3_R0_X_M (CPU_APM_REGION3_R0_X_V << CPU_APM_REGION3_R0_X_S) +#define CPU_APM_REGION3_R0_X_V 0x00000001U +#define CPU_APM_REGION3_R0_X_S 0 +/** CPU_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 3. + */ +#define CPU_APM_REGION3_R0_W (BIT(1)) +#define CPU_APM_REGION3_R0_W_M (CPU_APM_REGION3_R0_W_V << CPU_APM_REGION3_R0_W_S) +#define CPU_APM_REGION3_R0_W_V 0x00000001U +#define CPU_APM_REGION3_R0_W_S 1 +/** CPU_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 3. + */ +#define CPU_APM_REGION3_R0_R (BIT(2)) +#define CPU_APM_REGION3_R0_R_M (CPU_APM_REGION3_R0_R_V << CPU_APM_REGION3_R0_R_S) +#define CPU_APM_REGION3_R0_R_V 0x00000001U +#define CPU_APM_REGION3_R0_R_S 2 +/** CPU_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 3. + */ +#define CPU_APM_REGION3_R1_X (BIT(4)) +#define CPU_APM_REGION3_R1_X_M (CPU_APM_REGION3_R1_X_V << CPU_APM_REGION3_R1_X_S) +#define CPU_APM_REGION3_R1_X_V 0x00000001U +#define CPU_APM_REGION3_R1_X_S 4 +/** CPU_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 3. + */ +#define CPU_APM_REGION3_R1_W (BIT(5)) +#define CPU_APM_REGION3_R1_W_M (CPU_APM_REGION3_R1_W_V << CPU_APM_REGION3_R1_W_S) +#define CPU_APM_REGION3_R1_W_V 0x00000001U +#define CPU_APM_REGION3_R1_W_S 5 +/** CPU_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 3. + */ +#define CPU_APM_REGION3_R1_R (BIT(6)) +#define CPU_APM_REGION3_R1_R_M (CPU_APM_REGION3_R1_R_V << CPU_APM_REGION3_R1_R_S) +#define CPU_APM_REGION3_R1_R_V 0x00000001U +#define CPU_APM_REGION3_R1_R_S 6 +/** CPU_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 3. + */ +#define CPU_APM_REGION3_R2_X (BIT(8)) +#define CPU_APM_REGION3_R2_X_M (CPU_APM_REGION3_R2_X_V << CPU_APM_REGION3_R2_X_S) +#define CPU_APM_REGION3_R2_X_V 0x00000001U +#define CPU_APM_REGION3_R2_X_S 8 +/** CPU_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 3. + */ +#define CPU_APM_REGION3_R2_W (BIT(9)) +#define CPU_APM_REGION3_R2_W_M (CPU_APM_REGION3_R2_W_V << CPU_APM_REGION3_R2_W_S) +#define CPU_APM_REGION3_R2_W_V 0x00000001U +#define CPU_APM_REGION3_R2_W_S 9 +/** CPU_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 3. + */ +#define CPU_APM_REGION3_R2_R (BIT(10)) +#define CPU_APM_REGION3_R2_R_M (CPU_APM_REGION3_R2_R_V << CPU_APM_REGION3_R2_R_S) +#define CPU_APM_REGION3_R2_R_V 0x00000001U +#define CPU_APM_REGION3_R2_R_S 10 +/** CPU_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION3_LOCK (BIT(11)) +#define CPU_APM_REGION3_LOCK_M (CPU_APM_REGION3_LOCK_V << CPU_APM_REGION3_LOCK_S) +#define CPU_APM_REGION3_LOCK_V 0x00000001U +#define CPU_APM_REGION3_LOCK_S 11 + +/** CPU_APM_REGION4_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION4_ADDR_START_REG (DR_REG_CPU_BASE + 0x34) +/** CPU_APM_REGION4_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 4. + */ +#define CPU_APM_REGION4_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION4_ADDR_START_L_M (CPU_APM_REGION4_ADDR_START_L_V << CPU_APM_REGION4_ADDR_START_L_S) +#define CPU_APM_REGION4_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION4_ADDR_START_L_S 0 +/** CPU_APM_REGION4_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 4. + */ +#define CPU_APM_REGION4_ADDR_START 0x0000007FU +#define CPU_APM_REGION4_ADDR_START_M (CPU_APM_REGION4_ADDR_START_V << CPU_APM_REGION4_ADDR_START_S) +#define CPU_APM_REGION4_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION4_ADDR_START_S 12 +/** CPU_APM_REGION4_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 4. + */ +#define CPU_APM_REGION4_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION4_ADDR_START_H_M (CPU_APM_REGION4_ADDR_START_H_V << CPU_APM_REGION4_ADDR_START_H_S) +#define CPU_APM_REGION4_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION4_ADDR_START_H_S 19 + +/** CPU_APM_REGION4_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION4_ADDR_END_REG (DR_REG_CPU_BASE + 0x38) +/** CPU_APM_REGION4_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 4. + */ +#define CPU_APM_REGION4_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION4_ADDR_END_L_M (CPU_APM_REGION4_ADDR_END_L_V << CPU_APM_REGION4_ADDR_END_L_S) +#define CPU_APM_REGION4_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION4_ADDR_END_L_S 0 +/** CPU_APM_REGION4_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 4. + */ +#define CPU_APM_REGION4_ADDR_END 0x0000007FU +#define CPU_APM_REGION4_ADDR_END_M (CPU_APM_REGION4_ADDR_END_V << CPU_APM_REGION4_ADDR_END_S) +#define CPU_APM_REGION4_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION4_ADDR_END_S 12 +/** CPU_APM_REGION4_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 4. + */ +#define CPU_APM_REGION4_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION4_ADDR_END_H_M (CPU_APM_REGION4_ADDR_END_H_V << CPU_APM_REGION4_ADDR_END_H_S) +#define CPU_APM_REGION4_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION4_ADDR_END_H_S 19 + +/** CPU_APM_REGION4_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION4_ATTR_REG (DR_REG_CPU_BASE + 0x3c) +/** CPU_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 4. + */ +#define CPU_APM_REGION4_R0_X (BIT(0)) +#define CPU_APM_REGION4_R0_X_M (CPU_APM_REGION4_R0_X_V << CPU_APM_REGION4_R0_X_S) +#define CPU_APM_REGION4_R0_X_V 0x00000001U +#define CPU_APM_REGION4_R0_X_S 0 +/** CPU_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 4. + */ +#define CPU_APM_REGION4_R0_W (BIT(1)) +#define CPU_APM_REGION4_R0_W_M (CPU_APM_REGION4_R0_W_V << CPU_APM_REGION4_R0_W_S) +#define CPU_APM_REGION4_R0_W_V 0x00000001U +#define CPU_APM_REGION4_R0_W_S 1 +/** CPU_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 4. + */ +#define CPU_APM_REGION4_R0_R (BIT(2)) +#define CPU_APM_REGION4_R0_R_M (CPU_APM_REGION4_R0_R_V << CPU_APM_REGION4_R0_R_S) +#define CPU_APM_REGION4_R0_R_V 0x00000001U +#define CPU_APM_REGION4_R0_R_S 2 +/** CPU_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 4. + */ +#define CPU_APM_REGION4_R1_X (BIT(4)) +#define CPU_APM_REGION4_R1_X_M (CPU_APM_REGION4_R1_X_V << CPU_APM_REGION4_R1_X_S) +#define CPU_APM_REGION4_R1_X_V 0x00000001U +#define CPU_APM_REGION4_R1_X_S 4 +/** CPU_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 4. + */ +#define CPU_APM_REGION4_R1_W (BIT(5)) +#define CPU_APM_REGION4_R1_W_M (CPU_APM_REGION4_R1_W_V << CPU_APM_REGION4_R1_W_S) +#define CPU_APM_REGION4_R1_W_V 0x00000001U +#define CPU_APM_REGION4_R1_W_S 5 +/** CPU_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 4. + */ +#define CPU_APM_REGION4_R1_R (BIT(6)) +#define CPU_APM_REGION4_R1_R_M (CPU_APM_REGION4_R1_R_V << CPU_APM_REGION4_R1_R_S) +#define CPU_APM_REGION4_R1_R_V 0x00000001U +#define CPU_APM_REGION4_R1_R_S 6 +/** CPU_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 4. + */ +#define CPU_APM_REGION4_R2_X (BIT(8)) +#define CPU_APM_REGION4_R2_X_M (CPU_APM_REGION4_R2_X_V << CPU_APM_REGION4_R2_X_S) +#define CPU_APM_REGION4_R2_X_V 0x00000001U +#define CPU_APM_REGION4_R2_X_S 8 +/** CPU_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 4. + */ +#define CPU_APM_REGION4_R2_W (BIT(9)) +#define CPU_APM_REGION4_R2_W_M (CPU_APM_REGION4_R2_W_V << CPU_APM_REGION4_R2_W_S) +#define CPU_APM_REGION4_R2_W_V 0x00000001U +#define CPU_APM_REGION4_R2_W_S 9 +/** CPU_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 4. + */ +#define CPU_APM_REGION4_R2_R (BIT(10)) +#define CPU_APM_REGION4_R2_R_M (CPU_APM_REGION4_R2_R_V << CPU_APM_REGION4_R2_R_S) +#define CPU_APM_REGION4_R2_R_V 0x00000001U +#define CPU_APM_REGION4_R2_R_S 10 +/** CPU_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION4_LOCK (BIT(11)) +#define CPU_APM_REGION4_LOCK_M (CPU_APM_REGION4_LOCK_V << CPU_APM_REGION4_LOCK_S) +#define CPU_APM_REGION4_LOCK_V 0x00000001U +#define CPU_APM_REGION4_LOCK_S 11 + +/** CPU_APM_REGION5_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION5_ADDR_START_REG (DR_REG_CPU_BASE + 0x40) +/** CPU_APM_REGION5_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 5. + */ +#define CPU_APM_REGION5_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION5_ADDR_START_L_M (CPU_APM_REGION5_ADDR_START_L_V << CPU_APM_REGION5_ADDR_START_L_S) +#define CPU_APM_REGION5_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION5_ADDR_START_L_S 0 +/** CPU_APM_REGION5_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 5. + */ +#define CPU_APM_REGION5_ADDR_START 0x0000007FU +#define CPU_APM_REGION5_ADDR_START_M (CPU_APM_REGION5_ADDR_START_V << CPU_APM_REGION5_ADDR_START_S) +#define CPU_APM_REGION5_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION5_ADDR_START_S 12 +/** CPU_APM_REGION5_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 5. + */ +#define CPU_APM_REGION5_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION5_ADDR_START_H_M (CPU_APM_REGION5_ADDR_START_H_V << CPU_APM_REGION5_ADDR_START_H_S) +#define CPU_APM_REGION5_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION5_ADDR_START_H_S 19 + +/** CPU_APM_REGION5_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION5_ADDR_END_REG (DR_REG_CPU_BASE + 0x44) +/** CPU_APM_REGION5_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 5. + */ +#define CPU_APM_REGION5_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION5_ADDR_END_L_M (CPU_APM_REGION5_ADDR_END_L_V << CPU_APM_REGION5_ADDR_END_L_S) +#define CPU_APM_REGION5_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION5_ADDR_END_L_S 0 +/** CPU_APM_REGION5_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 5. + */ +#define CPU_APM_REGION5_ADDR_END 0x0000007FU +#define CPU_APM_REGION5_ADDR_END_M (CPU_APM_REGION5_ADDR_END_V << CPU_APM_REGION5_ADDR_END_S) +#define CPU_APM_REGION5_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION5_ADDR_END_S 12 +/** CPU_APM_REGION5_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 5. + */ +#define CPU_APM_REGION5_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION5_ADDR_END_H_M (CPU_APM_REGION5_ADDR_END_H_V << CPU_APM_REGION5_ADDR_END_H_S) +#define CPU_APM_REGION5_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION5_ADDR_END_H_S 19 + +/** CPU_APM_REGION5_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION5_ATTR_REG (DR_REG_CPU_BASE + 0x48) +/** CPU_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 5. + */ +#define CPU_APM_REGION5_R0_X (BIT(0)) +#define CPU_APM_REGION5_R0_X_M (CPU_APM_REGION5_R0_X_V << CPU_APM_REGION5_R0_X_S) +#define CPU_APM_REGION5_R0_X_V 0x00000001U +#define CPU_APM_REGION5_R0_X_S 0 +/** CPU_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 5. + */ +#define CPU_APM_REGION5_R0_W (BIT(1)) +#define CPU_APM_REGION5_R0_W_M (CPU_APM_REGION5_R0_W_V << CPU_APM_REGION5_R0_W_S) +#define CPU_APM_REGION5_R0_W_V 0x00000001U +#define CPU_APM_REGION5_R0_W_S 1 +/** CPU_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 5. + */ +#define CPU_APM_REGION5_R0_R (BIT(2)) +#define CPU_APM_REGION5_R0_R_M (CPU_APM_REGION5_R0_R_V << CPU_APM_REGION5_R0_R_S) +#define CPU_APM_REGION5_R0_R_V 0x00000001U +#define CPU_APM_REGION5_R0_R_S 2 +/** CPU_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 5. + */ +#define CPU_APM_REGION5_R1_X (BIT(4)) +#define CPU_APM_REGION5_R1_X_M (CPU_APM_REGION5_R1_X_V << CPU_APM_REGION5_R1_X_S) +#define CPU_APM_REGION5_R1_X_V 0x00000001U +#define CPU_APM_REGION5_R1_X_S 4 +/** CPU_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 5. + */ +#define CPU_APM_REGION5_R1_W (BIT(5)) +#define CPU_APM_REGION5_R1_W_M (CPU_APM_REGION5_R1_W_V << CPU_APM_REGION5_R1_W_S) +#define CPU_APM_REGION5_R1_W_V 0x00000001U +#define CPU_APM_REGION5_R1_W_S 5 +/** CPU_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 5. + */ +#define CPU_APM_REGION5_R1_R (BIT(6)) +#define CPU_APM_REGION5_R1_R_M (CPU_APM_REGION5_R1_R_V << CPU_APM_REGION5_R1_R_S) +#define CPU_APM_REGION5_R1_R_V 0x00000001U +#define CPU_APM_REGION5_R1_R_S 6 +/** CPU_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 5. + */ +#define CPU_APM_REGION5_R2_X (BIT(8)) +#define CPU_APM_REGION5_R2_X_M (CPU_APM_REGION5_R2_X_V << CPU_APM_REGION5_R2_X_S) +#define CPU_APM_REGION5_R2_X_V 0x00000001U +#define CPU_APM_REGION5_R2_X_S 8 +/** CPU_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 5. + */ +#define CPU_APM_REGION5_R2_W (BIT(9)) +#define CPU_APM_REGION5_R2_W_M (CPU_APM_REGION5_R2_W_V << CPU_APM_REGION5_R2_W_S) +#define CPU_APM_REGION5_R2_W_V 0x00000001U +#define CPU_APM_REGION5_R2_W_S 9 +/** CPU_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 5. + */ +#define CPU_APM_REGION5_R2_R (BIT(10)) +#define CPU_APM_REGION5_R2_R_M (CPU_APM_REGION5_R2_R_V << CPU_APM_REGION5_R2_R_S) +#define CPU_APM_REGION5_R2_R_V 0x00000001U +#define CPU_APM_REGION5_R2_R_S 10 +/** CPU_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION5_LOCK (BIT(11)) +#define CPU_APM_REGION5_LOCK_M (CPU_APM_REGION5_LOCK_V << CPU_APM_REGION5_LOCK_S) +#define CPU_APM_REGION5_LOCK_V 0x00000001U +#define CPU_APM_REGION5_LOCK_S 11 + +/** CPU_APM_REGION6_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION6_ADDR_START_REG (DR_REG_CPU_BASE + 0x4c) +/** CPU_APM_REGION6_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 6. + */ +#define CPU_APM_REGION6_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION6_ADDR_START_L_M (CPU_APM_REGION6_ADDR_START_L_V << CPU_APM_REGION6_ADDR_START_L_S) +#define CPU_APM_REGION6_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION6_ADDR_START_L_S 0 +/** CPU_APM_REGION6_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 6. + */ +#define CPU_APM_REGION6_ADDR_START 0x0000007FU +#define CPU_APM_REGION6_ADDR_START_M (CPU_APM_REGION6_ADDR_START_V << CPU_APM_REGION6_ADDR_START_S) +#define CPU_APM_REGION6_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION6_ADDR_START_S 12 +/** CPU_APM_REGION6_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 6. + */ +#define CPU_APM_REGION6_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION6_ADDR_START_H_M (CPU_APM_REGION6_ADDR_START_H_V << CPU_APM_REGION6_ADDR_START_H_S) +#define CPU_APM_REGION6_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION6_ADDR_START_H_S 19 + +/** CPU_APM_REGION6_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION6_ADDR_END_REG (DR_REG_CPU_BASE + 0x50) +/** CPU_APM_REGION6_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 6. + */ +#define CPU_APM_REGION6_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION6_ADDR_END_L_M (CPU_APM_REGION6_ADDR_END_L_V << CPU_APM_REGION6_ADDR_END_L_S) +#define CPU_APM_REGION6_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION6_ADDR_END_L_S 0 +/** CPU_APM_REGION6_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 6. + */ +#define CPU_APM_REGION6_ADDR_END 0x0000007FU +#define CPU_APM_REGION6_ADDR_END_M (CPU_APM_REGION6_ADDR_END_V << CPU_APM_REGION6_ADDR_END_S) +#define CPU_APM_REGION6_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION6_ADDR_END_S 12 +/** CPU_APM_REGION6_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 6. + */ +#define CPU_APM_REGION6_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION6_ADDR_END_H_M (CPU_APM_REGION6_ADDR_END_H_V << CPU_APM_REGION6_ADDR_END_H_S) +#define CPU_APM_REGION6_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION6_ADDR_END_H_S 19 + +/** CPU_APM_REGION6_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION6_ATTR_REG (DR_REG_CPU_BASE + 0x54) +/** CPU_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 6. + */ +#define CPU_APM_REGION6_R0_X (BIT(0)) +#define CPU_APM_REGION6_R0_X_M (CPU_APM_REGION6_R0_X_V << CPU_APM_REGION6_R0_X_S) +#define CPU_APM_REGION6_R0_X_V 0x00000001U +#define CPU_APM_REGION6_R0_X_S 0 +/** CPU_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 6. + */ +#define CPU_APM_REGION6_R0_W (BIT(1)) +#define CPU_APM_REGION6_R0_W_M (CPU_APM_REGION6_R0_W_V << CPU_APM_REGION6_R0_W_S) +#define CPU_APM_REGION6_R0_W_V 0x00000001U +#define CPU_APM_REGION6_R0_W_S 1 +/** CPU_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 6. + */ +#define CPU_APM_REGION6_R0_R (BIT(2)) +#define CPU_APM_REGION6_R0_R_M (CPU_APM_REGION6_R0_R_V << CPU_APM_REGION6_R0_R_S) +#define CPU_APM_REGION6_R0_R_V 0x00000001U +#define CPU_APM_REGION6_R0_R_S 2 +/** CPU_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 6. + */ +#define CPU_APM_REGION6_R1_X (BIT(4)) +#define CPU_APM_REGION6_R1_X_M (CPU_APM_REGION6_R1_X_V << CPU_APM_REGION6_R1_X_S) +#define CPU_APM_REGION6_R1_X_V 0x00000001U +#define CPU_APM_REGION6_R1_X_S 4 +/** CPU_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 6. + */ +#define CPU_APM_REGION6_R1_W (BIT(5)) +#define CPU_APM_REGION6_R1_W_M (CPU_APM_REGION6_R1_W_V << CPU_APM_REGION6_R1_W_S) +#define CPU_APM_REGION6_R1_W_V 0x00000001U +#define CPU_APM_REGION6_R1_W_S 5 +/** CPU_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 6. + */ +#define CPU_APM_REGION6_R1_R (BIT(6)) +#define CPU_APM_REGION6_R1_R_M (CPU_APM_REGION6_R1_R_V << CPU_APM_REGION6_R1_R_S) +#define CPU_APM_REGION6_R1_R_V 0x00000001U +#define CPU_APM_REGION6_R1_R_S 6 +/** CPU_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 6. + */ +#define CPU_APM_REGION6_R2_X (BIT(8)) +#define CPU_APM_REGION6_R2_X_M (CPU_APM_REGION6_R2_X_V << CPU_APM_REGION6_R2_X_S) +#define CPU_APM_REGION6_R2_X_V 0x00000001U +#define CPU_APM_REGION6_R2_X_S 8 +/** CPU_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 6. + */ +#define CPU_APM_REGION6_R2_W (BIT(9)) +#define CPU_APM_REGION6_R2_W_M (CPU_APM_REGION6_R2_W_V << CPU_APM_REGION6_R2_W_S) +#define CPU_APM_REGION6_R2_W_V 0x00000001U +#define CPU_APM_REGION6_R2_W_S 9 +/** CPU_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 6. + */ +#define CPU_APM_REGION6_R2_R (BIT(10)) +#define CPU_APM_REGION6_R2_R_M (CPU_APM_REGION6_R2_R_V << CPU_APM_REGION6_R2_R_S) +#define CPU_APM_REGION6_R2_R_V 0x00000001U +#define CPU_APM_REGION6_R2_R_S 10 +/** CPU_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION6_LOCK (BIT(11)) +#define CPU_APM_REGION6_LOCK_M (CPU_APM_REGION6_LOCK_V << CPU_APM_REGION6_LOCK_S) +#define CPU_APM_REGION6_LOCK_V 0x00000001U +#define CPU_APM_REGION6_LOCK_S 11 + +/** CPU_APM_REGION7_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION7_ADDR_START_REG (DR_REG_CPU_BASE + 0x58) +/** CPU_APM_REGION7_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 7. + */ +#define CPU_APM_REGION7_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION7_ADDR_START_L_M (CPU_APM_REGION7_ADDR_START_L_V << CPU_APM_REGION7_ADDR_START_L_S) +#define CPU_APM_REGION7_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION7_ADDR_START_L_S 0 +/** CPU_APM_REGION7_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 7. + */ +#define CPU_APM_REGION7_ADDR_START 0x0000007FU +#define CPU_APM_REGION7_ADDR_START_M (CPU_APM_REGION7_ADDR_START_V << CPU_APM_REGION7_ADDR_START_S) +#define CPU_APM_REGION7_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION7_ADDR_START_S 12 +/** CPU_APM_REGION7_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 7. + */ +#define CPU_APM_REGION7_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION7_ADDR_START_H_M (CPU_APM_REGION7_ADDR_START_H_V << CPU_APM_REGION7_ADDR_START_H_S) +#define CPU_APM_REGION7_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION7_ADDR_START_H_S 19 + +/** CPU_APM_REGION7_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION7_ADDR_END_REG (DR_REG_CPU_BASE + 0x5c) +/** CPU_APM_REGION7_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 7. + */ +#define CPU_APM_REGION7_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION7_ADDR_END_L_M (CPU_APM_REGION7_ADDR_END_L_V << CPU_APM_REGION7_ADDR_END_L_S) +#define CPU_APM_REGION7_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION7_ADDR_END_L_S 0 +/** CPU_APM_REGION7_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 7. + */ +#define CPU_APM_REGION7_ADDR_END 0x0000007FU +#define CPU_APM_REGION7_ADDR_END_M (CPU_APM_REGION7_ADDR_END_V << CPU_APM_REGION7_ADDR_END_S) +#define CPU_APM_REGION7_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION7_ADDR_END_S 12 +/** CPU_APM_REGION7_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 7. + */ +#define CPU_APM_REGION7_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION7_ADDR_END_H_M (CPU_APM_REGION7_ADDR_END_H_V << CPU_APM_REGION7_ADDR_END_H_S) +#define CPU_APM_REGION7_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION7_ADDR_END_H_S 19 + +/** CPU_APM_REGION7_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION7_ATTR_REG (DR_REG_CPU_BASE + 0x60) +/** CPU_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 7. + */ +#define CPU_APM_REGION7_R0_X (BIT(0)) +#define CPU_APM_REGION7_R0_X_M (CPU_APM_REGION7_R0_X_V << CPU_APM_REGION7_R0_X_S) +#define CPU_APM_REGION7_R0_X_V 0x00000001U +#define CPU_APM_REGION7_R0_X_S 0 +/** CPU_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 7. + */ +#define CPU_APM_REGION7_R0_W (BIT(1)) +#define CPU_APM_REGION7_R0_W_M (CPU_APM_REGION7_R0_W_V << CPU_APM_REGION7_R0_W_S) +#define CPU_APM_REGION7_R0_W_V 0x00000001U +#define CPU_APM_REGION7_R0_W_S 1 +/** CPU_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 7. + */ +#define CPU_APM_REGION7_R0_R (BIT(2)) +#define CPU_APM_REGION7_R0_R_M (CPU_APM_REGION7_R0_R_V << CPU_APM_REGION7_R0_R_S) +#define CPU_APM_REGION7_R0_R_V 0x00000001U +#define CPU_APM_REGION7_R0_R_S 2 +/** CPU_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 7. + */ +#define CPU_APM_REGION7_R1_X (BIT(4)) +#define CPU_APM_REGION7_R1_X_M (CPU_APM_REGION7_R1_X_V << CPU_APM_REGION7_R1_X_S) +#define CPU_APM_REGION7_R1_X_V 0x00000001U +#define CPU_APM_REGION7_R1_X_S 4 +/** CPU_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 7. + */ +#define CPU_APM_REGION7_R1_W (BIT(5)) +#define CPU_APM_REGION7_R1_W_M (CPU_APM_REGION7_R1_W_V << CPU_APM_REGION7_R1_W_S) +#define CPU_APM_REGION7_R1_W_V 0x00000001U +#define CPU_APM_REGION7_R1_W_S 5 +/** CPU_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 7. + */ +#define CPU_APM_REGION7_R1_R (BIT(6)) +#define CPU_APM_REGION7_R1_R_M (CPU_APM_REGION7_R1_R_V << CPU_APM_REGION7_R1_R_S) +#define CPU_APM_REGION7_R1_R_V 0x00000001U +#define CPU_APM_REGION7_R1_R_S 6 +/** CPU_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 7. + */ +#define CPU_APM_REGION7_R2_X (BIT(8)) +#define CPU_APM_REGION7_R2_X_M (CPU_APM_REGION7_R2_X_V << CPU_APM_REGION7_R2_X_S) +#define CPU_APM_REGION7_R2_X_V 0x00000001U +#define CPU_APM_REGION7_R2_X_S 8 +/** CPU_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 7. + */ +#define CPU_APM_REGION7_R2_W (BIT(9)) +#define CPU_APM_REGION7_R2_W_M (CPU_APM_REGION7_R2_W_V << CPU_APM_REGION7_R2_W_S) +#define CPU_APM_REGION7_R2_W_V 0x00000001U +#define CPU_APM_REGION7_R2_W_S 9 +/** CPU_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 7. + */ +#define CPU_APM_REGION7_R2_R (BIT(10)) +#define CPU_APM_REGION7_R2_R_M (CPU_APM_REGION7_R2_R_V << CPU_APM_REGION7_R2_R_S) +#define CPU_APM_REGION7_R2_R_V 0x00000001U +#define CPU_APM_REGION7_R2_R_S 10 +/** CPU_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION7_LOCK (BIT(11)) +#define CPU_APM_REGION7_LOCK_M (CPU_APM_REGION7_LOCK_V << CPU_APM_REGION7_LOCK_S) +#define CPU_APM_REGION7_LOCK_V 0x00000001U +#define CPU_APM_REGION7_LOCK_S 11 + +/** CPU_APM_FUNC_CTRL_REG register + * APM function control register + */ +#define CPU_APM_FUNC_CTRL_REG (DR_REG_CPU_BASE + 0xc4) +/** CPU_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define CPU_APM_M0_FUNC_EN (BIT(0)) +#define CPU_APM_M0_FUNC_EN_M (CPU_APM_M0_FUNC_EN_V << CPU_APM_M0_FUNC_EN_S) +#define CPU_APM_M0_FUNC_EN_V 0x00000001U +#define CPU_APM_M0_FUNC_EN_S 0 +/** CPU_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ +#define CPU_APM_M1_FUNC_EN (BIT(1)) +#define CPU_APM_M1_FUNC_EN_M (CPU_APM_M1_FUNC_EN_V << CPU_APM_M1_FUNC_EN_S) +#define CPU_APM_M1_FUNC_EN_V 0x00000001U +#define CPU_APM_M1_FUNC_EN_S 1 + +/** CPU_APM_M0_STATUS_REG register + * M0 status register + */ +#define CPU_APM_M0_STATUS_REG (DR_REG_CPU_BASE + 0xc8) +/** CPU_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ +#define CPU_APM_M0_EXCEPTION_STATUS 0x00000003U +#define CPU_APM_M0_EXCEPTION_STATUS_M (CPU_APM_M0_EXCEPTION_STATUS_V << CPU_APM_M0_EXCEPTION_STATUS_S) +#define CPU_APM_M0_EXCEPTION_STATUS_V 0x00000003U +#define CPU_APM_M0_EXCEPTION_STATUS_S 0 + +/** CPU_APM_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define CPU_APM_M0_STATUS_CLR_REG (DR_REG_CPU_BASE + 0xcc) +/** CPU_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ +#define CPU_APM_M0_EXCEPTION_STATUS_CLR (BIT(0)) +#define CPU_APM_M0_EXCEPTION_STATUS_CLR_M (CPU_APM_M0_EXCEPTION_STATUS_CLR_V << CPU_APM_M0_EXCEPTION_STATUS_CLR_S) +#define CPU_APM_M0_EXCEPTION_STATUS_CLR_V 0x00000001U +#define CPU_APM_M0_EXCEPTION_STATUS_CLR_S 0 + +/** CPU_APM_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define CPU_APM_M0_EXCEPTION_INFO0_REG (DR_REG_CPU_BASE + 0xd0) +/** CPU_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ +#define CPU_APM_M0_EXCEPTION_REGION 0x0000FFFFU +#define CPU_APM_M0_EXCEPTION_REGION_M (CPU_APM_M0_EXCEPTION_REGION_V << CPU_APM_M0_EXCEPTION_REGION_S) +#define CPU_APM_M0_EXCEPTION_REGION_V 0x0000FFFFU +#define CPU_APM_M0_EXCEPTION_REGION_S 0 +/** CPU_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ +#define CPU_APM_M0_EXCEPTION_MODE 0x00000003U +#define CPU_APM_M0_EXCEPTION_MODE_M (CPU_APM_M0_EXCEPTION_MODE_V << CPU_APM_M0_EXCEPTION_MODE_S) +#define CPU_APM_M0_EXCEPTION_MODE_V 0x00000003U +#define CPU_APM_M0_EXCEPTION_MODE_S 16 +/** CPU_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ +#define CPU_APM_M0_EXCEPTION_ID 0x0000001FU +#define CPU_APM_M0_EXCEPTION_ID_M (CPU_APM_M0_EXCEPTION_ID_V << CPU_APM_M0_EXCEPTION_ID_S) +#define CPU_APM_M0_EXCEPTION_ID_V 0x0000001FU +#define CPU_APM_M0_EXCEPTION_ID_S 18 + +/** CPU_APM_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define CPU_APM_M0_EXCEPTION_INFO1_REG (DR_REG_CPU_BASE + 0xd4) +/** CPU_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ +#define CPU_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define CPU_APM_M0_EXCEPTION_ADDR_M (CPU_APM_M0_EXCEPTION_ADDR_V << CPU_APM_M0_EXCEPTION_ADDR_S) +#define CPU_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define CPU_APM_M0_EXCEPTION_ADDR_S 0 + +/** CPU_APM_M1_STATUS_REG register + * M1 status register + */ +#define CPU_APM_M1_STATUS_REG (DR_REG_CPU_BASE + 0xd8) +/** CPU_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ +#define CPU_APM_M1_EXCEPTION_STATUS 0x00000003U +#define CPU_APM_M1_EXCEPTION_STATUS_M (CPU_APM_M1_EXCEPTION_STATUS_V << CPU_APM_M1_EXCEPTION_STATUS_S) +#define CPU_APM_M1_EXCEPTION_STATUS_V 0x00000003U +#define CPU_APM_M1_EXCEPTION_STATUS_S 0 + +/** CPU_APM_M1_STATUS_CLR_REG register + * M1 status clear register + */ +#define CPU_APM_M1_STATUS_CLR_REG (DR_REG_CPU_BASE + 0xdc) +/** CPU_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ +#define CPU_APM_M1_EXCEPTION_STATUS_CLR (BIT(0)) +#define CPU_APM_M1_EXCEPTION_STATUS_CLR_M (CPU_APM_M1_EXCEPTION_STATUS_CLR_V << CPU_APM_M1_EXCEPTION_STATUS_CLR_S) +#define CPU_APM_M1_EXCEPTION_STATUS_CLR_V 0x00000001U +#define CPU_APM_M1_EXCEPTION_STATUS_CLR_S 0 + +/** CPU_APM_M1_EXCEPTION_INFO0_REG register + * M1 exception_info0 register + */ +#define CPU_APM_M1_EXCEPTION_INFO0_REG (DR_REG_CPU_BASE + 0xe0) +/** CPU_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ +#define CPU_APM_M1_EXCEPTION_REGION 0x0000FFFFU +#define CPU_APM_M1_EXCEPTION_REGION_M (CPU_APM_M1_EXCEPTION_REGION_V << CPU_APM_M1_EXCEPTION_REGION_S) +#define CPU_APM_M1_EXCEPTION_REGION_V 0x0000FFFFU +#define CPU_APM_M1_EXCEPTION_REGION_S 0 +/** CPU_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ +#define CPU_APM_M1_EXCEPTION_MODE 0x00000003U +#define CPU_APM_M1_EXCEPTION_MODE_M (CPU_APM_M1_EXCEPTION_MODE_V << CPU_APM_M1_EXCEPTION_MODE_S) +#define CPU_APM_M1_EXCEPTION_MODE_V 0x00000003U +#define CPU_APM_M1_EXCEPTION_MODE_S 16 +/** CPU_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ +#define CPU_APM_M1_EXCEPTION_ID 0x0000001FU +#define CPU_APM_M1_EXCEPTION_ID_M (CPU_APM_M1_EXCEPTION_ID_V << CPU_APM_M1_EXCEPTION_ID_S) +#define CPU_APM_M1_EXCEPTION_ID_V 0x0000001FU +#define CPU_APM_M1_EXCEPTION_ID_S 18 + +/** CPU_APM_M1_EXCEPTION_INFO1_REG register + * M1 exception_info1 register + */ +#define CPU_APM_M1_EXCEPTION_INFO1_REG (DR_REG_CPU_BASE + 0xe4) +/** CPU_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ +#define CPU_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU +#define CPU_APM_M1_EXCEPTION_ADDR_M (CPU_APM_M1_EXCEPTION_ADDR_V << CPU_APM_M1_EXCEPTION_ADDR_S) +#define CPU_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define CPU_APM_M1_EXCEPTION_ADDR_S 0 + +/** CPU_APM_INT_EN_REG register + * APM interrupt enable register + */ +#define CPU_APM_INT_EN_REG (DR_REG_CPU_BASE + 0x118) +/** CPU_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * Configures to enable APM M0 interrupt. + * 0: disable + * 1: enable + */ +#define CPU_APM_M0_APM_INT_EN (BIT(0)) +#define CPU_APM_M0_APM_INT_EN_M (CPU_APM_M0_APM_INT_EN_V << CPU_APM_M0_APM_INT_EN_S) +#define CPU_APM_M0_APM_INT_EN_V 0x00000001U +#define CPU_APM_M0_APM_INT_EN_S 0 +/** CPU_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; + * Configures to enable APM M1 interrupt. + * 0: disable + * 1: enable + */ +#define CPU_APM_M1_APM_INT_EN (BIT(1)) +#define CPU_APM_M1_APM_INT_EN_M (CPU_APM_M1_APM_INT_EN_V << CPU_APM_M1_APM_INT_EN_S) +#define CPU_APM_M1_APM_INT_EN_V 0x00000001U +#define CPU_APM_M1_APM_INT_EN_S 1 + +/** CPU_APM_CLOCK_GATE_REG register + * Clock gating register + */ +#define CPU_APM_CLOCK_GATE_REG (DR_REG_CPU_BASE + 0x7f8) +/** CPU_APM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on + */ +#define CPU_APM_CLK_EN (BIT(0)) +#define CPU_APM_CLK_EN_M (CPU_APM_CLK_EN_V << CPU_APM_CLK_EN_S) +#define CPU_APM_CLK_EN_V 0x00000001U +#define CPU_APM_CLK_EN_S 0 + +/** CPU_APM_DATE_REG register + * Version control register + */ +#define CPU_APM_DATE_REG (DR_REG_CPU_BASE + 0x7fc) +/** CPU_APM_DATE : R/W; bitpos: [27:0]; default: 37823248; + * Version control register. + */ +#define CPU_APM_DATE 0x0FFFFFFFU +#define CPU_APM_DATE_M (CPU_APM_DATE_V << CPU_APM_DATE_S) +#define CPU_APM_DATE_V 0x0FFFFFFFU +#define CPU_APM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/register/soc/cpu_apm_struct.h b/components/soc/esp32c61/register/soc/cpu_apm_struct.h new file mode 100644 index 0000000000..8cb9219a85 --- /dev/null +++ b/components/soc/esp32c61/register/soc/cpu_apm_struct.h @@ -0,0 +1,403 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of apm_region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** apm_region_filter_en : R/W; bitpos: [7:0]; default: 1; + * Configure bit $n (0-7) to enable region $n. + * 0: disable + * 1: enable + */ + uint32_t apm_region_filter_en:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} cpu_apm_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of apm_regionn_addr_start register + * Region address register + */ +typedef union { + struct { + /** apm_regionn_addr_start_l : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region n. + */ + uint32_t apm_regionn_addr_start_l:12; + /** apm_regionn_addr_start : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region n. + */ + uint32_t apm_regionn_addr_start:7; + /** apm_regionn_addr_start_h : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region n. + */ + uint32_t apm_regionn_addr_start_h:13; + }; + uint32_t val; +} cpu_apm_regionn_addr_start_reg_t; + +/** Type of apm_regionn_addr_end register + * Region address register + */ +typedef union { + struct { + /** apm_regionn_addr_end_l : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region n. + */ + uint32_t apm_regionn_addr_end_l:12; + /** apm_regionn_addr_end : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region n. + */ + uint32_t apm_regionn_addr_end:7; + /** apm_regionn_addr_end_h : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region n. + */ + uint32_t apm_regionn_addr_end_h:13; + }; + uint32_t val; +} cpu_apm_regionn_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of apm_regionn_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** apm_regionn_r0_x : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region n. + */ + uint32_t apm_regionn_r0_x:1; + /** apm_regionn_r0_w : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region n. + */ + uint32_t apm_regionn_r0_w:1; + /** apm_regionn_r0_r : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region n. + */ + uint32_t apm_regionn_r0_r:1; + uint32_t reserved_3:1; + /** apm_regionn_r1_x : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region n. + */ + uint32_t apm_regionn_r1_x:1; + /** apm_regionn_r1_w : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region n. + */ + uint32_t apm_regionn_r1_w:1; + /** apm_regionn_r1_r : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region n. + */ + uint32_t apm_regionn_r1_r:1; + uint32_t reserved_7:1; + /** apm_regionn_r2_x : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region n. + */ + uint32_t apm_regionn_r2_x:1; + /** apm_regionn_r2_w : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region n. + */ + uint32_t apm_regionn_r2_w:1; + /** apm_regionn_r2_r : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region n. + */ + uint32_t apm_regionn_r2_r:1; + /** apm_regionn_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ + uint32_t apm_regionn_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} cpu_apm_regionn_attr_reg_t; + + +/** Group: function control register */ +/** Type of apm_func_ctrl register + * APM function control register + */ +typedef union { + struct { + /** apm_m0_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t apm_m0_func_en:1; + /** apm_m1_func_en : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ + uint32_t apm_m1_func_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} cpu_apm_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of apm_m0_status register + * M0 status register + */ +typedef union { + struct { + /** apm_m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ + uint32_t apm_m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} cpu_apm_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of apm_m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** apm_m0_exception_status_clr : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ + uint32_t apm_m0_exception_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} cpu_apm_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of apm_m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** apm_m0_exception_region : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ + uint32_t apm_m0_exception_region:16; + /** apm_m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ + uint32_t apm_m0_exception_mode:2; + /** apm_m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ + uint32_t apm_m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} cpu_apm_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of apm_m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** apm_m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ + uint32_t apm_m0_exception_addr:32; + }; + uint32_t val; +} cpu_apm_m0_exception_info1_reg_t; + + +/** Group: M1 status register */ +/** Type of apm_m1_status register + * M1 status register + */ +typedef union { + struct { + /** apm_m1_exception_status : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ + uint32_t apm_m1_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} cpu_apm_m1_status_reg_t; + + +/** Group: M1 status clear register */ +/** Type of apm_m1_status_clr register + * M1 status clear register + */ +typedef union { + struct { + /** apm_m1_exception_status_clr : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ + uint32_t apm_m1_exception_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} cpu_apm_m1_status_clr_reg_t; + + +/** Group: M1 exception_info0 register */ +/** Type of apm_m1_exception_info0 register + * M1 exception_info0 register + */ +typedef union { + struct { + /** apm_m1_exception_region : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ + uint32_t apm_m1_exception_region:16; + /** apm_m1_exception_mode : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ + uint32_t apm_m1_exception_mode:2; + /** apm_m1_exception_id : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ + uint32_t apm_m1_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} cpu_apm_m1_exception_info0_reg_t; + + +/** Group: M1 exception_info1 register */ +/** Type of apm_m1_exception_info1 register + * M1 exception_info1 register + */ +typedef union { + struct { + /** apm_m1_exception_addr : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ + uint32_t apm_m1_exception_addr:32; + }; + uint32_t val; +} cpu_apm_m1_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of apm_int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** apm_m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * Configures to enable APM M0 interrupt. + * 0: disable + * 1: enable + */ + uint32_t apm_m0_apm_int_en:1; + /** apm_m1_apm_int_en : R/W; bitpos: [1]; default: 0; + * Configures to enable APM M1 interrupt. + * 0: disable + * 1: enable + */ + uint32_t apm_m1_apm_int_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} cpu_apm_int_en_reg_t; + + +/** Group: Clock gating register */ +/** Type of apm_clock_gate register + * Clock gating register + */ +typedef union { + struct { + /** apm_clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on + */ + uint32_t apm_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} cpu_apm_clock_gate_reg_t; + + +/** Group: Version control register */ +/** Type of apm_date register + * Version control register + */ +typedef union { + struct { + /** apm_date : R/W; bitpos: [27:0]; default: 37823248; + * Version control register. + */ + uint32_t apm_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cpu_apm_date_reg_t; + + +typedef struct { + volatile cpu_apm_region_filter_en_reg_t apm_region_filter_en; + volatile cpu_apm_regionn_addr_start_reg_t apm_region0_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t apm_region0_addr_end; + volatile cpu_apm_regionn_attr_reg_t apm_region0_attr; + volatile cpu_apm_regionn_addr_start_reg_t apm_region1_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t apm_region1_addr_end; + volatile cpu_apm_regionn_attr_reg_t apm_region1_attr; + volatile cpu_apm_regionn_addr_start_reg_t apm_region2_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t apm_region2_addr_end; + volatile cpu_apm_regionn_attr_reg_t apm_region2_attr; + volatile cpu_apm_regionn_addr_start_reg_t apm_region3_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t apm_region3_addr_end; + volatile cpu_apm_regionn_attr_reg_t apm_region3_attr; + volatile cpu_apm_regionn_addr_start_reg_t apm_region4_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t apm_region4_addr_end; + volatile cpu_apm_regionn_attr_reg_t apm_region4_attr; + volatile cpu_apm_regionn_addr_start_reg_t apm_region5_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t apm_region5_addr_end; + volatile cpu_apm_regionn_attr_reg_t apm_region5_attr; + volatile cpu_apm_regionn_addr_start_reg_t apm_region6_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t apm_region6_addr_end; + volatile cpu_apm_regionn_attr_reg_t apm_region6_attr; + volatile cpu_apm_regionn_addr_start_reg_t apm_region7_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t apm_region7_addr_end; + volatile cpu_apm_regionn_attr_reg_t apm_region7_attr; + uint32_t reserved_064[24]; + volatile cpu_apm_func_ctrl_reg_t apm_func_ctrl; + volatile cpu_apm_m0_status_reg_t apm_m0_status; + volatile cpu_apm_m0_status_clr_reg_t apm_m0_status_clr; + volatile cpu_apm_m0_exception_info0_reg_t apm_m0_exception_info0; + volatile cpu_apm_m0_exception_info1_reg_t apm_m0_exception_info1; + volatile cpu_apm_m1_status_reg_t apm_m1_status; + volatile cpu_apm_m1_status_clr_reg_t apm_m1_status_clr; + volatile cpu_apm_m1_exception_info0_reg_t apm_m1_exception_info0; + volatile cpu_apm_m1_exception_info1_reg_t apm_m1_exception_info1; + uint32_t reserved_0e8[12]; + volatile cpu_apm_int_en_reg_t apm_int_en; + uint32_t reserved_11c[439]; + volatile cpu_apm_clock_gate_reg_t apm_clock_gate; + volatile cpu_apm_date_reg_t apm_date; +} cpu_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(cpu_dev_t) == 0x800, "Invalid size of cpu_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/register/soc/gpio_ext_reg.h b/components/soc/esp32c61/register/soc/gpio_ext_reg.h index 2385576c33..ea6e3730e6 100644 --- a/components/soc/esp32c61/register/soc/gpio_ext_reg.h +++ b/components/soc/esp32c61/register/soc/gpio_ext_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,48 +11,27 @@ extern "C" { #endif -/** GPIO_EXT_CLOCK_GATE_REG register - * Clock Gating Configure Register - */ -#define GPIO_EXT_CLOCK_GATE_REG (DR_REG_GPIO_EXT_BASE + 0x0) -/** GPIO_EXT_CLK_EN : R/W; bitpos: [0]; default: 0; - * Clock enable bit of configuration registers for sigma delta modulation. - */ -#define GPIO_EXT_CLK_EN (BIT(0)) -#define GPIO_EXT_CLK_EN_M (GPIO_EXT_CLK_EN_V << GPIO_EXT_CLK_EN_S) -#define GPIO_EXT_CLK_EN_V 0x00000001U -#define GPIO_EXT_CLK_EN_S 0 - /** GPIO_EXT_PAD_COMP_CONFIG_0_REG register - * Configuration register for zero-crossing detection + * PAD Compare configure Register */ -#define GPIO_EXT_PAD_COMP_CONFIG_0_REG (DR_REG_GPIO_EXT_BASE + 0x58) +#define GPIO_EXT_PAD_COMP_CONFIG_0_REG (DR_REG_GPIO_BASE + 0x58) /** GPIO_EXT_XPD_COMP_0 : R/W; bitpos: [0]; default: 0; - * Configures whether to enable the function of analog PAD voltage comparator.\\ - * 0: Disable\\ - * 1: Enable\\ + * Pad compare enable bit. */ #define GPIO_EXT_XPD_COMP_0 (BIT(0)) #define GPIO_EXT_XPD_COMP_0_M (GPIO_EXT_XPD_COMP_0_V << GPIO_EXT_XPD_COMP_0_S) #define GPIO_EXT_XPD_COMP_0_V 0x00000001U #define GPIO_EXT_XPD_COMP_0_S 0 /** GPIO_EXT_MODE_COMP_0 : R/W; bitpos: [1]; default: 0; - * Configures the reference voltage for analog PAD voltage comparator.. \\ - * 0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be - * used as a regular GPIO\\ - * 1: Reference voltage is the voltage on the GPIO8 PAD\\ + * 1 to enable external reference from PAD[x]. 0 to enable internal reference, + * meanwhile PAD[x] can be used as a regular GPIO. */ #define GPIO_EXT_MODE_COMP_0 (BIT(1)) #define GPIO_EXT_MODE_COMP_0_M (GPIO_EXT_MODE_COMP_0_V << GPIO_EXT_MODE_COMP_0_S) #define GPIO_EXT_MODE_COMP_0_V 0x00000001U #define GPIO_EXT_MODE_COMP_0_S 1 /** GPIO_EXT_DREF_COMP_0 : R/W; bitpos: [4:2]; default: 0; - * Configures the internal reference voltage for analog PAD voltage coparator. \\ - * 0: Internal reference voltage is 0 * VDDPST1\\ - * 1: Internal reference voltage is 0.1 * VDDPST1\\ - * ......\\ - * 6: Internal reference voltage is 0.6 * VDDPST1\\ - * 7: Internal reference voltage is 0.7 * VDDPST1\\ + * internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST. */ #define GPIO_EXT_DREF_COMP_0 0x00000007U #define GPIO_EXT_DREF_COMP_0_M (GPIO_EXT_DREF_COMP_0_V << GPIO_EXT_DREF_COMP_0_S) @@ -60,13 +39,11 @@ extern "C" { #define GPIO_EXT_DREF_COMP_0_S 2 /** GPIO_EXT_PAD_COMP_FILTER_0_REG register - * Configuration register for interrupt source mask period of zero-crossing detection + * Zero Detect filter Register */ -#define GPIO_EXT_PAD_COMP_FILTER_0_REG (DR_REG_GPIO_EXT_BASE + 0x5c) +#define GPIO_EXT_PAD_COMP_FILTER_0_REG (DR_REG_GPIO_BASE + 0x5c) /** GPIO_EXT_ZERO_DET_FILTER_CNT_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the period of masking new interrupt source foe analog PAD voltage - * comparator.\\ - * Measurement unit: IO MUX operating clock cycle\\ + * Zero Detect filter cycle length */ #define GPIO_EXT_ZERO_DET_FILTER_CNT_0 0xFFFFFFFFU #define GPIO_EXT_ZERO_DET_FILTER_CNT_0_M (GPIO_EXT_ZERO_DET_FILTER_CNT_0_V << GPIO_EXT_ZERO_DET_FILTER_CNT_0_S) @@ -74,26 +51,18 @@ extern "C" { #define GPIO_EXT_ZERO_DET_FILTER_CNT_0_S 0 /** GPIO_EXT_ETM_EVENT_CH0_CFG_REG register - * ETM configuration register for channel 0 + * Etm Config register of Channel0 */ -#define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x118) -/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * 25 ~ 31: Reserved\\ +#define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_BASE + 0x118) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Etm event channel select gpio. */ -#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU #define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU #define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 /** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Etm event send enable bit. */ #define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) #define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) @@ -101,293 +70,207 @@ extern "C" { #define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH1_CFG_REG register - * ETM configuration register for channel 0 + * Etm Config register of Channel1 */ -#define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x11c) -/** GPIO_EXT_ETM_CH1_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * 25 ~ 31: Reserved\\ +#define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_BASE + 0x11c) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Etm event channel select gpio. */ -#define GPIO_EXT_ETM_CH1_EVENT_SEL 0x0000001FU -#define GPIO_EXT_ETM_CH1_EVENT_SEL_M (GPIO_EXT_ETM_CH1_EVENT_SEL_V << GPIO_EXT_ETM_CH1_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH1_EVENT_SEL_V 0x0000001FU -#define GPIO_EXT_ETM_CH1_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH1_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. */ -#define GPIO_EXT_ETM_CH1_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH1_EVENT_EN_M (GPIO_EXT_ETM_CH1_EVENT_EN_V << GPIO_EXT_ETM_CH1_EVENT_EN_S) -#define GPIO_EXT_ETM_CH1_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH1_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH2_CFG_REG register - * ETM configuration register for channel 0 + * Etm Config register of Channel2 */ -#define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x120) -/** GPIO_EXT_ETM_CH2_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * 25 ~ 31: Reserved\\ +#define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_BASE + 0x120) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Etm event channel select gpio. */ -#define GPIO_EXT_ETM_CH2_EVENT_SEL 0x0000001FU -#define GPIO_EXT_ETM_CH2_EVENT_SEL_M (GPIO_EXT_ETM_CH2_EVENT_SEL_V << GPIO_EXT_ETM_CH2_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH2_EVENT_SEL_V 0x0000001FU -#define GPIO_EXT_ETM_CH2_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH2_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. */ -#define GPIO_EXT_ETM_CH2_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH2_EVENT_EN_M (GPIO_EXT_ETM_CH2_EVENT_EN_V << GPIO_EXT_ETM_CH2_EVENT_EN_S) -#define GPIO_EXT_ETM_CH2_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH2_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH3_CFG_REG register - * ETM configuration register for channel 0 + * Etm Config register of Channel3 */ -#define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x124) -/** GPIO_EXT_ETM_CH3_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * 25 ~ 31: Reserved\\ +#define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_BASE + 0x124) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Etm event channel select gpio. */ -#define GPIO_EXT_ETM_CH3_EVENT_SEL 0x0000001FU -#define GPIO_EXT_ETM_CH3_EVENT_SEL_M (GPIO_EXT_ETM_CH3_EVENT_SEL_V << GPIO_EXT_ETM_CH3_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH3_EVENT_SEL_V 0x0000001FU -#define GPIO_EXT_ETM_CH3_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH3_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. */ -#define GPIO_EXT_ETM_CH3_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH3_EVENT_EN_M (GPIO_EXT_ETM_CH3_EVENT_EN_V << GPIO_EXT_ETM_CH3_EVENT_EN_S) -#define GPIO_EXT_ETM_CH3_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH3_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH4_CFG_REG register - * ETM configuration register for channel 0 + * Etm Config register of Channel4 */ -#define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x128) -/** GPIO_EXT_ETM_CH4_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * 25 ~ 31: Reserved\\ +#define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_BASE + 0x128) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Etm event channel select gpio. */ -#define GPIO_EXT_ETM_CH4_EVENT_SEL 0x0000001FU -#define GPIO_EXT_ETM_CH4_EVENT_SEL_M (GPIO_EXT_ETM_CH4_EVENT_SEL_V << GPIO_EXT_ETM_CH4_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH4_EVENT_SEL_V 0x0000001FU -#define GPIO_EXT_ETM_CH4_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH4_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. */ -#define GPIO_EXT_ETM_CH4_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH4_EVENT_EN_M (GPIO_EXT_ETM_CH4_EVENT_EN_V << GPIO_EXT_ETM_CH4_EVENT_EN_S) -#define GPIO_EXT_ETM_CH4_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH4_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH5_CFG_REG register - * ETM configuration register for channel 0 + * Etm Config register of Channel5 */ -#define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x12c) -/** GPIO_EXT_ETM_CH5_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * 25 ~ 31: Reserved\\ +#define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_BASE + 0x12c) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Etm event channel select gpio. */ -#define GPIO_EXT_ETM_CH5_EVENT_SEL 0x0000001FU -#define GPIO_EXT_ETM_CH5_EVENT_SEL_M (GPIO_EXT_ETM_CH5_EVENT_SEL_V << GPIO_EXT_ETM_CH5_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH5_EVENT_SEL_V 0x0000001FU -#define GPIO_EXT_ETM_CH5_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH5_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. */ -#define GPIO_EXT_ETM_CH5_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH5_EVENT_EN_M (GPIO_EXT_ETM_CH5_EVENT_EN_V << GPIO_EXT_ETM_CH5_EVENT_EN_S) -#define GPIO_EXT_ETM_CH5_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH5_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH6_CFG_REG register - * ETM configuration register for channel 0 + * Etm Config register of Channel6 */ -#define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x130) -/** GPIO_EXT_ETM_CH6_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * 25 ~ 31: Reserved\\ +#define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_BASE + 0x130) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Etm event channel select gpio. */ -#define GPIO_EXT_ETM_CH6_EVENT_SEL 0x0000001FU -#define GPIO_EXT_ETM_CH6_EVENT_SEL_M (GPIO_EXT_ETM_CH6_EVENT_SEL_V << GPIO_EXT_ETM_CH6_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH6_EVENT_SEL_V 0x0000001FU -#define GPIO_EXT_ETM_CH6_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH6_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. */ -#define GPIO_EXT_ETM_CH6_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH6_EVENT_EN_M (GPIO_EXT_ETM_CH6_EVENT_EN_V << GPIO_EXT_ETM_CH6_EVENT_EN_S) -#define GPIO_EXT_ETM_CH6_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH6_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH7_CFG_REG register - * ETM configuration register for channel 0 + * Etm Config register of Channel7 */ -#define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x134) -/** GPIO_EXT_ETM_CH7_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * 25 ~ 31: Reserved\\ +#define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_BASE + 0x134) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Etm event channel select gpio. */ -#define GPIO_EXT_ETM_CH7_EVENT_SEL 0x0000001FU -#define GPIO_EXT_ETM_CH7_EVENT_SEL_M (GPIO_EXT_ETM_CH7_EVENT_SEL_V << GPIO_EXT_ETM_CH7_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH7_EVENT_SEL_V 0x0000001FU -#define GPIO_EXT_ETM_CH7_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH7_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. */ -#define GPIO_EXT_ETM_CH7_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH7_EVENT_EN_M (GPIO_EXT_ETM_CH7_EVENT_EN_V << GPIO_EXT_ETM_CH7_EVENT_EN_S) -#define GPIO_EXT_ETM_CH7_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH7_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 /** GPIO_EXT_ETM_TASK_P0_CFG_REG register - * GPIO selection register 0 for ETM + * Etm Configure Register to decide which GPIO been chosen */ -#define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x158) +#define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_BASE + 0x158) /** GPIO_EXT_ETM_TASK_GPIO0_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO0.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO0_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO0_SEL_M (GPIO_EXT_ETM_TASK_GPIO0_SEL_V << GPIO_EXT_ETM_TASK_GPIO0_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO0_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO0_SEL_S 0 /** GPIO_EXT_ETM_TASK_GPIO0_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO0 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO0_EN (BIT(5)) #define GPIO_EXT_ETM_TASK_GPIO0_EN_M (GPIO_EXT_ETM_TASK_GPIO0_EN_V << GPIO_EXT_ETM_TASK_GPIO0_EN_S) #define GPIO_EXT_ETM_TASK_GPIO0_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO0_EN_S 5 /** GPIO_EXT_ETM_TASK_GPIO1_SEL : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO1.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO1_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO1_SEL_M (GPIO_EXT_ETM_TASK_GPIO1_SEL_V << GPIO_EXT_ETM_TASK_GPIO1_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO1_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO1_SEL_S 6 /** GPIO_EXT_ETM_TASK_GPIO1_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO1 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO1_EN (BIT(11)) #define GPIO_EXT_ETM_TASK_GPIO1_EN_M (GPIO_EXT_ETM_TASK_GPIO1_EN_V << GPIO_EXT_ETM_TASK_GPIO1_EN_S) #define GPIO_EXT_ETM_TASK_GPIO1_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO1_EN_S 11 /** GPIO_EXT_ETM_TASK_GPIO2_SEL : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO2.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO2_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO2_SEL_M (GPIO_EXT_ETM_TASK_GPIO2_SEL_V << GPIO_EXT_ETM_TASK_GPIO2_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO2_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO2_SEL_S 12 /** GPIO_EXT_ETM_TASK_GPIO2_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO2 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO2_EN (BIT(17)) #define GPIO_EXT_ETM_TASK_GPIO2_EN_M (GPIO_EXT_ETM_TASK_GPIO2_EN_V << GPIO_EXT_ETM_TASK_GPIO2_EN_S) #define GPIO_EXT_ETM_TASK_GPIO2_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO2_EN_S 17 /** GPIO_EXT_ETM_TASK_GPIO3_SEL : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO3.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO3_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO3_SEL_M (GPIO_EXT_ETM_TASK_GPIO3_SEL_V << GPIO_EXT_ETM_TASK_GPIO3_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO3_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO3_SEL_S 18 /** GPIO_EXT_ETM_TASK_GPIO3_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO3 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO3_EN (BIT(23)) #define GPIO_EXT_ETM_TASK_GPIO3_EN_M (GPIO_EXT_ETM_TASK_GPIO3_EN_V << GPIO_EXT_ETM_TASK_GPIO3_EN_S) #define GPIO_EXT_ETM_TASK_GPIO3_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO3_EN_S 23 /** GPIO_EXT_ETM_TASK_GPIO4_SEL : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO4.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO4_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO4_SEL_M (GPIO_EXT_ETM_TASK_GPIO4_SEL_V << GPIO_EXT_ETM_TASK_GPIO4_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO4_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO4_SEL_S 24 /** GPIO_EXT_ETM_TASK_GPIO4_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO4 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO4_EN (BIT(29)) #define GPIO_EXT_ETM_TASK_GPIO4_EN_M (GPIO_EXT_ETM_TASK_GPIO4_EN_V << GPIO_EXT_ETM_TASK_GPIO4_EN_S) @@ -395,104 +278,74 @@ extern "C" { #define GPIO_EXT_ETM_TASK_GPIO4_EN_S 29 /** GPIO_EXT_ETM_TASK_P1_CFG_REG register - * GPIO selection register 1 for ETM + * Etm Configure Register to decide which GPIO been chosen */ -#define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x15c) +#define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_BASE + 0x15c) /** GPIO_EXT_ETM_TASK_GPIO5_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO5.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO5_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO5_SEL_M (GPIO_EXT_ETM_TASK_GPIO5_SEL_V << GPIO_EXT_ETM_TASK_GPIO5_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO5_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO5_SEL_S 0 /** GPIO_EXT_ETM_TASK_GPIO5_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO5 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO5_EN (BIT(5)) #define GPIO_EXT_ETM_TASK_GPIO5_EN_M (GPIO_EXT_ETM_TASK_GPIO5_EN_V << GPIO_EXT_ETM_TASK_GPIO5_EN_S) #define GPIO_EXT_ETM_TASK_GPIO5_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO5_EN_S 5 /** GPIO_EXT_ETM_TASK_GPIO6_SEL : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO6.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO6_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO6_SEL_M (GPIO_EXT_ETM_TASK_GPIO6_SEL_V << GPIO_EXT_ETM_TASK_GPIO6_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO6_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO6_SEL_S 6 /** GPIO_EXT_ETM_TASK_GPIO6_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO6 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO6_EN (BIT(11)) #define GPIO_EXT_ETM_TASK_GPIO6_EN_M (GPIO_EXT_ETM_TASK_GPIO6_EN_V << GPIO_EXT_ETM_TASK_GPIO6_EN_S) #define GPIO_EXT_ETM_TASK_GPIO6_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO6_EN_S 11 /** GPIO_EXT_ETM_TASK_GPIO7_SEL : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO7.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO7_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO7_SEL_M (GPIO_EXT_ETM_TASK_GPIO7_SEL_V << GPIO_EXT_ETM_TASK_GPIO7_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO7_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO7_SEL_S 12 /** GPIO_EXT_ETM_TASK_GPIO7_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO7 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO7_EN (BIT(17)) #define GPIO_EXT_ETM_TASK_GPIO7_EN_M (GPIO_EXT_ETM_TASK_GPIO7_EN_V << GPIO_EXT_ETM_TASK_GPIO7_EN_S) #define GPIO_EXT_ETM_TASK_GPIO7_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO7_EN_S 17 /** GPIO_EXT_ETM_TASK_GPIO8_SEL : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO8.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO8_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO8_SEL_M (GPIO_EXT_ETM_TASK_GPIO8_SEL_V << GPIO_EXT_ETM_TASK_GPIO8_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO8_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO8_SEL_S 18 /** GPIO_EXT_ETM_TASK_GPIO8_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO8 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO8_EN (BIT(23)) #define GPIO_EXT_ETM_TASK_GPIO8_EN_M (GPIO_EXT_ETM_TASK_GPIO8_EN_V << GPIO_EXT_ETM_TASK_GPIO8_EN_S) #define GPIO_EXT_ETM_TASK_GPIO8_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO8_EN_S 23 /** GPIO_EXT_ETM_TASK_GPIO9_SEL : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO9.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO9_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO9_SEL_M (GPIO_EXT_ETM_TASK_GPIO9_SEL_V << GPIO_EXT_ETM_TASK_GPIO9_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO9_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO9_SEL_S 24 /** GPIO_EXT_ETM_TASK_GPIO9_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO9 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO9_EN (BIT(29)) #define GPIO_EXT_ETM_TASK_GPIO9_EN_M (GPIO_EXT_ETM_TASK_GPIO9_EN_V << GPIO_EXT_ETM_TASK_GPIO9_EN_S) @@ -500,104 +353,74 @@ extern "C" { #define GPIO_EXT_ETM_TASK_GPIO9_EN_S 29 /** GPIO_EXT_ETM_TASK_P2_CFG_REG register - * GPIO selection register 2 for ETM + * Etm Configure Register to decide which GPIO been chosen */ -#define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x160) +#define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_BASE + 0x160) /** GPIO_EXT_ETM_TASK_GPIO10_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO10.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO10_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO10_SEL_M (GPIO_EXT_ETM_TASK_GPIO10_SEL_V << GPIO_EXT_ETM_TASK_GPIO10_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO10_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO10_SEL_S 0 /** GPIO_EXT_ETM_TASK_GPIO10_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO10 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO10_EN (BIT(5)) #define GPIO_EXT_ETM_TASK_GPIO10_EN_M (GPIO_EXT_ETM_TASK_GPIO10_EN_V << GPIO_EXT_ETM_TASK_GPIO10_EN_S) #define GPIO_EXT_ETM_TASK_GPIO10_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO10_EN_S 5 /** GPIO_EXT_ETM_TASK_GPIO11_SEL : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO11.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO11_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO11_SEL_M (GPIO_EXT_ETM_TASK_GPIO11_SEL_V << GPIO_EXT_ETM_TASK_GPIO11_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO11_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO11_SEL_S 6 /** GPIO_EXT_ETM_TASK_GPIO11_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO11 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO11_EN (BIT(11)) #define GPIO_EXT_ETM_TASK_GPIO11_EN_M (GPIO_EXT_ETM_TASK_GPIO11_EN_V << GPIO_EXT_ETM_TASK_GPIO11_EN_S) #define GPIO_EXT_ETM_TASK_GPIO11_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO11_EN_S 11 /** GPIO_EXT_ETM_TASK_GPIO12_SEL : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO12.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO12_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO12_SEL_M (GPIO_EXT_ETM_TASK_GPIO12_SEL_V << GPIO_EXT_ETM_TASK_GPIO12_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO12_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO12_SEL_S 12 /** GPIO_EXT_ETM_TASK_GPIO12_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO12 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO12_EN (BIT(17)) #define GPIO_EXT_ETM_TASK_GPIO12_EN_M (GPIO_EXT_ETM_TASK_GPIO12_EN_V << GPIO_EXT_ETM_TASK_GPIO12_EN_S) #define GPIO_EXT_ETM_TASK_GPIO12_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO12_EN_S 17 /** GPIO_EXT_ETM_TASK_GPIO13_SEL : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO13.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO13_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO13_SEL_M (GPIO_EXT_ETM_TASK_GPIO13_SEL_V << GPIO_EXT_ETM_TASK_GPIO13_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO13_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO13_SEL_S 18 /** GPIO_EXT_ETM_TASK_GPIO13_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO13 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO13_EN (BIT(23)) #define GPIO_EXT_ETM_TASK_GPIO13_EN_M (GPIO_EXT_ETM_TASK_GPIO13_EN_V << GPIO_EXT_ETM_TASK_GPIO13_EN_S) #define GPIO_EXT_ETM_TASK_GPIO13_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO13_EN_S 23 /** GPIO_EXT_ETM_TASK_GPIO14_SEL : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO14.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO14_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO14_SEL_M (GPIO_EXT_ETM_TASK_GPIO14_SEL_V << GPIO_EXT_ETM_TASK_GPIO14_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO14_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO14_SEL_S 24 /** GPIO_EXT_ETM_TASK_GPIO14_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO14 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO14_EN (BIT(29)) #define GPIO_EXT_ETM_TASK_GPIO14_EN_M (GPIO_EXT_ETM_TASK_GPIO14_EN_V << GPIO_EXT_ETM_TASK_GPIO14_EN_S) @@ -605,104 +428,74 @@ extern "C" { #define GPIO_EXT_ETM_TASK_GPIO14_EN_S 29 /** GPIO_EXT_ETM_TASK_P3_CFG_REG register - * GPIO selection register 3 for ETM + * Etm Configure Register to decide which GPIO been chosen */ -#define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x164) +#define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_BASE + 0x164) /** GPIO_EXT_ETM_TASK_GPIO15_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO15.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO15_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO15_SEL_M (GPIO_EXT_ETM_TASK_GPIO15_SEL_V << GPIO_EXT_ETM_TASK_GPIO15_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO15_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO15_SEL_S 0 /** GPIO_EXT_ETM_TASK_GPIO15_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO15 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO15_EN (BIT(5)) #define GPIO_EXT_ETM_TASK_GPIO15_EN_M (GPIO_EXT_ETM_TASK_GPIO15_EN_V << GPIO_EXT_ETM_TASK_GPIO15_EN_S) #define GPIO_EXT_ETM_TASK_GPIO15_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO15_EN_S 5 /** GPIO_EXT_ETM_TASK_GPIO16_SEL : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO16.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO16_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO16_SEL_M (GPIO_EXT_ETM_TASK_GPIO16_SEL_V << GPIO_EXT_ETM_TASK_GPIO16_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO16_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO16_SEL_S 6 /** GPIO_EXT_ETM_TASK_GPIO16_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO16 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO16_EN (BIT(11)) #define GPIO_EXT_ETM_TASK_GPIO16_EN_M (GPIO_EXT_ETM_TASK_GPIO16_EN_V << GPIO_EXT_ETM_TASK_GPIO16_EN_S) #define GPIO_EXT_ETM_TASK_GPIO16_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO16_EN_S 11 /** GPIO_EXT_ETM_TASK_GPIO17_SEL : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO17.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO17_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO17_SEL_M (GPIO_EXT_ETM_TASK_GPIO17_SEL_V << GPIO_EXT_ETM_TASK_GPIO17_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO17_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO17_SEL_S 12 /** GPIO_EXT_ETM_TASK_GPIO17_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO17 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO17_EN (BIT(17)) #define GPIO_EXT_ETM_TASK_GPIO17_EN_M (GPIO_EXT_ETM_TASK_GPIO17_EN_V << GPIO_EXT_ETM_TASK_GPIO17_EN_S) #define GPIO_EXT_ETM_TASK_GPIO17_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO17_EN_S 17 /** GPIO_EXT_ETM_TASK_GPIO18_SEL : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO18.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO18_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO18_SEL_M (GPIO_EXT_ETM_TASK_GPIO18_SEL_V << GPIO_EXT_ETM_TASK_GPIO18_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO18_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO18_SEL_S 18 /** GPIO_EXT_ETM_TASK_GPIO18_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO18 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO18_EN (BIT(23)) #define GPIO_EXT_ETM_TASK_GPIO18_EN_M (GPIO_EXT_ETM_TASK_GPIO18_EN_V << GPIO_EXT_ETM_TASK_GPIO18_EN_S) #define GPIO_EXT_ETM_TASK_GPIO18_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO18_EN_S 23 /** GPIO_EXT_ETM_TASK_GPIO19_SEL : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO19.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO19_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO19_SEL_M (GPIO_EXT_ETM_TASK_GPIO19_SEL_V << GPIO_EXT_ETM_TASK_GPIO19_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO19_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO19_SEL_S 24 /** GPIO_EXT_ETM_TASK_GPIO19_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO19 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO19_EN (BIT(29)) #define GPIO_EXT_ETM_TASK_GPIO19_EN_M (GPIO_EXT_ETM_TASK_GPIO19_EN_V << GPIO_EXT_ETM_TASK_GPIO19_EN_S) @@ -710,114 +503,159 @@ extern "C" { #define GPIO_EXT_ETM_TASK_GPIO19_EN_S 29 /** GPIO_EXT_ETM_TASK_P4_CFG_REG register - * GPIO selection register 4 for ETM + * Etm Configure Register to decide which GPIO been chosen */ -#define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x168) +#define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_BASE + 0x168) /** GPIO_EXT_ETM_TASK_GPIO20_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO20.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO20_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO20_SEL_M (GPIO_EXT_ETM_TASK_GPIO20_SEL_V << GPIO_EXT_ETM_TASK_GPIO20_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO20_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO20_SEL_S 0 /** GPIO_EXT_ETM_TASK_GPIO20_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO20 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO20_EN (BIT(5)) #define GPIO_EXT_ETM_TASK_GPIO20_EN_M (GPIO_EXT_ETM_TASK_GPIO20_EN_V << GPIO_EXT_ETM_TASK_GPIO20_EN_S) #define GPIO_EXT_ETM_TASK_GPIO20_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO20_EN_S 5 /** GPIO_EXT_ETM_TASK_GPIO21_SEL : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO21.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO21_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO21_SEL_M (GPIO_EXT_ETM_TASK_GPIO21_SEL_V << GPIO_EXT_ETM_TASK_GPIO21_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO21_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO21_SEL_S 6 /** GPIO_EXT_ETM_TASK_GPIO21_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO21 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO21_EN (BIT(11)) #define GPIO_EXT_ETM_TASK_GPIO21_EN_M (GPIO_EXT_ETM_TASK_GPIO21_EN_V << GPIO_EXT_ETM_TASK_GPIO21_EN_S) #define GPIO_EXT_ETM_TASK_GPIO21_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO21_EN_S 11 /** GPIO_EXT_ETM_TASK_GPIO22_SEL : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO22.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO22_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO22_SEL_M (GPIO_EXT_ETM_TASK_GPIO22_SEL_V << GPIO_EXT_ETM_TASK_GPIO22_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO22_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO22_SEL_S 12 /** GPIO_EXT_ETM_TASK_GPIO22_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO22 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO22_EN (BIT(17)) #define GPIO_EXT_ETM_TASK_GPIO22_EN_M (GPIO_EXT_ETM_TASK_GPIO22_EN_V << GPIO_EXT_ETM_TASK_GPIO22_EN_S) #define GPIO_EXT_ETM_TASK_GPIO22_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO22_EN_S 17 /** GPIO_EXT_ETM_TASK_GPIO23_SEL : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO23.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO23_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO23_SEL_M (GPIO_EXT_ETM_TASK_GPIO23_SEL_V << GPIO_EXT_ETM_TASK_GPIO23_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO23_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO23_SEL_S 18 /** GPIO_EXT_ETM_TASK_GPIO23_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO23 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO23_EN (BIT(23)) #define GPIO_EXT_ETM_TASK_GPIO23_EN_M (GPIO_EXT_ETM_TASK_GPIO23_EN_V << GPIO_EXT_ETM_TASK_GPIO23_EN_S) #define GPIO_EXT_ETM_TASK_GPIO23_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO23_EN_S 23 /** GPIO_EXT_ETM_TASK_GPIO24_SEL : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO24.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO24_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO24_SEL_M (GPIO_EXT_ETM_TASK_GPIO24_SEL_V << GPIO_EXT_ETM_TASK_GPIO24_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO24_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO24_SEL_S 24 /** GPIO_EXT_ETM_TASK_GPIO24_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO24 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO24_EN (BIT(29)) #define GPIO_EXT_ETM_TASK_GPIO24_EN_M (GPIO_EXT_ETM_TASK_GPIO24_EN_V << GPIO_EXT_ETM_TASK_GPIO24_EN_S) #define GPIO_EXT_ETM_TASK_GPIO24_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO24_EN_S 29 +/** GPIO_EXT_ETM_TASK_P5_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_EXT_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_BASE + 0x16c) +/** GPIO_EXT_ETM_TASK_GPIO25_SEL : R/W; bitpos: [2:0]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO25_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO25_SEL_M (GPIO_EXT_ETM_TASK_GPIO25_SEL_V << GPIO_EXT_ETM_TASK_GPIO25_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO25_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO25_SEL_S 0 +/** GPIO_EXT_ETM_TASK_GPIO25_EN : R/W; bitpos: [5]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO25_EN (BIT(5)) +#define GPIO_EXT_ETM_TASK_GPIO25_EN_M (GPIO_EXT_ETM_TASK_GPIO25_EN_V << GPIO_EXT_ETM_TASK_GPIO25_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO25_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO25_EN_S 5 +/** GPIO_EXT_ETM_TASK_GPIO26_SEL : R/W; bitpos: [8:6]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO26_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO26_SEL_M (GPIO_EXT_ETM_TASK_GPIO26_SEL_V << GPIO_EXT_ETM_TASK_GPIO26_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO26_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO26_SEL_S 6 +/** GPIO_EXT_ETM_TASK_GPIO26_EN : R/W; bitpos: [11]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO26_EN (BIT(11)) +#define GPIO_EXT_ETM_TASK_GPIO26_EN_M (GPIO_EXT_ETM_TASK_GPIO26_EN_V << GPIO_EXT_ETM_TASK_GPIO26_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO26_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO26_EN_S 11 +/** GPIO_EXT_ETM_TASK_GPIO27_SEL : R/W; bitpos: [14:12]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO27_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO27_SEL_M (GPIO_EXT_ETM_TASK_GPIO27_SEL_V << GPIO_EXT_ETM_TASK_GPIO27_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO27_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO27_SEL_S 12 +/** GPIO_EXT_ETM_TASK_GPIO27_EN : R/W; bitpos: [17]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO27_EN (BIT(17)) +#define GPIO_EXT_ETM_TASK_GPIO27_EN_M (GPIO_EXT_ETM_TASK_GPIO27_EN_V << GPIO_EXT_ETM_TASK_GPIO27_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO27_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO27_EN_S 17 +/** GPIO_EXT_ETM_TASK_GPIO28_SEL : R/W; bitpos: [20:18]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO28_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO28_SEL_M (GPIO_EXT_ETM_TASK_GPIO28_SEL_V << GPIO_EXT_ETM_TASK_GPIO28_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO28_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO28_SEL_S 18 +/** GPIO_EXT_ETM_TASK_GPIO28_EN : R/W; bitpos: [23]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO28_EN (BIT(23)) +#define GPIO_EXT_ETM_TASK_GPIO28_EN_M (GPIO_EXT_ETM_TASK_GPIO28_EN_V << GPIO_EXT_ETM_TASK_GPIO28_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO28_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO28_EN_S 23 +/** GPIO_EXT_ETM_TASK_GPIO29_SEL : R/W; bitpos: [26:24]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO29_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO29_SEL_M (GPIO_EXT_ETM_TASK_GPIO29_SEL_V << GPIO_EXT_ETM_TASK_GPIO29_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO29_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO29_SEL_S 24 +/** GPIO_EXT_ETM_TASK_GPIO29_EN : R/W; bitpos: [29]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO29_EN (BIT(29)) +#define GPIO_EXT_ETM_TASK_GPIO29_EN_M (GPIO_EXT_ETM_TASK_GPIO29_EN_V << GPIO_EXT_ETM_TASK_GPIO29_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO29_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO29_EN_S 29 + /** GPIO_EXT_INT_RAW_REG register * GPIO_EXT interrupt raw register */ -#define GPIO_EXT_INT_RAW_REG (DR_REG_GPIO_EXT_BASE + 0x1d0) +#define GPIO_EXT_INT_RAW_REG (DR_REG_GPIO_BASE + 0x1d0) /** GPIO_EXT_COMP_NEG_0_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; * analog comparator pos edge interrupt raw */ @@ -843,7 +681,7 @@ extern "C" { /** GPIO_EXT_INT_ST_REG register * GPIO_EXT interrupt masked register */ -#define GPIO_EXT_INT_ST_REG (DR_REG_GPIO_EXT_BASE + 0x1d4) +#define GPIO_EXT_INT_ST_REG (DR_REG_GPIO_BASE + 0x1d4) /** GPIO_EXT_COMP_NEG_0_INT_ST : RO; bitpos: [0]; default: 0; * analog comparator pos edge interrupt status */ @@ -869,7 +707,7 @@ extern "C" { /** GPIO_EXT_INT_ENA_REG register * GPIO_EXT interrupt enable register */ -#define GPIO_EXT_INT_ENA_REG (DR_REG_GPIO_EXT_BASE + 0x1d8) +#define GPIO_EXT_INT_ENA_REG (DR_REG_GPIO_BASE + 0x1d8) /** GPIO_EXT_COMP_NEG_0_INT_ENA : R/W; bitpos: [0]; default: 1; * analog comparator pos edge interrupt enable */ @@ -895,7 +733,7 @@ extern "C" { /** GPIO_EXT_INT_CLR_REG register * GPIO_EXT interrupt clear register */ -#define GPIO_EXT_INT_CLR_REG (DR_REG_GPIO_EXT_BASE + 0x1dc) +#define GPIO_EXT_INT_CLR_REG (DR_REG_GPIO_BASE + 0x1dc) /** GPIO_EXT_COMP_NEG_0_INT_CLR : WT; bitpos: [0]; default: 0; * analog comparator pos edge interrupt clear */ @@ -921,7 +759,7 @@ extern "C" { /** GPIO_EXT_PIN_CTRL_REG register * Clock Output Configuration Register */ -#define GPIO_EXT_PIN_CTRL_REG (DR_REG_GPIO_EXT_BASE + 0x1e0) +#define GPIO_EXT_PIN_CTRL_REG (DR_REG_GPIO_BASE + 0x1e0) /** GPIO_EXT_CLK_OUT1 : R/W; bitpos: [4:0]; default: 0; * If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. * CLK_OUT_out1 can be found in peripheral output signals. @@ -948,10 +786,10 @@ extern "C" { #define GPIO_EXT_CLK_OUT3_S 10 /** GPIO_EXT_VERSION_REG register - * Version control register + * Version Control Register */ -#define GPIO_EXT_VERSION_REG (DR_REG_GPIO_EXT_BASE + 0x1fc) -/** GPIO_EXT_DATE : R/W; bitpos: [27:0]; default: 37753392; +#define GPIO_EXT_VERSION_REG (DR_REG_GPIO_BASE + 0x1fc) +/** GPIO_EXT_DATE : R/W; bitpos: [27:0]; default: 37823120; * Version control register. */ #define GPIO_EXT_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c61/register/soc/gpio_ext_struct.h b/components/soc/esp32c61/register/soc/gpio_ext_struct.h index 1f7f58950e..9886bf6295 100644 --- a/components/soc/esp32c61/register/soc/gpio_ext_struct.h +++ b/components/soc/esp32c61/register/soc/gpio_ext_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,48 +10,23 @@ extern "C" { #endif -/** Group: Clock gate Register */ -/** Type of clock_gate register - * Clock Gating Configure Register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * Clock enable bit of configuration registers for sigma delta modulation. - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} gpio_ext_clock_gate_reg_t; - - /** Group: Configure Registers */ /** Type of pad_comp_config_0 register - * Configuration register for zero-crossing detection + * PAD Compare configure Register */ typedef union { struct { /** xpd_comp_0 : R/W; bitpos: [0]; default: 0; - * Configures whether to enable the function of analog PAD voltage comparator.\\ - * 0: Disable\\ - * 1: Enable\\ + * Pad compare enable bit. */ uint32_t xpd_comp_0:1; /** mode_comp_0 : R/W; bitpos: [1]; default: 0; - * Configures the reference voltage for analog PAD voltage comparator.. \\ - * 0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be - * used as a regular GPIO\\ - * 1: Reference voltage is the voltage on the GPIO8 PAD\\ + * 1 to enable external reference from PAD[x]. 0 to enable internal reference, + * meanwhile PAD[x] can be used as a regular GPIO. */ uint32_t mode_comp_0:1; /** dref_comp_0 : R/W; bitpos: [4:2]; default: 0; - * Configures the internal reference voltage for analog PAD voltage coparator. \\ - * 0: Internal reference voltage is 0 * VDDPST1\\ - * 1: Internal reference voltage is 0.1 * VDDPST1\\ - * ......\\ - * 6: Internal reference voltage is 0.6 * VDDPST1\\ - * 7: Internal reference voltage is 0.7 * VDDPST1\\ + * internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST. */ uint32_t dref_comp_0:3; uint32_t reserved_5:27; @@ -60,14 +35,12 @@ typedef union { } gpio_ext_pad_comp_config_0_reg_t; /** Type of pad_comp_filter_0 register - * Configuration register for interrupt source mask period of zero-crossing detection + * Zero Detect filter Register */ typedef union { struct { /** zero_det_filter_cnt_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the period of masking new interrupt source foe analog PAD voltage - * comparator.\\ - * Measurement unit: IO MUX operating clock cycle\\ + * Zero Detect filter cycle length */ uint32_t zero_det_filter_cnt_0:32; }; @@ -100,27 +73,19 @@ typedef union { } gpio_ext_pin_ctrl_reg_t; -/** Group: ETM Configuration Registers */ +/** Group: Etm Configure Registers */ /** Type of etm_event_chn_cfg register - * ETM configuration register for channel 0 + * Etm Config register of Channeln */ typedef union { struct { - /** etm_chn_event_sel : R/W; bitpos: [4:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * 25 ~ 31: Reserved\\ + /** etm_chn_event_sel : R/W; bitpos: [5:0]; default: 0; + * Etm event channel select gpio. */ - uint32_t etm_chn_event_sel:5; - uint32_t reserved_5:2; + uint32_t etm_chn_event_sel:6; + uint32_t reserved_6:1; /** etm_chn_event_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Etm event send enable bit. */ uint32_t etm_chn_event_en:1; uint32_t reserved_8:24; @@ -129,177 +94,108 @@ typedef union { } gpio_ext_etm_event_chn_cfg_reg_t; /** Type of etm_task_pn_cfg register - * GPIO selection register for ETM. - * This register is an abstraction of the following registers: - * gpio_ext_etm_task_p0_cfg_reg_t ~ gpio_ext_etm_task_p4_cfg_reg_t - */ -typedef union { - uint32_t val; -} gpio_ext_etm_task_pn_cfg_reg_t; - -/** Type of etm_task_p0_cfg register - * GPIO selection register 0 for ETM + * Etm Configure Register to decide which GPIO been chosen */ typedef union { struct { /** etm_task_gpio0_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO0.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio0_sel:3; uint32_t reserved_3:2; /** etm_task_gpio0_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO0 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio0_en:1; /** etm_task_gpio1_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO1.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio1_sel:3; uint32_t reserved_9:2; /** etm_task_gpio1_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO1 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio1_en:1; /** etm_task_gpio2_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO2.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio2_sel:3; uint32_t reserved_15:2; /** etm_task_gpio2_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO2 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio2_en:1; /** etm_task_gpio3_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO3.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio3_sel:3; uint32_t reserved_21:2; /** etm_task_gpio3_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO3 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio3_en:1; /** etm_task_gpio4_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO4.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio4_sel:3; uint32_t reserved_27:2; /** etm_task_gpio4_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO4 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio4_en:1; uint32_t reserved_30:2; }; uint32_t val; -} gpio_ext_etm_task_p0_cfg_reg_t; +} gpio_ext_etm_task_pn_cfg_reg_t; /** Type of etm_task_p1_cfg register - * GPIO selection register 1 for ETM + * Etm Configure Register to decide which GPIO been chosen */ typedef union { struct { /** etm_task_gpio5_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO5.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio5_sel:3; uint32_t reserved_3:2; /** etm_task_gpio5_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO5 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio5_en:1; /** etm_task_gpio6_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO6.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio6_sel:3; uint32_t reserved_9:2; /** etm_task_gpio6_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO6 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio6_en:1; /** etm_task_gpio7_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO7.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio7_sel:3; uint32_t reserved_15:2; /** etm_task_gpio7_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO7 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio7_en:1; /** etm_task_gpio8_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO8.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio8_sel:3; uint32_t reserved_21:2; /** etm_task_gpio8_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO8 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio8_en:1; /** etm_task_gpio9_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO9.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio9_sel:3; uint32_t reserved_27:2; /** etm_task_gpio9_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO9 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio9_en:1; uint32_t reserved_30:2; @@ -308,83 +204,53 @@ typedef union { } gpio_ext_etm_task_p1_cfg_reg_t; /** Type of etm_task_p2_cfg register - * GPIO selection register 2 for ETM + * Etm Configure Register to decide which GPIO been chosen */ typedef union { struct { /** etm_task_gpio10_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO10.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio10_sel:3; uint32_t reserved_3:2; /** etm_task_gpio10_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO10 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio10_en:1; /** etm_task_gpio11_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO11.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio11_sel:3; uint32_t reserved_9:2; /** etm_task_gpio11_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO11 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio11_en:1; /** etm_task_gpio12_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO12.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio12_sel:3; uint32_t reserved_15:2; /** etm_task_gpio12_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO12 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio12_en:1; /** etm_task_gpio13_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO13.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio13_sel:3; uint32_t reserved_21:2; /** etm_task_gpio13_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO13 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio13_en:1; /** etm_task_gpio14_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO14.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio14_sel:3; uint32_t reserved_27:2; /** etm_task_gpio14_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO14 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio14_en:1; uint32_t reserved_30:2; @@ -393,83 +259,53 @@ typedef union { } gpio_ext_etm_task_p2_cfg_reg_t; /** Type of etm_task_p3_cfg register - * GPIO selection register 3 for ETM + * Etm Configure Register to decide which GPIO been chosen */ typedef union { struct { /** etm_task_gpio15_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO15.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio15_sel:3; uint32_t reserved_3:2; /** etm_task_gpio15_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO15 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio15_en:1; /** etm_task_gpio16_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO16.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio16_sel:3; uint32_t reserved_9:2; /** etm_task_gpio16_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO16 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio16_en:1; /** etm_task_gpio17_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO17.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio17_sel:3; uint32_t reserved_15:2; /** etm_task_gpio17_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO17 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio17_en:1; /** etm_task_gpio18_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO18.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio18_sel:3; uint32_t reserved_21:2; /** etm_task_gpio18_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO18 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio18_en:1; /** etm_task_gpio19_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO19.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio19_sel:3; uint32_t reserved_27:2; /** etm_task_gpio19_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO19 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio19_en:1; uint32_t reserved_30:2; @@ -478,83 +314,53 @@ typedef union { } gpio_ext_etm_task_p3_cfg_reg_t; /** Type of etm_task_p4_cfg register - * GPIO selection register 4 for ETM + * Etm Configure Register to decide which GPIO been chosen */ typedef union { struct { /** etm_task_gpio20_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO20.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio20_sel:3; uint32_t reserved_3:2; /** etm_task_gpio20_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO20 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio20_en:1; /** etm_task_gpio21_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO21.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio21_sel:3; uint32_t reserved_9:2; /** etm_task_gpio21_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO21 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio21_en:1; /** etm_task_gpio22_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO22.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio22_sel:3; uint32_t reserved_15:2; /** etm_task_gpio22_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO22 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio22_en:1; /** etm_task_gpio23_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO23.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio23_sel:3; uint32_t reserved_21:2; /** etm_task_gpio23_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO23 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio23_en:1; /** etm_task_gpio24_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO24.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio24_sel:3; uint32_t reserved_27:2; /** etm_task_gpio24_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO24 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio24_en:1; uint32_t reserved_30:2; @@ -562,6 +368,61 @@ typedef union { uint32_t val; } gpio_ext_etm_task_p4_cfg_reg_t; +/** Type of etm_task_p5_cfg register + * Etm Configure Register to decide which GPIO been chosen + */ +typedef union { + struct { + /** etm_task_gpio25_sel : R/W; bitpos: [2:0]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio25_sel:3; + uint32_t reserved_3:2; + /** etm_task_gpio25_en : R/W; bitpos: [5]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio25_en:1; + /** etm_task_gpio26_sel : R/W; bitpos: [8:6]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio26_sel:3; + uint32_t reserved_9:2; + /** etm_task_gpio26_en : R/W; bitpos: [11]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio26_en:1; + /** etm_task_gpio27_sel : R/W; bitpos: [14:12]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio27_sel:3; + uint32_t reserved_15:2; + /** etm_task_gpio27_en : R/W; bitpos: [17]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio27_en:1; + /** etm_task_gpio28_sel : R/W; bitpos: [20:18]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio28_sel:3; + uint32_t reserved_21:2; + /** etm_task_gpio28_en : R/W; bitpos: [23]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio28_en:1; + /** etm_task_gpio29_sel : R/W; bitpos: [26:24]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio29_sel:3; + uint32_t reserved_27:2; + /** etm_task_gpio29_en : R/W; bitpos: [29]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio29_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_ext_etm_task_p5_cfg_reg_t; + /** Group: Interrupt Registers */ /** Type of int_raw register @@ -655,11 +516,11 @@ typedef union { /** Group: Version Register */ /** Type of version register - * Version control register + * Version Control Register */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 37753392; + /** date : R/W; bitpos: [27:0]; default: 37823120; * Version control register. */ uint32_t date:28; @@ -670,18 +531,17 @@ typedef union { typedef struct gpio_etm_dev_t { volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; - uint32_t reserved_138[8]; - volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[5]; + uint32_t reserved_080[8]; + volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[6]; } gpio_etm_dev_t; typedef struct { - volatile gpio_ext_clock_gate_reg_t clock_gate; - uint32_t reserved_004[21]; + uint32_t reserved_000[22]; volatile gpio_ext_pad_comp_config_0_reg_t pad_comp_config_0; volatile gpio_ext_pad_comp_filter_0_reg_t pad_comp_filter_0; uint32_t reserved_060[46]; volatile gpio_etm_dev_t etm; - uint32_t reserved_16c[25]; + uint32_t reserved_170[24]; volatile gpio_ext_int_raw_reg_t int_raw; volatile gpio_ext_int_st_reg_t int_st; volatile gpio_ext_int_ena_reg_t int_ena; diff --git a/components/soc/esp32c61/register/soc/gpio_reg.h b/components/soc/esp32c61/register/soc/gpio_reg.h index f9eaeac424..af5013c93f 100644 --- a/components/soc/esp32c61/register/soc/gpio_reg.h +++ b/components/soc/esp32c61/register/soc/gpio_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,17 +12,11 @@ extern "C" { #endif /** GPIO_STRAP_REG register - * Strapping pin register + * pad strapping register */ #define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0) /** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0; - * Represents the values of GPIO strapping pins. - * - * - bit0 ~ bit1: invalid - * - bit2: GPIO8 - * - bit3: GPIO9 - * - bit4: GPIO7 - * - bit5 ~ bit15: invalid + * pad strapping register */ #define GPIO_STRAPPING 0x0000FFFFU #define GPIO_STRAPPING_M (GPIO_STRAPPING_V << GPIO_STRAPPING_S) @@ -30,281 +24,362 @@ extern "C" { #define GPIO_STRAPPING_S 0 /** GPIO_OUT_REG register - * GPIO output register + * GPIO output register for GPIO0-31 */ #define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) -/** GPIO_OUT_DATA_ORIG : R/W/SC/WTC; bitpos: [28:0]; default: 0; - * Configures the output value of GPIO0 ~ 24 output in simple GPIO output mode.\\ - * 0: Low level\\ - * 1: High level\\ - * The value of bit0 ~ bit24 correspond to the output value of GPIO0 ~ GPIO24 - * respectively. Bit25 ~ bit31 are invalid.\\ +/** GPIO_OUT_DATA_ORIG : R/W/SC/WTC; bitpos: [31:0]; default: 0; + * GPIO output register for GPIO0-31 */ -#define GPIO_OUT_DATA_ORIG 0x1FFFFFFFU +#define GPIO_OUT_DATA_ORIG 0xFFFFFFFFU #define GPIO_OUT_DATA_ORIG_M (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S) -#define GPIO_OUT_DATA_ORIG_V 0x1FFFFFFFU +#define GPIO_OUT_DATA_ORIG_V 0xFFFFFFFFU #define GPIO_OUT_DATA_ORIG_S 0 /** GPIO_OUT_W1TS_REG register - * GPIO output set register + * GPIO output set register for GPIO0-31 */ #define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) -/** GPIO_OUT_W1TS : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~ - * GPIO24.\\ - * 0: Not set\\ - * 1: The corresponding bit in GPIO_OUT_REG will be set to 1\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ - * Recommended operation: use this register to set GPIO_OUT_REG. \\ +/** GPIO_OUT_W1TS : WT; bitpos: [31:0]; default: 0; + * GPIO output set register for GPIO0-31 */ -#define GPIO_OUT_W1TS 0x1FFFFFFFU +#define GPIO_OUT_W1TS 0xFFFFFFFFU #define GPIO_OUT_W1TS_M (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S) -#define GPIO_OUT_W1TS_V 0x1FFFFFFFU +#define GPIO_OUT_W1TS_V 0xFFFFFFFFU #define GPIO_OUT_W1TS_S 0 /** GPIO_OUT_W1TC_REG register - * GPIO output clear register + * GPIO output clear register for GPIO0-31 */ #define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc) -/** GPIO_OUT_W1TC : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0 ~ - * GPIO24 output.\\ - * 0: Not clear\\ - * 1: The corresponding bit in GPIO_OUT_REG will be cleared.\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ - * Recommended operation: use this register to clear GPIO_OUT_REG. \\ +/** GPIO_OUT_W1TC : WT; bitpos: [31:0]; default: 0; + * GPIO output clear register for GPIO0-31 */ -#define GPIO_OUT_W1TC 0x1FFFFFFFU +#define GPIO_OUT_W1TC 0xFFFFFFFFU #define GPIO_OUT_W1TC_M (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S) -#define GPIO_OUT_W1TC_V 0x1FFFFFFFU +#define GPIO_OUT_W1TC_V 0xFFFFFFFFU #define GPIO_OUT_W1TC_S 0 +/** GPIO_OUT1_REG register + * GPIO output register for GPIO32-33 + */ +#define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x10) +/** GPIO_OUT1_DATA_ORIG : R/W/SC/WTC; bitpos: [1:0]; default: 0; + * GPIO output register for GPIO32-33 + */ +#define GPIO_OUT1_DATA_ORIG 0x00000003U +#define GPIO_OUT1_DATA_ORIG_M (GPIO_OUT1_DATA_ORIG_V << GPIO_OUT1_DATA_ORIG_S) +#define GPIO_OUT1_DATA_ORIG_V 0x00000003U +#define GPIO_OUT1_DATA_ORIG_S 0 + +/** GPIO_OUT1_W1TS_REG register + * GPIO output set register for GPIO32-33 + */ +#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x14) +/** GPIO_OUT1_W1TS : WT; bitpos: [1:0]; default: 0; + * GPIO output set register for GPIO32-33 + */ +#define GPIO_OUT1_W1TS 0x00000003U +#define GPIO_OUT1_W1TS_M (GPIO_OUT1_W1TS_V << GPIO_OUT1_W1TS_S) +#define GPIO_OUT1_W1TS_V 0x00000003U +#define GPIO_OUT1_W1TS_S 0 + +/** GPIO_OUT1_W1TC_REG register + * GPIO output clear register for GPIO32-33 + */ +#define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x18) +/** GPIO_OUT1_W1TC : WT; bitpos: [1:0]; default: 0; + * GPIO output clear register for GPIO32-33 + */ +#define GPIO_OUT1_W1TC 0x00000003U +#define GPIO_OUT1_W1TC_M (GPIO_OUT1_W1TC_V << GPIO_OUT1_W1TC_S) +#define GPIO_OUT1_W1TC_V 0x00000003U +#define GPIO_OUT1_W1TC_S 0 + /** GPIO_ENABLE_REG register - * GPIO output enable register + * GPIO output enable register for GPIO0-31 */ #define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x34) -/** GPIO_ENABLE_DATA : R/W/WTC; bitpos: [28:0]; default: 0; - * Configures whether or not to enable the output of GPIO0 ~ GPIO24.\\ - * 0: Not enable\\ - * 1: Enable\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\ +/** GPIO_ENABLE_DATA : R/W/WTC; bitpos: [31:0]; default: 0; + * GPIO output enable register for GPIO0-31 */ -#define GPIO_ENABLE_DATA 0x1FFFFFFFU +#define GPIO_ENABLE_DATA 0xFFFFFFFFU #define GPIO_ENABLE_DATA_M (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S) -#define GPIO_ENABLE_DATA_V 0x1FFFFFFFU +#define GPIO_ENABLE_DATA_V 0xFFFFFFFFU #define GPIO_ENABLE_DATA_S 0 /** GPIO_ENABLE_W1TS_REG register - * GPIO output enable set register + * GPIO output enable set register for GPIO0-31 */ #define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x38) -/** GPIO_ENABLE_W1TS : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to set the output enable register GPIO_ENABLE_REG of - * GPIO0 ~ GPIO24.\\ - * 0: Not set\\ - * 1: The corresponding bit in GPIO_ENABLE_REG will be set to 1\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ - * Recommended operation: use this register to set GPIO_ENABLE_REG.\\ +/** GPIO_ENABLE_W1TS : WT; bitpos: [31:0]; default: 0; + * GPIO output enable set register for GPIO0-31 */ -#define GPIO_ENABLE_W1TS 0x1FFFFFFFU +#define GPIO_ENABLE_W1TS 0xFFFFFFFFU #define GPIO_ENABLE_W1TS_M (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S) -#define GPIO_ENABLE_W1TS_V 0x1FFFFFFFU +#define GPIO_ENABLE_W1TS_V 0xFFFFFFFFU #define GPIO_ENABLE_W1TS_S 0 /** GPIO_ENABLE_W1TC_REG register - * GPIO output enable clear register + * GPIO output enable clear register for GPIO0-31 */ #define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x3c) -/** GPIO_ENABLE_W1TC : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to clear the output enable register GPIO_ENABLE_REG of - * GPIO0 ~ GPIO24. \\ - * 0: Not clear\\ - * 1: The corresponding bit in GPIO_ENABLE_REG will be cleared\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ - * Recommended operation: use this register to clear GPIO_ENABLE_REG.\\ +/** GPIO_ENABLE_W1TC : WT; bitpos: [31:0]; default: 0; + * GPIO output enable clear register for GPIO0-31 */ -#define GPIO_ENABLE_W1TC 0x1FFFFFFFU +#define GPIO_ENABLE_W1TC 0xFFFFFFFFU #define GPIO_ENABLE_W1TC_M (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S) -#define GPIO_ENABLE_W1TC_V 0x1FFFFFFFU +#define GPIO_ENABLE_W1TC_V 0xFFFFFFFFU #define GPIO_ENABLE_W1TC_S 0 +/** GPIO_ENABLE1_REG register + * GPIO output enable register for GPIO32-33 + */ +#define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x40) +/** GPIO_ENABLE1_DATA : R/W/WTC; bitpos: [1:0]; default: 0; + * GPIO output enable register for GPIO32-33 + */ +#define GPIO_ENABLE1_DATA 0x00000003U +#define GPIO_ENABLE1_DATA_M (GPIO_ENABLE1_DATA_V << GPIO_ENABLE1_DATA_S) +#define GPIO_ENABLE1_DATA_V 0x00000003U +#define GPIO_ENABLE1_DATA_S 0 + +/** GPIO_ENABLE1_W1TS_REG register + * GPIO output enable set register for GPIO32-33 + */ +#define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x44) +/** GPIO_ENABLE1_W1TS : WT; bitpos: [1:0]; default: 0; + * GPIO output enable set register for GPIO32-33 + */ +#define GPIO_ENABLE1_W1TS 0x00000003U +#define GPIO_ENABLE1_W1TS_M (GPIO_ENABLE1_W1TS_V << GPIO_ENABLE1_W1TS_S) +#define GPIO_ENABLE1_W1TS_V 0x00000003U +#define GPIO_ENABLE1_W1TS_S 0 + +/** GPIO_ENABLE1_W1TC_REG register + * GPIO output enable clear register for GPIO32-33 + */ +#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x48) +/** GPIO_ENABLE1_W1TC : WT; bitpos: [1:0]; default: 0; + * GPIO output enable clear register for GPIO32-33 + */ +#define GPIO_ENABLE1_W1TC 0x00000003U +#define GPIO_ENABLE1_W1TC_M (GPIO_ENABLE1_W1TC_V << GPIO_ENABLE1_W1TC_S) +#define GPIO_ENABLE1_W1TC_V 0x00000003U +#define GPIO_ENABLE1_W1TC_S 0 + /** GPIO_IN_REG register - * GPIO input register + * GPIO input register for GPIO0-31 */ #define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x64) -/** GPIO_IN_DATA_NEXT : RO; bitpos: [28:0]; default: 0; - * Represents the input value of GPIO0 ~ GPIO24. Each bit represents a pin input - * value:\\ - * 0: Low level\\ - * 1: High level\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\ +/** GPIO_IN_DATA_NEXT : RO; bitpos: [31:0]; default: 0; + * GPIO input register for GPIO0-31 */ -#define GPIO_IN_DATA_NEXT 0x1FFFFFFFU +#define GPIO_IN_DATA_NEXT 0xFFFFFFFFU #define GPIO_IN_DATA_NEXT_M (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S) -#define GPIO_IN_DATA_NEXT_V 0x1FFFFFFFU +#define GPIO_IN_DATA_NEXT_V 0xFFFFFFFFU #define GPIO_IN_DATA_NEXT_S 0 +/** GPIO_IN1_REG register + * GPIO input register for GPIO32-33 + */ +#define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x68) +/** GPIO_IN1_DATA_NEXT : RO; bitpos: [1:0]; default: 0; + * GPIO input register for GPIO32-33 + */ +#define GPIO_IN1_DATA_NEXT 0x00000003U +#define GPIO_IN1_DATA_NEXT_M (GPIO_IN1_DATA_NEXT_V << GPIO_IN1_DATA_NEXT_S) +#define GPIO_IN1_DATA_NEXT_V 0x00000003U +#define GPIO_IN1_DATA_NEXT_S 0 + /** GPIO_STATUS_REG register - * GPIO interrupt status register + * GPIO interrupt status register for GPIO0-31 */ #define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x74) -/** GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [28:0]; default: 0; - * The interrupt status of GPIO0 ~ GPIO24, can be configured by the software. - * - * - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. - * - Each bit represents the status of its corresponding GPIO: - * - * - 0: Represents the GPIO does not generate the interrupt configured by - * GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software. - * - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE, - * or this bit is configured to 1 by the software. - * +/** GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [31:0]; default: 0; + * GPIO interrupt status register for GPIO0-31 */ -#define GPIO_STATUS_INTERRUPT 0x1FFFFFFFU +#define GPIO_STATUS_INTERRUPT 0xFFFFFFFFU #define GPIO_STATUS_INTERRUPT_M (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S) -#define GPIO_STATUS_INTERRUPT_V 0x1FFFFFFFU +#define GPIO_STATUS_INTERRUPT_V 0xFFFFFFFFU #define GPIO_STATUS_INTERRUPT_S 0 /** GPIO_STATUS_W1TS_REG register - * GPIO interrupt status set register + * GPIO interrupt status set register for GPIO0-31 */ #define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x78) -/** GPIO_STATUS_W1TS : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to set the interrupt status register - * GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24. - * - * - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. - * - If the value 1 is written to a bit here, the corresponding bit in - * GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this - * register to set GPIO_STATUS_INTERRUPT. +/** GPIO_STATUS_W1TS : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status set register for GPIO0-31 */ -#define GPIO_STATUS_W1TS 0x1FFFFFFFU +#define GPIO_STATUS_W1TS 0xFFFFFFFFU #define GPIO_STATUS_W1TS_M (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S) -#define GPIO_STATUS_W1TS_V 0x1FFFFFFFU +#define GPIO_STATUS_W1TS_V 0xFFFFFFFFU #define GPIO_STATUS_W1TS_S 0 /** GPIO_STATUS_W1TC_REG register - * GPIO interrupt status clear register + * GPIO interrupt status clear register for GPIO0-31 */ #define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x7c) -/** GPIO_STATUS_W1TC : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to clear the interrupt status register - * GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24. - * - * - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. - * - If the value 1 is written to a bit here, the corresponding bit in - * GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this - * register to clear GPIO_STATUS_INTERRUPT. +/** GPIO_STATUS_W1TC : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status clear register for GPIO0-31 */ -#define GPIO_STATUS_W1TC 0x1FFFFFFFU +#define GPIO_STATUS_W1TC 0xFFFFFFFFU #define GPIO_STATUS_W1TC_M (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S) -#define GPIO_STATUS_W1TC_V 0x1FFFFFFFU +#define GPIO_STATUS_W1TC_V 0xFFFFFFFFU #define GPIO_STATUS_W1TC_S 0 +/** GPIO_STATUS1_REG register + * GPIO interrupt status register for GPIO32-33 + */ +#define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x80) +/** GPIO_STATUS1_INTERRUPT : R/W/WTC; bitpos: [1:0]; default: 0; + * GPIO interrupt status register for GPIO32-33 + */ +#define GPIO_STATUS1_INTERRUPT 0x00000003U +#define GPIO_STATUS1_INTERRUPT_M (GPIO_STATUS1_INTERRUPT_V << GPIO_STATUS1_INTERRUPT_S) +#define GPIO_STATUS1_INTERRUPT_V 0x00000003U +#define GPIO_STATUS1_INTERRUPT_S 0 + +/** GPIO_STATUS1_W1TS_REG register + * GPIO interrupt status set register for GPIO32-33 + */ +#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x84) +/** GPIO_STATUS1_W1TS : WT; bitpos: [1:0]; default: 0; + * GPIO interrupt status set register for GPIO32-33 + */ +#define GPIO_STATUS1_W1TS 0x00000003U +#define GPIO_STATUS1_W1TS_M (GPIO_STATUS1_W1TS_V << GPIO_STATUS1_W1TS_S) +#define GPIO_STATUS1_W1TS_V 0x00000003U +#define GPIO_STATUS1_W1TS_S 0 + +/** GPIO_STATUS1_W1TC_REG register + * GPIO interrupt status clear register for GPIO32-33 + */ +#define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x88) +/** GPIO_STATUS1_W1TC : WT; bitpos: [1:0]; default: 0; + * GPIO interrupt status clear register for GPIO32-33 + */ +#define GPIO_STATUS1_W1TC 0x00000003U +#define GPIO_STATUS1_W1TC_M (GPIO_STATUS1_W1TC_V << GPIO_STATUS1_W1TC_S) +#define GPIO_STATUS1_W1TC_V 0x00000003U +#define GPIO_STATUS1_W1TC_S 0 + /** GPIO_PROCPU_INT_REG register - * CPU interrupt status register + * GPIO_PROCPU_INT interrupt status register for GPIO0-31 */ #define GPIO_PROCPU_INT_REG (DR_REG_GPIO_BASE + 0xa4) -/** GPIO_PROCPU_INT : RO; bitpos: [28:0]; default: 0; - * Represents the CPU interrupt status of GPIO0 ~ GPIO24. Each bit represents:\\ - * 0: Represents CPU interrupt is not enabled, or the GPIO does not generate the - * interrupt configured by GPIO_PIN$n_INT_TYPE.\\ - * 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE - * after the CPU interrupt is enabled.\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. This - * interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high) - * enable signal (bit13 of GPIO_PIN$n_REG). \\ +/** GPIO_PROCPU_INT : RO; bitpos: [31:0]; default: 0; + * GPIO_PROCPU_INT interrupt status register for GPIO0-31 */ -#define GPIO_PROCPU_INT 0x1FFFFFFFU +#define GPIO_PROCPU_INT 0xFFFFFFFFU #define GPIO_PROCPU_INT_M (GPIO_PROCPU_INT_V << GPIO_PROCPU_INT_S) -#define GPIO_PROCPU_INT_V 0x1FFFFFFFU +#define GPIO_PROCPU_INT_V 0xFFFFFFFFU #define GPIO_PROCPU_INT_S 0 +/** GPIO_SDIO_INT_REG register + * GPIO_SDIO_INT interrupt status register for GPIO0-31 + */ +#define GPIO_SDIO_INT_REG (DR_REG_GPIO_BASE + 0xa8) +/** GPIO_SDIO_INT : RO; bitpos: [31:0]; default: 0; + * GPIO_SDIO_INT interrupt status register for GPIO0-31 + */ +#define GPIO_SDIO_INT 0xFFFFFFFFU +#define GPIO_SDIO_INT_M (GPIO_SDIO_INT_V << GPIO_SDIO_INT_S) +#define GPIO_SDIO_INT_V 0xFFFFFFFFU +#define GPIO_SDIO_INT_S 0 + +/** GPIO_PROCPU_INT1_REG register + * GPIO_PROCPU_INT interrupt status register for GPIO32-33 + */ +#define GPIO_PROCPU_INT1_REG (DR_REG_GPIO_BASE + 0xac) +/** GPIO_PROCPU_INT1 : RO; bitpos: [1:0]; default: 0; + * GPIO_PROCPU_INT interrupt status register for GPIO32-33 + */ +#define GPIO_PROCPU_INT1 0x00000003U +#define GPIO_PROCPU_INT1_M (GPIO_PROCPU_INT1_V << GPIO_PROCPU_INT1_S) +#define GPIO_PROCPU_INT1_V 0x00000003U +#define GPIO_PROCPU_INT1_S 0 + +/** GPIO_SDIO_INT1_REG register + * GPIO_SDIO_INT interrupt status register for GPIO32-33 + */ +#define GPIO_SDIO_INT1_REG (DR_REG_GPIO_BASE + 0xb0) +/** GPIO_SDIO_INT1 : RO; bitpos: [1:0]; default: 0; + * GPIO_SDIO_INT interrupt status register for GPIO32-33 + */ +#define GPIO_SDIO_INT1 0x00000003U +#define GPIO_SDIO_INT1_M (GPIO_SDIO_INT1_V << GPIO_SDIO_INT1_S) +#define GPIO_SDIO_INT1_V 0x00000003U +#define GPIO_SDIO_INT1_S 0 + /** GPIO_STATUS_NEXT_REG register - * GPIO interrupt source register + * GPIO interrupt source register for GPIO0-31 */ -#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0xb4) -/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [28:0]; default: 0; - * Represents the interrupt source signal of GPIO0 ~ GPIO24.\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. Each - * bit represents:\\ - * 0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.\\ - * 1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.\\ - * The interrupt could be rising edge interrupt, falling edge interrupt, level - * sensitive interrupt and any edge interrupt.\\ +#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0xc4) +/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [31:0]; default: 0; + * GPIO interrupt source register for GPIO0-31 */ -#define GPIO_STATUS_INTERRUPT_NEXT 0x1FFFFFFFU +#define GPIO_STATUS_INTERRUPT_NEXT 0xFFFFFFFFU #define GPIO_STATUS_INTERRUPT_NEXT_M (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S) -#define GPIO_STATUS_INTERRUPT_NEXT_V 0x1FFFFFFFU +#define GPIO_STATUS_INTERRUPT_NEXT_V 0xFFFFFFFFU #define GPIO_STATUS_INTERRUPT_NEXT_S 0 -/** GPIO_PIN0_REG register - * GPIO0 configuration register +/** GPIO_STATUS_NEXT1_REG register + * GPIO interrupt source register for GPIO32-33 */ -#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0xc4) +#define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0xc8) +/** GPIO_STATUS_INTERRUPT_NEXT1 : RO; bitpos: [1:0]; default: 0; + * GPIO interrupt source register for GPIO32-33 + */ +#define GPIO_STATUS_INTERRUPT_NEXT1 0x00000003U +#define GPIO_STATUS_INTERRUPT_NEXT1_M (GPIO_STATUS_INTERRUPT_NEXT1_V << GPIO_STATUS_INTERRUPT_NEXT1_S) +#define GPIO_STATUS_INTERRUPT_NEXT1_V 0x00000003U +#define GPIO_STATUS_INTERRUPT_NEXT1_S 0 + +/** GPIO_PIN0_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0xd4) /** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN0_SYNC2_BYPASS 0x00000003U #define GPIO_PIN0_SYNC2_BYPASS_M (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S) #define GPIO_PIN0_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN0_SYNC2_BYPASS_S 0 /** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN0_PAD_DRIVER (BIT(2)) #define GPIO_PIN0_PAD_DRIVER_M (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S) #define GPIO_PIN0_PAD_DRIVER_V 0x00000001U #define GPIO_PIN0_PAD_DRIVER_S 2 /** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN0_SYNC1_BYPASS 0x00000003U #define GPIO_PIN0_SYNC1_BYPASS_M (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S) #define GPIO_PIN0_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN0_SYNC1_BYPASS_S 3 /** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN0_INT_TYPE 0x00000007U #define GPIO_PIN0_INT_TYPE_M (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S) #define GPIO_PIN0_INT_TYPE_V 0x00000007U #define GPIO_PIN0_INT_TYPE_S 7 /** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN0_WAKEUP_ENABLE_M (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S) #define GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN0_WAKEUP_ENABLE_S 10 /** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN0_INT_ENA 0x0000001FU #define GPIO_PIN0_INT_ENA_M (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S) @@ -312,72 +387,50 @@ extern "C" { #define GPIO_PIN0_INT_ENA_S 13 /** GPIO_PIN1_REG register - * GPIO1 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0xc8) +#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0xd8) /** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN1_SYNC2_BYPASS 0x00000003U #define GPIO_PIN1_SYNC2_BYPASS_M (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S) #define GPIO_PIN1_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN1_SYNC2_BYPASS_S 0 /** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN1_PAD_DRIVER (BIT(2)) #define GPIO_PIN1_PAD_DRIVER_M (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S) #define GPIO_PIN1_PAD_DRIVER_V 0x00000001U #define GPIO_PIN1_PAD_DRIVER_S 2 /** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN1_SYNC1_BYPASS 0x00000003U #define GPIO_PIN1_SYNC1_BYPASS_M (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S) #define GPIO_PIN1_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN1_SYNC1_BYPASS_S 3 /** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN1_INT_TYPE 0x00000007U #define GPIO_PIN1_INT_TYPE_M (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S) #define GPIO_PIN1_INT_TYPE_V 0x00000007U #define GPIO_PIN1_INT_TYPE_S 7 /** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN1_WAKEUP_ENABLE_M (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S) #define GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN1_WAKEUP_ENABLE_S 10 /** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN1_INT_ENA 0x0000001FU #define GPIO_PIN1_INT_ENA_M (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S) @@ -385,72 +438,50 @@ extern "C" { #define GPIO_PIN1_INT_ENA_S 13 /** GPIO_PIN2_REG register - * GPIO2 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0xcc) +#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0xdc) /** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN2_SYNC2_BYPASS 0x00000003U #define GPIO_PIN2_SYNC2_BYPASS_M (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S) #define GPIO_PIN2_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN2_SYNC2_BYPASS_S 0 /** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN2_PAD_DRIVER (BIT(2)) #define GPIO_PIN2_PAD_DRIVER_M (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S) #define GPIO_PIN2_PAD_DRIVER_V 0x00000001U #define GPIO_PIN2_PAD_DRIVER_S 2 /** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN2_SYNC1_BYPASS 0x00000003U #define GPIO_PIN2_SYNC1_BYPASS_M (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S) #define GPIO_PIN2_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN2_SYNC1_BYPASS_S 3 /** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN2_INT_TYPE 0x00000007U #define GPIO_PIN2_INT_TYPE_M (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S) #define GPIO_PIN2_INT_TYPE_V 0x00000007U #define GPIO_PIN2_INT_TYPE_S 7 /** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN2_WAKEUP_ENABLE_M (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S) #define GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN2_WAKEUP_ENABLE_S 10 /** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN2_INT_ENA 0x0000001FU #define GPIO_PIN2_INT_ENA_M (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S) @@ -458,72 +489,50 @@ extern "C" { #define GPIO_PIN2_INT_ENA_S 13 /** GPIO_PIN3_REG register - * GPIO3 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0xd0) +#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0xe0) /** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN3_SYNC2_BYPASS 0x00000003U #define GPIO_PIN3_SYNC2_BYPASS_M (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S) #define GPIO_PIN3_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN3_SYNC2_BYPASS_S 0 /** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN3_PAD_DRIVER (BIT(2)) #define GPIO_PIN3_PAD_DRIVER_M (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S) #define GPIO_PIN3_PAD_DRIVER_V 0x00000001U #define GPIO_PIN3_PAD_DRIVER_S 2 /** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN3_SYNC1_BYPASS 0x00000003U #define GPIO_PIN3_SYNC1_BYPASS_M (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S) #define GPIO_PIN3_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN3_SYNC1_BYPASS_S 3 /** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN3_INT_TYPE 0x00000007U #define GPIO_PIN3_INT_TYPE_M (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S) #define GPIO_PIN3_INT_TYPE_V 0x00000007U #define GPIO_PIN3_INT_TYPE_S 7 /** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN3_WAKEUP_ENABLE_M (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S) #define GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN3_WAKEUP_ENABLE_S 10 /** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN3_INT_ENA 0x0000001FU #define GPIO_PIN3_INT_ENA_M (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S) @@ -531,72 +540,50 @@ extern "C" { #define GPIO_PIN3_INT_ENA_S 13 /** GPIO_PIN4_REG register - * GPIO4 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0xd4) +#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0xe4) /** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN4_SYNC2_BYPASS 0x00000003U #define GPIO_PIN4_SYNC2_BYPASS_M (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S) #define GPIO_PIN4_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN4_SYNC2_BYPASS_S 0 /** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN4_PAD_DRIVER (BIT(2)) #define GPIO_PIN4_PAD_DRIVER_M (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S) #define GPIO_PIN4_PAD_DRIVER_V 0x00000001U #define GPIO_PIN4_PAD_DRIVER_S 2 /** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN4_SYNC1_BYPASS 0x00000003U #define GPIO_PIN4_SYNC1_BYPASS_M (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S) #define GPIO_PIN4_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN4_SYNC1_BYPASS_S 3 /** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN4_INT_TYPE 0x00000007U #define GPIO_PIN4_INT_TYPE_M (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S) #define GPIO_PIN4_INT_TYPE_V 0x00000007U #define GPIO_PIN4_INT_TYPE_S 7 /** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN4_WAKEUP_ENABLE_M (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S) #define GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN4_WAKEUP_ENABLE_S 10 /** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN4_INT_ENA 0x0000001FU #define GPIO_PIN4_INT_ENA_M (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S) @@ -604,72 +591,50 @@ extern "C" { #define GPIO_PIN4_INT_ENA_S 13 /** GPIO_PIN5_REG register - * GPIO5 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0xd8) +#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0xe8) /** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN5_SYNC2_BYPASS 0x00000003U #define GPIO_PIN5_SYNC2_BYPASS_M (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S) #define GPIO_PIN5_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN5_SYNC2_BYPASS_S 0 /** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN5_PAD_DRIVER (BIT(2)) #define GPIO_PIN5_PAD_DRIVER_M (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S) #define GPIO_PIN5_PAD_DRIVER_V 0x00000001U #define GPIO_PIN5_PAD_DRIVER_S 2 /** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN5_SYNC1_BYPASS 0x00000003U #define GPIO_PIN5_SYNC1_BYPASS_M (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S) #define GPIO_PIN5_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN5_SYNC1_BYPASS_S 3 /** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN5_INT_TYPE 0x00000007U #define GPIO_PIN5_INT_TYPE_M (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S) #define GPIO_PIN5_INT_TYPE_V 0x00000007U #define GPIO_PIN5_INT_TYPE_S 7 /** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN5_WAKEUP_ENABLE_M (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S) #define GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN5_WAKEUP_ENABLE_S 10 /** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN5_INT_ENA 0x0000001FU #define GPIO_PIN5_INT_ENA_M (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S) @@ -677,72 +642,50 @@ extern "C" { #define GPIO_PIN5_INT_ENA_S 13 /** GPIO_PIN6_REG register - * GPIO6 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0xdc) +#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0xec) /** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN6_SYNC2_BYPASS 0x00000003U #define GPIO_PIN6_SYNC2_BYPASS_M (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S) #define GPIO_PIN6_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN6_SYNC2_BYPASS_S 0 /** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN6_PAD_DRIVER (BIT(2)) #define GPIO_PIN6_PAD_DRIVER_M (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S) #define GPIO_PIN6_PAD_DRIVER_V 0x00000001U #define GPIO_PIN6_PAD_DRIVER_S 2 /** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN6_SYNC1_BYPASS 0x00000003U #define GPIO_PIN6_SYNC1_BYPASS_M (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S) #define GPIO_PIN6_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN6_SYNC1_BYPASS_S 3 /** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN6_INT_TYPE 0x00000007U #define GPIO_PIN6_INT_TYPE_M (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S) #define GPIO_PIN6_INT_TYPE_V 0x00000007U #define GPIO_PIN6_INT_TYPE_S 7 /** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN6_WAKEUP_ENABLE_M (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S) #define GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN6_WAKEUP_ENABLE_S 10 /** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN6_INT_ENA 0x0000001FU #define GPIO_PIN6_INT_ENA_M (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S) @@ -750,72 +693,50 @@ extern "C" { #define GPIO_PIN6_INT_ENA_S 13 /** GPIO_PIN7_REG register - * GPIO7 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0xe0) +#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0xf0) /** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN7_SYNC2_BYPASS 0x00000003U #define GPIO_PIN7_SYNC2_BYPASS_M (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S) #define GPIO_PIN7_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN7_SYNC2_BYPASS_S 0 /** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN7_PAD_DRIVER (BIT(2)) #define GPIO_PIN7_PAD_DRIVER_M (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S) #define GPIO_PIN7_PAD_DRIVER_V 0x00000001U #define GPIO_PIN7_PAD_DRIVER_S 2 /** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN7_SYNC1_BYPASS 0x00000003U #define GPIO_PIN7_SYNC1_BYPASS_M (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S) #define GPIO_PIN7_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN7_SYNC1_BYPASS_S 3 /** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN7_INT_TYPE 0x00000007U #define GPIO_PIN7_INT_TYPE_M (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S) #define GPIO_PIN7_INT_TYPE_V 0x00000007U #define GPIO_PIN7_INT_TYPE_S 7 /** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN7_WAKEUP_ENABLE_M (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S) #define GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN7_WAKEUP_ENABLE_S 10 /** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN7_INT_ENA 0x0000001FU #define GPIO_PIN7_INT_ENA_M (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S) @@ -823,72 +744,50 @@ extern "C" { #define GPIO_PIN7_INT_ENA_S 13 /** GPIO_PIN8_REG register - * GPIO8 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0xe4) +#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0xf4) /** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN8_SYNC2_BYPASS 0x00000003U #define GPIO_PIN8_SYNC2_BYPASS_M (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S) #define GPIO_PIN8_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN8_SYNC2_BYPASS_S 0 /** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN8_PAD_DRIVER (BIT(2)) #define GPIO_PIN8_PAD_DRIVER_M (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S) #define GPIO_PIN8_PAD_DRIVER_V 0x00000001U #define GPIO_PIN8_PAD_DRIVER_S 2 /** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN8_SYNC1_BYPASS 0x00000003U #define GPIO_PIN8_SYNC1_BYPASS_M (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S) #define GPIO_PIN8_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN8_SYNC1_BYPASS_S 3 /** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN8_INT_TYPE 0x00000007U #define GPIO_PIN8_INT_TYPE_M (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S) #define GPIO_PIN8_INT_TYPE_V 0x00000007U #define GPIO_PIN8_INT_TYPE_S 7 /** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN8_WAKEUP_ENABLE_M (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S) #define GPIO_PIN8_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN8_WAKEUP_ENABLE_S 10 /** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN8_INT_ENA 0x0000001FU #define GPIO_PIN8_INT_ENA_M (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S) @@ -896,72 +795,50 @@ extern "C" { #define GPIO_PIN8_INT_ENA_S 13 /** GPIO_PIN9_REG register - * GPIO9 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0xe8) +#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0xf8) /** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN9_SYNC2_BYPASS 0x00000003U #define GPIO_PIN9_SYNC2_BYPASS_M (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S) #define GPIO_PIN9_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN9_SYNC2_BYPASS_S 0 /** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN9_PAD_DRIVER (BIT(2)) #define GPIO_PIN9_PAD_DRIVER_M (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S) #define GPIO_PIN9_PAD_DRIVER_V 0x00000001U #define GPIO_PIN9_PAD_DRIVER_S 2 /** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN9_SYNC1_BYPASS 0x00000003U #define GPIO_PIN9_SYNC1_BYPASS_M (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S) #define GPIO_PIN9_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN9_SYNC1_BYPASS_S 3 /** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN9_INT_TYPE 0x00000007U #define GPIO_PIN9_INT_TYPE_M (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S) #define GPIO_PIN9_INT_TYPE_V 0x00000007U #define GPIO_PIN9_INT_TYPE_S 7 /** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN9_WAKEUP_ENABLE_M (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S) #define GPIO_PIN9_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN9_WAKEUP_ENABLE_S 10 /** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN9_INT_ENA 0x0000001FU #define GPIO_PIN9_INT_ENA_M (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S) @@ -969,72 +846,50 @@ extern "C" { #define GPIO_PIN9_INT_ENA_S 13 /** GPIO_PIN10_REG register - * GPIO10 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0xec) +#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0xfc) /** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN10_SYNC2_BYPASS 0x00000003U #define GPIO_PIN10_SYNC2_BYPASS_M (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S) #define GPIO_PIN10_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN10_SYNC2_BYPASS_S 0 /** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN10_PAD_DRIVER (BIT(2)) #define GPIO_PIN10_PAD_DRIVER_M (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S) #define GPIO_PIN10_PAD_DRIVER_V 0x00000001U #define GPIO_PIN10_PAD_DRIVER_S 2 /** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN10_SYNC1_BYPASS 0x00000003U #define GPIO_PIN10_SYNC1_BYPASS_M (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S) #define GPIO_PIN10_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN10_SYNC1_BYPASS_S 3 /** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN10_INT_TYPE 0x00000007U #define GPIO_PIN10_INT_TYPE_M (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S) #define GPIO_PIN10_INT_TYPE_V 0x00000007U #define GPIO_PIN10_INT_TYPE_S 7 /** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN10_WAKEUP_ENABLE_M (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S) #define GPIO_PIN10_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN10_WAKEUP_ENABLE_S 10 /** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN10_INT_ENA 0x0000001FU #define GPIO_PIN10_INT_ENA_M (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S) @@ -1042,72 +897,50 @@ extern "C" { #define GPIO_PIN10_INT_ENA_S 13 /** GPIO_PIN11_REG register - * GPIO11 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xf0) +#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0x100) /** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN11_SYNC2_BYPASS 0x00000003U #define GPIO_PIN11_SYNC2_BYPASS_M (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S) #define GPIO_PIN11_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN11_SYNC2_BYPASS_S 0 /** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN11_PAD_DRIVER (BIT(2)) #define GPIO_PIN11_PAD_DRIVER_M (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S) #define GPIO_PIN11_PAD_DRIVER_V 0x00000001U #define GPIO_PIN11_PAD_DRIVER_S 2 /** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN11_SYNC1_BYPASS 0x00000003U #define GPIO_PIN11_SYNC1_BYPASS_M (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S) #define GPIO_PIN11_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN11_SYNC1_BYPASS_S 3 /** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN11_INT_TYPE 0x00000007U #define GPIO_PIN11_INT_TYPE_M (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S) #define GPIO_PIN11_INT_TYPE_V 0x00000007U #define GPIO_PIN11_INT_TYPE_S 7 /** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN11_WAKEUP_ENABLE_M (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S) #define GPIO_PIN11_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN11_WAKEUP_ENABLE_S 10 /** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN11_INT_ENA 0x0000001FU #define GPIO_PIN11_INT_ENA_M (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S) @@ -1115,72 +948,50 @@ extern "C" { #define GPIO_PIN11_INT_ENA_S 13 /** GPIO_PIN12_REG register - * GPIO12 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xf4) +#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0x104) /** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN12_SYNC2_BYPASS 0x00000003U #define GPIO_PIN12_SYNC2_BYPASS_M (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S) #define GPIO_PIN12_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN12_SYNC2_BYPASS_S 0 /** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN12_PAD_DRIVER (BIT(2)) #define GPIO_PIN12_PAD_DRIVER_M (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S) #define GPIO_PIN12_PAD_DRIVER_V 0x00000001U #define GPIO_PIN12_PAD_DRIVER_S 2 /** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN12_SYNC1_BYPASS 0x00000003U #define GPIO_PIN12_SYNC1_BYPASS_M (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S) #define GPIO_PIN12_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN12_SYNC1_BYPASS_S 3 /** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN12_INT_TYPE 0x00000007U #define GPIO_PIN12_INT_TYPE_M (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S) #define GPIO_PIN12_INT_TYPE_V 0x00000007U #define GPIO_PIN12_INT_TYPE_S 7 /** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN12_WAKEUP_ENABLE_M (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S) #define GPIO_PIN12_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN12_WAKEUP_ENABLE_S 10 /** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN12_INT_ENA 0x0000001FU #define GPIO_PIN12_INT_ENA_M (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S) @@ -1188,72 +999,50 @@ extern "C" { #define GPIO_PIN12_INT_ENA_S 13 /** GPIO_PIN13_REG register - * GPIO13 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xf8) +#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0x108) /** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN13_SYNC2_BYPASS 0x00000003U #define GPIO_PIN13_SYNC2_BYPASS_M (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S) #define GPIO_PIN13_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN13_SYNC2_BYPASS_S 0 /** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN13_PAD_DRIVER (BIT(2)) #define GPIO_PIN13_PAD_DRIVER_M (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S) #define GPIO_PIN13_PAD_DRIVER_V 0x00000001U #define GPIO_PIN13_PAD_DRIVER_S 2 /** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN13_SYNC1_BYPASS 0x00000003U #define GPIO_PIN13_SYNC1_BYPASS_M (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S) #define GPIO_PIN13_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN13_SYNC1_BYPASS_S 3 /** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN13_INT_TYPE 0x00000007U #define GPIO_PIN13_INT_TYPE_M (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S) #define GPIO_PIN13_INT_TYPE_V 0x00000007U #define GPIO_PIN13_INT_TYPE_S 7 /** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN13_WAKEUP_ENABLE_M (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S) #define GPIO_PIN13_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN13_WAKEUP_ENABLE_S 10 /** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN13_INT_ENA 0x0000001FU #define GPIO_PIN13_INT_ENA_M (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S) @@ -1261,72 +1050,50 @@ extern "C" { #define GPIO_PIN13_INT_ENA_S 13 /** GPIO_PIN14_REG register - * GPIO14 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xfc) +#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0x10c) /** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN14_SYNC2_BYPASS 0x00000003U #define GPIO_PIN14_SYNC2_BYPASS_M (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S) #define GPIO_PIN14_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN14_SYNC2_BYPASS_S 0 /** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN14_PAD_DRIVER (BIT(2)) #define GPIO_PIN14_PAD_DRIVER_M (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S) #define GPIO_PIN14_PAD_DRIVER_V 0x00000001U #define GPIO_PIN14_PAD_DRIVER_S 2 /** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN14_SYNC1_BYPASS 0x00000003U #define GPIO_PIN14_SYNC1_BYPASS_M (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S) #define GPIO_PIN14_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN14_SYNC1_BYPASS_S 3 /** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN14_INT_TYPE 0x00000007U #define GPIO_PIN14_INT_TYPE_M (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S) #define GPIO_PIN14_INT_TYPE_V 0x00000007U #define GPIO_PIN14_INT_TYPE_S 7 /** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN14_WAKEUP_ENABLE_M (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S) #define GPIO_PIN14_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN14_WAKEUP_ENABLE_S 10 /** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN14_INT_ENA 0x0000001FU #define GPIO_PIN14_INT_ENA_M (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S) @@ -1334,72 +1101,50 @@ extern "C" { #define GPIO_PIN14_INT_ENA_S 13 /** GPIO_PIN15_REG register - * GPIO15 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0x100) +#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0x110) /** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN15_SYNC2_BYPASS 0x00000003U #define GPIO_PIN15_SYNC2_BYPASS_M (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S) #define GPIO_PIN15_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN15_SYNC2_BYPASS_S 0 /** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN15_PAD_DRIVER (BIT(2)) #define GPIO_PIN15_PAD_DRIVER_M (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S) #define GPIO_PIN15_PAD_DRIVER_V 0x00000001U #define GPIO_PIN15_PAD_DRIVER_S 2 /** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN15_SYNC1_BYPASS 0x00000003U #define GPIO_PIN15_SYNC1_BYPASS_M (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S) #define GPIO_PIN15_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN15_SYNC1_BYPASS_S 3 /** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN15_INT_TYPE 0x00000007U #define GPIO_PIN15_INT_TYPE_M (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S) #define GPIO_PIN15_INT_TYPE_V 0x00000007U #define GPIO_PIN15_INT_TYPE_S 7 /** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN15_WAKEUP_ENABLE_M (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S) #define GPIO_PIN15_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN15_WAKEUP_ENABLE_S 10 /** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN15_INT_ENA 0x0000001FU #define GPIO_PIN15_INT_ENA_M (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S) @@ -1407,72 +1152,50 @@ extern "C" { #define GPIO_PIN15_INT_ENA_S 13 /** GPIO_PIN16_REG register - * GPIO16 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0x104) +#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0x114) /** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN16_SYNC2_BYPASS 0x00000003U #define GPIO_PIN16_SYNC2_BYPASS_M (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S) #define GPIO_PIN16_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN16_SYNC2_BYPASS_S 0 /** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN16_PAD_DRIVER (BIT(2)) #define GPIO_PIN16_PAD_DRIVER_M (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S) #define GPIO_PIN16_PAD_DRIVER_V 0x00000001U #define GPIO_PIN16_PAD_DRIVER_S 2 /** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN16_SYNC1_BYPASS 0x00000003U #define GPIO_PIN16_SYNC1_BYPASS_M (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S) #define GPIO_PIN16_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN16_SYNC1_BYPASS_S 3 /** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN16_INT_TYPE 0x00000007U #define GPIO_PIN16_INT_TYPE_M (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S) #define GPIO_PIN16_INT_TYPE_V 0x00000007U #define GPIO_PIN16_INT_TYPE_S 7 /** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN16_WAKEUP_ENABLE_M (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S) #define GPIO_PIN16_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN16_WAKEUP_ENABLE_S 10 /** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN16_INT_ENA 0x0000001FU #define GPIO_PIN16_INT_ENA_M (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S) @@ -1480,72 +1203,50 @@ extern "C" { #define GPIO_PIN16_INT_ENA_S 13 /** GPIO_PIN17_REG register - * GPIO17 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0x108) +#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0x118) /** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN17_SYNC2_BYPASS 0x00000003U #define GPIO_PIN17_SYNC2_BYPASS_M (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S) #define GPIO_PIN17_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN17_SYNC2_BYPASS_S 0 /** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN17_PAD_DRIVER (BIT(2)) #define GPIO_PIN17_PAD_DRIVER_M (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S) #define GPIO_PIN17_PAD_DRIVER_V 0x00000001U #define GPIO_PIN17_PAD_DRIVER_S 2 /** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN17_SYNC1_BYPASS 0x00000003U #define GPIO_PIN17_SYNC1_BYPASS_M (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S) #define GPIO_PIN17_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN17_SYNC1_BYPASS_S 3 /** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN17_INT_TYPE 0x00000007U #define GPIO_PIN17_INT_TYPE_M (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S) #define GPIO_PIN17_INT_TYPE_V 0x00000007U #define GPIO_PIN17_INT_TYPE_S 7 /** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN17_WAKEUP_ENABLE_M (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S) #define GPIO_PIN17_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN17_WAKEUP_ENABLE_S 10 /** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN17_INT_ENA 0x0000001FU #define GPIO_PIN17_INT_ENA_M (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S) @@ -1553,72 +1254,50 @@ extern "C" { #define GPIO_PIN17_INT_ENA_S 13 /** GPIO_PIN18_REG register - * GPIO18 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0x10c) +#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0x11c) /** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN18_SYNC2_BYPASS 0x00000003U #define GPIO_PIN18_SYNC2_BYPASS_M (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S) #define GPIO_PIN18_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN18_SYNC2_BYPASS_S 0 /** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN18_PAD_DRIVER (BIT(2)) #define GPIO_PIN18_PAD_DRIVER_M (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S) #define GPIO_PIN18_PAD_DRIVER_V 0x00000001U #define GPIO_PIN18_PAD_DRIVER_S 2 /** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN18_SYNC1_BYPASS 0x00000003U #define GPIO_PIN18_SYNC1_BYPASS_M (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S) #define GPIO_PIN18_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN18_SYNC1_BYPASS_S 3 /** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN18_INT_TYPE 0x00000007U #define GPIO_PIN18_INT_TYPE_M (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S) #define GPIO_PIN18_INT_TYPE_V 0x00000007U #define GPIO_PIN18_INT_TYPE_S 7 /** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN18_WAKEUP_ENABLE_M (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S) #define GPIO_PIN18_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN18_WAKEUP_ENABLE_S 10 /** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN18_INT_ENA 0x0000001FU #define GPIO_PIN18_INT_ENA_M (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S) @@ -1626,72 +1305,50 @@ extern "C" { #define GPIO_PIN18_INT_ENA_S 13 /** GPIO_PIN19_REG register - * GPIO19 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0x110) +#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0x120) /** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN19_SYNC2_BYPASS 0x00000003U #define GPIO_PIN19_SYNC2_BYPASS_M (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S) #define GPIO_PIN19_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN19_SYNC2_BYPASS_S 0 /** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN19_PAD_DRIVER (BIT(2)) #define GPIO_PIN19_PAD_DRIVER_M (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S) #define GPIO_PIN19_PAD_DRIVER_V 0x00000001U #define GPIO_PIN19_PAD_DRIVER_S 2 /** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN19_SYNC1_BYPASS 0x00000003U #define GPIO_PIN19_SYNC1_BYPASS_M (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S) #define GPIO_PIN19_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN19_SYNC1_BYPASS_S 3 /** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN19_INT_TYPE 0x00000007U #define GPIO_PIN19_INT_TYPE_M (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S) #define GPIO_PIN19_INT_TYPE_V 0x00000007U #define GPIO_PIN19_INT_TYPE_S 7 /** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN19_WAKEUP_ENABLE_M (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S) #define GPIO_PIN19_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN19_WAKEUP_ENABLE_S 10 /** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN19_INT_ENA 0x0000001FU #define GPIO_PIN19_INT_ENA_M (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S) @@ -1699,72 +1356,50 @@ extern "C" { #define GPIO_PIN19_INT_ENA_S 13 /** GPIO_PIN20_REG register - * GPIO20 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0x114) +#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0x124) /** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN20_SYNC2_BYPASS 0x00000003U #define GPIO_PIN20_SYNC2_BYPASS_M (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S) #define GPIO_PIN20_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN20_SYNC2_BYPASS_S 0 /** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN20_PAD_DRIVER (BIT(2)) #define GPIO_PIN20_PAD_DRIVER_M (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S) #define GPIO_PIN20_PAD_DRIVER_V 0x00000001U #define GPIO_PIN20_PAD_DRIVER_S 2 /** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN20_SYNC1_BYPASS 0x00000003U #define GPIO_PIN20_SYNC1_BYPASS_M (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S) #define GPIO_PIN20_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN20_SYNC1_BYPASS_S 3 /** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN20_INT_TYPE 0x00000007U #define GPIO_PIN20_INT_TYPE_M (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S) #define GPIO_PIN20_INT_TYPE_V 0x00000007U #define GPIO_PIN20_INT_TYPE_S 7 /** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN20_WAKEUP_ENABLE_M (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S) #define GPIO_PIN20_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN20_WAKEUP_ENABLE_S 10 /** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN20_INT_ENA 0x0000001FU #define GPIO_PIN20_INT_ENA_M (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S) @@ -1772,72 +1407,50 @@ extern "C" { #define GPIO_PIN20_INT_ENA_S 13 /** GPIO_PIN21_REG register - * GPIO21 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0x118) +#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0x128) /** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN21_SYNC2_BYPASS 0x00000003U #define GPIO_PIN21_SYNC2_BYPASS_M (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S) #define GPIO_PIN21_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN21_SYNC2_BYPASS_S 0 /** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN21_PAD_DRIVER (BIT(2)) #define GPIO_PIN21_PAD_DRIVER_M (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S) #define GPIO_PIN21_PAD_DRIVER_V 0x00000001U #define GPIO_PIN21_PAD_DRIVER_S 2 /** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN21_SYNC1_BYPASS 0x00000003U #define GPIO_PIN21_SYNC1_BYPASS_M (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S) #define GPIO_PIN21_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN21_SYNC1_BYPASS_S 3 /** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN21_INT_TYPE 0x00000007U #define GPIO_PIN21_INT_TYPE_M (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S) #define GPIO_PIN21_INT_TYPE_V 0x00000007U #define GPIO_PIN21_INT_TYPE_S 7 /** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN21_WAKEUP_ENABLE_M (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S) #define GPIO_PIN21_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN21_WAKEUP_ENABLE_S 10 /** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN21_INT_ENA 0x0000001FU #define GPIO_PIN21_INT_ENA_M (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S) @@ -1845,72 +1458,50 @@ extern "C" { #define GPIO_PIN21_INT_ENA_S 13 /** GPIO_PIN22_REG register - * GPIO22 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0x11c) +#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0x12c) /** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN22_SYNC2_BYPASS 0x00000003U #define GPIO_PIN22_SYNC2_BYPASS_M (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S) #define GPIO_PIN22_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN22_SYNC2_BYPASS_S 0 /** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN22_PAD_DRIVER (BIT(2)) #define GPIO_PIN22_PAD_DRIVER_M (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S) #define GPIO_PIN22_PAD_DRIVER_V 0x00000001U #define GPIO_PIN22_PAD_DRIVER_S 2 /** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN22_SYNC1_BYPASS 0x00000003U #define GPIO_PIN22_SYNC1_BYPASS_M (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S) #define GPIO_PIN22_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN22_SYNC1_BYPASS_S 3 /** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN22_INT_TYPE 0x00000007U #define GPIO_PIN22_INT_TYPE_M (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S) #define GPIO_PIN22_INT_TYPE_V 0x00000007U #define GPIO_PIN22_INT_TYPE_S 7 /** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN22_WAKEUP_ENABLE_M (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S) #define GPIO_PIN22_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN22_WAKEUP_ENABLE_S 10 /** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN22_INT_ENA 0x0000001FU #define GPIO_PIN22_INT_ENA_M (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S) @@ -1918,72 +1509,50 @@ extern "C" { #define GPIO_PIN22_INT_ENA_S 13 /** GPIO_PIN23_REG register - * GPIO23 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0x120) +#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0x130) /** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN23_SYNC2_BYPASS 0x00000003U #define GPIO_PIN23_SYNC2_BYPASS_M (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S) #define GPIO_PIN23_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN23_SYNC2_BYPASS_S 0 /** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN23_PAD_DRIVER (BIT(2)) #define GPIO_PIN23_PAD_DRIVER_M (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S) #define GPIO_PIN23_PAD_DRIVER_V 0x00000001U #define GPIO_PIN23_PAD_DRIVER_S 2 /** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN23_SYNC1_BYPASS 0x00000003U #define GPIO_PIN23_SYNC1_BYPASS_M (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S) #define GPIO_PIN23_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN23_SYNC1_BYPASS_S 3 /** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN23_INT_TYPE 0x00000007U #define GPIO_PIN23_INT_TYPE_M (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S) #define GPIO_PIN23_INT_TYPE_V 0x00000007U #define GPIO_PIN23_INT_TYPE_S 7 /** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN23_WAKEUP_ENABLE_M (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S) #define GPIO_PIN23_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN23_WAKEUP_ENABLE_S 10 /** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN23_INT_ENA 0x0000001FU #define GPIO_PIN23_INT_ENA_M (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S) @@ -1991,1918 +1560,1787 @@ extern "C" { #define GPIO_PIN23_INT_ENA_S 13 /** GPIO_PIN24_REG register - * GPIO24 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0x124) +#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0x134) /** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN24_SYNC2_BYPASS 0x00000003U #define GPIO_PIN24_SYNC2_BYPASS_M (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S) #define GPIO_PIN24_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN24_SYNC2_BYPASS_S 0 /** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN24_PAD_DRIVER (BIT(2)) #define GPIO_PIN24_PAD_DRIVER_M (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S) #define GPIO_PIN24_PAD_DRIVER_V 0x00000001U #define GPIO_PIN24_PAD_DRIVER_S 2 /** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN24_SYNC1_BYPASS 0x00000003U #define GPIO_PIN24_SYNC1_BYPASS_M (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S) #define GPIO_PIN24_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN24_SYNC1_BYPASS_S 3 /** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN24_INT_TYPE 0x00000007U #define GPIO_PIN24_INT_TYPE_M (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S) #define GPIO_PIN24_INT_TYPE_V 0x00000007U #define GPIO_PIN24_INT_TYPE_S 7 /** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN24_WAKEUP_ENABLE_M (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S) #define GPIO_PIN24_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN24_WAKEUP_ENABLE_S 10 /** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN24_INT_ENA 0x0000001FU #define GPIO_PIN24_INT_ENA_M (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S) #define GPIO_PIN24_INT_ENA_V 0x0000001FU #define GPIO_PIN24_INT_ENA_S 13 +/** GPIO_PIN25_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0x138) +/** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN25_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN25_SYNC2_BYPASS_M (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S) +#define GPIO_PIN25_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN25_SYNC2_BYPASS_S 0 +/** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN25_PAD_DRIVER (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_M (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S) +#define GPIO_PIN25_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN25_PAD_DRIVER_S 2 +/** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN25_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN25_SYNC1_BYPASS_M (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S) +#define GPIO_PIN25_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN25_SYNC1_BYPASS_S 3 +/** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN25_INT_TYPE 0x00000007U +#define GPIO_PIN25_INT_TYPE_M (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S) +#define GPIO_PIN25_INT_TYPE_V 0x00000007U +#define GPIO_PIN25_INT_TYPE_S 7 +/** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_M (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S) +#define GPIO_PIN25_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN25_WAKEUP_ENABLE_S 10 +/** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. + */ +#define GPIO_PIN25_INT_ENA 0x0000001FU +#define GPIO_PIN25_INT_ENA_M (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S) +#define GPIO_PIN25_INT_ENA_V 0x0000001FU +#define GPIO_PIN25_INT_ENA_S 13 + +/** GPIO_PIN26_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0x13c) +/** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN26_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN26_SYNC2_BYPASS_M (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S) +#define GPIO_PIN26_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN26_SYNC2_BYPASS_S 0 +/** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN26_PAD_DRIVER (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_M (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S) +#define GPIO_PIN26_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN26_PAD_DRIVER_S 2 +/** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN26_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN26_SYNC1_BYPASS_M (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S) +#define GPIO_PIN26_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN26_SYNC1_BYPASS_S 3 +/** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN26_INT_TYPE 0x00000007U +#define GPIO_PIN26_INT_TYPE_M (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S) +#define GPIO_PIN26_INT_TYPE_V 0x00000007U +#define GPIO_PIN26_INT_TYPE_S 7 +/** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_M (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S) +#define GPIO_PIN26_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN26_WAKEUP_ENABLE_S 10 +/** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. + */ +#define GPIO_PIN26_INT_ENA 0x0000001FU +#define GPIO_PIN26_INT_ENA_M (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S) +#define GPIO_PIN26_INT_ENA_V 0x0000001FU +#define GPIO_PIN26_INT_ENA_S 13 + +/** GPIO_PIN27_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0x140) +/** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN27_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN27_SYNC2_BYPASS_M (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S) +#define GPIO_PIN27_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN27_SYNC2_BYPASS_S 0 +/** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN27_PAD_DRIVER (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_M (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S) +#define GPIO_PIN27_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN27_PAD_DRIVER_S 2 +/** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN27_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN27_SYNC1_BYPASS_M (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S) +#define GPIO_PIN27_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN27_SYNC1_BYPASS_S 3 +/** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN27_INT_TYPE 0x00000007U +#define GPIO_PIN27_INT_TYPE_M (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S) +#define GPIO_PIN27_INT_TYPE_V 0x00000007U +#define GPIO_PIN27_INT_TYPE_S 7 +/** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_M (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S) +#define GPIO_PIN27_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN27_WAKEUP_ENABLE_S 10 +/** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. + */ +#define GPIO_PIN27_INT_ENA 0x0000001FU +#define GPIO_PIN27_INT_ENA_M (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S) +#define GPIO_PIN27_INT_ENA_V 0x0000001FU +#define GPIO_PIN27_INT_ENA_S 13 + +/** GPIO_PIN28_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0x144) +/** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN28_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN28_SYNC2_BYPASS_M (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S) +#define GPIO_PIN28_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN28_SYNC2_BYPASS_S 0 +/** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN28_PAD_DRIVER (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_M (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S) +#define GPIO_PIN28_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN28_PAD_DRIVER_S 2 +/** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN28_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN28_SYNC1_BYPASS_M (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S) +#define GPIO_PIN28_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN28_SYNC1_BYPASS_S 3 +/** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN28_INT_TYPE 0x00000007U +#define GPIO_PIN28_INT_TYPE_M (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S) +#define GPIO_PIN28_INT_TYPE_V 0x00000007U +#define GPIO_PIN28_INT_TYPE_S 7 +/** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_M (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S) +#define GPIO_PIN28_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN28_WAKEUP_ENABLE_S 10 +/** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. + */ +#define GPIO_PIN28_INT_ENA 0x0000001FU +#define GPIO_PIN28_INT_ENA_M (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S) +#define GPIO_PIN28_INT_ENA_V 0x0000001FU +#define GPIO_PIN28_INT_ENA_S 13 + +/** GPIO_PIN29_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0x148) +/** GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN29_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN29_SYNC2_BYPASS_M (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S) +#define GPIO_PIN29_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN29_SYNC2_BYPASS_S 0 +/** GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN29_PAD_DRIVER (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_M (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S) +#define GPIO_PIN29_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN29_PAD_DRIVER_S 2 +/** GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN29_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN29_SYNC1_BYPASS_M (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S) +#define GPIO_PIN29_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN29_SYNC1_BYPASS_S 3 +/** GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN29_INT_TYPE 0x00000007U +#define GPIO_PIN29_INT_TYPE_M (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S) +#define GPIO_PIN29_INT_TYPE_V 0x00000007U +#define GPIO_PIN29_INT_TYPE_S 7 +/** GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_M (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S) +#define GPIO_PIN29_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN29_WAKEUP_ENABLE_S 10 +/** GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. + */ +#define GPIO_PIN29_INT_ENA 0x0000001FU +#define GPIO_PIN29_INT_ENA_M (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S) +#define GPIO_PIN29_INT_ENA_V 0x0000001FU +#define GPIO_PIN29_INT_ENA_S 13 + +/** GPIO_PIN30_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0x14c) +/** GPIO_PIN30_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN30_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN30_SYNC2_BYPASS_M (GPIO_PIN30_SYNC2_BYPASS_V << GPIO_PIN30_SYNC2_BYPASS_S) +#define GPIO_PIN30_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN30_SYNC2_BYPASS_S 0 +/** GPIO_PIN30_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN30_PAD_DRIVER (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER_M (GPIO_PIN30_PAD_DRIVER_V << GPIO_PIN30_PAD_DRIVER_S) +#define GPIO_PIN30_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN30_PAD_DRIVER_S 2 +/** GPIO_PIN30_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN30_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN30_SYNC1_BYPASS_M (GPIO_PIN30_SYNC1_BYPASS_V << GPIO_PIN30_SYNC1_BYPASS_S) +#define GPIO_PIN30_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN30_SYNC1_BYPASS_S 3 +/** GPIO_PIN30_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN30_INT_TYPE 0x00000007U +#define GPIO_PIN30_INT_TYPE_M (GPIO_PIN30_INT_TYPE_V << GPIO_PIN30_INT_TYPE_S) +#define GPIO_PIN30_INT_TYPE_V 0x00000007U +#define GPIO_PIN30_INT_TYPE_S 7 +/** GPIO_PIN30_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE_M (GPIO_PIN30_WAKEUP_ENABLE_V << GPIO_PIN30_WAKEUP_ENABLE_S) +#define GPIO_PIN30_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN30_WAKEUP_ENABLE_S 10 +/** GPIO_PIN30_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. + */ +#define GPIO_PIN30_INT_ENA 0x0000001FU +#define GPIO_PIN30_INT_ENA_M (GPIO_PIN30_INT_ENA_V << GPIO_PIN30_INT_ENA_S) +#define GPIO_PIN30_INT_ENA_V 0x0000001FU +#define GPIO_PIN30_INT_ENA_S 13 + +/** GPIO_PIN31_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0x150) +/** GPIO_PIN31_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN31_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN31_SYNC2_BYPASS_M (GPIO_PIN31_SYNC2_BYPASS_V << GPIO_PIN31_SYNC2_BYPASS_S) +#define GPIO_PIN31_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN31_SYNC2_BYPASS_S 0 +/** GPIO_PIN31_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN31_PAD_DRIVER (BIT(2)) +#define GPIO_PIN31_PAD_DRIVER_M (GPIO_PIN31_PAD_DRIVER_V << GPIO_PIN31_PAD_DRIVER_S) +#define GPIO_PIN31_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN31_PAD_DRIVER_S 2 +/** GPIO_PIN31_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN31_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN31_SYNC1_BYPASS_M (GPIO_PIN31_SYNC1_BYPASS_V << GPIO_PIN31_SYNC1_BYPASS_S) +#define GPIO_PIN31_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN31_SYNC1_BYPASS_S 3 +/** GPIO_PIN31_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN31_INT_TYPE 0x00000007U +#define GPIO_PIN31_INT_TYPE_M (GPIO_PIN31_INT_TYPE_V << GPIO_PIN31_INT_TYPE_S) +#define GPIO_PIN31_INT_TYPE_V 0x00000007U +#define GPIO_PIN31_INT_TYPE_S 7 +/** GPIO_PIN31_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN31_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN31_WAKEUP_ENABLE_M (GPIO_PIN31_WAKEUP_ENABLE_V << GPIO_PIN31_WAKEUP_ENABLE_S) +#define GPIO_PIN31_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN31_WAKEUP_ENABLE_S 10 +/** GPIO_PIN31_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. + */ +#define GPIO_PIN31_INT_ENA 0x0000001FU +#define GPIO_PIN31_INT_ENA_M (GPIO_PIN31_INT_ENA_V << GPIO_PIN31_INT_ENA_S) +#define GPIO_PIN31_INT_ENA_V 0x0000001FU +#define GPIO_PIN31_INT_ENA_S 13 + +/** GPIO_PIN32_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0x154) +/** GPIO_PIN32_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN32_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN32_SYNC2_BYPASS_M (GPIO_PIN32_SYNC2_BYPASS_V << GPIO_PIN32_SYNC2_BYPASS_S) +#define GPIO_PIN32_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN32_SYNC2_BYPASS_S 0 +/** GPIO_PIN32_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN32_PAD_DRIVER (BIT(2)) +#define GPIO_PIN32_PAD_DRIVER_M (GPIO_PIN32_PAD_DRIVER_V << GPIO_PIN32_PAD_DRIVER_S) +#define GPIO_PIN32_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN32_PAD_DRIVER_S 2 +/** GPIO_PIN32_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN32_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN32_SYNC1_BYPASS_M (GPIO_PIN32_SYNC1_BYPASS_V << GPIO_PIN32_SYNC1_BYPASS_S) +#define GPIO_PIN32_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN32_SYNC1_BYPASS_S 3 +/** GPIO_PIN32_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN32_INT_TYPE 0x00000007U +#define GPIO_PIN32_INT_TYPE_M (GPIO_PIN32_INT_TYPE_V << GPIO_PIN32_INT_TYPE_S) +#define GPIO_PIN32_INT_TYPE_V 0x00000007U +#define GPIO_PIN32_INT_TYPE_S 7 +/** GPIO_PIN32_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN32_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN32_WAKEUP_ENABLE_M (GPIO_PIN32_WAKEUP_ENABLE_V << GPIO_PIN32_WAKEUP_ENABLE_S) +#define GPIO_PIN32_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN32_WAKEUP_ENABLE_S 10 +/** GPIO_PIN32_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. + */ +#define GPIO_PIN32_INT_ENA 0x0000001FU +#define GPIO_PIN32_INT_ENA_M (GPIO_PIN32_INT_ENA_V << GPIO_PIN32_INT_ENA_S) +#define GPIO_PIN32_INT_ENA_V 0x0000001FU +#define GPIO_PIN32_INT_ENA_S 13 + +/** GPIO_PIN33_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0x158) +/** GPIO_PIN33_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN33_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN33_SYNC2_BYPASS_M (GPIO_PIN33_SYNC2_BYPASS_V << GPIO_PIN33_SYNC2_BYPASS_S) +#define GPIO_PIN33_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN33_SYNC2_BYPASS_S 0 +/** GPIO_PIN33_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN33_PAD_DRIVER (BIT(2)) +#define GPIO_PIN33_PAD_DRIVER_M (GPIO_PIN33_PAD_DRIVER_V << GPIO_PIN33_PAD_DRIVER_S) +#define GPIO_PIN33_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN33_PAD_DRIVER_S 2 +/** GPIO_PIN33_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN33_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN33_SYNC1_BYPASS_M (GPIO_PIN33_SYNC1_BYPASS_V << GPIO_PIN33_SYNC1_BYPASS_S) +#define GPIO_PIN33_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN33_SYNC1_BYPASS_S 3 +/** GPIO_PIN33_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN33_INT_TYPE 0x00000007U +#define GPIO_PIN33_INT_TYPE_M (GPIO_PIN33_INT_TYPE_V << GPIO_PIN33_INT_TYPE_S) +#define GPIO_PIN33_INT_TYPE_V 0x00000007U +#define GPIO_PIN33_INT_TYPE_S 7 +/** GPIO_PIN33_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN33_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN33_WAKEUP_ENABLE_M (GPIO_PIN33_WAKEUP_ENABLE_V << GPIO_PIN33_WAKEUP_ENABLE_S) +#define GPIO_PIN33_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN33_WAKEUP_ENABLE_S 10 +/** GPIO_PIN33_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. + */ +#define GPIO_PIN33_INT_ENA 0x0000001FU +#define GPIO_PIN33_INT_ENA_M (GPIO_PIN33_INT_ENA_V << GPIO_PIN33_INT_ENA_S) +#define GPIO_PIN33_INT_ENA_V 0x0000001FU +#define GPIO_PIN33_INT_ENA_S 13 + /** GPIO_FUNC0_IN_SEL_CFG_REG register - * Configuration register for input signal 0 + * GPIO input function configuration register */ -#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4) -/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 0.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d4) +/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC0_IN_SEL 0x0000003FU +#define GPIO_FUNC0_IN_SEL 0x0000007FU #define GPIO_FUNC0_IN_SEL_M (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S) -#define GPIO_FUNC0_IN_SEL_V 0x0000003FU +#define GPIO_FUNC0_IN_SEL_V 0x0000007FU #define GPIO_FUNC0_IN_SEL_S 0 -/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL (BIT(7)) #define GPIO_FUNC0_IN_INV_SEL_M (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S) #define GPIO_FUNC0_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC0_IN_INV_SEL_S 6 -/** GPIO_SIG0_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC0_IN_INV_SEL_S 7 +/** GPIO_SIG0_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG0_IN_SEL (BIT(7)) +#define GPIO_SIG0_IN_SEL (BIT(8)) #define GPIO_SIG0_IN_SEL_M (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S) #define GPIO_SIG0_IN_SEL_V 0x00000001U -#define GPIO_SIG0_IN_SEL_S 7 +#define GPIO_SIG0_IN_SEL_S 8 /** GPIO_FUNC6_IN_SEL_CFG_REG register - * Configuration register for input signal 6 + * GPIO input function configuration register */ -#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc) -/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 6.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) +/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC6_IN_SEL 0x0000003FU +#define GPIO_FUNC6_IN_SEL 0x0000007FU #define GPIO_FUNC6_IN_SEL_M (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S) -#define GPIO_FUNC6_IN_SEL_V 0x0000003FU +#define GPIO_FUNC6_IN_SEL_V 0x0000007FU #define GPIO_FUNC6_IN_SEL_S 0 -/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC6_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL (BIT(7)) #define GPIO_FUNC6_IN_INV_SEL_M (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S) #define GPIO_FUNC6_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC6_IN_INV_SEL_S 6 -/** GPIO_SIG6_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC6_IN_INV_SEL_S 7 +/** GPIO_SIG6_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG6_IN_SEL (BIT(7)) +#define GPIO_SIG6_IN_SEL (BIT(8)) #define GPIO_SIG6_IN_SEL_M (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S) #define GPIO_SIG6_IN_SEL_V 0x00000001U -#define GPIO_SIG6_IN_SEL_S 7 +#define GPIO_SIG6_IN_SEL_S 8 /** GPIO_FUNC7_IN_SEL_CFG_REG register - * Configuration register for input signal 7 + * GPIO input function configuration register */ -#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0) -/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 7.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) +/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC7_IN_SEL 0x0000003FU +#define GPIO_FUNC7_IN_SEL 0x0000007FU #define GPIO_FUNC7_IN_SEL_M (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S) -#define GPIO_FUNC7_IN_SEL_V 0x0000003FU +#define GPIO_FUNC7_IN_SEL_V 0x0000007FU #define GPIO_FUNC7_IN_SEL_S 0 -/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC7_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL (BIT(7)) #define GPIO_FUNC7_IN_INV_SEL_M (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S) #define GPIO_FUNC7_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC7_IN_INV_SEL_S 6 -/** GPIO_SIG7_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC7_IN_INV_SEL_S 7 +/** GPIO_SIG7_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG7_IN_SEL (BIT(7)) +#define GPIO_SIG7_IN_SEL (BIT(8)) #define GPIO_SIG7_IN_SEL_M (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S) #define GPIO_SIG7_IN_SEL_V 0x00000001U -#define GPIO_SIG7_IN_SEL_S 7 +#define GPIO_SIG7_IN_SEL_S 8 /** GPIO_FUNC8_IN_SEL_CFG_REG register - * Configuration register for input signal 8 + * GPIO input function configuration register */ -#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4) -/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 8.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) +/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC8_IN_SEL 0x0000003FU +#define GPIO_FUNC8_IN_SEL 0x0000007FU #define GPIO_FUNC8_IN_SEL_M (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S) -#define GPIO_FUNC8_IN_SEL_V 0x0000003FU +#define GPIO_FUNC8_IN_SEL_V 0x0000007FU #define GPIO_FUNC8_IN_SEL_S 0 -/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC8_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL (BIT(7)) #define GPIO_FUNC8_IN_INV_SEL_M (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S) #define GPIO_FUNC8_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC8_IN_INV_SEL_S 6 -/** GPIO_SIG8_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC8_IN_INV_SEL_S 7 +/** GPIO_SIG8_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG8_IN_SEL (BIT(7)) +#define GPIO_SIG8_IN_SEL (BIT(8)) #define GPIO_SIG8_IN_SEL_M (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S) #define GPIO_SIG8_IN_SEL_V 0x00000001U -#define GPIO_SIG8_IN_SEL_S 7 +#define GPIO_SIG8_IN_SEL_S 8 /** GPIO_FUNC9_IN_SEL_CFG_REG register - * Configuration register for input signal 9 + * GPIO input function configuration register */ -#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8) -/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 9.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) +/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [6:0]; default: 64; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC9_IN_SEL 0x0000003FU +#define GPIO_FUNC9_IN_SEL 0x0000007FU #define GPIO_FUNC9_IN_SEL_M (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S) -#define GPIO_FUNC9_IN_SEL_V 0x0000003FU +#define GPIO_FUNC9_IN_SEL_V 0x0000007FU #define GPIO_FUNC9_IN_SEL_S 0 -/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC9_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL (BIT(7)) #define GPIO_FUNC9_IN_INV_SEL_M (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S) #define GPIO_FUNC9_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC9_IN_INV_SEL_S 6 -/** GPIO_SIG9_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC9_IN_INV_SEL_S 7 +/** GPIO_SIG9_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG9_IN_SEL (BIT(7)) +#define GPIO_SIG9_IN_SEL (BIT(8)) #define GPIO_SIG9_IN_SEL_M (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S) #define GPIO_SIG9_IN_SEL_V 0x00000001U -#define GPIO_SIG9_IN_SEL_S 7 +#define GPIO_SIG9_IN_SEL_S 8 /** GPIO_FUNC10_IN_SEL_CFG_REG register - * Configuration register for input signal 10 + * GPIO input function configuration register */ -#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) -/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 10.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) +/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC10_IN_SEL 0x0000003FU +#define GPIO_FUNC10_IN_SEL 0x0000007FU #define GPIO_FUNC10_IN_SEL_M (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S) -#define GPIO_FUNC10_IN_SEL_V 0x0000003FU +#define GPIO_FUNC10_IN_SEL_V 0x0000007FU #define GPIO_FUNC10_IN_SEL_S 0 -/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC10_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL (BIT(7)) #define GPIO_FUNC10_IN_INV_SEL_M (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S) #define GPIO_FUNC10_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC10_IN_INV_SEL_S 6 -/** GPIO_SIG10_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC10_IN_INV_SEL_S 7 +/** GPIO_SIG10_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG10_IN_SEL (BIT(7)) +#define GPIO_SIG10_IN_SEL (BIT(8)) #define GPIO_SIG10_IN_SEL_M (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S) #define GPIO_SIG10_IN_SEL_V 0x00000001U -#define GPIO_SIG10_IN_SEL_S 7 +#define GPIO_SIG10_IN_SEL_S 8 /** GPIO_FUNC11_IN_SEL_CFG_REG register - * Configuration register for input signal 11 + * GPIO input function configuration register */ -#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) -/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 11.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) +/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC11_IN_SEL 0x0000003FU +#define GPIO_FUNC11_IN_SEL 0x0000007FU #define GPIO_FUNC11_IN_SEL_M (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S) -#define GPIO_FUNC11_IN_SEL_V 0x0000003FU +#define GPIO_FUNC11_IN_SEL_V 0x0000007FU #define GPIO_FUNC11_IN_SEL_S 0 -/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC11_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL (BIT(7)) #define GPIO_FUNC11_IN_INV_SEL_M (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S) #define GPIO_FUNC11_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC11_IN_INV_SEL_S 6 -/** GPIO_SIG11_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC11_IN_INV_SEL_S 7 +/** GPIO_SIG11_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG11_IN_SEL (BIT(7)) +#define GPIO_SIG11_IN_SEL (BIT(8)) #define GPIO_SIG11_IN_SEL_M (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S) #define GPIO_SIG11_IN_SEL_V 0x00000001U -#define GPIO_SIG11_IN_SEL_S 7 +#define GPIO_SIG11_IN_SEL_S 8 /** GPIO_FUNC12_IN_SEL_CFG_REG register - * Configuration register for input signal 12 + * GPIO input function configuration register */ -#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) -/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 12.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) +/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC12_IN_SEL 0x0000003FU +#define GPIO_FUNC12_IN_SEL 0x0000007FU #define GPIO_FUNC12_IN_SEL_M (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S) -#define GPIO_FUNC12_IN_SEL_V 0x0000003FU +#define GPIO_FUNC12_IN_SEL_V 0x0000007FU #define GPIO_FUNC12_IN_SEL_S 0 -/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC12_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL (BIT(7)) #define GPIO_FUNC12_IN_INV_SEL_M (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S) #define GPIO_FUNC12_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC12_IN_INV_SEL_S 6 -/** GPIO_SIG12_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC12_IN_INV_SEL_S 7 +/** GPIO_SIG12_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG12_IN_SEL (BIT(7)) +#define GPIO_SIG12_IN_SEL (BIT(8)) #define GPIO_SIG12_IN_SEL_M (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S) #define GPIO_SIG12_IN_SEL_V 0x00000001U -#define GPIO_SIG12_IN_SEL_S 7 +#define GPIO_SIG12_IN_SEL_S 8 /** GPIO_FUNC13_IN_SEL_CFG_REG register - * Configuration register for input signal 13 + * GPIO input function configuration register */ -#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) -/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 13.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) +/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC13_IN_SEL 0x0000003FU +#define GPIO_FUNC13_IN_SEL 0x0000007FU #define GPIO_FUNC13_IN_SEL_M (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S) -#define GPIO_FUNC13_IN_SEL_V 0x0000003FU +#define GPIO_FUNC13_IN_SEL_V 0x0000007FU #define GPIO_FUNC13_IN_SEL_S 0 -/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC13_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL (BIT(7)) #define GPIO_FUNC13_IN_INV_SEL_M (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S) #define GPIO_FUNC13_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC13_IN_INV_SEL_S 6 -/** GPIO_SIG13_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC13_IN_INV_SEL_S 7 +/** GPIO_SIG13_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG13_IN_SEL (BIT(7)) +#define GPIO_SIG13_IN_SEL (BIT(8)) #define GPIO_SIG13_IN_SEL_M (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S) #define GPIO_SIG13_IN_SEL_V 0x00000001U -#define GPIO_SIG13_IN_SEL_S 7 +#define GPIO_SIG13_IN_SEL_S 8 /** GPIO_FUNC14_IN_SEL_CFG_REG register - * Configuration register for input signal 14 + * GPIO input function configuration register */ -#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) -/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 14.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c) +/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC14_IN_SEL 0x0000003FU +#define GPIO_FUNC14_IN_SEL 0x0000007FU #define GPIO_FUNC14_IN_SEL_M (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S) -#define GPIO_FUNC14_IN_SEL_V 0x0000003FU +#define GPIO_FUNC14_IN_SEL_V 0x0000007FU #define GPIO_FUNC14_IN_SEL_S 0 -/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC14_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL (BIT(7)) #define GPIO_FUNC14_IN_INV_SEL_M (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S) #define GPIO_FUNC14_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC14_IN_INV_SEL_S 6 -/** GPIO_SIG14_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC14_IN_INV_SEL_S 7 +/** GPIO_SIG14_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG14_IN_SEL (BIT(7)) +#define GPIO_SIG14_IN_SEL (BIT(8)) #define GPIO_SIG14_IN_SEL_M (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S) #define GPIO_SIG14_IN_SEL_V 0x00000001U -#define GPIO_SIG14_IN_SEL_S 7 +#define GPIO_SIG14_IN_SEL_S 8 /** GPIO_FUNC15_IN_SEL_CFG_REG register - * Configuration register for input signal 15 + * GPIO input function configuration register */ -#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) -/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 15.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) +/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC15_IN_SEL 0x0000003FU +#define GPIO_FUNC15_IN_SEL 0x0000007FU #define GPIO_FUNC15_IN_SEL_M (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S) -#define GPIO_FUNC15_IN_SEL_V 0x0000003FU +#define GPIO_FUNC15_IN_SEL_V 0x0000007FU #define GPIO_FUNC15_IN_SEL_S 0 -/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC15_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL (BIT(7)) #define GPIO_FUNC15_IN_INV_SEL_M (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S) #define GPIO_FUNC15_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC15_IN_INV_SEL_S 6 -/** GPIO_SIG15_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC15_IN_INV_SEL_S 7 +/** GPIO_SIG15_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG15_IN_SEL (BIT(7)) +#define GPIO_SIG15_IN_SEL (BIT(8)) #define GPIO_SIG15_IN_SEL_M (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S) #define GPIO_SIG15_IN_SEL_V 0x00000001U -#define GPIO_SIG15_IN_SEL_S 7 +#define GPIO_SIG15_IN_SEL_S 8 /** GPIO_FUNC16_IN_SEL_CFG_REG register - * Configuration register for input signal 16 + * GPIO input function configuration register */ -#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) -/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 16.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) +/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC16_IN_SEL 0x0000003FU +#define GPIO_FUNC16_IN_SEL 0x0000007FU #define GPIO_FUNC16_IN_SEL_M (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S) -#define GPIO_FUNC16_IN_SEL_V 0x0000003FU +#define GPIO_FUNC16_IN_SEL_V 0x0000007FU #define GPIO_FUNC16_IN_SEL_S 0 -/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC16_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL (BIT(7)) #define GPIO_FUNC16_IN_INV_SEL_M (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S) #define GPIO_FUNC16_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC16_IN_INV_SEL_S 6 -/** GPIO_SIG16_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC16_IN_INV_SEL_S 7 +/** GPIO_SIG16_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG16_IN_SEL (BIT(7)) +#define GPIO_SIG16_IN_SEL (BIT(8)) #define GPIO_SIG16_IN_SEL_M (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S) #define GPIO_SIG16_IN_SEL_V 0x00000001U -#define GPIO_SIG16_IN_SEL_S 7 +#define GPIO_SIG16_IN_SEL_S 8 /** GPIO_FUNC17_IN_SEL_CFG_REG register - * Configuration register for input signal 17 + * GPIO input function configuration register */ -#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) -/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 17.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) +/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC17_IN_SEL 0x0000003FU +#define GPIO_FUNC17_IN_SEL 0x0000007FU #define GPIO_FUNC17_IN_SEL_M (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S) -#define GPIO_FUNC17_IN_SEL_V 0x0000003FU +#define GPIO_FUNC17_IN_SEL_V 0x0000007FU #define GPIO_FUNC17_IN_SEL_S 0 -/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC17_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL (BIT(7)) #define GPIO_FUNC17_IN_INV_SEL_M (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S) #define GPIO_FUNC17_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC17_IN_INV_SEL_S 6 -/** GPIO_SIG17_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC17_IN_INV_SEL_S 7 +/** GPIO_SIG17_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG17_IN_SEL (BIT(7)) +#define GPIO_SIG17_IN_SEL (BIT(8)) #define GPIO_SIG17_IN_SEL_M (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S) #define GPIO_SIG17_IN_SEL_V 0x00000001U -#define GPIO_SIG17_IN_SEL_S 7 +#define GPIO_SIG17_IN_SEL_S 8 /** GPIO_FUNC27_IN_SEL_CFG_REG register - * Configuration register for input signal 27 + * GPIO input function configuration register */ -#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) -/** GPIO_FUNC27_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 27.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) +/** GPIO_FUNC27_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC27_IN_SEL 0x0000003FU +#define GPIO_FUNC27_IN_SEL 0x0000007FU #define GPIO_FUNC27_IN_SEL_M (GPIO_FUNC27_IN_SEL_V << GPIO_FUNC27_IN_SEL_S) -#define GPIO_FUNC27_IN_SEL_V 0x0000003FU +#define GPIO_FUNC27_IN_SEL_V 0x0000007FU #define GPIO_FUNC27_IN_SEL_S 0 -/** GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC27_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC27_IN_INV_SEL (BIT(7)) #define GPIO_FUNC27_IN_INV_SEL_M (GPIO_FUNC27_IN_INV_SEL_V << GPIO_FUNC27_IN_INV_SEL_S) #define GPIO_FUNC27_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC27_IN_INV_SEL_S 6 -/** GPIO_SIG27_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC27_IN_INV_SEL_S 7 +/** GPIO_SIG27_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG27_IN_SEL (BIT(7)) +#define GPIO_SIG27_IN_SEL (BIT(8)) #define GPIO_SIG27_IN_SEL_M (GPIO_SIG27_IN_SEL_V << GPIO_SIG27_IN_SEL_S) #define GPIO_SIG27_IN_SEL_V 0x00000001U -#define GPIO_SIG27_IN_SEL_S 7 +#define GPIO_SIG27_IN_SEL_S 8 /** GPIO_FUNC28_IN_SEL_CFG_REG register - * Configuration register for input signal 28 + * GPIO input function configuration register */ -#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) -/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 28.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) +/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC28_IN_SEL 0x0000003FU +#define GPIO_FUNC28_IN_SEL 0x0000007FU #define GPIO_FUNC28_IN_SEL_M (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S) -#define GPIO_FUNC28_IN_SEL_V 0x0000003FU +#define GPIO_FUNC28_IN_SEL_V 0x0000007FU #define GPIO_FUNC28_IN_SEL_S 0 -/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC28_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL (BIT(7)) #define GPIO_FUNC28_IN_INV_SEL_M (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S) #define GPIO_FUNC28_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC28_IN_INV_SEL_S 6 -/** GPIO_SIG28_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC28_IN_INV_SEL_S 7 +/** GPIO_SIG28_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG28_IN_SEL (BIT(7)) +#define GPIO_SIG28_IN_SEL (BIT(8)) #define GPIO_SIG28_IN_SEL_M (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S) #define GPIO_SIG28_IN_SEL_V 0x00000001U -#define GPIO_SIG28_IN_SEL_S 7 +#define GPIO_SIG28_IN_SEL_S 8 /** GPIO_FUNC29_IN_SEL_CFG_REG register - * Configuration register for input signal 29 + * GPIO input function configuration register */ -#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) -/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 29.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) +/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC29_IN_SEL 0x0000003FU +#define GPIO_FUNC29_IN_SEL 0x0000007FU #define GPIO_FUNC29_IN_SEL_M (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S) -#define GPIO_FUNC29_IN_SEL_V 0x0000003FU +#define GPIO_FUNC29_IN_SEL_V 0x0000007FU #define GPIO_FUNC29_IN_SEL_S 0 -/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC29_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL (BIT(7)) #define GPIO_FUNC29_IN_INV_SEL_M (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S) #define GPIO_FUNC29_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC29_IN_INV_SEL_S 6 -/** GPIO_SIG29_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC29_IN_INV_SEL_S 7 +/** GPIO_SIG29_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG29_IN_SEL (BIT(7)) +#define GPIO_SIG29_IN_SEL (BIT(8)) #define GPIO_SIG29_IN_SEL_M (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S) #define GPIO_SIG29_IN_SEL_V 0x00000001U -#define GPIO_SIG29_IN_SEL_S 7 +#define GPIO_SIG29_IN_SEL_S 8 /** GPIO_FUNC30_IN_SEL_CFG_REG register - * Configuration register for input signal 30 + * GPIO input function configuration register */ -#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c) -/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 30.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c) +/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC30_IN_SEL 0x0000003FU +#define GPIO_FUNC30_IN_SEL 0x0000007FU #define GPIO_FUNC30_IN_SEL_M (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S) -#define GPIO_FUNC30_IN_SEL_V 0x0000003FU +#define GPIO_FUNC30_IN_SEL_V 0x0000007FU #define GPIO_FUNC30_IN_SEL_S 0 -/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC30_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL (BIT(7)) #define GPIO_FUNC30_IN_INV_SEL_M (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S) #define GPIO_FUNC30_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC30_IN_INV_SEL_S 6 -/** GPIO_SIG30_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC30_IN_INV_SEL_S 7 +/** GPIO_SIG30_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG30_IN_SEL (BIT(7)) +#define GPIO_SIG30_IN_SEL (BIT(8)) #define GPIO_SIG30_IN_SEL_M (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S) #define GPIO_SIG30_IN_SEL_V 0x00000001U -#define GPIO_SIG30_IN_SEL_S 7 +#define GPIO_SIG30_IN_SEL_S 8 /** GPIO_FUNC31_IN_SEL_CFG_REG register - * Configuration register for input signal 31 + * GPIO input function configuration register */ -#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) -/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 31.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) +/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC31_IN_SEL 0x0000003FU +#define GPIO_FUNC31_IN_SEL 0x0000007FU #define GPIO_FUNC31_IN_SEL_M (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S) -#define GPIO_FUNC31_IN_SEL_V 0x0000003FU +#define GPIO_FUNC31_IN_SEL_V 0x0000007FU #define GPIO_FUNC31_IN_SEL_S 0 -/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC31_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL (BIT(7)) #define GPIO_FUNC31_IN_INV_SEL_M (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S) #define GPIO_FUNC31_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC31_IN_INV_SEL_S 6 -/** GPIO_SIG31_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC31_IN_INV_SEL_S 7 +/** GPIO_SIG31_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG31_IN_SEL (BIT(7)) +#define GPIO_SIG31_IN_SEL (BIT(8)) #define GPIO_SIG31_IN_SEL_M (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S) #define GPIO_SIG31_IN_SEL_V 0x00000001U -#define GPIO_SIG31_IN_SEL_S 7 +#define GPIO_SIG31_IN_SEL_S 8 /** GPIO_FUNC32_IN_SEL_CFG_REG register - * Configuration register for input signal 32 + * GPIO input function configuration register */ -#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) -/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 32.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x354) +/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC32_IN_SEL 0x0000003FU +#define GPIO_FUNC32_IN_SEL 0x0000007FU #define GPIO_FUNC32_IN_SEL_M (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S) -#define GPIO_FUNC32_IN_SEL_V 0x0000003FU +#define GPIO_FUNC32_IN_SEL_V 0x0000007FU #define GPIO_FUNC32_IN_SEL_S 0 -/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC32_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL (BIT(7)) #define GPIO_FUNC32_IN_INV_SEL_M (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S) #define GPIO_FUNC32_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC32_IN_INV_SEL_S 6 -/** GPIO_SIG32_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC32_IN_INV_SEL_S 7 +/** GPIO_SIG32_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG32_IN_SEL (BIT(7)) +#define GPIO_SIG32_IN_SEL (BIT(8)) #define GPIO_SIG32_IN_SEL_M (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S) #define GPIO_SIG32_IN_SEL_V 0x00000001U -#define GPIO_SIG32_IN_SEL_S 7 +#define GPIO_SIG32_IN_SEL_S 8 /** GPIO_FUNC33_IN_SEL_CFG_REG register - * Configuration register for input signal 33 + * GPIO input function configuration register */ -#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) -/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 33.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x358) +/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC33_IN_SEL 0x0000003FU +#define GPIO_FUNC33_IN_SEL 0x0000007FU #define GPIO_FUNC33_IN_SEL_M (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S) -#define GPIO_FUNC33_IN_SEL_V 0x0000003FU +#define GPIO_FUNC33_IN_SEL_V 0x0000007FU #define GPIO_FUNC33_IN_SEL_S 0 -/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC33_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL (BIT(7)) #define GPIO_FUNC33_IN_INV_SEL_M (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S) #define GPIO_FUNC33_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC33_IN_INV_SEL_S 6 -/** GPIO_SIG33_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC33_IN_INV_SEL_S 7 +/** GPIO_SIG33_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG33_IN_SEL (BIT(7)) +#define GPIO_SIG33_IN_SEL (BIT(8)) #define GPIO_SIG33_IN_SEL_M (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S) #define GPIO_SIG33_IN_SEL_V 0x00000001U -#define GPIO_SIG33_IN_SEL_S 7 +#define GPIO_SIG33_IN_SEL_S 8 /** GPIO_FUNC34_IN_SEL_CFG_REG register - * Configuration register for input signal 34 + * GPIO input function configuration register */ -#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c) -/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 34.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x35c) +/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC34_IN_SEL 0x0000003FU +#define GPIO_FUNC34_IN_SEL 0x0000007FU #define GPIO_FUNC34_IN_SEL_M (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S) -#define GPIO_FUNC34_IN_SEL_V 0x0000003FU +#define GPIO_FUNC34_IN_SEL_V 0x0000007FU #define GPIO_FUNC34_IN_SEL_S 0 -/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC34_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL (BIT(7)) #define GPIO_FUNC34_IN_INV_SEL_M (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S) #define GPIO_FUNC34_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC34_IN_INV_SEL_S 6 -/** GPIO_SIG34_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC34_IN_INV_SEL_S 7 +/** GPIO_SIG34_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG34_IN_SEL (BIT(7)) +#define GPIO_SIG34_IN_SEL (BIT(8)) #define GPIO_SIG34_IN_SEL_M (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S) #define GPIO_SIG34_IN_SEL_V 0x00000001U -#define GPIO_SIG34_IN_SEL_S 7 +#define GPIO_SIG34_IN_SEL_S 8 /** GPIO_FUNC35_IN_SEL_CFG_REG register - * Configuration register for input signal 35 + * GPIO input function configuration register */ -#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) -/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 35.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x360) +/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC35_IN_SEL 0x0000003FU +#define GPIO_FUNC35_IN_SEL 0x0000007FU #define GPIO_FUNC35_IN_SEL_M (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S) -#define GPIO_FUNC35_IN_SEL_V 0x0000003FU +#define GPIO_FUNC35_IN_SEL_V 0x0000007FU #define GPIO_FUNC35_IN_SEL_S 0 -/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC35_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL (BIT(7)) #define GPIO_FUNC35_IN_INV_SEL_M (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S) #define GPIO_FUNC35_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC35_IN_INV_SEL_S 6 -/** GPIO_SIG35_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC35_IN_INV_SEL_S 7 +/** GPIO_SIG35_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG35_IN_SEL (BIT(7)) +#define GPIO_SIG35_IN_SEL (BIT(8)) #define GPIO_SIG35_IN_SEL_M (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S) #define GPIO_SIG35_IN_SEL_V 0x00000001U -#define GPIO_SIG35_IN_SEL_S 7 +#define GPIO_SIG35_IN_SEL_S 8 /** GPIO_FUNC41_IN_SEL_CFG_REG register - * Configuration register for input signal 41 + * GPIO input function configuration register */ -#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x368) -/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 41.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x378) +/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC41_IN_SEL 0x0000003FU +#define GPIO_FUNC41_IN_SEL 0x0000007FU #define GPIO_FUNC41_IN_SEL_M (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S) -#define GPIO_FUNC41_IN_SEL_V 0x0000003FU +#define GPIO_FUNC41_IN_SEL_V 0x0000007FU #define GPIO_FUNC41_IN_SEL_S 0 -/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC41_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL (BIT(7)) #define GPIO_FUNC41_IN_INV_SEL_M (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S) #define GPIO_FUNC41_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC41_IN_INV_SEL_S 6 -/** GPIO_SIG41_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC41_IN_INV_SEL_S 7 +/** GPIO_SIG41_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG41_IN_SEL (BIT(7)) +#define GPIO_SIG41_IN_SEL (BIT(8)) #define GPIO_SIG41_IN_SEL_M (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S) #define GPIO_SIG41_IN_SEL_V 0x00000001U -#define GPIO_SIG41_IN_SEL_S 7 +#define GPIO_SIG41_IN_SEL_S 8 /** GPIO_FUNC42_IN_SEL_CFG_REG register - * Configuration register for input signal 42 + * GPIO input function configuration register */ -#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x36c) -/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 42.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x37c) +/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC42_IN_SEL 0x0000003FU +#define GPIO_FUNC42_IN_SEL 0x0000007FU #define GPIO_FUNC42_IN_SEL_M (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S) -#define GPIO_FUNC42_IN_SEL_V 0x0000003FU +#define GPIO_FUNC42_IN_SEL_V 0x0000007FU #define GPIO_FUNC42_IN_SEL_S 0 -/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC42_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL (BIT(7)) #define GPIO_FUNC42_IN_INV_SEL_M (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S) #define GPIO_FUNC42_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC42_IN_INV_SEL_S 6 -/** GPIO_SIG42_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC42_IN_INV_SEL_S 7 +/** GPIO_SIG42_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG42_IN_SEL (BIT(7)) +#define GPIO_SIG42_IN_SEL (BIT(8)) #define GPIO_SIG42_IN_SEL_M (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S) #define GPIO_SIG42_IN_SEL_V 0x00000001U -#define GPIO_SIG42_IN_SEL_S 7 +#define GPIO_SIG42_IN_SEL_S 8 /** GPIO_FUNC43_IN_SEL_CFG_REG register - * Configuration register for input signal 43 + * GPIO input function configuration register */ -#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x370) -/** GPIO_FUNC43_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 43.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x380) +/** GPIO_FUNC43_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC43_IN_SEL 0x0000003FU +#define GPIO_FUNC43_IN_SEL 0x0000007FU #define GPIO_FUNC43_IN_SEL_M (GPIO_FUNC43_IN_SEL_V << GPIO_FUNC43_IN_SEL_S) -#define GPIO_FUNC43_IN_SEL_V 0x0000003FU +#define GPIO_FUNC43_IN_SEL_V 0x0000007FU #define GPIO_FUNC43_IN_SEL_S 0 -/** GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC43_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC43_IN_INV_SEL (BIT(7)) #define GPIO_FUNC43_IN_INV_SEL_M (GPIO_FUNC43_IN_INV_SEL_V << GPIO_FUNC43_IN_INV_SEL_S) #define GPIO_FUNC43_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC43_IN_INV_SEL_S 6 -/** GPIO_SIG43_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC43_IN_INV_SEL_S 7 +/** GPIO_SIG43_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG43_IN_SEL (BIT(7)) +#define GPIO_SIG43_IN_SEL (BIT(8)) #define GPIO_SIG43_IN_SEL_M (GPIO_SIG43_IN_SEL_V << GPIO_SIG43_IN_SEL_S) #define GPIO_SIG43_IN_SEL_V 0x00000001U -#define GPIO_SIG43_IN_SEL_S 7 +#define GPIO_SIG43_IN_SEL_S 8 /** GPIO_FUNC46_IN_SEL_CFG_REG register - * Configuration register for input signal 46 + * GPIO input function configuration register */ -#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x37c) -/** GPIO_FUNC46_IN_SEL : R/W; bitpos: [5:0]; default: 32; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 46.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x38c) +/** GPIO_FUNC46_IN_SEL : R/W; bitpos: [6:0]; default: 64; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC46_IN_SEL 0x0000003FU +#define GPIO_FUNC46_IN_SEL 0x0000007FU #define GPIO_FUNC46_IN_SEL_M (GPIO_FUNC46_IN_SEL_V << GPIO_FUNC46_IN_SEL_S) -#define GPIO_FUNC46_IN_SEL_V 0x0000003FU +#define GPIO_FUNC46_IN_SEL_V 0x0000007FU #define GPIO_FUNC46_IN_SEL_S 0 -/** GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC46_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL (BIT(7)) #define GPIO_FUNC46_IN_INV_SEL_M (GPIO_FUNC46_IN_INV_SEL_V << GPIO_FUNC46_IN_INV_SEL_S) #define GPIO_FUNC46_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC46_IN_INV_SEL_S 6 -/** GPIO_SIG46_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC46_IN_INV_SEL_S 7 +/** GPIO_SIG46_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG46_IN_SEL (BIT(7)) +#define GPIO_SIG46_IN_SEL (BIT(8)) #define GPIO_SIG46_IN_SEL_M (GPIO_SIG46_IN_SEL_V << GPIO_SIG46_IN_SEL_S) #define GPIO_SIG46_IN_SEL_V 0x00000001U -#define GPIO_SIG46_IN_SEL_S 7 +#define GPIO_SIG46_IN_SEL_S 8 /** GPIO_FUNC47_IN_SEL_CFG_REG register - * Configuration register for input signal 47 + * GPIO input function configuration register */ -#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x380) -/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [5:0]; default: 32; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 47.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x390) +/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [6:0]; default: 64; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC47_IN_SEL 0x0000003FU +#define GPIO_FUNC47_IN_SEL 0x0000007FU #define GPIO_FUNC47_IN_SEL_M (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S) -#define GPIO_FUNC47_IN_SEL_V 0x0000003FU +#define GPIO_FUNC47_IN_SEL_V 0x0000007FU #define GPIO_FUNC47_IN_SEL_S 0 -/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC47_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL (BIT(7)) #define GPIO_FUNC47_IN_INV_SEL_M (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S) #define GPIO_FUNC47_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC47_IN_INV_SEL_S 6 -/** GPIO_SIG47_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC47_IN_INV_SEL_S 7 +/** GPIO_SIG47_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG47_IN_SEL (BIT(7)) +#define GPIO_SIG47_IN_SEL (BIT(8)) #define GPIO_SIG47_IN_SEL_M (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S) #define GPIO_SIG47_IN_SEL_V 0x00000001U -#define GPIO_SIG47_IN_SEL_S 7 +#define GPIO_SIG47_IN_SEL_S 8 /** GPIO_FUNC64_IN_SEL_CFG_REG register - * Configuration register for input signal 64 + * GPIO input function configuration register */ -#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c4) -/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 64.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d4) +/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC64_IN_SEL 0x0000003FU +#define GPIO_FUNC64_IN_SEL 0x0000007FU #define GPIO_FUNC64_IN_SEL_M (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S) -#define GPIO_FUNC64_IN_SEL_V 0x0000003FU +#define GPIO_FUNC64_IN_SEL_V 0x0000007FU #define GPIO_FUNC64_IN_SEL_S 0 -/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC64_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL (BIT(7)) #define GPIO_FUNC64_IN_INV_SEL_M (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S) #define GPIO_FUNC64_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC64_IN_INV_SEL_S 6 -/** GPIO_SIG64_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC64_IN_INV_SEL_S 7 +/** GPIO_SIG64_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG64_IN_SEL (BIT(7)) +#define GPIO_SIG64_IN_SEL (BIT(8)) #define GPIO_SIG64_IN_SEL_M (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S) #define GPIO_SIG64_IN_SEL_V 0x00000001U -#define GPIO_SIG64_IN_SEL_S 7 +#define GPIO_SIG64_IN_SEL_S 8 /** GPIO_FUNC65_IN_SEL_CFG_REG register - * Configuration register for input signal 65 + * GPIO input function configuration register */ -#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c8) -/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 65.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d8) +/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC65_IN_SEL 0x0000003FU +#define GPIO_FUNC65_IN_SEL 0x0000007FU #define GPIO_FUNC65_IN_SEL_M (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S) -#define GPIO_FUNC65_IN_SEL_V 0x0000003FU +#define GPIO_FUNC65_IN_SEL_V 0x0000007FU #define GPIO_FUNC65_IN_SEL_S 0 -/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC65_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL (BIT(7)) #define GPIO_FUNC65_IN_INV_SEL_M (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S) #define GPIO_FUNC65_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC65_IN_INV_SEL_S 6 -/** GPIO_SIG65_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC65_IN_INV_SEL_S 7 +/** GPIO_SIG65_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG65_IN_SEL (BIT(7)) +#define GPIO_SIG65_IN_SEL (BIT(8)) #define GPIO_SIG65_IN_SEL_M (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S) #define GPIO_SIG65_IN_SEL_V 0x00000001U -#define GPIO_SIG65_IN_SEL_S 7 +#define GPIO_SIG65_IN_SEL_S 8 /** GPIO_FUNC66_IN_SEL_CFG_REG register - * Configuration register for input signal 66 + * GPIO input function configuration register */ -#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3cc) -/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 66.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3dc) +/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC66_IN_SEL 0x0000003FU +#define GPIO_FUNC66_IN_SEL 0x0000007FU #define GPIO_FUNC66_IN_SEL_M (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S) -#define GPIO_FUNC66_IN_SEL_V 0x0000003FU +#define GPIO_FUNC66_IN_SEL_V 0x0000007FU #define GPIO_FUNC66_IN_SEL_S 0 -/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC66_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL (BIT(7)) #define GPIO_FUNC66_IN_INV_SEL_M (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S) #define GPIO_FUNC66_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC66_IN_INV_SEL_S 6 -/** GPIO_SIG66_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC66_IN_INV_SEL_S 7 +/** GPIO_SIG66_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG66_IN_SEL (BIT(7)) +#define GPIO_SIG66_IN_SEL (BIT(8)) #define GPIO_SIG66_IN_SEL_M (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S) #define GPIO_SIG66_IN_SEL_V 0x00000001U -#define GPIO_SIG66_IN_SEL_S 7 +#define GPIO_SIG66_IN_SEL_S 8 /** GPIO_FUNC67_IN_SEL_CFG_REG register - * Configuration register for input signal 67 + * GPIO input function configuration register */ -#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d0) -/** GPIO_FUNC67_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 67.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e0) +/** GPIO_FUNC67_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC67_IN_SEL 0x0000003FU +#define GPIO_FUNC67_IN_SEL 0x0000007FU #define GPIO_FUNC67_IN_SEL_M (GPIO_FUNC67_IN_SEL_V << GPIO_FUNC67_IN_SEL_S) -#define GPIO_FUNC67_IN_SEL_V 0x0000003FU +#define GPIO_FUNC67_IN_SEL_V 0x0000007FU #define GPIO_FUNC67_IN_SEL_S 0 -/** GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC67_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL (BIT(7)) #define GPIO_FUNC67_IN_INV_SEL_M (GPIO_FUNC67_IN_INV_SEL_V << GPIO_FUNC67_IN_INV_SEL_S) #define GPIO_FUNC67_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC67_IN_INV_SEL_S 6 -/** GPIO_SIG67_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC67_IN_INV_SEL_S 7 +/** GPIO_SIG67_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG67_IN_SEL (BIT(7)) +#define GPIO_SIG67_IN_SEL (BIT(8)) #define GPIO_SIG67_IN_SEL_M (GPIO_SIG67_IN_SEL_V << GPIO_SIG67_IN_SEL_S) #define GPIO_SIG67_IN_SEL_V 0x00000001U -#define GPIO_SIG67_IN_SEL_S 7 +#define GPIO_SIG67_IN_SEL_S 8 /** GPIO_FUNC68_IN_SEL_CFG_REG register - * Configuration register for input signal 68 + * GPIO input function configuration register */ -#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d4) -/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 68.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e4) +/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC68_IN_SEL 0x0000003FU +#define GPIO_FUNC68_IN_SEL 0x0000007FU #define GPIO_FUNC68_IN_SEL_M (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S) -#define GPIO_FUNC68_IN_SEL_V 0x0000003FU +#define GPIO_FUNC68_IN_SEL_V 0x0000007FU #define GPIO_FUNC68_IN_SEL_S 0 -/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC68_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL (BIT(7)) #define GPIO_FUNC68_IN_INV_SEL_M (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S) #define GPIO_FUNC68_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC68_IN_INV_SEL_S 6 -/** GPIO_SIG68_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC68_IN_INV_SEL_S 7 +/** GPIO_SIG68_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG68_IN_SEL (BIT(7)) +#define GPIO_SIG68_IN_SEL (BIT(8)) #define GPIO_SIG68_IN_SEL_M (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S) #define GPIO_SIG68_IN_SEL_V 0x00000001U -#define GPIO_SIG68_IN_SEL_S 7 +#define GPIO_SIG68_IN_SEL_S 8 /** GPIO_FUNC69_IN_SEL_CFG_REG register - * Configuration register for input signal 69 + * GPIO input function configuration register */ -#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d8) -/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 69.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e8) +/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC69_IN_SEL 0x0000003FU +#define GPIO_FUNC69_IN_SEL 0x0000007FU #define GPIO_FUNC69_IN_SEL_M (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S) -#define GPIO_FUNC69_IN_SEL_V 0x0000003FU +#define GPIO_FUNC69_IN_SEL_V 0x0000007FU #define GPIO_FUNC69_IN_SEL_S 0 -/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC69_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL (BIT(7)) #define GPIO_FUNC69_IN_INV_SEL_M (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S) #define GPIO_FUNC69_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC69_IN_INV_SEL_S 6 -/** GPIO_SIG69_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC69_IN_INV_SEL_S 7 +/** GPIO_SIG69_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG69_IN_SEL (BIT(7)) +#define GPIO_SIG69_IN_SEL (BIT(8)) #define GPIO_SIG69_IN_SEL_M (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S) #define GPIO_SIG69_IN_SEL_V 0x00000001U -#define GPIO_SIG69_IN_SEL_S 7 +#define GPIO_SIG69_IN_SEL_S 8 /** GPIO_FUNC72_IN_SEL_CFG_REG register - * Configuration register for input signal 72 + * GPIO input function configuration register */ -#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e4) -/** GPIO_FUNC72_IN_SEL : R/W; bitpos: [5:0]; default: 32; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 72.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f4) +/** GPIO_FUNC72_IN_SEL : R/W; bitpos: [6:0]; default: 64; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC72_IN_SEL 0x0000003FU +#define GPIO_FUNC72_IN_SEL 0x0000007FU #define GPIO_FUNC72_IN_SEL_M (GPIO_FUNC72_IN_SEL_V << GPIO_FUNC72_IN_SEL_S) -#define GPIO_FUNC72_IN_SEL_V 0x0000003FU +#define GPIO_FUNC72_IN_SEL_V 0x0000007FU #define GPIO_FUNC72_IN_SEL_S 0 -/** GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC72_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL (BIT(7)) #define GPIO_FUNC72_IN_INV_SEL_M (GPIO_FUNC72_IN_INV_SEL_V << GPIO_FUNC72_IN_INV_SEL_S) #define GPIO_FUNC72_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC72_IN_INV_SEL_S 6 -/** GPIO_SIG72_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC72_IN_INV_SEL_S 7 +/** GPIO_SIG72_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG72_IN_SEL (BIT(7)) +#define GPIO_SIG72_IN_SEL (BIT(8)) #define GPIO_SIG72_IN_SEL_M (GPIO_SIG72_IN_SEL_V << GPIO_SIG72_IN_SEL_S) #define GPIO_SIG72_IN_SEL_V 0x00000001U -#define GPIO_SIG72_IN_SEL_S 7 +#define GPIO_SIG72_IN_SEL_S 8 /** GPIO_FUNC73_IN_SEL_CFG_REG register - * Configuration register for input signal 73 + * GPIO input function configuration register */ -#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e8) -/** GPIO_FUNC73_IN_SEL : R/W; bitpos: [5:0]; default: 32; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 73.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f8) +/** GPIO_FUNC73_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC73_IN_SEL 0x0000003FU +#define GPIO_FUNC73_IN_SEL 0x0000007FU #define GPIO_FUNC73_IN_SEL_M (GPIO_FUNC73_IN_SEL_V << GPIO_FUNC73_IN_SEL_S) -#define GPIO_FUNC73_IN_SEL_V 0x0000003FU +#define GPIO_FUNC73_IN_SEL_V 0x0000007FU #define GPIO_FUNC73_IN_SEL_S 0 -/** GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC73_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL (BIT(7)) #define GPIO_FUNC73_IN_INV_SEL_M (GPIO_FUNC73_IN_INV_SEL_V << GPIO_FUNC73_IN_INV_SEL_S) #define GPIO_FUNC73_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC73_IN_INV_SEL_S 6 -/** GPIO_SIG73_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC73_IN_INV_SEL_S 7 +/** GPIO_SIG73_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG73_IN_SEL (BIT(7)) +#define GPIO_SIG73_IN_SEL (BIT(8)) #define GPIO_SIG73_IN_SEL_M (GPIO_SIG73_IN_SEL_V << GPIO_SIG73_IN_SEL_S) #define GPIO_SIG73_IN_SEL_V 0x00000001U -#define GPIO_SIG73_IN_SEL_S 7 +#define GPIO_SIG73_IN_SEL_S 8 /** GPIO_FUNC74_IN_SEL_CFG_REG register - * Configuration register for input signal 74 + * GPIO input function configuration register */ -#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ec) -/** GPIO_FUNC74_IN_SEL : R/W; bitpos: [5:0]; default: 32; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 74.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3fc) +/** GPIO_FUNC74_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC74_IN_SEL 0x0000003FU +#define GPIO_FUNC74_IN_SEL 0x0000007FU #define GPIO_FUNC74_IN_SEL_M (GPIO_FUNC74_IN_SEL_V << GPIO_FUNC74_IN_SEL_S) -#define GPIO_FUNC74_IN_SEL_V 0x0000003FU +#define GPIO_FUNC74_IN_SEL_V 0x0000007FU #define GPIO_FUNC74_IN_SEL_S 0 -/** GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC74_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC74_IN_INV_SEL (BIT(7)) #define GPIO_FUNC74_IN_INV_SEL_M (GPIO_FUNC74_IN_INV_SEL_V << GPIO_FUNC74_IN_INV_SEL_S) #define GPIO_FUNC74_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC74_IN_INV_SEL_S 6 -/** GPIO_SIG74_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC74_IN_INV_SEL_S 7 +/** GPIO_SIG74_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG74_IN_SEL (BIT(7)) +#define GPIO_SIG74_IN_SEL (BIT(8)) #define GPIO_SIG74_IN_SEL_M (GPIO_SIG74_IN_SEL_V << GPIO_SIG74_IN_SEL_S) #define GPIO_SIG74_IN_SEL_V 0x00000001U -#define GPIO_SIG74_IN_SEL_S 7 +#define GPIO_SIG74_IN_SEL_S 8 /** GPIO_FUNC82_IN_SEL_CFG_REG register - * Configuration register for input signal 82 + * GPIO input function configuration register */ -#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x40c) -/** GPIO_FUNC82_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 82.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x41c) +/** GPIO_FUNC82_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC82_IN_SEL 0x0000003FU +#define GPIO_FUNC82_IN_SEL 0x0000007FU #define GPIO_FUNC82_IN_SEL_M (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S) -#define GPIO_FUNC82_IN_SEL_V 0x0000003FU +#define GPIO_FUNC82_IN_SEL_V 0x0000007FU #define GPIO_FUNC82_IN_SEL_S 0 -/** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC82_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL (BIT(7)) #define GPIO_FUNC82_IN_INV_SEL_M (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S) #define GPIO_FUNC82_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC82_IN_INV_SEL_S 6 -/** GPIO_SIG82_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC82_IN_INV_SEL_S 7 +/** GPIO_SIG82_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG82_IN_SEL (BIT(7)) +#define GPIO_SIG82_IN_SEL (BIT(8)) #define GPIO_SIG82_IN_SEL_M (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S) #define GPIO_SIG82_IN_SEL_V 0x00000001U -#define GPIO_SIG82_IN_SEL_S 7 +#define GPIO_SIG82_IN_SEL_S 8 /** GPIO_FUNC83_IN_SEL_CFG_REG register - * Configuration register for input signal 83 + * GPIO input function configuration register */ -#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x410) -/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 83.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x420) +/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC83_IN_SEL 0x0000003FU +#define GPIO_FUNC83_IN_SEL 0x0000007FU #define GPIO_FUNC83_IN_SEL_M (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S) -#define GPIO_FUNC83_IN_SEL_V 0x0000003FU +#define GPIO_FUNC83_IN_SEL_V 0x0000007FU #define GPIO_FUNC83_IN_SEL_S 0 -/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC83_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC83_IN_INV_SEL (BIT(7)) #define GPIO_FUNC83_IN_INV_SEL_M (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S) #define GPIO_FUNC83_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC83_IN_INV_SEL_S 6 -/** GPIO_SIG83_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC83_IN_INV_SEL_S 7 +/** GPIO_SIG83_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG83_IN_SEL (BIT(7)) +#define GPIO_SIG83_IN_SEL (BIT(8)) #define GPIO_SIG83_IN_SEL_M (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S) #define GPIO_SIG83_IN_SEL_V 0x00000001U -#define GPIO_SIG83_IN_SEL_S 7 +#define GPIO_SIG83_IN_SEL_S 8 /** GPIO_FUNC97_IN_SEL_CFG_REG register - * Configuration register for input signal 97 + * GPIO input function configuration register */ -#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x448) -/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 97.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x458) +/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC97_IN_SEL 0x0000003FU +#define GPIO_FUNC97_IN_SEL 0x0000007FU #define GPIO_FUNC97_IN_SEL_M (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S) -#define GPIO_FUNC97_IN_SEL_V 0x0000003FU +#define GPIO_FUNC97_IN_SEL_V 0x0000007FU #define GPIO_FUNC97_IN_SEL_S 0 -/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC97_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL (BIT(7)) #define GPIO_FUNC97_IN_INV_SEL_M (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S) #define GPIO_FUNC97_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC97_IN_INV_SEL_S 6 -/** GPIO_SIG97_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC97_IN_INV_SEL_S 7 +/** GPIO_SIG97_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG97_IN_SEL (BIT(7)) +#define GPIO_SIG97_IN_SEL (BIT(8)) #define GPIO_SIG97_IN_SEL_M (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S) #define GPIO_SIG97_IN_SEL_V 0x00000001U -#define GPIO_SIG97_IN_SEL_S 7 +#define GPIO_SIG97_IN_SEL_S 8 /** GPIO_FUNC98_IN_SEL_CFG_REG register - * Configuration register for input signal 98 + * GPIO input function configuration register */ -#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x44c) -/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 98.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x45c) +/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC98_IN_SEL 0x0000003FU +#define GPIO_FUNC98_IN_SEL 0x0000007FU #define GPIO_FUNC98_IN_SEL_M (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S) -#define GPIO_FUNC98_IN_SEL_V 0x0000003FU +#define GPIO_FUNC98_IN_SEL_V 0x0000007FU #define GPIO_FUNC98_IN_SEL_S 0 -/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC98_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL (BIT(7)) #define GPIO_FUNC98_IN_INV_SEL_M (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S) #define GPIO_FUNC98_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC98_IN_INV_SEL_S 6 -/** GPIO_SIG98_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC98_IN_INV_SEL_S 7 +/** GPIO_SIG98_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG98_IN_SEL (BIT(7)) +#define GPIO_SIG98_IN_SEL (BIT(8)) #define GPIO_SIG98_IN_SEL_M (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S) #define GPIO_SIG98_IN_SEL_V 0x00000001U -#define GPIO_SIG98_IN_SEL_S 7 +#define GPIO_SIG98_IN_SEL_S 8 /** GPIO_FUNC99_IN_SEL_CFG_REG register - * Configuration register for input signal 99 + * GPIO input function configuration register */ -#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x450) -/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 99.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x460) +/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC99_IN_SEL 0x0000003FU +#define GPIO_FUNC99_IN_SEL 0x0000007FU #define GPIO_FUNC99_IN_SEL_M (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S) -#define GPIO_FUNC99_IN_SEL_V 0x0000003FU +#define GPIO_FUNC99_IN_SEL_V 0x0000007FU #define GPIO_FUNC99_IN_SEL_S 0 -/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC99_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL (BIT(7)) #define GPIO_FUNC99_IN_INV_SEL_M (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S) #define GPIO_FUNC99_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC99_IN_INV_SEL_S 6 -/** GPIO_SIG99_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC99_IN_INV_SEL_S 7 +/** GPIO_SIG99_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG99_IN_SEL (BIT(7)) +#define GPIO_SIG99_IN_SEL (BIT(8)) #define GPIO_SIG99_IN_SEL_M (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S) #define GPIO_SIG99_IN_SEL_V 0x00000001U -#define GPIO_SIG99_IN_SEL_S 7 +#define GPIO_SIG99_IN_SEL_S 8 /** GPIO_FUNC100_IN_SEL_CFG_REG register - * Configuration register for input signal 100 + * GPIO input function configuration register */ -#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x454) -/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 100.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x464) +/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC100_IN_SEL 0x0000003FU +#define GPIO_FUNC100_IN_SEL 0x0000007FU #define GPIO_FUNC100_IN_SEL_M (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S) -#define GPIO_FUNC100_IN_SEL_V 0x0000003FU +#define GPIO_FUNC100_IN_SEL_V 0x0000007FU #define GPIO_FUNC100_IN_SEL_S 0 -/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC100_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL (BIT(7)) #define GPIO_FUNC100_IN_INV_SEL_M (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S) #define GPIO_FUNC100_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC100_IN_INV_SEL_S 6 -/** GPIO_SIG100_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC100_IN_INV_SEL_S 7 +/** GPIO_SIG100_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG100_IN_SEL (BIT(7)) +#define GPIO_SIG100_IN_SEL (BIT(8)) #define GPIO_SIG100_IN_SEL_M (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S) #define GPIO_SIG100_IN_SEL_V 0x00000001U -#define GPIO_SIG100_IN_SEL_S 7 +#define GPIO_SIG100_IN_SEL_S 8 /** GPIO_FUNC118_IN_SEL_CFG_REG register - * Configuration register for input signal 118 + * GPIO input function configuration register */ -#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x49c) -/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 118.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4ac) +/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC118_IN_SEL 0x0000003FU +#define GPIO_FUNC118_IN_SEL 0x0000007FU #define GPIO_FUNC118_IN_SEL_M (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S) -#define GPIO_FUNC118_IN_SEL_V 0x0000003FU +#define GPIO_FUNC118_IN_SEL_V 0x0000007FU #define GPIO_FUNC118_IN_SEL_S 0 -/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC118_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL (BIT(7)) #define GPIO_FUNC118_IN_INV_SEL_M (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S) #define GPIO_FUNC118_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC118_IN_INV_SEL_S 6 -/** GPIO_SIG118_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC118_IN_INV_SEL_S 7 +/** GPIO_SIG118_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG118_IN_SEL (BIT(7)) +#define GPIO_SIG118_IN_SEL (BIT(8)) #define GPIO_SIG118_IN_SEL_M (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S) #define GPIO_SIG118_IN_SEL_V 0x00000001U -#define GPIO_SIG118_IN_SEL_S 7 +#define GPIO_SIG118_IN_SEL_S 8 /** GPIO_FUNC119_IN_SEL_CFG_REG register - * Configuration register for input signal 119 + * GPIO input function configuration register */ -#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a0) -/** GPIO_FUNC119_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 119.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b0) +/** GPIO_FUNC119_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC119_IN_SEL 0x0000003FU +#define GPIO_FUNC119_IN_SEL 0x0000007FU #define GPIO_FUNC119_IN_SEL_M (GPIO_FUNC119_IN_SEL_V << GPIO_FUNC119_IN_SEL_S) -#define GPIO_FUNC119_IN_SEL_V 0x0000003FU +#define GPIO_FUNC119_IN_SEL_V 0x0000007FU #define GPIO_FUNC119_IN_SEL_S 0 -/** GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC119_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL (BIT(7)) #define GPIO_FUNC119_IN_INV_SEL_M (GPIO_FUNC119_IN_INV_SEL_V << GPIO_FUNC119_IN_INV_SEL_S) #define GPIO_FUNC119_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC119_IN_INV_SEL_S 6 -/** GPIO_SIG119_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC119_IN_INV_SEL_S 7 +/** GPIO_SIG119_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG119_IN_SEL (BIT(7)) +#define GPIO_SIG119_IN_SEL (BIT(8)) #define GPIO_SIG119_IN_SEL_M (GPIO_SIG119_IN_SEL_V << GPIO_SIG119_IN_SEL_S) #define GPIO_SIG119_IN_SEL_V 0x00000001U -#define GPIO_SIG119_IN_SEL_S 7 +#define GPIO_SIG119_IN_SEL_S 8 /** GPIO_FUNC120_IN_SEL_CFG_REG register - * Configuration register for input signal 120 + * GPIO input function configuration register */ -#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a4) -/** GPIO_FUNC120_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 120.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b4) +/** GPIO_FUNC120_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC120_IN_SEL 0x0000003FU +#define GPIO_FUNC120_IN_SEL 0x0000007FU #define GPIO_FUNC120_IN_SEL_M (GPIO_FUNC120_IN_SEL_V << GPIO_FUNC120_IN_SEL_S) -#define GPIO_FUNC120_IN_SEL_V 0x0000003FU +#define GPIO_FUNC120_IN_SEL_V 0x0000007FU #define GPIO_FUNC120_IN_SEL_S 0 -/** GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC120_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL (BIT(7)) #define GPIO_FUNC120_IN_INV_SEL_M (GPIO_FUNC120_IN_INV_SEL_V << GPIO_FUNC120_IN_INV_SEL_S) #define GPIO_FUNC120_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC120_IN_INV_SEL_S 6 -/** GPIO_SIG120_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC120_IN_INV_SEL_S 7 +/** GPIO_SIG120_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG120_IN_SEL (BIT(7)) +#define GPIO_SIG120_IN_SEL (BIT(8)) #define GPIO_SIG120_IN_SEL_M (GPIO_SIG120_IN_SEL_V << GPIO_SIG120_IN_SEL_S) #define GPIO_SIG120_IN_SEL_V 0x00000001U -#define GPIO_SIG120_IN_SEL_S 7 +#define GPIO_SIG120_IN_SEL_S 8 /** GPIO_FUNC121_IN_SEL_CFG_REG register - * Configuration register for input signal 121 + * GPIO input function configuration register */ -#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a8) -/** GPIO_FUNC121_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 121.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b8) +/** GPIO_FUNC121_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC121_IN_SEL 0x0000003FU +#define GPIO_FUNC121_IN_SEL 0x0000007FU #define GPIO_FUNC121_IN_SEL_M (GPIO_FUNC121_IN_SEL_V << GPIO_FUNC121_IN_SEL_S) -#define GPIO_FUNC121_IN_SEL_V 0x0000003FU +#define GPIO_FUNC121_IN_SEL_V 0x0000007FU #define GPIO_FUNC121_IN_SEL_S 0 -/** GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC121_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL (BIT(7)) #define GPIO_FUNC121_IN_INV_SEL_M (GPIO_FUNC121_IN_INV_SEL_V << GPIO_FUNC121_IN_INV_SEL_S) #define GPIO_FUNC121_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC121_IN_INV_SEL_S 6 -/** GPIO_SIG121_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC121_IN_INV_SEL_S 7 +/** GPIO_SIG121_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG121_IN_SEL (BIT(7)) +#define GPIO_SIG121_IN_SEL (BIT(8)) #define GPIO_SIG121_IN_SEL_M (GPIO_SIG121_IN_SEL_V << GPIO_SIG121_IN_SEL_S) #define GPIO_SIG121_IN_SEL_V 0x00000001U -#define GPIO_SIG121_IN_SEL_S 7 +#define GPIO_SIG121_IN_SEL_S 8 /** GPIO_FUNC0_OUT_SEL_CFG_REG register - * Configuration register for GPIO0 output + * GPIO output function select register */ -#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xac4) +#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad4) /** GPIO_FUNC0_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO0.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 0 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC0_OUT_SEL 0x000001FFU #define GPIO_FUNC0_OUT_SEL_M (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S) #define GPIO_FUNC0_OUT_SEL_V 0x000001FFU #define GPIO_FUNC0_OUT_SEL_S 0 /** GPIO_FUNC0_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC0_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC0_OUT_INV_SEL_M (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S) #define GPIO_FUNC0_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC0_OUT_INV_SEL_S 9 /** GPIO_FUNC0_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 0 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC0_OE_SEL (BIT(10)) #define GPIO_FUNC0_OE_SEL_M (GPIO_FUNC0_OE_SEL_V << GPIO_FUNC0_OE_SEL_S) #define GPIO_FUNC0_OE_SEL_V 0x00000001U #define GPIO_FUNC0_OE_SEL_S 10 /** GPIO_FUNC0_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC0_OE_INV_SEL (BIT(11)) #define GPIO_FUNC0_OE_INV_SEL_M (GPIO_FUNC0_OE_INV_SEL_V << GPIO_FUNC0_OE_INV_SEL_S) @@ -3910,51 +3348,35 @@ extern "C" { #define GPIO_FUNC0_OE_INV_SEL_S 11 /** GPIO_FUNC1_OUT_SEL_CFG_REG register - * Configuration register for GPIO1 output + * GPIO output function select register */ -#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xac8) +#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad8) /** GPIO_FUNC1_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO1.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 1 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC1_OUT_SEL 0x000001FFU #define GPIO_FUNC1_OUT_SEL_M (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S) #define GPIO_FUNC1_OUT_SEL_V 0x000001FFU #define GPIO_FUNC1_OUT_SEL_S 0 /** GPIO_FUNC1_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC1_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC1_OUT_INV_SEL_M (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S) #define GPIO_FUNC1_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC1_OUT_INV_SEL_S 9 /** GPIO_FUNC1_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 1 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC1_OE_SEL (BIT(10)) #define GPIO_FUNC1_OE_SEL_M (GPIO_FUNC1_OE_SEL_V << GPIO_FUNC1_OE_SEL_S) #define GPIO_FUNC1_OE_SEL_V 0x00000001U #define GPIO_FUNC1_OE_SEL_S 10 /** GPIO_FUNC1_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC1_OE_INV_SEL (BIT(11)) #define GPIO_FUNC1_OE_INV_SEL_M (GPIO_FUNC1_OE_INV_SEL_V << GPIO_FUNC1_OE_INV_SEL_S) @@ -3962,51 +3384,35 @@ extern "C" { #define GPIO_FUNC1_OE_INV_SEL_S 11 /** GPIO_FUNC2_OUT_SEL_CFG_REG register - * Configuration register for GPIO2 output + * GPIO output function select register */ -#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xacc) +#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xadc) /** GPIO_FUNC2_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO2.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 2 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC2_OUT_SEL 0x000001FFU #define GPIO_FUNC2_OUT_SEL_M (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S) #define GPIO_FUNC2_OUT_SEL_V 0x000001FFU #define GPIO_FUNC2_OUT_SEL_S 0 /** GPIO_FUNC2_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC2_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC2_OUT_INV_SEL_M (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S) #define GPIO_FUNC2_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC2_OUT_INV_SEL_S 9 /** GPIO_FUNC2_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 2 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC2_OE_SEL (BIT(10)) #define GPIO_FUNC2_OE_SEL_M (GPIO_FUNC2_OE_SEL_V << GPIO_FUNC2_OE_SEL_S) #define GPIO_FUNC2_OE_SEL_V 0x00000001U #define GPIO_FUNC2_OE_SEL_S 10 /** GPIO_FUNC2_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC2_OE_INV_SEL (BIT(11)) #define GPIO_FUNC2_OE_INV_SEL_M (GPIO_FUNC2_OE_INV_SEL_V << GPIO_FUNC2_OE_INV_SEL_S) @@ -4014,51 +3420,35 @@ extern "C" { #define GPIO_FUNC2_OE_INV_SEL_S 11 /** GPIO_FUNC3_OUT_SEL_CFG_REG register - * Configuration register for GPIO3 output + * GPIO output function select register */ -#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad0) +#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae0) /** GPIO_FUNC3_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO3.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 3 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC3_OUT_SEL 0x000001FFU #define GPIO_FUNC3_OUT_SEL_M (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S) #define GPIO_FUNC3_OUT_SEL_V 0x000001FFU #define GPIO_FUNC3_OUT_SEL_S 0 /** GPIO_FUNC3_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC3_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC3_OUT_INV_SEL_M (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S) #define GPIO_FUNC3_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC3_OUT_INV_SEL_S 9 /** GPIO_FUNC3_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 3 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC3_OE_SEL (BIT(10)) #define GPIO_FUNC3_OE_SEL_M (GPIO_FUNC3_OE_SEL_V << GPIO_FUNC3_OE_SEL_S) #define GPIO_FUNC3_OE_SEL_V 0x00000001U #define GPIO_FUNC3_OE_SEL_S 10 /** GPIO_FUNC3_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC3_OE_INV_SEL (BIT(11)) #define GPIO_FUNC3_OE_INV_SEL_M (GPIO_FUNC3_OE_INV_SEL_V << GPIO_FUNC3_OE_INV_SEL_S) @@ -4066,51 +3456,35 @@ extern "C" { #define GPIO_FUNC3_OE_INV_SEL_S 11 /** GPIO_FUNC4_OUT_SEL_CFG_REG register - * Configuration register for GPIO4 output + * GPIO output function select register */ -#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad4) +#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae4) /** GPIO_FUNC4_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO4.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 4 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC4_OUT_SEL 0x000001FFU #define GPIO_FUNC4_OUT_SEL_M (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S) #define GPIO_FUNC4_OUT_SEL_V 0x000001FFU #define GPIO_FUNC4_OUT_SEL_S 0 /** GPIO_FUNC4_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC4_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC4_OUT_INV_SEL_M (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S) #define GPIO_FUNC4_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC4_OUT_INV_SEL_S 9 /** GPIO_FUNC4_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 4 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC4_OE_SEL (BIT(10)) #define GPIO_FUNC4_OE_SEL_M (GPIO_FUNC4_OE_SEL_V << GPIO_FUNC4_OE_SEL_S) #define GPIO_FUNC4_OE_SEL_V 0x00000001U #define GPIO_FUNC4_OE_SEL_S 10 /** GPIO_FUNC4_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC4_OE_INV_SEL (BIT(11)) #define GPIO_FUNC4_OE_INV_SEL_M (GPIO_FUNC4_OE_INV_SEL_V << GPIO_FUNC4_OE_INV_SEL_S) @@ -4118,51 +3492,35 @@ extern "C" { #define GPIO_FUNC4_OE_INV_SEL_S 11 /** GPIO_FUNC5_OUT_SEL_CFG_REG register - * Configuration register for GPIO5 output + * GPIO output function select register */ -#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad8) +#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae8) /** GPIO_FUNC5_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO5.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 5 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC5_OUT_SEL 0x000001FFU #define GPIO_FUNC5_OUT_SEL_M (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S) #define GPIO_FUNC5_OUT_SEL_V 0x000001FFU #define GPIO_FUNC5_OUT_SEL_S 0 /** GPIO_FUNC5_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC5_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC5_OUT_INV_SEL_M (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S) #define GPIO_FUNC5_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC5_OUT_INV_SEL_S 9 /** GPIO_FUNC5_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 5 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC5_OE_SEL (BIT(10)) #define GPIO_FUNC5_OE_SEL_M (GPIO_FUNC5_OE_SEL_V << GPIO_FUNC5_OE_SEL_S) #define GPIO_FUNC5_OE_SEL_V 0x00000001U #define GPIO_FUNC5_OE_SEL_S 10 /** GPIO_FUNC5_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC5_OE_INV_SEL (BIT(11)) #define GPIO_FUNC5_OE_INV_SEL_M (GPIO_FUNC5_OE_INV_SEL_V << GPIO_FUNC5_OE_INV_SEL_S) @@ -4170,51 +3528,35 @@ extern "C" { #define GPIO_FUNC5_OE_INV_SEL_S 11 /** GPIO_FUNC6_OUT_SEL_CFG_REG register - * Configuration register for GPIO6 output + * GPIO output function select register */ -#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xadc) +#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaec) /** GPIO_FUNC6_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO6.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 6 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC6_OUT_SEL 0x000001FFU #define GPIO_FUNC6_OUT_SEL_M (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S) #define GPIO_FUNC6_OUT_SEL_V 0x000001FFU #define GPIO_FUNC6_OUT_SEL_S 0 /** GPIO_FUNC6_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC6_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC6_OUT_INV_SEL_M (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S) #define GPIO_FUNC6_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC6_OUT_INV_SEL_S 9 /** GPIO_FUNC6_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 6 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC6_OE_SEL (BIT(10)) #define GPIO_FUNC6_OE_SEL_M (GPIO_FUNC6_OE_SEL_V << GPIO_FUNC6_OE_SEL_S) #define GPIO_FUNC6_OE_SEL_V 0x00000001U #define GPIO_FUNC6_OE_SEL_S 10 /** GPIO_FUNC6_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC6_OE_INV_SEL (BIT(11)) #define GPIO_FUNC6_OE_INV_SEL_M (GPIO_FUNC6_OE_INV_SEL_V << GPIO_FUNC6_OE_INV_SEL_S) @@ -4222,51 +3564,35 @@ extern "C" { #define GPIO_FUNC6_OE_INV_SEL_S 11 /** GPIO_FUNC7_OUT_SEL_CFG_REG register - * Configuration register for GPIO7 output + * GPIO output function select register */ -#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae0) +#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf0) /** GPIO_FUNC7_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO7.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 7 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC7_OUT_SEL 0x000001FFU #define GPIO_FUNC7_OUT_SEL_M (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S) #define GPIO_FUNC7_OUT_SEL_V 0x000001FFU #define GPIO_FUNC7_OUT_SEL_S 0 /** GPIO_FUNC7_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC7_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC7_OUT_INV_SEL_M (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S) #define GPIO_FUNC7_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC7_OUT_INV_SEL_S 9 /** GPIO_FUNC7_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 7 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC7_OE_SEL (BIT(10)) #define GPIO_FUNC7_OE_SEL_M (GPIO_FUNC7_OE_SEL_V << GPIO_FUNC7_OE_SEL_S) #define GPIO_FUNC7_OE_SEL_V 0x00000001U #define GPIO_FUNC7_OE_SEL_S 10 /** GPIO_FUNC7_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC7_OE_INV_SEL (BIT(11)) #define GPIO_FUNC7_OE_INV_SEL_M (GPIO_FUNC7_OE_INV_SEL_V << GPIO_FUNC7_OE_INV_SEL_S) @@ -4274,51 +3600,35 @@ extern "C" { #define GPIO_FUNC7_OE_INV_SEL_S 11 /** GPIO_FUNC8_OUT_SEL_CFG_REG register - * Configuration register for GPIO8 output + * GPIO output function select register */ -#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae4) +#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf4) /** GPIO_FUNC8_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO8.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 8 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC8_OUT_SEL 0x000001FFU #define GPIO_FUNC8_OUT_SEL_M (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S) #define GPIO_FUNC8_OUT_SEL_V 0x000001FFU #define GPIO_FUNC8_OUT_SEL_S 0 /** GPIO_FUNC8_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC8_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC8_OUT_INV_SEL_M (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S) #define GPIO_FUNC8_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC8_OUT_INV_SEL_S 9 /** GPIO_FUNC8_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 8 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC8_OE_SEL (BIT(10)) #define GPIO_FUNC8_OE_SEL_M (GPIO_FUNC8_OE_SEL_V << GPIO_FUNC8_OE_SEL_S) #define GPIO_FUNC8_OE_SEL_V 0x00000001U #define GPIO_FUNC8_OE_SEL_S 10 /** GPIO_FUNC8_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC8_OE_INV_SEL (BIT(11)) #define GPIO_FUNC8_OE_INV_SEL_M (GPIO_FUNC8_OE_INV_SEL_V << GPIO_FUNC8_OE_INV_SEL_S) @@ -4326,51 +3636,35 @@ extern "C" { #define GPIO_FUNC8_OE_INV_SEL_S 11 /** GPIO_FUNC9_OUT_SEL_CFG_REG register - * Configuration register for GPIO9 output + * GPIO output function select register */ -#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae8) +#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf8) /** GPIO_FUNC9_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO9.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 9 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC9_OUT_SEL 0x000001FFU #define GPIO_FUNC9_OUT_SEL_M (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S) #define GPIO_FUNC9_OUT_SEL_V 0x000001FFU #define GPIO_FUNC9_OUT_SEL_S 0 /** GPIO_FUNC9_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC9_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC9_OUT_INV_SEL_M (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S) #define GPIO_FUNC9_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC9_OUT_INV_SEL_S 9 /** GPIO_FUNC9_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 9 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC9_OE_SEL (BIT(10)) #define GPIO_FUNC9_OE_SEL_M (GPIO_FUNC9_OE_SEL_V << GPIO_FUNC9_OE_SEL_S) #define GPIO_FUNC9_OE_SEL_V 0x00000001U #define GPIO_FUNC9_OE_SEL_S 10 /** GPIO_FUNC9_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC9_OE_INV_SEL (BIT(11)) #define GPIO_FUNC9_OE_INV_SEL_M (GPIO_FUNC9_OE_INV_SEL_V << GPIO_FUNC9_OE_INV_SEL_S) @@ -4378,51 +3672,35 @@ extern "C" { #define GPIO_FUNC9_OE_INV_SEL_S 11 /** GPIO_FUNC10_OUT_SEL_CFG_REG register - * Configuration register for GPIO10 output + * GPIO output function select register */ -#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaec) +#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xafc) /** GPIO_FUNC10_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO10.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 10 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC10_OUT_SEL 0x000001FFU #define GPIO_FUNC10_OUT_SEL_M (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S) #define GPIO_FUNC10_OUT_SEL_V 0x000001FFU #define GPIO_FUNC10_OUT_SEL_S 0 /** GPIO_FUNC10_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC10_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC10_OUT_INV_SEL_M (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S) #define GPIO_FUNC10_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC10_OUT_INV_SEL_S 9 /** GPIO_FUNC10_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 10 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC10_OE_SEL (BIT(10)) #define GPIO_FUNC10_OE_SEL_M (GPIO_FUNC10_OE_SEL_V << GPIO_FUNC10_OE_SEL_S) #define GPIO_FUNC10_OE_SEL_V 0x00000001U #define GPIO_FUNC10_OE_SEL_S 10 /** GPIO_FUNC10_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC10_OE_INV_SEL (BIT(11)) #define GPIO_FUNC10_OE_INV_SEL_M (GPIO_FUNC10_OE_INV_SEL_V << GPIO_FUNC10_OE_INV_SEL_S) @@ -4430,51 +3708,35 @@ extern "C" { #define GPIO_FUNC10_OE_INV_SEL_S 11 /** GPIO_FUNC11_OUT_SEL_CFG_REG register - * Configuration register for GPIO11 output + * GPIO output function select register */ -#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf0) +#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb00) /** GPIO_FUNC11_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO11.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 11 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC11_OUT_SEL 0x000001FFU #define GPIO_FUNC11_OUT_SEL_M (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S) #define GPIO_FUNC11_OUT_SEL_V 0x000001FFU #define GPIO_FUNC11_OUT_SEL_S 0 /** GPIO_FUNC11_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC11_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC11_OUT_INV_SEL_M (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S) #define GPIO_FUNC11_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC11_OUT_INV_SEL_S 9 /** GPIO_FUNC11_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 11 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC11_OE_SEL (BIT(10)) #define GPIO_FUNC11_OE_SEL_M (GPIO_FUNC11_OE_SEL_V << GPIO_FUNC11_OE_SEL_S) #define GPIO_FUNC11_OE_SEL_V 0x00000001U #define GPIO_FUNC11_OE_SEL_S 10 /** GPIO_FUNC11_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC11_OE_INV_SEL (BIT(11)) #define GPIO_FUNC11_OE_INV_SEL_M (GPIO_FUNC11_OE_INV_SEL_V << GPIO_FUNC11_OE_INV_SEL_S) @@ -4482,51 +3744,35 @@ extern "C" { #define GPIO_FUNC11_OE_INV_SEL_S 11 /** GPIO_FUNC12_OUT_SEL_CFG_REG register - * Configuration register for GPIO12 output + * GPIO output function select register */ -#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf4) +#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb04) /** GPIO_FUNC12_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO12.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 12 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC12_OUT_SEL 0x000001FFU #define GPIO_FUNC12_OUT_SEL_M (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S) #define GPIO_FUNC12_OUT_SEL_V 0x000001FFU #define GPIO_FUNC12_OUT_SEL_S 0 /** GPIO_FUNC12_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC12_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC12_OUT_INV_SEL_M (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S) #define GPIO_FUNC12_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC12_OUT_INV_SEL_S 9 /** GPIO_FUNC12_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 12 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC12_OE_SEL (BIT(10)) #define GPIO_FUNC12_OE_SEL_M (GPIO_FUNC12_OE_SEL_V << GPIO_FUNC12_OE_SEL_S) #define GPIO_FUNC12_OE_SEL_V 0x00000001U #define GPIO_FUNC12_OE_SEL_S 10 /** GPIO_FUNC12_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC12_OE_INV_SEL (BIT(11)) #define GPIO_FUNC12_OE_INV_SEL_M (GPIO_FUNC12_OE_INV_SEL_V << GPIO_FUNC12_OE_INV_SEL_S) @@ -4534,51 +3780,35 @@ extern "C" { #define GPIO_FUNC12_OE_INV_SEL_S 11 /** GPIO_FUNC13_OUT_SEL_CFG_REG register - * Configuration register for GPIO13 output + * GPIO output function select register */ -#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf8) +#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb08) /** GPIO_FUNC13_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO13.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 13 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC13_OUT_SEL 0x000001FFU #define GPIO_FUNC13_OUT_SEL_M (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S) #define GPIO_FUNC13_OUT_SEL_V 0x000001FFU #define GPIO_FUNC13_OUT_SEL_S 0 /** GPIO_FUNC13_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC13_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC13_OUT_INV_SEL_M (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S) #define GPIO_FUNC13_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC13_OUT_INV_SEL_S 9 /** GPIO_FUNC13_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 13 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC13_OE_SEL (BIT(10)) #define GPIO_FUNC13_OE_SEL_M (GPIO_FUNC13_OE_SEL_V << GPIO_FUNC13_OE_SEL_S) #define GPIO_FUNC13_OE_SEL_V 0x00000001U #define GPIO_FUNC13_OE_SEL_S 10 /** GPIO_FUNC13_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC13_OE_INV_SEL (BIT(11)) #define GPIO_FUNC13_OE_INV_SEL_M (GPIO_FUNC13_OE_INV_SEL_V << GPIO_FUNC13_OE_INV_SEL_S) @@ -4586,51 +3816,35 @@ extern "C" { #define GPIO_FUNC13_OE_INV_SEL_S 11 /** GPIO_FUNC14_OUT_SEL_CFG_REG register - * Configuration register for GPIO14 output + * GPIO output function select register */ -#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xafc) +#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb0c) /** GPIO_FUNC14_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO14.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 14 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC14_OUT_SEL 0x000001FFU #define GPIO_FUNC14_OUT_SEL_M (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S) #define GPIO_FUNC14_OUT_SEL_V 0x000001FFU #define GPIO_FUNC14_OUT_SEL_S 0 /** GPIO_FUNC14_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC14_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC14_OUT_INV_SEL_M (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S) #define GPIO_FUNC14_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC14_OUT_INV_SEL_S 9 /** GPIO_FUNC14_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 14 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC14_OE_SEL (BIT(10)) #define GPIO_FUNC14_OE_SEL_M (GPIO_FUNC14_OE_SEL_V << GPIO_FUNC14_OE_SEL_S) #define GPIO_FUNC14_OE_SEL_V 0x00000001U #define GPIO_FUNC14_OE_SEL_S 10 /** GPIO_FUNC14_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC14_OE_INV_SEL (BIT(11)) #define GPIO_FUNC14_OE_INV_SEL_M (GPIO_FUNC14_OE_INV_SEL_V << GPIO_FUNC14_OE_INV_SEL_S) @@ -4638,51 +3852,35 @@ extern "C" { #define GPIO_FUNC14_OE_INV_SEL_S 11 /** GPIO_FUNC15_OUT_SEL_CFG_REG register - * Configuration register for GPIO15 output + * GPIO output function select register */ -#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb00) +#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb10) /** GPIO_FUNC15_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO15.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 15 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC15_OUT_SEL 0x000001FFU #define GPIO_FUNC15_OUT_SEL_M (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S) #define GPIO_FUNC15_OUT_SEL_V 0x000001FFU #define GPIO_FUNC15_OUT_SEL_S 0 /** GPIO_FUNC15_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC15_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC15_OUT_INV_SEL_M (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S) #define GPIO_FUNC15_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC15_OUT_INV_SEL_S 9 /** GPIO_FUNC15_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 15 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC15_OE_SEL (BIT(10)) #define GPIO_FUNC15_OE_SEL_M (GPIO_FUNC15_OE_SEL_V << GPIO_FUNC15_OE_SEL_S) #define GPIO_FUNC15_OE_SEL_V 0x00000001U #define GPIO_FUNC15_OE_SEL_S 10 /** GPIO_FUNC15_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC15_OE_INV_SEL (BIT(11)) #define GPIO_FUNC15_OE_INV_SEL_M (GPIO_FUNC15_OE_INV_SEL_V << GPIO_FUNC15_OE_INV_SEL_S) @@ -4690,51 +3888,35 @@ extern "C" { #define GPIO_FUNC15_OE_INV_SEL_S 11 /** GPIO_FUNC16_OUT_SEL_CFG_REG register - * Configuration register for GPIO16 output + * GPIO output function select register */ -#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb04) +#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb14) /** GPIO_FUNC16_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO16.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 16 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC16_OUT_SEL 0x000001FFU #define GPIO_FUNC16_OUT_SEL_M (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S) #define GPIO_FUNC16_OUT_SEL_V 0x000001FFU #define GPIO_FUNC16_OUT_SEL_S 0 /** GPIO_FUNC16_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC16_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC16_OUT_INV_SEL_M (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S) #define GPIO_FUNC16_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC16_OUT_INV_SEL_S 9 /** GPIO_FUNC16_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 16 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC16_OE_SEL (BIT(10)) #define GPIO_FUNC16_OE_SEL_M (GPIO_FUNC16_OE_SEL_V << GPIO_FUNC16_OE_SEL_S) #define GPIO_FUNC16_OE_SEL_V 0x00000001U #define GPIO_FUNC16_OE_SEL_S 10 /** GPIO_FUNC16_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC16_OE_INV_SEL (BIT(11)) #define GPIO_FUNC16_OE_INV_SEL_M (GPIO_FUNC16_OE_INV_SEL_V << GPIO_FUNC16_OE_INV_SEL_S) @@ -4742,51 +3924,35 @@ extern "C" { #define GPIO_FUNC16_OE_INV_SEL_S 11 /** GPIO_FUNC17_OUT_SEL_CFG_REG register - * Configuration register for GPIO17 output + * GPIO output function select register */ -#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb08) +#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb18) /** GPIO_FUNC17_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO17.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 17 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC17_OUT_SEL 0x000001FFU #define GPIO_FUNC17_OUT_SEL_M (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S) #define GPIO_FUNC17_OUT_SEL_V 0x000001FFU #define GPIO_FUNC17_OUT_SEL_S 0 /** GPIO_FUNC17_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC17_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC17_OUT_INV_SEL_M (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S) #define GPIO_FUNC17_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC17_OUT_INV_SEL_S 9 /** GPIO_FUNC17_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 17 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC17_OE_SEL (BIT(10)) #define GPIO_FUNC17_OE_SEL_M (GPIO_FUNC17_OE_SEL_V << GPIO_FUNC17_OE_SEL_S) #define GPIO_FUNC17_OE_SEL_V 0x00000001U #define GPIO_FUNC17_OE_SEL_S 10 /** GPIO_FUNC17_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC17_OE_INV_SEL (BIT(11)) #define GPIO_FUNC17_OE_INV_SEL_M (GPIO_FUNC17_OE_INV_SEL_V << GPIO_FUNC17_OE_INV_SEL_S) @@ -4794,51 +3960,35 @@ extern "C" { #define GPIO_FUNC17_OE_INV_SEL_S 11 /** GPIO_FUNC18_OUT_SEL_CFG_REG register - * Configuration register for GPIO18 output + * GPIO output function select register */ -#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb0c) +#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb1c) /** GPIO_FUNC18_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO18.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 18 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC18_OUT_SEL 0x000001FFU #define GPIO_FUNC18_OUT_SEL_M (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S) #define GPIO_FUNC18_OUT_SEL_V 0x000001FFU #define GPIO_FUNC18_OUT_SEL_S 0 /** GPIO_FUNC18_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC18_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC18_OUT_INV_SEL_M (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S) #define GPIO_FUNC18_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC18_OUT_INV_SEL_S 9 /** GPIO_FUNC18_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 18 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC18_OE_SEL (BIT(10)) #define GPIO_FUNC18_OE_SEL_M (GPIO_FUNC18_OE_SEL_V << GPIO_FUNC18_OE_SEL_S) #define GPIO_FUNC18_OE_SEL_V 0x00000001U #define GPIO_FUNC18_OE_SEL_S 10 /** GPIO_FUNC18_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC18_OE_INV_SEL (BIT(11)) #define GPIO_FUNC18_OE_INV_SEL_M (GPIO_FUNC18_OE_INV_SEL_V << GPIO_FUNC18_OE_INV_SEL_S) @@ -4846,51 +3996,35 @@ extern "C" { #define GPIO_FUNC18_OE_INV_SEL_S 11 /** GPIO_FUNC19_OUT_SEL_CFG_REG register - * Configuration register for GPIO19 output + * GPIO output function select register */ -#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb10) +#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb20) /** GPIO_FUNC19_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO19.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 19 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC19_OUT_SEL 0x000001FFU #define GPIO_FUNC19_OUT_SEL_M (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S) #define GPIO_FUNC19_OUT_SEL_V 0x000001FFU #define GPIO_FUNC19_OUT_SEL_S 0 /** GPIO_FUNC19_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC19_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC19_OUT_INV_SEL_M (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S) #define GPIO_FUNC19_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC19_OUT_INV_SEL_S 9 /** GPIO_FUNC19_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 19 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC19_OE_SEL (BIT(10)) #define GPIO_FUNC19_OE_SEL_M (GPIO_FUNC19_OE_SEL_V << GPIO_FUNC19_OE_SEL_S) #define GPIO_FUNC19_OE_SEL_V 0x00000001U #define GPIO_FUNC19_OE_SEL_S 10 /** GPIO_FUNC19_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC19_OE_INV_SEL (BIT(11)) #define GPIO_FUNC19_OE_INV_SEL_M (GPIO_FUNC19_OE_INV_SEL_V << GPIO_FUNC19_OE_INV_SEL_S) @@ -4898,51 +4032,35 @@ extern "C" { #define GPIO_FUNC19_OE_INV_SEL_S 11 /** GPIO_FUNC20_OUT_SEL_CFG_REG register - * Configuration register for GPIO20 output + * GPIO output function select register */ -#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb14) +#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb24) /** GPIO_FUNC20_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO20.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 20 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC20_OUT_SEL 0x000001FFU #define GPIO_FUNC20_OUT_SEL_M (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S) #define GPIO_FUNC20_OUT_SEL_V 0x000001FFU #define GPIO_FUNC20_OUT_SEL_S 0 /** GPIO_FUNC20_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC20_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC20_OUT_INV_SEL_M (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S) #define GPIO_FUNC20_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC20_OUT_INV_SEL_S 9 /** GPIO_FUNC20_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 20 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC20_OE_SEL (BIT(10)) #define GPIO_FUNC20_OE_SEL_M (GPIO_FUNC20_OE_SEL_V << GPIO_FUNC20_OE_SEL_S) #define GPIO_FUNC20_OE_SEL_V 0x00000001U #define GPIO_FUNC20_OE_SEL_S 10 /** GPIO_FUNC20_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC20_OE_INV_SEL (BIT(11)) #define GPIO_FUNC20_OE_INV_SEL_M (GPIO_FUNC20_OE_INV_SEL_V << GPIO_FUNC20_OE_INV_SEL_S) @@ -4950,51 +4068,35 @@ extern "C" { #define GPIO_FUNC20_OE_INV_SEL_S 11 /** GPIO_FUNC21_OUT_SEL_CFG_REG register - * Configuration register for GPIO21 output + * GPIO output function select register */ -#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb18) +#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb28) /** GPIO_FUNC21_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO21.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 21 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC21_OUT_SEL 0x000001FFU #define GPIO_FUNC21_OUT_SEL_M (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S) #define GPIO_FUNC21_OUT_SEL_V 0x000001FFU #define GPIO_FUNC21_OUT_SEL_S 0 /** GPIO_FUNC21_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC21_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC21_OUT_INV_SEL_M (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S) #define GPIO_FUNC21_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC21_OUT_INV_SEL_S 9 /** GPIO_FUNC21_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 21 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC21_OE_SEL (BIT(10)) #define GPIO_FUNC21_OE_SEL_M (GPIO_FUNC21_OE_SEL_V << GPIO_FUNC21_OE_SEL_S) #define GPIO_FUNC21_OE_SEL_V 0x00000001U #define GPIO_FUNC21_OE_SEL_S 10 /** GPIO_FUNC21_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC21_OE_INV_SEL (BIT(11)) #define GPIO_FUNC21_OE_INV_SEL_M (GPIO_FUNC21_OE_INV_SEL_V << GPIO_FUNC21_OE_INV_SEL_S) @@ -5002,51 +4104,35 @@ extern "C" { #define GPIO_FUNC21_OE_INV_SEL_S 11 /** GPIO_FUNC22_OUT_SEL_CFG_REG register - * Configuration register for GPIO22 output + * GPIO output function select register */ -#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb1c) +#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb2c) /** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO22.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 22 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC22_OUT_SEL 0x000001FFU #define GPIO_FUNC22_OUT_SEL_M (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S) #define GPIO_FUNC22_OUT_SEL_V 0x000001FFU #define GPIO_FUNC22_OUT_SEL_S 0 /** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC22_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC22_OUT_INV_SEL_M (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S) #define GPIO_FUNC22_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC22_OUT_INV_SEL_S 9 /** GPIO_FUNC22_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 22 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC22_OE_SEL (BIT(10)) #define GPIO_FUNC22_OE_SEL_M (GPIO_FUNC22_OE_SEL_V << GPIO_FUNC22_OE_SEL_S) #define GPIO_FUNC22_OE_SEL_V 0x00000001U #define GPIO_FUNC22_OE_SEL_S 10 /** GPIO_FUNC22_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC22_OE_INV_SEL (BIT(11)) #define GPIO_FUNC22_OE_INV_SEL_M (GPIO_FUNC22_OE_INV_SEL_V << GPIO_FUNC22_OE_INV_SEL_S) @@ -5054,51 +4140,35 @@ extern "C" { #define GPIO_FUNC22_OE_INV_SEL_S 11 /** GPIO_FUNC23_OUT_SEL_CFG_REG register - * Configuration register for GPIO23 output + * GPIO output function select register */ -#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb20) +#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb30) /** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO23.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 23 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC23_OUT_SEL 0x000001FFU #define GPIO_FUNC23_OUT_SEL_M (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S) #define GPIO_FUNC23_OUT_SEL_V 0x000001FFU #define GPIO_FUNC23_OUT_SEL_S 0 /** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC23_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC23_OUT_INV_SEL_M (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S) #define GPIO_FUNC23_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC23_OUT_INV_SEL_S 9 /** GPIO_FUNC23_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 23 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC23_OE_SEL (BIT(10)) #define GPIO_FUNC23_OE_SEL_M (GPIO_FUNC23_OE_SEL_V << GPIO_FUNC23_OE_SEL_S) #define GPIO_FUNC23_OE_SEL_V 0x00000001U #define GPIO_FUNC23_OE_SEL_S 10 /** GPIO_FUNC23_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC23_OE_INV_SEL (BIT(11)) #define GPIO_FUNC23_OE_INV_SEL_M (GPIO_FUNC23_OE_INV_SEL_V << GPIO_FUNC23_OE_INV_SEL_S) @@ -5106,65 +4176,371 @@ extern "C" { #define GPIO_FUNC23_OE_INV_SEL_S 11 /** GPIO_FUNC24_OUT_SEL_CFG_REG register - * Configuration register for GPIO24 output + * GPIO output function select register */ -#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb24) +#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb34) /** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO24.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 24 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC24_OUT_SEL 0x000001FFU #define GPIO_FUNC24_OUT_SEL_M (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S) #define GPIO_FUNC24_OUT_SEL_V 0x000001FFU #define GPIO_FUNC24_OUT_SEL_S 0 /** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC24_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC24_OUT_INV_SEL_M (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S) #define GPIO_FUNC24_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC24_OUT_INV_SEL_S 9 /** GPIO_FUNC24_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 24 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC24_OE_SEL (BIT(10)) #define GPIO_FUNC24_OE_SEL_M (GPIO_FUNC24_OE_SEL_V << GPIO_FUNC24_OE_SEL_S) #define GPIO_FUNC24_OE_SEL_V 0x00000001U #define GPIO_FUNC24_OE_SEL_S 10 /** GPIO_FUNC24_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC24_OE_INV_SEL (BIT(11)) #define GPIO_FUNC24_OE_INV_SEL_M (GPIO_FUNC24_OE_INV_SEL_V << GPIO_FUNC24_OE_INV_SEL_S) #define GPIO_FUNC24_OE_INV_SEL_V 0x00000001U #define GPIO_FUNC24_OE_INV_SEL_S 11 +/** GPIO_FUNC25_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb38) +/** GPIO_FUNC25_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC25_OUT_SEL 0x000001FFU +#define GPIO_FUNC25_OUT_SEL_M (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S) +#define GPIO_FUNC25_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC25_OUT_SEL_S 0 +/** GPIO_FUNC25_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC25_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC25_OUT_INV_SEL_M (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S) +#define GPIO_FUNC25_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_OUT_INV_SEL_S 9 +/** GPIO_FUNC25_OE_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC25_OE_SEL (BIT(10)) +#define GPIO_FUNC25_OE_SEL_M (GPIO_FUNC25_OE_SEL_V << GPIO_FUNC25_OE_SEL_S) +#define GPIO_FUNC25_OE_SEL_V 0x00000001U +#define GPIO_FUNC25_OE_SEL_S 10 +/** GPIO_FUNC25_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC25_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC25_OE_INV_SEL_M (GPIO_FUNC25_OE_INV_SEL_V << GPIO_FUNC25_OE_INV_SEL_S) +#define GPIO_FUNC25_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_OE_INV_SEL_S 11 + +/** GPIO_FUNC26_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb3c) +/** GPIO_FUNC26_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC26_OUT_SEL 0x000001FFU +#define GPIO_FUNC26_OUT_SEL_M (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S) +#define GPIO_FUNC26_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC26_OUT_SEL_S 0 +/** GPIO_FUNC26_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC26_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC26_OUT_INV_SEL_M (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S) +#define GPIO_FUNC26_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_OUT_INV_SEL_S 9 +/** GPIO_FUNC26_OE_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC26_OE_SEL (BIT(10)) +#define GPIO_FUNC26_OE_SEL_M (GPIO_FUNC26_OE_SEL_V << GPIO_FUNC26_OE_SEL_S) +#define GPIO_FUNC26_OE_SEL_V 0x00000001U +#define GPIO_FUNC26_OE_SEL_S 10 +/** GPIO_FUNC26_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC26_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC26_OE_INV_SEL_M (GPIO_FUNC26_OE_INV_SEL_V << GPIO_FUNC26_OE_INV_SEL_S) +#define GPIO_FUNC26_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_OE_INV_SEL_S 11 + +/** GPIO_FUNC27_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb40) +/** GPIO_FUNC27_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC27_OUT_SEL 0x000001FFU +#define GPIO_FUNC27_OUT_SEL_M (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S) +#define GPIO_FUNC27_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC27_OUT_SEL_S 0 +/** GPIO_FUNC27_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC27_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC27_OUT_INV_SEL_M (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S) +#define GPIO_FUNC27_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_OUT_INV_SEL_S 9 +/** GPIO_FUNC27_OE_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC27_OE_SEL (BIT(10)) +#define GPIO_FUNC27_OE_SEL_M (GPIO_FUNC27_OE_SEL_V << GPIO_FUNC27_OE_SEL_S) +#define GPIO_FUNC27_OE_SEL_V 0x00000001U +#define GPIO_FUNC27_OE_SEL_S 10 +/** GPIO_FUNC27_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC27_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC27_OE_INV_SEL_M (GPIO_FUNC27_OE_INV_SEL_V << GPIO_FUNC27_OE_INV_SEL_S) +#define GPIO_FUNC27_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_OE_INV_SEL_S 11 + +/** GPIO_FUNC28_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb44) +/** GPIO_FUNC28_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC28_OUT_SEL 0x000001FFU +#define GPIO_FUNC28_OUT_SEL_M (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S) +#define GPIO_FUNC28_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC28_OUT_SEL_S 0 +/** GPIO_FUNC28_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC28_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC28_OUT_INV_SEL_M (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S) +#define GPIO_FUNC28_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_OUT_INV_SEL_S 9 +/** GPIO_FUNC28_OE_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC28_OE_SEL (BIT(10)) +#define GPIO_FUNC28_OE_SEL_M (GPIO_FUNC28_OE_SEL_V << GPIO_FUNC28_OE_SEL_S) +#define GPIO_FUNC28_OE_SEL_V 0x00000001U +#define GPIO_FUNC28_OE_SEL_S 10 +/** GPIO_FUNC28_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC28_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC28_OE_INV_SEL_M (GPIO_FUNC28_OE_INV_SEL_V << GPIO_FUNC28_OE_INV_SEL_S) +#define GPIO_FUNC28_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_OE_INV_SEL_S 11 + +/** GPIO_FUNC29_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb48) +/** GPIO_FUNC29_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC29_OUT_SEL 0x000001FFU +#define GPIO_FUNC29_OUT_SEL_M (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S) +#define GPIO_FUNC29_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC29_OUT_SEL_S 0 +/** GPIO_FUNC29_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC29_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC29_OUT_INV_SEL_M (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S) +#define GPIO_FUNC29_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_OUT_INV_SEL_S 9 +/** GPIO_FUNC29_OE_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC29_OE_SEL (BIT(10)) +#define GPIO_FUNC29_OE_SEL_M (GPIO_FUNC29_OE_SEL_V << GPIO_FUNC29_OE_SEL_S) +#define GPIO_FUNC29_OE_SEL_V 0x00000001U +#define GPIO_FUNC29_OE_SEL_S 10 +/** GPIO_FUNC29_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC29_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC29_OE_INV_SEL_M (GPIO_FUNC29_OE_INV_SEL_V << GPIO_FUNC29_OE_INV_SEL_S) +#define GPIO_FUNC29_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_OE_INV_SEL_S 11 + +/** GPIO_FUNC30_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb4c) +/** GPIO_FUNC30_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC30_OUT_SEL 0x000001FFU +#define GPIO_FUNC30_OUT_SEL_M (GPIO_FUNC30_OUT_SEL_V << GPIO_FUNC30_OUT_SEL_S) +#define GPIO_FUNC30_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC30_OUT_SEL_S 0 +/** GPIO_FUNC30_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC30_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC30_OUT_INV_SEL_M (GPIO_FUNC30_OUT_INV_SEL_V << GPIO_FUNC30_OUT_INV_SEL_S) +#define GPIO_FUNC30_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_OUT_INV_SEL_S 9 +/** GPIO_FUNC30_OE_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC30_OE_SEL (BIT(10)) +#define GPIO_FUNC30_OE_SEL_M (GPIO_FUNC30_OE_SEL_V << GPIO_FUNC30_OE_SEL_S) +#define GPIO_FUNC30_OE_SEL_V 0x00000001U +#define GPIO_FUNC30_OE_SEL_S 10 +/** GPIO_FUNC30_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC30_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC30_OE_INV_SEL_M (GPIO_FUNC30_OE_INV_SEL_V << GPIO_FUNC30_OE_INV_SEL_S) +#define GPIO_FUNC30_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_OE_INV_SEL_S 11 + +/** GPIO_FUNC31_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb50) +/** GPIO_FUNC31_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC31_OUT_SEL 0x000001FFU +#define GPIO_FUNC31_OUT_SEL_M (GPIO_FUNC31_OUT_SEL_V << GPIO_FUNC31_OUT_SEL_S) +#define GPIO_FUNC31_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC31_OUT_SEL_S 0 +/** GPIO_FUNC31_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC31_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC31_OUT_INV_SEL_M (GPIO_FUNC31_OUT_INV_SEL_V << GPIO_FUNC31_OUT_INV_SEL_S) +#define GPIO_FUNC31_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC31_OUT_INV_SEL_S 9 +/** GPIO_FUNC31_OE_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC31_OE_SEL (BIT(10)) +#define GPIO_FUNC31_OE_SEL_M (GPIO_FUNC31_OE_SEL_V << GPIO_FUNC31_OE_SEL_S) +#define GPIO_FUNC31_OE_SEL_V 0x00000001U +#define GPIO_FUNC31_OE_SEL_S 10 +/** GPIO_FUNC31_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC31_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC31_OE_INV_SEL_M (GPIO_FUNC31_OE_INV_SEL_V << GPIO_FUNC31_OE_INV_SEL_S) +#define GPIO_FUNC31_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC31_OE_INV_SEL_S 11 + +/** GPIO_FUNC32_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb54) +/** GPIO_FUNC32_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC32_OUT_SEL 0x000001FFU +#define GPIO_FUNC32_OUT_SEL_M (GPIO_FUNC32_OUT_SEL_V << GPIO_FUNC32_OUT_SEL_S) +#define GPIO_FUNC32_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC32_OUT_SEL_S 0 +/** GPIO_FUNC32_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC32_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC32_OUT_INV_SEL_M (GPIO_FUNC32_OUT_INV_SEL_V << GPIO_FUNC32_OUT_INV_SEL_S) +#define GPIO_FUNC32_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC32_OUT_INV_SEL_S 9 +/** GPIO_FUNC32_OE_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC32_OE_SEL (BIT(10)) +#define GPIO_FUNC32_OE_SEL_M (GPIO_FUNC32_OE_SEL_V << GPIO_FUNC32_OE_SEL_S) +#define GPIO_FUNC32_OE_SEL_V 0x00000001U +#define GPIO_FUNC32_OE_SEL_S 10 +/** GPIO_FUNC32_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC32_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC32_OE_INV_SEL_M (GPIO_FUNC32_OE_INV_SEL_V << GPIO_FUNC32_OE_INV_SEL_S) +#define GPIO_FUNC32_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC32_OE_INV_SEL_S 11 + +/** GPIO_FUNC33_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb58) +/** GPIO_FUNC33_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC33_OUT_SEL 0x000001FFU +#define GPIO_FUNC33_OUT_SEL_M (GPIO_FUNC33_OUT_SEL_V << GPIO_FUNC33_OUT_SEL_S) +#define GPIO_FUNC33_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC33_OUT_SEL_S 0 +/** GPIO_FUNC33_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC33_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC33_OUT_INV_SEL_M (GPIO_FUNC33_OUT_INV_SEL_V << GPIO_FUNC33_OUT_INV_SEL_S) +#define GPIO_FUNC33_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC33_OUT_INV_SEL_S 9 +/** GPIO_FUNC33_OE_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC33_OE_SEL (BIT(10)) +#define GPIO_FUNC33_OE_SEL_M (GPIO_FUNC33_OE_SEL_V << GPIO_FUNC33_OE_SEL_S) +#define GPIO_FUNC33_OE_SEL_V 0x00000001U +#define GPIO_FUNC33_OE_SEL_S 10 +/** GPIO_FUNC33_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC33_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC33_OE_INV_SEL_M (GPIO_FUNC33_OE_INV_SEL_V << GPIO_FUNC33_OE_INV_SEL_S) +#define GPIO_FUNC33_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC33_OE_INV_SEL_S 11 + /** GPIO_CLOCK_GATE_REG register * GPIO clock gate register */ #define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0xdf8) /** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1; - * Configures whether or not to enable clock gate.\\ - * 0: Not enable\\ - * 1: Enable, the clock is free running. \\ + * set this bit to enable GPIO clock gate */ #define GPIO_CLK_EN (BIT(0)) #define GPIO_CLK_EN_M (GPIO_CLK_EN_V << GPIO_CLK_EN_S) @@ -5175,8 +4551,8 @@ extern "C" { * GPIO version register */ #define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0xdfc) -/** GPIO_DATE : R/W; bitpos: [27:0]; default: 37753392; - * Version control register. \\ +/** GPIO_DATE : R/W; bitpos: [27:0]; default: 37823120; + * version register */ #define GPIO_DATE 0x0FFFFFFFU #define GPIO_DATE_M (GPIO_DATE_V << GPIO_DATE_S) diff --git a/components/soc/esp32c61/register/soc/gpio_struct.h b/components/soc/esp32c61/register/soc/gpio_struct.h index d37ed33d56..e5f244d4de 100644 --- a/components/soc/esp32c61/register/soc/gpio_struct.h +++ b/components/soc/esp32c61/register/soc/gpio_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,20 +10,14 @@ extern "C" { #endif -/** Group: Configuration Registers */ +/** Group: configuration register */ /** Type of strap register - * Strapping pin register + * pad strapping register */ typedef union { struct { /** strapping : RO; bitpos: [15:0]; default: 0; - * Represents the values of GPIO strapping pins. - * - * - bit0 ~ bit1: invalid - * - bit2: GPIO8 - * - bit3: GPIO9 - * - bit4: GPIO7 - * - bit5 ~ bit15: invalid + * pad strapping register */ uint32_t strapping:16; uint32_t reserved_16:16; @@ -32,297 +26,389 @@ typedef union { } gpio_strap_reg_t; /** Type of out register - * GPIO output register + * GPIO output register for GPIO0-31 */ typedef union { struct { - /** out_data_orig : R/W/SC/WTC; bitpos: [28:0]; default: 0; - * Configures the output value of GPIO0 ~ 24 output in simple GPIO output mode.\\ - * 0: Low level\\ - * 1: High level\\ - * The value of bit0 ~ bit24 correspond to the output value of GPIO0 ~ GPIO24 - * respectively. Bit25 ~ bit31 are invalid.\\ + /** out_data_orig : R/W/SC/WTC; bitpos: [31:0]; default: 0; + * GPIO output register for GPIO0-31 */ - uint32_t out_data_orig:29; - uint32_t reserved_29:3; + uint32_t out_data_orig:32; }; uint32_t val; } gpio_out_reg_t; /** Type of out_w1ts register - * GPIO output set register + * GPIO output set register for GPIO0-31 */ typedef union { struct { - /** out_w1ts : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~ - * GPIO24.\\ - * 0: Not set\\ - * 1: The corresponding bit in GPIO_OUT_REG will be set to 1\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ - * Recommended operation: use this register to set GPIO_OUT_REG. \\ + /** out_w1ts : WT; bitpos: [31:0]; default: 0; + * GPIO output set register for GPIO0-31 */ - uint32_t out_w1ts:29; - uint32_t reserved_29:3; + uint32_t out_w1ts:32; }; uint32_t val; } gpio_out_w1ts_reg_t; /** Type of out_w1tc register - * GPIO output clear register + * GPIO output clear register for GPIO0-31 */ typedef union { struct { - /** out_w1tc : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0 ~ - * GPIO24 output.\\ - * 0: Not clear\\ - * 1: The corresponding bit in GPIO_OUT_REG will be cleared.\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ - * Recommended operation: use this register to clear GPIO_OUT_REG. \\ + /** out_w1tc : WT; bitpos: [31:0]; default: 0; + * GPIO output clear register for GPIO0-31 */ - uint32_t out_w1tc:29; - uint32_t reserved_29:3; + uint32_t out_w1tc:32; }; uint32_t val; } gpio_out_w1tc_reg_t; -/** Type of enable register - * GPIO output enable register +/** Type of out1 register + * GPIO output register for GPIO32-33 */ typedef union { struct { - /** enable_data : R/W/WTC; bitpos: [28:0]; default: 0; - * Configures whether or not to enable the output of GPIO0 ~ GPIO24.\\ - * 0: Not enable\\ - * 1: Enable\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\ + /** out1_data_orig : R/W/SC/WTC; bitpos: [1:0]; default: 0; + * GPIO output register for GPIO32-33 */ - uint32_t enable_data:29; - uint32_t reserved_29:3; + uint32_t out1_data_orig:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_out1_reg_t; + +/** Type of out1_w1ts register + * GPIO output set register for GPIO32-33 + */ +typedef union { + struct { + /** out1_w1ts : WT; bitpos: [1:0]; default: 0; + * GPIO output set register for GPIO32-33 + */ + uint32_t out1_w1ts:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_out1_w1ts_reg_t; + +/** Type of out1_w1tc register + * GPIO output clear register for GPIO32-33 + */ +typedef union { + struct { + /** out1_w1tc : WT; bitpos: [1:0]; default: 0; + * GPIO output clear register for GPIO32-33 + */ + uint32_t out1_w1tc:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_out1_w1tc_reg_t; + +/** Type of enable register + * GPIO output enable register for GPIO0-31 + */ +typedef union { + struct { + /** enable_data : R/W/WTC; bitpos: [31:0]; default: 0; + * GPIO output enable register for GPIO0-31 + */ + uint32_t enable_data:32; }; uint32_t val; } gpio_enable_reg_t; /** Type of enable_w1ts register - * GPIO output enable set register + * GPIO output enable set register for GPIO0-31 */ typedef union { struct { - /** enable_w1ts : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to set the output enable register GPIO_ENABLE_REG of - * GPIO0 ~ GPIO24.\\ - * 0: Not set\\ - * 1: The corresponding bit in GPIO_ENABLE_REG will be set to 1\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ - * Recommended operation: use this register to set GPIO_ENABLE_REG.\\ + /** enable_w1ts : WT; bitpos: [31:0]; default: 0; + * GPIO output enable set register for GPIO0-31 */ - uint32_t enable_w1ts:29; - uint32_t reserved_29:3; + uint32_t enable_w1ts:32; }; uint32_t val; } gpio_enable_w1ts_reg_t; /** Type of enable_w1tc register - * GPIO output enable clear register + * GPIO output enable clear register for GPIO0-31 */ typedef union { struct { - /** enable_w1tc : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to clear the output enable register GPIO_ENABLE_REG of - * GPIO0 ~ GPIO24. \\ - * 0: Not clear\\ - * 1: The corresponding bit in GPIO_ENABLE_REG will be cleared\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ - * Recommended operation: use this register to clear GPIO_ENABLE_REG.\\ + /** enable_w1tc : WT; bitpos: [31:0]; default: 0; + * GPIO output enable clear register for GPIO0-31 */ - uint32_t enable_w1tc:29; - uint32_t reserved_29:3; + uint32_t enable_w1tc:32; }; uint32_t val; } gpio_enable_w1tc_reg_t; -/** Type of in register - * GPIO input register +/** Type of enable1 register + * GPIO output enable register for GPIO32-33 */ typedef union { struct { - /** in_data_next : RO; bitpos: [28:0]; default: 0; - * Represents the input value of GPIO0 ~ GPIO24. Each bit represents a pin input - * value:\\ - * 0: Low level\\ - * 1: High level\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\ + /** enable1_data : R/W/WTC; bitpos: [1:0]; default: 0; + * GPIO output enable register for GPIO32-33 */ - uint32_t in_data_next:29; - uint32_t reserved_29:3; + uint32_t enable1_data:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_enable1_reg_t; + +/** Type of enable1_w1ts register + * GPIO output enable set register for GPIO32-33 + */ +typedef union { + struct { + /** enable1_w1ts : WT; bitpos: [1:0]; default: 0; + * GPIO output enable set register for GPIO32-33 + */ + uint32_t enable1_w1ts:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_enable1_w1ts_reg_t; + +/** Type of enable1_w1tc register + * GPIO output enable clear register for GPIO32-33 + */ +typedef union { + struct { + /** enable1_w1tc : WT; bitpos: [1:0]; default: 0; + * GPIO output enable clear register for GPIO32-33 + */ + uint32_t enable1_w1tc:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_enable1_w1tc_reg_t; + +/** Type of in register + * GPIO input register for GPIO0-31 + */ +typedef union { + struct { + /** in_data_next : RO; bitpos: [31:0]; default: 0; + * GPIO input register for GPIO0-31 + */ + uint32_t in_data_next:32; }; uint32_t val; } gpio_in_reg_t; - -/** Group: Interrupt Status Registers */ -/** Type of status register - * GPIO interrupt status register +/** Type of in1 register + * GPIO input register for GPIO32-33 */ typedef union { struct { - /** status_interrupt : R/W/WTC; bitpos: [28:0]; default: 0; - * The interrupt status of GPIO0 ~ GPIO24, can be configured by the software. - * - * - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. - * - Each bit represents the status of its corresponding GPIO: - * - * - 0: Represents the GPIO does not generate the interrupt configured by - * GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software. - * - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE, - * or this bit is configured to 1 by the software. - * + /** in1_data_next : RO; bitpos: [1:0]; default: 0; + * GPIO input register for GPIO32-33 */ - uint32_t status_interrupt:29; - uint32_t reserved_29:3; + uint32_t in1_data_next:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_in1_reg_t; + +/** Type of status register + * GPIO interrupt status register for GPIO0-31 + */ +typedef union { + struct { + /** status_interrupt : R/W/WTC; bitpos: [31:0]; default: 0; + * GPIO interrupt status register for GPIO0-31 + */ + uint32_t status_interrupt:32; }; uint32_t val; } gpio_status_reg_t; /** Type of status_w1ts register - * GPIO interrupt status set register + * GPIO interrupt status set register for GPIO0-31 */ typedef union { struct { - /** status_w1ts : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to set the interrupt status register - * GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24. - * - * - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. - * - If the value 1 is written to a bit here, the corresponding bit in - * GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this - * register to set GPIO_STATUS_INTERRUPT. + /** status_w1ts : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status set register for GPIO0-31 */ - uint32_t status_w1ts:29; - uint32_t reserved_29:3; + uint32_t status_w1ts:32; }; uint32_t val; } gpio_status_w1ts_reg_t; /** Type of status_w1tc register - * GPIO interrupt status clear register + * GPIO interrupt status clear register for GPIO0-31 */ typedef union { struct { - /** status_w1tc : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to clear the interrupt status register - * GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24. - * - * - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. - * - If the value 1 is written to a bit here, the corresponding bit in - * GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this - * register to clear GPIO_STATUS_INTERRUPT. + /** status_w1tc : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status clear register for GPIO0-31 */ - uint32_t status_w1tc:29; - uint32_t reserved_29:3; + uint32_t status_w1tc:32; }; uint32_t val; } gpio_status_w1tc_reg_t; -/** Type of procpu_int register - * CPU interrupt status register +/** Type of status1 register + * GPIO interrupt status register for GPIO32-33 */ typedef union { struct { - /** procpu_int : RO; bitpos: [28:0]; default: 0; - * Represents the CPU interrupt status of GPIO0 ~ GPIO24. Each bit represents:\\ - * 0: Represents CPU interrupt is not enabled, or the GPIO does not generate the - * interrupt configured by GPIO_PIN$n_INT_TYPE.\\ - * 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE - * after the CPU interrupt is enabled.\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. This - * interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high) - * enable signal (bit13 of GPIO_PIN$n_REG). \\ + /** status1_interrupt : R/W/WTC; bitpos: [1:0]; default: 0; + * GPIO interrupt status register for GPIO32-33 */ - uint32_t procpu_int:29; - uint32_t reserved_29:3; + uint32_t status1_interrupt:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_status1_reg_t; + +/** Type of status1_w1ts register + * GPIO interrupt status set register for GPIO32-33 + */ +typedef union { + struct { + /** status1_w1ts : WT; bitpos: [1:0]; default: 0; + * GPIO interrupt status set register for GPIO32-33 + */ + uint32_t status1_w1ts:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_status1_w1ts_reg_t; + +/** Type of status1_w1tc register + * GPIO interrupt status clear register for GPIO32-33 + */ +typedef union { + struct { + /** status1_w1tc : WT; bitpos: [1:0]; default: 0; + * GPIO interrupt status clear register for GPIO32-33 + */ + uint32_t status1_w1tc:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_status1_w1tc_reg_t; + +/** Type of procpu_int register + * GPIO_PROCPU_INT interrupt status register for GPIO0-31 + */ +typedef union { + struct { + /** procpu_int : RO; bitpos: [31:0]; default: 0; + * GPIO_PROCPU_INT interrupt status register for GPIO0-31 + */ + uint32_t procpu_int:32; }; uint32_t val; } gpio_procpu_int_reg_t; -/** Type of status_next register - * GPIO interrupt source register +/** Type of sdio_int register + * GPIO_SDIO_INT interrupt status register for GPIO0-31 */ typedef union { struct { - /** status_interrupt_next : RO; bitpos: [28:0]; default: 0; - * Represents the interrupt source signal of GPIO0 ~ GPIO24.\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. Each - * bit represents:\\ - * 0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.\\ - * 1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.\\ - * The interrupt could be rising edge interrupt, falling edge interrupt, level - * sensitive interrupt and any edge interrupt.\\ + /** sdio_int : RO; bitpos: [31:0]; default: 0; + * GPIO_SDIO_INT interrupt status register for GPIO0-31 */ - uint32_t status_interrupt_next:29; - uint32_t reserved_29:3; + uint32_t sdio_int:32; + }; + uint32_t val; +} gpio_sdio_int_reg_t; + +/** Type of procpu_int1 register + * GPIO_PROCPU_INT interrupt status register for GPIO32-33 + */ +typedef union { + struct { + /** procpu_int1 : RO; bitpos: [1:0]; default: 0; + * GPIO_PROCPU_INT interrupt status register for GPIO32-33 + */ + uint32_t procpu_int1:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_procpu_int1_reg_t; + +/** Type of sdio_int1 register + * GPIO_SDIO_INT interrupt status register for GPIO32-33 + */ +typedef union { + struct { + /** sdio_int1 : RO; bitpos: [1:0]; default: 0; + * GPIO_SDIO_INT interrupt status register for GPIO32-33 + */ + uint32_t sdio_int1:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_sdio_int1_reg_t; + +/** Type of status_next register + * GPIO interrupt source register for GPIO0-31 + */ +typedef union { + struct { + /** status_interrupt_next : RO; bitpos: [31:0]; default: 0; + * GPIO interrupt source register for GPIO0-31 + */ + uint32_t status_interrupt_next:32; }; uint32_t val; } gpio_status_next_reg_t; +/** Type of status_next1 register + * GPIO interrupt source register for GPIO32-33 + */ +typedef union { + struct { + /** status_interrupt_next1 : RO; bitpos: [1:0]; default: 0; + * GPIO interrupt source register for GPIO32-33 + */ + uint32_t status_interrupt_next1:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_status_next1_reg_t; -/** Group: Pin Configuration Registers */ /** Type of pinn register - * GPIOn configuration register + * GPIO pin configuration register */ typedef union { struct { /** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ uint32_t pinn_sync2_bypass:2; /** pinn_pad_driver : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ uint32_t pinn_pad_driver:1; /** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ uint32_t pinn_sync1_bypass:2; uint32_t reserved_5:2; /** pinn_int_type : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ uint32_t pinn_int_type:3; /** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ uint32_t pinn_wakeup_enable:1; uint32_t reserved_11:2; /** pinn_int_ena : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ uint32_t pinn_int_ena:5; uint32_t reserved_18:14; @@ -330,82 +416,51 @@ typedef union { uint32_t val; } gpio_pinn_reg_t; - -/** Group: Input Configuration Registers */ -/** Type of func0_in_sel_cfg register - * Configuration register for input signal 0 +/** Type of func_in_sel_cfg register + * GPIO input function configuration register */ typedef union { struct { - /** func_in_sel : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 0.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ + /** func_in_sel : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ - uint32_t func_in_sel:6; - /** func_in_inv_sel : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + uint32_t func_in_sel:7; + /** func_in_inv_sel : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ uint32_t func_in_inv_sel:1; - /** sig_in_sel : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + /** sig0_in_sel : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ uint32_t sig_in_sel:1; - uint32_t reserved_8:24; + uint32_t reserved_9:23; }; uint32_t val; } gpio_func_in_sel_cfg_reg_t; -/** Group: Output Configuration Registers */ /** Type of funcn_out_sel_cfg register - * Configuration register for GPIOn output + * GPIO output function select register */ typedef union { struct { /** funcn_out_sel : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIOn.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ uint32_t funcn_out_sel:9; /** funcn_out_inv_sel : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ uint32_t funcn_out_inv_sel:1; /** funcn_oe_sel : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ uint32_t funcn_oe_sel:1; /** funcn_oe_inv_sel : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ uint32_t funcn_oe_inv_sel:1; uint32_t reserved_12:20; @@ -413,17 +468,13 @@ typedef union { uint32_t val; } gpio_funcn_out_sel_cfg_reg_t; - -/** Group: Clock Gate Register */ /** Type of clock_gate register * GPIO clock gate register */ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; - * Configures whether or not to enable clock gate.\\ - * 0: Not enable\\ - * 1: Enable, the clock is free running. \\ + * set this bit to enable GPIO clock gate */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -431,15 +482,13 @@ typedef union { uint32_t val; } gpio_clock_gate_reg_t; - -/** Group: Version Register */ /** Type of date register * GPIO version register */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 37753392; - * Version control register. \\ + /** date : R/W; bitpos: [27:0]; default: 37823120; + * version register */ uint32_t date:28; uint32_t reserved_28:4; @@ -453,27 +502,41 @@ typedef struct { volatile gpio_out_reg_t out; volatile gpio_out_w1ts_reg_t out_w1ts; volatile gpio_out_w1tc_reg_t out_w1tc; - uint32_t reserved_010[9]; + volatile gpio_out1_reg_t out1; + volatile gpio_out1_w1ts_reg_t out1_w1ts; + volatile gpio_out1_w1tc_reg_t out1_w1tc; + uint32_t reserved_01c[6]; volatile gpio_enable_reg_t enable; volatile gpio_enable_w1ts_reg_t enable_w1ts; volatile gpio_enable_w1tc_reg_t enable_w1tc; - uint32_t reserved_040[9]; + volatile gpio_enable1_reg_t enable1; + volatile gpio_enable1_w1ts_reg_t enable1_w1ts; + volatile gpio_enable1_w1tc_reg_t enable1_w1tc; + uint32_t reserved_04c[6]; volatile gpio_in_reg_t in; - uint32_t reserved_068[3]; + volatile gpio_in1_reg_t in1; + uint32_t reserved_06c[2]; volatile gpio_status_reg_t status; volatile gpio_status_w1ts_reg_t status_w1ts; volatile gpio_status_w1tc_reg_t status_w1tc; - uint32_t reserved_080[9]; + volatile gpio_status1_reg_t status1; + volatile gpio_status1_w1ts_reg_t status1_w1ts; + volatile gpio_status1_w1tc_reg_t status1_w1tc; + uint32_t reserved_08c[6]; volatile gpio_procpu_int_reg_t procpu_int; - uint32_t reserved_0a8[3]; + volatile gpio_sdio_int_reg_t sdio_int; + volatile gpio_procpu_int1_reg_t procpu_int1; + volatile gpio_sdio_int1_reg_t sdio_int1; + uint32_t reserved_0b4[4]; volatile gpio_status_next_reg_t status_next; - uint32_t reserved_0b8[3]; - volatile gpio_pinn_reg_t pinn[25]; // 0-24 are fanned out, 25-28 are not padded out. Only 0-24 are available. - uint32_t reserved_128[103]; - volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; //0-255. reserved: 1-5, 18-26, 36-40, 44-45, 48-63, 70-71, 75-81, 84-96, 101-117, 122-255; - uint32_t reserved_4ac[256]; - volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[25]; - uint32_t reserved_b28[180]; + volatile gpio_status_next1_reg_t status_next1; + uint32_t reserved_0cc[2]; + volatile gpio_pinn_reg_t pinn[34]; // 0~29 available, 30~34 not fan out, N/A + uint32_t reserved_15c[94]; + volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; // 0-255. reserved: 1-5, 18-26, 36-40, 44-45, 48-63, 70-71, 75-81, 84-96, 101-117, 122-255 + uint32_t reserved_542[256]; + volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[34]; // 0~29 available, 30~34 not fan out, N/A + uint32_t reserved_b5c[167]; volatile gpio_clock_gate_reg_t clock_gate; volatile gpio_date_reg_t date; } gpio_dev_t; diff --git a/components/soc/esp32c61/register/soc/hp_system_reg.h b/components/soc/esp32c61/register/soc/hp_system_reg.h index 168e95015c..83459c8135 100644 --- a/components/soc/esp32c61/register/soc/hp_system_reg.h +++ b/components/soc/esp32c61/register/soc/hp_system_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,9 +16,9 @@ extern "C" { */ #define HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYSTEM_BASE + 0x0) /** HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode. + * 0: Disable + * 1: Enable */ #define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) #define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S) @@ -32,10 +32,9 @@ extern "C" { #define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U #define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 /** HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable MSPI XTS auto decryption in download boot - * mode.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable MSPI XTS auto decryption in download boot mode. + * 0: Disable + * 1: Enable */ #define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) #define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S) @@ -43,9 +42,9 @@ extern "C" { #define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 /** HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0; * Configures whether or not to enable MSPI XTS manual encryption in download boot - * mode. \\ - * 0: Disable\\ - * 1: Enable\\ + * mode. + * 0: Disable + * 1: Enable */ #define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) #define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S) @@ -56,13 +55,6 @@ extern "C" { * HP memory usage configuration register */ #define HP_SYSTEM_SRAM_USAGE_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x4) -/** HP_SYSTEM_CACHE_USAGE : HRO; bitpos: [0]; default: 0; - * reserved - */ -#define HP_SYSTEM_CACHE_USAGE (BIT(0)) -#define HP_SYSTEM_CACHE_USAGE_M (HP_SYSTEM_CACHE_USAGE_V << HP_SYSTEM_CACHE_USAGE_S) -#define HP_SYSTEM_CACHE_USAGE_V 0x00000001U -#define HP_SYSTEM_CACHE_USAGE_S 0 /** HP_SYSTEM_SRAM_USAGE : R/W; bitpos: [12:8]; default: 0; * 0: cpu use hp-memory. 1:mac-dump accessing hp-memory. */ @@ -84,11 +76,11 @@ extern "C" { #define HP_SYSTEM_SEC_DPA_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x8) /** HP_SYSTEM_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to enable anti-DPA attack. Valid only when - * HP_SYSTEM_SEC_DPA_CFG_SEL is 0. \\ - * 0: Disable\\ + * HP_SYSTEM_SEC_DPA_CFG_SEL is 0. + * 0: Disable * 1-3: Enable. The larger the number, the higher the security level, which represents * the ability to resist DPA attacks, with increased computational overhead of the - * hardware crypto-accelerators at the same time. \\ + * hardware crypto-accelerators at the same time. */ #define HP_SYSTEM_SEC_DPA_LEVEL 0x00000003U #define HP_SYSTEM_SEC_DPA_LEVEL_M (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S) @@ -96,9 +88,9 @@ extern "C" { #define HP_SYSTEM_SEC_DPA_LEVEL_S 0 /** HP_SYSTEM_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0; * Configures whether to select HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from - * eFuse) to control DPA level. \\ - * 0: Select EFUSE_SEC_DPA_LEVEL\\ - * 1: Select HP_SYSTEM_SEC_DPA_LEVEL\\ + * eFuse) to control DPA level. + * 0: Select EFUSE_SEC_DPA_LEVEL + * 1: Select HP_SYSTEM_SEC_DPA_LEVEL */ #define HP_SYSTEM_SEC_DPA_CFG_SEL (BIT(2)) #define HP_SYSTEM_SEC_DPA_CFG_SEL_M (HP_SYSTEM_SEC_DPA_CFG_SEL_V << HP_SYSTEM_SEC_DPA_CFG_SEL_S) @@ -126,9 +118,9 @@ extern "C" { #define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S 16 /** HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; * Configures whether or not to enable timeout protection for accessing CPU peripheral - * registers.\\ - * 0: Disable\\ - * 1: Enable\\ + * registers. + * 0: Disable + * 1: Enable */ #define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN (BIT(17)) #define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S) @@ -173,9 +165,9 @@ extern "C" { #define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V 0x0000FFFFU #define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S 0 /** HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear timeout interrupt.\\ - * 0: No effect\\ - * 1: Clear timeout interrupt\\ + * Configures whether or not to clear timeout interrupt. + * 0: No effect + * 1: Clear timeout interrupt */ #define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR (BIT(16)) #define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S) @@ -183,9 +175,9 @@ extern "C" { #define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S 16 /** HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; * Configures whether or not to enable timeout protection for accessing HP peripheral - * registers.\\ - * 0: Disable\\ - * 1: Enable\\ + * registers. + * 0: Disable + * 1: Enable */ #define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN (BIT(17)) #define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S) @@ -217,66 +209,14 @@ extern "C" { #define HP_SYSTEM_HP_PERI_TIMEOUT_UID_V 0x0000007FU #define HP_SYSTEM_HP_PERI_TIMEOUT_UID_S 0 -/** HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG register - * MODEM_PERI_TIMEOUT configuration register - */ -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x24) -/** HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535; - * Set the timeout threshold for bus access, corresponding to the number of clock - * cycles of the clock domain. - */ -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES 0x0000FFFFU -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S) -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V 0x0000FFFFU -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S 0 -/** HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0; - * Set this bit as 1 to clear timeout interrupt - */ -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR (BIT(16)) -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S) -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S 16 -/** HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; - * Set this bit as 1 to enable timeout protection for accessing modem registers - */ -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN (BIT(17)) -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S) -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S 17 - -/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG register - * MODEM_PERI_TIMEOUT_ADDR register - */ -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x28) -/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; - * Record the address information of abnormal access - */ -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR 0xFFFFFFFFU -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S) -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S 0 - -/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG register - * MODEM_PERI_TIMEOUT_UID register - */ -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x2c) -/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; - * Record master id[4:0] & master permission[6:5] when trigger timeout. This register - * will be cleared after the interrupt is cleared. - */ -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID 0x0000007FU -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S) -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V 0x0000007FU -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S 0 - /** HP_SYSTEM_ROM_TABLE_LOCK_REG register * ROM-Table lock register */ #define HP_SYSTEM_ROM_TABLE_LOCK_REG (DR_REG_HP_SYSTEM_BASE + 0x30) /** HP_SYSTEM_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0; - * Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. \\ - * 0: Unlock \\ - * 1: Lock \\ + * Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. + * 0: Unlock + * 1: Lock */ #define HP_SYSTEM_ROM_TABLE_LOCK (BIT(0)) #define HP_SYSTEM_ROM_TABLE_LOCK_M (HP_SYSTEM_ROM_TABLE_LOCK_V << HP_SYSTEM_ROM_TABLE_LOCK_S) @@ -357,78 +297,66 @@ extern "C" { #define HP_SYSTEM_SDPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU #define HP_SYSTEM_SDPRF_MEM_AUX_CTRL_S 0 -/** HP_SYSTEM_RND_ECO_REG register - * redcy eco register. - */ -#define HP_SYSTEM_RND_ECO_REG (DR_REG_HP_SYSTEM_BASE + 0x4c) -/** HP_SYSTEM_REDCY_ENA : W/R; bitpos: [0]; default: 0; - * Only reserved for ECO. - */ -#define HP_SYSTEM_REDCY_ENA (BIT(0)) -#define HP_SYSTEM_REDCY_ENA_M (HP_SYSTEM_REDCY_ENA_V << HP_SYSTEM_REDCY_ENA_S) -#define HP_SYSTEM_REDCY_ENA_V 0x00000001U -#define HP_SYSTEM_REDCY_ENA_S 0 -/** HP_SYSTEM_REDCY_RESULT : RO; bitpos: [1]; default: 0; - * Only reserved for ECO. - */ -#define HP_SYSTEM_REDCY_RESULT (BIT(1)) -#define HP_SYSTEM_REDCY_RESULT_M (HP_SYSTEM_REDCY_RESULT_V << HP_SYSTEM_REDCY_RESULT_S) -#define HP_SYSTEM_REDCY_RESULT_V 0x00000001U -#define HP_SYSTEM_REDCY_RESULT_S 1 - -/** HP_SYSTEM_RND_ECO_LOW_REG register - * redcy eco low register. - */ -#define HP_SYSTEM_RND_ECO_LOW_REG (DR_REG_HP_SYSTEM_BASE + 0x50) -/** HP_SYSTEM_REDCY_LOW : W/R; bitpos: [31:0]; default: 0; - * Only reserved for ECO. - */ -#define HP_SYSTEM_REDCY_LOW 0xFFFFFFFFU -#define HP_SYSTEM_REDCY_LOW_M (HP_SYSTEM_REDCY_LOW_V << HP_SYSTEM_REDCY_LOW_S) -#define HP_SYSTEM_REDCY_LOW_V 0xFFFFFFFFU -#define HP_SYSTEM_REDCY_LOW_S 0 - -/** HP_SYSTEM_RND_ECO_HIGH_REG register - * redcy eco high register. - */ -#define HP_SYSTEM_RND_ECO_HIGH_REG (DR_REG_HP_SYSTEM_BASE + 0x54) -/** HP_SYSTEM_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295; - * Only reserved for ECO. - */ -#define HP_SYSTEM_REDCY_HIGH 0xFFFFFFFFU -#define HP_SYSTEM_REDCY_HIGH_M (HP_SYSTEM_REDCY_HIGH_V << HP_SYSTEM_REDCY_HIGH_S) -#define HP_SYSTEM_REDCY_HIGH_V 0xFFFFFFFFU -#define HP_SYSTEM_REDCY_HIGH_S 0 - -/** HP_SYSTEM_DEBUG_REG register - * HP-SYSTEM debug register - */ -#define HP_SYSTEM_DEBUG_REG (DR_REG_HP_SYSTEM_BASE + 0x58) -/** HP_SYSTEM_FPGA_DEBUG : R/W; bitpos: [0]; default: 1; - * Reserved - */ -#define HP_SYSTEM_FPGA_DEBUG (BIT(0)) -#define HP_SYSTEM_FPGA_DEBUG_M (HP_SYSTEM_FPGA_DEBUG_V << HP_SYSTEM_FPGA_DEBUG_S) -#define HP_SYSTEM_FPGA_DEBUG_V 0x00000001U -#define HP_SYSTEM_FPGA_DEBUG_S 0 - /** HP_SYSTEM_CLOCK_GATE_REG register * HP-SYSTEM clock gating configure register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define HP_SYSTEM_CLOCK_GATE_REG (DR_REG_HP_SYSTEM_BASE + 0x5c) /** HP_SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0; * Set this bit as 1 to force on clock gating. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define HP_SYSTEM_CLK_EN (BIT(0)) #define HP_SYSTEM_CLK_EN_M (HP_SYSTEM_CLK_EN_V << HP_SYSTEM_CLK_EN_S) #define HP_SYSTEM_CLK_EN_V 0x00000001U #define HP_SYSTEM_CLK_EN_S 0 +/** HP_SYSTEM_AXI_MST_PRI_REG register + * AXI mst priority configuration register + */ +#define HP_SYSTEM_AXI_MST_PRI_REG (DR_REG_HP_SYSTEM_BASE + 0x60) +/** HP_SYSTEM_DMA_PRIORITY : R/W; bitpos: [0]; default: 0; + * AHB-DMA arbitration priority for command channels between masters connected to + * ext_mem_DW_axi + */ +#define HP_SYSTEM_DMA_PRIORITY (BIT(0)) +#define HP_SYSTEM_DMA_PRIORITY_M (HP_SYSTEM_DMA_PRIORITY_V << HP_SYSTEM_DMA_PRIORITY_S) +#define HP_SYSTEM_DMA_PRIORITY_V 0x00000001U +#define HP_SYSTEM_DMA_PRIORITY_S 0 +/** HP_SYSTEM_CACHE_PRIORITY : R/W; bitpos: [1]; default: 0; + * CACHE arbitration priority for command channels between masters connected to + * ext_mem_DW_axi + */ +#define HP_SYSTEM_CACHE_PRIORITY (BIT(1)) +#define HP_SYSTEM_CACHE_PRIORITY_M (HP_SYSTEM_CACHE_PRIORITY_V << HP_SYSTEM_CACHE_PRIORITY_S) +#define HP_SYSTEM_CACHE_PRIORITY_V 0x00000001U +#define HP_SYSTEM_CACHE_PRIORITY_S 1 + +/** HP_SYSTEM_SDIO_CTRL_REG register + * SDIO Control configuration register + */ +#define HP_SYSTEM_SDIO_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x64) +/** HP_SYSTEM_DIS_SDIO_PROB : R/W; bitpos: [0]; default: 1; + * Set this bit as 1 to disable SDIO_PROB function. disable by default. + */ +#define HP_SYSTEM_DIS_SDIO_PROB (BIT(0)) +#define HP_SYSTEM_DIS_SDIO_PROB_M (HP_SYSTEM_DIS_SDIO_PROB_V << HP_SYSTEM_DIS_SDIO_PROB_S) +#define HP_SYSTEM_DIS_SDIO_PROB_V 0x00000001U +#define HP_SYSTEM_DIS_SDIO_PROB_S 0 +/** HP_SYSTEM_SDIO_WIN_ACCESS_EN : R/W; bitpos: [1]; default: 1; + * Enable sdio slave to access other peripherals on the chip + */ +#define HP_SYSTEM_SDIO_WIN_ACCESS_EN (BIT(1)) +#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_M (HP_SYSTEM_SDIO_WIN_ACCESS_EN_V << HP_SYSTEM_SDIO_WIN_ACCESS_EN_S) +#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_V 0x00000001U +#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_S 1 + /** HP_SYSTEM_DATE_REG register * Date control and version control register */ #define HP_SYSTEM_DATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3fc) -/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 36769824; +/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 37823088; * Version control register. */ #define HP_SYSTEM_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c61/register/soc/hp_system_struct.h b/components/soc/esp32c61/register/soc/hp_system_struct.h index 6c786758a9..23c94a00cb 100644 --- a/components/soc/esp32c61/register/soc/hp_system_struct.h +++ b/components/soc/esp32c61/register/soc/hp_system_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,438 +11,344 @@ extern "C" { #endif /** Group: Configuration Register */ -/** Type of external_device_encrypt_decrypt_control register +/** Type of system_external_device_encrypt_decrypt_control register * External device encryption/decryption configuration register */ typedef union { struct { - /** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.\\ - * 0: Disable\\ - * 1: Enable\\ + /** system_enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode. + * 0: Disable + * 1: Enable */ - uint32_t enable_spi_manual_encrypt:1; - /** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0; + uint32_t system_enable_spi_manual_encrypt:1; + /** system_enable_download_db_encrypt : R/W; bitpos: [1]; default: 0; * reserved */ - uint32_t enable_download_db_encrypt:1; - /** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable MSPI XTS auto decryption in download boot - * mode.\\ - * 0: Disable\\ - * 1: Enable\\ + uint32_t system_enable_download_db_encrypt:1; + /** system_enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable MSPI XTS auto decryption in download boot mode. + * 0: Disable + * 1: Enable */ - uint32_t enable_download_g0cb_decrypt:1; - /** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0; + uint32_t system_enable_download_g0cb_decrypt:1; + /** system_enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0; * Configures whether or not to enable MSPI XTS manual encryption in download boot - * mode. \\ - * 0: Disable\\ - * 1: Enable\\ + * mode. + * 0: Disable + * 1: Enable */ - uint32_t enable_download_manual_encrypt:1; + uint32_t system_enable_download_manual_encrypt:1; uint32_t reserved_4:28; }; uint32_t val; } hp_system_external_device_encrypt_decrypt_control_reg_t; -/** Type of sram_usage_conf register +/** Type of system_sram_usage_conf register * HP memory usage configuration register */ typedef union { struct { - /** cache_usage : HRO; bitpos: [0]; default: 0; - * reserved - */ - uint32_t cache_usage:1; - uint32_t reserved_1:7; - /** sram_usage : R/W; bitpos: [12:8]; default: 0; + uint32_t reserved_0:8; + /** system_sram_usage : R/W; bitpos: [12:8]; default: 0; * 0: cpu use hp-memory. 1:mac-dump accessing hp-memory. */ - uint32_t sram_usage:5; + uint32_t system_sram_usage:5; uint32_t reserved_13:3; - /** mac_dump_alloc : R/W; bitpos: [16]; default: 0; + /** system_mac_dump_alloc : R/W; bitpos: [16]; default: 0; * Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory. */ - uint32_t mac_dump_alloc:1; + uint32_t system_mac_dump_alloc:1; uint32_t reserved_17:15; }; uint32_t val; } hp_system_sram_usage_conf_reg_t; -/** Type of sec_dpa_conf register +/** Type of system_sec_dpa_conf register * HP anti-DPA security configuration register */ typedef union { struct { - /** sec_dpa_level : R/W; bitpos: [1:0]; default: 0; + /** system_sec_dpa_level : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to enable anti-DPA attack. Valid only when - * HP_SYSTEM_SEC_DPA_CFG_SEL is 0. \\ - * 0: Disable\\ + * HP_SYSTEM_SEC_DPA_CFG_SEL is 0. + * 0: Disable * 1-3: Enable. The larger the number, the higher the security level, which represents * the ability to resist DPA attacks, with increased computational overhead of the - * hardware crypto-accelerators at the same time. \\ + * hardware crypto-accelerators at the same time. */ - uint32_t sec_dpa_level:2; - /** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0; + uint32_t system_sec_dpa_level:2; + /** system_sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0; * Configures whether to select HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from - * eFuse) to control DPA level. \\ - * 0: Select EFUSE_SEC_DPA_LEVEL\\ - * 1: Select HP_SYSTEM_SEC_DPA_LEVEL\\ + * eFuse) to control DPA level. + * 0: Select EFUSE_SEC_DPA_LEVEL + * 1: Select HP_SYSTEM_SEC_DPA_LEVEL */ - uint32_t sec_dpa_cfg_sel:1; + uint32_t system_sec_dpa_cfg_sel:1; uint32_t reserved_3:29; }; uint32_t val; } hp_system_sec_dpa_conf_reg_t; -/** Type of rom_table_lock register +/** Type of system_rom_table_lock register * ROM-Table lock register */ typedef union { struct { - /** rom_table_lock : R/W; bitpos: [0]; default: 0; - * Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. \\ - * 0: Unlock \\ - * 1: Lock \\ + /** system_rom_table_lock : R/W; bitpos: [0]; default: 0; + * Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. + * 0: Unlock + * 1: Lock */ - uint32_t rom_table_lock:1; + uint32_t system_rom_table_lock:1; uint32_t reserved_1:31; }; uint32_t val; } hp_system_rom_table_lock_reg_t; -/** Type of rom_table register +/** Type of system_rom_table register * ROM-Table register */ typedef union { struct { - /** rom_table : R/W; bitpos: [31:0]; default: 0; + /** system_rom_table : R/W; bitpos: [31:0]; default: 0; * Software ROM-Table register, whose content can be modified only when * HP_SYSTEM_ROM_TABLE_LOCK is 0. */ - uint32_t rom_table:32; + uint32_t system_rom_table:32; }; uint32_t val; } hp_system_rom_table_reg_t; -/** Type of core_debug_runstall_conf register +/** Type of system_core_debug_runstall_conf register * Core Debug RunStall configurion register */ typedef union { struct { uint32_t reserved_0:1; - /** core_runstalled : RO; bitpos: [1]; default: 0; + /** system_core_runstalled : RO; bitpos: [1]; default: 0; * Software can read this field to get the runstall status of hp-core. 1: stalled, 0: * not stalled. */ - uint32_t core_runstalled:1; + uint32_t system_core_runstalled:1; uint32_t reserved_2:30; }; uint32_t val; } hp_system_core_debug_runstall_conf_reg_t; -/** Type of sprom_ctrl register +/** Type of system_sprom_ctrl register * reserved */ typedef union { struct { - /** sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 112; + /** system_sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 112; * reserved */ - uint32_t sprom_mem_aux_ctrl:32; + uint32_t system_sprom_mem_aux_ctrl:32; }; uint32_t val; } hp_system_sprom_ctrl_reg_t; -/** Type of spram_ctrl register +/** Type of system_spram_ctrl register * reserved */ typedef union { struct { - /** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; + /** system_spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; * reserved */ - uint32_t spram_mem_aux_ctrl:32; + uint32_t system_spram_mem_aux_ctrl:32; }; uint32_t val; } hp_system_spram_ctrl_reg_t; -/** Type of sprf_ctrl register +/** Type of system_sprf_ctrl register * reserved */ typedef union { struct { - /** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; + /** system_sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; * reserved */ - uint32_t sprf_mem_aux_ctrl:32; + uint32_t system_sprf_mem_aux_ctrl:32; }; uint32_t val; } hp_system_sprf_ctrl_reg_t; -/** Type of sdprf_ctrl register +/** Type of system_sdprf_ctrl register * reserved */ typedef union { struct { - /** sdprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 0; + /** system_sdprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 0; * reserved */ - uint32_t sdprf_mem_aux_ctrl:32; + uint32_t system_sdprf_mem_aux_ctrl:32; }; uint32_t val; } hp_system_sdprf_ctrl_reg_t; -/** Type of clock_gate register - * HP-SYSTEM clock gating configure register +/** Type of system_axi_mst_pri register + * AXI mst priority configuration register */ typedef union { struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * Set this bit as 1 to force on clock gating. + /** system_dma_priority : R/W; bitpos: [0]; default: 0; + * AHB-DMA arbitration priority for command channels between masters connected to + * ext_mem_DW_axi */ - uint32_t clk_en:1; - uint32_t reserved_1:31; + uint32_t system_dma_priority:1; + /** system_cache_priority : R/W; bitpos: [1]; default: 0; + * CACHE arbitration priority for command channels between masters connected to + * ext_mem_DW_axi + */ + uint32_t system_cache_priority:1; + uint32_t reserved_2:30; }; uint32_t val; -} hp_system_clock_gate_reg_t; +} hp_system_axi_mst_pri_reg_t; + +/** Type of system_sdio_ctrl register + * SDIO Control configuration register + */ +typedef union { + struct { + /** system_dis_sdio_prob : R/W; bitpos: [0]; default: 1; + * Set this bit as 1 to disable SDIO_PROB function. disable by default. + */ + uint32_t system_dis_sdio_prob:1; + /** system_sdio_win_access_en : R/W; bitpos: [1]; default: 1; + * Enable sdio slave to access other peripherals on the chip + */ + uint32_t system_sdio_win_access_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_system_sdio_ctrl_reg_t; /** Group: Timeout Register */ -/** Type of cpu_peri_timeout_conf register +/** Type of system_cpu_peri_timeout_conf register * CPU_PERI_TIMEOUT configuration register */ typedef union { struct { - /** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; + /** system_cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; * Configures the timeout threshold for bus access for accessing CPU peripheral * register in the number of clock cycles of the clock domain. */ - uint32_t cpu_peri_timeout_thres:16; - /** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; + uint32_t system_cpu_peri_timeout_thres:16; + /** system_cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; * Write 1 to clear timeout interrupt. */ - uint32_t cpu_peri_timeout_int_clear:1; - /** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; + uint32_t system_cpu_peri_timeout_int_clear:1; + /** system_cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; * Configures whether or not to enable timeout protection for accessing CPU peripheral - * registers.\\ - * 0: Disable\\ - * 1: Enable\\ + * registers. + * 0: Disable + * 1: Enable */ - uint32_t cpu_peri_timeout_protect_en:1; + uint32_t system_cpu_peri_timeout_protect_en:1; uint32_t reserved_18:14; }; uint32_t val; } hp_system_cpu_peri_timeout_conf_reg_t; -/** Type of cpu_peri_timeout_addr register +/** Type of system_cpu_peri_timeout_addr register * CPU_PERI_TIMEOUT_ADDR register */ typedef union { struct { - /** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + /** system_cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; * Represents the address information of abnormal access. */ - uint32_t cpu_peri_timeout_addr:32; + uint32_t system_cpu_peri_timeout_addr:32; }; uint32_t val; } hp_system_cpu_peri_timeout_addr_reg_t; -/** Type of cpu_peri_timeout_uid register +/** Type of system_cpu_peri_timeout_uid register * CPU_PERI_TIMEOUT_UID register */ typedef union { struct { - /** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + /** system_cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; * Represents the master id[4:0] and master permission[6:5] when trigger timeout. This * register will be cleared after the interrupt is cleared. */ - uint32_t cpu_peri_timeout_uid:7; + uint32_t system_cpu_peri_timeout_uid:7; uint32_t reserved_7:25; }; uint32_t val; } hp_system_cpu_peri_timeout_uid_reg_t; -/** Type of hp_peri_timeout_conf register +/** Type of system_hp_peri_timeout_conf register * HP_PERI_TIMEOUT configuration register */ typedef union { struct { - /** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; + /** system_hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; * Configures the timeout threshold for bus access for accessing HP peripheral * register, corresponding to the number of clock cycles of the clock domain. */ - uint32_t hp_peri_timeout_thres:16; - /** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear timeout interrupt.\\ - * 0: No effect\\ - * 1: Clear timeout interrupt\\ + uint32_t system_hp_peri_timeout_thres:16; + /** system_hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear timeout interrupt. + * 0: No effect + * 1: Clear timeout interrupt */ - uint32_t hp_peri_timeout_int_clear:1; - /** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; + uint32_t system_hp_peri_timeout_int_clear:1; + /** system_hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; * Configures whether or not to enable timeout protection for accessing HP peripheral - * registers.\\ - * 0: Disable\\ - * 1: Enable\\ + * registers. + * 0: Disable + * 1: Enable */ - uint32_t hp_peri_timeout_protect_en:1; + uint32_t system_hp_peri_timeout_protect_en:1; uint32_t reserved_18:14; }; uint32_t val; } hp_system_hp_peri_timeout_conf_reg_t; -/** Type of hp_peri_timeout_addr register +/** Type of system_hp_peri_timeout_addr register * HP_PERI_TIMEOUT_ADDR register */ typedef union { struct { - /** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + /** system_hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; * Represents the address information of abnormal access. */ - uint32_t hp_peri_timeout_addr:32; + uint32_t system_hp_peri_timeout_addr:32; }; uint32_t val; } hp_system_hp_peri_timeout_addr_reg_t; -/** Type of hp_peri_timeout_uid register +/** Type of system_hp_peri_timeout_uid register * HP_PERI_TIMEOUT_UID register */ typedef union { struct { - /** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + /** system_hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; * Represents the master id[4:0] and master permission[6:5] when trigger timeout. This * register will be cleared after the interrupt is cleared. */ - uint32_t hp_peri_timeout_uid:7; + uint32_t system_hp_peri_timeout_uid:7; uint32_t reserved_7:25; }; uint32_t val; } hp_system_hp_peri_timeout_uid_reg_t; -/** Type of modem_peri_timeout_conf register - * MODEM_PERI_TIMEOUT configuration register - */ -typedef union { - struct { - /** modem_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; - * Set the timeout threshold for bus access, corresponding to the number of clock - * cycles of the clock domain. - */ - uint32_t modem_peri_timeout_thres:16; - /** modem_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; - * Set this bit as 1 to clear timeout interrupt - */ - uint32_t modem_peri_timeout_int_clear:1; - /** modem_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; - * Set this bit as 1 to enable timeout protection for accessing modem registers - */ - uint32_t modem_peri_timeout_protect_en:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} hp_system_modem_peri_timeout_conf_reg_t; - -/** Type of modem_peri_timeout_addr register - * MODEM_PERI_TIMEOUT_ADDR register - */ -typedef union { - struct { - /** modem_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; - * Record the address information of abnormal access - */ - uint32_t modem_peri_timeout_addr:32; - }; - uint32_t val; -} hp_system_modem_peri_timeout_addr_reg_t; - -/** Type of modem_peri_timeout_uid register - * MODEM_PERI_TIMEOUT_UID register - */ -typedef union { - struct { - /** modem_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; - * Record master id[4:0] & master permission[6:5] when trigger timeout. This register - * will be cleared after the interrupt is cleared. - */ - uint32_t modem_peri_timeout_uid:7; - uint32_t reserved_7:25; - }; - uint32_t val; -} hp_system_modem_peri_timeout_uid_reg_t; - - -/** Group: Redcy ECO Registers */ -/** Type of rnd_eco register - * redcy eco register. - */ -typedef union { - struct { - /** redcy_ena : W/R; bitpos: [0]; default: 0; - * Only reserved for ECO. - */ - uint32_t redcy_ena:1; - /** redcy_result : RO; bitpos: [1]; default: 0; - * Only reserved for ECO. - */ - uint32_t redcy_result:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} hp_system_rnd_eco_reg_t; - -/** Type of rnd_eco_low register - * redcy eco low register. - */ -typedef union { - struct { - /** redcy_low : W/R; bitpos: [31:0]; default: 0; - * Only reserved for ECO. - */ - uint32_t redcy_low:32; - }; - uint32_t val; -} hp_system_rnd_eco_low_reg_t; - -/** Type of rnd_eco_high register - * redcy eco high register. - */ -typedef union { - struct { - /** redcy_high : W/R; bitpos: [31:0]; default: 4294967295; - * Only reserved for ECO. - */ - uint32_t redcy_high:32; - }; - uint32_t val; -} hp_system_rnd_eco_high_reg_t; - - -/** Group: Debug Register */ -/** Type of debug register - * HP-SYSTEM debug register - */ -typedef union { - struct { - /** fpga_debug : R/W; bitpos: [0]; default: 1; - * Reserved - */ - uint32_t fpga_debug:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} hp_system_debug_reg_t; - /** Group: Version Register */ -/** Type of date register +/** Type of system_date register * Date control and version control register */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36769824; + /** system_date : R/W; bitpos: [27:0]; default: 37823088; * Version control register. */ - uint32_t date:28; + uint32_t system_date:28; uint32_t reserved_28:4; }; uint32_t val; @@ -450,32 +356,28 @@ typedef union { typedef struct { - volatile hp_system_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control; - volatile hp_system_sram_usage_conf_reg_t sram_usage_conf; - volatile hp_system_sec_dpa_conf_reg_t sec_dpa_conf; - volatile hp_system_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf; - volatile hp_system_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr; - volatile hp_system_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid; - volatile hp_system_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf; - volatile hp_system_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr; - volatile hp_system_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid; - volatile hp_system_modem_peri_timeout_conf_reg_t modem_peri_timeout_conf; - volatile hp_system_modem_peri_timeout_addr_reg_t modem_peri_timeout_addr; - volatile hp_system_modem_peri_timeout_uid_reg_t modem_peri_timeout_uid; - volatile hp_system_rom_table_lock_reg_t rom_table_lock; - volatile hp_system_rom_table_reg_t rom_table; - volatile hp_system_core_debug_runstall_conf_reg_t core_debug_runstall_conf; - volatile hp_system_sprom_ctrl_reg_t sprom_ctrl; - volatile hp_system_spram_ctrl_reg_t spram_ctrl; - volatile hp_system_sprf_ctrl_reg_t sprf_ctrl; - volatile hp_system_sdprf_ctrl_reg_t sdprf_ctrl; - volatile hp_system_rnd_eco_reg_t rnd_eco; - volatile hp_system_rnd_eco_low_reg_t rnd_eco_low; - volatile hp_system_rnd_eco_high_reg_t rnd_eco_high; - volatile hp_system_debug_reg_t debug; - volatile hp_system_clock_gate_reg_t clock_gate; - uint32_t reserved_060[231]; - volatile hp_system_date_reg_t date; + volatile hp_system_external_device_encrypt_decrypt_control_reg_t system_external_device_encrypt_decrypt_control; + volatile hp_system_sram_usage_conf_reg_t system_sram_usage_conf; + volatile hp_system_sec_dpa_conf_reg_t system_sec_dpa_conf; + volatile hp_system_cpu_peri_timeout_conf_reg_t system_cpu_peri_timeout_conf; + volatile hp_system_cpu_peri_timeout_addr_reg_t system_cpu_peri_timeout_addr; + volatile hp_system_cpu_peri_timeout_uid_reg_t system_cpu_peri_timeout_uid; + volatile hp_system_hp_peri_timeout_conf_reg_t system_hp_peri_timeout_conf; + volatile hp_system_hp_peri_timeout_addr_reg_t system_hp_peri_timeout_addr; + volatile hp_system_hp_peri_timeout_uid_reg_t system_hp_peri_timeout_uid; + uint32_t reserved_024[3]; + volatile hp_system_rom_table_lock_reg_t system_rom_table_lock; + volatile hp_system_rom_table_reg_t system_rom_table; + volatile hp_system_core_debug_runstall_conf_reg_t system_core_debug_runstall_conf; + volatile hp_system_sprom_ctrl_reg_t system_sprom_ctrl; + volatile hp_system_spram_ctrl_reg_t system_spram_ctrl; + volatile hp_system_sprf_ctrl_reg_t system_sprf_ctrl; + volatile hp_system_sdprf_ctrl_reg_t system_sdprf_ctrl; + uint32_t reserved_04c[5]; + volatile hp_system_axi_mst_pri_reg_t system_axi_mst_pri; + volatile hp_system_sdio_ctrl_reg_t system_sdio_ctrl; + uint32_t reserved_068[229]; + volatile hp_system_date_reg_t system_date; } hp_system_dev_t; extern hp_system_dev_t HP_SYSTEM; diff --git a/components/soc/esp32c61/register/soc/i2c_reg.h b/components/soc/esp32c61/register/soc/i2c_reg.h index 07e1c4309d..cd4228ee9b 100644 --- a/components/soc/esp32c61/register/soc/i2c_reg.h +++ b/components/soc/esp32c61/register/soc/i2c_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,8 +17,8 @@ extern "C" { */ #define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0) /** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; - * Configures the low level width of the SCL Clock in master mode. \\ - * Measurement unit: i2c_sclk \\ + * Configures the low level width of the SCL Clock in master mode. + * Measurement unit: i2c_sclk */ #define I2C_SCL_LOW_PERIOD 0x000001FFU #define I2C_SCL_LOW_PERIOD_M (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S) @@ -30,27 +30,27 @@ extern "C" { */ #define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4) /** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0; - * Configures the SDA output mode.\\ - * 0: Open drain output \\ - * 1: Direct output \\ + * Configures the SDA output mode. + * 0: Open drain output + * 1: Direct output */ #define I2C_SDA_FORCE_OUT (BIT(0)) #define I2C_SDA_FORCE_OUT_M (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S) #define I2C_SDA_FORCE_OUT_V 0x00000001U #define I2C_SDA_FORCE_OUT_S 0 /** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0; - * Configures the SCL output mode.\\ - * 0: Open drain output \\ - * 1: Direct output \\ + * Configures the SCL output mode. + * 0: Open drain output + * 1: Direct output */ #define I2C_SCL_FORCE_OUT (BIT(1)) #define I2C_SCL_FORCE_OUT_M (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S) #define I2C_SCL_FORCE_OUT_V 0x00000001U #define I2C_SCL_FORCE_OUT_S 1 /** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; - * Configures the sample mode for SDA.\\ - * 0: Sample SDA data on the SCL high level \\ - * 1: Sample SDA data on the SCL low level \\ + * Configures the sample mode for SDA. + * 0: Sample SDA data on the SCL high level + * 1: Sample SDA data on the SCL low level */ #define I2C_SAMPLE_SCL_LEVEL (BIT(2)) #define I2C_SAMPLE_SCL_LEVEL_M (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S) @@ -58,24 +58,24 @@ extern "C" { #define I2C_SAMPLE_SCL_LEVEL_S 2 /** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; * Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has - * reached the threshold.\\ + * reached the threshold. */ #define I2C_RX_FULL_ACK_LEVEL (BIT(3)) #define I2C_RX_FULL_ACK_LEVEL_M (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S) #define I2C_RX_FULL_ACK_LEVEL_V 0x00000001U #define I2C_RX_FULL_ACK_LEVEL_S 3 /** I2C_MS_MODE : R/W; bitpos: [4]; default: 0; - * Configures the module as an I2C Master or Slave.\\ - * 0: Slave \\ - * 1: Master \\ + * Configures the module as an I2C Master or Slave. + * 0: Slave + * 1: Master */ #define I2C_MS_MODE (BIT(4)) #define I2C_MS_MODE_M (I2C_MS_MODE_V << I2C_MS_MODE_S) #define I2C_MS_MODE_V 0x00000001U #define I2C_MS_MODE_S 4 /** I2C_TRANS_START : WT; bitpos: [5]; default: 0; - * Configures whether the slave starts sending the data in txfifo.\\ - * 0: No effect \\ + * Configures whether the slave starts sending the data in txfifo. + * 0: No effect * 1: Start */ #define I2C_TRANS_START (BIT(5)) @@ -83,44 +83,44 @@ extern "C" { #define I2C_TRANS_START_V 0x00000001U #define I2C_TRANS_START_S 5 /** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; - * Configures to control the sending order for data needing to be sent.\\ - * 0: send data from the most significant bit \\ - * 1: send data from the least significant bit \\ + * Configures to control the sending order for data needing to be sent. + * 0: send data from the most significant bit + * 1: send data from the least significant bit */ #define I2C_TX_LSB_FIRST (BIT(6)) #define I2C_TX_LSB_FIRST_M (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S) #define I2C_TX_LSB_FIRST_V 0x00000001U #define I2C_TX_LSB_FIRST_S 6 /** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; - * Configures to control the storage order for received data.\\ - * 0: receive data from the most significant bit \\ - * 1: receive data from the least significant bit \\ + * Configures to control the storage order for received data. + * 0: receive data from the most significant bit + * 1: receive data from the least significant bit */ #define I2C_RX_LSB_FIRST (BIT(7)) #define I2C_RX_LSB_FIRST_M (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S) #define I2C_RX_LSB_FIRST_V 0x00000001U #define I2C_RX_LSB_FIRST_S 7 /** I2C_CLK_EN : R/W; bitpos: [8]; default: 0; - * Configures whether to gate clock signal for registers.\\ - * 0: Support clock only when registers are read or written to by software \\ - * 1: Force clock on for registers \\ + * Configures whether to gate clock signal for registers. + * 0: Support clock only when registers are read or written to by software + * 1: Force clock on for registers */ #define I2C_CLK_EN (BIT(8)) #define I2C_CLK_EN_M (I2C_CLK_EN_V << I2C_CLK_EN_S) #define I2C_CLK_EN_V 0x00000001U #define I2C_CLK_EN_S 8 /** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; - * Configures to enable I2C bus arbitration detection.\\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable I2C bus arbitration detection. + * 0: No effect + * 1: Enable */ #define I2C_ARBITRATION_EN (BIT(9)) #define I2C_ARBITRATION_EN_M (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S) #define I2C_ARBITRATION_EN_V 0x00000001U #define I2C_ARBITRATION_EN_S 9 /** I2C_FSM_RST : WT; bitpos: [10]; default: 0; - * Configures to reset the SCL_FSM.\\ - * 0: No effect \\ + * Configures to reset the SCL_FSM. + * 0: No effect * 1: Reset */ #define I2C_FSM_RST (BIT(10)) @@ -128,8 +128,8 @@ extern "C" { #define I2C_FSM_RST_V 0x00000001U #define I2C_FSM_RST_S 10 /** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; - * Configures this bit for synchronization.\\ - * 0: No effect \\ + * Configures this bit for synchronization. + * 0: No effect * 1: Synchronize */ #define I2C_CONF_UPGATE (BIT(11)) @@ -137,17 +137,17 @@ extern "C" { #define I2C_CONF_UPGATE_V 0x00000001U #define I2C_CONF_UPGATE_S 11 /** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0; - * Configures to enable slave to send data automatically\\ - * 0: Disable\\ - * 1: Enable \\ + * Configures to enable slave to send data automatically + * 0: Disable + * 1: Enable */ #define I2C_SLV_TX_AUTO_START_EN (BIT(12)) #define I2C_SLV_TX_AUTO_START_EN_M (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S) #define I2C_SLV_TX_AUTO_START_EN_V 0x00000001U #define I2C_SLV_TX_AUTO_START_EN_S 12 /** I2C_ADDR_10BIT_RW_CHECK_EN : R/W; bitpos: [13]; default: 0; - * Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.\\ - * 0: Not check\\ + * Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. + * 0: Not check * 1: Check */ #define I2C_ADDR_10BIT_RW_CHECK_EN (BIT(13)) @@ -155,9 +155,9 @@ extern "C" { #define I2C_ADDR_10BIT_RW_CHECK_EN_V 0x00000001U #define I2C_ADDR_10BIT_RW_CHECK_EN_S 13 /** I2C_ADDR_BROADCASTING_EN : R/W; bitpos: [14]; default: 0; - * Configures to support the 7 bit general call function.\\ - * 0: Not support \\ - * 1: Support \\ + * Configures to support the 7 bit general call function. + * 0: Not support + * 1: Support */ #define I2C_ADDR_BROADCASTING_EN (BIT(14)) #define I2C_ADDR_BROADCASTING_EN_M (I2C_ADDR_BROADCASTING_EN_V << I2C_ADDR_BROADCASTING_EN_S) @@ -169,8 +169,8 @@ extern "C" { */ #define I2C_SR_REG (DR_REG_I2C_BASE + 0x8) /** I2C_RESP_REC : RO; bitpos: [0]; default: 0; - * Represents the received ACK value in master mode or slave mode.\\ - * 0: ACK\\ + * Represents the received ACK value in master mode or slave mode. + * 0: ACK * 1: NACK. */ #define I2C_RESP_REC (BIT(0)) @@ -178,8 +178,8 @@ extern "C" { #define I2C_RESP_REC_V 0x00000001U #define I2C_RESP_REC_S 0 /** I2C_SLAVE_RW : RO; bitpos: [1]; default: 0; - * Represents the transfer direction in slave mode.\\ - * 1: Master reads from slave\\ + * Represents the transfer direction in slave mode. + * 1: Master reads from slave * 0: Master writes to slave. */ #define I2C_SLAVE_RW (BIT(1)) @@ -187,18 +187,18 @@ extern "C" { #define I2C_SLAVE_RW_V 0x00000001U #define I2C_SLAVE_RW_S 1 /** I2C_ARB_LOST : RO; bitpos: [3]; default: 0; - * Represents whether the I2C controller loses control of SCL line.\\ - * 0: No arbitration lost\\ - * 1: Arbitration lost\\ + * Represents whether the I2C controller loses control of SCL line. + * 0: No arbitration lost + * 1: Arbitration lost */ #define I2C_ARB_LOST (BIT(3)) #define I2C_ARB_LOST_M (I2C_ARB_LOST_V << I2C_ARB_LOST_S) #define I2C_ARB_LOST_V 0x00000001U #define I2C_ARB_LOST_S 3 /** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; - * Represents the I2C bus state.\\ - * 1: The I2C bus is busy transferring data\\ - * 0: The I2C bus is in idle state.\\ + * Represents the I2C bus state. + * 1: The I2C bus is busy transferring data + * 0: The I2C bus is in idle state. */ #define I2C_BUS_BUSY (BIT(4)) #define I2C_BUS_BUSY_M (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S) @@ -206,10 +206,10 @@ extern "C" { #define I2C_BUS_BUSY_S 4 /** I2C_SLAVE_ADDRESSED : RO; bitpos: [5]; default: 0; * Represents whether the address sent by the master is equal to the address of the - * slave.\\ - * Valid only when the module is configured as an I2C Slave.\\ - * 0: Not equal\\ - * 1: Equal\\ + * slave. + * Valid only when the module is configured as an I2C Slave. + * 0: Not equal + * 1: Equal */ #define I2C_SLAVE_ADDRESSED (BIT(5)) #define I2C_SLAVE_ADDRESSED_M (I2C_SLAVE_ADDRESSED_V << I2C_SLAVE_ADDRESSED_S) @@ -223,9 +223,9 @@ extern "C" { #define I2C_RXFIFO_CNT_V 0x0000003FU #define I2C_RXFIFO_CNT_S 8 /** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 3; - * Represents the cause of SCL clocking stretching in slave mode.\\ - * 0: Stretching SCL low when the master starts to read data.\\ - * 1: Stretching SCL low when I2C TX FIFO is empty in slave mode.\\ + * Represents the cause of SCL clocking stretching in slave mode. + * 0: Stretching SCL low when the master starts to read data. + * 1: Stretching SCL low when I2C TX FIFO is empty in slave mode. * 2: Stretching SCL low when I2C RX FIFO is full in slave mode. */ #define I2C_STRETCH_CAUSE 0x00000003U @@ -240,13 +240,13 @@ extern "C" { #define I2C_TXFIFO_CNT_V 0x0000003FU #define I2C_TXFIFO_CNT_S 18 /** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; - * Represents the states of the I2C module state machine.\\ - * 0: Idle\\ - * 1: Address shift\\ - * 2: ACK address\\ - * 3: Rx data\\ - * 4: Tx data\\ - * 5: Send ACK\\ + * Represents the states of the I2C module state machine. + * 0: Idle + * 1: Address shift + * 2: ACK address + * 3: Rx data + * 4: Tx data + * 5: Send ACK * 6: Wait ACK */ #define I2C_SCL_MAIN_STATE_LAST 0x00000007U @@ -254,13 +254,13 @@ extern "C" { #define I2C_SCL_MAIN_STATE_LAST_V 0x00000007U #define I2C_SCL_MAIN_STATE_LAST_S 24 /** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; - * Represents the states of the state machine used to produce SCL.\\ - * 0: Idle\\ - * 1: Start\\ - * 2: Negative edge\\ - * 3: Low\\ - * 4: Positive edge\\ - * 5: High\\ + * Represents the states of the state machine used to produce SCL. + * 0: Idle + * 1: Start + * 2: Negative edge + * 3: Low + * 4: Positive edge + * 5: High * 6: Stop */ #define I2C_SCL_STATE_LAST 0x00000007U @@ -274,17 +274,17 @@ extern "C" { #define I2C_TO_REG (DR_REG_I2C_BASE + 0xc) /** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; * Configures the timeout threshold period for SCL stucking at high or low level. The - * actual period is 2\^{}(reg_time_out_value).\\ - * Measurement unit: i2c_sclk \\ + * actual period is 2\^{}(reg_time_out_value). + * Measurement unit: i2c_sclk */ #define I2C_TIME_OUT_VALUE 0x0000001FU #define I2C_TIME_OUT_VALUE_M (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S) #define I2C_TIME_OUT_VALUE_V 0x0000001FU #define I2C_TIME_OUT_VALUE_S 0 /** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; - * Configures to enable time out control.\\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable time out control. + * 0: No effect + * 1: Enable */ #define I2C_TIME_OUT_EN (BIT(5)) #define I2C_TIME_OUT_EN_M (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S) @@ -296,16 +296,16 @@ extern "C" { */ #define I2C_SLAVE_ADDR_REG (DR_REG_I2C_BASE + 0x10) /** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0; - * Configure the slave address of I2C Slave.\\ + * Configure the slave address of I2C Slave. */ #define I2C_SLAVE_ADDR 0x00007FFFU #define I2C_SLAVE_ADDR_M (I2C_SLAVE_ADDR_V << I2C_SLAVE_ADDR_S) #define I2C_SLAVE_ADDR_V 0x00007FFFU #define I2C_SLAVE_ADDR_S 0 /** I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0; - * Configures to enable the slave 10-bit addressing mode in master mode.\\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable the slave 10-bit addressing mode in master mode. + * 0: No effect + * 1: Enable */ #define I2C_ADDR_10BIT_EN (BIT(31)) #define I2C_ADDR_10BIT_EN_M (I2C_ADDR_10BIT_EN_V << I2C_ADDR_10BIT_EN_S) @@ -387,17 +387,17 @@ extern "C" { /** I2C_FIFO_ADDR_CFG_EN : R/W; bitpos: [11]; default: 0; * Configures the slave to enable dual address mode. When this mode is enabled, the * byte received after the I2C address byte represents the offset address in the I2C - * Slave RAM. \\ - * 0: Disable\\ - * 1: Enable \\ + * Slave RAM. + * 0: Disable + * 1: Enable */ #define I2C_FIFO_ADDR_CFG_EN (BIT(11)) #define I2C_FIFO_ADDR_CFG_EN_M (I2C_FIFO_ADDR_CFG_EN_V << I2C_FIFO_ADDR_CFG_EN_S) #define I2C_FIFO_ADDR_CFG_EN_V 0x00000001U #define I2C_FIFO_ADDR_CFG_EN_S 11 /** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; - * Configures to reset RXFIFO.\\ - * 0: No effect \\ + * Configures to reset RXFIFO. + * 0: No effect * 1: Reset */ #define I2C_RX_FIFO_RST (BIT(12)) @@ -405,8 +405,8 @@ extern "C" { #define I2C_RX_FIFO_RST_V 0x00000001U #define I2C_RX_FIFO_RST_S 12 /** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; - * Configures to reset TXFIFO.\\ - * 0: No effect \\ + * Configures to reset TXFIFO. + * 0: No effect * 1: Reset */ #define I2C_TX_FIFO_RST (BIT(13)) @@ -415,9 +415,9 @@ extern "C" { #define I2C_TX_FIFO_RST_S 13 /** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; * Configures to enable FIFO pointer in non-fifo access mode. This bit controls the - * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.\\ - * 0: No effect \\ - * 1: Enable \\ + * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. + * 0: No effect + * 1: Enable */ #define I2C_FIFO_PRT_EN (BIT(14)) #define I2C_FIFO_PRT_EN_M (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S) @@ -993,8 +993,8 @@ extern "C" { */ #define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30) /** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; - * Configures the time to hold the data after the falling edge of SCL.\\ - * Measurement unit: i2c_sclk \\ + * Configures the time to hold the data after the falling edge of SCL. + * Measurement unit: i2c_sclk */ #define I2C_SDA_HOLD_TIME 0x000001FFU #define I2C_SDA_HOLD_TIME_M (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S) @@ -1006,8 +1006,8 @@ extern "C" { */ #define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34) /** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; - * Configures the time for sampling SDA.\\ - * Measurement unit: i2c_sclk \\ + * Configures the time for sampling SDA. + * Measurement unit: i2c_sclk */ #define I2C_SDA_SAMPLE_TIME 0x000001FFU #define I2C_SDA_SAMPLE_TIME_M (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S) @@ -1019,16 +1019,16 @@ extern "C" { */ #define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38) /** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; - * Configures for how long SCL remains high in master mode.\\ - * Measurement unit: i2c_sclk \\ + * Configures for how long SCL remains high in master mode. + * Measurement unit: i2c_sclk */ #define I2C_SCL_HIGH_PERIOD 0x000001FFU #define I2C_SCL_HIGH_PERIOD_M (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S) #define I2C_SCL_HIGH_PERIOD_V 0x000001FFU #define I2C_SCL_HIGH_PERIOD_S 0 /** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; - * Configures the SCL_FSM's waiting period for SCL high level in master mode.\\ - * Measurement unit: i2c_sclk \\ + * Configures the SCL_FSM's waiting period for SCL high level in master mode. + * Measurement unit: i2c_sclk */ #define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU #define I2C_SCL_WAIT_HIGH_PERIOD_M (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S) @@ -1041,8 +1041,8 @@ extern "C" { #define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40) /** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; * Configures the time between the falling edge of SDA and the falling edge of SCL for - * a START condition.\\ - * Measurement unit: i2c_sclk \\ + * a START condition. + * Measurement unit: i2c_sclk */ #define I2C_SCL_START_HOLD_TIME 0x000001FFU #define I2C_SCL_START_HOLD_TIME_M (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S) @@ -1056,8 +1056,8 @@ extern "C" { #define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44) /** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; * Configures the time between the positive edge of SCL and the negative edge of SDA - * for a RESTART condition.\\ - * Measurement unit: i2c_sclk \\ + * for a RESTART condition. + * Measurement unit: i2c_sclk */ #define I2C_SCL_RSTART_SETUP_TIME 0x000001FFU #define I2C_SCL_RSTART_SETUP_TIME_M (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S) @@ -1070,8 +1070,8 @@ extern "C" { */ #define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48) /** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; - * Configures the delay after the STOP condition.\\ - * Measurement unit: i2c_sclk \\ + * Configures the delay after the STOP condition. + * Measurement unit: i2c_sclk */ #define I2C_SCL_STOP_HOLD_TIME 0x000001FFU #define I2C_SCL_STOP_HOLD_TIME_M (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S) @@ -1100,7 +1100,7 @@ extern "C" { * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL * input has smaller width than this register value, the I2C controller will ignore * that pulse. - * Measurement unit: i2c_sclk \\ + * Measurement unit: i2c_sclk */ #define I2C_SCL_FILTER_THRES 0x0000000FU #define I2C_SCL_FILTER_THRES_M (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S) @@ -1110,97 +1110,57 @@ extern "C" { * Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA * input has smaller width than this register value, the I2C controller will ignore * that pulse. - * Measurement unit: i2c_sclk \\ + * Measurement unit: i2c_sclk */ #define I2C_SDA_FILTER_THRES 0x0000000FU #define I2C_SDA_FILTER_THRES_M (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S) #define I2C_SDA_FILTER_THRES_V 0x0000000FU #define I2C_SDA_FILTER_THRES_S 4 /** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; - * Configures to enable the filter function for SCL. \\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable the filter function for SCL. + * 0: No effect + * 1: Enable */ #define I2C_SCL_FILTER_EN (BIT(8)) #define I2C_SCL_FILTER_EN_M (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S) #define I2C_SCL_FILTER_EN_V 0x00000001U #define I2C_SCL_FILTER_EN_S 8 /** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; - * Configures to enable the filter function for SDA. \\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable the filter function for SDA. + * 0: No effect + * 1: Enable */ #define I2C_SDA_FILTER_EN (BIT(9)) #define I2C_SDA_FILTER_EN_M (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S) #define I2C_SDA_FILTER_EN_V 0x00000001U #define I2C_SDA_FILTER_EN_S 9 -/** I2C_CLK_CONF_REG register - * I2C CLK configuration register - */ -#define I2C_CLK_CONF_REG (DR_REG_I2C_BASE + 0x54) -/** I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * the integral part of the fractional divisor for i2c module - */ -#define I2C_SCLK_DIV_NUM 0x000000FFU -#define I2C_SCLK_DIV_NUM_M (I2C_SCLK_DIV_NUM_V << I2C_SCLK_DIV_NUM_S) -#define I2C_SCLK_DIV_NUM_V 0x000000FFU -#define I2C_SCLK_DIV_NUM_S 0 -/** I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; - * the numerator of the fractional part of the fractional divisor for i2c module - */ -#define I2C_SCLK_DIV_A 0x0000003FU -#define I2C_SCLK_DIV_A_M (I2C_SCLK_DIV_A_V << I2C_SCLK_DIV_A_S) -#define I2C_SCLK_DIV_A_V 0x0000003FU -#define I2C_SCLK_DIV_A_S 8 -/** I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; - * the denominator of the fractional part of the fractional divisor for i2c module - */ -#define I2C_SCLK_DIV_B 0x0000003FU -#define I2C_SCLK_DIV_B_M (I2C_SCLK_DIV_B_V << I2C_SCLK_DIV_B_S) -#define I2C_SCLK_DIV_B_V 0x0000003FU -#define I2C_SCLK_DIV_B_S 14 -/** I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; - * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. - */ -#define I2C_SCLK_SEL (BIT(20)) -#define I2C_SCLK_SEL_M (I2C_SCLK_SEL_V << I2C_SCLK_SEL_S) -#define I2C_SCLK_SEL_V 0x00000001U -#define I2C_SCLK_SEL_S 20 -/** I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; - * The clock switch for i2c module - */ -#define I2C_SCLK_ACTIVE (BIT(21)) -#define I2C_SCLK_ACTIVE_M (I2C_SCLK_ACTIVE_V << I2C_SCLK_ACTIVE_S) -#define I2C_SCLK_ACTIVE_V 0x00000001U -#define I2C_SCLK_ACTIVE_S 21 - /** I2C_COMD0_REG register * I2C command register 0 */ #define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58) /** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; - * Configures command 0. \\ - * It consists of three parts:\\ - * op_code is the command\\ - * 1: WRITE\\ - * 2: STOP\\ - * 3: READ\\ - * 4: END\\ - * 6: RSTART\\ - * Byte_num represents the number of bytes that need to be sent or received.\\ + * Configures command 0. + * It consists of three parts: + * op_code is the command + * 1: WRITE + * 2: STOP + * 3: READ + * 4: END + * 6: RSTART + * Byte_num represents the number of bytes that need to be sent or received. * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd - * structure link for more information. - * \\\tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}" + * structure for more information. + * \tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}" */ #define I2C_COMMAND0 0x00003FFFU #define I2C_COMMAND0_M (I2C_COMMAND0_V << I2C_COMMAND0_S) #define I2C_COMMAND0_V 0x00003FFFU #define I2C_COMMAND0_S 0 /** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 0 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether command 0 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND0_DONE (BIT(31)) #define I2C_COMMAND0_DONE_M (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S) @@ -1212,7 +1172,7 @@ extern "C" { */ #define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c) /** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; - * Configures command 1.\\ + * Configures command 1. * See details in I2C_CMD0_REG[13:0]. */ #define I2C_COMMAND1 0x00003FFFU @@ -1220,9 +1180,9 @@ extern "C" { #define I2C_COMMAND1_V 0x00003FFFU #define I2C_COMMAND1_S 0 /** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 1 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether command 1 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND1_DONE (BIT(31)) #define I2C_COMMAND1_DONE_M (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S) @@ -1241,9 +1201,9 @@ extern "C" { #define I2C_COMMAND2_V 0x00003FFFU #define I2C_COMMAND2_S 0 /** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 2 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether command 2 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND2_DONE (BIT(31)) #define I2C_COMMAND2_DONE_M (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S) @@ -1262,9 +1222,9 @@ extern "C" { #define I2C_COMMAND3_V 0x00003FFFU #define I2C_COMMAND3_S 0 /** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 3 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether command 3 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND3_DONE (BIT(31)) #define I2C_COMMAND3_DONE_M (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S) @@ -1283,9 +1243,9 @@ extern "C" { #define I2C_COMMAND4_V 0x00003FFFU #define I2C_COMMAND4_S 0 /** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 4 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether command 4 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND4_DONE (BIT(31)) #define I2C_COMMAND4_DONE_M (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S) @@ -1304,9 +1264,9 @@ extern "C" { #define I2C_COMMAND5_V 0x00003FFFU #define I2C_COMMAND5_S 0 /** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 5 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether command 5 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND5_DONE (BIT(31)) #define I2C_COMMAND5_DONE_M (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S) @@ -1325,9 +1285,9 @@ extern "C" { #define I2C_COMMAND6_V 0x00003FFFU #define I2C_COMMAND6_S 0 /** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 6 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether command 6 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND6_DONE (BIT(31)) #define I2C_COMMAND6_DONE_M (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S) @@ -1346,9 +1306,9 @@ extern "C" { #define I2C_COMMAND7_V 0x00003FFFU #define I2C_COMMAND7_S 0 /** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 7 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether command 7 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND7_DONE (BIT(31)) #define I2C_COMMAND7_DONE_M (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S) @@ -1361,8 +1321,8 @@ extern "C" { #define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78) /** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; * Configures the threshold value of SCL_FSM state unchanged period. It should be no - * more than 23.\\ - * Measurement unit: i2c_sclk \\ + * more than 23. + * Measurement unit: i2c_sclk */ #define I2C_SCL_ST_TO_I2C 0x0000001FU #define I2C_SCL_ST_TO_I2C_M (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S) @@ -1375,8 +1335,8 @@ extern "C" { #define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c) /** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; * Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be - * no more than 23.\\ - * Measurement unit: i2c_sclk \\ + * no more than 23. + * Measurement unit: i2c_sclk */ #define I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU #define I2C_SCL_MAIN_ST_TO_I2C_M (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S) @@ -1396,18 +1356,18 @@ extern "C" { #define I2C_SCL_RST_SLV_EN_V 0x00000001U #define I2C_SCL_RST_SLV_EN_S 0 /** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; - * Configure the pulses of SCL generated in I2C master mode. \\ - * Valid when I2C_SCL_RST_SLV_EN is 1.\\ - * Measurement unit: i2c_sclk \\ + * Configure the pulses of SCL generated in I2C master mode. + * Valid when I2C_SCL_RST_SLV_EN is 1. + * Measurement unit: i2c_sclk */ #define I2C_SCL_RST_SLV_NUM 0x0000001FU #define I2C_SCL_RST_SLV_NUM_M (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S) #define I2C_SCL_RST_SLV_NUM_V 0x0000001FU #define I2C_SCL_RST_SLV_NUM_S 1 /** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; - * Configures to power down the I2C output SCL line. \\ - * 0: Not power down.\\ - * 1: Not work and power down.\\ + * Configures to power down the I2C output SCL line. + * 0: Not power down. + * 1: Not work and power down. * Valid only when I2C_SCL_FORCE_OUT is 1. */ #define I2C_SCL_PD_EN (BIT(6)) @@ -1415,9 +1375,9 @@ extern "C" { #define I2C_SCL_PD_EN_V 0x00000001U #define I2C_SCL_PD_EN_S 6 /** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; - * Configures to power down the I2C output SDA line. \\ - * 0: Not power down.\\ - * 1: Not work and power down.\\ + * Configures to power down the I2C output SDA line. + * 0: Not power down. + * 1: Not work and power down. * Valid only when I2C_SDA_FORCE_OUT is 1. */ #define I2C_SDA_PD_EN (BIT(7)) @@ -1431,8 +1391,8 @@ extern "C" { #define I2C_SCL_STRETCH_CONF_REG (DR_REG_I2C_BASE + 0x84) /** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0; * Configures the time period to release the SCL line from stretching to avoid timing - * violation. Usually it should be larger than the SDA setup time.\\ - * Measurement unit: i2c_sclk \\ + * violation. Usually it should be larger than the SDA setup time. + * Measurement unit: i2c_sclk */ #define I2C_STRETCH_PROTECT_NUM 0x000003FFU #define I2C_STRETCH_PROTECT_NUM_M (I2C_STRETCH_PROTECT_NUM_V << I2C_STRETCH_PROTECT_NUM_S) @@ -1441,36 +1401,36 @@ extern "C" { /** I2C_SLAVE_SCL_STRETCH_EN : R/W; bitpos: [10]; default: 0; * Configures to enable slave SCL stretch function. The SCL output line will be * stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The - * stretch cause can be seen in I2C_STRETCH_CAUSE.\\ - * 0: Disable \\ - * 1: Enable \\ + * stretch cause can be seen in I2C_STRETCH_CAUSE. + * 0: Disable + * 1: Enable */ #define I2C_SLAVE_SCL_STRETCH_EN (BIT(10)) #define I2C_SLAVE_SCL_STRETCH_EN_M (I2C_SLAVE_SCL_STRETCH_EN_V << I2C_SLAVE_SCL_STRETCH_EN_S) #define I2C_SLAVE_SCL_STRETCH_EN_V 0x00000001U #define I2C_SLAVE_SCL_STRETCH_EN_S 10 /** I2C_SLAVE_SCL_STRETCH_CLR : WT; bitpos: [11]; default: 0; - * Configures to clear the I2C slave SCL stretch function.\\ - * 0: No effect \\ - * 1: Clear\\ + * Configures to clear the I2C slave SCL stretch function. + * 0: No effect + * 1: Clear */ #define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11)) #define I2C_SLAVE_SCL_STRETCH_CLR_M (I2C_SLAVE_SCL_STRETCH_CLR_V << I2C_SLAVE_SCL_STRETCH_CLR_S) #define I2C_SLAVE_SCL_STRETCH_CLR_V 0x00000001U #define I2C_SLAVE_SCL_STRETCH_CLR_S 11 /** I2C_SLAVE_BYTE_ACK_CTL_EN : R/W; bitpos: [12]; default: 0; - * Configures to enable the function for slave to control ACK level.\\ - * 0: Disable \\ - * 1: Enable \\ + * Configures to enable the function for slave to control ACK level. + * 0: Disable + * 1: Enable */ #define I2C_SLAVE_BYTE_ACK_CTL_EN (BIT(12)) #define I2C_SLAVE_BYTE_ACK_CTL_EN_M (I2C_SLAVE_BYTE_ACK_CTL_EN_V << I2C_SLAVE_BYTE_ACK_CTL_EN_S) #define I2C_SLAVE_BYTE_ACK_CTL_EN_V 0x00000001U #define I2C_SLAVE_BYTE_ACK_CTL_EN_S 12 /** I2C_SLAVE_BYTE_ACK_LVL : R/W; bitpos: [13]; default: 0; - * Set the ACK level when slave controlling ACK level function enables.\\ - * 0: Low level\\ - * 1: High level \\ + * Set the ACK level when slave controlling ACK level function enables. + * 0: Low level + * 1: High level */ #define I2C_SLAVE_BYTE_ACK_LVL (BIT(13)) #define I2C_SLAVE_BYTE_ACK_LVL_M (I2C_SLAVE_BYTE_ACK_LVL_V << I2C_SLAVE_BYTE_ACK_LVL_S) @@ -1481,7 +1441,7 @@ extern "C" { * Version register */ #define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8) -/** I2C_DATE : R/W; bitpos: [31:0]; default: 37752896; +/** I2C_DATE : R/W; bitpos: [31:0]; default: 37765248; * Version control register. */ #define I2C_DATE 0xFFFFFFFFU diff --git a/components/soc/esp32c61/register/soc/i2c_struct.h b/components/soc/esp32c61/register/soc/i2c_struct.h index 4cb22ab31c..73534f36d9 100644 --- a/components/soc/esp32c61/register/soc/i2c_struct.h +++ b/components/soc/esp32c61/register/soc/i2c_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -18,8 +18,8 @@ extern "C" { typedef union { struct { /** scl_low_period : R/W; bitpos: [8:0]; default: 0; - * Configures the low level width of the SCL Clock in master mode. \\ - * Measurement unit: i2c_sclk \\ + * Configures the low level width of the SCL Clock in master mode. + * Measurement unit: i2c_sclk */ uint32_t scl_low_period:9; uint32_t reserved_9:23; @@ -33,8 +33,8 @@ typedef union { typedef union { struct { /** sda_hold_time : R/W; bitpos: [8:0]; default: 0; - * Configures the time to hold the data after the falling edge of SCL.\\ - * Measurement unit: i2c_sclk \\ + * Configures the time to hold the data after the falling edge of SCL. + * Measurement unit: i2c_sclk */ uint32_t sda_hold_time:9; uint32_t reserved_9:23; @@ -48,8 +48,8 @@ typedef union { typedef union { struct { /** sda_sample_time : R/W; bitpos: [8:0]; default: 0; - * Configures the time for sampling SDA.\\ - * Measurement unit: i2c_sclk \\ + * Configures the time for sampling SDA. + * Measurement unit: i2c_sclk */ uint32_t sda_sample_time:9; uint32_t reserved_9:23; @@ -63,13 +63,13 @@ typedef union { typedef union { struct { /** scl_high_period : R/W; bitpos: [8:0]; default: 0; - * Configures for how long SCL remains high in master mode.\\ - * Measurement unit: i2c_sclk \\ + * Configures for how long SCL remains high in master mode. + * Measurement unit: i2c_sclk */ uint32_t scl_high_period:9; /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0; - * Configures the SCL_FSM's waiting period for SCL high level in master mode.\\ - * Measurement unit: i2c_sclk \\ + * Configures the SCL_FSM's waiting period for SCL high level in master mode. + * Measurement unit: i2c_sclk */ uint32_t scl_wait_high_period:7; uint32_t reserved_16:16; @@ -84,8 +84,8 @@ typedef union { struct { /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8; * Configures the time between the falling edge of SDA and the falling edge of SCL for - * a START condition.\\ - * Measurement unit: i2c_sclk \\ + * a START condition. + * Measurement unit: i2c_sclk */ uint32_t scl_start_hold_time:9; uint32_t reserved_9:23; @@ -101,8 +101,8 @@ typedef union { struct { /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8; * Configures the time between the positive edge of SCL and the negative edge of SDA - * for a RESTART condition.\\ - * Measurement unit: i2c_sclk \\ + * for a RESTART condition. + * Measurement unit: i2c_sclk */ uint32_t scl_rstart_setup_time:9; uint32_t reserved_9:23; @@ -117,8 +117,8 @@ typedef union { typedef union { struct { /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8; - * Configures the delay after the STOP condition.\\ - * Measurement unit: i2c_sclk \\ + * Configures the delay after the STOP condition. + * Measurement unit: i2c_sclk */ uint32_t scl_stop_hold_time:9; uint32_t reserved_9:23; @@ -149,8 +149,8 @@ typedef union { struct { /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16; * Configures the threshold value of SCL_FSM state unchanged period. It should be no - * more than 23.\\ - * Measurement unit: i2c_sclk \\ + * more than 23. + * Measurement unit: i2c_sclk */ uint32_t scl_st_to_i2c:5; uint32_t reserved_5:27; @@ -165,8 +165,8 @@ typedef union { struct { /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16; * Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be - * no more than 23.\\ - * Measurement unit: i2c_sclk \\ + * no more than 23. + * Measurement unit: i2c_sclk */ uint32_t scl_main_st_to_i2c:5; uint32_t reserved_5:27; @@ -182,92 +182,92 @@ typedef union { typedef union { struct { /** sda_force_out : R/W; bitpos: [0]; default: 0; - * Configures the SDA output mode.\\ - * 0: Open drain output \\ - * 1: Direct output \\ + * Configures the SDA output mode. + * 0: Open drain output + * 1: Direct output */ uint32_t sda_force_out:1; /** scl_force_out : R/W; bitpos: [1]; default: 0; - * Configures the SCL output mode.\\ - * 0: Open drain output \\ - * 1: Direct output \\ + * Configures the SCL output mode. + * 0: Open drain output + * 1: Direct output */ uint32_t scl_force_out:1; /** sample_scl_level : R/W; bitpos: [2]; default: 0; - * Configures the sample mode for SDA.\\ - * 0: Sample SDA data on the SCL high level \\ - * 1: Sample SDA data on the SCL low level \\ + * Configures the sample mode for SDA. + * 0: Sample SDA data on the SCL high level + * 1: Sample SDA data on the SCL low level */ uint32_t sample_scl_level:1; /** rx_full_ack_level : R/W; bitpos: [3]; default: 1; * Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has - * reached the threshold.\\ + * reached the threshold. */ uint32_t rx_full_ack_level:1; /** ms_mode : R/W; bitpos: [4]; default: 0; - * Configures the module as an I2C Master or Slave.\\ - * 0: Slave \\ - * 1: Master \\ + * Configures the module as an I2C Master or Slave. + * 0: Slave + * 1: Master */ uint32_t ms_mode:1; /** trans_start : WT; bitpos: [5]; default: 0; - * Configures whether the slave starts sending the data in txfifo.\\ - * 0: No effect \\ + * Configures whether the slave starts sending the data in txfifo. + * 0: No effect * 1: Start */ uint32_t trans_start:1; /** tx_lsb_first : R/W; bitpos: [6]; default: 0; - * Configures to control the sending order for data needing to be sent.\\ - * 0: send data from the most significant bit \\ - * 1: send data from the least significant bit \\ + * Configures to control the sending order for data needing to be sent. + * 0: send data from the most significant bit + * 1: send data from the least significant bit */ uint32_t tx_lsb_first:1; /** rx_lsb_first : R/W; bitpos: [7]; default: 0; - * Configures to control the storage order for received data.\\ - * 0: receive data from the most significant bit \\ - * 1: receive data from the least significant bit \\ + * Configures to control the storage order for received data. + * 0: receive data from the most significant bit + * 1: receive data from the least significant bit */ uint32_t rx_lsb_first:1; /** clk_en : R/W; bitpos: [8]; default: 0; - * Configures whether to gate clock signal for registers.\\ - * 0: Support clock only when registers are read or written to by software \\ - * 1: Force clock on for registers \\ + * Configures whether to gate clock signal for registers. + * 0: Support clock only when registers are read or written to by software + * 1: Force clock on for registers */ uint32_t clk_en:1; /** arbitration_en : R/W; bitpos: [9]; default: 1; - * Configures to enable I2C bus arbitration detection.\\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable I2C bus arbitration detection. + * 0: No effect + * 1: Enable */ uint32_t arbitration_en:1; /** fsm_rst : WT; bitpos: [10]; default: 0; - * Configures to reset the SCL_FSM.\\ - * 0: No effect \\ + * Configures to reset the SCL_FSM. + * 0: No effect * 1: Reset */ uint32_t fsm_rst:1; /** conf_upgate : WT; bitpos: [11]; default: 0; - * Configures this bit for synchronization.\\ - * 0: No effect \\ + * Configures this bit for synchronization. + * 0: No effect * 1: Synchronize */ uint32_t conf_upgate:1; /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0; - * Configures to enable slave to send data automatically\\ - * 0: Disable\\ - * 1: Enable \\ + * Configures to enable slave to send data automatically + * 0: Disable + * 1: Enable */ uint32_t slv_tx_auto_start_en:1; /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0; - * Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.\\ - * 0: Not check\\ + * Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. + * 0: Not check * 1: Check */ uint32_t addr_10bit_rw_check_en:1; /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0; - * Configures to support the 7 bit general call function.\\ - * 0: Not support \\ - * 1: Support \\ + * Configures to support the 7 bit general call function. + * 0: Not support + * 1: Support */ uint32_t addr_broadcasting_en:1; uint32_t reserved_15:17; @@ -282,14 +282,14 @@ typedef union { struct { /** time_out_value : R/W; bitpos: [4:0]; default: 16; * Configures the timeout threshold period for SCL stucking at high or low level. The - * actual period is 2\^{}(reg_time_out_value).\\ - * Measurement unit: i2c_sclk \\ + * actual period is 2\^{}(reg_time_out_value). + * Measurement unit: i2c_sclk */ uint32_t time_out_value:5; /** time_out_en : R/W; bitpos: [5]; default: 0; - * Configures to enable time out control.\\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable time out control. + * 0: No effect + * 1: Enable */ uint32_t time_out_en:1; uint32_t reserved_6:26; @@ -303,14 +303,14 @@ typedef union { typedef union { struct { /** slave_addr : R/W; bitpos: [14:0]; default: 0; - * Configure the slave address of I2C Slave.\\ + * Configure the slave address of I2C Slave. */ uint32_t slave_addr:15; uint32_t reserved_15:16; /** addr_10bit_en : R/W; bitpos: [31]; default: 0; - * Configures to enable the slave 10-bit addressing mode in master mode.\\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable the slave 10-bit addressing mode in master mode. + * 0: No effect + * 1: Enable */ uint32_t addr_10bit_en:1; }; @@ -343,28 +343,28 @@ typedef union { /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0; * Configures the slave to enable dual address mode. When this mode is enabled, the * byte received after the I2C address byte represents the offset address in the I2C - * Slave RAM. \\ - * 0: Disable\\ - * 1: Enable \\ + * Slave RAM. + * 0: Disable + * 1: Enable */ uint32_t fifo_addr_cfg_en:1; /** rx_fifo_rst : R/W; bitpos: [12]; default: 0; - * Configures to reset RXFIFO.\\ - * 0: No effect \\ + * Configures to reset RXFIFO. + * 0: No effect * 1: Reset */ uint32_t rx_fifo_rst:1; /** tx_fifo_rst : R/W; bitpos: [13]; default: 0; - * Configures to reset TXFIFO.\\ - * 0: No effect \\ + * Configures to reset TXFIFO. + * 0: No effect * 1: Reset */ uint32_t tx_fifo_rst:1; /** fifo_prt_en : R/W; bitpos: [14]; default: 1; * Configures to enable FIFO pointer in non-fifo access mode. This bit controls the - * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.\\ - * 0: No effect \\ - * 1: Enable \\ + * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. + * 0: No effect + * 1: Enable */ uint32_t fifo_prt_en:1; uint32_t reserved_15:17; @@ -381,26 +381,26 @@ typedef union { * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL * input has smaller width than this register value, the I2C controller will ignore * that pulse. - * Measurement unit: i2c_sclk \\ + * Measurement unit: i2c_sclk */ uint32_t scl_filter_thres:4; /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0; * Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA * input has smaller width than this register value, the I2C controller will ignore * that pulse. - * Measurement unit: i2c_sclk \\ + * Measurement unit: i2c_sclk */ uint32_t sda_filter_thres:4; /** scl_filter_en : R/W; bitpos: [8]; default: 1; - * Configures to enable the filter function for SCL. \\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable the filter function for SCL. + * 0: No effect + * 1: Enable */ uint32_t scl_filter_en:1; /** sda_filter_en : R/W; bitpos: [9]; default: 1; - * Configures to enable the filter function for SDA. \\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable the filter function for SDA. + * 0: No effect + * 1: Enable */ uint32_t sda_filter_en:1; uint32_t reserved_10:22; @@ -408,36 +408,6 @@ typedef union { uint32_t val; } i2c_filter_cfg_reg_t; -/** Type of clk_conf register - * I2C CLK configuration register - */ -typedef union { - struct { - /** sclk_div_num : R/W; bitpos: [7:0]; default: 0; - * the integral part of the fractional divisor for i2c module - */ - uint32_t sclk_div_num:8; - /** sclk_div_a : R/W; bitpos: [13:8]; default: 0; - * the numerator of the fractional part of the fractional divisor for i2c module - */ - uint32_t sclk_div_a:6; - /** sclk_div_b : R/W; bitpos: [19:14]; default: 0; - * the denominator of the fractional part of the fractional divisor for i2c module - */ - uint32_t sclk_div_b:6; - /** sclk_sel : R/W; bitpos: [20]; default: 0; - * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. - */ - uint32_t sclk_sel:1; - /** sclk_active : R/W; bitpos: [21]; default: 1; - * The clock switch for i2c module - */ - uint32_t sclk_active:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} i2c_clk_conf_reg_t; - /** Type of scl_sp_conf register * Power configuration register */ @@ -449,22 +419,22 @@ typedef union { */ uint32_t scl_rst_slv_en:1; /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0; - * Configure the pulses of SCL generated in I2C master mode. \\ - * Valid when I2C_SCL_RST_SLV_EN is 1.\\ - * Measurement unit: i2c_sclk \\ + * Configure the pulses of SCL generated in I2C master mode. + * Valid when I2C_SCL_RST_SLV_EN is 1. + * Measurement unit: i2c_sclk */ uint32_t scl_rst_slv_num:5; /** scl_pd_en : R/W; bitpos: [6]; default: 0; - * Configures to power down the I2C output SCL line. \\ - * 0: Not power down.\\ - * 1: Not work and power down.\\ + * Configures to power down the I2C output SCL line. + * 0: Not power down. + * 1: Not work and power down. * Valid only when I2C_SCL_FORCE_OUT is 1. */ uint32_t scl_pd_en:1; /** sda_pd_en : R/W; bitpos: [7]; default: 0; - * Configures to power down the I2C output SDA line. \\ - * 0: Not power down.\\ - * 1: Not work and power down.\\ + * Configures to power down the I2C output SDA line. + * 0: Not power down. + * 1: Not work and power down. * Valid only when I2C_SDA_FORCE_OUT is 1. */ uint32_t sda_pd_en:1; @@ -480,34 +450,34 @@ typedef union { struct { /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0; * Configures the time period to release the SCL line from stretching to avoid timing - * violation. Usually it should be larger than the SDA setup time.\\ - * Measurement unit: i2c_sclk \\ + * violation. Usually it should be larger than the SDA setup time. + * Measurement unit: i2c_sclk */ uint32_t stretch_protect_num:10; /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0; * Configures to enable slave SCL stretch function. The SCL output line will be * stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The - * stretch cause can be seen in I2C_STRETCH_CAUSE.\\ - * 0: Disable \\ - * 1: Enable \\ + * stretch cause can be seen in I2C_STRETCH_CAUSE. + * 0: Disable + * 1: Enable */ uint32_t slave_scl_stretch_en:1; /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0; - * Configures to clear the I2C slave SCL stretch function.\\ - * 0: No effect \\ - * 1: Clear\\ + * Configures to clear the I2C slave SCL stretch function. + * 0: No effect + * 1: Clear */ uint32_t slave_scl_stretch_clr:1; /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0; - * Configures to enable the function for slave to control ACK level.\\ - * 0: Disable \\ - * 1: Enable \\ + * Configures to enable the function for slave to control ACK level. + * 0: Disable + * 1: Enable */ uint32_t slave_byte_ack_ctl_en:1; /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0; - * Set the ACK level when slave controlling ACK level function enables.\\ - * 0: Low level\\ - * 1: High level \\ + * Set the ACK level when slave controlling ACK level function enables. + * 0: Low level + * 1: High level */ uint32_t slave_byte_ack_lvl:1; uint32_t reserved_14:18; @@ -523,36 +493,36 @@ typedef union { typedef union { struct { /** resp_rec : RO; bitpos: [0]; default: 0; - * Represents the received ACK value in master mode or slave mode.\\ - * 0: ACK\\ + * Represents the received ACK value in master mode or slave mode. + * 0: ACK * 1: NACK. */ uint32_t resp_rec:1; /** slave_rw : RO; bitpos: [1]; default: 0; - * Represents the transfer direction in slave mode.\\ - * 1: Master reads from slave\\ + * Represents the transfer direction in slave mode. + * 1: Master reads from slave * 0: Master writes to slave. */ uint32_t slave_rw:1; uint32_t reserved_2:1; /** arb_lost : RO; bitpos: [3]; default: 0; - * Represents whether the I2C controller loses control of SCL line.\\ - * 0: No arbitration lost\\ - * 1: Arbitration lost\\ + * Represents whether the I2C controller loses control of SCL line. + * 0: No arbitration lost + * 1: Arbitration lost */ uint32_t arb_lost:1; /** bus_busy : RO; bitpos: [4]; default: 0; - * Represents the I2C bus state.\\ - * 1: The I2C bus is busy transferring data\\ - * 0: The I2C bus is in idle state.\\ + * Represents the I2C bus state. + * 1: The I2C bus is busy transferring data + * 0: The I2C bus is in idle state. */ uint32_t bus_busy:1; /** slave_addressed : RO; bitpos: [5]; default: 0; * Represents whether the address sent by the master is equal to the address of the - * slave.\\ - * Valid only when the module is configured as an I2C Slave.\\ - * 0: Not equal\\ - * 1: Equal\\ + * slave. + * Valid only when the module is configured as an I2C Slave. + * 0: Not equal + * 1: Equal */ uint32_t slave_addressed:1; uint32_t reserved_6:2; @@ -561,9 +531,9 @@ typedef union { */ uint32_t rxfifo_cnt:6; /** stretch_cause : RO; bitpos: [15:14]; default: 3; - * Represents the cause of SCL clocking stretching in slave mode.\\ - * 0: Stretching SCL low when the master starts to read data.\\ - * 1: Stretching SCL low when I2C TX FIFO is empty in slave mode.\\ + * Represents the cause of SCL clocking stretching in slave mode. + * 0: Stretching SCL low when the master starts to read data. + * 1: Stretching SCL low when I2C TX FIFO is empty in slave mode. * 2: Stretching SCL low when I2C RX FIFO is full in slave mode. */ uint32_t stretch_cause:2; @@ -573,25 +543,25 @@ typedef union { */ uint32_t txfifo_cnt:6; /** scl_main_state_last : RO; bitpos: [26:24]; default: 0; - * Represents the states of the I2C module state machine.\\ - * 0: Idle\\ - * 1: Address shift\\ - * 2: ACK address\\ - * 3: Rx data\\ - * 4: Tx data\\ - * 5: Send ACK\\ + * Represents the states of the I2C module state machine. + * 0: Idle + * 1: Address shift + * 2: ACK address + * 3: Rx data + * 4: Tx data + * 5: Send ACK * 6: Wait ACK */ uint32_t scl_main_state_last:3; uint32_t reserved_27:1; /** scl_state_last : RO; bitpos: [30:28]; default: 0; - * Represents the states of the state machine used to produce SCL.\\ - * 0: Idle\\ - * 1: Start\\ - * 2: Negative edge\\ - * 3: Low\\ - * 4: Positive edge\\ - * 5: High\\ + * Represents the states of the state machine used to produce SCL. + * 0: Idle + * 1: Start + * 2: Negative edge + * 3: Low + * 4: Positive edge + * 5: High * 6: Stop */ uint32_t scl_state_last:3; @@ -1000,38 +970,39 @@ typedef union { typedef union { struct { /** command : R/W; bitpos: [13:0]; default: 0; - * Configures command 0. \\ - * It consists of three parts:\\ - * op_code is the command\\ - * 1: WRITE\\ - * 2: STOP\\ - * 3: READ\\ - * 4: END\\ - * 6: RSTART\\ - * Byte_num represents the number of bytes that need to be sent or received.\\ + * Configures command 0. + * It consists of three parts: + * op_code is the command + * 1: WRITE + * 2: STOP + * 3: READ + * 4: END + * 6: RSTART + * Byte_num represents the number of bytes that need to be sent or received. * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd - * structure link for more information. - * \\\tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}" + * structure for more information. + * \tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}" */ uint32_t command:14; uint32_t reserved_14:17; - /** command0_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 0 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ + /** command_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 0 is done in I2C Master mode. + * 0: Not done + * 1: Done */ uint32_t command_done:1; }; uint32_t val; } i2c_comd_reg_t; + /** Group: Version register */ /** Type of date register * Version register */ typedef union { struct { - /** date : R/W; bitpos: [31:0]; default: 37752896; + /** date : R/W; bitpos: [31:0]; default: 37765248; * Version control register. */ uint32_t date:32; @@ -1040,6 +1011,34 @@ typedef union { } i2c_date_reg_t; +/** Group: Address register */ +/** Type of txfifo_start_addr register + * I2C TXFIFO base address register + */ +typedef union { + struct { + /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C txfifo first address. + */ + uint32_t txfifo_start_addr:32; + }; + uint32_t val; +} i2c_txfifo_start_addr_reg_t; + +/** Type of rxfifo_start_addr register + * I2C RXFIFO base address register + */ +typedef union { + struct { + /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C rxfifo first address. + */ + uint32_t rxfifo_start_addr:32; + }; + uint32_t val; +} i2c_rxfifo_start_addr_reg_t; + + typedef struct { volatile i2c_scl_low_period_reg_t scl_low_period; volatile i2c_ctr_reg_t ctr; @@ -1062,7 +1061,7 @@ typedef struct { volatile i2c_scl_stop_hold_reg_t scl_stop_hold; volatile i2c_scl_stop_setup_reg_t scl_stop_setup; volatile i2c_filter_cfg_reg_t filter_cfg; - volatile i2c_clk_conf_reg_t clk_conf; + uint32_t reserved_054; volatile i2c_comd_reg_t command[8]; volatile i2c_scl_st_time_out_reg_t scl_st_time_out; volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out; diff --git a/components/soc/esp32c61/register/soc/interrupt_matrix_reg.h b/components/soc/esp32c61/register/soc/interrupt_matrix_reg.h index f76f3e6593..ad4026911d 100644 --- a/components/soc/esp32c61/register/soc/interrupt_matrix_reg.h +++ b/components/soc/esp32c61/register/soc/interrupt_matrix_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,7 +14,7 @@ extern "C" { /** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG register * WIFI_MAC_INTR mapping register */ -#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0) +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x0) /** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -22,11 +22,18 @@ extern "C" { #define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_M (INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V << INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S) #define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG register * WIFI_MAC_NMI mapping register */ -#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4) +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTMTX_BASE + 0x4) /** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -34,11 +41,18 @@ extern "C" { #define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_M (INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V << INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S) #define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V 0x0000003FU #define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S 0 +/** INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_M (INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG register * WIFI_PWR_INTR mapping register */ -#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8) +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x8) /** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -46,11 +60,18 @@ extern "C" { #define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_M (INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V << INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S) #define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S 0 +/** INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG register * WIFI_BB_INTR mapping register */ -#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc) +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc) /** INTERRUPT_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -58,11 +79,18 @@ extern "C" { #define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_M (INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V << INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S) #define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S 0 +/** INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG register * BT_MAC_INTR mapping register */ -#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10) +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x10) /** INTERRUPT_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -70,11 +98,18 @@ extern "C" { #define INTERRUPT_CORE0_BT_MAC_INTR_MAP_M (INTERRUPT_CORE0_BT_MAC_INTR_MAP_V << INTERRUPT_CORE0_BT_MAC_INTR_MAP_S) #define INTERRUPT_CORE0_BT_MAC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_BT_MAC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_BT_BB_INTR_MAP_REG register * BT_BB_INTR mapping register */ -#define INTERRUPT_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14) +#define INTERRUPT_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x14) /** INTERRUPT_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -82,11 +117,18 @@ extern "C" { #define INTERRUPT_CORE0_BT_BB_INTR_MAP_M (INTERRUPT_CORE0_BT_BB_INTR_MAP_V << INTERRUPT_CORE0_BT_BB_INTR_MAP_S) #define INTERRUPT_CORE0_BT_BB_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_BT_BB_INTR_MAP_S 0 +/** INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_BT_BB_NMI_MAP_REG register * BT_BB_NMI mapping register */ -#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18) +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTMTX_BASE + 0x18) /** INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -94,11 +136,18 @@ extern "C" { #define INTERRUPT_CORE0_BT_BB_NMI_MAP_M (INTERRUPT_CORE0_BT_BB_NMI_MAP_V << INTERRUPT_CORE0_BT_BB_NMI_MAP_S) #define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x0000003FU #define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0 +/** INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_M (INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_V << INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG register * LP_TIMER_INTR mapping register */ -#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c) +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x1c) /** INTERRUPT_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -106,11 +155,18 @@ extern "C" { #define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_M (INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S) #define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_COEX_INTR_MAP_REG register * COEX_INTR mapping register */ -#define INTERRUPT_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20) +#define INTERRUPT_CORE0_COEX_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x20) /** INTERRUPT_CORE0_COEX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -118,11 +174,18 @@ extern "C" { #define INTERRUPT_CORE0_COEX_INTR_MAP_M (INTERRUPT_CORE0_COEX_INTR_MAP_V << INTERRUPT_CORE0_COEX_INTR_MAP_S) #define INTERRUPT_CORE0_COEX_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_COEX_INTR_MAP_S 0 +/** INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG register * BLE_TIMER_INTR mapping register */ -#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24) +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x24) /** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -130,11 +193,18 @@ extern "C" { #define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_M (INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V << INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S) #define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S 0 +/** INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG register * BLE_SEC_INTR mapping register */ -#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28) +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x28) /** INTERRUPT_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -142,11 +212,18 @@ extern "C" { #define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_M (INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V << INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S) #define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG register * I2C_MST_INTR mapping register */ -#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c) +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x2c) /** INTERRUPT_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -154,11 +231,18 @@ extern "C" { #define INTERRUPT_CORE0_I2C_MST_INTR_MAP_M (INTERRUPT_CORE0_I2C_MST_INTR_MAP_V << INTERRUPT_CORE0_I2C_MST_INTR_MAP_S) #define INTERRUPT_CORE0_I2C_MST_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_I2C_MST_INTR_MAP_S 0 +/** INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG register * ZB_MAC_INTR mapping register */ -#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30) +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x30) /** INTERRUPT_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -166,11 +250,18 @@ extern "C" { #define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_M (INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V << INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S) #define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_PMU_INTR_MAP_REG register * PMU_INTR mapping register */ -#define INTERRUPT_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34) +#define INTERRUPT_CORE0_PMU_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x34) /** INTERRUPT_CORE0_PMU_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -178,11 +269,18 @@ extern "C" { #define INTERRUPT_CORE0_PMU_INTR_MAP_M (INTERRUPT_CORE0_PMU_INTR_MAP_V << INTERRUPT_CORE0_PMU_INTR_MAP_S) #define INTERRUPT_CORE0_PMU_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_PMU_INTR_MAP_S 0 +/** INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_EFUSE_INTR_MAP_REG register * EFUSE_INTR mapping register */ -#define INTERRUPT_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38) +#define INTERRUPT_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x38) /** INTERRUPT_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -190,11 +288,18 @@ extern "C" { #define INTERRUPT_CORE0_EFUSE_INTR_MAP_M (INTERRUPT_CORE0_EFUSE_INTR_MAP_V << INTERRUPT_CORE0_EFUSE_INTR_MAP_S) #define INTERRUPT_CORE0_EFUSE_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_EFUSE_INTR_MAP_S 0 +/** INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG register * LP_RTC_TIMER_INTR mapping register */ -#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3c) +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x3c) /** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -202,11 +307,18 @@ extern "C" { #define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_M (INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S) #define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG register * LP_WDT_INTR mapping register */ -#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40) +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x40) /** INTERRUPT_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -214,11 +326,18 @@ extern "C" { #define INTERRUPT_CORE0_LP_WDT_INTR_MAP_M (INTERRUPT_CORE0_LP_WDT_INTR_MAP_V << INTERRUPT_CORE0_LP_WDT_INTR_MAP_S) #define INTERRUPT_CORE0_LP_WDT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_WDT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register * LP_PERI_TIMEOUT_INTR mapping register */ -#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44) +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x44) /** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -226,11 +345,18 @@ extern "C" { #define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S) #define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG register * LP_APM_M0_INTR mapping register */ -#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48) +#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x48) /** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -238,11 +364,18 @@ extern "C" { #define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S) #define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register * CPU_INTR_FROM_CPU_0 mapping register */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4c) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTMTX_BASE + 0x4c) /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -250,11 +383,18 @@ extern "C" { #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S) #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0 +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register * CPU_INTR_FROM_CPU_1 mapping register */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTMTX_BASE + 0x50) /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -262,11 +402,18 @@ extern "C" { #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S) #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0 +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register * CPU_INTR_FROM_CPU_2 mapping register */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTMTX_BASE + 0x54) /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -274,11 +421,18 @@ extern "C" { #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S) #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0 +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register * CPU_INTR_FROM_CPU_3 mapping register */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTMTX_BASE + 0x58) /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -286,11 +440,18 @@ extern "C" { #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S) #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0 +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG register * ASSIST_DEBUG_INTR mapping register */ -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5c) +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x5c) /** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -298,11 +459,18 @@ extern "C" { #define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M (INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S) #define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0 +/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_ASSIST_DEBUG_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ASSIST_DEBUG_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TRACE_INTR_MAP_REG register * TRACE_INTR mapping register */ -#define INTERRUPT_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60) +#define INTERRUPT_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x60) /** INTERRUPT_CORE0_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -310,11 +478,18 @@ extern "C" { #define INTERRUPT_CORE0_TRACE_INTR_MAP_M (INTERRUPT_CORE0_TRACE_INTR_MAP_V << INTERRUPT_CORE0_TRACE_INTR_MAP_S) #define INTERRUPT_CORE0_TRACE_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TRACE_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_CACHE_INTR_MAP_REG register * CACHE_INTR mapping register */ -#define INTERRUPT_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64) +#define INTERRUPT_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x64) /** INTERRUPT_CORE0_CACHE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -322,11 +497,18 @@ extern "C" { #define INTERRUPT_CORE0_CACHE_INTR_MAP_M (INTERRUPT_CORE0_CACHE_INTR_MAP_V << INTERRUPT_CORE0_CACHE_INTR_MAP_S) #define INTERRUPT_CORE0_CACHE_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CACHE_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register * CPU_PERI_TIMEOUT_INTR mapping register */ -#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68) +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x68) /** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -334,11 +516,18 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S) #define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register * GPIO_INTERRUPT_PRO mapping register */ -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTMTX_BASE + 0x6c) /** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -346,11 +535,18 @@ extern "C" { #define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S) #define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x0000003FU #define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0 +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_REG register * GPIO_INTERRUPT_EXT mapping register */ -#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_REG (DR_REG_INTMTX_BASE + 0x70) /** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -358,11 +554,18 @@ extern "C" { #define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_S) #define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_S 0 +/** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC_M (INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC_V << INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_PAU_INTR_MAP_REG register * PAU_INTR mapping register */ -#define INTERRUPT_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74) +#define INTERRUPT_CORE0_PAU_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x74) /** INTERRUPT_CORE0_PAU_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -370,11 +573,18 @@ extern "C" { #define INTERRUPT_CORE0_PAU_INTR_MAP_M (INTERRUPT_CORE0_PAU_INTR_MAP_V << INTERRUPT_CORE0_PAU_INTR_MAP_S) #define INTERRUPT_CORE0_PAU_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_PAU_INTR_MAP_S 0 +/** INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register * HP_PERI_TIMEOUT_INTR mapping register */ -#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78) +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x78) /** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -382,11 +592,18 @@ extern "C" { #define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S) #define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register * MODEM_PERI_TIMEOUT_INTR mapping register */ -#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7c) +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x7c) /** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -394,11 +611,18 @@ extern "C" { #define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S) #define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG register * HP_APM_M0_INTR mapping register */ -#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80) +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x80) /** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -406,11 +630,18 @@ extern "C" { #define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S) #define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG register * HP_APM_M1_INTR mapping register */ -#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84) +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x84) /** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -418,11 +649,18 @@ extern "C" { #define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S) #define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG register * HP_APM_M2_INTR mapping register */ -#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88) +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x88) /** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -430,11 +668,18 @@ extern "C" { #define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S) #define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG register * HP_APM_M3_INTR mapping register */ -#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c) +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x8c) /** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -442,11 +687,56 @@ extern "C" { #define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S) #define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG register + * CPU_APM_M0_INTR mapping register + */ +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x90) +/** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_S) +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG register + * CPU_APM_M1_INTR mapping register + */ +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x94) +/** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_M (INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_S) +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_MSPI_INTR_MAP_REG register * MSPI_INTR mapping register */ -#define INTERRUPT_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90) +#define INTERRUPT_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x98) /** INTERRUPT_CORE0_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -454,11 +744,18 @@ extern "C" { #define INTERRUPT_CORE0_MSPI_INTR_MAP_M (INTERRUPT_CORE0_MSPI_INTR_MAP_V << INTERRUPT_CORE0_MSPI_INTR_MAP_S) #define INTERRUPT_CORE0_MSPI_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_MSPI_INTR_MAP_S 0 +/** INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_I2S1_INTR_MAP_REG register * I2S1_INTR mapping register */ -#define INTERRUPT_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94) +#define INTERRUPT_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x9c) /** INTERRUPT_CORE0_I2S1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -466,11 +763,18 @@ extern "C" { #define INTERRUPT_CORE0_I2S1_INTR_MAP_M (INTERRUPT_CORE0_I2S1_INTR_MAP_V << INTERRUPT_CORE0_I2S1_INTR_MAP_S) #define INTERRUPT_CORE0_I2S1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_I2S1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_I2S1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_I2S1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_I2S1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_I2S1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_I2S1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_I2S1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_I2S1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_UART0_INTR_MAP_REG register * UART0_INTR mapping register */ -#define INTERRUPT_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98) +#define INTERRUPT_CORE0_UART0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa0) /** INTERRUPT_CORE0_UART0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -478,11 +782,18 @@ extern "C" { #define INTERRUPT_CORE0_UART0_INTR_MAP_M (INTERRUPT_CORE0_UART0_INTR_MAP_V << INTERRUPT_CORE0_UART0_INTR_MAP_S) #define INTERRUPT_CORE0_UART0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_UART0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_UART1_INTR_MAP_REG register * UART1_INTR mapping register */ -#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c) +#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa4) /** INTERRUPT_CORE0_UART1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -490,11 +801,18 @@ extern "C" { #define INTERRUPT_CORE0_UART1_INTR_MAP_M (INTERRUPT_CORE0_UART1_INTR_MAP_V << INTERRUPT_CORE0_UART1_INTR_MAP_S) #define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_UART1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_UART2_INTR_MAP_REG register * UART2_INTR mapping register */ -#define INTERRUPT_CORE0_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0) +#define INTERRUPT_CORE0_UART2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa8) /** INTERRUPT_CORE0_UART2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -502,11 +820,18 @@ extern "C" { #define INTERRUPT_CORE0_UART2_INTR_MAP_M (INTERRUPT_CORE0_UART2_INTR_MAP_V << INTERRUPT_CORE0_UART2_INTR_MAP_S) #define INTERRUPT_CORE0_UART2_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_UART2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_UART2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_UART2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_UART2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_UART2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_UART2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_UART2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_UART2_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LEDC_INTR_MAP_REG register * LEDC_INTR mapping register */ -#define INTERRUPT_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa4) +#define INTERRUPT_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xac) /** INTERRUPT_CORE0_LEDC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -514,11 +839,18 @@ extern "C" { #define INTERRUPT_CORE0_LEDC_INTR_MAP_M (INTERRUPT_CORE0_LEDC_INTR_MAP_V << INTERRUPT_CORE0_LEDC_INTR_MAP_S) #define INTERRUPT_CORE0_LEDC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LEDC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_USB_INTR_MAP_REG register * USB_INTR mapping register */ -#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8) +#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb0) /** INTERRUPT_CORE0_USB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -526,11 +858,18 @@ extern "C" { #define INTERRUPT_CORE0_USB_INTR_MAP_M (INTERRUPT_CORE0_USB_INTR_MAP_V << INTERRUPT_CORE0_USB_INTR_MAP_S) #define INTERRUPT_CORE0_USB_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_USB_INTR_MAP_S 0 +/** INTERRUPT_CORE0_USB_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_USB_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_USB_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_USB_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_USB_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_USB_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_USB_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG register * I2C_EXT0_INTR mapping register */ -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb4) /** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -538,11 +877,18 @@ extern "C" { #define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M (INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V << INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S) #define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG register * TG0_T0_INTR mapping register */ -#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0) +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb8) /** INTERRUPT_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -550,11 +896,18 @@ extern "C" { #define INTERRUPT_CORE0_TG0_T0_INTR_MAP_M (INTERRUPT_CORE0_TG0_T0_INTR_MAP_V << INTERRUPT_CORE0_TG0_T0_INTR_MAP_S) #define INTERRUPT_CORE0_TG0_T0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TG0_T0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TG0_T1_INTR_MAP_REG register * TG0_T1_INTR mapping register */ -#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4) +#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xbc) /** INTERRUPT_CORE0_TG0_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -562,11 +915,18 @@ extern "C" { #define INTERRUPT_CORE0_TG0_T1_INTR_MAP_M (INTERRUPT_CORE0_TG0_T1_INTR_MAP_V << INTERRUPT_CORE0_TG0_T1_INTR_MAP_S) #define INTERRUPT_CORE0_TG0_T1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TG0_T1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG0_T1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG0_T1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG0_T1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG0_T1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG0_T1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG0_T1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG0_T1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG register * TG0_WDT_INTR mapping register */ -#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8) +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc0) /** INTERRUPT_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -574,11 +934,18 @@ extern "C" { #define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_M (INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S) #define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG register * TG1_T0_INTR mapping register */ -#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc) +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc4) /** INTERRUPT_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -586,11 +953,18 @@ extern "C" { #define INTERRUPT_CORE0_TG1_T0_INTR_MAP_M (INTERRUPT_CORE0_TG1_T0_INTR_MAP_V << INTERRUPT_CORE0_TG1_T0_INTR_MAP_S) #define INTERRUPT_CORE0_TG1_T0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TG1_T0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TG1_T1_INTR_MAP_REG register * TG1_T1_INTR mapping register */ -#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0) +#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc8) /** INTERRUPT_CORE0_TG1_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -598,11 +972,18 @@ extern "C" { #define INTERRUPT_CORE0_TG1_T1_INTR_MAP_M (INTERRUPT_CORE0_TG1_T1_INTR_MAP_V << INTERRUPT_CORE0_TG1_T1_INTR_MAP_S) #define INTERRUPT_CORE0_TG1_T1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TG1_T1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG1_T1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG1_T1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG1_T1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG1_T1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG1_T1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG1_T1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG1_T1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG register * TG1_WDT_INTR mapping register */ -#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4) +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xcc) /** INTERRUPT_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -610,11 +991,18 @@ extern "C" { #define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_M (INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S) #define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register * SYSTIMER_TARGET0_INTR mapping register */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd0) /** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -622,11 +1010,18 @@ extern "C" { #define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S) #define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register * SYSTIMER_TARGET1_INTR mapping register */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd4) /** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -634,11 +1029,18 @@ extern "C" { #define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S) #define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register * SYSTIMER_TARGET2_INTR mapping register */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd8) /** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -646,11 +1048,18 @@ extern "C" { #define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S) #define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG register * APB_ADC_INTR mapping register */ -#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4) +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xdc) /** INTERRUPT_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -658,11 +1067,56 @@ extern "C" { #define INTERRUPT_CORE0_APB_ADC_INTR_MAP_M (INTERRUPT_CORE0_APB_ADC_INTR_MAP_V << INTERRUPT_CORE0_APB_ADC_INTR_MAP_S) #define INTERRUPT_CORE0_APB_ADC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_APB_ADC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_SLC0_INTR_MAP_REG register + * SLC0_INTR mapping register + */ +#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe0) +/** INTERRUPT_CORE0_SLC0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SLC0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SLC0_INTR_MAP_M (INTERRUPT_CORE0_SLC0_INTR_MAP_V << INTERRUPT_CORE0_SLC0_INTR_MAP_S) +#define INTERRUPT_CORE0_SLC0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SLC0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_SLC1_INTR_MAP_REG register + * SLC1_INTR mapping register + */ +#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe4) +/** INTERRUPT_CORE0_SLC1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SLC1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SLC1_INTR_MAP_M (INTERRUPT_CORE0_SLC1_INTR_MAP_V << INTERRUPT_CORE0_SLC1_INTR_MAP_S) +#define INTERRUPT_CORE0_SLC1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SLC1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG register * DMA_IN_CH0_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8) +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe8) /** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -670,11 +1124,18 @@ extern "C" { #define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S) #define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG register * DMA_IN_CH1_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc) +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xec) /** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -682,11 +1143,18 @@ extern "C" { #define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S) #define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG register * DMA_OUT_CH0_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0) +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf0) /** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -694,11 +1162,18 @@ extern "C" { #define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S) #define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG register * DMA_OUT_CH1_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4) +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf4) /** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -706,11 +1181,18 @@ extern "C" { #define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S) #define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG register * GPSPI2_INTR mapping register */ -#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8) +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf8) /** INTERRUPT_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -718,11 +1200,18 @@ extern "C" { #define INTERRUPT_CORE0_GPSPI2_INTR_MAP_M (INTERRUPT_CORE0_GPSPI2_INTR_MAP_V << INTERRUPT_CORE0_GPSPI2_INTR_MAP_S) #define INTERRUPT_CORE0_GPSPI2_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_GPSPI2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_SHA_INTR_MAP_REG register * SHA_INTR mapping register */ -#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec) +#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xfc) /** INTERRUPT_CORE0_SHA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -730,11 +1219,18 @@ extern "C" { #define INTERRUPT_CORE0_SHA_INTR_MAP_M (INTERRUPT_CORE0_SHA_INTR_MAP_V << INTERRUPT_CORE0_SHA_INTR_MAP_S) #define INTERRUPT_CORE0_SHA_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SHA_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_ECC_INTR_MAP_REG register * ECC_INTR mapping register */ -#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0) +#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x100) /** INTERRUPT_CORE0_ECC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -742,11 +1238,18 @@ extern "C" { #define INTERRUPT_CORE0_ECC_INTR_MAP_M (INTERRUPT_CORE0_ECC_INTR_MAP_V << INTERRUPT_CORE0_ECC_INTR_MAP_S) #define INTERRUPT_CORE0_ECC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_ECC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_ECDSA_INTR_MAP_REG register * ECDSA_INTR mapping register */ -#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4) +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x104) /** INTERRUPT_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -754,14 +1257,21 @@ extern "C" { #define INTERRUPT_CORE0_ECDSA_INTR_MAP_M (INTERRUPT_CORE0_ECDSA_INTR_MAP_V << INTERRUPT_CORE0_ECDSA_INTR_MAP_S) #define INTERRUPT_CORE0_ECDSA_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_ECDSA_INTR_MAP_S 0 +/** INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_S 8 -/** INTERRUPT_CORE0_INT_STATUS_0_REG register +/** INTERRUPT_CORE0_INT_STATUS_REG_0_REG register * Status register for interrupt sources 0 ~ 31 */ -#define INTERRUPT_CORE0_INT_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8) +#define INTERRUPT_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTMTX_BASE + 0x108) /** INTERRUPT_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0; - * Represents the status of the interrupt sources numbered from .Each bit corresponds - * to one interrupt source + * Represents the status of the interrupt sources within interrupt-index-range 0 ~ 31. + * Each bit corresponds to one interrupt source * 0:The corresponding interrupt source triggered an interrupt * 1:No interrupt triggered */ @@ -770,13 +1280,13 @@ extern "C" { #define INTERRUPT_CORE0_INT_STATUS_0_V 0xFFFFFFFFU #define INTERRUPT_CORE0_INT_STATUS_0_S 0 -/** INTERRUPT_CORE0_INT_STATUS_1_REG register +/** INTERRUPT_CORE0_INT_STATUS_REG_1_REG register * Status register for interrupt sources 32 ~ 63 */ -#define INTERRUPT_CORE0_INT_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc) +#define INTERRUPT_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTMTX_BASE + 0x10c) /** INTERRUPT_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0; - * Represents the status of the interrupt sources numbered from .Each bit corresponds - * to one interrupt source + * Represents the status of the interrupt sources within interrupt-index-range 32 ~ + * 63. Each bit corresponds to one interrupt source * 0:The corresponding interrupt source triggered an interrupt * 1:No interrupt triggered */ @@ -785,10 +1295,94 @@ extern "C" { #define INTERRUPT_CORE0_INT_STATUS_1_V 0xFFFFFFFFU #define INTERRUPT_CORE0_INT_STATUS_1_S 0 +/** INTERRUPT_CORE0_INT_STATUS_REG_2_REG register + * Status register for interrupt sources 64 ~ 65 + */ +#define INTERRUPT_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTMTX_BASE + 0x110) +/** INTERRUPT_CORE0_INT_STATUS_2 : RO; bitpos: [1:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 64 ~ + * 65. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ +#define INTERRUPT_CORE0_INT_STATUS_2 0x00000003U +#define INTERRUPT_CORE0_INT_STATUS_2_M (INTERRUPT_CORE0_INT_STATUS_2_V << INTERRUPT_CORE0_INT_STATUS_2_S) +#define INTERRUPT_CORE0_INT_STATUS_2_V 0x00000003U +#define INTERRUPT_CORE0_INT_STATUS_2_S 0 + +/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_0_REG register + * PASS_IN_SEC status register for interrupt sources 0 ~ 31 + */ +#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_0_REG (DR_REG_INTMTX_BASE + 0x114) +/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0 : RO; bitpos: [31:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources within + * interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_M (INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_S) +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_S 0 + +/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_1_REG register + * PASS_IN_SEC status register for interrupt sources 32 ~ 63 + */ +#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_1_REG (DR_REG_INTMTX_BASE + 0x118) +/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1 : RO; bitpos: [31:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources within + * interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_M (INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_S) +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_S 0 + +/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_2_REG register + * PASS_IN_SEC status register for interrupt sources 64 ~ 65 + */ +#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_2_REG (DR_REG_INTMTX_BASE + 0x11c) +/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2 : RO; bitpos: [1:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources with + * interrupt-index-range 64 ~ 65. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2 0x00000003U +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_M (INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_S) +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_V 0x00000003U +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_S 0 + +/** INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG register + * reserved + */ +#define INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG (DR_REG_INTMTX_BASE + 0x120) +/** INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC : R/W; bitpos: [5:0]; default: 0; + * reserved + */ +#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC 0x0000003FU +#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_M (INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_V << INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_S) +#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_V 0x0000003FU +#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_S 0 + +/** INTERRUPT_CORE0_SECURE_STATUS_REG register + * reserved + */ +#define INTERRUPT_CORE0_SECURE_STATUS_REG (DR_REG_INTMTX_BASE + 0x124) +/** INTERRUPT_CORE0_INT_SECURE_STATUS : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define INTERRUPT_CORE0_INT_SECURE_STATUS 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SECURE_STATUS_M (INTERRUPT_CORE0_INT_SECURE_STATUS_V << INTERRUPT_CORE0_INT_SECURE_STATUS_S) +#define INTERRUPT_CORE0_INT_SECURE_STATUS_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SECURE_STATUS_S 0 + /** INTERRUPT_CORE0_CLOCK_GATE_REG register * Interrupt clock gating configure register */ -#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) +#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTMTX_BASE + 0x128) /** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 0; * Interrupt clock gating configure register */ @@ -800,8 +1394,8 @@ extern "C" { /** INTERRUPT_CORE0_INTERRUPT_DATE_REG register * Version control register */ -#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7fc) -/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 36774400; +#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTMTX_BASE + 0x7fc) +/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 38801441; * Version control register */ #define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c61/register/soc/interrupt_matrix_struct.h b/components/soc/esp32c61/register/soc/interrupt_matrix_struct.h index 2b7d52e189..1920ed6d89 100644 --- a/components/soc/esp32c61/register/soc/interrupt_matrix_struct.h +++ b/components/soc/esp32c61/register/soc/interrupt_matrix_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,1005 +11,1496 @@ extern "C" { #endif /** Group: Configuration Registers */ -/** Type of wifi_mac_intr_map register +/** Type of core0_wifi_mac_intr_map register * WIFI_MAC_INTR mapping register */ typedef union { struct { - /** wifi_mac_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_wifi_mac_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t wifi_mac_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_wifi_mac_intr_map:6; + uint32_t reserved_6:2; + /** core0_wifi_mac_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_wifi_mac_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_wifi_mac_intr_map_reg_t; +} interrupt_core0_wifi_mac_intr_map_reg_t; -/** Type of wifi_mac_nmi_map register +/** Type of core0_wifi_mac_nmi_map register * WIFI_MAC_NMI mapping register */ typedef union { struct { - /** wifi_mac_nmi_map : R/W; bitpos: [5:0]; default: 0; + /** core0_wifi_mac_nmi_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t wifi_mac_nmi_map:6; - uint32_t reserved_6:26; + uint32_t core0_wifi_mac_nmi_map:6; + uint32_t reserved_6:2; + /** core0_wifi_mac_nmi_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_wifi_mac_nmi_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_wifi_mac_nmi_map_reg_t; +} interrupt_core0_wifi_mac_nmi_map_reg_t; -/** Type of wifi_pwr_intr_map register +/** Type of core0_wifi_pwr_intr_map register * WIFI_PWR_INTR mapping register */ typedef union { struct { - /** wifi_pwr_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_wifi_pwr_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t wifi_pwr_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_wifi_pwr_intr_map:6; + uint32_t reserved_6:2; + /** core0_wifi_pwr_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_wifi_pwr_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_wifi_pwr_intr_map_reg_t; +} interrupt_core0_wifi_pwr_intr_map_reg_t; -/** Type of wifi_bb_intr_map register +/** Type of core0_wifi_bb_intr_map register * WIFI_BB_INTR mapping register */ typedef union { struct { - /** wifi_bb_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_wifi_bb_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t wifi_bb_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_wifi_bb_intr_map:6; + uint32_t reserved_6:2; + /** core0_wifi_bb_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_wifi_bb_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_wifi_bb_intr_map_reg_t; +} interrupt_core0_wifi_bb_intr_map_reg_t; -/** Type of bt_mac_intr_map register +/** Type of core0_bt_mac_intr_map register * BT_MAC_INTR mapping register */ typedef union { struct { - /** bt_mac_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_bt_mac_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t bt_mac_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_bt_mac_intr_map:6; + uint32_t reserved_6:2; + /** core0_bt_mac_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_bt_mac_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_bt_mac_intr_map_reg_t; +} interrupt_core0_bt_mac_intr_map_reg_t; -/** Type of bt_bb_intr_map register +/** Type of core0_bt_bb_intr_map register * BT_BB_INTR mapping register */ typedef union { struct { - /** bt_bb_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_bt_bb_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t bt_bb_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_bt_bb_intr_map:6; + uint32_t reserved_6:2; + /** core0_bt_bb_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_bt_bb_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_bt_bb_intr_map_reg_t; +} interrupt_core0_bt_bb_intr_map_reg_t; -/** Type of bt_bb_nmi_map register +/** Type of core0_bt_bb_nmi_map register * BT_BB_NMI mapping register */ typedef union { struct { - /** bt_bb_nmi_map : R/W; bitpos: [5:0]; default: 0; + /** core0_bt_bb_nmi_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t bt_bb_nmi_map:6; - uint32_t reserved_6:26; + uint32_t core0_bt_bb_nmi_map:6; + uint32_t reserved_6:2; + /** core0_bt_bb_nmi_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_bt_bb_nmi_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_bt_bb_nmi_map_reg_t; +} interrupt_core0_bt_bb_nmi_map_reg_t; -/** Type of lp_timer_intr_map register +/** Type of core0_lp_timer_intr_map register * LP_TIMER_INTR mapping register */ typedef union { struct { - /** lp_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_lp_timer_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t lp_timer_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_lp_timer_intr_map:6; + uint32_t reserved_6:2; + /** core0_lp_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_lp_timer_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_lp_timer_intr_map_reg_t; +} interrupt_core0_lp_timer_intr_map_reg_t; -/** Type of coex_intr_map register +/** Type of core0_coex_intr_map register * COEX_INTR mapping register */ typedef union { struct { - /** coex_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_coex_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t coex_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_coex_intr_map:6; + uint32_t reserved_6:2; + /** core0_coex_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_coex_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_coex_intr_map_reg_t; +} interrupt_core0_coex_intr_map_reg_t; -/** Type of ble_timer_intr_map register +/** Type of core0_ble_timer_intr_map register * BLE_TIMER_INTR mapping register */ typedef union { struct { - /** ble_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_ble_timer_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t ble_timer_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_ble_timer_intr_map:6; + uint32_t reserved_6:2; + /** core0_ble_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_ble_timer_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_ble_timer_intr_map_reg_t; +} interrupt_core0_ble_timer_intr_map_reg_t; -/** Type of ble_sec_intr_map register +/** Type of core0_ble_sec_intr_map register * BLE_SEC_INTR mapping register */ typedef union { struct { - /** ble_sec_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_ble_sec_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t ble_sec_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_ble_sec_intr_map:6; + uint32_t reserved_6:2; + /** core0_ble_sec_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_ble_sec_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_ble_sec_intr_map_reg_t; +} interrupt_core0_ble_sec_intr_map_reg_t; -/** Type of i2c_mst_intr_map register +/** Type of core0_i2c_mst_intr_map register * I2C_MST_INTR mapping register */ typedef union { struct { - /** i2c_mst_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_i2c_mst_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t i2c_mst_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_i2c_mst_intr_map:6; + uint32_t reserved_6:2; + /** core0_i2c_mst_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_i2c_mst_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_i2c_mst_intr_map_reg_t; +} interrupt_core0_i2c_mst_intr_map_reg_t; -/** Type of zb_mac_intr_map register +/** Type of core0_zb_mac_intr_map register * ZB_MAC_INTR mapping register */ typedef union { struct { - /** zb_mac_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_zb_mac_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t zb_mac_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_zb_mac_intr_map:6; + uint32_t reserved_6:2; + /** core0_zb_mac_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_zb_mac_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_zb_mac_intr_map_reg_t; +} interrupt_core0_zb_mac_intr_map_reg_t; -/** Type of pmu_intr_map register +/** Type of core0_pmu_intr_map register * PMU_INTR mapping register */ typedef union { struct { - /** pmu_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_pmu_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t pmu_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_pmu_intr_map:6; + uint32_t reserved_6:2; + /** core0_pmu_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_pmu_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_pmu_intr_map_reg_t; +} interrupt_core0_pmu_intr_map_reg_t; -/** Type of efuse_intr_map register +/** Type of core0_efuse_intr_map register * EFUSE_INTR mapping register */ typedef union { struct { - /** efuse_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_efuse_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t efuse_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_efuse_intr_map:6; + uint32_t reserved_6:2; + /** core0_efuse_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_efuse_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_efuse_intr_map_reg_t; +} interrupt_core0_efuse_intr_map_reg_t; -/** Type of lp_rtc_timer_intr_map register +/** Type of core0_lp_rtc_timer_intr_map register * LP_RTC_TIMER_INTR mapping register */ typedef union { struct { - /** lp_rtc_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_lp_rtc_timer_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t lp_rtc_timer_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_lp_rtc_timer_intr_map:6; + uint32_t reserved_6:2; + /** core0_lp_rtc_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_lp_rtc_timer_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_lp_rtc_timer_intr_map_reg_t; +} interrupt_core0_lp_rtc_timer_intr_map_reg_t; -/** Type of lp_wdt_intr_map register +/** Type of core0_lp_wdt_intr_map register * LP_WDT_INTR mapping register */ typedef union { struct { - /** lp_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_lp_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t lp_wdt_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_lp_wdt_intr_map:6; + uint32_t reserved_6:2; + /** core0_lp_wdt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_lp_wdt_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_lp_wdt_intr_map_reg_t; +} interrupt_core0_lp_wdt_intr_map_reg_t; -/** Type of lp_peri_timeout_intr_map register +/** Type of core0_lp_peri_timeout_intr_map register * LP_PERI_TIMEOUT_INTR mapping register */ typedef union { struct { - /** lp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_lp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t lp_peri_timeout_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_lp_peri_timeout_intr_map:6; + uint32_t reserved_6:2; + /** core0_lp_peri_timeout_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_lp_peri_timeout_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_lp_peri_timeout_intr_map_reg_t; +} interrupt_core0_lp_peri_timeout_intr_map_reg_t; -/** Type of lp_apm_m0_intr_map register +/** Type of core0_lp_apm_m0_intr_map register * LP_APM_M0_INTR mapping register */ typedef union { struct { - /** lp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_lp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t lp_apm_m0_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_lp_apm_m0_intr_map:6; + uint32_t reserved_6:2; + /** core0_lp_apm_m0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_lp_apm_m0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_lp_apm_m0_intr_map_reg_t; +} interrupt_core0_lp_apm_m0_intr_map_reg_t; -/** Type of cpu_intr_from_cpu_0_map register +/** Type of core0_cpu_intr_from_cpu_0_map register * CPU_INTR_FROM_CPU_0 mapping register */ typedef union { struct { - /** cpu_intr_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0; + /** core0_cpu_intr_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t cpu_intr_from_cpu_0_map:6; - uint32_t reserved_6:26; + uint32_t core0_cpu_intr_from_cpu_0_map:6; + uint32_t reserved_6:2; + /** core0_cpu_intr_from_cpu_0_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_cpu_intr_from_cpu_0_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_cpu_intr_from_cpu_0_map_reg_t; +} interrupt_core0_cpu_intr_from_cpu_0_map_reg_t; -/** Type of cpu_intr_from_cpu_1_map register +/** Type of core0_cpu_intr_from_cpu_1_map register * CPU_INTR_FROM_CPU_1 mapping register */ typedef union { struct { - /** cpu_intr_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0; + /** core0_cpu_intr_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t cpu_intr_from_cpu_1_map:6; - uint32_t reserved_6:26; + uint32_t core0_cpu_intr_from_cpu_1_map:6; + uint32_t reserved_6:2; + /** core0_cpu_intr_from_cpu_1_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_cpu_intr_from_cpu_1_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_cpu_intr_from_cpu_1_map_reg_t; +} interrupt_core0_cpu_intr_from_cpu_1_map_reg_t; -/** Type of cpu_intr_from_cpu_2_map register +/** Type of core0_cpu_intr_from_cpu_2_map register * CPU_INTR_FROM_CPU_2 mapping register */ typedef union { struct { - /** cpu_intr_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0; + /** core0_cpu_intr_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t cpu_intr_from_cpu_2_map:6; - uint32_t reserved_6:26; + uint32_t core0_cpu_intr_from_cpu_2_map:6; + uint32_t reserved_6:2; + /** core0_cpu_intr_from_cpu_2_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_cpu_intr_from_cpu_2_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_cpu_intr_from_cpu_2_map_reg_t; +} interrupt_core0_cpu_intr_from_cpu_2_map_reg_t; -/** Type of cpu_intr_from_cpu_3_map register +/** Type of core0_cpu_intr_from_cpu_3_map register * CPU_INTR_FROM_CPU_3 mapping register */ typedef union { struct { - /** cpu_intr_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0; + /** core0_cpu_intr_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t cpu_intr_from_cpu_3_map:6; - uint32_t reserved_6:26; + uint32_t core0_cpu_intr_from_cpu_3_map:6; + uint32_t reserved_6:2; + /** core0_cpu_intr_from_cpu_3_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_cpu_intr_from_cpu_3_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_cpu_intr_from_cpu_3_map_reg_t; +} interrupt_core0_cpu_intr_from_cpu_3_map_reg_t; -/** Type of assist_debug_intr_map register +/** Type of core0_assist_debug_intr_map register * ASSIST_DEBUG_INTR mapping register */ typedef union { struct { - /** assist_debug_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_assist_debug_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t assist_debug_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_assist_debug_intr_map:6; + uint32_t reserved_6:2; + /** core0_assist_debug_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_assist_debug_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_assist_debug_intr_map_reg_t; +} interrupt_core0_assist_debug_intr_map_reg_t; -/** Type of trace_intr_map register +/** Type of core0_trace_intr_map register * TRACE_INTR mapping register */ typedef union { struct { - /** trace_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_trace_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t trace_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_trace_intr_map:6; + uint32_t reserved_6:2; + /** core0_trace_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_trace_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_trace_intr_map_reg_t; +} interrupt_core0_trace_intr_map_reg_t; -/** Type of cache_intr_map register +/** Type of core0_cache_intr_map register * CACHE_INTR mapping register */ typedef union { struct { - /** cache_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_cache_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t cache_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_cache_intr_map:6; + uint32_t reserved_6:2; + /** core0_cache_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_cache_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_cache_intr_map_reg_t; +} interrupt_core0_cache_intr_map_reg_t; -/** Type of cpu_peri_timeout_intr_map register +/** Type of core0_cpu_peri_timeout_intr_map register * CPU_PERI_TIMEOUT_INTR mapping register */ typedef union { struct { - /** cpu_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_cpu_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t cpu_peri_timeout_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_cpu_peri_timeout_intr_map:6; + uint32_t reserved_6:2; + /** core0_cpu_peri_timeout_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_cpu_peri_timeout_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_cpu_peri_timeout_intr_map_reg_t; +} interrupt_core0_cpu_peri_timeout_intr_map_reg_t; -/** Type of gpio_interrupt_pro_map register +/** Type of core0_gpio_interrupt_pro_map register * GPIO_INTERRUPT_PRO mapping register */ typedef union { struct { - /** gpio_interrupt_pro_map : R/W; bitpos: [5:0]; default: 0; + /** core0_gpio_interrupt_pro_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t gpio_interrupt_pro_map:6; - uint32_t reserved_6:26; + uint32_t core0_gpio_interrupt_pro_map:6; + uint32_t reserved_6:2; + /** core0_gpio_interrupt_pro_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_gpio_interrupt_pro_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_gpio_interrupt_pro_map_reg_t; +} interrupt_core0_gpio_interrupt_pro_map_reg_t; -/** Type of gpio_interrupt_ext_map register +/** Type of core0_gpio_interrupt_ext_map register * GPIO_INTERRUPT_EXT mapping register */ typedef union { struct { - /** gpio_interrupt_ext_map : R/W; bitpos: [5:0]; default: 0; + /** core0_gpio_interrupt_ext_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t gpio_interrupt_ext_map:6; - uint32_t reserved_6:26; + uint32_t core0_gpio_interrupt_ext_map:6; + uint32_t reserved_6:2; + /** core0_gpio_interrupt_ext_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_gpio_interrupt_ext_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_gpio_interrupt_ext_map_reg_t; +} interrupt_core0_gpio_interrupt_ext_map_reg_t; -/** Type of pau_intr_map register +/** Type of core0_pau_intr_map register * PAU_INTR mapping register */ typedef union { struct { - /** pau_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_pau_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t pau_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_pau_intr_map:6; + uint32_t reserved_6:2; + /** core0_pau_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_pau_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_pau_intr_map_reg_t; +} interrupt_core0_pau_intr_map_reg_t; -/** Type of hp_peri_timeout_intr_map register +/** Type of core0_hp_peri_timeout_intr_map register * HP_PERI_TIMEOUT_INTR mapping register */ typedef union { struct { - /** hp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_hp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t hp_peri_timeout_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_hp_peri_timeout_intr_map:6; + uint32_t reserved_6:2; + /** core0_hp_peri_timeout_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_hp_peri_timeout_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_hp_peri_timeout_intr_map_reg_t; +} interrupt_core0_hp_peri_timeout_intr_map_reg_t; -/** Type of modem_peri_timeout_intr_map register +/** Type of core0_modem_peri_timeout_intr_map register * MODEM_PERI_TIMEOUT_INTR mapping register */ typedef union { struct { - /** modem_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_modem_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t modem_peri_timeout_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_modem_peri_timeout_intr_map:6; + uint32_t reserved_6:2; + /** core0_modem_peri_timeout_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_modem_peri_timeout_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_modem_peri_timeout_intr_map_reg_t; +} interrupt_core0_modem_peri_timeout_intr_map_reg_t; -/** Type of hp_apm_m0_intr_map register +/** Type of core0_hp_apm_m0_intr_map register * HP_APM_M0_INTR mapping register */ typedef union { struct { - /** hp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_hp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t hp_apm_m0_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_hp_apm_m0_intr_map:6; + uint32_t reserved_6:2; + /** core0_hp_apm_m0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_hp_apm_m0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_hp_apm_m0_intr_map_reg_t; +} interrupt_core0_hp_apm_m0_intr_map_reg_t; -/** Type of hp_apm_m1_intr_map register +/** Type of core0_hp_apm_m1_intr_map register * HP_APM_M1_INTR mapping register */ typedef union { struct { - /** hp_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_hp_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t hp_apm_m1_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_hp_apm_m1_intr_map:6; + uint32_t reserved_6:2; + /** core0_hp_apm_m1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_hp_apm_m1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_hp_apm_m1_intr_map_reg_t; +} interrupt_core0_hp_apm_m1_intr_map_reg_t; -/** Type of hp_apm_m2_intr_map register +/** Type of core0_hp_apm_m2_intr_map register * HP_APM_M2_INTR mapping register */ typedef union { struct { - /** hp_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_hp_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t hp_apm_m2_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_hp_apm_m2_intr_map:6; + uint32_t reserved_6:2; + /** core0_hp_apm_m2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_hp_apm_m2_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_hp_apm_m2_intr_map_reg_t; +} interrupt_core0_hp_apm_m2_intr_map_reg_t; -/** Type of hp_apm_m3_intr_map register +/** Type of core0_hp_apm_m3_intr_map register * HP_APM_M3_INTR mapping register */ typedef union { struct { - /** hp_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_hp_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t hp_apm_m3_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_hp_apm_m3_intr_map:6; + uint32_t reserved_6:2; + /** core0_hp_apm_m3_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_hp_apm_m3_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_hp_apm_m3_intr_map_reg_t; +} interrupt_core0_hp_apm_m3_intr_map_reg_t; -/** Type of mspi_intr_map register +/** Type of core0_cpu_apm_m0_intr_map register + * CPU_APM_M0_INTR mapping register + */ +typedef union { + struct { + /** core0_cpu_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core0_cpu_apm_m0_intr_map:6; + uint32_t reserved_6:2; + /** core0_cpu_apm_m0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_cpu_apm_m0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_cpu_apm_m0_intr_map_reg_t; + +/** Type of core0_cpu_apm_m1_intr_map register + * CPU_APM_M1_INTR mapping register + */ +typedef union { + struct { + /** core0_cpu_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core0_cpu_apm_m1_intr_map:6; + uint32_t reserved_6:2; + /** core0_cpu_apm_m1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_cpu_apm_m1_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_cpu_apm_m1_intr_map_reg_t; + +/** Type of core0_mspi_intr_map register * MSPI_INTR mapping register */ typedef union { struct { - /** mspi_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_mspi_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t mspi_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_mspi_intr_map:6; + uint32_t reserved_6:2; + /** core0_mspi_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_mspi_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_mspi_intr_map_reg_t; +} interrupt_core0_mspi_intr_map_reg_t; -/** Type of i2s1_intr_map register +/** Type of core0_i2s1_intr_map register * I2S1_INTR mapping register */ typedef union { struct { - /** i2s1_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_i2s1_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t i2s1_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_i2s1_intr_map:6; + uint32_t reserved_6:2; + /** core0_i2s1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_i2s1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_i2s1_intr_map_reg_t; +} interrupt_core0_i2s1_intr_map_reg_t; -/** Type of uart0_intr_map register +/** Type of core0_uart0_intr_map register * UART0_INTR mapping register */ typedef union { struct { - /** uart0_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_uart0_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t uart0_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_uart0_intr_map:6; + uint32_t reserved_6:2; + /** core0_uart0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_uart0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_uart0_intr_map_reg_t; +} interrupt_core0_uart0_intr_map_reg_t; -/** Type of uart1_intr_map register +/** Type of core0_uart1_intr_map register * UART1_INTR mapping register */ typedef union { struct { - /** uart1_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_uart1_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t uart1_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_uart1_intr_map:6; + uint32_t reserved_6:2; + /** core0_uart1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_uart1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_uart1_intr_map_reg_t; +} interrupt_core0_uart1_intr_map_reg_t; -/** Type of uart2_intr_map register +/** Type of core0_uart2_intr_map register * UART2_INTR mapping register */ typedef union { struct { - /** uart2_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_uart2_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t uart2_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_uart2_intr_map:6; + uint32_t reserved_6:2; + /** core0_uart2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_uart2_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_uart2_intr_map_reg_t; +} interrupt_core0_uart2_intr_map_reg_t; -/** Type of ledc_intr_map register +/** Type of core0_ledc_intr_map register * LEDC_INTR mapping register */ typedef union { struct { - /** ledc_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_ledc_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t ledc_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_ledc_intr_map:6; + uint32_t reserved_6:2; + /** core0_ledc_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_ledc_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_ledc_intr_map_reg_t; +} interrupt_core0_ledc_intr_map_reg_t; -/** Type of usb_intr_map register +/** Type of core0_usb_intr_map register * USB_INTR mapping register */ typedef union { struct { - /** usb_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_usb_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t usb_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_usb_intr_map:6; + uint32_t reserved_6:2; + /** core0_usb_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_usb_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_usb_intr_map_reg_t; +} interrupt_core0_usb_intr_map_reg_t; -/** Type of i2c_ext0_intr_map register +/** Type of core0_i2c_ext0_intr_map register * I2C_EXT0_INTR mapping register */ typedef union { struct { - /** i2c_ext0_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_i2c_ext0_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t i2c_ext0_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_i2c_ext0_intr_map:6; + uint32_t reserved_6:2; + /** core0_i2c_ext0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_i2c_ext0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_i2c_ext0_intr_map_reg_t; +} interrupt_core0_i2c_ext0_intr_map_reg_t; -/** Type of tg0_t0_intr_map register +/** Type of core0_tg0_t0_intr_map register * TG0_T0_INTR mapping register */ typedef union { struct { - /** tg0_t0_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_tg0_t0_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t tg0_t0_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_tg0_t0_intr_map:6; + uint32_t reserved_6:2; + /** core0_tg0_t0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_tg0_t0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_tg0_t0_intr_map_reg_t; +} interrupt_core0_tg0_t0_intr_map_reg_t; -/** Type of tg0_t1_intr_map register +/** Type of core0_tg0_t1_intr_map register * TG0_T1_INTR mapping register */ typedef union { struct { - /** tg0_t1_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_tg0_t1_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t tg0_t1_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_tg0_t1_intr_map:6; + uint32_t reserved_6:2; + /** core0_tg0_t1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_tg0_t1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_tg0_t1_intr_map_reg_t; +} interrupt_core0_tg0_t1_intr_map_reg_t; -/** Type of tg0_wdt_intr_map register +/** Type of core0_tg0_wdt_intr_map register * TG0_WDT_INTR mapping register */ typedef union { struct { - /** tg0_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_tg0_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t tg0_wdt_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_tg0_wdt_intr_map:6; + uint32_t reserved_6:2; + /** core0_tg0_wdt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_tg0_wdt_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_tg0_wdt_intr_map_reg_t; +} interrupt_core0_tg0_wdt_intr_map_reg_t; -/** Type of tg1_t0_intr_map register +/** Type of core0_tg1_t0_intr_map register * TG1_T0_INTR mapping register */ typedef union { struct { - /** tg1_t0_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_tg1_t0_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t tg1_t0_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_tg1_t0_intr_map:6; + uint32_t reserved_6:2; + /** core0_tg1_t0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_tg1_t0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_tg1_t0_intr_map_reg_t; +} interrupt_core0_tg1_t0_intr_map_reg_t; -/** Type of tg1_t1_intr_map register +/** Type of core0_tg1_t1_intr_map register * TG1_T1_INTR mapping register */ typedef union { struct { - /** tg1_t1_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_tg1_t1_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t tg1_t1_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_tg1_t1_intr_map:6; + uint32_t reserved_6:2; + /** core0_tg1_t1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_tg1_t1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_tg1_t1_intr_map_reg_t; +} interrupt_core0_tg1_t1_intr_map_reg_t; -/** Type of tg1_wdt_intr_map register +/** Type of core0_tg1_wdt_intr_map register * TG1_WDT_INTR mapping register */ typedef union { struct { - /** tg1_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_tg1_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t tg1_wdt_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_tg1_wdt_intr_map:6; + uint32_t reserved_6:2; + /** core0_tg1_wdt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_tg1_wdt_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_tg1_wdt_intr_map_reg_t; +} interrupt_core0_tg1_wdt_intr_map_reg_t; -/** Type of systimer_target0_intr_map register +/** Type of core0_systimer_target0_intr_map register * SYSTIMER_TARGET0_INTR mapping register */ typedef union { struct { - /** systimer_target0_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_systimer_target0_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t systimer_target0_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_systimer_target0_intr_map:6; + uint32_t reserved_6:2; + /** core0_systimer_target0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_systimer_target0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_systimer_target0_intr_map_reg_t; +} interrupt_core0_systimer_target0_intr_map_reg_t; -/** Type of systimer_target1_intr_map register +/** Type of core0_systimer_target1_intr_map register * SYSTIMER_TARGET1_INTR mapping register */ typedef union { struct { - /** systimer_target1_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_systimer_target1_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t systimer_target1_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_systimer_target1_intr_map:6; + uint32_t reserved_6:2; + /** core0_systimer_target1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_systimer_target1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_systimer_target1_intr_map_reg_t; +} interrupt_core0_systimer_target1_intr_map_reg_t; -/** Type of systimer_target2_intr_map register +/** Type of core0_systimer_target2_intr_map register * SYSTIMER_TARGET2_INTR mapping register */ typedef union { struct { - /** systimer_target2_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_systimer_target2_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t systimer_target2_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_systimer_target2_intr_map:6; + uint32_t reserved_6:2; + /** core0_systimer_target2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_systimer_target2_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_systimer_target2_intr_map_reg_t; +} interrupt_core0_systimer_target2_intr_map_reg_t; -/** Type of apb_adc_intr_map register +/** Type of core0_apb_adc_intr_map register * APB_ADC_INTR mapping register */ typedef union { struct { - /** apb_adc_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_apb_adc_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t apb_adc_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_apb_adc_intr_map:6; + uint32_t reserved_6:2; + /** core0_apb_adc_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_apb_adc_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_apb_adc_intr_map_reg_t; +} interrupt_core0_apb_adc_intr_map_reg_t; -/** Type of dma_in_ch0_intr_map register +/** Type of core0_slc0_intr_map register + * SLC0_INTR mapping register + */ +typedef union { + struct { + /** core0_slc0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core0_slc0_intr_map:6; + uint32_t reserved_6:2; + /** core0_slc0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_slc0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_slc0_intr_map_reg_t; + +/** Type of core0_slc1_intr_map register + * SLC1_INTR mapping register + */ +typedef union { + struct { + /** core0_slc1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core0_slc1_intr_map:6; + uint32_t reserved_6:2; + /** core0_slc1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_slc1_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_slc1_intr_map_reg_t; + +/** Type of core0_dma_in_ch0_intr_map register * DMA_IN_CH0_INTR mapping register */ typedef union { struct { - /** dma_in_ch0_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_dma_in_ch0_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t dma_in_ch0_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_dma_in_ch0_intr_map:6; + uint32_t reserved_6:2; + /** core0_dma_in_ch0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_dma_in_ch0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_dma_in_ch0_intr_map_reg_t; +} interrupt_core0_dma_in_ch0_intr_map_reg_t; -/** Type of dma_in_ch1_intr_map register +/** Type of core0_dma_in_ch1_intr_map register * DMA_IN_CH1_INTR mapping register */ typedef union { struct { - /** dma_in_ch1_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_dma_in_ch1_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t dma_in_ch1_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_dma_in_ch1_intr_map:6; + uint32_t reserved_6:2; + /** core0_dma_in_ch1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_dma_in_ch1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_dma_in_ch1_intr_map_reg_t; +} interrupt_core0_dma_in_ch1_intr_map_reg_t; -/** Type of dma_out_ch0_intr_map register +/** Type of core0_dma_out_ch0_intr_map register * DMA_OUT_CH0_INTR mapping register */ typedef union { struct { - /** dma_out_ch0_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_dma_out_ch0_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t dma_out_ch0_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_dma_out_ch0_intr_map:6; + uint32_t reserved_6:2; + /** core0_dma_out_ch0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_dma_out_ch0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_dma_out_ch0_intr_map_reg_t; +} interrupt_core0_dma_out_ch0_intr_map_reg_t; -/** Type of dma_out_ch1_intr_map register +/** Type of core0_dma_out_ch1_intr_map register * DMA_OUT_CH1_INTR mapping register */ typedef union { struct { - /** dma_out_ch1_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_dma_out_ch1_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t dma_out_ch1_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_dma_out_ch1_intr_map:6; + uint32_t reserved_6:2; + /** core0_dma_out_ch1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_dma_out_ch1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_dma_out_ch1_intr_map_reg_t; +} interrupt_core0_dma_out_ch1_intr_map_reg_t; -/** Type of gpspi2_intr_map register +/** Type of core0_gpspi2_intr_map register * GPSPI2_INTR mapping register */ typedef union { struct { - /** gpspi2_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_gpspi2_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t gpspi2_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_gpspi2_intr_map:6; + uint32_t reserved_6:2; + /** core0_gpspi2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_gpspi2_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_gpspi2_intr_map_reg_t; +} interrupt_core0_gpspi2_intr_map_reg_t; -/** Type of sha_intr_map register +/** Type of core0_sha_intr_map register * SHA_INTR mapping register */ typedef union { struct { - /** sha_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_sha_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t sha_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_sha_intr_map:6; + uint32_t reserved_6:2; + /** core0_sha_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_sha_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_sha_intr_map_reg_t; +} interrupt_core0_sha_intr_map_reg_t; -/** Type of ecc_intr_map register +/** Type of core0_ecc_intr_map register * ECC_INTR mapping register */ typedef union { struct { - /** ecc_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_ecc_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t ecc_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_ecc_intr_map:6; + uint32_t reserved_6:2; + /** core0_ecc_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_ecc_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_ecc_intr_map_reg_t; +} interrupt_core0_ecc_intr_map_reg_t; -/** Type of ecdsa_intr_map register +/** Type of core0_ecdsa_intr_map register * ECDSA_INTR mapping register */ typedef union { struct { - /** ecdsa_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_ecdsa_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t ecdsa_intr_map:6; + uint32_t core0_ecdsa_intr_map:6; + uint32_t reserved_6:2; + /** core0_ecdsa_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_ecdsa_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_ecdsa_intr_map_reg_t; + +/** Type of core0_sig_idx_assert_in_sec register + * reserved + */ +typedef union { + struct { + /** core0_int_sig_idx_assert_in_sec : R/W; bitpos: [5:0]; default: 0; + * reserved + */ + uint32_t core0_int_sig_idx_assert_in_sec:6; uint32_t reserved_6:26; }; uint32_t val; -} interrupt_matrix_ecdsa_intr_map_reg_t; +} interrupt_core0_sig_idx_assert_in_sec_reg_t; -/** Type of int_status_0 register - * Status register for interrupt sources 0 ~ 31 - */ -typedef union { - struct { - /** int_status_0 : RO; bitpos: [31:0]; default: 0; - * Represents the status of the interrupt sources numbered from .Each bit corresponds - * to one interrupt source - * 0:The corresponding interrupt source triggered an interrupt - * 1:No interrupt triggered - */ - uint32_t int_status_0:32; - }; - uint32_t val; -} interrupt_matrix_int_status_0_reg_t; - -/** Type of int_status_1 register - * Status register for interrupt sources 32 ~ 63 - */ -typedef union { - struct { - /** int_status_1 : RO; bitpos: [31:0]; default: 0; - * Represents the status of the interrupt sources numbered from .Each bit corresponds - * to one interrupt source - * 0:The corresponding interrupt source triggered an interrupt - * 1:No interrupt triggered - */ - uint32_t int_status_1:32; - }; - uint32_t val; -} interrupt_matrix_int_status_1_reg_t; - -/** Type of clock_gate register +/** Type of core0_clock_gate register * Interrupt clock gating configure register */ typedef union { struct { - /** reg_clk_en : R/W; bitpos: [0]; default: 0; + /** core0_reg_clk_en : R/W; bitpos: [0]; default: 0; * Interrupt clock gating configure register */ - uint32_t reg_clk_en:1; + uint32_t core0_reg_clk_en:1; uint32_t reserved_1:31; }; uint32_t val; -} interrupt_matrix_clock_gate_reg_t; +} interrupt_core0_clock_gate_reg_t; + + +/** Group: Status Registers */ +/** Type of core0_int_status_reg_0 register + * Status register for interrupt sources 0 ~ 31 + */ +typedef union { + struct { + /** core0_int_status_0 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 0 ~ 31. + * Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t core0_int_status_0:32; + }; + uint32_t val; +} interrupt_core0_int_status_reg_0_reg_t; + +/** Type of core0_int_status_reg_1 register + * Status register for interrupt sources 32 ~ 63 + */ +typedef union { + struct { + /** core0_int_status_1 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 32 ~ + * 63. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t core0_int_status_1:32; + }; + uint32_t val; +} interrupt_core0_int_status_reg_1_reg_t; + +/** Type of core0_int_status_reg_2 register + * Status register for interrupt sources 64 ~ 65 + */ +typedef union { + struct { + /** core0_int_status_2 : RO; bitpos: [1:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 64 ~ + * 65. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t core0_int_status_2:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} interrupt_core0_int_status_reg_2_reg_t; + +/** Type of core0_src_pass_in_sec_status_0 register + * PASS_IN_SEC status register for interrupt sources 0 ~ 31 + */ +typedef union { + struct { + /** core0_int_src_pass_in_sec_status_0 : RO; bitpos: [31:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources within + * interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ + uint32_t core0_int_src_pass_in_sec_status_0:32; + }; + uint32_t val; +} interrupt_core0_src_pass_in_sec_status_0_reg_t; + +/** Type of core0_src_pass_in_sec_status_1 register + * PASS_IN_SEC status register for interrupt sources 32 ~ 63 + */ +typedef union { + struct { + /** core0_int_src_pass_in_sec_status_1 : RO; bitpos: [31:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources within + * interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ + uint32_t core0_int_src_pass_in_sec_status_1:32; + }; + uint32_t val; +} interrupt_core0_src_pass_in_sec_status_1_reg_t; + +/** Type of core0_src_pass_in_sec_status_2 register + * PASS_IN_SEC status register for interrupt sources 64 ~ 65 + */ +typedef union { + struct { + /** core0_int_src_pass_in_sec_status_2 : RO; bitpos: [1:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources with + * interrupt-index-range 64 ~ 65. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ + uint32_t core0_int_src_pass_in_sec_status_2:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} interrupt_core0_src_pass_in_sec_status_2_reg_t; + +/** Type of core0_secure_status register + * reserved + */ +typedef union { + struct { + /** core0_int_secure_status : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t core0_int_secure_status:32; + }; + uint32_t val; +} interrupt_core0_secure_status_reg_t; /** Group: Version Register */ -/** Type of interrupt_date register +/** Type of core0_interrupt_date register * Version control register */ typedef union { struct { - /** interrupt_date : R/W; bitpos: [27:0]; default: 36774400; + /** core0_interrupt_date : R/W; bitpos: [27:0]; default: 38801441; * Version control register */ - uint32_t interrupt_date:28; + uint32_t core0_interrupt_date:28; uint32_t reserved_28:4; }; uint32_t val; -} interrupt_matrix_interrupt_date_reg_t; +} interrupt_core0_interrupt_date_reg_t; typedef struct { - volatile interrupt_matrix_wifi_mac_intr_map_reg_t wifi_mac_intr_map; - volatile interrupt_matrix_wifi_mac_nmi_map_reg_t wifi_mac_nmi_map; - volatile interrupt_matrix_wifi_pwr_intr_map_reg_t wifi_pwr_intr_map; - volatile interrupt_matrix_wifi_bb_intr_map_reg_t wifi_bb_intr_map; - volatile interrupt_matrix_bt_mac_intr_map_reg_t bt_mac_intr_map; - volatile interrupt_matrix_bt_bb_intr_map_reg_t bt_bb_intr_map; - volatile interrupt_matrix_bt_bb_nmi_map_reg_t bt_bb_nmi_map; - volatile interrupt_matrix_lp_timer_intr_map_reg_t lp_timer_intr_map; - volatile interrupt_matrix_coex_intr_map_reg_t coex_intr_map; - volatile interrupt_matrix_ble_timer_intr_map_reg_t ble_timer_intr_map; - volatile interrupt_matrix_ble_sec_intr_map_reg_t ble_sec_intr_map; - volatile interrupt_matrix_i2c_mst_intr_map_reg_t i2c_mst_intr_map; - volatile interrupt_matrix_zb_mac_intr_map_reg_t zb_mac_intr_map; - volatile interrupt_matrix_pmu_intr_map_reg_t pmu_intr_map; - volatile interrupt_matrix_efuse_intr_map_reg_t efuse_intr_map; - volatile interrupt_matrix_lp_rtc_timer_intr_map_reg_t lp_rtc_timer_intr_map; - volatile interrupt_matrix_lp_wdt_intr_map_reg_t lp_wdt_intr_map; - volatile interrupt_matrix_lp_peri_timeout_intr_map_reg_t lp_peri_timeout_intr_map; - volatile interrupt_matrix_lp_apm_m0_intr_map_reg_t lp_apm_m0_intr_map; - volatile interrupt_matrix_cpu_intr_from_cpu_0_map_reg_t cpu_intr_from_cpu_0_map; - volatile interrupt_matrix_cpu_intr_from_cpu_1_map_reg_t cpu_intr_from_cpu_1_map; - volatile interrupt_matrix_cpu_intr_from_cpu_2_map_reg_t cpu_intr_from_cpu_2_map; - volatile interrupt_matrix_cpu_intr_from_cpu_3_map_reg_t cpu_intr_from_cpu_3_map; - volatile interrupt_matrix_assist_debug_intr_map_reg_t assist_debug_intr_map; - volatile interrupt_matrix_trace_intr_map_reg_t trace_intr_map; - volatile interrupt_matrix_cache_intr_map_reg_t cache_intr_map; - volatile interrupt_matrix_cpu_peri_timeout_intr_map_reg_t cpu_peri_timeout_intr_map; - volatile interrupt_matrix_gpio_interrupt_pro_map_reg_t gpio_interrupt_pro_map; - volatile interrupt_matrix_gpio_interrupt_ext_map_reg_t gpio_interrupt_ext_map; - volatile interrupt_matrix_pau_intr_map_reg_t pau_intr_map; - volatile interrupt_matrix_hp_peri_timeout_intr_map_reg_t hp_peri_timeout_intr_map; - volatile interrupt_matrix_modem_peri_timeout_intr_map_reg_t modem_peri_timeout_intr_map; - volatile interrupt_matrix_hp_apm_m0_intr_map_reg_t hp_apm_m0_intr_map; - volatile interrupt_matrix_hp_apm_m1_intr_map_reg_t hp_apm_m1_intr_map; - volatile interrupt_matrix_hp_apm_m2_intr_map_reg_t hp_apm_m2_intr_map; - volatile interrupt_matrix_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map; - volatile interrupt_matrix_mspi_intr_map_reg_t mspi_intr_map; - volatile interrupt_matrix_i2s1_intr_map_reg_t i2s1_intr_map; - volatile interrupt_matrix_uart0_intr_map_reg_t uart0_intr_map; - volatile interrupt_matrix_uart1_intr_map_reg_t uart1_intr_map; - volatile interrupt_matrix_uart2_intr_map_reg_t uart2_intr_map; - volatile interrupt_matrix_ledc_intr_map_reg_t ledc_intr_map; - volatile interrupt_matrix_usb_intr_map_reg_t usb_intr_map; - volatile interrupt_matrix_i2c_ext0_intr_map_reg_t i2c_ext0_intr_map; - volatile interrupt_matrix_tg0_t0_intr_map_reg_t tg0_t0_intr_map; - volatile interrupt_matrix_tg0_t1_intr_map_reg_t tg0_t1_intr_map; - volatile interrupt_matrix_tg0_wdt_intr_map_reg_t tg0_wdt_intr_map; - volatile interrupt_matrix_tg1_t0_intr_map_reg_t tg1_t0_intr_map; - volatile interrupt_matrix_tg1_t1_intr_map_reg_t tg1_t1_intr_map; - volatile interrupt_matrix_tg1_wdt_intr_map_reg_t tg1_wdt_intr_map; - volatile interrupt_matrix_systimer_target0_intr_map_reg_t systimer_target0_intr_map; - volatile interrupt_matrix_systimer_target1_intr_map_reg_t systimer_target1_intr_map; - volatile interrupt_matrix_systimer_target2_intr_map_reg_t systimer_target2_intr_map; - volatile interrupt_matrix_apb_adc_intr_map_reg_t apb_adc_intr_map; - volatile interrupt_matrix_dma_in_ch0_intr_map_reg_t dma_in_ch0_intr_map; - volatile interrupt_matrix_dma_in_ch1_intr_map_reg_t dma_in_ch1_intr_map; - volatile interrupt_matrix_dma_out_ch0_intr_map_reg_t dma_out_ch0_intr_map; - volatile interrupt_matrix_dma_out_ch1_intr_map_reg_t dma_out_ch1_intr_map; - volatile interrupt_matrix_gpspi2_intr_map_reg_t gpspi2_intr_map; - volatile interrupt_matrix_sha_intr_map_reg_t sha_intr_map; - volatile interrupt_matrix_ecc_intr_map_reg_t ecc_intr_map; - volatile interrupt_matrix_ecdsa_intr_map_reg_t ecdsa_intr_map; - volatile interrupt_matrix_int_status_0_reg_t int_status_0; - volatile interrupt_matrix_int_status_1_reg_t int_status_1; - volatile interrupt_matrix_clock_gate_reg_t clock_gate; - uint32_t reserved_104[446]; - volatile interrupt_matrix_interrupt_date_reg_t interrupt_date; + volatile interrupt_core0_wifi_mac_intr_map_reg_t core0_wifi_mac_intr_map; + volatile interrupt_core0_wifi_mac_nmi_map_reg_t core0_wifi_mac_nmi_map; + volatile interrupt_core0_wifi_pwr_intr_map_reg_t core0_wifi_pwr_intr_map; + volatile interrupt_core0_wifi_bb_intr_map_reg_t core0_wifi_bb_intr_map; + volatile interrupt_core0_bt_mac_intr_map_reg_t core0_bt_mac_intr_map; + volatile interrupt_core0_bt_bb_intr_map_reg_t core0_bt_bb_intr_map; + volatile interrupt_core0_bt_bb_nmi_map_reg_t core0_bt_bb_nmi_map; + volatile interrupt_core0_lp_timer_intr_map_reg_t core0_lp_timer_intr_map; + volatile interrupt_core0_coex_intr_map_reg_t core0_coex_intr_map; + volatile interrupt_core0_ble_timer_intr_map_reg_t core0_ble_timer_intr_map; + volatile interrupt_core0_ble_sec_intr_map_reg_t core0_ble_sec_intr_map; + volatile interrupt_core0_i2c_mst_intr_map_reg_t core0_i2c_mst_intr_map; + volatile interrupt_core0_zb_mac_intr_map_reg_t core0_zb_mac_intr_map; + volatile interrupt_core0_pmu_intr_map_reg_t core0_pmu_intr_map; + volatile interrupt_core0_efuse_intr_map_reg_t core0_efuse_intr_map; + volatile interrupt_core0_lp_rtc_timer_intr_map_reg_t core0_lp_rtc_timer_intr_map; + volatile interrupt_core0_lp_wdt_intr_map_reg_t core0_lp_wdt_intr_map; + volatile interrupt_core0_lp_peri_timeout_intr_map_reg_t core0_lp_peri_timeout_intr_map; + volatile interrupt_core0_lp_apm_m0_intr_map_reg_t core0_lp_apm_m0_intr_map; + volatile interrupt_core0_cpu_intr_from_cpu_0_map_reg_t core0_cpu_intr_from_cpu_0_map; + volatile interrupt_core0_cpu_intr_from_cpu_1_map_reg_t core0_cpu_intr_from_cpu_1_map; + volatile interrupt_core0_cpu_intr_from_cpu_2_map_reg_t core0_cpu_intr_from_cpu_2_map; + volatile interrupt_core0_cpu_intr_from_cpu_3_map_reg_t core0_cpu_intr_from_cpu_3_map; + volatile interrupt_core0_assist_debug_intr_map_reg_t core0_assist_debug_intr_map; + volatile interrupt_core0_trace_intr_map_reg_t core0_trace_intr_map; + volatile interrupt_core0_cache_intr_map_reg_t core0_cache_intr_map; + volatile interrupt_core0_cpu_peri_timeout_intr_map_reg_t core0_cpu_peri_timeout_intr_map; + volatile interrupt_core0_gpio_interrupt_pro_map_reg_t core0_gpio_interrupt_pro_map; + volatile interrupt_core0_gpio_interrupt_ext_map_reg_t core0_gpio_interrupt_ext_map; + volatile interrupt_core0_pau_intr_map_reg_t core0_pau_intr_map; + volatile interrupt_core0_hp_peri_timeout_intr_map_reg_t core0_hp_peri_timeout_intr_map; + volatile interrupt_core0_modem_peri_timeout_intr_map_reg_t core0_modem_peri_timeout_intr_map; + volatile interrupt_core0_hp_apm_m0_intr_map_reg_t core0_hp_apm_m0_intr_map; + volatile interrupt_core0_hp_apm_m1_intr_map_reg_t core0_hp_apm_m1_intr_map; + volatile interrupt_core0_hp_apm_m2_intr_map_reg_t core0_hp_apm_m2_intr_map; + volatile interrupt_core0_hp_apm_m3_intr_map_reg_t core0_hp_apm_m3_intr_map; + volatile interrupt_core0_cpu_apm_m0_intr_map_reg_t core0_cpu_apm_m0_intr_map; + volatile interrupt_core0_cpu_apm_m1_intr_map_reg_t core0_cpu_apm_m1_intr_map; + volatile interrupt_core0_mspi_intr_map_reg_t core0_mspi_intr_map; + volatile interrupt_core0_i2s1_intr_map_reg_t core0_i2s1_intr_map; + volatile interrupt_core0_uart0_intr_map_reg_t core0_uart0_intr_map; + volatile interrupt_core0_uart1_intr_map_reg_t core0_uart1_intr_map; + volatile interrupt_core0_uart2_intr_map_reg_t core0_uart2_intr_map; + volatile interrupt_core0_ledc_intr_map_reg_t core0_ledc_intr_map; + volatile interrupt_core0_usb_intr_map_reg_t core0_usb_intr_map; + volatile interrupt_core0_i2c_ext0_intr_map_reg_t core0_i2c_ext0_intr_map; + volatile interrupt_core0_tg0_t0_intr_map_reg_t core0_tg0_t0_intr_map; + volatile interrupt_core0_tg0_t1_intr_map_reg_t core0_tg0_t1_intr_map; + volatile interrupt_core0_tg0_wdt_intr_map_reg_t core0_tg0_wdt_intr_map; + volatile interrupt_core0_tg1_t0_intr_map_reg_t core0_tg1_t0_intr_map; + volatile interrupt_core0_tg1_t1_intr_map_reg_t core0_tg1_t1_intr_map; + volatile interrupt_core0_tg1_wdt_intr_map_reg_t core0_tg1_wdt_intr_map; + volatile interrupt_core0_systimer_target0_intr_map_reg_t core0_systimer_target0_intr_map; + volatile interrupt_core0_systimer_target1_intr_map_reg_t core0_systimer_target1_intr_map; + volatile interrupt_core0_systimer_target2_intr_map_reg_t core0_systimer_target2_intr_map; + volatile interrupt_core0_apb_adc_intr_map_reg_t core0_apb_adc_intr_map; + volatile interrupt_core0_slc0_intr_map_reg_t core0_slc0_intr_map; + volatile interrupt_core0_slc1_intr_map_reg_t core0_slc1_intr_map; + volatile interrupt_core0_dma_in_ch0_intr_map_reg_t core0_dma_in_ch0_intr_map; + volatile interrupt_core0_dma_in_ch1_intr_map_reg_t core0_dma_in_ch1_intr_map; + volatile interrupt_core0_dma_out_ch0_intr_map_reg_t core0_dma_out_ch0_intr_map; + volatile interrupt_core0_dma_out_ch1_intr_map_reg_t core0_dma_out_ch1_intr_map; + volatile interrupt_core0_gpspi2_intr_map_reg_t core0_gpspi2_intr_map; + volatile interrupt_core0_sha_intr_map_reg_t core0_sha_intr_map; + volatile interrupt_core0_ecc_intr_map_reg_t core0_ecc_intr_map; + volatile interrupt_core0_ecdsa_intr_map_reg_t core0_ecdsa_intr_map; + volatile interrupt_core0_int_status_reg_0_reg_t core0_int_status_reg_0; + volatile interrupt_core0_int_status_reg_1_reg_t core0_int_status_reg_1; + volatile interrupt_core0_int_status_reg_2_reg_t core0_int_status_reg_2; + volatile interrupt_core0_src_pass_in_sec_status_0_reg_t core0_src_pass_in_sec_status_0; + volatile interrupt_core0_src_pass_in_sec_status_1_reg_t core0_src_pass_in_sec_status_1; + volatile interrupt_core0_src_pass_in_sec_status_2_reg_t core0_src_pass_in_sec_status_2; + volatile interrupt_core0_sig_idx_assert_in_sec_reg_t core0_sig_idx_assert_in_sec; + volatile interrupt_core0_secure_status_reg_t core0_secure_status; + volatile interrupt_core0_clock_gate_reg_t core0_clock_gate; + uint32_t reserved_12c[436]; + volatile interrupt_core0_interrupt_date_reg_t core0_interrupt_date; } interrupt_matrix_dev_t; extern interrupt_matrix_dev_t INTMTX; diff --git a/components/soc/esp32c61/register/soc/io_mux_reg.h b/components/soc/esp32c61/register/soc/io_mux_reg.h index 78c9face38..0843609299 100644 --- a/components/soc/esp32c61/register/soc/io_mux_reg.h +++ b/components/soc/esp32c61/register/soc/io_mux_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -73,59 +73,38 @@ extern "C" { #define FILTER_EN_V 1 #define FILTER_EN_S 15 -#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) -#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) -#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE) -#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE) -#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU) -#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU) -#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD) -#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD) -#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) -#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) +#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U +#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_XTAL_32K_N_U +#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U +#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_MTMS_U +#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTDI_U +#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTCK_U +#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_MTDO_U +#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U +#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U +#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U +#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_U0RXD_U +#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_U0TXD_U +#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U +#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_GPIO13_U +#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_SPICS1_U +#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_SPICS0_U +#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_SPIQ_U +#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_SPIWP_U +#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_VDD_SPI_U +#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_SPIHD_U +#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_SPICLK_U +#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_SPID_U +#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_SDIO_DATA2_U +#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_SDIO_DATA3_U +#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_GPIO24_U +#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_SDIO_CMD_U +#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_SDIO_CLK_U +#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_SDIO_DATA0_U +#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_SDIO_DATA1_U +#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_GPIO29_U -#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) -#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) -#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); -#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) -#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) -#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) -#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) -#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) -#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN) -#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN) - -#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_P -#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_N -#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_U_PAD_GPIO2 -#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_U_PAD_MTMS -#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_U_PAD_MTDI -#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_U_PAD_MTCK -#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_U_PAD_MTDO -#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_U_PAD_GPIO7 -#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_U_PAD_GPIO8 -#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_U_PAD_GPIO9 -#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_U_PAD_U0RXD -#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_U_PAD_U0TXD -#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_U_PAD_GPIO12 -#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_U_PAD_GPIO13 -#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_U_PAD_SPICS1 -#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_U_PAD_SPICS0 -#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_U_PAD_SPIQ -#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_U_PAD_SPIWP -#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_U_PAD_VDD_SPI -#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U_PAD_SPIHD -#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U_PAD_SPICLK -#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U_PAD_SPID -#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U_PAD_GPIO22 -#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U_PAD_GPIO23 -#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U_PAD_GPIO24 - -#define PIN_FUNC_GPIO 1 - -#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) -#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) -#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) +#define PIN_FUNC_GPIO 1 #define USB_INT_PHY0_DM_GPIO_NUM 12 #define USB_INT_PHY0_DP_GPIO_NUM 13 @@ -141,111 +120,136 @@ extern "C" { // definitions above are inherited from previous version of code, should double check // definitions below are generated from pin_txt.csv -#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_P (REG_IO_MUX_BASE + 0x0) -#define FUNC_XTAL_32K_P_GPIO0 1 -#define FUNC_XTAL_32K_P_GPIO0_0 0 +#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_XTAL_32K_P_GPIO0_0 0 +#define FUNC_XTAL_32K_P_GPIO0 1 -#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_N (REG_IO_MUX_BASE + 0x4) -#define FUNC_XTAL_32K_N_GPIO1 1 -#define FUNC_XTAL_32K_N_GPIO1_0 0 +#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_XTAL_32K_N_GPIO1_0 0 +#define FUNC_XTAL_32K_N_GPIO1 1 -#define PERIPHS_IO_MUX_U_PAD_GPIO2 (REG_IO_MUX_BASE + 0x8) -#define FUNC_GPIO2_FSPIQ 2 -#define FUNC_GPIO2_GPIO2 1 -#define FUNC_GPIO2_GPIO2_0 0 +#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO2_GPIO2_0 0 +#define FUNC_GPIO2_GPIO2 1 +#define FUNC_GPIO2_FSPIQ 2 -#define PERIPHS_IO_MUX_U_PAD_MTMS (REG_IO_MUX_BASE + 0xC) -#define FUNC_MTMS_FSPIHD 2 -#define FUNC_MTMS_GPIO3 1 -#define FUNC_MTMS_MTMS 0 +// Strapping: Boot Mode select 0/SDIO input strapping +#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_MTMS_MTMS 0 +#define FUNC_MTMS_GPIO3 1 +#define FUNC_MTMS_FSPIHD 2 -#define PERIPHS_IO_MUX_U_PAD_MTDI (REG_IO_MUX_BASE + 0x10) -#define FUNC_MTDI_FSPIWP 2 -#define FUNC_MTDI_GPIO4 1 -#define FUNC_MTDI_MTDI 0 +// Strapping: Boot Mode select 1/SDIO output strapping +#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_MTDI_MTDI 0 +#define FUNC_MTDI_GPIO4 1 +#define FUNC_MTDI_FSPIWP 2 -#define PERIPHS_IO_MUX_U_PAD_MTCK (REG_IO_MUX_BASE + 0x14) -#define FUNC_MTCK_GPIO5 1 -#define FUNC_MTCK_MTCK 0 +#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_MTCK_MTCK 0 +#define FUNC_MTCK_GPIO5 1 -#define PERIPHS_IO_MUX_U_PAD_MTDO (REG_IO_MUX_BASE + 0x18) -#define FUNC_MTDO_FSPICLK 2 -#define FUNC_MTDO_GPIO6 1 -#define FUNC_MTDO_MTDO 0 +#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_MTDO_MTDO 0 +#define FUNC_MTDO_GPIO6 1 +#define FUNC_MTDO_FSPICLK 2 -#define PERIPHS_IO_MUX_U_PAD_GPIO7 (REG_IO_MUX_BASE + 0x1C) -#define FUNC_GPIO7_FSPID 2 -#define FUNC_GPIO7_GPIO7 1 -#define FUNC_GPIO7_GPIO7_0 0 +// Strapping: JTAG select +#define PERIPHS_IO_MUX_GPIO7_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO7_GPIO7_0 0 +#define FUNC_GPIO7_GPIO7 1 +#define FUNC_GPIO7_FSPID 2 -#define PERIPHS_IO_MUX_U_PAD_GPIO8 (REG_IO_MUX_BASE + 0x20) -#define FUNC_GPIO8_FSPICS0 2 -#define FUNC_GPIO8_GPIO8 1 -#define FUNC_GPIO8_GPIO8_0 0 +// Strapping: Boot Mode select 2 +#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO8_GPIO8_0 0 +#define FUNC_GPIO8_GPIO8 1 +#define FUNC_GPIO8_FSPICS0 2 -#define PERIPHS_IO_MUX_U_PAD_GPIO9 (REG_IO_MUX_BASE + 0x24) -#define FUNC_GPIO9_GPIO9 1 -#define FUNC_GPIO9_GPIO9_0 0 +// Strapping: Boot Mode select 3 +#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO9_GPIO9_0 0 +#define FUNC_GPIO9_GPIO9 1 -#define PERIPHS_IO_MUX_U_PAD_U0RXD (REG_IO_MUX_BASE + 0x28) -#define FUNC_U0RXD_GPIO10 1 -#define FUNC_U0RXD_U0RXD 0 +#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_U0RXD_U0RXD 0 +#define FUNC_U0RXD_GPIO10 1 -#define PERIPHS_IO_MUX_U_PAD_U0TXD (REG_IO_MUX_BASE + 0x2C) -#define FUNC_U0TXD_GPIO11 1 -#define FUNC_U0TXD_U0TXD 0 +#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_U0TXD_U0TXD 0 +#define FUNC_U0TXD_GPIO11 1 -#define PERIPHS_IO_MUX_U_PAD_GPIO12 (REG_IO_MUX_BASE + 0x30) -#define FUNC_GPIO12_GPIO12 1 -#define FUNC_GPIO12_GPIO12_0 0 +#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO12_GPIO12_0 0 +#define FUNC_GPIO12_GPIO12 1 -#define PERIPHS_IO_MUX_U_PAD_GPIO13 (REG_IO_MUX_BASE + 0x34) -#define FUNC_GPIO13_GPIO13 1 -#define FUNC_GPIO13_GPIO13_0 0 +#define PERIPHS_IO_MUX_GPIO13_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO13_GPIO13_0 0 +#define FUNC_GPIO13_GPIO13 1 -#define PERIPHS_IO_MUX_U_PAD_SPICS1 (REG_IO_MUX_BASE + 0x38) -#define FUNC_SPICS1_GPIO14 1 -#define FUNC_SPICS1_SPICS1 0 +#define PERIPHS_IO_MUX_SPICS1_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_SPICS1_SPICS1 0 +#define FUNC_SPICS1_GPIO14 1 -#define PERIPHS_IO_MUX_U_PAD_SPICS0 (REG_IO_MUX_BASE + 0x3C) -#define FUNC_SPICS0_GPIO15 1 -#define FUNC_SPICS0_SPICS0 0 +#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_SPICS0_SPICS0 0 +#define FUNC_SPICS0_GPIO15 1 -#define PERIPHS_IO_MUX_U_PAD_SPIQ (REG_IO_MUX_BASE + 0x40) -#define FUNC_SPIQ_GPIO16 1 -#define FUNC_SPIQ_SPIQ 0 +#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_SPIQ_SPIQ 0 +#define FUNC_SPIQ_GPIO16 1 -#define PERIPHS_IO_MUX_U_PAD_SPIWP (REG_IO_MUX_BASE + 0x44) -#define FUNC_SPIWP_GPIO17 1 -#define FUNC_SPIWP_SPIWP 0 +#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_SPIWP_SPIWP 0 +#define FUNC_SPIWP_GPIO17 1 -#define PERIPHS_IO_MUX_U_PAD_VDD_SPI (REG_IO_MUX_BASE + 0x48) -#define FUNC_VDD_SPI_GPIO18 1 -#define FUNC_VDD_SPI_GPIO18_0 0 +#define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_VDD_SPI_GPIO18_0 0 +#define FUNC_VDD_SPI_GPIO18 1 -#define PERIPHS_IO_MUX_U_PAD_SPIHD (REG_IO_MUX_BASE + 0x4C) -#define FUNC_SPIHD_GPIO19 1 -#define FUNC_SPIHD_SPIHD 0 +#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_SPIHD_SPIHD 0 +#define FUNC_SPIHD_GPIO19 1 -#define PERIPHS_IO_MUX_U_PAD_SPICLK (REG_IO_MUX_BASE + 0x50) -#define FUNC_SPICLK_GPIO20 1 -#define FUNC_SPICLK_SPICLK 0 +#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_SPICLK_SPICLK 0 +#define FUNC_SPICLK_GPIO20 1 -#define PERIPHS_IO_MUX_U_PAD_SPID (REG_IO_MUX_BASE + 0x54) -#define FUNC_SPID_GPIO21 1 -#define FUNC_SPID_SPID 0 +#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_SPID_SPID 0 +#define FUNC_SPID_GPIO21 1 -#define PERIPHS_IO_MUX_U_PAD_GPIO22 (REG_IO_MUX_BASE + 0x58) -#define FUNC_GPIO22_GPIO22 1 -#define FUNC_GPIO22_GPIO22_0 0 +#define PERIPHS_IO_MUX_SDIO_DATA2_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_SDIO_DATA2_SDIO_DATA2 0 +#define FUNC_SDIO_DATA2_GPIO22 1 -#define PERIPHS_IO_MUX_U_PAD_GPIO23 (REG_IO_MUX_BASE + 0x5C) -#define FUNC_GPIO23_GPIO23 1 -#define FUNC_GPIO23_GPIO23_0 0 +#define PERIPHS_IO_MUX_SDIO_DATA3_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_SDIO_DATA3_SDIO_DATA3 0 +#define FUNC_SDIO_DATA3_GPIO23 1 -#define PERIPHS_IO_MUX_U_PAD_GPIO24 (REG_IO_MUX_BASE + 0x60) -#define FUNC_GPIO24_GPIO24 1 -#define FUNC_GPIO24_GPIO24_0 0 +#define PERIPHS_IO_MUX_GPIO24_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO24_GPIO24_0 0 +#define FUNC_GPIO24_GPIO24 1 + +#define PERIPHS_IO_MUX_SDIO_CMD_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_SDIO_CMD_SDIO_CMD 0 +#define FUNC_SDIO_CMD_GPIO25 1 + +#define PERIPHS_IO_MUX_SDIO_CLK_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_SDIO_CLK_SDIO_CLK 0 +#define FUNC_SDIO_CLK_GPIO26 1 + +#define PERIPHS_IO_MUX_SDIO_DATA0_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_SDIO_DATA0_SDIO_DATA0 0 +#define FUNC_SDIO_DATA0_GPIO27 1 + +#define PERIPHS_IO_MUX_SDIO_DATA1_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_SDIO_DATA1_SDIO_DATA1 0 +#define FUNC_SDIO_DATA1_GPIO28 1 + +#define PERIPHS_IO_MUX_GPIO29_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_GPIO29_GPIO29_0 0 +#define FUNC_GPIO29_GPIO29 1 /** IO_MUX_DATE_REG register * Version control register diff --git a/components/soc/esp32c61/register/soc/io_mux_struct.h b/components/soc/esp32c61/register/soc/io_mux_struct.h index b4091d4d98..e04f4ba0e0 100644 --- a/components/soc/esp32c61/register/soc/io_mux_struct.h +++ b/components/soc/esp32c61/register/soc/io_mux_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,100 +10,73 @@ extern "C" { #endif -/** Group: Configuration Registers */ +/** Group: Configure Registers */ /** Type of gpion register - * IO MUX configuration register for GPIOn + * IO_MUX Configure Register */ typedef union { struct { /** gpion_mcu_oe : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the output of GPIOn in sleep mode. - * 0: Disable\\ - * 1: Enable\\ + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. */ uint32_t gpion_mcu_oe:1; /** gpion_slp_sel : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enter sleep mode for GPIOn.\\ - * 0: Not enter\\ - * 1: Enter\\ + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. */ uint32_t gpion_slp_sel:1; /** gpion_mcu_wpd : R/W; bitpos: [2]; default: 0; - * Configure whether or not to enable pull-down resistor of GPIOn in sleep mode.\\ - * 0: Disable\\ - * 1: Enable\\ + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. */ uint32_t gpion_mcu_wpd:1; /** gpion_mcu_wpu : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable pull-up resistor of GPIOn during sleep mode. \\ - * 0: Disable\\ - * 1: Enable\\ + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. */ uint32_t gpion_mcu_wpu:1; /** gpion_mcu_ie : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the input of GPIOn during sleep mode.\\ - * 0: Disable\\ - * 1: Enable\\ + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. */ uint32_t gpion_mcu_ie:1; /** gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * Configures the drive strength of GPIOn during sleep mode. \\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad during sleep mode. */ uint32_t gpion_mcu_drv:2; /** gpion_fun_wpd : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable pull-down resistor of GPIOn.\\ - * 0: Disable\\ - * 1: Enable\\ + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. */ uint32_t gpion_fun_wpd:1; /** gpion_fun_wpu : R/W; bitpos: [8]; default: 0; - * Configures whether or not enable pull-up resistor of GPIOn.\\ - * 0: Disable\\ - * 1: Enable\\ + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. */ uint32_t gpion_fun_wpu:1; /** gpion_fun_ie : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable input of GPIOn.\\ - * 0: Disable\\ - * 1: Enable\\ + * Input enable of the pad. 1: input enabled. 0: input disabled. */ uint32_t gpion_fun_ie:1; /** gpion_fun_drv : R/W; bitpos: [11:10]; default: 2; - * Configures the drive strength of GPIOn. \\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad. */ uint32_t gpion_fun_drv:2; /** gpion_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * Configures to select IO MUX function for this signal. \\ - * 0: Select Function 0\\ - * 1: Select Function 1\\ - * ......\\ + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. */ uint32_t gpion_mcu_sel:3; /** gpion_filter_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable filter for pin input signals.\\ - * 0: Disable\\ - * 1: Enable\\ + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. */ uint32_t gpion_filter_en:1; /** gpion_hys_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the hysteresis function of the pin when - * IO_MUX_GPIOn_HYS_SEL is set to 1.\\ - * 0: Disable\\ - * 1: Enable\\ + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. */ uint32_t gpion_hys_en:1; /** gpion_hys_sel : R/W; bitpos: [17]; default: 0; - * Configures to choose the signal for enabling the hysteresis function for GPIOn. \\ - * 0: Choose the output enable signal of eFuse, there is no efuse bit for it, should never set to 0\\ - * 1: Choose the output enable signal of IO_MUX_GPIOn_HYS_EN, always set to 1\\ + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling signal from slftware. 0: Select enabling signal from efuse hardware. */ uint32_t gpion_hys_sel:1; uint32_t reserved_18:14; @@ -111,14 +84,12 @@ typedef union { uint32_t val; } io_mux_gpion_reg_t; - -/** Group: Version Register */ /** Type of date register - * Version control register + * IO_MUX Version Control Register */ typedef union { struct { - /** reg_date : R/W; bitpos: [27:0]; default: 36774288; + /** reg_date : R/W; bitpos: [27:0]; default: 37823072; * Version control register */ uint32_t reg_date:28; @@ -129,8 +100,8 @@ typedef union { typedef struct { - volatile io_mux_gpion_reg_t gpion[25]; - uint32_t reserved_064[102]; + volatile io_mux_gpion_reg_t gpion[30]; + uint32_t reserved_078[97]; volatile io_mux_date_reg_t date; } io_mux_dev_t; diff --git a/components/soc/esp32c61/register/soc/lp_aon_reg.h b/components/soc/esp32c61/register/soc/lp_aon_reg.h index 7ed2a522c4..5979338227 100644 --- a/components/soc/esp32c61/register/soc/lp_aon_reg.h +++ b/components/soc/esp32c61/register/soc/lp_aon_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -290,31 +290,17 @@ extern "C" { #define LP_AON_USB_RESET_DISABLE_V 0x00000001U #define LP_AON_USB_RESET_DISABLE_S 31 -/** LP_AON_LPBUS_REG register +/** LP_AON_SDIO_ACTIVE_REG register * need_des */ -#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48) -/** LP_AON_FAST_MEM_WPULSE : R/W; bitpos: [18:16]; default: 0; - * This field controls fast memory WPULSE parameter. +#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c) +/** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10; + * need_des */ -#define LP_AON_FAST_MEM_WPULSE 0x00000007U -#define LP_AON_FAST_MEM_WPULSE_M (LP_AON_FAST_MEM_WPULSE_V << LP_AON_FAST_MEM_WPULSE_S) -#define LP_AON_FAST_MEM_WPULSE_V 0x00000007U -#define LP_AON_FAST_MEM_WPULSE_S 16 -/** LP_AON_FAST_MEM_WA : R/W; bitpos: [21:19]; default: 4; - * This field controls fast memory WA parameter. - */ -#define LP_AON_FAST_MEM_WA 0x00000007U -#define LP_AON_FAST_MEM_WA_M (LP_AON_FAST_MEM_WA_V << LP_AON_FAST_MEM_WA_S) -#define LP_AON_FAST_MEM_WA_V 0x00000007U -#define LP_AON_FAST_MEM_WA_S 19 -/** LP_AON_FAST_MEM_RA : R/W; bitpos: [23:22]; default: 0; - * This field controls fast memory RA parameter. - */ -#define LP_AON_FAST_MEM_RA 0x00000003U -#define LP_AON_FAST_MEM_RA_M (LP_AON_FAST_MEM_RA_V << LP_AON_FAST_MEM_RA_S) -#define LP_AON_FAST_MEM_RA_V 0x00000003U -#define LP_AON_FAST_MEM_RA_S 22 +#define LP_AON_SDIO_ACT_DNUM 0x000003FFU +#define LP_AON_SDIO_ACT_DNUM_M (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S) +#define LP_AON_SDIO_ACT_DNUM_V 0x000003FFU +#define LP_AON_SDIO_ACT_DNUM_S 22 /** LP_AON_LPCORE_REG register * need_des @@ -439,7 +425,7 @@ extern "C" { * need_des */ #define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) -/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 36766272; +/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 37823232; * need_des */ #define LP_AON_DATE 0x7FFFFFFFU diff --git a/components/soc/esp32c61/register/soc/lp_aon_struct.h b/components/soc/esp32c61/register/soc/lp_aon_struct.h index 96660def85..77a93971bc 100644 --- a/components/soc/esp32c61/register/soc/lp_aon_struct.h +++ b/components/soc/esp32c61/register/soc/lp_aon_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -287,28 +287,19 @@ typedef union { uint32_t val; } lp_aon_usb_reg_t; -/** Type of lpbus register +/** Type of sdio_active register * need_des */ typedef union { struct { - uint32_t reserved_0:16; - /** fast_mem_wpulse : R/W; bitpos: [18:16]; default: 0; - * This field controls fast memory WPULSE parameter. + uint32_t reserved_0:22; + /** sdio_act_dnum : R/W; bitpos: [31:22]; default: 10; + * need_des */ - uint32_t fast_mem_wpulse:3; - /** fast_mem_wa : R/W; bitpos: [21:19]; default: 4; - * This field controls fast memory WA parameter. - */ - uint32_t fast_mem_wa:3; - /** fast_mem_ra : R/W; bitpos: [23:22]; default: 0; - * This field controls fast memory RA parameter. - */ - uint32_t fast_mem_ra:2; - uint32_t reserved_24:8; + uint32_t sdio_act_dnum:10; }; uint32_t val; -} lp_aon_lpbus_reg_t; +} lp_aon_sdio_active_reg_t; /** Type of lpcore register * need_des @@ -405,7 +396,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [30:0]; default: 36766272; + /** date : R/W; bitpos: [30:0]; default: 37823232; * need_des */ uint32_t date:31; @@ -465,8 +456,8 @@ typedef struct { volatile lp_aon_io_mux_reg_t io_mux; volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl; volatile lp_aon_usb_reg_t usb; - volatile lp_aon_lpbus_reg_t lpbus; - uint32_t reserved_04c; + uint32_t reserved_048; + volatile lp_aon_sdio_active_reg_t sdio_active; volatile lp_aon_lpcore_reg_t lpcore; volatile lp_aon_sar_cct_reg_t sar_cct; volatile lp_aon_modem_bus_reg_t modem_bus; diff --git a/components/soc/esp32c61/register/soc/pcr_reg.h b/components/soc/esp32c61/register/soc/pcr_reg.h index feedd3ae52..c6d3a60ba9 100644 --- a/components/soc/esp32c61/register/soc/pcr_reg.h +++ b/components/soc/esp32c61/register/soc/pcr_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,7 +23,7 @@ extern "C" { #define PCR_UART0_CLK_EN_V 0x00000001U #define PCR_UART0_CLK_EN_S 0 /** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart0 module + * Set 1 to reset uart0 module */ #define PCR_UART0_RST_EN (BIT(1)) #define PCR_UART0_RST_EN_M (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S) @@ -63,10 +63,10 @@ extern "C" { #define PCR_UART0_SCLK_DIV_NUM_V 0x000000FFU #define PCR_UART0_SCLK_DIV_NUM_S 12 /** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_UART0_SCLK_SEL 0x00000003U #define PCR_UART0_SCLK_SEL_M (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S) @@ -111,7 +111,7 @@ extern "C" { #define PCR_UART1_CLK_EN_V 0x00000001U #define PCR_UART1_CLK_EN_S 0 /** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart1 module + * Set 1 to reset uart1 module */ #define PCR_UART1_RST_EN (BIT(1)) #define PCR_UART1_RST_EN_M (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S) @@ -151,10 +151,10 @@ extern "C" { #define PCR_UART1_SCLK_DIV_NUM_V 0x000000FFU #define PCR_UART1_SCLK_DIV_NUM_S 12 /** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_UART1_SCLK_SEL 0x00000003U #define PCR_UART1_SCLK_SEL_M (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S) @@ -199,7 +199,7 @@ extern "C" { #define PCR_UART2_CLK_EN_V 0x00000001U #define PCR_UART2_CLK_EN_S 0 /** PCR_UART2_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart2 module + * Set 1 to reset uart2 module */ #define PCR_UART2_RST_EN (BIT(1)) #define PCR_UART2_RST_EN_M (PCR_UART2_RST_EN_V << PCR_UART2_RST_EN_S) @@ -239,10 +239,10 @@ extern "C" { #define PCR_UART2_SCLK_DIV_NUM_V 0x000000FFU #define PCR_UART2_SCLK_DIV_NUM_S 12 /** PCR_UART2_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART2.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART2. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_UART2_SCLK_SEL 0x00000003U #define PCR_UART2_SCLK_SEL_M (PCR_UART2_SCLK_SEL_V << PCR_UART2_SCLK_SEL_S) @@ -287,7 +287,7 @@ extern "C" { #define PCR_MSPI_CLK_EN_V 0x00000001U #define PCR_MSPI_CLK_EN_S 0 /** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset mspi module + * Set 1 to reset mspi module */ #define PCR_MSPI_RST_EN (BIT(1)) #define PCR_MSPI_RST_EN_M (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S) @@ -322,10 +322,10 @@ extern "C" { #define PCR_MSPI_FAST_DIV_NUM_V 0x000000FFU #define PCR_MSPI_FAST_DIV_NUM_S 0 /** PCR_MSPI_FUNC_CLK_SEL : R/W; bitpos: [9:8]; default: 0; - * Configures the clock source for MSPI.\\ - * 0(default): XTAL_CLK\\ - * 1 RC_FAST_CLK\\ - * 2: PLL_F480M_CLK\\ + * Configures the clock source for MSPI. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK */ #define PCR_MSPI_FUNC_CLK_SEL 0x00000003U #define PCR_MSPI_FUNC_CLK_SEL_M (PCR_MSPI_FUNC_CLK_SEL_V << PCR_MSPI_FUNC_CLK_SEL_S) @@ -339,7 +339,7 @@ extern "C" { #define PCR_MSPI_FUNC_CLK_EN_V 0x00000001U #define PCR_MSPI_FUNC_CLK_EN_S 10 /** PCR_MSPI_AXI_RST_EN : R/W; bitpos: [11]; default: 0; - * Set 0 to reset axi_clock domain of mspi module + * Set 1 to reset axi_clock domain of mspi module */ #define PCR_MSPI_AXI_RST_EN (BIT(11)) #define PCR_MSPI_AXI_RST_EN_M (PCR_MSPI_AXI_RST_EN_V << PCR_MSPI_AXI_RST_EN_S) @@ -358,7 +358,7 @@ extern "C" { #define PCR_I2C_CLK_EN_V 0x00000001U #define PCR_I2C_CLK_EN_S 0 /** PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2c module + * Set 1 to reset i2c module */ #define PCR_I2C_RST_EN (BIT(1)) #define PCR_I2C_RST_EN_M (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S) @@ -391,9 +391,9 @@ extern "C" { #define PCR_I2C_SCLK_DIV_NUM_V 0x000000FFU #define PCR_I2C_SCLK_DIV_NUM_S 12 /** PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of I2C.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of I2C. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ #define PCR_I2C_SCLK_SEL (BIT(20)) #define PCR_I2C_SCLK_SEL_M (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S) @@ -419,7 +419,7 @@ extern "C" { #define PCR_LEDC_CLK_EN_V 0x00000001U #define PCR_LEDC_CLK_EN_S 0 /** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ledc module + * Set 1 to reset ledc module */ #define PCR_LEDC_RST_EN (BIT(1)) #define PCR_LEDC_RST_EN_M (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S) @@ -438,10 +438,10 @@ extern "C" { */ #define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38) /** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of LEDC.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of LEDC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_LEDC_SCLK_SEL 0x00000003U #define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) @@ -486,7 +486,7 @@ extern "C" { #define PCR_TG0_CLK_EN_V 0x00000001U #define PCR_TG0_CLK_EN_S 0 /** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group0 module + * Set 1 to reset timer_group0 module */ #define PCR_TG0_RST_EN (BIT(1)) #define PCR_TG0_RST_EN_M (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S) @@ -519,10 +519,10 @@ extern "C" { */ #define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x44) /** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of general-purpose timers in Timer Group 0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of general-purpose timers in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_TG0_TIMER_CLK_SEL 0x00000003U #define PCR_TG0_TIMER_CLK_SEL_M (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S) @@ -541,10 +541,10 @@ extern "C" { */ #define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x48) /** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of WDT in Timer Group 0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of WDT in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_TG0_WDT_CLK_SEL 0x00000003U #define PCR_TG0_WDT_CLK_SEL_M (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S) @@ -570,7 +570,7 @@ extern "C" { #define PCR_TG1_CLK_EN_V 0x00000001U #define PCR_TG1_CLK_EN_S 0 /** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 module + * Set 1 to reset timer_group1 module */ #define PCR_TG1_RST_EN (BIT(1)) #define PCR_TG1_RST_EN_M (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S) @@ -603,10 +603,10 @@ extern "C" { */ #define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x50) /** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of general-purpose timers in Timer Group 1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of general-purpose timers in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_TG1_TIMER_CLK_SEL 0x00000003U #define PCR_TG1_TIMER_CLK_SEL_M (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S) @@ -625,10 +625,10 @@ extern "C" { */ #define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x54) /** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of WDT in Timer Group 1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of WDT in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_TG1_WDT_CLK_SEL 0x00000003U #define PCR_TG1_WDT_CLK_SEL_M (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S) @@ -654,7 +654,7 @@ extern "C" { #define PCR_SYSTIMER_CLK_EN_V 0x00000001U #define PCR_SYSTIMER_CLK_EN_S 0 /** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset systimer module + * Set 1 to reset systimer module */ #define PCR_SYSTIMER_RST_EN (BIT(1)) #define PCR_SYSTIMER_RST_EN_M (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S) @@ -673,9 +673,9 @@ extern "C" { */ #define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x5c) /** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of System Timer.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of System Timer. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ #define PCR_SYSTIMER_FUNC_CLK_SEL (BIT(20)) #define PCR_SYSTIMER_FUNC_CLK_SEL_M (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S) @@ -701,7 +701,7 @@ extern "C" { #define PCR_I2S_CLK_EN_V 0x00000001U #define PCR_I2S_CLK_EN_S 0 /** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2s module + * Set 1 to reset i2s module */ #define PCR_I2S_RST_EN (BIT(1)) #define PCR_I2S_RST_EN_M (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S) @@ -737,11 +737,11 @@ extern "C" { #define PCR_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU #define PCR_I2S_TX_CLKM_DIV_NUM_S 12 /** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of I2S TX.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F120M_CLK\\ - * 2: PLL_F160M_CLK\\ - * 3: I2S_MCLK_in\\ + * Configures the clock source of I2S TX. + * 0 (default): XTAL_CLK + * 1: PLL_F120M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in */ #define PCR_I2S_TX_CLKM_SEL 0x00000003U #define PCR_I2S_TX_CLKM_SEL_M (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S) @@ -804,11 +804,11 @@ extern "C" { #define PCR_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU #define PCR_I2S_RX_CLKM_DIV_NUM_S 12 /** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of I2S RX.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F120M_CLK\\ - * 2: PLL_F160M_CLK\\ - * 3: I2S_MCLK_in\\ + * Configures the clock source of I2S RX. + * 0 (default): XTAL_CLK + * 1: PLL_F120M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in */ #define PCR_I2S_RX_CLKM_SEL 0x00000003U #define PCR_I2S_RX_CLKM_SEL_M (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S) @@ -822,9 +822,9 @@ extern "C" { #define PCR_I2S_RX_CLKM_EN_V 0x00000001U #define PCR_I2S_RX_CLKM_EN_S 22 /** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0; - * Configures to select master clock.\\ - * 0 (default): I2S_TX_CLK\\ - * 1: I2S_RX_CLK\\ + * Configures to select master clock. + * 0 (default): I2S_TX_CLK + * 1: I2S_RX_CLK */ #define PCR_I2S_MCLK_SEL (BIT(23)) #define PCR_I2S_MCLK_SEL_M (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S) @@ -880,7 +880,7 @@ extern "C" { #define PCR_SARADC_CLK_EN_V 0x00000001U #define PCR_SARADC_CLK_EN_S 0 /** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset function_register of saradc module + * Set 1 to reset function_register of saradc module */ #define PCR_SARADC_RST_EN (BIT(1)) #define PCR_SARADC_RST_EN_M (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S) @@ -894,7 +894,7 @@ extern "C" { #define PCR_SARADC_REG_CLK_EN_V 0x00000001U #define PCR_SARADC_REG_CLK_EN_S 2 /** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0; - * Set 0 to reset apb_register of saradc module + * Set 1 to reset apb_register of saradc module */ #define PCR_SARADC_REG_RST_EN (BIT(3)) #define PCR_SARADC_REG_RST_EN_M (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S) @@ -927,10 +927,10 @@ extern "C" { #define PCR_SARADC_CLKM_DIV_NUM_V 0x000000FFU #define PCR_SARADC_CLKM_DIV_NUM_S 12 /** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of SAR ADC.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of SAR ADC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_SARADC_CLKM_SEL 0x00000003U #define PCR_SARADC_CLKM_SEL_M (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S) @@ -949,9 +949,9 @@ extern "C" { */ #define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x7c) /** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of the temperature sensor.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of the temperature sensor. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ #define PCR_TSENS_CLK_SEL (BIT(20)) #define PCR_TSENS_CLK_SEL_M (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S) @@ -965,7 +965,7 @@ extern "C" { #define PCR_TSENS_CLK_EN_V 0x00000001U #define PCR_TSENS_CLK_EN_S 22 /** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0; - * Set 0 to reset tsens module + * Set 1 to reset tsens module */ #define PCR_TSENS_RST_EN (BIT(23)) #define PCR_TSENS_RST_EN_M (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S) @@ -984,7 +984,7 @@ extern "C" { #define PCR_USB_DEVICE_CLK_EN_V 0x00000001U #define PCR_USB_DEVICE_CLK_EN_S 0 /** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset usb_device module + * Set 1 to reset usb_device module */ #define PCR_USB_DEVICE_RST_EN (BIT(1)) #define PCR_USB_DEVICE_RST_EN_M (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S) @@ -1010,7 +1010,7 @@ extern "C" { #define PCR_INTMTX_CLK_EN_V 0x00000001U #define PCR_INTMTX_CLK_EN_S 0 /** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset intmtx module + * Set 1 to reset intmtx module */ #define PCR_INTMTX_RST_EN (BIT(1)) #define PCR_INTMTX_RST_EN_M (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S) @@ -1076,9 +1076,9 @@ extern "C" { #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 /** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of PVT MONITOR.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F160M_CLK\\ + * Configures the clock source of PVT MONITOR. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK */ #define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) #define PCR_PVT_MONITOR_FUNC_CLK_SEL_M (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S) @@ -1104,7 +1104,7 @@ extern "C" { #define PCR_GDMA_CLK_EN_V 0x00000001U #define PCR_GDMA_CLK_EN_S 0 /** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset gdma module + * Set 1 to reset gdma module */ #define PCR_GDMA_RST_EN (BIT(1)) #define PCR_GDMA_RST_EN_M (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S) @@ -1123,7 +1123,7 @@ extern "C" { #define PCR_SPI2_CLK_EN_V 0x00000001U #define PCR_SPI2_CLK_EN_S 0 /** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset spi2 module + * Set 1 to reset spi2 module */ #define PCR_SPI2_RST_EN (BIT(1)) #define PCR_SPI2_RST_EN_M (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S) @@ -1149,10 +1149,10 @@ extern "C" { #define PCR_SPI2_CLKM_DIV_NUM_V 0x000000FFU #define PCR_SPI2_CLKM_DIV_NUM_S 12 /** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of SPI2.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F160M_CLK\\ - * 2: RC_FAST_CLK\\ + * Configures the clock source of SPI2. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK + * 2: RC_FAST_CLK */ #define PCR_SPI2_CLKM_SEL 0x00000003U #define PCR_SPI2_CLKM_SEL_M (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S) @@ -1178,7 +1178,7 @@ extern "C" { #define PCR_AES_CLK_EN_V 0x00000001U #define PCR_AES_CLK_EN_S 0 /** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset aes module + * Set 1 to reset aes module */ #define PCR_AES_RST_EN (BIT(1)) #define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S) @@ -1204,7 +1204,7 @@ extern "C" { #define PCR_SHA_CLK_EN_V 0x00000001U #define PCR_SHA_CLK_EN_S 0 /** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset sha module + * Set 1 to reset sha module */ #define PCR_SHA_RST_EN (BIT(1)) #define PCR_SHA_RST_EN_M (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S) @@ -1230,7 +1230,7 @@ extern "C" { #define PCR_RSA_CLK_EN_V 0x00000001U #define PCR_RSA_CLK_EN_S 0 /** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset rsa module + * Set 1 to reset rsa module */ #define PCR_RSA_RST_EN (BIT(1)) #define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S) @@ -1282,7 +1282,7 @@ extern "C" { #define PCR_ECC_CLK_EN_V 0x00000001U #define PCR_ECC_CLK_EN_S 0 /** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ecc module + * Set 1 to reset ecc module */ #define PCR_ECC_RST_EN (BIT(1)) #define PCR_ECC_RST_EN_M (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S) @@ -1334,7 +1334,7 @@ extern "C" { #define PCR_DS_CLK_EN_V 0x00000001U #define PCR_DS_CLK_EN_S 0 /** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ds module + * Set 1 to reset ds module */ #define PCR_DS_RST_EN (BIT(1)) #define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S) @@ -1360,7 +1360,7 @@ extern "C" { #define PCR_HMAC_CLK_EN_V 0x00000001U #define PCR_HMAC_CLK_EN_S 0 /** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset hmac module + * Set 1 to reset hmac module */ #define PCR_HMAC_RST_EN (BIT(1)) #define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S) @@ -1386,7 +1386,7 @@ extern "C" { #define PCR_ECDSA_CLK_EN_V 0x00000001U #define PCR_ECDSA_CLK_EN_S 0 /** PCR_ECDSA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ecdsa module + * Set 1 to reset ecdsa module */ #define PCR_ECDSA_RST_EN (BIT(1)) #define PCR_ECDSA_RST_EN_M (PCR_ECDSA_RST_EN_V << PCR_ECDSA_RST_EN_S) @@ -1412,7 +1412,7 @@ extern "C" { #define PCR_IOMUX_CLK_EN_V 0x00000001U #define PCR_IOMUX_CLK_EN_S 0 /** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset iomux module + * Set 1 to reset iomux module */ #define PCR_IOMUX_RST_EN (BIT(1)) #define PCR_IOMUX_RST_EN_M (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S) @@ -1424,10 +1424,10 @@ extern "C" { */ #define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xc4) /** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of IO MUX.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of IO MUX. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_IOMUX_FUNC_CLK_SEL 0x00000003U #define PCR_IOMUX_FUNC_CLK_SEL_M (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S) @@ -1453,7 +1453,7 @@ extern "C" { #define PCR_TCM_MEM_MONITOR_CLK_EN_V 0x00000001U #define PCR_TCM_MEM_MONITOR_CLK_EN_S 0 /** PCR_TCM_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset tcm_mem_monitor module + * Set 1 to reset tcm_mem_monitor module */ #define PCR_TCM_MEM_MONITOR_RST_EN (BIT(1)) #define PCR_TCM_MEM_MONITOR_RST_EN_M (PCR_TCM_MEM_MONITOR_RST_EN_V << PCR_TCM_MEM_MONITOR_RST_EN_S) @@ -1479,7 +1479,7 @@ extern "C" { #define PCR_PSRAM_MEM_MONITOR_CLK_EN_V 0x00000001U #define PCR_PSRAM_MEM_MONITOR_CLK_EN_S 0 /** PCR_PSRAM_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset psram_mem_monitor module + * Set 1 to reset psram_mem_monitor module */ #define PCR_PSRAM_MEM_MONITOR_RST_EN (BIT(1)) #define PCR_PSRAM_MEM_MONITOR_RST_EN_M (PCR_PSRAM_MEM_MONITOR_RST_EN_V << PCR_PSRAM_MEM_MONITOR_RST_EN_S) @@ -1505,7 +1505,7 @@ extern "C" { #define PCR_TRACE_CLK_EN_V 0x00000001U #define PCR_TRACE_CLK_EN_S 0 /** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset trace module + * Set 1 to reset trace module */ #define PCR_TRACE_RST_EN (BIT(1)) #define PCR_TRACE_RST_EN_M (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S) @@ -1524,7 +1524,7 @@ extern "C" { #define PCR_ASSIST_CLK_EN_V 0x00000001U #define PCR_ASSIST_CLK_EN_S 0 /** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset assist module + * Set 1 to reset assist module */ #define PCR_ASSIST_RST_EN (BIT(1)) #define PCR_ASSIST_RST_EN_M (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S) @@ -1543,7 +1543,7 @@ extern "C" { #define PCR_CACHE_CLK_EN_V 0x00000001U #define PCR_CACHE_CLK_EN_S 0 /** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cache module + * Set 1 to reset cache module */ #define PCR_CACHE_RST_EN (BIT(1)) #define PCR_CACHE_RST_EN_M (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S) @@ -1601,14 +1601,14 @@ extern "C" { */ #define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0xe4) /** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cpu_peri timeout module + * Set 1 to reset cpu_peri timeout module */ #define PCR_CPU_TIMEOUT_RST_EN (BIT(1)) #define PCR_CPU_TIMEOUT_RST_EN_M (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S) #define PCR_CPU_TIMEOUT_RST_EN_V 0x00000001U #define PCR_CPU_TIMEOUT_RST_EN_S 1 /** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0; - * Set 0 to reset hp_peri timeout module and hp_modem timeout module + * Set 1 to reset hp_peri timeout module and hp_modem timeout module */ #define PCR_HP_TIMEOUT_RST_EN (BIT(2)) #define PCR_HP_TIMEOUT_RST_EN_M (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S) @@ -1619,11 +1619,26 @@ extern "C" { * SYSCLK configuration register */ #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0xe8) +/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ +#define PCR_LS_DIV_NUM 0x000000FFU +#define PCR_LS_DIV_NUM_M (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S) +#define PCR_LS_DIV_NUM_V 0x000000FFU +#define PCR_LS_DIV_NUM_S 0 +/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ +#define PCR_HS_DIV_NUM 0x000000FFU +#define PCR_HS_DIV_NUM_M (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S) +#define PCR_HS_DIV_NUM_V 0x000000FFU +#define PCR_HS_DIV_NUM_S 8 /** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0; - * Configures to select the clock source of HP_ROOT_CLK.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F160M_CLK\\ + * Configures to select the clock source of HP_ROOT_CLK. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F160M_CLK */ #define PCR_SOC_CLK_SEL 0x00000003U #define PCR_SOC_CLK_SEL_M (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S) @@ -1649,20 +1664,6 @@ extern "C" { * CPU_WAITI configuration register */ #define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0xec) -/** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM - */ -#define PCR_CPUPERIOD_SEL 0x00000003U -#define PCR_CPUPERIOD_SEL_M (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S) -#define PCR_CPUPERIOD_SEL_V 0x00000003U -#define PCR_CPUPERIOD_SEL_S 0 -/** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM - */ -#define PCR_PLL_FREQ_SEL (BIT(2)) -#define PCR_PLL_FREQ_SEL_M (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S) -#define PCR_PLL_FREQ_SEL_V 0x00000001U -#define PCR_PLL_FREQ_SEL_S 2 /** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; * Set 1 to force cpu_waiti_clk enable. */ @@ -1684,7 +1685,7 @@ extern "C" { */ #define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0xf0) /** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_cpu derived by clk_hproot. The clk_cpu is + * Set this field to generate clk_cpu driven by clk_hproot. The clk_cpu is * div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. */ @@ -1698,7 +1699,7 @@ extern "C" { */ #define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0xf4) /** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_ahb derived by clk_hproot. The clk_ahb is + * Set this field to generate clk_ahb driven by clk_hproot. The clk_ahb is * div1(default)/div2/div4/div8 of clk_hproot. This field is only available for * low-speed clock-source such as XTAL/FOSC, and should be used together with * PCR_CPU_DIV_NUM. @@ -1726,7 +1727,7 @@ extern "C" { #define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU #define PCR_APB_DECREASE_DIV_NUM_S 0 /** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; - * Set as one within (0,1,3) to generate clk_apb derived by clk_ahb. The clk_apb is + * Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is * div1(default)/div2/div4 of clk_ahb. */ #define PCR_APB_DIV_NUM 0x000000FFU @@ -1758,7 +1759,7 @@ extern "C" { */ #define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x100) /** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; - * This field is used to open 160 MHz clock (div3 of SPLL) derived from SPLL. 0: close, + * This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_160M_CLK_EN (BIT(1)) @@ -1766,7 +1767,7 @@ extern "C" { #define PCR_PLL_160M_CLK_EN_V 0x00000001U #define PCR_PLL_160M_CLK_EN_S 1 /** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; - * This field is used to open 120 MHz clock (div4 of SPLL) derived from SPLL. 0: close, + * This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_120M_CLK_EN (BIT(2)) @@ -1774,7 +1775,7 @@ extern "C" { #define PCR_PLL_120M_CLK_EN_V 0x00000001U #define PCR_PLL_120M_CLK_EN_S 2 /** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; - * This field is used to open 80 MHz clock (div6 of SPLL) derived from SPLL. 0: close, + * This field is used to open 80 MHz clock (div6 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_80M_CLK_EN (BIT(3)) @@ -1782,7 +1783,7 @@ extern "C" { #define PCR_PLL_80M_CLK_EN_V 0x00000001U #define PCR_PLL_80M_CLK_EN_S 3 /** PCR_PLL_60M_CLK_EN : R/W; bitpos: [4]; default: 1; - * This field is used to open 60 MHz clock (div8 of SPLL) derived from SPLL. 0: close, + * This field is used to open 60 MHz clock (div8 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_60M_CLK_EN (BIT(4)) @@ -1790,7 +1791,7 @@ extern "C" { #define PCR_PLL_60M_CLK_EN_V 0x00000001U #define PCR_PLL_60M_CLK_EN_S 4 /** PCR_PLL_48M_CLK_EN : R/W; bitpos: [5]; default: 1; - * This field is used to open 48 MHz clock (div10 of SPLL) derived from SPLL. 0: close, + * This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_48M_CLK_EN (BIT(5)) @@ -1798,7 +1799,7 @@ extern "C" { #define PCR_PLL_48M_CLK_EN_V 0x00000001U #define PCR_PLL_48M_CLK_EN_S 5 /** PCR_PLL_40M_CLK_EN : R/W; bitpos: [6]; default: 1; - * This field is used to open 40 MHz clock (div12 of SPLL) derived from SPLL. 0: close, + * This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_40M_CLK_EN (BIT(6)) @@ -1806,21 +1807,13 @@ extern "C" { #define PCR_PLL_40M_CLK_EN_V 0x00000001U #define PCR_PLL_40M_CLK_EN_S 6 /** PCR_PLL_20M_CLK_EN : R/W; bitpos: [7]; default: 1; - * This field is used to open 20 MHz clock (div24 of SPLL) derived from SPLL. 0: close, + * This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_20M_CLK_EN (BIT(7)) #define PCR_PLL_20M_CLK_EN_M (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S) #define PCR_PLL_20M_CLK_EN_V 0x00000001U #define PCR_PLL_20M_CLK_EN_S 7 -/** PCR_PLL_12M_CLK_EN : HRO; bitpos: [8]; default: 1; - * This field is used to open 12 MHz clock (div40 of SPLL) derived from SPLL. 0: close, - * 1: open(default). Only available when high-speed clock-source SPLL is active. - */ -#define PCR_PLL_12M_CLK_EN (BIT(8)) -#define PCR_PLL_12M_CLK_EN_M (PCR_PLL_12M_CLK_EN_V << PCR_PLL_12M_CLK_EN_S) -#define PCR_PLL_12M_CLK_EN_V 0x00000001U -#define PCR_PLL_12M_CLK_EN_S 8 /** PCR_CTRL_CLK_OUT_EN_REG register * CLK_OUT_EN configuration register @@ -1902,12 +1895,12 @@ extern "C" { */ #define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x10c) /** PCR_32K_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures the 32KHz clock for TIMER_GROUP.\\ - * 0 (default): RC32K_CLK\\ - * 1: XTAL32K_CLK\\ - * 2: OSC_SLOW_CLK\\ - * 3: RC_SLOW_CLK\\ - * 4: RC_FAST_CLK\\ + * Configures the 32KHz clock for TIMER_GROUP. + * 0 (default): RC32K_CLK + * 1: XTAL32K_CLK + * 2: OSC_SLOW_CLK + * 3: RC_SLOW_CLK + * 4: RC_FAST_CLK */ #define PCR_32K_SEL 0x00000007U #define PCR_32K_SEL_M (PCR_32K_SEL_V << PCR_32K_SEL_S) @@ -1982,52 +1975,33 @@ extern "C" { #define PCR_SEC_CONF_REG (DR_REG_PCR_BASE + 0x118) /** PCR_SEC_CLK_SEL : R/W; bitpos: [1:0]; default: 0; * Configures the clock source for the External Memory Encryption and Decryption - * module.\\ - * 0(default): XTAL_CLK\\ - * 1 RC_FAST_CLK\\ - * 2: PLL_F480M_CLK\\ + * module. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK */ #define PCR_SEC_CLK_SEL 0x00000003U #define PCR_SEC_CLK_SEL_M (PCR_SEC_CLK_SEL_V << PCR_SEC_CLK_SEL_S) #define PCR_SEC_CLK_SEL_V 0x00000003U #define PCR_SEC_CLK_SEL_S 0 /** PCR_SEC_RST_EN : R/W; bitpos: [2]; default: 0; - * Set 0 to reset sec module + * Set 1 to reset sec module */ #define PCR_SEC_RST_EN (BIT(2)) #define PCR_SEC_RST_EN_M (PCR_SEC_RST_EN_V << PCR_SEC_RST_EN_S) #define PCR_SEC_RST_EN_V 0x00000001U #define PCR_SEC_RST_EN_S 2 -/** PCR_ADC_DAC_INV_PHASE_CONF_REG register - * xxxx - */ -#define PCR_ADC_DAC_INV_PHASE_CONF_REG (DR_REG_PCR_BASE + 0x11c) -/** PCR_CLK_RX_ADC_INV_PHASE_ENA : R/W; bitpos: [0]; default: 0; - * xxxx - */ -#define PCR_CLK_RX_ADC_INV_PHASE_ENA (BIT(0)) -#define PCR_CLK_RX_ADC_INV_PHASE_ENA_M (PCR_CLK_RX_ADC_INV_PHASE_ENA_V << PCR_CLK_RX_ADC_INV_PHASE_ENA_S) -#define PCR_CLK_RX_ADC_INV_PHASE_ENA_V 0x00000001U -#define PCR_CLK_RX_ADC_INV_PHASE_ENA_S 0 -/** PCR_CLK_TX_DAC_INV_PHASE_ENA : R/W; bitpos: [1]; default: 0; - * xxxx - */ -#define PCR_CLK_TX_DAC_INV_PHASE_ENA (BIT(1)) -#define PCR_CLK_TX_DAC_INV_PHASE_ENA_M (PCR_CLK_TX_DAC_INV_PHASE_ENA_V << PCR_CLK_TX_DAC_INV_PHASE_ENA_S) -#define PCR_CLK_TX_DAC_INV_PHASE_ENA_V 0x00000001U -#define PCR_CLK_TX_DAC_INV_PHASE_ENA_S 1 - /** PCR_BUS_CLK_UPDATE_REG register * Configuration register for applying updated high-performance system clock sources */ #define PCR_BUS_CLK_UPDATE_REG (DR_REG_PCR_BASE + 0x120) /** PCR_BUS_CLOCK_UPDATE : R/W/WTC; bitpos: [0]; default: 0; * Configures whether or not to update configurations for CPU_CLK division, AHB_CLK - * division and HP_ROOT_CLK clock source selection.\\ - * 0: Not update configurations\\ - * 1: Update configurations\\ - * This bit is automatically cleared when configurations have been updated.\\ + * division and HP_ROOT_CLK clock source selection. + * 0: Not update configurations + * 1: Update configurations + * This bit is automatically cleared when configurations have been updated. */ #define PCR_BUS_CLOCK_UPDATE (BIT(0)) #define PCR_BUS_CLOCK_UPDATE_M (PCR_BUS_CLOCK_UPDATE_V << PCR_BUS_CLOCK_UPDATE_S) @@ -2039,54 +2013,33 @@ extern "C" { */ #define PCR_SAR_CLK_DIV_REG (DR_REG_PCR_BASE + 0x124) /** PCR_SAR2_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 4; - * Configures the divisor for SAR ADC 2 clock to generate ADC analog control - * signals.\\ + * Configures the divisor for SAR ADC 2 clock to generate ADC analog control signals. */ #define PCR_SAR2_CLK_DIV_NUM 0x000000FFU #define PCR_SAR2_CLK_DIV_NUM_M (PCR_SAR2_CLK_DIV_NUM_V << PCR_SAR2_CLK_DIV_NUM_S) #define PCR_SAR2_CLK_DIV_NUM_V 0x000000FFU #define PCR_SAR2_CLK_DIV_NUM_S 0 /** PCR_SAR1_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 4; - * Configures the divisor for SAR ADC 1 clock to generate ADC analog control - * signals.\\ + * Configures the divisor for SAR ADC 1 clock to generate ADC analog control signals. */ #define PCR_SAR1_CLK_DIV_NUM 0x000000FFU #define PCR_SAR1_CLK_DIV_NUM_M (PCR_SAR1_CLK_DIV_NUM_V << PCR_SAR1_CLK_DIV_NUM_S) #define PCR_SAR1_CLK_DIV_NUM_V 0x000000FFU #define PCR_SAR1_CLK_DIV_NUM_S 8 -/** PCR_PWDET_SAR_CLK_CONF_REG register - * xxxx - */ -#define PCR_PWDET_SAR_CLK_CONF_REG (DR_REG_PCR_BASE + 0x128) -/** PCR_PWDET_SAR_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 7; - * xxxx - */ -#define PCR_PWDET_SAR_CLK_DIV_NUM 0x000000FFU -#define PCR_PWDET_SAR_CLK_DIV_NUM_M (PCR_PWDET_SAR_CLK_DIV_NUM_V << PCR_PWDET_SAR_CLK_DIV_NUM_S) -#define PCR_PWDET_SAR_CLK_DIV_NUM_V 0x000000FFU -#define PCR_PWDET_SAR_CLK_DIV_NUM_S 0 -/** PCR_PWDET_SAR_CLK_EN : R/W; bitpos: [8]; default: 1; - * xxxx - */ -#define PCR_PWDET_SAR_CLK_EN (BIT(8)) -#define PCR_PWDET_SAR_CLK_EN_M (PCR_PWDET_SAR_CLK_EN_V << PCR_PWDET_SAR_CLK_EN_S) -#define PCR_PWDET_SAR_CLK_EN_V 0x00000001U -#define PCR_PWDET_SAR_CLK_EN_S 8 - /** PCR_TIMERGROUP_WDT_CONF_REG register * TIMERGROUP_WDT configuration register */ #define PCR_TIMERGROUP_WDT_CONF_REG (DR_REG_PCR_BASE + 0x12c) /** PCR_TG0_WDT_RST_EN : R/W; bitpos: [0]; default: 0; - * Set 0 to reset timer_group0 wdt module + * Set 1 to reset timer_group0 wdt module */ #define PCR_TG0_WDT_RST_EN (BIT(0)) #define PCR_TG0_WDT_RST_EN_M (PCR_TG0_WDT_RST_EN_V << PCR_TG0_WDT_RST_EN_S) #define PCR_TG0_WDT_RST_EN_V 0x00000001U #define PCR_TG0_WDT_RST_EN_S 0 /** PCR_TG1_WDT_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 wdt module + * Set 1 to reset timer_group1 wdt module */ #define PCR_TG1_WDT_RST_EN (BIT(1)) #define PCR_TG1_WDT_RST_EN_M (PCR_TG1_WDT_RST_EN_V << PCR_TG1_WDT_RST_EN_S) @@ -2098,14 +2051,14 @@ extern "C" { */ #define PCR_TIMERGROUP_XTAL_CONF_REG (DR_REG_PCR_BASE + 0x130) /** PCR_TG0_XTAL_RST_EN : R/W; bitpos: [0]; default: 0; - * Set 0 to reset timer_group0 xtal clock domain + * Set 1 to reset timer_group0 xtal clock domain */ #define PCR_TG0_XTAL_RST_EN (BIT(0)) #define PCR_TG0_XTAL_RST_EN_M (PCR_TG0_XTAL_RST_EN_V << PCR_TG0_XTAL_RST_EN_S) #define PCR_TG0_XTAL_RST_EN_V 0x00000001U #define PCR_TG0_XTAL_RST_EN_S 0 /** PCR_TG1_XTAL_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 xtal clock domain + * Set 1 to reset timer_group1 xtal clock domain */ #define PCR_TG1_XTAL_RST_EN (BIT(1)) #define PCR_TG1_XTAL_RST_EN_M (PCR_TG1_XTAL_RST_EN_V << PCR_TG1_XTAL_RST_EN_S) @@ -2156,7 +2109,7 @@ extern "C" { #define PCR_REGDMA_CLK_EN_V 0x00000001U #define PCR_REGDMA_CLK_EN_S 0 /** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset regdma module + * Set 1 to reset regdma module */ #define PCR_REGDMA_RST_EN (BIT(1)) #define PCR_REGDMA_RST_EN_M (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S) @@ -2175,7 +2128,7 @@ extern "C" { #define PCR_ETM_CLK_EN_V 0x00000001U #define PCR_ETM_CLK_EN_S 0 /** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset etm module + * Set 1 to reset etm module */ #define PCR_ETM_RST_EN (BIT(1)) #define PCR_ETM_RST_EN_M (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S) @@ -2189,35 +2142,49 @@ extern "C" { #define PCR_ETM_READY_V 0x00000001U #define PCR_ETM_READY_S 2 -/** PCR_FPGA_DEBUG_REG register - * fpga debug register +/** PCR_SDIO_SLAVE_CONF_REG register + * SDIO_SLAVE configuration register */ -#define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4) -/** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295; - * Only used in fpga debug. +#define PCR_SDIO_SLAVE_CONF_REG (DR_REG_PCR_BASE + 0x158) +/** PCR_SDIO_SLAVE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sdio_slave clock */ -#define PCR_FPGA_DEBUG 0xFFFFFFFFU -#define PCR_FPGA_DEBUG_M (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S) -#define PCR_FPGA_DEBUG_V 0xFFFFFFFFU -#define PCR_FPGA_DEBUG_S 0 +#define PCR_SDIO_SLAVE_CLK_EN (BIT(0)) +#define PCR_SDIO_SLAVE_CLK_EN_M (PCR_SDIO_SLAVE_CLK_EN_V << PCR_SDIO_SLAVE_CLK_EN_S) +#define PCR_SDIO_SLAVE_CLK_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_CLK_EN_S 0 +/** PCR_SDIO_SLAVE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset sdio_slave module + */ +#define PCR_SDIO_SLAVE_RST_EN (BIT(1)) +#define PCR_SDIO_SLAVE_RST_EN_M (PCR_SDIO_SLAVE_RST_EN_V << PCR_SDIO_SLAVE_RST_EN_S) +#define PCR_SDIO_SLAVE_RST_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_RST_EN_S 1 -/** PCR_CLOCK_GATE_REG register - * PCR clock gating configure register +/** PCR_SDIO_SLAVE_PD_CTRL_REG register + * LEDC power control register */ -#define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8) -/** PCR_CLK_EN : R/W; bitpos: [0]; default: 0; - * Set this bit as 1 to force on clock gating. +#define PCR_SDIO_SLAVE_PD_CTRL_REG (DR_REG_PCR_BASE + 0x15c) +/** PCR_SDIO_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down SDIO memory. */ -#define PCR_CLK_EN (BIT(0)) -#define PCR_CLK_EN_M (PCR_CLK_EN_V << PCR_CLK_EN_S) -#define PCR_CLK_EN_V 0x00000001U -#define PCR_CLK_EN_S 0 +#define PCR_SDIO_MEM_FORCE_PU (BIT(1)) +#define PCR_SDIO_MEM_FORCE_PU_M (PCR_SDIO_MEM_FORCE_PU_V << PCR_SDIO_MEM_FORCE_PU_S) +#define PCR_SDIO_MEM_FORCE_PU_V 0x00000001U +#define PCR_SDIO_MEM_FORCE_PU_S 1 +/** PCR_SDIO_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up SDIO memory. + */ +#define PCR_SDIO_MEM_FORCE_PD (BIT(2)) +#define PCR_SDIO_MEM_FORCE_PD_M (PCR_SDIO_MEM_FORCE_PD_V << PCR_SDIO_MEM_FORCE_PD_S) +#define PCR_SDIO_MEM_FORCE_PD_V 0x00000001U +#define PCR_SDIO_MEM_FORCE_PD_S 2 /** PCR_DATE_REG register * Date register. */ #define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc) -/** PCR_DATE : R/W; bitpos: [27:0]; default: 37753376; +/** PCR_DATE : R/W; bitpos: [27:0]; default: 37823120; * PCR version information. */ #define PCR_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c61/register/soc/pcr_struct.h b/components/soc/esp32c61/register/soc/pcr_struct.h index 0591f845ef..9e36f9e790 100644 --- a/components/soc/esp32c61/register/soc/pcr_struct.h +++ b/components/soc/esp32c61/register/soc/pcr_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -21,7 +21,7 @@ typedef union { */ uint32_t uart0_clk_en:1; /** uart0_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart0 module + * Set 1 to reset uart0 module */ uint32_t uart0_rst_en:1; /** uart0_ready : RO; bitpos: [2]; default: 1; @@ -51,10 +51,10 @@ typedef union { */ uint32_t uart0_sclk_div_num:8; /** uart0_sclk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t uart0_sclk_sel:2; /** uart0_sclk_en : R/W; bitpos: [22]; default: 1; @@ -95,7 +95,7 @@ typedef union { */ uint32_t uart1_clk_en:1; /** uart1_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart1 module + * Set 1 to reset uart1 module */ uint32_t uart1_rst_en:1; /** uart1_ready : RO; bitpos: [2]; default: 1; @@ -125,10 +125,10 @@ typedef union { */ uint32_t uart1_sclk_div_num:8; /** uart1_sclk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t uart1_sclk_sel:2; /** uart1_sclk_en : R/W; bitpos: [22]; default: 1; @@ -169,7 +169,7 @@ typedef union { */ uint32_t uart2_clk_en:1; /** uart2_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart2 module + * Set 1 to reset uart2 module */ uint32_t uart2_rst_en:1; /** uart2_ready : RO; bitpos: [2]; default: 1; @@ -199,10 +199,10 @@ typedef union { */ uint32_t uart2_sclk_div_num:8; /** uart2_sclk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART2.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART2. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t uart2_sclk_sel:2; /** uart2_sclk_en : R/W; bitpos: [22]; default: 1; @@ -243,7 +243,7 @@ typedef union { */ uint32_t mspi_clk_en:1; /** mspi_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset mspi module + * Set 1 to reset mspi module */ uint32_t mspi_rst_en:1; /** mspi_pll_clk_en : R/W; bitpos: [2]; default: 1; @@ -271,10 +271,10 @@ typedef union { */ uint32_t mspi_fast_div_num:8; /** mspi_func_clk_sel : R/W; bitpos: [9:8]; default: 0; - * Configures the clock source for MSPI.\\ - * 0(default): XTAL_CLK\\ - * 1 RC_FAST_CLK\\ - * 2: PLL_F480M_CLK\\ + * Configures the clock source for MSPI. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK */ uint32_t mspi_func_clk_sel:2; /** mspi_func_clk_en : R/W; bitpos: [10]; default: 1; @@ -282,7 +282,7 @@ typedef union { */ uint32_t mspi_func_clk_en:1; /** mspi_axi_rst_en : R/W; bitpos: [11]; default: 0; - * Set 0 to reset axi_clock domain of mspi module + * Set 1 to reset axi_clock domain of mspi module */ uint32_t mspi_axi_rst_en:1; uint32_t reserved_12:20; @@ -300,7 +300,7 @@ typedef union { */ uint32_t i2c_clk_en:1; /** i2c_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2c module + * Set 1 to reset i2c module */ uint32_t i2c_rst_en:1; uint32_t reserved_2:30; @@ -326,9 +326,9 @@ typedef union { */ uint32_t i2c_sclk_div_num:8; /** i2c_sclk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of I2C.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of I2C. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ uint32_t i2c_sclk_sel:1; uint32_t reserved_21:1; @@ -351,7 +351,7 @@ typedef union { */ uint32_t ledc_clk_en:1; /** ledc_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ledc module + * Set 1 to reset ledc module */ uint32_t ledc_rst_en:1; /** ledc_ready : RO; bitpos: [2]; default: 1; @@ -370,10 +370,10 @@ typedef union { struct { uint32_t reserved_0:20; /** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of LEDC.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of LEDC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t ledc_sclk_sel:2; /** ledc_sclk_en : R/W; bitpos: [22]; default: 1; @@ -414,7 +414,7 @@ typedef union { */ uint32_t tg0_clk_en:1; /** tg0_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group0 module + * Set 1 to reset timer_group0 module */ uint32_t tg0_rst_en:1; /** tg0_wdt_ready : RO; bitpos: [2]; default: 1; @@ -441,10 +441,10 @@ typedef union { struct { uint32_t reserved_0:20; /** tg0_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of general-purpose timers in Timer Group 0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of general-purpose timers in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t tg0_timer_clk_sel:2; /** tg0_timer_clk_en : R/W; bitpos: [22]; default: 1; @@ -463,10 +463,10 @@ typedef union { struct { uint32_t reserved_0:20; /** tg0_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of WDT in Timer Group 0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of WDT in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t tg0_wdt_clk_sel:2; /** tg0_wdt_clk_en : R/W; bitpos: [22]; default: 1; @@ -488,7 +488,7 @@ typedef union { */ uint32_t tg1_clk_en:1; /** tg1_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 module + * Set 1 to reset timer_group1 module */ uint32_t tg1_rst_en:1; /** tg1_wdt_ready : RO; bitpos: [2]; default: 1; @@ -515,10 +515,10 @@ typedef union { struct { uint32_t reserved_0:20; /** tg1_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of general-purpose timers in Timer Group 1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of general-purpose timers in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t tg1_timer_clk_sel:2; /** tg1_timer_clk_en : R/W; bitpos: [22]; default: 1; @@ -537,10 +537,10 @@ typedef union { struct { uint32_t reserved_0:20; /** tg1_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of WDT in Timer Group 1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of WDT in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t tg1_wdt_clk_sel:2; /** tg1_wdt_clk_en : R/W; bitpos: [22]; default: 1; @@ -562,7 +562,7 @@ typedef union { */ uint32_t systimer_clk_en:1; /** systimer_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset systimer module + * Set 1 to reset systimer module */ uint32_t systimer_rst_en:1; /** systimer_ready : RO; bitpos: [2]; default: 1; @@ -581,9 +581,9 @@ typedef union { struct { uint32_t reserved_0:20; /** systimer_func_clk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of System Timer.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of System Timer. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ uint32_t systimer_func_clk_sel:1; uint32_t reserved_21:1; @@ -606,7 +606,7 @@ typedef union { */ uint32_t i2s_clk_en:1; /** i2s_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2s module + * Set 1 to reset i2s module */ uint32_t i2s_rst_en:1; /** i2s_rx_ready : RO; bitpos: [2]; default: 1; @@ -636,11 +636,11 @@ typedef union { */ uint32_t i2s_tx_clkm_div_num:8; /** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of I2S TX.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F120M_CLK\\ - * 2: PLL_F160M_CLK\\ - * 3: I2S_MCLK_in\\ + * Configures the clock source of I2S TX. + * 0 (default): XTAL_CLK + * 1: PLL_F120M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in */ uint32_t i2s_tx_clkm_sel:2; /** i2s_tx_clkm_en : R/W; bitpos: [22]; default: 1; @@ -693,11 +693,11 @@ typedef union { */ uint32_t i2s_rx_clkm_div_num:8; /** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of I2S RX.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F120M_CLK\\ - * 2: PLL_F160M_CLK\\ - * 3: I2S_MCLK_in\\ + * Configures the clock source of I2S RX. + * 0 (default): XTAL_CLK + * 1: PLL_F120M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in */ uint32_t i2s_rx_clkm_sel:2; /** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1; @@ -705,9 +705,9 @@ typedef union { */ uint32_t i2s_rx_clkm_en:1; /** i2s_mclk_sel : R/W; bitpos: [23]; default: 0; - * Configures to select master clock.\\ - * 0 (default): I2S_TX_CLK\\ - * 1: I2S_RX_CLK\\ + * Configures to select master clock. + * 0 (default): I2S_TX_CLK + * 1: I2S_RX_CLK */ uint32_t i2s_mclk_sel:1; uint32_t reserved_24:8; @@ -755,7 +755,7 @@ typedef union { */ uint32_t saradc_clk_en:1; /** saradc_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset function_register of saradc module + * Set 1 to reset function_register of saradc module */ uint32_t saradc_rst_en:1; /** saradc_reg_clk_en : R/W; bitpos: [2]; default: 1; @@ -763,7 +763,7 @@ typedef union { */ uint32_t saradc_reg_clk_en:1; /** saradc_reg_rst_en : R/W; bitpos: [3]; default: 0; - * Set 0 to reset apb_register of saradc module + * Set 1 to reset apb_register of saradc module */ uint32_t saradc_reg_rst_en:1; uint32_t reserved_4:28; @@ -789,10 +789,10 @@ typedef union { */ uint32_t saradc_clkm_div_num:8; /** saradc_clkm_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of SAR ADC.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of SAR ADC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t saradc_clkm_sel:2; /** saradc_clkm_en : R/W; bitpos: [22]; default: 1; @@ -811,9 +811,9 @@ typedef union { struct { uint32_t reserved_0:20; /** tsens_clk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of the temperature sensor.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of the temperature sensor. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ uint32_t tsens_clk_sel:1; uint32_t reserved_21:1; @@ -822,7 +822,7 @@ typedef union { */ uint32_t tsens_clk_en:1; /** tsens_rst_en : R/W; bitpos: [23]; default: 0; - * Set 0 to reset tsens module + * Set 1 to reset tsens module */ uint32_t tsens_rst_en:1; uint32_t reserved_24:8; @@ -840,7 +840,7 @@ typedef union { */ uint32_t usb_device_clk_en:1; /** usb_device_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset usb_device module + * Set 1 to reset usb_device module */ uint32_t usb_device_rst_en:1; /** usb_device_ready : RO; bitpos: [2]; default: 1; @@ -862,7 +862,7 @@ typedef union { */ uint32_t intmtx_clk_en:1; /** intmtx_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset intmtx module + * Set 1 to reset intmtx module */ uint32_t intmtx_rst_en:1; /** intmtx_ready : RO; bitpos: [2]; default: 1; @@ -916,9 +916,9 @@ typedef union { uint32_t pvt_monitor_func_clk_div_num:4; uint32_t reserved_4:16; /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of PVT MONITOR.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F160M_CLK\\ + * Configures the clock source of PVT MONITOR. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK */ uint32_t pvt_monitor_func_clk_sel:1; uint32_t reserved_21:1; @@ -941,7 +941,7 @@ typedef union { */ uint32_t gdma_clk_en:1; /** gdma_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset gdma module + * Set 1 to reset gdma module */ uint32_t gdma_rst_en:1; uint32_t reserved_2:30; @@ -959,7 +959,7 @@ typedef union { */ uint32_t spi2_clk_en:1; /** spi2_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset spi2 module + * Set 1 to reset spi2 module */ uint32_t spi2_rst_en:1; /** spi2_ready : RO; bitpos: [2]; default: 1; @@ -982,10 +982,10 @@ typedef union { */ uint32_t spi2_clkm_div_num:8; /** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of SPI2.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F160M_CLK\\ - * 2: RC_FAST_CLK\\ + * Configures the clock source of SPI2. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK + * 2: RC_FAST_CLK */ uint32_t spi2_clkm_sel:2; /** spi2_clkm_en : R/W; bitpos: [22]; default: 1; @@ -1007,7 +1007,7 @@ typedef union { */ uint32_t aes_clk_en:1; /** aes_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset aes module + * Set 1 to reset aes module */ uint32_t aes_rst_en:1; /** aes_ready : RO; bitpos: [2]; default: 1; @@ -1029,7 +1029,7 @@ typedef union { */ uint32_t sha_clk_en:1; /** sha_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset sha module + * Set 1 to reset sha module */ uint32_t sha_rst_en:1; /** sha_ready : RO; bitpos: [2]; default: 1; @@ -1051,7 +1051,7 @@ typedef union { */ uint32_t rsa_clk_en:1; /** rsa_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset rsa module + * Set 1 to reset rsa module */ uint32_t rsa_rst_en:1; /** rsa_ready : RO; bitpos: [2]; default: 1; @@ -1095,7 +1095,7 @@ typedef union { */ uint32_t ecc_clk_en:1; /** ecc_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ecc module + * Set 1 to reset ecc module */ uint32_t ecc_rst_en:1; /** ecc_ready : RO; bitpos: [2]; default: 1; @@ -1139,7 +1139,7 @@ typedef union { */ uint32_t ds_clk_en:1; /** ds_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ds module + * Set 1 to reset ds module */ uint32_t ds_rst_en:1; /** ds_ready : RO; bitpos: [2]; default: 1; @@ -1161,7 +1161,7 @@ typedef union { */ uint32_t hmac_clk_en:1; /** hmac_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset hmac module + * Set 1 to reset hmac module */ uint32_t hmac_rst_en:1; /** hmac_ready : RO; bitpos: [2]; default: 1; @@ -1183,7 +1183,7 @@ typedef union { */ uint32_t ecdsa_clk_en:1; /** ecdsa_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ecdsa module + * Set 1 to reset ecdsa module */ uint32_t ecdsa_rst_en:1; /** ecdsa_ready : RO; bitpos: [2]; default: 1; @@ -1205,7 +1205,7 @@ typedef union { */ uint32_t iomux_clk_en:1; /** iomux_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset iomux module + * Set 1 to reset iomux module */ uint32_t iomux_rst_en:1; uint32_t reserved_2:30; @@ -1220,10 +1220,10 @@ typedef union { struct { uint32_t reserved_0:20; /** iomux_func_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of IO MUX.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of IO MUX. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t iomux_func_clk_sel:2; /** iomux_func_clk_en : R/W; bitpos: [22]; default: 1; @@ -1245,7 +1245,7 @@ typedef union { */ uint32_t tcm_mem_monitor_clk_en:1; /** tcm_mem_monitor_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset tcm_mem_monitor module + * Set 1 to reset tcm_mem_monitor module */ uint32_t tcm_mem_monitor_rst_en:1; /** tcm_mem_monitor_ready : RO; bitpos: [2]; default: 1; @@ -1267,7 +1267,7 @@ typedef union { */ uint32_t psram_mem_monitor_clk_en:1; /** psram_mem_monitor_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset psram_mem_monitor module + * Set 1 to reset psram_mem_monitor module */ uint32_t psram_mem_monitor_rst_en:1; /** psram_mem_monitor_ready : RO; bitpos: [2]; default: 1; @@ -1289,7 +1289,7 @@ typedef union { */ uint32_t trace_clk_en:1; /** trace_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset trace module + * Set 1 to reset trace module */ uint32_t trace_rst_en:1; uint32_t reserved_2:30; @@ -1307,7 +1307,7 @@ typedef union { */ uint32_t assist_clk_en:1; /** assist_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset assist module + * Set 1 to reset assist module */ uint32_t assist_rst_en:1; uint32_t reserved_2:30; @@ -1325,7 +1325,7 @@ typedef union { */ uint32_t cache_clk_en:1; /** cache_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cache module + * Set 1 to reset cache module */ uint32_t cache_rst_en:1; uint32_t reserved_2:30; @@ -1382,11 +1382,11 @@ typedef union { struct { uint32_t reserved_0:1; /** cpu_timeout_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cpu_peri timeout module + * Set 1 to reset cpu_peri timeout module */ uint32_t cpu_timeout_rst_en:1; /** hp_timeout_rst_en : R/W; bitpos: [2]; default: 0; - * Set 0 to reset hp_peri timeout module and hp_modem timeout module + * Set 1 to reset hp_peri timeout module and hp_modem timeout module */ uint32_t hp_timeout_rst_en:1; uint32_t reserved_3:29; @@ -1399,12 +1399,20 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:16; + /** ls_div_num : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ + uint32_t ls_div_num:8; + /** hs_div_num : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ + uint32_t hs_div_num:8; /** soc_clk_sel : R/W; bitpos: [17:16]; default: 0; - * Configures to select the clock source of HP_ROOT_CLK.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F160M_CLK\\ + * Configures to select the clock source of HP_ROOT_CLK. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F160M_CLK */ uint32_t soc_clk_sel:2; uint32_t reserved_18:6; @@ -1426,14 +1434,7 @@ typedef union { */ typedef union { struct { - /** cpuperiod_sel : HRO; bitpos: [1:0]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM - */ - uint32_t cpuperiod_sel:2; - /** pll_freq_sel : HRO; bitpos: [2]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM - */ - uint32_t pll_freq_sel:1; + uint32_t reserved_0:3; /** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1; * Set 1 to force cpu_waiti_clk enable. */ @@ -1454,7 +1455,7 @@ typedef union { typedef union { struct { /** cpu_div_num : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_cpu derived by clk_hproot. The clk_cpu is + * Set this field to generate clk_cpu driven by clk_hproot. The clk_cpu is * div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. */ @@ -1470,7 +1471,7 @@ typedef union { typedef union { struct { /** ahb_div_num : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_ahb derived by clk_hproot. The clk_ahb is + * Set this field to generate clk_ahb driven by clk_hproot. The clk_ahb is * div1(default)/div2/div4/div8 of clk_hproot. This field is only available for * low-speed clock-source such as XTAL/FOSC, and should be used together with * PCR_CPU_DIV_NUM. @@ -1497,7 +1498,7 @@ typedef union { */ uint32_t apb_decrease_div_num:8; /** apb_div_num : R/W; bitpos: [15:8]; default: 0; - * Set as one within (0,1,3) to generate clk_apb derived by clk_ahb. The clk_apb is + * Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is * div1(default)/div2/div4 of clk_ahb. */ uint32_t apb_div_num:8; @@ -1513,46 +1514,41 @@ typedef union { struct { uint32_t reserved_0:1; /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1; - * This field is used to open 160 MHz clock (div3 of SPLL) derived from SPLL. 0: close, + * This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_160m_clk_en:1; /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1; - * This field is used to open 120 MHz clock (div4 of SPLL) derived from SPLL. 0: close, + * This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_120m_clk_en:1; /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1; - * This field is used to open 80 MHz clock (div6 of SPLL) derived from SPLL. 0: close, + * This field is used to open 80 MHz clock (div6 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_80m_clk_en:1; /** pll_60m_clk_en : R/W; bitpos: [4]; default: 1; - * This field is used to open 60 MHz clock (div8 of SPLL) derived from SPLL. 0: close, + * This field is used to open 60 MHz clock (div8 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_60m_clk_en:1; /** pll_48m_clk_en : R/W; bitpos: [5]; default: 1; - * This field is used to open 48 MHz clock (div10 of SPLL) derived from SPLL. 0: close, + * This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_48m_clk_en:1; /** pll_40m_clk_en : R/W; bitpos: [6]; default: 1; - * This field is used to open 40 MHz clock (div12 of SPLL) derived from SPLL. 0: close, + * This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_40m_clk_en:1; /** pll_20m_clk_en : R/W; bitpos: [7]; default: 1; - * This field is used to open 20 MHz clock (div24 of SPLL) derived from SPLL. 0: close, + * This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_20m_clk_en:1; - /** pll_12m_clk_en : HRO; bitpos: [8]; default: 1; - * This field is used to open 12 MHz clock (div40 of SPLL) derived from SPLL. 0: close, - * 1: open(default). Only available when high-speed clock-source SPLL is active. - */ - uint32_t pll_12m_clk_en:1; - uint32_t reserved_9:23; + uint32_t reserved_8:24; }; uint32_t val; } pcr_pll_div_clk_en_reg_t; @@ -1612,13 +1608,13 @@ typedef union { */ typedef union { struct { - /** 32k_sel : R/W; bitpos: [2:0]; default: 0; - * Configures the 32KHz clock for TIMER_GROUP.\\ - * 0 (default): RC32K_CLK\\ - * 1: XTAL32K_CLK\\ - * 2: OSC_SLOW_CLK\\ - * 3: RC_SLOW_CLK\\ - * 4: RC_FAST_CLK\\ + /** clk_32k_sel : R/W; bitpos: [2:0]; default: 0; + * Configures the 32KHz clock for TIMER_GROUP. + * 0 (default): RC32K_CLK + * 1: XTAL32K_CLK + * 2: OSC_SLOW_CLK + * 3: RC_SLOW_CLK + * 4: RC_FAST_CLK */ uint32_t clk_32k_sel:3; uint32_t reserved_3:5; @@ -1687,14 +1683,14 @@ typedef union { struct { /** sec_clk_sel : R/W; bitpos: [1:0]; default: 0; * Configures the clock source for the External Memory Encryption and Decryption - * module.\\ - * 0(default): XTAL_CLK\\ - * 1 RC_FAST_CLK\\ - * 2: PLL_F480M_CLK\\ + * module. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK */ uint32_t sec_clk_sel:2; /** sec_rst_en : R/W; bitpos: [2]; default: 0; - * Set 0 to reset sec module + * Set 1 to reset sec module */ uint32_t sec_rst_en:1; uint32_t reserved_3:29; @@ -1702,24 +1698,6 @@ typedef union { uint32_t val; } pcr_sec_conf_reg_t; -/** Type of adc_dac_inv_phase_conf register - * xxxx - */ -typedef union { - struct { - /** clk_rx_adc_inv_phase_ena : R/W; bitpos: [0]; default: 0; - * xxxx - */ - uint32_t clk_rx_adc_inv_phase_ena:1; - /** clk_tx_dac_inv_phase_ena : R/W; bitpos: [1]; default: 0; - * xxxx - */ - uint32_t clk_tx_dac_inv_phase_ena:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} pcr_adc_dac_inv_phase_conf_reg_t; - /** Type of bus_clk_update register * Configuration register for applying updated high-performance system clock sources */ @@ -1727,10 +1705,10 @@ typedef union { struct { /** bus_clock_update : R/W/WTC; bitpos: [0]; default: 0; * Configures whether or not to update configurations for CPU_CLK division, AHB_CLK - * division and HP_ROOT_CLK clock source selection.\\ - * 0: Not update configurations\\ - * 1: Update configurations\\ - * This bit is automatically cleared when configurations have been updated.\\ + * division and HP_ROOT_CLK clock source selection. + * 0: Not update configurations + * 1: Update configurations + * This bit is automatically cleared when configurations have been updated. */ uint32_t bus_clock_update:1; uint32_t reserved_1:31; @@ -1744,13 +1722,11 @@ typedef union { typedef union { struct { /** sar2_clk_div_num : R/W; bitpos: [7:0]; default: 4; - * Configures the divisor for SAR ADC 2 clock to generate ADC analog control - * signals.\\ + * Configures the divisor for SAR ADC 2 clock to generate ADC analog control signals. */ uint32_t sar2_clk_div_num:8; /** sar1_clk_div_num : R/W; bitpos: [15:8]; default: 4; - * Configures the divisor for SAR ADC 1 clock to generate ADC analog control - * signals.\\ + * Configures the divisor for SAR ADC 1 clock to generate ADC analog control signals. */ uint32_t sar1_clk_div_num:8; uint32_t reserved_16:16; @@ -1758,35 +1734,17 @@ typedef union { uint32_t val; } pcr_sar_clk_div_reg_t; -/** Type of pwdet_sar_clk_conf register - * xxxx - */ -typedef union { - struct { - /** pwdet_sar_clk_div_num : R/W; bitpos: [7:0]; default: 7; - * xxxx - */ - uint32_t pwdet_sar_clk_div_num:8; - /** pwdet_sar_clk_en : R/W; bitpos: [8]; default: 1; - * xxxx - */ - uint32_t pwdet_sar_clk_en:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} pcr_pwdet_sar_clk_conf_reg_t; - /** Type of timergroup_wdt_conf register * TIMERGROUP_WDT configuration register */ typedef union { struct { /** tg0_wdt_rst_en : R/W; bitpos: [0]; default: 0; - * Set 0 to reset timer_group0 wdt module + * Set 1 to reset timer_group0 wdt module */ uint32_t tg0_wdt_rst_en:1; /** tg1_wdt_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 wdt module + * Set 1 to reset timer_group1 wdt module */ uint32_t tg1_wdt_rst_en:1; uint32_t reserved_2:30; @@ -1800,11 +1758,11 @@ typedef union { typedef union { struct { /** tg0_xtal_rst_en : R/W; bitpos: [0]; default: 0; - * Set 0 to reset timer_group0 xtal clock domain + * Set 1 to reset timer_group0 xtal clock domain */ uint32_t tg0_xtal_rst_en:1; /** tg1_xtal_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 xtal clock domain + * Set 1 to reset timer_group1 xtal clock domain */ uint32_t tg1_xtal_rst_en:1; /** tg0_xtal_clk_en : R/W; bitpos: [2]; default: 1; @@ -1816,30 +1774,6 @@ typedef union { uint32_t val; } pcr_timergroup_xtal_conf_reg_t; -/** Type of reset_event_bypass register - * reset event bypass backdoor configuration register - */ -typedef union { - struct { - /** reset_event_bypass_apm : R/W; bitpos: [0]; default: 0; - * This field is used to control reset event relationship for - * tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset - * by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg - * will not only be reset by power-reset, but also some reset event. - */ - uint32_t reset_event_bypass_apm:1; - /** reset_event_bypass : R/W; bitpos: [1]; default: 1; - * This field is used to control reset event relationship for system-bus. 1: system - * bus (including arbiter/router) will only be reset by power-reset. some reset event - * will be bypass. 0: system bus (including arbiter/router) will not only be reset by - * power-reset, but also some reset event. - */ - uint32_t reset_event_bypass:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} pcr_reset_event_bypass_reg_t; - /** Type of regdma_conf register * REGDMA configuration register */ @@ -1850,7 +1784,7 @@ typedef union { */ uint32_t regdma_clk_en:1; /** regdma_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset regdma module + * Set 1 to reset regdma module */ uint32_t regdma_rst_en:1; uint32_t reserved_2:30; @@ -1868,7 +1802,7 @@ typedef union { */ uint32_t etm_clk_en:1; /** etm_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset etm module + * Set 1 to reset etm module */ uint32_t etm_rst_en:1; /** etm_ready : RO; bitpos: [2]; default: 1; @@ -1880,19 +1814,42 @@ typedef union { uint32_t val; } pcr_etm_conf_reg_t; -/** Type of clock_gate register - * PCR clock gating configure register +/** Type of sdio_slave_conf register + * SDIO_SLAVE configuration register */ typedef union { struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * Set this bit as 1 to force on clock gating. + /** sdio_slave_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sdio_slave clock */ - uint32_t clk_en:1; - uint32_t reserved_1:31; + uint32_t sdio_slave_clk_en:1; + /** sdio_slave_rst_en : R/W; bitpos: [1]; default: 0; + * Set 1 to reset sdio_slave module + */ + uint32_t sdio_slave_rst_en:1; + uint32_t reserved_2:30; }; uint32_t val; -} pcr_clock_gate_reg_t; +} pcr_sdio_slave_conf_reg_t; + +/** Type of sdio_slave_pd_ctrl register + * LEDC power control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** sdio_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down SDIO memory. + */ + uint32_t sdio_mem_force_pu:1; + /** sdio_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up SDIO memory. + */ + uint32_t sdio_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_sdio_slave_pd_ctrl_reg_t; /** Group: Frequency Statistics Register */ @@ -1915,28 +1872,13 @@ typedef union { } pcr_sysclk_freq_query_0_reg_t; -/** Group: FPGA Debug Register */ -/** Type of fpga_debug register - * fpga debug register - */ -typedef union { - struct { - /** fpga_debug : R/W; bitpos: [31:0]; default: 4294967295; - * Only used in fpga debug. - */ - uint32_t fpga_debug:32; - }; - uint32_t val; -} pcr_fpga_debug_reg_t; - - /** Group: Version Register */ /** Type of date register * Date register. */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 37753376; + /** date : R/W; bitpos: [27:0]; default: 37823120; * PCR version information. */ uint32_t date:28; @@ -2018,18 +1960,19 @@ typedef struct { volatile pcr_sram_power_conf_0_reg_t sram_power_conf_0; volatile pcr_sram_power_conf_1_reg_t sram_power_conf_1; volatile pcr_sec_conf_reg_t sec_conf; - volatile pcr_adc_dac_inv_phase_conf_reg_t adc_dac_inv_phase_conf; + uint32_t reserved_11c; volatile pcr_bus_clk_update_reg_t bus_clk_update; volatile pcr_sar_clk_div_reg_t sar_clk_div; - volatile pcr_pwdet_sar_clk_conf_reg_t pwdet_sar_clk_conf; + uint32_t reserved_128; volatile pcr_timergroup_wdt_conf_reg_t timergroup_wdt_conf; volatile pcr_timergroup_xtal_conf_reg_t timergroup_xtal_conf; - volatile pcr_reset_event_bypass_reg_t reset_event_bypass; + uint32_t reserved_134; volatile pcr_regdma_conf_reg_t regdma_conf; volatile pcr_etm_conf_reg_t etm_conf; - uint32_t reserved_140[941]; - volatile pcr_fpga_debug_reg_t fpga_debug; - volatile pcr_clock_gate_reg_t clock_gate; + uint32_t reserved_140[6]; + volatile pcr_sdio_slave_conf_reg_t sdio_slave_conf; + volatile pcr_sdio_slave_pd_ctrl_reg_t sdio_slave_pd_ctrl; + uint32_t reserved_160[935]; volatile pcr_date_reg_t date; } pcr_dev_t; diff --git a/components/soc/esp32c61/register/soc/reg_base.h b/components/soc/esp32c61/register/soc/reg_base.h index d0af212f56..ec98bbf341 100644 --- a/components/soc/esp32c61/register/soc/reg_base.h +++ b/components/soc/esp32c61/register/soc/reg_base.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -20,9 +20,12 @@ #define DR_REG_SARADC_BASE 0x6000E000 #define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000 #define DR_REG_INTMTX_BASE 0x60010000 +#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTMTX_BASE #define DR_REG_SOC_ETM_BASE 0x60013000 -#define DR_REG_PVT_MONITOR_BASE 0x60019000 -#define DR_REG_PSRAM_MEM_MONITOR_BASE 0x6001A000 +#define DR_REG_HINF_BASE 0x60016000 +#define DR_REG_SLC_BASE 0x60017000 +#define DR_REG_HOST_BASE 0x60018000 +#define DR_REG_PVT_BASE 0x60019000 #define DR_REG_AHB_DMA_BASE 0x60080000 #define DR_REG_SPI2_BASE 0x60081000 #define DR_REG_SHA_BASE 0x60089000 @@ -31,18 +34,13 @@ #define DR_REG_IO_MUX_BASE 0x60090000 #define DR_REG_GPIO_BASE 0x60091000 #define DR_REG_GPIO_EXT_BASE 0x60091E00 -#define DR_REG_TCM_MEM_MONITOR_BASE 0x60092000 +#define DR_REG_MEM_MONITOR_BASE 0x60092000 #define DR_REG_PAU_BASE 0x60093000 #define DR_REG_HP_SYSTEM_BASE 0x60095000 #define DR_REG_PCR_BASE 0x60096000 #define DR_REG_TEE_BASE 0x60098000 #define DR_REG_HP_APM_BASE 0x60099000 -#define DR_REG_MISC_BASE 0x6009F000 -#define DR_REG_MODEM0_BASE 0x600A0000 -#define DR_REG_MODEM1_BASE 0x600AC000 -#define DR_REG_MODEM_PWR0_BASE 0x600AD000 -#define DR_REG_MODEM_PWR1_BASE 0x600AF000 -#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 +#define DR_REG_CPU_APM_REG_BASE 0x6009A000 #define DR_REG_PMU_BASE 0x600B0000 #define DR_REG_LP_CLKRST_BASE 0x600B0400 #define DR_REG_LP_TIMER_BASE 0x600B0C00 @@ -55,10 +53,13 @@ #define DR_REG_LP_IO_MUX_BASE 0x600B4000 #define DR_REG_LP_GPIO_BASE 0x600B4400 #define DR_REG_EFUSE0_BASE 0x600B4800 -#define DR_REG_EFUSE1_BASE 0x600B4C00 +#define DR_REG_OTP_DEBUG_BASE 0x600B4C00 #define DR_REG_TRACE_BASE 0x600C0000 #define DR_REG_BUS_MONITOR_BASE 0x600C2000 #define DR_REG_INTPRI_BASE 0x600C5000 #define DR_REG_CACHE_BASE 0x600C8000 + +// below are not generated but pick from old file #define DR_REG_CLINT_M_BASE 0x20000000 #define PWDET_CONF_REG 0x600A0808 +#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 diff --git a/components/soc/esp32c61/register/soc/sdio_hinf_reg.h b/components/soc/esp32c61/register/soc/sdio_hinf_reg.h new file mode 100644 index 0000000000..8c71517bcc --- /dev/null +++ b/components/soc/esp32c61/register/soc/sdio_hinf_reg.h @@ -0,0 +1,576 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HINF_CFG_DATA0_REG register + * Configure sdio cis content + */ +#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0) +/** HINF_DEVICE_ID_FN1 : R/W; bitpos: [15:0]; default: 26214; + * configure device id of function1 in cis + */ +#define HINF_DEVICE_ID_FN1 0x0000FFFFU +#define HINF_DEVICE_ID_FN1_M (HINF_DEVICE_ID_FN1_V << HINF_DEVICE_ID_FN1_S) +#define HINF_DEVICE_ID_FN1_V 0x0000FFFFU +#define HINF_DEVICE_ID_FN1_S 0 +/** HINF_USER_ID_FN1 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function1 in cis + */ +#define HINF_USER_ID_FN1 0x0000FFFFU +#define HINF_USER_ID_FN1_M (HINF_USER_ID_FN1_V << HINF_USER_ID_FN1_S) +#define HINF_USER_ID_FN1_V 0x0000FFFFU +#define HINF_USER_ID_FN1_S 16 + +/** HINF_CFG_DATA1_REG register + * SDIO configuration register + */ +#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4) +/** HINF_SDIO_ENABLE : R/W; bitpos: [0]; default: 1; + * Sdio clock enable + */ +#define HINF_SDIO_ENABLE (BIT(0)) +#define HINF_SDIO_ENABLE_M (HINF_SDIO_ENABLE_V << HINF_SDIO_ENABLE_S) +#define HINF_SDIO_ENABLE_V 0x00000001U +#define HINF_SDIO_ENABLE_S 0 +/** HINF_SDIO_IOREADY1 : R/W; bitpos: [1]; default: 0; + * sdio function1 io ready signal in cis + */ +#define HINF_SDIO_IOREADY1 (BIT(1)) +#define HINF_SDIO_IOREADY1_M (HINF_SDIO_IOREADY1_V << HINF_SDIO_IOREADY1_S) +#define HINF_SDIO_IOREADY1_V 0x00000001U +#define HINF_SDIO_IOREADY1_S 1 +/** HINF_HIGHSPEED_ENABLE : R/W; bitpos: [2]; default: 0; + * Highspeed enable in cccr + */ +#define HINF_HIGHSPEED_ENABLE (BIT(2)) +#define HINF_HIGHSPEED_ENABLE_M (HINF_HIGHSPEED_ENABLE_V << HINF_HIGHSPEED_ENABLE_S) +#define HINF_HIGHSPEED_ENABLE_V 0x00000001U +#define HINF_HIGHSPEED_ENABLE_S 2 +/** HINF_HIGHSPEED_MODE : RO; bitpos: [3]; default: 0; + * highspeed mode status in cccr + */ +#define HINF_HIGHSPEED_MODE (BIT(3)) +#define HINF_HIGHSPEED_MODE_M (HINF_HIGHSPEED_MODE_V << HINF_HIGHSPEED_MODE_S) +#define HINF_HIGHSPEED_MODE_V 0x00000001U +#define HINF_HIGHSPEED_MODE_S 3 +/** HINF_SDIO_CD_ENABLE : R/W; bitpos: [4]; default: 1; + * sdio card detect enable + */ +#define HINF_SDIO_CD_ENABLE (BIT(4)) +#define HINF_SDIO_CD_ENABLE_M (HINF_SDIO_CD_ENABLE_V << HINF_SDIO_CD_ENABLE_S) +#define HINF_SDIO_CD_ENABLE_V 0x00000001U +#define HINF_SDIO_CD_ENABLE_S 4 +/** HINF_SDIO_IOREADY2 : R/W; bitpos: [5]; default: 0; + * sdio function1 io ready signal in cis + */ +#define HINF_SDIO_IOREADY2 (BIT(5)) +#define HINF_SDIO_IOREADY2_M (HINF_SDIO_IOREADY2_V << HINF_SDIO_IOREADY2_S) +#define HINF_SDIO_IOREADY2_V 0x00000001U +#define HINF_SDIO_IOREADY2_S 5 +/** HINF_SDIO_INT_MASK : R/W; bitpos: [6]; default: 0; + * mask sdio interrupt in cccr, high active + */ +#define HINF_SDIO_INT_MASK (BIT(6)) +#define HINF_SDIO_INT_MASK_M (HINF_SDIO_INT_MASK_V << HINF_SDIO_INT_MASK_S) +#define HINF_SDIO_INT_MASK_V 0x00000001U +#define HINF_SDIO_INT_MASK_S 6 +/** HINF_IOENABLE2 : RO; bitpos: [7]; default: 0; + * ioe2 status in cccr + */ +#define HINF_IOENABLE2 (BIT(7)) +#define HINF_IOENABLE2_M (HINF_IOENABLE2_V << HINF_IOENABLE2_S) +#define HINF_IOENABLE2_V 0x00000001U +#define HINF_IOENABLE2_S 7 +/** HINF_CD_DISABLE : RO; bitpos: [8]; default: 0; + * card disable status in cccr + */ +#define HINF_CD_DISABLE (BIT(8)) +#define HINF_CD_DISABLE_M (HINF_CD_DISABLE_V << HINF_CD_DISABLE_S) +#define HINF_CD_DISABLE_V 0x00000001U +#define HINF_CD_DISABLE_S 8 +/** HINF_FUNC1_EPS : RO; bitpos: [9]; default: 0; + * function1 eps status in fbr + */ +#define HINF_FUNC1_EPS (BIT(9)) +#define HINF_FUNC1_EPS_M (HINF_FUNC1_EPS_V << HINF_FUNC1_EPS_S) +#define HINF_FUNC1_EPS_V 0x00000001U +#define HINF_FUNC1_EPS_S 9 +/** HINF_EMP : RO; bitpos: [10]; default: 0; + * empc status in cccr + */ +#define HINF_EMP (BIT(10)) +#define HINF_EMP_M (HINF_EMP_V << HINF_EMP_S) +#define HINF_EMP_V 0x00000001U +#define HINF_EMP_S 10 +/** HINF_IOENABLE1 : RO; bitpos: [11]; default: 0; + * ioe1 status in cccr + */ +#define HINF_IOENABLE1 (BIT(11)) +#define HINF_IOENABLE1_M (HINF_IOENABLE1_V << HINF_IOENABLE1_S) +#define HINF_IOENABLE1_V 0x00000001U +#define HINF_IOENABLE1_S 11 +/** HINF_SDIO_VER : R/W; bitpos: [23:12]; default: 562; + * sdio version in cccr + */ +#define HINF_SDIO_VER 0x00000FFFU +#define HINF_SDIO_VER_M (HINF_SDIO_VER_V << HINF_SDIO_VER_S) +#define HINF_SDIO_VER_V 0x00000FFFU +#define HINF_SDIO_VER_S 12 +/** HINF_FUNC2_EPS : RO; bitpos: [24]; default: 0; + * function2 eps status in fbr + */ +#define HINF_FUNC2_EPS (BIT(24)) +#define HINF_FUNC2_EPS_M (HINF_FUNC2_EPS_V << HINF_FUNC2_EPS_S) +#define HINF_FUNC2_EPS_V 0x00000001U +#define HINF_FUNC2_EPS_S 24 +/** HINF_SDIO20_CONF : R/W; bitpos: [31:25]; default: 0; + * [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat + * in delayed cycles control,0:no delay, 1:delay 1 cycle. + * [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed + * mode. + * [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when + * [12]=0,posedge when highspeed mode enable. + * [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay. + * [28]: sdio data pad pull up enable + */ +#define HINF_SDIO20_CONF 0x0000007FU +#define HINF_SDIO20_CONF_M (HINF_SDIO20_CONF_V << HINF_SDIO20_CONF_S) +#define HINF_SDIO20_CONF_V 0x0000007FU +#define HINF_SDIO20_CONF_S 25 + +/** HINF_CFG_TIMING_REG register + * Timing configuration registers + */ +#define HINF_CFG_TIMING_REG (DR_REG_HINF_BASE + 0x8) +/** HINF_NCRC : R/W; bitpos: [2:0]; default: 2; + * configure Ncrc parameter in sdr50/104 mode, no more than 6. + */ +#define HINF_NCRC 0x00000007U +#define HINF_NCRC_M (HINF_NCRC_V << HINF_NCRC_S) +#define HINF_NCRC_V 0x00000007U +#define HINF_NCRC_S 0 +/** HINF_PST_END_CMD_LOW_VALUE : R/W; bitpos: [9:3]; default: 2; + * configure cycles to lower cmd after voltage is changed to 1.8V. + */ +#define HINF_PST_END_CMD_LOW_VALUE 0x0000007FU +#define HINF_PST_END_CMD_LOW_VALUE_M (HINF_PST_END_CMD_LOW_VALUE_V << HINF_PST_END_CMD_LOW_VALUE_S) +#define HINF_PST_END_CMD_LOW_VALUE_V 0x0000007FU +#define HINF_PST_END_CMD_LOW_VALUE_S 3 +/** HINF_PST_END_DATA_LOW_VALUE : R/W; bitpos: [15:10]; default: 2; + * configure cycles to lower data after voltage is changed to 1.8V. + */ +#define HINF_PST_END_DATA_LOW_VALUE 0x0000003FU +#define HINF_PST_END_DATA_LOW_VALUE_M (HINF_PST_END_DATA_LOW_VALUE_V << HINF_PST_END_DATA_LOW_VALUE_S) +#define HINF_PST_END_DATA_LOW_VALUE_V 0x0000003FU +#define HINF_PST_END_DATA_LOW_VALUE_S 10 +/** HINF_SDCLK_STOP_THRES : R/W; bitpos: [26:16]; default: 1400; + * Configure the number of cycles of module clk to judge sdclk has stopped + */ +#define HINF_SDCLK_STOP_THRES 0x000007FFU +#define HINF_SDCLK_STOP_THRES_M (HINF_SDCLK_STOP_THRES_V << HINF_SDCLK_STOP_THRES_S) +#define HINF_SDCLK_STOP_THRES_V 0x000007FFU +#define HINF_SDCLK_STOP_THRES_S 16 +/** HINF_SAMPLE_CLK_DIVIDER : R/W; bitpos: [31:28]; default: 1; + * module clk divider to sample sdclk + */ +#define HINF_SAMPLE_CLK_DIVIDER 0x0000000FU +#define HINF_SAMPLE_CLK_DIVIDER_M (HINF_SAMPLE_CLK_DIVIDER_V << HINF_SAMPLE_CLK_DIVIDER_S) +#define HINF_SAMPLE_CLK_DIVIDER_V 0x0000000FU +#define HINF_SAMPLE_CLK_DIVIDER_S 28 + +/** HINF_CFG_UPDATE_REG register + * update sdio configurations + */ +#define HINF_CFG_UPDATE_REG (DR_REG_HINF_BASE + 0xc) +/** HINF_CONF_UPDATE : WT; bitpos: [0]; default: 0; + * update the timing configurations + */ +#define HINF_CONF_UPDATE (BIT(0)) +#define HINF_CONF_UPDATE_M (HINF_CONF_UPDATE_V << HINF_CONF_UPDATE_S) +#define HINF_CONF_UPDATE_V 0x00000001U +#define HINF_CONF_UPDATE_S 0 + +/** HINF_CFG_DATA7_REG register + * SDIO configuration register + */ +#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1c) +/** HINF_PIN_STATE : R/W; bitpos: [7:0]; default: 0; + * configure cis addr 318 and 574 + */ +#define HINF_PIN_STATE 0x000000FFU +#define HINF_PIN_STATE_M (HINF_PIN_STATE_V << HINF_PIN_STATE_S) +#define HINF_PIN_STATE_V 0x000000FFU +#define HINF_PIN_STATE_S 0 +/** HINF_CHIP_STATE : R/W; bitpos: [15:8]; default: 0; + * configure cis addr 312, 315, 568 and 571 + */ +#define HINF_CHIP_STATE 0x000000FFU +#define HINF_CHIP_STATE_M (HINF_CHIP_STATE_V << HINF_CHIP_STATE_S) +#define HINF_CHIP_STATE_V 0x000000FFU +#define HINF_CHIP_STATE_S 8 +/** HINF_SDIO_RST : R/W; bitpos: [16]; default: 0; + * soft reset control for sdio module + */ +#define HINF_SDIO_RST (BIT(16)) +#define HINF_SDIO_RST_M (HINF_SDIO_RST_V << HINF_SDIO_RST_S) +#define HINF_SDIO_RST_V 0x00000001U +#define HINF_SDIO_RST_S 16 +/** HINF_SDIO_IOREADY0 : R/W; bitpos: [17]; default: 1; + * sdio io ready, high enable + */ +#define HINF_SDIO_IOREADY0 (BIT(17)) +#define HINF_SDIO_IOREADY0_M (HINF_SDIO_IOREADY0_V << HINF_SDIO_IOREADY0_S) +#define HINF_SDIO_IOREADY0_V 0x00000001U +#define HINF_SDIO_IOREADY0_S 17 +/** HINF_SDIO_MEM_PD : R/W; bitpos: [18]; default: 0; + * sdio memory power down, high active + */ +#define HINF_SDIO_MEM_PD (BIT(18)) +#define HINF_SDIO_MEM_PD_M (HINF_SDIO_MEM_PD_V << HINF_SDIO_MEM_PD_S) +#define HINF_SDIO_MEM_PD_V 0x00000001U +#define HINF_SDIO_MEM_PD_S 18 +/** HINF_ESDIO_DATA1_INT_EN : R/W; bitpos: [19]; default: 0; + * enable sdio interrupt on data1 line + */ +#define HINF_ESDIO_DATA1_INT_EN (BIT(19)) +#define HINF_ESDIO_DATA1_INT_EN_M (HINF_ESDIO_DATA1_INT_EN_V << HINF_ESDIO_DATA1_INT_EN_S) +#define HINF_ESDIO_DATA1_INT_EN_V 0x00000001U +#define HINF_ESDIO_DATA1_INT_EN_S 19 +/** HINF_SDIO_SWITCH_VOLT_SW : R/W; bitpos: [20]; default: 0; + * control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V + */ +#define HINF_SDIO_SWITCH_VOLT_SW (BIT(20)) +#define HINF_SDIO_SWITCH_VOLT_SW_M (HINF_SDIO_SWITCH_VOLT_SW_V << HINF_SDIO_SWITCH_VOLT_SW_S) +#define HINF_SDIO_SWITCH_VOLT_SW_V 0x00000001U +#define HINF_SDIO_SWITCH_VOLT_SW_S 20 +/** HINF_DDR50_BLK_LEN_FIX_EN : R/W; bitpos: [21]; default: 0; + * enable block length to be fixed to 512 bytes in ddr50 mode + */ +#define HINF_DDR50_BLK_LEN_FIX_EN (BIT(21)) +#define HINF_DDR50_BLK_LEN_FIX_EN_M (HINF_DDR50_BLK_LEN_FIX_EN_V << HINF_DDR50_BLK_LEN_FIX_EN_S) +#define HINF_DDR50_BLK_LEN_FIX_EN_V 0x00000001U +#define HINF_DDR50_BLK_LEN_FIX_EN_S 21 +/** HINF_CLK_EN : R/W; bitpos: [22]; default: 0; + * sdio apb clock for configuration force on control:0-gating,1-force on. + */ +#define HINF_CLK_EN (BIT(22)) +#define HINF_CLK_EN_M (HINF_CLK_EN_V << HINF_CLK_EN_S) +#define HINF_CLK_EN_V 0x00000001U +#define HINF_CLK_EN_S 22 +/** HINF_SDDR50 : R/W; bitpos: [23]; default: 1; + * configure if support sdr50 mode in cccr + */ +#define HINF_SDDR50 (BIT(23)) +#define HINF_SDDR50_M (HINF_SDDR50_V << HINF_SDDR50_S) +#define HINF_SDDR50_V 0x00000001U +#define HINF_SDDR50_S 23 +/** HINF_SSDR104 : R/W; bitpos: [24]; default: 1; + * configure if support sdr104 mode in cccr + */ +#define HINF_SSDR104 (BIT(24)) +#define HINF_SSDR104_M (HINF_SSDR104_V << HINF_SSDR104_S) +#define HINF_SSDR104_V 0x00000001U +#define HINF_SSDR104_S 24 +/** HINF_SSDR50 : R/W; bitpos: [25]; default: 1; + * configure if support ddr50 mode in cccr + */ +#define HINF_SSDR50 (BIT(25)) +#define HINF_SSDR50_M (HINF_SSDR50_V << HINF_SSDR50_S) +#define HINF_SSDR50_V 0x00000001U +#define HINF_SSDR50_S 25 +/** HINF_SDTD : R/W; bitpos: [26]; default: 0; + * configure if support driver type D in cccr + */ +#define HINF_SDTD (BIT(26)) +#define HINF_SDTD_M (HINF_SDTD_V << HINF_SDTD_S) +#define HINF_SDTD_V 0x00000001U +#define HINF_SDTD_S 26 +/** HINF_SDTA : R/W; bitpos: [27]; default: 0; + * configure if support driver type A in cccr + */ +#define HINF_SDTA (BIT(27)) +#define HINF_SDTA_M (HINF_SDTA_V << HINF_SDTA_S) +#define HINF_SDTA_V 0x00000001U +#define HINF_SDTA_S 27 +/** HINF_SDTC : R/W; bitpos: [28]; default: 0; + * configure if support driver type C in cccr + */ +#define HINF_SDTC (BIT(28)) +#define HINF_SDTC_M (HINF_SDTC_V << HINF_SDTC_S) +#define HINF_SDTC_V 0x00000001U +#define HINF_SDTC_S 28 +/** HINF_SAI : R/W; bitpos: [29]; default: 1; + * configure if support asynchronous interrupt in cccr + */ +#define HINF_SAI (BIT(29)) +#define HINF_SAI_M (HINF_SAI_V << HINF_SAI_S) +#define HINF_SAI_V 0x00000001U +#define HINF_SAI_S 29 +/** HINF_SDIO_WAKEUP_CLR : R/W; bitpos: [30]; default: 0; + * clear sdio_wake_up signal after the chip wakes up + */ +#define HINF_SDIO_WAKEUP_CLR (BIT(30)) +#define HINF_SDIO_WAKEUP_CLR_M (HINF_SDIO_WAKEUP_CLR_V << HINF_SDIO_WAKEUP_CLR_S) +#define HINF_SDIO_WAKEUP_CLR_V 0x00000001U +#define HINF_SDIO_WAKEUP_CLR_S 30 + +/** HINF_CIS_CONF_W0_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W0_REG (DR_REG_HINF_BASE + 0x20) +/** HINF_CIS_CONF_W0 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 39~36 + */ +#define HINF_CIS_CONF_W0 0xFFFFFFFFU +#define HINF_CIS_CONF_W0_M (HINF_CIS_CONF_W0_V << HINF_CIS_CONF_W0_S) +#define HINF_CIS_CONF_W0_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W0_S 0 + +/** HINF_CIS_CONF_W1_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W1_REG (DR_REG_HINF_BASE + 0x24) +/** HINF_CIS_CONF_W1 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 43~40 + */ +#define HINF_CIS_CONF_W1 0xFFFFFFFFU +#define HINF_CIS_CONF_W1_M (HINF_CIS_CONF_W1_V << HINF_CIS_CONF_W1_S) +#define HINF_CIS_CONF_W1_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W1_S 0 + +/** HINF_CIS_CONF_W2_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W2_REG (DR_REG_HINF_BASE + 0x28) +/** HINF_CIS_CONF_W2 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 47~44 + */ +#define HINF_CIS_CONF_W2 0xFFFFFFFFU +#define HINF_CIS_CONF_W2_M (HINF_CIS_CONF_W2_V << HINF_CIS_CONF_W2_S) +#define HINF_CIS_CONF_W2_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W2_S 0 + +/** HINF_CIS_CONF_W3_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W3_REG (DR_REG_HINF_BASE + 0x2c) +/** HINF_CIS_CONF_W3 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 51~48 + */ +#define HINF_CIS_CONF_W3 0xFFFFFFFFU +#define HINF_CIS_CONF_W3_M (HINF_CIS_CONF_W3_V << HINF_CIS_CONF_W3_S) +#define HINF_CIS_CONF_W3_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W3_S 0 + +/** HINF_CIS_CONF_W4_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W4_REG (DR_REG_HINF_BASE + 0x30) +/** HINF_CIS_CONF_W4 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 55~52 + */ +#define HINF_CIS_CONF_W4 0xFFFFFFFFU +#define HINF_CIS_CONF_W4_M (HINF_CIS_CONF_W4_V << HINF_CIS_CONF_W4_S) +#define HINF_CIS_CONF_W4_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W4_S 0 + +/** HINF_CIS_CONF_W5_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W5_REG (DR_REG_HINF_BASE + 0x34) +/** HINF_CIS_CONF_W5 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 59~56 + */ +#define HINF_CIS_CONF_W5 0xFFFFFFFFU +#define HINF_CIS_CONF_W5_M (HINF_CIS_CONF_W5_V << HINF_CIS_CONF_W5_S) +#define HINF_CIS_CONF_W5_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W5_S 0 + +/** HINF_CIS_CONF_W6_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W6_REG (DR_REG_HINF_BASE + 0x38) +/** HINF_CIS_CONF_W6 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 63~60 + */ +#define HINF_CIS_CONF_W6 0xFFFFFFFFU +#define HINF_CIS_CONF_W6_M (HINF_CIS_CONF_W6_V << HINF_CIS_CONF_W6_S) +#define HINF_CIS_CONF_W6_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W6_S 0 + +/** HINF_CIS_CONF_W7_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W7_REG (DR_REG_HINF_BASE + 0x3c) +/** HINF_CIS_CONF_W7 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 67~64 + */ +#define HINF_CIS_CONF_W7 0xFFFFFFFFU +#define HINF_CIS_CONF_W7_M (HINF_CIS_CONF_W7_V << HINF_CIS_CONF_W7_S) +#define HINF_CIS_CONF_W7_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W7_S 0 + +/** HINF_CFG_DATA16_REG register + * SDIO cis configuration register + */ +#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40) +/** HINF_DEVICE_ID_FN2 : R/W; bitpos: [15:0]; default: 30583; + * configure device id of function2 in cis + */ +#define HINF_DEVICE_ID_FN2 0x0000FFFFU +#define HINF_DEVICE_ID_FN2_M (HINF_DEVICE_ID_FN2_V << HINF_DEVICE_ID_FN2_S) +#define HINF_DEVICE_ID_FN2_V 0x0000FFFFU +#define HINF_DEVICE_ID_FN2_S 0 +/** HINF_USER_ID_FN2 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function2 in cis + */ +#define HINF_USER_ID_FN2 0x0000FFFFU +#define HINF_USER_ID_FN2_M (HINF_USER_ID_FN2_V << HINF_USER_ID_FN2_S) +#define HINF_USER_ID_FN2_V 0x0000FFFFU +#define HINF_USER_ID_FN2_S 16 + +/** HINF_CFG_UHS1_INT_MODE_REG register + * configure int to start and end ahead of time in uhs1 mode + */ +#define HINF_CFG_UHS1_INT_MODE_REG (DR_REG_HINF_BASE + 0x44) +/** HINF_INTOE_END_AHEAD_MODE : R/W; bitpos: [1:0]; default: 0; + * intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INTOE_END_AHEAD_MODE 0x00000003U +#define HINF_INTOE_END_AHEAD_MODE_M (HINF_INTOE_END_AHEAD_MODE_V << HINF_INTOE_END_AHEAD_MODE_S) +#define HINF_INTOE_END_AHEAD_MODE_V 0x00000003U +#define HINF_INTOE_END_AHEAD_MODE_S 0 +/** HINF_INT_END_AHEAD_MODE : R/W; bitpos: [3:2]; default: 0; + * int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INT_END_AHEAD_MODE 0x00000003U +#define HINF_INT_END_AHEAD_MODE_M (HINF_INT_END_AHEAD_MODE_V << HINF_INT_END_AHEAD_MODE_S) +#define HINF_INT_END_AHEAD_MODE_V 0x00000003U +#define HINF_INT_END_AHEAD_MODE_S 2 +/** HINF_INTOE_ST_AHEAD_MODE : R/W; bitpos: [5:4]; default: 0; + * intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INTOE_ST_AHEAD_MODE 0x00000003U +#define HINF_INTOE_ST_AHEAD_MODE_M (HINF_INTOE_ST_AHEAD_MODE_V << HINF_INTOE_ST_AHEAD_MODE_S) +#define HINF_INTOE_ST_AHEAD_MODE_V 0x00000003U +#define HINF_INTOE_ST_AHEAD_MODE_S 4 +/** HINF_INT_ST_AHEAD_MODE : R/W; bitpos: [7:6]; default: 0; + * int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INT_ST_AHEAD_MODE 0x00000003U +#define HINF_INT_ST_AHEAD_MODE_M (HINF_INT_ST_AHEAD_MODE_V << HINF_INT_ST_AHEAD_MODE_S) +#define HINF_INT_ST_AHEAD_MODE_V 0x00000003U +#define HINF_INT_ST_AHEAD_MODE_S 6 + +/** HINF_CONF_STATUS_REG register + * func0 config0 status + */ +#define HINF_CONF_STATUS_REG (DR_REG_HINF_BASE + 0x54) +/** HINF_FUNC0_CONFIG0 : RO; bitpos: [7:0]; default: 0; + * func0 config0 (addr: 0x20f0 ) status + */ +#define HINF_FUNC0_CONFIG0 0x000000FFU +#define HINF_FUNC0_CONFIG0_M (HINF_FUNC0_CONFIG0_V << HINF_FUNC0_CONFIG0_S) +#define HINF_FUNC0_CONFIG0_V 0x000000FFU +#define HINF_FUNC0_CONFIG0_S 0 +/** HINF_SDR25_ST : RO; bitpos: [8]; default: 0; + * sdr25 status + */ +#define HINF_SDR25_ST (BIT(8)) +#define HINF_SDR25_ST_M (HINF_SDR25_ST_V << HINF_SDR25_ST_S) +#define HINF_SDR25_ST_V 0x00000001U +#define HINF_SDR25_ST_S 8 +/** HINF_SDR50_ST : RO; bitpos: [9]; default: 0; + * sdr50 status + */ +#define HINF_SDR50_ST (BIT(9)) +#define HINF_SDR50_ST_M (HINF_SDR50_ST_V << HINF_SDR50_ST_S) +#define HINF_SDR50_ST_V 0x00000001U +#define HINF_SDR50_ST_S 9 +/** HINF_SDR104_ST : RO; bitpos: [10]; default: 0; + * sdr104 status + */ +#define HINF_SDR104_ST (BIT(10)) +#define HINF_SDR104_ST_M (HINF_SDR104_ST_V << HINF_SDR104_ST_S) +#define HINF_SDR104_ST_V 0x00000001U +#define HINF_SDR104_ST_S 10 +/** HINF_DDR50_ST : RO; bitpos: [11]; default: 0; + * ddr50 status + */ +#define HINF_DDR50_ST (BIT(11)) +#define HINF_DDR50_ST_M (HINF_DDR50_ST_V << HINF_DDR50_ST_S) +#define HINF_DDR50_ST_V 0x00000001U +#define HINF_DDR50_ST_S 11 +/** HINF_TUNE_ST : RO; bitpos: [14:12]; default: 0; + * tune_st fsm status + */ +#define HINF_TUNE_ST 0x00000007U +#define HINF_TUNE_ST_M (HINF_TUNE_ST_V << HINF_TUNE_ST_S) +#define HINF_TUNE_ST_V 0x00000007U +#define HINF_TUNE_ST_S 12 +/** HINF_SDIO_SWITCH_VOLT_ST : RO; bitpos: [15]; default: 0; + * sdio switch voltage status:0-3.3V, 1-1.8V. + */ +#define HINF_SDIO_SWITCH_VOLT_ST (BIT(15)) +#define HINF_SDIO_SWITCH_VOLT_ST_M (HINF_SDIO_SWITCH_VOLT_ST_V << HINF_SDIO_SWITCH_VOLT_ST_S) +#define HINF_SDIO_SWITCH_VOLT_ST_V 0x00000001U +#define HINF_SDIO_SWITCH_VOLT_ST_S 15 +/** HINF_SDIO_SWITCH_END : RO; bitpos: [16]; default: 0; + * sdio switch voltage ldo ready + */ +#define HINF_SDIO_SWITCH_END (BIT(16)) +#define HINF_SDIO_SWITCH_END_M (HINF_SDIO_SWITCH_END_V << HINF_SDIO_SWITCH_END_S) +#define HINF_SDIO_SWITCH_END_V 0x00000001U +#define HINF_SDIO_SWITCH_END_S 16 + +/** HINF_SDIO_SLAVE_LDO_CONF_REG register + * sdio slave ldo control register + */ +#define HINF_SDIO_SLAVE_LDO_CONF_REG (DR_REG_HINF_BASE + 0xb0) +/** HINF_LDO_READY_CTL_IN_EN : R/W; bitpos: [0]; default: 0; + * control ldo ready signal by sdio slave itself + */ +#define HINF_LDO_READY_CTL_IN_EN (BIT(0)) +#define HINF_LDO_READY_CTL_IN_EN_M (HINF_LDO_READY_CTL_IN_EN_V << HINF_LDO_READY_CTL_IN_EN_S) +#define HINF_LDO_READY_CTL_IN_EN_V 0x00000001U +#define HINF_LDO_READY_CTL_IN_EN_S 0 +/** HINF_LDO_READY_THRES : R/W; bitpos: [5:1]; default: 10; + * configure ldo ready counting threshold value, the actual counting target is + * 2^(ldo_ready_thres)-1 + */ +#define HINF_LDO_READY_THRES 0x0000001FU +#define HINF_LDO_READY_THRES_M (HINF_LDO_READY_THRES_V << HINF_LDO_READY_THRES_S) +#define HINF_LDO_READY_THRES_V 0x0000001FU +#define HINF_LDO_READY_THRES_S 1 +/** HINF_LDO_READY_IGNORE_EN : R/W; bitpos: [6]; default: 0; + * ignore ldo ready signal + */ +#define HINF_LDO_READY_IGNORE_EN (BIT(6)) +#define HINF_LDO_READY_IGNORE_EN_M (HINF_LDO_READY_IGNORE_EN_V << HINF_LDO_READY_IGNORE_EN_S) +#define HINF_LDO_READY_IGNORE_EN_V 0x00000001U +#define HINF_LDO_READY_IGNORE_EN_S 6 + +/** HINF_SDIO_DATE_REG register + * ******* Description *********** + */ +#define HINF_SDIO_DATE_REG (DR_REG_HINF_BASE + 0xfc) +/** HINF_SDIO_DATE : R/W; bitpos: [31:0]; default: 37822544; + * sdio version date. + */ +#define HINF_SDIO_DATE 0xFFFFFFFFU +#define HINF_SDIO_DATE_M (HINF_SDIO_DATE_V << HINF_SDIO_DATE_S) +#define HINF_SDIO_DATE_V 0xFFFFFFFFU +#define HINF_SDIO_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/register/soc/sdio_hinf_struct.h b/components/soc/esp32c61/register/soc/sdio_hinf_struct.h new file mode 100644 index 0000000000..8b03a91781 --- /dev/null +++ b/components/soc/esp32c61/register/soc/sdio_hinf_struct.h @@ -0,0 +1,492 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration registers */ +/** Type of cfg_data0 register + * Configure sdio cis content + */ +typedef union { + struct { + /** device_id_fn1 : R/W; bitpos: [15:0]; default: 26214; + * configure device id of function1 in cis + */ + uint32_t device_id_fn1:16; + /** user_id_fn1 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function1 in cis + */ + uint32_t user_id_fn1:16; + }; + uint32_t val; +} hinf_cfg_data0_reg_t; + +/** Type of cfg_data1 register + * SDIO configuration register + */ +typedef union { + struct { + /** sdio_enable : R/W; bitpos: [0]; default: 1; + * Sdio clock enable + */ + uint32_t sdio_enable:1; + /** sdio_ioready1 : R/W; bitpos: [1]; default: 0; + * sdio function1 io ready signal in cis + */ + uint32_t sdio_ioready1:1; + /** highspeed_enable : R/W; bitpos: [2]; default: 0; + * Highspeed enable in cccr + */ + uint32_t highspeed_enable:1; + /** highspeed_mode : RO; bitpos: [3]; default: 0; + * highspeed mode status in cccr + */ + uint32_t highspeed_mode:1; + /** sdio_cd_enable : R/W; bitpos: [4]; default: 1; + * sdio card detect enable + */ + uint32_t sdio_cd_enable:1; + /** sdio_ioready2 : R/W; bitpos: [5]; default: 0; + * sdio function1 io ready signal in cis + */ + uint32_t sdio_ioready2:1; + /** sdio_int_mask : R/W; bitpos: [6]; default: 0; + * mask sdio interrupt in cccr, high active + */ + uint32_t sdio_int_mask:1; + /** ioenable2 : RO; bitpos: [7]; default: 0; + * ioe2 status in cccr + */ + uint32_t ioenable2:1; + /** cd_disable : RO; bitpos: [8]; default: 0; + * card disable status in cccr + */ + uint32_t cd_disable:1; + /** func1_eps : RO; bitpos: [9]; default: 0; + * function1 eps status in fbr + */ + uint32_t func1_eps:1; + /** emp : RO; bitpos: [10]; default: 0; + * empc status in cccr + */ + uint32_t emp:1; + /** ioenable1 : RO; bitpos: [11]; default: 0; + * ioe1 status in cccr + */ + uint32_t ioenable1:1; + /** sdio_ver : R/W; bitpos: [23:12]; default: 562; + * sdio version in cccr + */ + uint32_t sdio_ver:12; + /** func2_eps : RO; bitpos: [24]; default: 0; + * function2 eps status in fbr + */ + uint32_t func2_eps:1; + /** sdio20_conf : R/W; bitpos: [31:25]; default: 0; + * [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat + * in delayed cycles control,0:no delay, 1:delay 1 cycle. + * [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed + * mode. + * [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when + * [12]=0,posedge when highspeed mode enable. + * [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay. + * [28]: sdio data pad pull up enable + */ + uint32_t sdio20_conf:7; + }; + uint32_t val; +} hinf_cfg_data1_reg_t; + +/** Type of cfg_timing register + * Timing configuration registers + */ +typedef union { + struct { + /** ncrc : R/W; bitpos: [2:0]; default: 2; + * configure Ncrc parameter in sdr50/104 mode, no more than 6. + */ + uint32_t ncrc:3; + /** pst_end_cmd_low_value : R/W; bitpos: [9:3]; default: 2; + * configure cycles to lower cmd after voltage is changed to 1.8V. + */ + uint32_t pst_end_cmd_low_value:7; + /** pst_end_data_low_value : R/W; bitpos: [15:10]; default: 2; + * configure cycles to lower data after voltage is changed to 1.8V. + */ + uint32_t pst_end_data_low_value:6; + /** sdclk_stop_thres : R/W; bitpos: [26:16]; default: 1400; + * Configure the number of cycles of module clk to judge sdclk has stopped + */ + uint32_t sdclk_stop_thres:11; + uint32_t reserved_27:1; + /** sample_clk_divider : R/W; bitpos: [31:28]; default: 1; + * module clk divider to sample sdclk + */ + uint32_t sample_clk_divider:4; + }; + uint32_t val; +} hinf_cfg_timing_reg_t; + +/** Type of cfg_update register + * update sdio configurations + */ +typedef union { + struct { + /** conf_update : WT; bitpos: [0]; default: 0; + * update the timing configurations + */ + uint32_t conf_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hinf_cfg_update_reg_t; + +/** Type of cfg_data7 register + * SDIO configuration register + */ +typedef union { + struct { + /** pin_state : R/W; bitpos: [7:0]; default: 0; + * configure cis addr 318 and 574 + */ + uint32_t pin_state:8; + /** chip_state : R/W; bitpos: [15:8]; default: 0; + * configure cis addr 312, 315, 568 and 571 + */ + uint32_t chip_state:8; + /** sdio_rst : R/W; bitpos: [16]; default: 0; + * soft reset control for sdio module + */ + uint32_t sdio_rst:1; + /** sdio_ioready0 : R/W; bitpos: [17]; default: 1; + * sdio io ready, high enable + */ + uint32_t sdio_ioready0:1; + /** sdio_mem_pd : R/W; bitpos: [18]; default: 0; + * sdio memory power down, high active + */ + uint32_t sdio_mem_pd:1; + /** esdio_data1_int_en : R/W; bitpos: [19]; default: 0; + * enable sdio interrupt on data1 line + */ + uint32_t esdio_data1_int_en:1; + /** sdio_switch_volt_sw : R/W; bitpos: [20]; default: 0; + * control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V + */ + uint32_t sdio_switch_volt_sw:1; + /** ddr50_blk_len_fix_en : R/W; bitpos: [21]; default: 0; + * enable block length to be fixed to 512 bytes in ddr50 mode + */ + uint32_t ddr50_blk_len_fix_en:1; + /** clk_en : R/W; bitpos: [22]; default: 0; + * sdio apb clock for configuration force on control:0-gating,1-force on. + */ + uint32_t clk_en:1; + /** sddr50 : R/W; bitpos: [23]; default: 1; + * configure if support sdr50 mode in cccr + */ + uint32_t sddr50:1; + /** ssdr104 : R/W; bitpos: [24]; default: 1; + * configure if support sdr104 mode in cccr + */ + uint32_t ssdr104:1; + /** ssdr50 : R/W; bitpos: [25]; default: 1; + * configure if support ddr50 mode in cccr + */ + uint32_t ssdr50:1; + /** sdtd : R/W; bitpos: [26]; default: 0; + * configure if support driver type D in cccr + */ + uint32_t sdtd:1; + /** sdta : R/W; bitpos: [27]; default: 0; + * configure if support driver type A in cccr + */ + uint32_t sdta:1; + /** sdtc : R/W; bitpos: [28]; default: 0; + * configure if support driver type C in cccr + */ + uint32_t sdtc:1; + /** sai : R/W; bitpos: [29]; default: 1; + * configure if support asynchronous interrupt in cccr + */ + uint32_t sai:1; + /** sdio_wakeup_clr : R/W; bitpos: [30]; default: 0; + * clear sdio_wake_up signal after the chip wakes up + */ + uint32_t sdio_wakeup_clr:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} hinf_cfg_data7_reg_t; + +/** Type of cis_conf_w0 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w0 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 39~36 + */ + uint32_t cis_conf_w0:32; + }; + uint32_t val; +} hinf_cis_conf_w0_reg_t; + +/** Type of cis_conf_w1 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w1 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 43~40 + */ + uint32_t cis_conf_w1:32; + }; + uint32_t val; +} hinf_cis_conf_w1_reg_t; + +/** Type of cis_conf_w2 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w2 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 47~44 + */ + uint32_t cis_conf_w2:32; + }; + uint32_t val; +} hinf_cis_conf_w2_reg_t; + +/** Type of cis_conf_w3 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w3 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 51~48 + */ + uint32_t cis_conf_w3:32; + }; + uint32_t val; +} hinf_cis_conf_w3_reg_t; + +/** Type of cis_conf_w4 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w4 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 55~52 + */ + uint32_t cis_conf_w4:32; + }; + uint32_t val; +} hinf_cis_conf_w4_reg_t; + +/** Type of cis_conf_w5 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w5 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 59~56 + */ + uint32_t cis_conf_w5:32; + }; + uint32_t val; +} hinf_cis_conf_w5_reg_t; + +/** Type of cis_conf_w6 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w6 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 63~60 + */ + uint32_t cis_conf_w6:32; + }; + uint32_t val; +} hinf_cis_conf_w6_reg_t; + +/** Type of cis_conf_w7 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w7 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 67~64 + */ + uint32_t cis_conf_w7:32; + }; + uint32_t val; +} hinf_cis_conf_w7_reg_t; + +/** Type of cfg_data16 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** device_id_fn2 : R/W; bitpos: [15:0]; default: 30583; + * configure device id of function2 in cis + */ + uint32_t device_id_fn2:16; + /** user_id_fn2 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function2 in cis + */ + uint32_t user_id_fn2:16; + }; + uint32_t val; +} hinf_cfg_data16_reg_t; + +/** Type of cfg_uhs1_int_mode register + * configure int to start and end ahead of time in uhs1 mode + */ +typedef union { + struct { + /** intoe_end_ahead_mode : R/W; bitpos: [1:0]; default: 0; + * intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t intoe_end_ahead_mode:2; + /** int_end_ahead_mode : R/W; bitpos: [3:2]; default: 0; + * int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t int_end_ahead_mode:2; + /** intoe_st_ahead_mode : R/W; bitpos: [5:4]; default: 0; + * intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t intoe_st_ahead_mode:2; + /** int_st_ahead_mode : R/W; bitpos: [7:6]; default: 0; + * int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t int_st_ahead_mode:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} hinf_cfg_uhs1_int_mode_reg_t; + +/** Type of sdio_slave_ldo_conf register + * sdio slave ldo control register + */ +typedef union { + struct { + /** ldo_ready_ctl_in_en : R/W; bitpos: [0]; default: 0; + * control ldo ready signal by sdio slave itself + */ + uint32_t ldo_ready_ctl_in_en:1; + /** ldo_ready_thres : R/W; bitpos: [5:1]; default: 10; + * configure ldo ready counting threshold value, the actual counting target is + * 2^(ldo_ready_thres)-1 + */ + uint32_t ldo_ready_thres:5; + /** ldo_ready_ignore_en : R/W; bitpos: [6]; default: 0; + * ignore ldo ready signal + */ + uint32_t ldo_ready_ignore_en:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} hinf_sdio_slave_ldo_conf_reg_t; + + +/** Group: Status registers */ +/** Type of conf_status register + * func0 config0 status + */ +typedef union { + struct { + /** func0_config0 : RO; bitpos: [7:0]; default: 0; + * func0 config0 (addr: 0x20f0 ) status + */ + uint32_t func0_config0:8; + /** sdr25_st : RO; bitpos: [8]; default: 0; + * sdr25 status + */ + uint32_t sdr25_st:1; + /** sdr50_st : RO; bitpos: [9]; default: 0; + * sdr50 status + */ + uint32_t sdr50_st:1; + /** sdr104_st : RO; bitpos: [10]; default: 0; + * sdr104 status + */ + uint32_t sdr104_st:1; + /** ddr50_st : RO; bitpos: [11]; default: 0; + * ddr50 status + */ + uint32_t ddr50_st:1; + /** tune_st : RO; bitpos: [14:12]; default: 0; + * tune_st fsm status + */ + uint32_t tune_st:3; + /** sdio_switch_volt_st : RO; bitpos: [15]; default: 0; + * sdio switch voltage status:0-3.3V, 1-1.8V. + */ + uint32_t sdio_switch_volt_st:1; + /** sdio_switch_end : RO; bitpos: [16]; default: 0; + * sdio switch voltage ldo ready + */ + uint32_t sdio_switch_end:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} hinf_conf_status_reg_t; + + +/** Group: Version register */ +/** Type of sdio_date register + * ******* Description *********** + */ +typedef union { + struct { + /** sdio_date : R/W; bitpos: [31:0]; default: 37822544; + * sdio version date. + */ + uint32_t sdio_date:32; + }; + uint32_t val; +} hinf_sdio_date_reg_t; + + +typedef struct { + volatile hinf_cfg_data0_reg_t cfg_data0; + volatile hinf_cfg_data1_reg_t cfg_data1; + volatile hinf_cfg_timing_reg_t cfg_timing; + volatile hinf_cfg_update_reg_t cfg_update; + uint32_t reserved_010[3]; + volatile hinf_cfg_data7_reg_t cfg_data7; + volatile hinf_cis_conf_w0_reg_t cis_conf_w0; + volatile hinf_cis_conf_w1_reg_t cis_conf_w1; + volatile hinf_cis_conf_w2_reg_t cis_conf_w2; + volatile hinf_cis_conf_w3_reg_t cis_conf_w3; + volatile hinf_cis_conf_w4_reg_t cis_conf_w4; + volatile hinf_cis_conf_w5_reg_t cis_conf_w5; + volatile hinf_cis_conf_w6_reg_t cis_conf_w6; + volatile hinf_cis_conf_w7_reg_t cis_conf_w7; + volatile hinf_cfg_data16_reg_t cfg_data16; + volatile hinf_cfg_uhs1_int_mode_reg_t cfg_uhs1_int_mode; + uint32_t reserved_048[3]; + volatile hinf_conf_status_reg_t conf_status; + uint32_t reserved_058[22]; + volatile hinf_sdio_slave_ldo_conf_reg_t sdio_slave_ldo_conf; + uint32_t reserved_0b4[18]; + volatile hinf_sdio_date_reg_t sdio_date; +} hinf_dev_t; + +extern hinf_dev_t HINF; + +#ifndef __cplusplus +_Static_assert(sizeof(hinf_dev_t) == 0x100, "Invalid size of hinf_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/register/soc/sdio_slc_host_reg.h b/components/soc/esp32c61/register/soc/sdio_slc_host_reg.h new file mode 100644 index 0000000000..71fb89c394 --- /dev/null +++ b/components/soc/esp32c61/register/soc/sdio_slc_host_reg.h @@ -0,0 +1,3883 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SDIO_SLC_HOST_FUNC2_0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_FUNC2_0_REG (DR_REG_HOST_BASE + 0x10) +/** SDIO_SLCHOST_SLC_FUNC2_INT : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC_FUNC2_INT (BIT(24)) +#define SDIO_SLCHOST_SLC_FUNC2_INT_M (SDIO_SLCHOST_SLC_FUNC2_INT_V << SDIO_SLCHOST_SLC_FUNC2_INT_S) +#define SDIO_SLCHOST_SLC_FUNC2_INT_V 0x00000001U +#define SDIO_SLCHOST_SLC_FUNC2_INT_S 24 + +/** SDIO_SLC_HOST_FUNC2_1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_FUNC2_1_REG (DR_REG_HOST_BASE + 0x14) +/** SDIO_SLCHOST_SLC_FUNC2_INT_EN : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC_FUNC2_INT_EN (BIT(0)) +#define SDIO_SLCHOST_SLC_FUNC2_INT_EN_M (SDIO_SLCHOST_SLC_FUNC2_INT_EN_V << SDIO_SLCHOST_SLC_FUNC2_INT_EN_S) +#define SDIO_SLCHOST_SLC_FUNC2_INT_EN_V 0x00000001U +#define SDIO_SLCHOST_SLC_FUNC2_INT_EN_S 0 + +/** SDIO_SLC_HOST_FUNC2_2_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_FUNC2_2_REG (DR_REG_HOST_BASE + 0x20) +/** SDIO_SLCHOST_SLC_FUNC1_MDSTAT : R/W; bitpos: [0]; default: 1; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC_FUNC1_MDSTAT (BIT(0)) +#define SDIO_SLCHOST_SLC_FUNC1_MDSTAT_M (SDIO_SLCHOST_SLC_FUNC1_MDSTAT_V << SDIO_SLCHOST_SLC_FUNC1_MDSTAT_S) +#define SDIO_SLCHOST_SLC_FUNC1_MDSTAT_V 0x00000001U +#define SDIO_SLCHOST_SLC_FUNC1_MDSTAT_S 0 + +/** SDIO_SLC_HOST_GPIO_STATUS0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_STATUS0_REG (DR_REG_HOST_BASE + 0x34) +/** SDIO_SLCHOST_GPIO_SDIO_INT0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_GPIO_SDIO_INT0 0xFFFFFFFFU +#define SDIO_SLCHOST_GPIO_SDIO_INT0_M (SDIO_SLCHOST_GPIO_SDIO_INT0_V << SDIO_SLCHOST_GPIO_SDIO_INT0_S) +#define SDIO_SLCHOST_GPIO_SDIO_INT0_V 0xFFFFFFFFU +#define SDIO_SLCHOST_GPIO_SDIO_INT0_S 0 + +/** SDIO_SLC_HOST_GPIO_STATUS1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_STATUS1_REG (DR_REG_HOST_BASE + 0x38) +/** SDIO_SLCHOST_GPIO_SDIO_INT1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_GPIO_SDIO_INT1 0xFFFFFFFFU +#define SDIO_SLCHOST_GPIO_SDIO_INT1_M (SDIO_SLCHOST_GPIO_SDIO_INT1_V << SDIO_SLCHOST_GPIO_SDIO_INT1_S) +#define SDIO_SLCHOST_GPIO_SDIO_INT1_V 0xFFFFFFFFU +#define SDIO_SLCHOST_GPIO_SDIO_INT1_S 0 + +/** SDIO_SLC_HOST_GPIO_IN0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_IN0_REG (DR_REG_HOST_BASE + 0x3c) +/** SDIO_SLCHOST_GPIO_SDIO_IN0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_GPIO_SDIO_IN0 0xFFFFFFFFU +#define SDIO_SLCHOST_GPIO_SDIO_IN0_M (SDIO_SLCHOST_GPIO_SDIO_IN0_V << SDIO_SLCHOST_GPIO_SDIO_IN0_S) +#define SDIO_SLCHOST_GPIO_SDIO_IN0_V 0xFFFFFFFFU +#define SDIO_SLCHOST_GPIO_SDIO_IN0_S 0 + +/** SDIO_SLC_HOST_GPIO_IN1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_IN1_REG (DR_REG_HOST_BASE + 0x40) +/** SDIO_SLCHOST_GPIO_SDIO_IN1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_GPIO_SDIO_IN1 0xFFFFFFFFU +#define SDIO_SLCHOST_GPIO_SDIO_IN1_M (SDIO_SLCHOST_GPIO_SDIO_IN1_V << SDIO_SLCHOST_GPIO_SDIO_IN1_S) +#define SDIO_SLCHOST_GPIO_SDIO_IN1_V 0xFFFFFFFFU +#define SDIO_SLCHOST_GPIO_SDIO_IN1_S 0 + +/** SDIO_SLC_HOST_SLC0HOST_TOKEN_RDATA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_HOST_BASE + 0x44) +/** SDIO_SLCHOST_SLC0_TOKEN0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0 0x00000FFFU +#define SDIO_SLCHOST_SLC0_TOKEN0_M (SDIO_SLCHOST_SLC0_TOKEN0_V << SDIO_SLCHOST_SLC0_TOKEN0_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_V 0x00000FFFU +#define SDIO_SLCHOST_SLC0_TOKEN0_S 0 +/** SDIO_SLCHOST_SLC0_RX_PF_VALID : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_PF_VALID (BIT(12)) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_M (SDIO_SLCHOST_SLC0_RX_PF_VALID_V << SDIO_SLCHOST_SLC0_RX_PF_VALID_S) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_S 12 +/** SDIO_SLCHOST_HOSTSLCHOST_SLC0_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_TOKEN1 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_M (SDIO_SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_V << SDIO_SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_V 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_S 16 +/** SDIO_SLCHOST_SLC0_RX_PF_EOF : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_PF_EOF 0x0000000FU +#define SDIO_SLCHOST_SLC0_RX_PF_EOF_M (SDIO_SLCHOST_SLC0_RX_PF_EOF_V << SDIO_SLCHOST_SLC0_RX_PF_EOF_S) +#define SDIO_SLCHOST_SLC0_RX_PF_EOF_V 0x0000000FU +#define SDIO_SLCHOST_SLC0_RX_PF_EOF_S 28 + +/** SDIO_SLC_HOST_SLC0_HOST_PF_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_HOST_PF_REG (DR_REG_HOST_BASE + 0x48) +/** SDIO_SLCHOST_SLC0_PF_DATA : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_PF_DATA 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC0_PF_DATA_M (SDIO_SLCHOST_SLC0_PF_DATA_V << SDIO_SLCHOST_SLC0_PF_DATA_S) +#define SDIO_SLCHOST_SLC0_PF_DATA_V 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC0_PF_DATA_S 0 + +/** SDIO_SLC_HOST_SLC1_HOST_PF_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_HOST_PF_REG (DR_REG_HOST_BASE + 0x4c) +/** SDIO_SLCHOST_SLC1_PF_DATA : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_PF_DATA 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC1_PF_DATA_M (SDIO_SLCHOST_SLC1_PF_DATA_V << SDIO_SLCHOST_SLC1_PF_DATA_S) +#define SDIO_SLCHOST_SLC1_PF_DATA_V 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC1_PF_DATA_S 0 + +/** SDIO_SLC_HOST_SLC0HOST_INT_RAW_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_INT_RAW_REG (DR_REG_HOST_BASE + 0x50) +/** SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_RAW (BIT(0)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_M (SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_V << SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_S 0 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_RAW (BIT(1)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_M (SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_V << SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_S 1 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_RAW (BIT(2)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_M (SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_V << SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_S 2 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_RAW (BIT(3)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_M (SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_V << SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_S 3 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_RAW (BIT(4)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_M (SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_V << SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_S 4 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_RAW (BIT(5)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_M (SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_V << SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_S 5 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_RAW : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_RAW (BIT(6)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_M (SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_V << SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_S 6 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_RAW : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_RAW (BIT(7)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_M (SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_V << SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_S 7 +/** SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW (BIT(8)) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_M (SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_V << SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_S 8 +/** SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW (BIT(9)) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_M (SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_V << SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_S 9 +/** SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW (BIT(10)) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_M (SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_V << SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_S 10 +/** SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW (BIT(11)) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_M (SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_V << SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_S 11 +/** SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_RAW (BIT(12)) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_RAW_M (SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_RAW_V << SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_RAW_S) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_RAW_S 12 +/** SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_RAW (BIT(13)) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_RAW_M (SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_RAW_V << SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_RAW_S) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_RAW_S 13 +/** SDIO_SLCHOST_SLC0HOST_RX_START_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_RAW (BIT(14)) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_RAW_M (SDIO_SLCHOST_SLC0HOST_RX_START_INT_RAW_V << SDIO_SLCHOST_SLC0HOST_RX_START_INT_RAW_S) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_RAW_S 14 +/** SDIO_SLCHOST_SLC0HOST_TX_START_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_RAW (BIT(15)) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_RAW_M (SDIO_SLCHOST_SLC0HOST_TX_START_INT_RAW_V << SDIO_SLCHOST_SLC0HOST_TX_START_INT_RAW_S) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_RAW_S 15 +/** SDIO_SLCHOST_SLC0_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_RAW (BIT(16)) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_RAW_M (SDIO_SLCHOST_SLC0_RX_UDF_INT_RAW_V << SDIO_SLCHOST_SLC0_RX_UDF_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_RAW_S 16 +/** SDIO_SLCHOST_SLC0_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_RAW (BIT(17)) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_RAW_M (SDIO_SLCHOST_SLC0_TX_OVF_INT_RAW_V << SDIO_SLCHOST_SLC0_TX_OVF_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_RAW_S 17 +/** SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_RAW (BIT(18)) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_RAW_M (SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_RAW_V << SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_RAW_S 18 +/** SDIO_SLCHOST_SLC0_EXT_BIT0_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_RAW (BIT(19)) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_RAW_M (SDIO_SLCHOST_SLC0_EXT_BIT0_INT_RAW_V << SDIO_SLCHOST_SLC0_EXT_BIT0_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_RAW_S 19 +/** SDIO_SLCHOST_SLC0_EXT_BIT1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_RAW (BIT(20)) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_RAW_M (SDIO_SLCHOST_SLC0_EXT_BIT1_INT_RAW_V << SDIO_SLCHOST_SLC0_EXT_BIT1_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_RAW_S 20 +/** SDIO_SLCHOST_SLC0_EXT_BIT2_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_RAW (BIT(21)) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_RAW_M (SDIO_SLCHOST_SLC0_EXT_BIT2_INT_RAW_V << SDIO_SLCHOST_SLC0_EXT_BIT2_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_RAW_S 21 +/** SDIO_SLCHOST_SLC0_EXT_BIT3_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_RAW (BIT(22)) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_RAW_M (SDIO_SLCHOST_SLC0_EXT_BIT3_INT_RAW_V << SDIO_SLCHOST_SLC0_EXT_BIT3_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_RAW_S 22 +/** SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW (BIT(23)) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_M (SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_V << SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_S 23 +/** SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW (BIT(24)) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_M (SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_V << SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_S 24 +/** SDIO_SLCHOST_GPIO_SDIO_INT_RAW : R/WTC/SS/SC; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_GPIO_SDIO_INT_RAW (BIT(25)) +#define SDIO_SLCHOST_GPIO_SDIO_INT_RAW_M (SDIO_SLCHOST_GPIO_SDIO_INT_RAW_V << SDIO_SLCHOST_GPIO_SDIO_INT_RAW_S) +#define SDIO_SLCHOST_GPIO_SDIO_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_GPIO_SDIO_INT_RAW_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_INT_RAW_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_INT_RAW_REG (DR_REG_HOST_BASE + 0x54) +/** SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_RAW (BIT(0)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_M (SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_V << SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_S 0 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_RAW (BIT(1)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_M (SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_V << SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_S 1 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_RAW (BIT(2)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_M (SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_V << SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_S 2 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_RAW (BIT(3)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_M (SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_V << SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_S 3 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_RAW (BIT(4)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_M (SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_V << SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_S 4 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_RAW (BIT(5)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_M (SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_V << SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_S 5 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_RAW : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_RAW (BIT(6)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_M (SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_V << SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_S 6 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_RAW : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_RAW (BIT(7)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_M (SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_V << SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_S 7 +/** SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW (BIT(8)) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_M (SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_V << SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_S 8 +/** SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW (BIT(9)) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_M (SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_V << SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_S 9 +/** SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW (BIT(10)) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_M (SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_V << SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_S 10 +/** SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW (BIT(11)) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_M (SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_V << SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_S 11 +/** SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_RAW (BIT(12)) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_RAW_M (SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_RAW_V << SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_RAW_S) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_RAW_S 12 +/** SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_RAW (BIT(13)) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_RAW_M (SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_RAW_V << SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_RAW_S) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_RAW_S 13 +/** SDIO_SLCHOST_SLC1HOST_RX_START_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_RAW (BIT(14)) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_RAW_M (SDIO_SLCHOST_SLC1HOST_RX_START_INT_RAW_V << SDIO_SLCHOST_SLC1HOST_RX_START_INT_RAW_S) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_RAW_S 14 +/** SDIO_SLCHOST_SLC1HOST_TX_START_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_RAW (BIT(15)) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_RAW_M (SDIO_SLCHOST_SLC1HOST_TX_START_INT_RAW_V << SDIO_SLCHOST_SLC1HOST_TX_START_INT_RAW_S) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_RAW_S 15 +/** SDIO_SLCHOST_SLC1_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_RAW (BIT(16)) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_RAW_M (SDIO_SLCHOST_SLC1_RX_UDF_INT_RAW_V << SDIO_SLCHOST_SLC1_RX_UDF_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_RAW_S 16 +/** SDIO_SLCHOST_SLC1_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_RAW (BIT(17)) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_RAW_M (SDIO_SLCHOST_SLC1_TX_OVF_INT_RAW_V << SDIO_SLCHOST_SLC1_TX_OVF_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_RAW_S 17 +/** SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_RAW (BIT(18)) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_RAW_M (SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_RAW_V << SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_RAW_S 18 +/** SDIO_SLCHOST_SLC1_EXT_BIT0_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_RAW (BIT(19)) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_RAW_M (SDIO_SLCHOST_SLC1_EXT_BIT0_INT_RAW_V << SDIO_SLCHOST_SLC1_EXT_BIT0_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_RAW_S 19 +/** SDIO_SLCHOST_SLC1_EXT_BIT1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_RAW (BIT(20)) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_RAW_M (SDIO_SLCHOST_SLC1_EXT_BIT1_INT_RAW_V << SDIO_SLCHOST_SLC1_EXT_BIT1_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_RAW_S 20 +/** SDIO_SLCHOST_SLC1_EXT_BIT2_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_RAW (BIT(21)) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_RAW_M (SDIO_SLCHOST_SLC1_EXT_BIT2_INT_RAW_V << SDIO_SLCHOST_SLC1_EXT_BIT2_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_RAW_S 21 +/** SDIO_SLCHOST_SLC1_EXT_BIT3_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_RAW (BIT(22)) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_RAW_M (SDIO_SLCHOST_SLC1_EXT_BIT3_INT_RAW_V << SDIO_SLCHOST_SLC1_EXT_BIT3_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_RAW_S 22 +/** SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW (BIT(23)) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_M (SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V << SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S 23 +/** SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW (BIT(24)) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_M (SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_V << SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_S 24 +/** SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW (BIT(25)) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_M (SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V << SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S 25 + +/** SDIO_SLC_HOST_SLC0HOST_INT_ST_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_INT_ST_REG (DR_REG_HOST_BASE + 0x58) +/** SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ST (BIT(0)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ST_M (SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ST_V << SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ST_S 0 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ST (BIT(1)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ST_M (SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ST_V << SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ST_S 1 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ST (BIT(2)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ST_M (SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ST_V << SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ST_S 2 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ST (BIT(3)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ST_M (SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ST_V << SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ST_S 3 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ST (BIT(4)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ST_M (SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ST_V << SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ST_S 4 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ST (BIT(5)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ST_M (SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ST_V << SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ST_S 5 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ST (BIT(6)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ST_M (SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ST_V << SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ST_S 6 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ST (BIT(7)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ST_M (SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ST_V << SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ST_S 7 +/** SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ST : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ST (BIT(8)) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_M (SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_V << SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_S 8 +/** SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ST : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ST (BIT(9)) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_M (SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_V << SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_S 9 +/** SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ST : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ST (BIT(10)) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_M (SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_V << SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_S 10 +/** SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ST : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ST (BIT(11)) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_M (SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_V << SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_S 11 +/** SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ST : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ST (BIT(12)) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ST_M (SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ST_V << SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ST_S) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ST_S 12 +/** SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ST : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ST (BIT(13)) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ST_M (SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ST_V << SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ST_S) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ST_S 13 +/** SDIO_SLCHOST_SLC0HOST_RX_START_INT_ST : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ST (BIT(14)) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ST_M (SDIO_SLCHOST_SLC0HOST_RX_START_INT_ST_V << SDIO_SLCHOST_SLC0HOST_RX_START_INT_ST_S) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ST_S 14 +/** SDIO_SLCHOST_SLC0HOST_TX_START_INT_ST : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ST (BIT(15)) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ST_M (SDIO_SLCHOST_SLC0HOST_TX_START_INT_ST_V << SDIO_SLCHOST_SLC0HOST_TX_START_INT_ST_S) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ST_S 15 +/** SDIO_SLCHOST_SLC0_RX_UDF_INT_ST : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ST (BIT(16)) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ST_M (SDIO_SLCHOST_SLC0_RX_UDF_INT_ST_V << SDIO_SLCHOST_SLC0_RX_UDF_INT_ST_S) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ST_S 16 +/** SDIO_SLCHOST_SLC0_TX_OVF_INT_ST : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ST (BIT(17)) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ST_M (SDIO_SLCHOST_SLC0_TX_OVF_INT_ST_V << SDIO_SLCHOST_SLC0_TX_OVF_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ST_S 17 +/** SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ST : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ST (BIT(18)) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ST_M (SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ST_V << SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ST_S) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ST_S 18 +/** SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ST : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ST (BIT(19)) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ST_M (SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ST_V << SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ST_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ST_S 19 +/** SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ST : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ST (BIT(20)) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ST_M (SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ST_V << SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ST_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ST_S 20 +/** SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ST : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ST (BIT(21)) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ST_M (SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ST_V << SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ST_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ST_S 21 +/** SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ST : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ST (BIT(22)) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ST_M (SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ST_V << SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ST_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ST_S 22 +/** SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ST : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ST (BIT(23)) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_M (SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_V << SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_S) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_S 23 +/** SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ST : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ST (BIT(24)) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_M (SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_V << SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_S) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_S 24 +/** SDIO_SLCHOST_GPIO_SDIO_INT_ST : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_GPIO_SDIO_INT_ST (BIT(25)) +#define SDIO_SLCHOST_GPIO_SDIO_INT_ST_M (SDIO_SLCHOST_GPIO_SDIO_INT_ST_V << SDIO_SLCHOST_GPIO_SDIO_INT_ST_S) +#define SDIO_SLCHOST_GPIO_SDIO_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_GPIO_SDIO_INT_ST_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_INT_ST_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_INT_ST_REG (DR_REG_HOST_BASE + 0x5c) +/** SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ST (BIT(0)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ST_M (SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ST_V << SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ST_S 0 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ST (BIT(1)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ST_M (SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ST_V << SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ST_S 1 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ST (BIT(2)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ST_M (SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ST_V << SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ST_S 2 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ST (BIT(3)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ST_M (SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ST_V << SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ST_S 3 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ST (BIT(4)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ST_M (SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ST_V << SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ST_S 4 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ST (BIT(5)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ST_M (SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ST_V << SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ST_S 5 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ST (BIT(6)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ST_M (SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ST_V << SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ST_S 6 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ST (BIT(7)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ST_M (SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ST_V << SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ST_S 7 +/** SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ST : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ST (BIT(8)) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_M (SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_V << SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_S 8 +/** SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ST : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ST (BIT(9)) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_M (SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_V << SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_S 9 +/** SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ST : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ST (BIT(10)) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_M (SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_V << SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_S 10 +/** SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ST : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ST (BIT(11)) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_M (SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_V << SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_S 11 +/** SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ST : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ST (BIT(12)) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ST_M (SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ST_V << SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ST_S) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ST_S 12 +/** SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ST : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ST (BIT(13)) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ST_M (SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ST_V << SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ST_S) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ST_S 13 +/** SDIO_SLCHOST_SLC1HOST_RX_START_INT_ST : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ST (BIT(14)) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ST_M (SDIO_SLCHOST_SLC1HOST_RX_START_INT_ST_V << SDIO_SLCHOST_SLC1HOST_RX_START_INT_ST_S) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ST_S 14 +/** SDIO_SLCHOST_SLC1HOST_TX_START_INT_ST : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ST (BIT(15)) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ST_M (SDIO_SLCHOST_SLC1HOST_TX_START_INT_ST_V << SDIO_SLCHOST_SLC1HOST_TX_START_INT_ST_S) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ST_S 15 +/** SDIO_SLCHOST_SLC1_RX_UDF_INT_ST : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ST (BIT(16)) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ST_M (SDIO_SLCHOST_SLC1_RX_UDF_INT_ST_V << SDIO_SLCHOST_SLC1_RX_UDF_INT_ST_S) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ST_S 16 +/** SDIO_SLCHOST_SLC1_TX_OVF_INT_ST : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ST (BIT(17)) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ST_M (SDIO_SLCHOST_SLC1_TX_OVF_INT_ST_V << SDIO_SLCHOST_SLC1_TX_OVF_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ST_S 17 +/** SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ST : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ST (BIT(18)) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ST_M (SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ST_V << SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ST_S) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ST_S 18 +/** SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ST : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ST (BIT(19)) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ST_M (SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ST_V << SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ST_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ST_S 19 +/** SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ST : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ST (BIT(20)) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ST_M (SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ST_V << SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ST_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ST_S 20 +/** SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ST : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ST (BIT(21)) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ST_M (SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ST_V << SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ST_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ST_S 21 +/** SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ST : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ST (BIT(22)) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ST_M (SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ST_V << SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ST_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ST_S 22 +/** SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST (BIT(23)) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_M (SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V << SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S 23 +/** SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ST : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ST (BIT(24)) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_M (SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_V << SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_S) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_S 24 +/** SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST (BIT(25)) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_M (SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V << SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S 25 + +/** SDIO_SLC_HOST_PKT_LEN_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_PKT_LEN_REG (DR_REG_HOST_BASE + 0x60) +/** SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN 0x000FFFFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_M (SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_V << SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_V 0x000FFFFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_S 0 +/** SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_M (SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_V << SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_V 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_S 20 + +/** SDIO_SLC_HOST_STATE_W0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_STATE_W0_REG (DR_REG_HOST_BASE + 0x64) +/** SDIO_SLCHOST_SLCHOST_STATE0 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_STATE0 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE0_M (SDIO_SLCHOST_SLCHOST_STATE0_V << SDIO_SLCHOST_SLCHOST_STATE0_S) +#define SDIO_SLCHOST_SLCHOST_STATE0_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE0_S 0 +/** SDIO_SLCHOST_SLCHOST_STATE1 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_STATE1 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE1_M (SDIO_SLCHOST_SLCHOST_STATE1_V << SDIO_SLCHOST_SLCHOST_STATE1_S) +#define SDIO_SLCHOST_SLCHOST_STATE1_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE1_S 8 +/** SDIO_SLCHOST_SLCHOST_STATE2 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_STATE2 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE2_M (SDIO_SLCHOST_SLCHOST_STATE2_V << SDIO_SLCHOST_SLCHOST_STATE2_S) +#define SDIO_SLCHOST_SLCHOST_STATE2_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE2_S 16 +/** SDIO_SLCHOST_SLCHOST_STATE3 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_STATE3 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE3_M (SDIO_SLCHOST_SLCHOST_STATE3_V << SDIO_SLCHOST_SLCHOST_STATE3_S) +#define SDIO_SLCHOST_SLCHOST_STATE3_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE3_S 24 + +/** SDIO_SLC_HOST_STATE_W1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_STATE_W1_REG (DR_REG_HOST_BASE + 0x68) +/** SDIO_SLCHOST_SLCHOST_STATE4 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_STATE4 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE4_M (SDIO_SLCHOST_SLCHOST_STATE4_V << SDIO_SLCHOST_SLCHOST_STATE4_S) +#define SDIO_SLCHOST_SLCHOST_STATE4_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE4_S 0 +/** SDIO_SLCHOST_SLCHOST_STATE5 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_STATE5 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE5_M (SDIO_SLCHOST_SLCHOST_STATE5_V << SDIO_SLCHOST_SLCHOST_STATE5_S) +#define SDIO_SLCHOST_SLCHOST_STATE5_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE5_S 8 +/** SDIO_SLCHOST_SLCHOST_STATE6 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_STATE6 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE6_M (SDIO_SLCHOST_SLCHOST_STATE6_V << SDIO_SLCHOST_SLCHOST_STATE6_S) +#define SDIO_SLCHOST_SLCHOST_STATE6_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE6_S 16 +/** SDIO_SLCHOST_SLCHOST_STATE7 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_STATE7 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE7_M (SDIO_SLCHOST_SLCHOST_STATE7_V << SDIO_SLCHOST_SLCHOST_STATE7_S) +#define SDIO_SLCHOST_SLCHOST_STATE7_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE7_S 24 + +/** SDIO_SLC_HOST_CONF_W0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W0_REG (DR_REG_HOST_BASE + 0x6c) +/** SDIO_SLCHOST_SLCHOST_CONF0 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF0 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF0_M (SDIO_SLCHOST_SLCHOST_CONF0_V << SDIO_SLCHOST_SLCHOST_CONF0_S) +#define SDIO_SLCHOST_SLCHOST_CONF0_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF0_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF1 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF1 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF1_M (SDIO_SLCHOST_SLCHOST_CONF1_V << SDIO_SLCHOST_SLCHOST_CONF1_S) +#define SDIO_SLCHOST_SLCHOST_CONF1_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF1_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF2 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF2 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF2_M (SDIO_SLCHOST_SLCHOST_CONF2_V << SDIO_SLCHOST_SLCHOST_CONF2_S) +#define SDIO_SLCHOST_SLCHOST_CONF2_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF2_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF3 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF3 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF3_M (SDIO_SLCHOST_SLCHOST_CONF3_V << SDIO_SLCHOST_SLCHOST_CONF3_S) +#define SDIO_SLCHOST_SLCHOST_CONF3_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF3_S 24 + +/** SDIO_SLC_HOST_CONF_W1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W1_REG (DR_REG_HOST_BASE + 0x70) +/** SDIO_SLCHOST_SLCHOST_CONF4 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF4 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF4_M (SDIO_SLCHOST_SLCHOST_CONF4_V << SDIO_SLCHOST_SLCHOST_CONF4_S) +#define SDIO_SLCHOST_SLCHOST_CONF4_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF4_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF5 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF5 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF5_M (SDIO_SLCHOST_SLCHOST_CONF5_V << SDIO_SLCHOST_SLCHOST_CONF5_S) +#define SDIO_SLCHOST_SLCHOST_CONF5_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF5_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF6 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF6 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF6_M (SDIO_SLCHOST_SLCHOST_CONF6_V << SDIO_SLCHOST_SLCHOST_CONF6_S) +#define SDIO_SLCHOST_SLCHOST_CONF6_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF6_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF7 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF7 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF7_M (SDIO_SLCHOST_SLCHOST_CONF7_V << SDIO_SLCHOST_SLCHOST_CONF7_S) +#define SDIO_SLCHOST_SLCHOST_CONF7_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF7_S 24 + +/** SDIO_SLC_HOST_CONF_W2_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W2_REG (DR_REG_HOST_BASE + 0x74) +/** SDIO_SLCHOST_SLCHOST_CONF8 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF8 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF8_M (SDIO_SLCHOST_SLCHOST_CONF8_V << SDIO_SLCHOST_SLCHOST_CONF8_S) +#define SDIO_SLCHOST_SLCHOST_CONF8_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF8_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF9 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF9 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF9_M (SDIO_SLCHOST_SLCHOST_CONF9_V << SDIO_SLCHOST_SLCHOST_CONF9_S) +#define SDIO_SLCHOST_SLCHOST_CONF9_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF9_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF10 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF10 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF10_M (SDIO_SLCHOST_SLCHOST_CONF10_V << SDIO_SLCHOST_SLCHOST_CONF10_S) +#define SDIO_SLCHOST_SLCHOST_CONF10_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF10_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF11 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF11 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF11_M (SDIO_SLCHOST_SLCHOST_CONF11_V << SDIO_SLCHOST_SLCHOST_CONF11_S) +#define SDIO_SLCHOST_SLCHOST_CONF11_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF11_S 24 + +/** SDIO_SLC_HOST_CONF_W3_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W3_REG (DR_REG_HOST_BASE + 0x78) +/** SDIO_SLCHOST_SLCHOST_CONF12 : R/W; bitpos: [7:0]; default: 192; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF12 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF12_M (SDIO_SLCHOST_SLCHOST_CONF12_V << SDIO_SLCHOST_SLCHOST_CONF12_S) +#define SDIO_SLCHOST_SLCHOST_CONF12_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF12_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF13 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF13 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF13_M (SDIO_SLCHOST_SLCHOST_CONF13_V << SDIO_SLCHOST_SLCHOST_CONF13_S) +#define SDIO_SLCHOST_SLCHOST_CONF13_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF13_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF14 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF14 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF14_M (SDIO_SLCHOST_SLCHOST_CONF14_V << SDIO_SLCHOST_SLCHOST_CONF14_S) +#define SDIO_SLCHOST_SLCHOST_CONF14_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF14_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF15 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF15 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF15_M (SDIO_SLCHOST_SLCHOST_CONF15_V << SDIO_SLCHOST_SLCHOST_CONF15_S) +#define SDIO_SLCHOST_SLCHOST_CONF15_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF15_S 24 + +/** SDIO_SLC_HOST_CONF_W4_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W4_REG (DR_REG_HOST_BASE + 0x7c) +/** SDIO_SLCHOST_SLCHOST_CONF16 : R/W; bitpos: [7:0]; default: 255; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF16 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF16_M (SDIO_SLCHOST_SLCHOST_CONF16_V << SDIO_SLCHOST_SLCHOST_CONF16_S) +#define SDIO_SLCHOST_SLCHOST_CONF16_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF16_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF17 : R/W; bitpos: [15:8]; default: 1; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF17 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF17_M (SDIO_SLCHOST_SLCHOST_CONF17_V << SDIO_SLCHOST_SLCHOST_CONF17_S) +#define SDIO_SLCHOST_SLCHOST_CONF17_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF17_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF18 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF18 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF18_M (SDIO_SLCHOST_SLCHOST_CONF18_V << SDIO_SLCHOST_SLCHOST_CONF18_S) +#define SDIO_SLCHOST_SLCHOST_CONF18_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF18_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF19 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF19 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF19_M (SDIO_SLCHOST_SLCHOST_CONF19_V << SDIO_SLCHOST_SLCHOST_CONF19_S) +#define SDIO_SLCHOST_SLCHOST_CONF19_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF19_S 24 + +/** SDIO_SLC_HOST_CONF_W5_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W5_REG (DR_REG_HOST_BASE + 0x80) +/** SDIO_SLCHOST_SLCHOST_CONF20 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF20 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF20_M (SDIO_SLCHOST_SLCHOST_CONF20_V << SDIO_SLCHOST_SLCHOST_CONF20_S) +#define SDIO_SLCHOST_SLCHOST_CONF20_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF20_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF21 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF21 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF21_M (SDIO_SLCHOST_SLCHOST_CONF21_V << SDIO_SLCHOST_SLCHOST_CONF21_S) +#define SDIO_SLCHOST_SLCHOST_CONF21_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF21_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF22 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF22 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF22_M (SDIO_SLCHOST_SLCHOST_CONF22_V << SDIO_SLCHOST_SLCHOST_CONF22_S) +#define SDIO_SLCHOST_SLCHOST_CONF22_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF22_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF23 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF23 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF23_M (SDIO_SLCHOST_SLCHOST_CONF23_V << SDIO_SLCHOST_SLCHOST_CONF23_S) +#define SDIO_SLCHOST_SLCHOST_CONF23_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF23_S 24 + +/** SDIO_SLC_HOST_WIN_CMD_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_WIN_CMD_REG (DR_REG_HOST_BASE + 0x84) +/** SDIO_SLCHOST_SLCHOST_WIN_CMD : R/W; bitpos: [15:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_WIN_CMD 0x0000FFFFU +#define SDIO_SLCHOST_SLCHOST_WIN_CMD_M (SDIO_SLCHOST_SLCHOST_WIN_CMD_V << SDIO_SLCHOST_SLCHOST_WIN_CMD_S) +#define SDIO_SLCHOST_SLCHOST_WIN_CMD_V 0x0000FFFFU +#define SDIO_SLCHOST_SLCHOST_WIN_CMD_S 0 + +/** SDIO_SLC_HOST_CONF_W6_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W6_REG (DR_REG_HOST_BASE + 0x88) +/** SDIO_SLCHOST_SLCHOST_CONF24 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF24 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF24_M (SDIO_SLCHOST_SLCHOST_CONF24_V << SDIO_SLCHOST_SLCHOST_CONF24_S) +#define SDIO_SLCHOST_SLCHOST_CONF24_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF24_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF25 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF25 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF25_M (SDIO_SLCHOST_SLCHOST_CONF25_V << SDIO_SLCHOST_SLCHOST_CONF25_S) +#define SDIO_SLCHOST_SLCHOST_CONF25_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF25_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF26 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF26 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF26_M (SDIO_SLCHOST_SLCHOST_CONF26_V << SDIO_SLCHOST_SLCHOST_CONF26_S) +#define SDIO_SLCHOST_SLCHOST_CONF26_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF26_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF27 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF27 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF27_M (SDIO_SLCHOST_SLCHOST_CONF27_V << SDIO_SLCHOST_SLCHOST_CONF27_S) +#define SDIO_SLCHOST_SLCHOST_CONF27_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF27_S 24 + +/** SDIO_SLC_HOST_CONF_W7_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W7_REG (DR_REG_HOST_BASE + 0x8c) +/** SDIO_SLCHOST_SLCHOST_CONF28 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF28 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF28_M (SDIO_SLCHOST_SLCHOST_CONF28_V << SDIO_SLCHOST_SLCHOST_CONF28_S) +#define SDIO_SLCHOST_SLCHOST_CONF28_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF28_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF29 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF29 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF29_M (SDIO_SLCHOST_SLCHOST_CONF29_V << SDIO_SLCHOST_SLCHOST_CONF29_S) +#define SDIO_SLCHOST_SLCHOST_CONF29_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF29_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF30 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF30 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF30_M (SDIO_SLCHOST_SLCHOST_CONF30_V << SDIO_SLCHOST_SLCHOST_CONF30_S) +#define SDIO_SLCHOST_SLCHOST_CONF30_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF30_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF31 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF31 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF31_M (SDIO_SLCHOST_SLCHOST_CONF31_V << SDIO_SLCHOST_SLCHOST_CONF31_S) +#define SDIO_SLCHOST_SLCHOST_CONF31_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF31_S 24 + +/** SDIO_SLC_HOST_PKT_LEN0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_PKT_LEN0_REG (DR_REG_HOST_BASE + 0x90) +/** SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0 0x000FFFFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_M (SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_V << SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_V 0x000FFFFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_S 0 +/** SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_M (SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_V << SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_V 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_S 20 + +/** SDIO_SLC_HOST_PKT_LEN1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_PKT_LEN1_REG (DR_REG_HOST_BASE + 0x94) +/** SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1 0x000FFFFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_M (SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_V << SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_V 0x000FFFFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_S 0 +/** SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_M (SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_V << SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_V 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_S 20 + +/** SDIO_SLC_HOST_PKT_LEN2_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_PKT_LEN2_REG (DR_REG_HOST_BASE + 0x98) +/** SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2 0x000FFFFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_M (SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_V << SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_V 0x000FFFFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_S 0 +/** SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_M (SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_V << SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_V 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_S 20 + +/** SDIO_SLC_HOST_CONF_W8_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W8_REG (DR_REG_HOST_BASE + 0x9c) +/** SDIO_SLCHOST_SLCHOST_CONF32 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF32 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF32_M (SDIO_SLCHOST_SLCHOST_CONF32_V << SDIO_SLCHOST_SLCHOST_CONF32_S) +#define SDIO_SLCHOST_SLCHOST_CONF32_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF32_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF33 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF33 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF33_M (SDIO_SLCHOST_SLCHOST_CONF33_V << SDIO_SLCHOST_SLCHOST_CONF33_S) +#define SDIO_SLCHOST_SLCHOST_CONF33_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF33_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF34 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF34 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF34_M (SDIO_SLCHOST_SLCHOST_CONF34_V << SDIO_SLCHOST_SLCHOST_CONF34_S) +#define SDIO_SLCHOST_SLCHOST_CONF34_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF34_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF35 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF35 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF35_M (SDIO_SLCHOST_SLCHOST_CONF35_V << SDIO_SLCHOST_SLCHOST_CONF35_S) +#define SDIO_SLCHOST_SLCHOST_CONF35_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF35_S 24 + +/** SDIO_SLC_HOST_CONF_W9_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W9_REG (DR_REG_HOST_BASE + 0xa0) +/** SDIO_SLCHOST_SLCHOST_CONF36 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF36 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF36_M (SDIO_SLCHOST_SLCHOST_CONF36_V << SDIO_SLCHOST_SLCHOST_CONF36_S) +#define SDIO_SLCHOST_SLCHOST_CONF36_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF36_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF37 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF37 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF37_M (SDIO_SLCHOST_SLCHOST_CONF37_V << SDIO_SLCHOST_SLCHOST_CONF37_S) +#define SDIO_SLCHOST_SLCHOST_CONF37_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF37_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF38 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF38 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF38_M (SDIO_SLCHOST_SLCHOST_CONF38_V << SDIO_SLCHOST_SLCHOST_CONF38_S) +#define SDIO_SLCHOST_SLCHOST_CONF38_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF38_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF39 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF39 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF39_M (SDIO_SLCHOST_SLCHOST_CONF39_V << SDIO_SLCHOST_SLCHOST_CONF39_S) +#define SDIO_SLCHOST_SLCHOST_CONF39_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF39_S 24 + +/** SDIO_SLC_HOST_CONF_W10_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W10_REG (DR_REG_HOST_BASE + 0xa4) +/** SDIO_SLCHOST_SLCHOST_CONF40 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF40 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF40_M (SDIO_SLCHOST_SLCHOST_CONF40_V << SDIO_SLCHOST_SLCHOST_CONF40_S) +#define SDIO_SLCHOST_SLCHOST_CONF40_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF40_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF41 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF41 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF41_M (SDIO_SLCHOST_SLCHOST_CONF41_V << SDIO_SLCHOST_SLCHOST_CONF41_S) +#define SDIO_SLCHOST_SLCHOST_CONF41_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF41_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF42 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF42 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF42_M (SDIO_SLCHOST_SLCHOST_CONF42_V << SDIO_SLCHOST_SLCHOST_CONF42_S) +#define SDIO_SLCHOST_SLCHOST_CONF42_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF42_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF43 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF43 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF43_M (SDIO_SLCHOST_SLCHOST_CONF43_V << SDIO_SLCHOST_SLCHOST_CONF43_S) +#define SDIO_SLCHOST_SLCHOST_CONF43_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF43_S 24 + +/** SDIO_SLC_HOST_CONF_W11_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W11_REG (DR_REG_HOST_BASE + 0xa8) +/** SDIO_SLCHOST_SLCHOST_CONF44 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF44 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF44_M (SDIO_SLCHOST_SLCHOST_CONF44_V << SDIO_SLCHOST_SLCHOST_CONF44_S) +#define SDIO_SLCHOST_SLCHOST_CONF44_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF44_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF45 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF45 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF45_M (SDIO_SLCHOST_SLCHOST_CONF45_V << SDIO_SLCHOST_SLCHOST_CONF45_S) +#define SDIO_SLCHOST_SLCHOST_CONF45_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF45_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF46 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF46 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF46_M (SDIO_SLCHOST_SLCHOST_CONF46_V << SDIO_SLCHOST_SLCHOST_CONF46_S) +#define SDIO_SLCHOST_SLCHOST_CONF46_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF46_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF47 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF47 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF47_M (SDIO_SLCHOST_SLCHOST_CONF47_V << SDIO_SLCHOST_SLCHOST_CONF47_S) +#define SDIO_SLCHOST_SLCHOST_CONF47_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF47_S 24 + +/** SDIO_SLC_HOST_CONF_W12_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W12_REG (DR_REG_HOST_BASE + 0xac) +/** SDIO_SLCHOST_SLCHOST_CONF48 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF48 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF48_M (SDIO_SLCHOST_SLCHOST_CONF48_V << SDIO_SLCHOST_SLCHOST_CONF48_S) +#define SDIO_SLCHOST_SLCHOST_CONF48_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF48_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF49 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF49 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF49_M (SDIO_SLCHOST_SLCHOST_CONF49_V << SDIO_SLCHOST_SLCHOST_CONF49_S) +#define SDIO_SLCHOST_SLCHOST_CONF49_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF49_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF50 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF50 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF50_M (SDIO_SLCHOST_SLCHOST_CONF50_V << SDIO_SLCHOST_SLCHOST_CONF50_S) +#define SDIO_SLCHOST_SLCHOST_CONF50_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF50_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF51 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF51 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF51_M (SDIO_SLCHOST_SLCHOST_CONF51_V << SDIO_SLCHOST_SLCHOST_CONF51_S) +#define SDIO_SLCHOST_SLCHOST_CONF51_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF51_S 24 + +/** SDIO_SLC_HOST_CONF_W13_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W13_REG (DR_REG_HOST_BASE + 0xb0) +/** SDIO_SLCHOST_SLCHOST_CONF52 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF52 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF52_M (SDIO_SLCHOST_SLCHOST_CONF52_V << SDIO_SLCHOST_SLCHOST_CONF52_S) +#define SDIO_SLCHOST_SLCHOST_CONF52_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF52_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF53 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF53 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF53_M (SDIO_SLCHOST_SLCHOST_CONF53_V << SDIO_SLCHOST_SLCHOST_CONF53_S) +#define SDIO_SLCHOST_SLCHOST_CONF53_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF53_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF54 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF54 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF54_M (SDIO_SLCHOST_SLCHOST_CONF54_V << SDIO_SLCHOST_SLCHOST_CONF54_S) +#define SDIO_SLCHOST_SLCHOST_CONF54_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF54_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF55 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF55 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF55_M (SDIO_SLCHOST_SLCHOST_CONF55_V << SDIO_SLCHOST_SLCHOST_CONF55_S) +#define SDIO_SLCHOST_SLCHOST_CONF55_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF55_S 24 + +/** SDIO_SLC_HOST_CONF_W14_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W14_REG (DR_REG_HOST_BASE + 0xb4) +/** SDIO_SLCHOST_SLCHOST_CONF56 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF56 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF56_M (SDIO_SLCHOST_SLCHOST_CONF56_V << SDIO_SLCHOST_SLCHOST_CONF56_S) +#define SDIO_SLCHOST_SLCHOST_CONF56_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF56_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF57 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF57 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF57_M (SDIO_SLCHOST_SLCHOST_CONF57_V << SDIO_SLCHOST_SLCHOST_CONF57_S) +#define SDIO_SLCHOST_SLCHOST_CONF57_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF57_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF58 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF58 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF58_M (SDIO_SLCHOST_SLCHOST_CONF58_V << SDIO_SLCHOST_SLCHOST_CONF58_S) +#define SDIO_SLCHOST_SLCHOST_CONF58_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF58_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF59 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF59 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF59_M (SDIO_SLCHOST_SLCHOST_CONF59_V << SDIO_SLCHOST_SLCHOST_CONF59_S) +#define SDIO_SLCHOST_SLCHOST_CONF59_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF59_S 24 + +/** SDIO_SLC_HOST_CONF_W15_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W15_REG (DR_REG_HOST_BASE + 0xb8) +/** SDIO_SLCHOST_SLCHOST_CONF60 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF60 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF60_M (SDIO_SLCHOST_SLCHOST_CONF60_V << SDIO_SLCHOST_SLCHOST_CONF60_S) +#define SDIO_SLCHOST_SLCHOST_CONF60_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF60_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF61 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF61 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF61_M (SDIO_SLCHOST_SLCHOST_CONF61_V << SDIO_SLCHOST_SLCHOST_CONF61_S) +#define SDIO_SLCHOST_SLCHOST_CONF61_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF61_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF62 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF62 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF62_M (SDIO_SLCHOST_SLCHOST_CONF62_V << SDIO_SLCHOST_SLCHOST_CONF62_S) +#define SDIO_SLCHOST_SLCHOST_CONF62_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF62_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF63 : R/W; bitpos: [31:24]; default: 0; + * Bit [27:24] used for reg_slc_apbwin_addr[31:28] + */ +#define SDIO_SLCHOST_SLCHOST_CONF63 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF63_M (SDIO_SLCHOST_SLCHOST_CONF63_V << SDIO_SLCHOST_SLCHOST_CONF63_S) +#define SDIO_SLCHOST_SLCHOST_CONF63_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF63_S 24 + +/** SDIO_SLC_HOST_CHECK_SUM0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CHECK_SUM0_REG (DR_REG_HOST_BASE + 0xbc) +/** SDIO_SLCHOST_SLCHOST_CHECK_SUM0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CHECK_SUM0 0xFFFFFFFFU +#define SDIO_SLCHOST_SLCHOST_CHECK_SUM0_M (SDIO_SLCHOST_SLCHOST_CHECK_SUM0_V << SDIO_SLCHOST_SLCHOST_CHECK_SUM0_S) +#define SDIO_SLCHOST_SLCHOST_CHECK_SUM0_V 0xFFFFFFFFU +#define SDIO_SLCHOST_SLCHOST_CHECK_SUM0_S 0 + +/** SDIO_SLC_HOST_CHECK_SUM1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CHECK_SUM1_REG (DR_REG_HOST_BASE + 0xc0) +/** SDIO_SLCHOST_SLCHOST_CHECK_SUM1 : RO; bitpos: [31:0]; default: 319; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CHECK_SUM1 0xFFFFFFFFU +#define SDIO_SLCHOST_SLCHOST_CHECK_SUM1_M (SDIO_SLCHOST_SLCHOST_CHECK_SUM1_V << SDIO_SLCHOST_SLCHOST_CHECK_SUM1_S) +#define SDIO_SLCHOST_SLCHOST_CHECK_SUM1_V 0xFFFFFFFFU +#define SDIO_SLCHOST_SLCHOST_CHECK_SUM1_S 0 + +/** SDIO_SLC_HOST_SLC1HOST_TOKEN_RDATA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_TOKEN_RDATA_REG (DR_REG_HOST_BASE + 0xc4) +/** SDIO_SLCHOST_SLC1_TOKEN0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0 0x00000FFFU +#define SDIO_SLCHOST_SLC1_TOKEN0_M (SDIO_SLCHOST_SLC1_TOKEN0_V << SDIO_SLCHOST_SLC1_TOKEN0_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_V 0x00000FFFU +#define SDIO_SLCHOST_SLC1_TOKEN0_S 0 +/** SDIO_SLCHOST_SLC1_RX_PF_VALID : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_PF_VALID (BIT(12)) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_M (SDIO_SLCHOST_SLC1_RX_PF_VALID_V << SDIO_SLCHOST_SLC1_RX_PF_VALID_S) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_S 12 +/** SDIO_SLCHOST_HOSTSLCHOST_SLC1_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC1_TOKEN1 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_M (SDIO_SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_V << SDIO_SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_V 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_S 16 +/** SDIO_SLCHOST_SLC1_RX_PF_EOF : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_PF_EOF 0x0000000FU +#define SDIO_SLCHOST_SLC1_RX_PF_EOF_M (SDIO_SLCHOST_SLC1_RX_PF_EOF_V << SDIO_SLCHOST_SLC1_RX_PF_EOF_S) +#define SDIO_SLCHOST_SLC1_RX_PF_EOF_V 0x0000000FU +#define SDIO_SLCHOST_SLC1_RX_PF_EOF_S 28 + +/** SDIO_SLC_HOST_SLC0HOST_TOKEN_WDATA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_TOKEN_WDATA_REG (DR_REG_HOST_BASE + 0xc8) +/** SDIO_SLCHOST_SLC0HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_WD 0x00000FFFU +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_WD_M (SDIO_SLCHOST_SLC0HOST_TOKEN0_WD_V << SDIO_SLCHOST_SLC0HOST_TOKEN0_WD_S) +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_WD_V 0x00000FFFU +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_WD_S 0 +/** SDIO_SLCHOST_SLC0HOST_TOKEN1_WD : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_WD 0x00000FFFU +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_WD_M (SDIO_SLCHOST_SLC0HOST_TOKEN1_WD_V << SDIO_SLCHOST_SLC0HOST_TOKEN1_WD_S) +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_WD_V 0x00000FFFU +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_WD_S 16 + +/** SDIO_SLC_HOST_SLC1HOST_TOKEN_WDATA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_TOKEN_WDATA_REG (DR_REG_HOST_BASE + 0xcc) +/** SDIO_SLCHOST_SLC1HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_WD 0x00000FFFU +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_WD_M (SDIO_SLCHOST_SLC1HOST_TOKEN0_WD_V << SDIO_SLCHOST_SLC1HOST_TOKEN0_WD_S) +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_WD_V 0x00000FFFU +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_WD_S 0 +/** SDIO_SLCHOST_SLC1HOST_TOKEN1_WD : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_WD 0x00000FFFU +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_WD_M (SDIO_SLCHOST_SLC1HOST_TOKEN1_WD_V << SDIO_SLCHOST_SLC1HOST_TOKEN1_WD_S) +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_WD_V 0x00000FFFU +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_WD_S 16 + +/** SDIO_SLC_HOST_TOKEN_CON_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_TOKEN_CON_REG (DR_REG_HOST_BASE + 0xd0) +/** SDIO_SLCHOST_SLC0HOST_TOKEN0_DEC : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_DEC (BIT(0)) +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_DEC_M (SDIO_SLCHOST_SLC0HOST_TOKEN0_DEC_V << SDIO_SLCHOST_SLC0HOST_TOKEN0_DEC_S) +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_DEC_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_DEC_S 0 +/** SDIO_SLCHOST_SLC0HOST_TOKEN1_DEC : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_DEC (BIT(1)) +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_DEC_M (SDIO_SLCHOST_SLC0HOST_TOKEN1_DEC_V << SDIO_SLCHOST_SLC0HOST_TOKEN1_DEC_S) +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_DEC_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_DEC_S 1 +/** SDIO_SLCHOST_SLC0HOST_TOKEN0_WR : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_WR (BIT(2)) +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_WR_M (SDIO_SLCHOST_SLC0HOST_TOKEN0_WR_V << SDIO_SLCHOST_SLC0HOST_TOKEN0_WR_S) +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_WR_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_WR_S 2 +/** SDIO_SLCHOST_SLC0HOST_TOKEN1_WR : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_WR (BIT(3)) +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_WR_M (SDIO_SLCHOST_SLC0HOST_TOKEN1_WR_V << SDIO_SLCHOST_SLC0HOST_TOKEN1_WR_S) +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_WR_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_WR_S 3 +/** SDIO_SLCHOST_SLC1HOST_TOKEN0_DEC : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_DEC (BIT(4)) +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_DEC_M (SDIO_SLCHOST_SLC1HOST_TOKEN0_DEC_V << SDIO_SLCHOST_SLC1HOST_TOKEN0_DEC_S) +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_DEC_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_DEC_S 4 +/** SDIO_SLCHOST_SLC1HOST_TOKEN1_DEC : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_DEC (BIT(5)) +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_DEC_M (SDIO_SLCHOST_SLC1HOST_TOKEN1_DEC_V << SDIO_SLCHOST_SLC1HOST_TOKEN1_DEC_S) +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_DEC_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_DEC_S 5 +/** SDIO_SLCHOST_SLC1HOST_TOKEN0_WR : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_WR (BIT(6)) +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_WR_M (SDIO_SLCHOST_SLC1HOST_TOKEN0_WR_V << SDIO_SLCHOST_SLC1HOST_TOKEN0_WR_S) +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_WR_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_WR_S 6 +/** SDIO_SLCHOST_SLC1HOST_TOKEN1_WR : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_WR (BIT(7)) +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_WR_M (SDIO_SLCHOST_SLC1HOST_TOKEN1_WR_V << SDIO_SLCHOST_SLC1HOST_TOKEN1_WR_S) +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_WR_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_WR_S 7 +/** SDIO_SLCHOST_SLC0HOST_LEN_WR : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_LEN_WR (BIT(8)) +#define SDIO_SLCHOST_SLC0HOST_LEN_WR_M (SDIO_SLCHOST_SLC0HOST_LEN_WR_V << SDIO_SLCHOST_SLC0HOST_LEN_WR_S) +#define SDIO_SLCHOST_SLC0HOST_LEN_WR_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_LEN_WR_S 8 + +/** SDIO_SLC_HOST_SLC0HOST_INT_CLR_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_INT_CLR_REG (DR_REG_HOST_BASE + 0xd4) +/** SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_CLR (BIT(0)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_M (SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_V << SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_S 0 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_CLR (BIT(1)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_M (SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_V << SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_S 1 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_CLR (BIT(2)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_M (SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_V << SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_S 2 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_CLR (BIT(3)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_M (SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_V << SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_S 3 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_CLR (BIT(4)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_M (SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_V << SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_S 4 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_CLR (BIT(5)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_M (SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_V << SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_S 5 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_CLR (BIT(6)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_M (SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_V << SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_S 6 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_CLR (BIT(7)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_M (SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_V << SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_S 7 +/** SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR (BIT(8)) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_M (SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_V << SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_S 8 +/** SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR (BIT(9)) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_M (SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_V << SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_S 9 +/** SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR (BIT(10)) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_M (SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_V << SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_S 10 +/** SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR (BIT(11)) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_M (SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_V << SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_S 11 +/** SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_CLR : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_CLR (BIT(12)) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_CLR_M (SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_CLR_V << SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_CLR_S) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_CLR_S 12 +/** SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_CLR : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_CLR (BIT(13)) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_CLR_M (SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_CLR_V << SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_CLR_S) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_CLR_S 13 +/** SDIO_SLCHOST_SLC0HOST_RX_START_INT_CLR : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_CLR (BIT(14)) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_CLR_M (SDIO_SLCHOST_SLC0HOST_RX_START_INT_CLR_V << SDIO_SLCHOST_SLC0HOST_RX_START_INT_CLR_S) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_CLR_S 14 +/** SDIO_SLCHOST_SLC0HOST_TX_START_INT_CLR : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_CLR (BIT(15)) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_CLR_M (SDIO_SLCHOST_SLC0HOST_TX_START_INT_CLR_V << SDIO_SLCHOST_SLC0HOST_TX_START_INT_CLR_S) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_CLR_S 15 +/** SDIO_SLCHOST_SLC0_RX_UDF_INT_CLR : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_CLR (BIT(16)) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_CLR_M (SDIO_SLCHOST_SLC0_RX_UDF_INT_CLR_V << SDIO_SLCHOST_SLC0_RX_UDF_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_CLR_S 16 +/** SDIO_SLCHOST_SLC0_TX_OVF_INT_CLR : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_CLR (BIT(17)) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_CLR_M (SDIO_SLCHOST_SLC0_TX_OVF_INT_CLR_V << SDIO_SLCHOST_SLC0_TX_OVF_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_CLR_S 17 +/** SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_CLR : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_CLR (BIT(18)) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_CLR_M (SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_CLR_V << SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_CLR_S 18 +/** SDIO_SLCHOST_SLC0_EXT_BIT0_INT_CLR : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_CLR (BIT(19)) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_CLR_M (SDIO_SLCHOST_SLC0_EXT_BIT0_INT_CLR_V << SDIO_SLCHOST_SLC0_EXT_BIT0_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_CLR_S 19 +/** SDIO_SLCHOST_SLC0_EXT_BIT1_INT_CLR : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_CLR (BIT(20)) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_CLR_M (SDIO_SLCHOST_SLC0_EXT_BIT1_INT_CLR_V << SDIO_SLCHOST_SLC0_EXT_BIT1_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_CLR_S 20 +/** SDIO_SLCHOST_SLC0_EXT_BIT2_INT_CLR : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_CLR (BIT(21)) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_CLR_M (SDIO_SLCHOST_SLC0_EXT_BIT2_INT_CLR_V << SDIO_SLCHOST_SLC0_EXT_BIT2_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_CLR_S 21 +/** SDIO_SLCHOST_SLC0_EXT_BIT3_INT_CLR : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_CLR (BIT(22)) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_CLR_M (SDIO_SLCHOST_SLC0_EXT_BIT3_INT_CLR_V << SDIO_SLCHOST_SLC0_EXT_BIT3_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_CLR_S 22 +/** SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR (BIT(23)) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_M (SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_V << SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_S 23 +/** SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR (BIT(24)) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_M (SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_V << SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_S 24 +/** SDIO_SLCHOST_GPIO_SDIO_INT_CLR : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_GPIO_SDIO_INT_CLR (BIT(25)) +#define SDIO_SLCHOST_GPIO_SDIO_INT_CLR_M (SDIO_SLCHOST_GPIO_SDIO_INT_CLR_V << SDIO_SLCHOST_GPIO_SDIO_INT_CLR_S) +#define SDIO_SLCHOST_GPIO_SDIO_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_GPIO_SDIO_INT_CLR_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_INT_CLR_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_INT_CLR_REG (DR_REG_HOST_BASE + 0xd8) +/** SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_CLR (BIT(0)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_M (SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_V << SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_S 0 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_CLR (BIT(1)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_M (SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_V << SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_S 1 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_CLR (BIT(2)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_M (SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_V << SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_S 2 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_CLR (BIT(3)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_M (SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_V << SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_S 3 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_CLR (BIT(4)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_M (SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_V << SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_S 4 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_CLR (BIT(5)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_M (SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_V << SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_S 5 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_CLR (BIT(6)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_M (SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_V << SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_S 6 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_CLR (BIT(7)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_M (SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_V << SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_S 7 +/** SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR (BIT(8)) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_M (SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_V << SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_S 8 +/** SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR (BIT(9)) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_M (SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_V << SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_S 9 +/** SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR (BIT(10)) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_M (SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_V << SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_S 10 +/** SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR (BIT(11)) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_M (SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_V << SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_S 11 +/** SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_CLR : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_CLR (BIT(12)) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_CLR_M (SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_CLR_V << SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_CLR_S) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_CLR_S 12 +/** SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_CLR : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_CLR (BIT(13)) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_CLR_M (SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_CLR_V << SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_CLR_S) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_CLR_S 13 +/** SDIO_SLCHOST_SLC1HOST_RX_START_INT_CLR : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_CLR (BIT(14)) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_CLR_M (SDIO_SLCHOST_SLC1HOST_RX_START_INT_CLR_V << SDIO_SLCHOST_SLC1HOST_RX_START_INT_CLR_S) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_CLR_S 14 +/** SDIO_SLCHOST_SLC1HOST_TX_START_INT_CLR : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_CLR (BIT(15)) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_CLR_M (SDIO_SLCHOST_SLC1HOST_TX_START_INT_CLR_V << SDIO_SLCHOST_SLC1HOST_TX_START_INT_CLR_S) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_CLR_S 15 +/** SDIO_SLCHOST_SLC1_RX_UDF_INT_CLR : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_CLR (BIT(16)) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_CLR_M (SDIO_SLCHOST_SLC1_RX_UDF_INT_CLR_V << SDIO_SLCHOST_SLC1_RX_UDF_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_CLR_S 16 +/** SDIO_SLCHOST_SLC1_TX_OVF_INT_CLR : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_CLR (BIT(17)) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_CLR_M (SDIO_SLCHOST_SLC1_TX_OVF_INT_CLR_V << SDIO_SLCHOST_SLC1_TX_OVF_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_CLR_S 17 +/** SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_CLR : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_CLR (BIT(18)) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_CLR_M (SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_CLR_V << SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_CLR_S 18 +/** SDIO_SLCHOST_SLC1_EXT_BIT0_INT_CLR : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_CLR (BIT(19)) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_CLR_M (SDIO_SLCHOST_SLC1_EXT_BIT0_INT_CLR_V << SDIO_SLCHOST_SLC1_EXT_BIT0_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_CLR_S 19 +/** SDIO_SLCHOST_SLC1_EXT_BIT1_INT_CLR : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_CLR (BIT(20)) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_CLR_M (SDIO_SLCHOST_SLC1_EXT_BIT1_INT_CLR_V << SDIO_SLCHOST_SLC1_EXT_BIT1_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_CLR_S 20 +/** SDIO_SLCHOST_SLC1_EXT_BIT2_INT_CLR : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_CLR (BIT(21)) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_CLR_M (SDIO_SLCHOST_SLC1_EXT_BIT2_INT_CLR_V << SDIO_SLCHOST_SLC1_EXT_BIT2_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_CLR_S 21 +/** SDIO_SLCHOST_SLC1_EXT_BIT3_INT_CLR : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_CLR (BIT(22)) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_CLR_M (SDIO_SLCHOST_SLC1_EXT_BIT3_INT_CLR_V << SDIO_SLCHOST_SLC1_EXT_BIT3_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_CLR_S 22 +/** SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR (BIT(23)) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_M (SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V << SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S 23 +/** SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR (BIT(24)) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_M (SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_V << SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_S 24 +/** SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR (BIT(25)) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_M (SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V << SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S 25 + +/** SDIO_SLC_HOST_SLC0HOST_FUNC1_INT_ENA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_FUNC1_INT_ENA_REG (DR_REG_HOST_BASE + 0xdc) +/** SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SDIO_SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/** SDIO_SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SDIO_SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/** SDIO_SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SDIO_SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/** SDIO_SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SDIO_SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/** SDIO_SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S 12 +/** SDIO_SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S 13 +/** SDIO_SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_S 14 +/** SDIO_SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define SDIO_SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_S 15 +/** SDIO_SLCHOST_FN1_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define SDIO_SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_S 16 +/** SDIO_SLCHOST_FN1_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define SDIO_SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_S 17 +/** SDIO_SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define SDIO_SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S 18 +/** SDIO_SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_S 19 +/** SDIO_SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_S 20 +/** SDIO_SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_S 21 +/** SDIO_SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_S 22 +/** SDIO_SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SDIO_SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/** SDIO_SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SDIO_SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/** SDIO_SLCHOST_FN1_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_GPIO_SDIO_INT_ENA (BIT(25)) +#define SDIO_SLCHOST_FN1_GPIO_SDIO_INT_ENA_M (SDIO_SLCHOST_FN1_GPIO_SDIO_INT_ENA_V << SDIO_SLCHOST_FN1_GPIO_SDIO_INT_ENA_S) +#define SDIO_SLCHOST_FN1_GPIO_SDIO_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_GPIO_SDIO_INT_ENA_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_FUNC1_INT_ENA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_FUNC1_INT_ENA_REG (DR_REG_HOST_BASE + 0xe0) +/** SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SDIO_SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S 8 +/** SDIO_SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SDIO_SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S 9 +/** SDIO_SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SDIO_SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S 10 +/** SDIO_SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SDIO_SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S 11 +/** SDIO_SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S 12 +/** SDIO_SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S 13 +/** SDIO_SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA (BIT(14)) +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_S 14 +/** SDIO_SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA (BIT(15)) +#define SDIO_SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_S 15 +/** SDIO_SLCHOST_FN1_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_RX_UDF_INT_ENA (BIT(16)) +#define SDIO_SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_S 16 +/** SDIO_SLCHOST_FN1_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TX_OVF_INT_ENA (BIT(17)) +#define SDIO_SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_S 17 +/** SDIO_SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) +#define SDIO_SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S 18 +/** SDIO_SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA (BIT(19)) +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_S 19 +/** SDIO_SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA (BIT(20)) +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_S 20 +/** SDIO_SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA (BIT(21)) +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_S 21 +/** SDIO_SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA (BIT(22)) +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_S 22 +/** SDIO_SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SDIO_SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 +/** SDIO_SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SDIO_SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S 24 +/** SDIO_SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) +#define SDIO_SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 + +/** SDIO_SLC_HOST_SLC0HOST_FUNC2_INT_ENA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_FUNC2_INT_ENA_REG (DR_REG_HOST_BASE + 0xe4) +/** SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SDIO_SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/** SDIO_SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SDIO_SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/** SDIO_SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SDIO_SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/** SDIO_SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SDIO_SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/** SDIO_SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S 12 +/** SDIO_SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S 13 +/** SDIO_SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_S 14 +/** SDIO_SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define SDIO_SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_S 15 +/** SDIO_SLCHOST_FN2_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define SDIO_SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_S 16 +/** SDIO_SLCHOST_FN2_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define SDIO_SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_S 17 +/** SDIO_SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define SDIO_SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S 18 +/** SDIO_SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_S 19 +/** SDIO_SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_S 20 +/** SDIO_SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_S 21 +/** SDIO_SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_S 22 +/** SDIO_SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SDIO_SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/** SDIO_SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SDIO_SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/** SDIO_SLCHOST_FN2_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_GPIO_SDIO_INT_ENA (BIT(25)) +#define SDIO_SLCHOST_FN2_GPIO_SDIO_INT_ENA_M (SDIO_SLCHOST_FN2_GPIO_SDIO_INT_ENA_V << SDIO_SLCHOST_FN2_GPIO_SDIO_INT_ENA_S) +#define SDIO_SLCHOST_FN2_GPIO_SDIO_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_GPIO_SDIO_INT_ENA_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_FUNC2_INT_ENA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_FUNC2_INT_ENA_REG (DR_REG_HOST_BASE + 0xe8) +/** SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SDIO_SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S 8 +/** SDIO_SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SDIO_SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S 9 +/** SDIO_SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SDIO_SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S 10 +/** SDIO_SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SDIO_SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S 11 +/** SDIO_SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S 12 +/** SDIO_SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S 13 +/** SDIO_SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA (BIT(14)) +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_S 14 +/** SDIO_SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA (BIT(15)) +#define SDIO_SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_S 15 +/** SDIO_SLCHOST_FN2_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_RX_UDF_INT_ENA (BIT(16)) +#define SDIO_SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_S 16 +/** SDIO_SLCHOST_FN2_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TX_OVF_INT_ENA (BIT(17)) +#define SDIO_SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_S 17 +/** SDIO_SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) +#define SDIO_SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S 18 +/** SDIO_SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA (BIT(19)) +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_S 19 +/** SDIO_SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA (BIT(20)) +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_S 20 +/** SDIO_SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA (BIT(21)) +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_S 21 +/** SDIO_SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA (BIT(22)) +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_S 22 +/** SDIO_SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SDIO_SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 +/** SDIO_SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SDIO_SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S 24 +/** SDIO_SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) +#define SDIO_SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 + +/** SDIO_SLC_HOST_SLC0HOST_INT_ENA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_INT_ENA_REG (DR_REG_HOST_BASE + 0xec) +/** SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_M (SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_V << SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_M (SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_V << SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_M (SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_V << SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_M (SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_V << SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_M (SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_V << SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_M (SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_V << SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_M (SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_V << SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_M (SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_V << SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_M (SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_V << SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/** SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_M (SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_V << SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/** SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_M (SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_V << SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/** SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_M (SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_V << SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/** SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA_M (SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA_V << SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA_S) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA_S 12 +/** SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA_M (SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA_V << SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA_S) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA_S 13 +/** SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA_M (SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA_V << SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA_S) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA_S 14 +/** SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA_M (SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA_V << SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA_S) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA_S 15 +/** SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA_M (SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA_V << SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA_S 16 +/** SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA_M (SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA_V << SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA_S 17 +/** SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA_M (SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA_V << SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA_S 18 +/** SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA_M (SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA_V << SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA_S 19 +/** SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA_M (SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA_V << SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA_S 20 +/** SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA_M (SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA_V << SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA_S 21 +/** SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA_M (SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA_V << SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA_S 22 +/** SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_M (SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_V << SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/** SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_M (SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_V << SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/** SDIO_SLCHOST_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_GPIO_SDIO_INT_ENA (BIT(25)) +#define SDIO_SLCHOST_GPIO_SDIO_INT_ENA_M (SDIO_SLCHOST_GPIO_SDIO_INT_ENA_V << SDIO_SLCHOST_GPIO_SDIO_INT_ENA_S) +#define SDIO_SLCHOST_GPIO_SDIO_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_GPIO_SDIO_INT_ENA_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_INT_ENA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_INT_ENA_REG (DR_REG_HOST_BASE + 0xf0) +/** SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_M (SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_V << SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_M (SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_V << SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_M (SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_V << SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_M (SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_V << SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_M (SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_V << SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_M (SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_V << SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_M (SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_V << SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_M (SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_V << SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_M (SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_V << SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_S 8 +/** SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_M (SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_V << SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_S 9 +/** SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_M (SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_V << SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_S 10 +/** SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_M (SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_V << SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_S 11 +/** SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA_M (SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA_V << SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA_S) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA_S 12 +/** SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA_M (SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA_V << SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA_S) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA_S 13 +/** SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA (BIT(14)) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA_M (SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA_V << SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA_S) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA_S 14 +/** SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA (BIT(15)) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA_M (SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA_V << SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA_S) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA_S 15 +/** SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA (BIT(16)) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA_M (SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA_V << SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA_S 16 +/** SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA (BIT(17)) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA_M (SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA_V << SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA_S 17 +/** SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA_M (SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA_V << SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA_S 18 +/** SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA (BIT(19)) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA_M (SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA_V << SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA_S 19 +/** SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA (BIT(20)) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA_M (SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA_V << SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA_S 20 +/** SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA (BIT(21)) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA_M (SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA_V << SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA_S 21 +/** SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA (BIT(22)) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA_M (SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA_V << SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA_S 22 +/** SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 +/** SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_M (SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_V << SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_S 24 +/** SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 + +/** SDIO_SLC_HOST_SLC0HOST_RX_INFOR_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_RX_INFOR_REG (DR_REG_HOST_BASE + 0xf4) +/** SDIO_SLCHOST_SLC0HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_INFOR 0x000FFFFFU +#define SDIO_SLCHOST_SLC0HOST_RX_INFOR_M (SDIO_SLCHOST_SLC0HOST_RX_INFOR_V << SDIO_SLCHOST_SLC0HOST_RX_INFOR_S) +#define SDIO_SLCHOST_SLC0HOST_RX_INFOR_V 0x000FFFFFU +#define SDIO_SLCHOST_SLC0HOST_RX_INFOR_S 0 + +/** SDIO_SLC_HOST_SLC1HOST_RX_INFOR_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_RX_INFOR_REG (DR_REG_HOST_BASE + 0xf8) +/** SDIO_SLCHOST_SLC1HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_INFOR 0x000FFFFFU +#define SDIO_SLCHOST_SLC1HOST_RX_INFOR_M (SDIO_SLCHOST_SLC1HOST_RX_INFOR_V << SDIO_SLCHOST_SLC1HOST_RX_INFOR_S) +#define SDIO_SLCHOST_SLC1HOST_RX_INFOR_V 0x000FFFFFU +#define SDIO_SLCHOST_SLC1HOST_RX_INFOR_S 0 + +/** SDIO_SLC_HOST_SLC0HOST_LEN_WD_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_LEN_WD_REG (DR_REG_HOST_BASE + 0xfc) +/** SDIO_SLCHOST_SLC0HOST_LEN_WD : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_LEN_WD 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC0HOST_LEN_WD_M (SDIO_SLCHOST_SLC0HOST_LEN_WD_V << SDIO_SLCHOST_SLC0HOST_LEN_WD_S) +#define SDIO_SLCHOST_SLC0HOST_LEN_WD_V 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC0HOST_LEN_WD_S 0 + +/** SDIO_SLC_HOST_SLC_APBWIN_WDATA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC_APBWIN_WDATA_REG (DR_REG_HOST_BASE + 0x100) +/** SDIO_SLCHOST_SLC_APBWIN_WDATA : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC_APBWIN_WDATA 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC_APBWIN_WDATA_M (SDIO_SLCHOST_SLC_APBWIN_WDATA_V << SDIO_SLCHOST_SLC_APBWIN_WDATA_S) +#define SDIO_SLCHOST_SLC_APBWIN_WDATA_V 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC_APBWIN_WDATA_S 0 + +/** SDIO_SLC_HOST_SLC_APBWIN_CONF_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC_APBWIN_CONF_REG (DR_REG_HOST_BASE + 0x104) +/** SDIO_SLCHOST_SLC_APBWIN_ADDR : R/W; bitpos: [27:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC_APBWIN_ADDR 0x0FFFFFFFU +#define SDIO_SLCHOST_SLC_APBWIN_ADDR_M (SDIO_SLCHOST_SLC_APBWIN_ADDR_V << SDIO_SLCHOST_SLC_APBWIN_ADDR_S) +#define SDIO_SLCHOST_SLC_APBWIN_ADDR_V 0x0FFFFFFFU +#define SDIO_SLCHOST_SLC_APBWIN_ADDR_S 0 +/** SDIO_SLCHOST_SLC_APBWIN_WR : R/W; bitpos: [28]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC_APBWIN_WR (BIT(28)) +#define SDIO_SLCHOST_SLC_APBWIN_WR_M (SDIO_SLCHOST_SLC_APBWIN_WR_V << SDIO_SLCHOST_SLC_APBWIN_WR_S) +#define SDIO_SLCHOST_SLC_APBWIN_WR_V 0x00000001U +#define SDIO_SLCHOST_SLC_APBWIN_WR_S 28 +/** SDIO_SLCHOST_SLC_APBWIN_START : R/W/SC; bitpos: [29]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC_APBWIN_START (BIT(29)) +#define SDIO_SLCHOST_SLC_APBWIN_START_M (SDIO_SLCHOST_SLC_APBWIN_START_V << SDIO_SLCHOST_SLC_APBWIN_START_S) +#define SDIO_SLCHOST_SLC_APBWIN_START_V 0x00000001U +#define SDIO_SLCHOST_SLC_APBWIN_START_S 29 + +/** SDIO_SLC_HOST_SLC_APBWIN_RDATA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC_APBWIN_RDATA_REG (DR_REG_HOST_BASE + 0x108) +/** SDIO_SLCHOST_SLC_APBWIN_RDATA : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC_APBWIN_RDATA 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC_APBWIN_RDATA_M (SDIO_SLCHOST_SLC_APBWIN_RDATA_V << SDIO_SLCHOST_SLC_APBWIN_RDATA_S) +#define SDIO_SLCHOST_SLC_APBWIN_RDATA_V 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC_APBWIN_RDATA_S 0 + +/** SDIO_SLC_HOST_RDCLR0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_RDCLR0_REG (DR_REG_HOST_BASE + 0x10c) +/** SDIO_SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 68; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR 0x000001FFU +#define SDIO_SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_M (SDIO_SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_V << SDIO_SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_S) +#define SDIO_SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_V 0x000001FFU +#define SDIO_SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_S 0 +/** SDIO_SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR 0x000001FFU +#define SDIO_SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_M (SDIO_SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_V << SDIO_SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_S) +#define SDIO_SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_V 0x000001FFU +#define SDIO_SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_S 9 + +/** SDIO_SLC_HOST_RDCLR1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_RDCLR1_REG (DR_REG_HOST_BASE + 0x110) +/** SDIO_SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 480; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR 0x000001FFU +#define SDIO_SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_M (SDIO_SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_V << SDIO_SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_S) +#define SDIO_SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_V 0x000001FFU +#define SDIO_SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_S 0 +/** SDIO_SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR 0x000001FFU +#define SDIO_SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_M (SDIO_SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_V << SDIO_SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_S) +#define SDIO_SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_V 0x000001FFU +#define SDIO_SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_S 9 + +/** SDIO_SLC_HOST_SLC0HOST_INT_ENA1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_INT_ENA1_REG (DR_REG_HOST_BASE + 0x114) +/** SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1 (BIT(0)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_S 0 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1 (BIT(1)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_S 1 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1 (BIT(2)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_S 2 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1 (BIT(3)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_S 3 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1 (BIT(4)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_S 4 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1 (BIT(5)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_S 5 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1 (BIT(6)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_S 6 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1 (BIT(7)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_S 7 +/** SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(8)) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_S 8 +/** SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(9)) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_S 9 +/** SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1 (BIT(10)) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_S 10 +/** SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1 (BIT(11)) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_S 11 +/** SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA1 (BIT(12)) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_M (SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_V << SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_S 12 +/** SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA1 (BIT(13)) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_M (SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_V << SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_S 13 +/** SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA1 (BIT(14)) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA1_M (SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA1_V << SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA1_S 14 +/** SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA1 (BIT(15)) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA1_M (SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA1_V << SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA1_S 15 +/** SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA1 (BIT(16)) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA1_M (SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA1_V << SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA1_S 16 +/** SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA1 (BIT(17)) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA1_M (SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA1_V << SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA1_S 17 +/** SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA1 (BIT(18)) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_M (SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_V << SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_S 18 +/** SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA1 (BIT(19)) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA1_M (SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA1_V << SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA1_S 19 +/** SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA1 (BIT(20)) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA1_M (SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA1_V << SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA1_S 20 +/** SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA1 (BIT(21)) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA1_M (SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA1_V << SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA1_S 21 +/** SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA1 (BIT(22)) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA1_M (SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA1_V << SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA1_S 22 +/** SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1 (BIT(23)) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_M (SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_V << SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_S 23 +/** SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1 (BIT(24)) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_M (SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_V << SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_S 24 +/** SDIO_SLCHOST_GPIO_SDIO_INT_ENA1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_GPIO_SDIO_INT_ENA1 (BIT(25)) +#define SDIO_SLCHOST_GPIO_SDIO_INT_ENA1_M (SDIO_SLCHOST_GPIO_SDIO_INT_ENA1_V << SDIO_SLCHOST_GPIO_SDIO_INT_ENA1_S) +#define SDIO_SLCHOST_GPIO_SDIO_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_GPIO_SDIO_INT_ENA1_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_INT_ENA1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_INT_ENA1_REG (DR_REG_HOST_BASE + 0x118) +/** SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1 (BIT(0)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_S 0 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1 (BIT(1)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_S 1 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1 (BIT(2)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_S 2 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1 (BIT(3)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_S 3 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1 (BIT(4)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_S 4 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1 (BIT(5)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_S 5 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1 (BIT(6)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_S 6 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1 (BIT(7)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_S 7 +/** SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1 (BIT(8)) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_S 8 +/** SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1 (BIT(9)) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_S 9 +/** SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1 (BIT(10)) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_S 10 +/** SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1 (BIT(11)) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_S 11 +/** SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA1 (BIT(12)) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_M (SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_V << SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_S 12 +/** SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA1 (BIT(13)) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_M (SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_V << SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_S 13 +/** SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA1 (BIT(14)) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA1_M (SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA1_V << SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA1_S 14 +/** SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA1 (BIT(15)) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA1_M (SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA1_V << SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA1_S 15 +/** SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA1 (BIT(16)) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA1_M (SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA1_V << SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA1_S 16 +/** SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA1 (BIT(17)) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA1_M (SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA1_V << SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA1_S 17 +/** SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA1 (BIT(18)) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_M (SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_V << SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_S 18 +/** SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA1 (BIT(19)) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA1_M (SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA1_V << SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA1_S 19 +/** SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA1 (BIT(20)) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA1_M (SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA1_V << SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA1_S 20 +/** SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA1 (BIT(21)) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA1_M (SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA1_V << SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA1_S 21 +/** SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA1 (BIT(22)) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA1_M (SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA1_V << SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA1_S 22 +/** SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 (BIT(23)) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_M (SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V << SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S 23 +/** SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1 (BIT(24)) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_M (SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_V << SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_S 24 +/** SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 (BIT(25)) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_M (SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V << SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S 25 + +/** SDIO_SLC_HOST_DATE_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_DATE_REG (DR_REG_HOST_BASE + 0x178) +/** SDIO_SLCHOST_SLCHOST_DATE : R/W; bitpos: [31:0]; default: 554043136; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_DATE 0xFFFFFFFFU +#define SDIO_SLCHOST_SLCHOST_DATE_M (SDIO_SLCHOST_SLCHOST_DATE_V << SDIO_SLCHOST_SLCHOST_DATE_S) +#define SDIO_SLCHOST_SLCHOST_DATE_V 0xFFFFFFFFU +#define SDIO_SLCHOST_SLCHOST_DATE_S 0 + +/** SDIO_SLC_HOST_ID_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_ID_REG (DR_REG_HOST_BASE + 0x17c) +/** SDIO_SLCHOST_SLCHOST_ID : R/W; bitpos: [31:0]; default: 1536; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_ID 0xFFFFFFFFU +#define SDIO_SLCHOST_SLCHOST_ID_M (SDIO_SLCHOST_SLCHOST_ID_V << SDIO_SLCHOST_SLCHOST_ID_S) +#define SDIO_SLCHOST_SLCHOST_ID_V 0xFFFFFFFFU +#define SDIO_SLCHOST_SLCHOST_ID_S 0 + +/** SDIO_SLC_HOST_CONF_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_REG (DR_REG_HOST_BASE + 0x1f0) +/** SDIO_SLCHOST_FRC_SDIO11 : R/W; bitpos: [4:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FRC_SDIO11 0x0000001FU +#define SDIO_SLCHOST_FRC_SDIO11_M (SDIO_SLCHOST_FRC_SDIO11_V << SDIO_SLCHOST_FRC_SDIO11_S) +#define SDIO_SLCHOST_FRC_SDIO11_V 0x0000001FU +#define SDIO_SLCHOST_FRC_SDIO11_S 0 +/** SDIO_SLCHOST_FRC_SDIO20 : R/W; bitpos: [9:5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FRC_SDIO20 0x0000001FU +#define SDIO_SLCHOST_FRC_SDIO20_M (SDIO_SLCHOST_FRC_SDIO20_V << SDIO_SLCHOST_FRC_SDIO20_S) +#define SDIO_SLCHOST_FRC_SDIO20_V 0x0000001FU +#define SDIO_SLCHOST_FRC_SDIO20_S 5 +/** SDIO_SLCHOST_FRC_NEG_SAMP : R/W; bitpos: [14:10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FRC_NEG_SAMP 0x0000001FU +#define SDIO_SLCHOST_FRC_NEG_SAMP_M (SDIO_SLCHOST_FRC_NEG_SAMP_V << SDIO_SLCHOST_FRC_NEG_SAMP_S) +#define SDIO_SLCHOST_FRC_NEG_SAMP_V 0x0000001FU +#define SDIO_SLCHOST_FRC_NEG_SAMP_S 10 +/** SDIO_SLCHOST_FRC_POS_SAMP : R/W; bitpos: [19:15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FRC_POS_SAMP 0x0000001FU +#define SDIO_SLCHOST_FRC_POS_SAMP_M (SDIO_SLCHOST_FRC_POS_SAMP_V << SDIO_SLCHOST_FRC_POS_SAMP_S) +#define SDIO_SLCHOST_FRC_POS_SAMP_V 0x0000001FU +#define SDIO_SLCHOST_FRC_POS_SAMP_S 15 +/** SDIO_SLCHOST_FRC_QUICK_IN : R/W; bitpos: [24:20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FRC_QUICK_IN 0x0000001FU +#define SDIO_SLCHOST_FRC_QUICK_IN_M (SDIO_SLCHOST_FRC_QUICK_IN_V << SDIO_SLCHOST_FRC_QUICK_IN_S) +#define SDIO_SLCHOST_FRC_QUICK_IN_V 0x0000001FU +#define SDIO_SLCHOST_FRC_QUICK_IN_S 20 +/** SDIO_SLCHOST_SDIO20_INT_DELAY : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SDIO20_INT_DELAY (BIT(25)) +#define SDIO_SLCHOST_SDIO20_INT_DELAY_M (SDIO_SLCHOST_SDIO20_INT_DELAY_V << SDIO_SLCHOST_SDIO20_INT_DELAY_S) +#define SDIO_SLCHOST_SDIO20_INT_DELAY_V 0x00000001U +#define SDIO_SLCHOST_SDIO20_INT_DELAY_S 25 +/** SDIO_SLCHOST_SDIO_PAD_PULLUP : R/W; bitpos: [26]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SDIO_PAD_PULLUP (BIT(26)) +#define SDIO_SLCHOST_SDIO_PAD_PULLUP_M (SDIO_SLCHOST_SDIO_PAD_PULLUP_V << SDIO_SLCHOST_SDIO_PAD_PULLUP_S) +#define SDIO_SLCHOST_SDIO_PAD_PULLUP_V 0x00000001U +#define SDIO_SLCHOST_SDIO_PAD_PULLUP_S 26 +/** SDIO_SLCHOST_HSPEED_CON_EN : R/W; bitpos: [27]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HSPEED_CON_EN (BIT(27)) +#define SDIO_SLCHOST_HSPEED_CON_EN_M (SDIO_SLCHOST_HSPEED_CON_EN_V << SDIO_SLCHOST_HSPEED_CON_EN_S) +#define SDIO_SLCHOST_HSPEED_CON_EN_V 0x00000001U +#define SDIO_SLCHOST_HSPEED_CON_EN_S 27 + +/** SDIO_SLC_HOST_INF_ST_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_INF_ST_REG (DR_REG_HOST_BASE + 0x1f4) +/** SDIO_SLCHOST_SDIO20_MODE : RO; bitpos: [4:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SDIO20_MODE 0x0000001FU +#define SDIO_SLCHOST_SDIO20_MODE_M (SDIO_SLCHOST_SDIO20_MODE_V << SDIO_SLCHOST_SDIO20_MODE_S) +#define SDIO_SLCHOST_SDIO20_MODE_V 0x0000001FU +#define SDIO_SLCHOST_SDIO20_MODE_S 0 +/** SDIO_SLCHOST_SDIO_NEG_SAMP : RO; bitpos: [9:5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SDIO_NEG_SAMP 0x0000001FU +#define SDIO_SLCHOST_SDIO_NEG_SAMP_M (SDIO_SLCHOST_SDIO_NEG_SAMP_V << SDIO_SLCHOST_SDIO_NEG_SAMP_S) +#define SDIO_SLCHOST_SDIO_NEG_SAMP_V 0x0000001FU +#define SDIO_SLCHOST_SDIO_NEG_SAMP_S 5 +/** SDIO_SLCHOST_SDIO_QUICK_IN : RO; bitpos: [14:10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SDIO_QUICK_IN 0x0000001FU +#define SDIO_SLCHOST_SDIO_QUICK_IN_M (SDIO_SLCHOST_SDIO_QUICK_IN_V << SDIO_SLCHOST_SDIO_QUICK_IN_S) +#define SDIO_SLCHOST_SDIO_QUICK_IN_V 0x0000001FU +#define SDIO_SLCHOST_SDIO_QUICK_IN_S 10 +/** SDIO_SLCHOST_DLL_ON_SW : R/W; bitpos: [15]; default: 0; + * dll is controlled by software + */ +#define SDIO_SLCHOST_DLL_ON_SW (BIT(15)) +#define SDIO_SLCHOST_DLL_ON_SW_M (SDIO_SLCHOST_DLL_ON_SW_V << SDIO_SLCHOST_DLL_ON_SW_S) +#define SDIO_SLCHOST_DLL_ON_SW_V 0x00000001U +#define SDIO_SLCHOST_DLL_ON_SW_S 15 +/** SDIO_SLCHOST_DLL_ON : R/W; bitpos: [16]; default: 0; + * Software dll on + */ +#define SDIO_SLCHOST_DLL_ON (BIT(16)) +#define SDIO_SLCHOST_DLL_ON_M (SDIO_SLCHOST_DLL_ON_V << SDIO_SLCHOST_DLL_ON_S) +#define SDIO_SLCHOST_DLL_ON_V 0x00000001U +#define SDIO_SLCHOST_DLL_ON_S 16 +/** SDIO_SLCHOST_CLK_MODE_SW : R/W; bitpos: [17]; default: 0; + * dll clock mode is controlled by software + */ +#define SDIO_SLCHOST_CLK_MODE_SW (BIT(17)) +#define SDIO_SLCHOST_CLK_MODE_SW_M (SDIO_SLCHOST_CLK_MODE_SW_V << SDIO_SLCHOST_CLK_MODE_SW_S) +#define SDIO_SLCHOST_CLK_MODE_SW_V 0x00000001U +#define SDIO_SLCHOST_CLK_MODE_SW_S 17 +/** SDIO_SLCHOST_CLK_MODE : R/W; bitpos: [19:18]; default: 0; + * Software set clock mode + */ +#define SDIO_SLCHOST_CLK_MODE 0x00000003U +#define SDIO_SLCHOST_CLK_MODE_M (SDIO_SLCHOST_CLK_MODE_V << SDIO_SLCHOST_CLK_MODE_S) +#define SDIO_SLCHOST_CLK_MODE_V 0x00000003U +#define SDIO_SLCHOST_CLK_MODE_S 18 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/register/soc/sdio_slc_host_struct.h b/components/soc/esp32c61/register/soc/sdio_slc_host_struct.h new file mode 100644 index 0000000000..94964cd0c7 --- /dev/null +++ b/components/soc/esp32c61/register/soc/sdio_slc_host_struct.h @@ -0,0 +1,2738 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: ********Registers */ +/** Type of slc_host_func2_0 register + * *******Description*********** + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** slchost_slc_func2_int : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc_func2_int:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_host_func2_0_reg_t; + +/** Type of slc_host_func2_1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc_func2_int_en : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc_func2_int_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sdio_slc_host_func2_1_reg_t; + +/** Type of slc_host_func2_2 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc_func1_mdstat : R/W; bitpos: [0]; default: 1; + * *******Description*********** + */ + uint32_t slchost_slc_func1_mdstat:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sdio_slc_host_func2_2_reg_t; + +/** Type of slc_host_gpio_status0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_gpio_sdio_int0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_gpio_sdio_int0:32; + }; + uint32_t val; +} sdio_slc_host_gpio_status0_reg_t; + +/** Type of slc_host_gpio_status1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_gpio_sdio_int1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_gpio_sdio_int1:32; + }; + uint32_t val; +} sdio_slc_host_gpio_status1_reg_t; + +/** Type of slc_host_gpio_in0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_gpio_sdio_in0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_gpio_sdio_in0:32; + }; + uint32_t val; +} sdio_slc_host_gpio_in0_reg_t; + +/** Type of slc_host_gpio_in1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_gpio_sdio_in1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_gpio_sdio_in1:32; + }; + uint32_t val; +} sdio_slc_host_gpio_in1_reg_t; + +/** Type of slc_host_slc0host_token_rdata register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0_token0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0:12; + /** slchost_slc0_rx_pf_valid : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_pf_valid:1; + uint32_t reserved_13:3; + /** slchost_hostslchost_slc0_token1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc0_token1:12; + /** slchost_slc0_rx_pf_eof : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_pf_eof:4; + }; + uint32_t val; +} sdio_slc_host_slc0host_token_rdata_reg_t; + +/** Type of slc_host_slc0_host_pf register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0_pf_data : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_pf_data:32; + }; + uint32_t val; +} sdio_slc_host_slc0_host_pf_reg_t; + +/** Type of slc_host_slc1_host_pf register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1_pf_data : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_pf_data:32; + }; + uint32_t val; +} sdio_slc_host_slc1_host_pf_reg_t; + +/** Type of slc_host_slc0host_int_raw register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0_tohost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit0_int_raw:1; + /** slchost_slc0_tohost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit1_int_raw:1; + /** slchost_slc0_tohost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit2_int_raw:1; + /** slchost_slc0_tohost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit3_int_raw:1; + /** slchost_slc0_tohost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit4_int_raw:1; + /** slchost_slc0_tohost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit5_int_raw:1; + /** slchost_slc0_tohost_bit6_int_raw : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit6_int_raw:1; + /** slchost_slc0_tohost_bit7_int_raw : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit7_int_raw:1; + /** slchost_slc0_token0_1to0_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_1to0_int_raw:1; + /** slchost_slc0_token1_1to0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_1to0_int_raw:1; + /** slchost_slc0_token0_0to1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_0to1_int_raw:1; + /** slchost_slc0_token1_0to1_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_0to1_int_raw:1; + /** slchost_slc0host_rx_sof_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_sof_int_raw:1; + /** slchost_slc0host_rx_eof_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_eof_int_raw:1; + /** slchost_slc0host_rx_start_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_start_int_raw:1; + /** slchost_slc0host_tx_start_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_tx_start_int_raw:1; + /** slchost_slc0_rx_udf_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_udf_int_raw:1; + /** slchost_slc0_tx_ovf_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tx_ovf_int_raw:1; + /** slchost_slc0_rx_pf_valid_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_pf_valid_int_raw:1; + /** slchost_slc0_ext_bit0_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit0_int_raw:1; + /** slchost_slc0_ext_bit1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit1_int_raw:1; + /** slchost_slc0_ext_bit2_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit2_int_raw:1; + /** slchost_slc0_ext_bit3_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit3_int_raw:1; + /** slchost_slc0_rx_new_packet_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_new_packet_int_raw:1; + /** slchost_slc0_host_rd_retry_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_host_rd_retry_int_raw:1; + /** slchost_gpio_sdio_int_raw : R/WTC/SS/SC; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_gpio_sdio_int_raw:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_int_raw_reg_t; + +/** Type of slc_host_slc1host_int_raw register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1_tohost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit0_int_raw:1; + /** slchost_slc1_tohost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit1_int_raw:1; + /** slchost_slc1_tohost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit2_int_raw:1; + /** slchost_slc1_tohost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit3_int_raw:1; + /** slchost_slc1_tohost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit4_int_raw:1; + /** slchost_slc1_tohost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit5_int_raw:1; + /** slchost_slc1_tohost_bit6_int_raw : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit6_int_raw:1; + /** slchost_slc1_tohost_bit7_int_raw : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit7_int_raw:1; + /** slchost_slc1_token0_1to0_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_1to0_int_raw:1; + /** slchost_slc1_token1_1to0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_1to0_int_raw:1; + /** slchost_slc1_token0_0to1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_0to1_int_raw:1; + /** slchost_slc1_token1_0to1_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_0to1_int_raw:1; + /** slchost_slc1host_rx_sof_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_sof_int_raw:1; + /** slchost_slc1host_rx_eof_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_eof_int_raw:1; + /** slchost_slc1host_rx_start_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_start_int_raw:1; + /** slchost_slc1host_tx_start_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_tx_start_int_raw:1; + /** slchost_slc1_rx_udf_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_udf_int_raw:1; + /** slchost_slc1_tx_ovf_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tx_ovf_int_raw:1; + /** slchost_slc1_rx_pf_valid_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_pf_valid_int_raw:1; + /** slchost_slc1_ext_bit0_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit0_int_raw:1; + /** slchost_slc1_ext_bit1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit1_int_raw:1; + /** slchost_slc1_ext_bit2_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit2_int_raw:1; + /** slchost_slc1_ext_bit3_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit3_int_raw:1; + /** slchost_slc1_wifi_rx_new_packet_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_wifi_rx_new_packet_int_raw:1; + /** slchost_slc1_host_rd_retry_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_host_rd_retry_int_raw:1; + /** slchost_slc1_bt_rx_new_packet_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_bt_rx_new_packet_int_raw:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_int_raw_reg_t; + +/** Type of slc_host_slc0host_int_st register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0_tohost_bit0_int_st : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit0_int_st:1; + /** slchost_slc0_tohost_bit1_int_st : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit1_int_st:1; + /** slchost_slc0_tohost_bit2_int_st : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit2_int_st:1; + /** slchost_slc0_tohost_bit3_int_st : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit3_int_st:1; + /** slchost_slc0_tohost_bit4_int_st : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit4_int_st:1; + /** slchost_slc0_tohost_bit5_int_st : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit5_int_st:1; + /** slchost_slc0_tohost_bit6_int_st : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit6_int_st:1; + /** slchost_slc0_tohost_bit7_int_st : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit7_int_st:1; + /** slchost_slc0_token0_1to0_int_st : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_1to0_int_st:1; + /** slchost_slc0_token1_1to0_int_st : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_1to0_int_st:1; + /** slchost_slc0_token0_0to1_int_st : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_0to1_int_st:1; + /** slchost_slc0_token1_0to1_int_st : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_0to1_int_st:1; + /** slchost_slc0host_rx_sof_int_st : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_sof_int_st:1; + /** slchost_slc0host_rx_eof_int_st : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_eof_int_st:1; + /** slchost_slc0host_rx_start_int_st : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_start_int_st:1; + /** slchost_slc0host_tx_start_int_st : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_tx_start_int_st:1; + /** slchost_slc0_rx_udf_int_st : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_udf_int_st:1; + /** slchost_slc0_tx_ovf_int_st : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tx_ovf_int_st:1; + /** slchost_slc0_rx_pf_valid_int_st : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_pf_valid_int_st:1; + /** slchost_slc0_ext_bit0_int_st : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit0_int_st:1; + /** slchost_slc0_ext_bit1_int_st : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit1_int_st:1; + /** slchost_slc0_ext_bit2_int_st : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit2_int_st:1; + /** slchost_slc0_ext_bit3_int_st : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit3_int_st:1; + /** slchost_slc0_rx_new_packet_int_st : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_new_packet_int_st:1; + /** slchost_slc0_host_rd_retry_int_st : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_host_rd_retry_int_st:1; + /** slchost_gpio_sdio_int_st : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_gpio_sdio_int_st:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_int_st_reg_t; + +/** Type of slc_host_slc1host_int_st register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1_tohost_bit0_int_st : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit0_int_st:1; + /** slchost_slc1_tohost_bit1_int_st : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit1_int_st:1; + /** slchost_slc1_tohost_bit2_int_st : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit2_int_st:1; + /** slchost_slc1_tohost_bit3_int_st : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit3_int_st:1; + /** slchost_slc1_tohost_bit4_int_st : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit4_int_st:1; + /** slchost_slc1_tohost_bit5_int_st : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit5_int_st:1; + /** slchost_slc1_tohost_bit6_int_st : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit6_int_st:1; + /** slchost_slc1_tohost_bit7_int_st : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit7_int_st:1; + /** slchost_slc1_token0_1to0_int_st : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_1to0_int_st:1; + /** slchost_slc1_token1_1to0_int_st : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_1to0_int_st:1; + /** slchost_slc1_token0_0to1_int_st : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_0to1_int_st:1; + /** slchost_slc1_token1_0to1_int_st : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_0to1_int_st:1; + /** slchost_slc1host_rx_sof_int_st : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_sof_int_st:1; + /** slchost_slc1host_rx_eof_int_st : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_eof_int_st:1; + /** slchost_slc1host_rx_start_int_st : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_start_int_st:1; + /** slchost_slc1host_tx_start_int_st : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_tx_start_int_st:1; + /** slchost_slc1_rx_udf_int_st : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_udf_int_st:1; + /** slchost_slc1_tx_ovf_int_st : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tx_ovf_int_st:1; + /** slchost_slc1_rx_pf_valid_int_st : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_pf_valid_int_st:1; + /** slchost_slc1_ext_bit0_int_st : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit0_int_st:1; + /** slchost_slc1_ext_bit1_int_st : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit1_int_st:1; + /** slchost_slc1_ext_bit2_int_st : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit2_int_st:1; + /** slchost_slc1_ext_bit3_int_st : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit3_int_st:1; + /** slchost_slc1_wifi_rx_new_packet_int_st : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_wifi_rx_new_packet_int_st:1; + /** slchost_slc1_host_rd_retry_int_st : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_host_rd_retry_int_st:1; + /** slchost_slc1_bt_rx_new_packet_int_st : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_bt_rx_new_packet_int_st:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_int_st_reg_t; + +/** Type of slc_host_pkt_len register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_hostslchost_slc0_len : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc0_len:20; + /** slchost_hostslchost_slc0_len_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc0_len_check:12; + }; + uint32_t val; +} sdio_slc_host_pkt_len_reg_t; + +/** Type of slc_host_state_w0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_state0 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_state0:8; + /** slchost_slchost_state1 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_state1:8; + /** slchost_slchost_state2 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_state2:8; + /** slchost_slchost_state3 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_state3:8; + }; + uint32_t val; +} sdio_slc_host_state_w0_reg_t; + +/** Type of slc_host_state_w1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_state4 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_state4:8; + /** slchost_slchost_state5 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_state5:8; + /** slchost_slchost_state6 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_state6:8; + /** slchost_slchost_state7 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_state7:8; + }; + uint32_t val; +} sdio_slc_host_state_w1_reg_t; + +/** Type of slc_host_conf_w0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf0 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf0:8; + /** slchost_slchost_conf1 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf1:8; + /** slchost_slchost_conf2 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf2:8; + /** slchost_slchost_conf3 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf3:8; + }; + uint32_t val; +} sdio_slc_host_conf_w0_reg_t; + +/** Type of slc_host_conf_w1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf4 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf4:8; + /** slchost_slchost_conf5 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf5:8; + /** slchost_slchost_conf6 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf6:8; + /** slchost_slchost_conf7 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf7:8; + }; + uint32_t val; +} sdio_slc_host_conf_w1_reg_t; + +/** Type of slc_host_conf_w2 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf8 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf8:8; + /** slchost_slchost_conf9 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf9:8; + /** slchost_slchost_conf10 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf10:8; + /** slchost_slchost_conf11 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf11:8; + }; + uint32_t val; +} sdio_slc_host_conf_w2_reg_t; + +/** Type of slc_host_conf_w3 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf12 : R/W; bitpos: [7:0]; default: 192; + * *******Description*********** + */ + uint32_t slchost_slchost_conf12:8; + /** slchost_slchost_conf13 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf13:8; + /** slchost_slchost_conf14 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf14:8; + /** slchost_slchost_conf15 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf15:8; + }; + uint32_t val; +} sdio_slc_host_conf_w3_reg_t; + +/** Type of slc_host_conf_w4 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf16 : R/W; bitpos: [7:0]; default: 255; + * *******Description*********** + */ + uint32_t slchost_slchost_conf16:8; + /** slchost_slchost_conf17 : R/W; bitpos: [15:8]; default: 1; + * *******Description*********** + */ + uint32_t slchost_slchost_conf17:8; + /** slchost_slchost_conf18 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf18:8; + /** slchost_slchost_conf19 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf19:8; + }; + uint32_t val; +} sdio_slc_host_conf_w4_reg_t; + +/** Type of slc_host_conf_w5 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf20 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf20:8; + /** slchost_slchost_conf21 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf21:8; + /** slchost_slchost_conf22 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf22:8; + /** slchost_slchost_conf23 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf23:8; + }; + uint32_t val; +} sdio_slc_host_conf_w5_reg_t; + +/** Type of slc_host_win_cmd register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_win_cmd : R/W; bitpos: [15:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_win_cmd:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} sdio_slc_host_win_cmd_reg_t; + +/** Type of slc_host_conf_w6 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf24 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf24:8; + /** slchost_slchost_conf25 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf25:8; + /** slchost_slchost_conf26 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf26:8; + /** slchost_slchost_conf27 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf27:8; + }; + uint32_t val; +} sdio_slc_host_conf_w6_reg_t; + +/** Type of slc_host_conf_w7 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf28 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf28:8; + /** slchost_slchost_conf29 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf29:8; + /** slchost_slchost_conf30 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf30:8; + /** slchost_slchost_conf31 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf31:8; + }; + uint32_t val; +} sdio_slc_host_conf_w7_reg_t; + +/** Type of slc_host_pkt_len0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_hostslchost_slc0_len0 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc0_len0:20; + /** slchost_hostslchost_slc0_len0_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc0_len0_check:12; + }; + uint32_t val; +} sdio_slc_host_pkt_len0_reg_t; + +/** Type of slc_host_pkt_len1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_hostslchost_slc0_len1 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc0_len1:20; + /** slchost_hostslchost_slc0_len1_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc0_len1_check:12; + }; + uint32_t val; +} sdio_slc_host_pkt_len1_reg_t; + +/** Type of slc_host_pkt_len2 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_hostslchost_slc0_len2 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc0_len2:20; + /** slchost_hostslchost_slc0_len2_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc0_len2_check:12; + }; + uint32_t val; +} sdio_slc_host_pkt_len2_reg_t; + +/** Type of slc_host_conf_w8 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf32 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf32:8; + /** slchost_slchost_conf33 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf33:8; + /** slchost_slchost_conf34 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf34:8; + /** slchost_slchost_conf35 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf35:8; + }; + uint32_t val; +} sdio_slc_host_conf_w8_reg_t; + +/** Type of slc_host_conf_w9 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf36 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf36:8; + /** slchost_slchost_conf37 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf37:8; + /** slchost_slchost_conf38 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf38:8; + /** slchost_slchost_conf39 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf39:8; + }; + uint32_t val; +} sdio_slc_host_conf_w9_reg_t; + +/** Type of slc_host_conf_w10 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf40 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf40:8; + /** slchost_slchost_conf41 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf41:8; + /** slchost_slchost_conf42 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf42:8; + /** slchost_slchost_conf43 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf43:8; + }; + uint32_t val; +} sdio_slc_host_conf_w10_reg_t; + +/** Type of slc_host_conf_w11 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf44 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf44:8; + /** slchost_slchost_conf45 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf45:8; + /** slchost_slchost_conf46 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf46:8; + /** slchost_slchost_conf47 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf47:8; + }; + uint32_t val; +} sdio_slc_host_conf_w11_reg_t; + +/** Type of slc_host_conf_w12 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf48 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf48:8; + /** slchost_slchost_conf49 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf49:8; + /** slchost_slchost_conf50 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf50:8; + /** slchost_slchost_conf51 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf51:8; + }; + uint32_t val; +} sdio_slc_host_conf_w12_reg_t; + +/** Type of slc_host_conf_w13 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf52 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf52:8; + /** slchost_slchost_conf53 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf53:8; + /** slchost_slchost_conf54 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf54:8; + /** slchost_slchost_conf55 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf55:8; + }; + uint32_t val; +} sdio_slc_host_conf_w13_reg_t; + +/** Type of slc_host_conf_w14 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf56 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf56:8; + /** slchost_slchost_conf57 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf57:8; + /** slchost_slchost_conf58 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf58:8; + /** slchost_slchost_conf59 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf59:8; + }; + uint32_t val; +} sdio_slc_host_conf_w14_reg_t; + +/** Type of slc_host_conf_w15 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf60 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf60:8; + /** slchost_slchost_conf61 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf61:8; + /** slchost_slchost_conf62 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf62:8; + /** slchost_slchost_conf63 : R/W; bitpos: [31:24]; default: 0; + * Bit [27:24] used for reg_slc_apbwin_addr[31:28] + */ + uint32_t slchost_slchost_conf63:8; + }; + uint32_t val; +} sdio_slc_host_conf_w15_reg_t; + +/** Type of slc_host_check_sum0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_check_sum0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_check_sum0:32; + }; + uint32_t val; +} sdio_slc_host_check_sum0_reg_t; + +/** Type of slc_host_check_sum1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_check_sum1 : RO; bitpos: [31:0]; default: 319; + * *******Description*********** + */ + uint32_t slchost_slchost_check_sum1:32; + }; + uint32_t val; +} sdio_slc_host_check_sum1_reg_t; + +/** Type of slc_host_slc1host_token_rdata register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1_token0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0:12; + /** slchost_slc1_rx_pf_valid : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_pf_valid:1; + uint32_t reserved_13:3; + /** slchost_hostslchost_slc1_token1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc1_token1:12; + /** slchost_slc1_rx_pf_eof : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_pf_eof:4; + }; + uint32_t val; +} sdio_slc_host_slc1host_token_rdata_reg_t; + +/** Type of slc_host_slc0host_token_wdata register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0host_token0_wd : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_token0_wd:12; + uint32_t reserved_12:4; + /** slchost_slc0host_token1_wd : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_token1_wd:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_host_slc0host_token_wdata_reg_t; + +/** Type of slc_host_slc1host_token_wdata register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1host_token0_wd : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_token0_wd:12; + uint32_t reserved_12:4; + /** slchost_slc1host_token1_wd : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_token1_wd:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_host_slc1host_token_wdata_reg_t; + +/** Type of slc_host_token_con register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0host_token0_dec : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_token0_dec:1; + /** slchost_slc0host_token1_dec : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_token1_dec:1; + /** slchost_slc0host_token0_wr : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_token0_wr:1; + /** slchost_slc0host_token1_wr : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_token1_wr:1; + /** slchost_slc1host_token0_dec : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_token0_dec:1; + /** slchost_slc1host_token1_dec : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_token1_dec:1; + /** slchost_slc1host_token0_wr : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_token0_wr:1; + /** slchost_slc1host_token1_wr : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_token1_wr:1; + /** slchost_slc0host_len_wr : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_len_wr:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} sdio_slc_host_token_con_reg_t; + +/** Type of slc_host_slc0host_int_clr register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0_tohost_bit0_int_clr : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit0_int_clr:1; + /** slchost_slc0_tohost_bit1_int_clr : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit1_int_clr:1; + /** slchost_slc0_tohost_bit2_int_clr : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit2_int_clr:1; + /** slchost_slc0_tohost_bit3_int_clr : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit3_int_clr:1; + /** slchost_slc0_tohost_bit4_int_clr : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit4_int_clr:1; + /** slchost_slc0_tohost_bit5_int_clr : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit5_int_clr:1; + /** slchost_slc0_tohost_bit6_int_clr : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit6_int_clr:1; + /** slchost_slc0_tohost_bit7_int_clr : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit7_int_clr:1; + /** slchost_slc0_token0_1to0_int_clr : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_1to0_int_clr:1; + /** slchost_slc0_token1_1to0_int_clr : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_1to0_int_clr:1; + /** slchost_slc0_token0_0to1_int_clr : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_0to1_int_clr:1; + /** slchost_slc0_token1_0to1_int_clr : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_0to1_int_clr:1; + /** slchost_slc0host_rx_sof_int_clr : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_sof_int_clr:1; + /** slchost_slc0host_rx_eof_int_clr : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_eof_int_clr:1; + /** slchost_slc0host_rx_start_int_clr : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_start_int_clr:1; + /** slchost_slc0host_tx_start_int_clr : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_tx_start_int_clr:1; + /** slchost_slc0_rx_udf_int_clr : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_udf_int_clr:1; + /** slchost_slc0_tx_ovf_int_clr : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tx_ovf_int_clr:1; + /** slchost_slc0_rx_pf_valid_int_clr : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_pf_valid_int_clr:1; + /** slchost_slc0_ext_bit0_int_clr : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit0_int_clr:1; + /** slchost_slc0_ext_bit1_int_clr : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit1_int_clr:1; + /** slchost_slc0_ext_bit2_int_clr : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit2_int_clr:1; + /** slchost_slc0_ext_bit3_int_clr : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit3_int_clr:1; + /** slchost_slc0_rx_new_packet_int_clr : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_new_packet_int_clr:1; + /** slchost_slc0_host_rd_retry_int_clr : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_host_rd_retry_int_clr:1; + /** slchost_gpio_sdio_int_clr : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_gpio_sdio_int_clr:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_int_clr_reg_t; + +/** Type of slc_host_slc1host_int_clr register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1_tohost_bit0_int_clr : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit0_int_clr:1; + /** slchost_slc1_tohost_bit1_int_clr : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit1_int_clr:1; + /** slchost_slc1_tohost_bit2_int_clr : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit2_int_clr:1; + /** slchost_slc1_tohost_bit3_int_clr : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit3_int_clr:1; + /** slchost_slc1_tohost_bit4_int_clr : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit4_int_clr:1; + /** slchost_slc1_tohost_bit5_int_clr : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit5_int_clr:1; + /** slchost_slc1_tohost_bit6_int_clr : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit6_int_clr:1; + /** slchost_slc1_tohost_bit7_int_clr : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit7_int_clr:1; + /** slchost_slc1_token0_1to0_int_clr : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_1to0_int_clr:1; + /** slchost_slc1_token1_1to0_int_clr : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_1to0_int_clr:1; + /** slchost_slc1_token0_0to1_int_clr : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_0to1_int_clr:1; + /** slchost_slc1_token1_0to1_int_clr : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_0to1_int_clr:1; + /** slchost_slc1host_rx_sof_int_clr : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_sof_int_clr:1; + /** slchost_slc1host_rx_eof_int_clr : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_eof_int_clr:1; + /** slchost_slc1host_rx_start_int_clr : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_start_int_clr:1; + /** slchost_slc1host_tx_start_int_clr : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_tx_start_int_clr:1; + /** slchost_slc1_rx_udf_int_clr : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_udf_int_clr:1; + /** slchost_slc1_tx_ovf_int_clr : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tx_ovf_int_clr:1; + /** slchost_slc1_rx_pf_valid_int_clr : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_pf_valid_int_clr:1; + /** slchost_slc1_ext_bit0_int_clr : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit0_int_clr:1; + /** slchost_slc1_ext_bit1_int_clr : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit1_int_clr:1; + /** slchost_slc1_ext_bit2_int_clr : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit2_int_clr:1; + /** slchost_slc1_ext_bit3_int_clr : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit3_int_clr:1; + /** slchost_slc1_wifi_rx_new_packet_int_clr : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_wifi_rx_new_packet_int_clr:1; + /** slchost_slc1_host_rd_retry_int_clr : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_host_rd_retry_int_clr:1; + /** slchost_slc1_bt_rx_new_packet_int_clr : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_bt_rx_new_packet_int_clr:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_int_clr_reg_t; + +/** Type of slc_host_slc0host_func1_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_fn1_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_tohost_bit0_int_ena:1; + /** slchost_fn1_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_tohost_bit1_int_ena:1; + /** slchost_fn1_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_tohost_bit2_int_ena:1; + /** slchost_fn1_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_tohost_bit3_int_ena:1; + /** slchost_fn1_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_tohost_bit4_int_ena:1; + /** slchost_fn1_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_tohost_bit5_int_ena:1; + /** slchost_fn1_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_tohost_bit6_int_ena:1; + /** slchost_fn1_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_tohost_bit7_int_ena:1; + /** slchost_fn1_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_token0_1to0_int_ena:1; + /** slchost_fn1_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_token1_1to0_int_ena:1; + /** slchost_fn1_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_token0_0to1_int_ena:1; + /** slchost_fn1_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_token1_0to1_int_ena:1; + /** slchost_fn1_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0host_rx_sof_int_ena:1; + /** slchost_fn1_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0host_rx_eof_int_ena:1; + /** slchost_fn1_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0host_rx_start_int_ena:1; + /** slchost_fn1_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0host_tx_start_int_ena:1; + /** slchost_fn1_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_rx_udf_int_ena:1; + /** slchost_fn1_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_tx_ovf_int_ena:1; + /** slchost_fn1_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_rx_pf_valid_int_ena:1; + /** slchost_fn1_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_ext_bit0_int_ena:1; + /** slchost_fn1_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_ext_bit1_int_ena:1; + /** slchost_fn1_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_ext_bit2_int_ena:1; + /** slchost_fn1_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_ext_bit3_int_ena:1; + /** slchost_fn1_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_rx_new_packet_int_ena:1; + /** slchost_fn1_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_host_rd_retry_int_ena:1; + /** slchost_fn1_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_gpio_sdio_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_func1_int_ena_reg_t; + +/** Type of slc_host_slc1host_func1_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_fn1_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_tohost_bit0_int_ena:1; + /** slchost_fn1_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_tohost_bit1_int_ena:1; + /** slchost_fn1_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_tohost_bit2_int_ena:1; + /** slchost_fn1_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_tohost_bit3_int_ena:1; + /** slchost_fn1_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_tohost_bit4_int_ena:1; + /** slchost_fn1_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_tohost_bit5_int_ena:1; + /** slchost_fn1_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_tohost_bit6_int_ena:1; + /** slchost_fn1_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_tohost_bit7_int_ena:1; + /** slchost_fn1_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_token0_1to0_int_ena:1; + /** slchost_fn1_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_token1_1to0_int_ena:1; + /** slchost_fn1_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_token0_0to1_int_ena:1; + /** slchost_fn1_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_token1_0to1_int_ena:1; + /** slchost_fn1_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1host_rx_sof_int_ena:1; + /** slchost_fn1_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1host_rx_eof_int_ena:1; + /** slchost_fn1_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1host_rx_start_int_ena:1; + /** slchost_fn1_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1host_tx_start_int_ena:1; + /** slchost_fn1_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_rx_udf_int_ena:1; + /** slchost_fn1_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_tx_ovf_int_ena:1; + /** slchost_fn1_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_rx_pf_valid_int_ena:1; + /** slchost_fn1_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_ext_bit0_int_ena:1; + /** slchost_fn1_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_ext_bit1_int_ena:1; + /** slchost_fn1_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_ext_bit2_int_ena:1; + /** slchost_fn1_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_ext_bit3_int_ena:1; + /** slchost_fn1_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_wifi_rx_new_packet_int_ena:1; + /** slchost_fn1_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_host_rd_retry_int_ena:1; + /** slchost_fn1_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_bt_rx_new_packet_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_func1_int_ena_reg_t; + +/** Type of slc_host_slc0host_func2_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_fn2_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_tohost_bit0_int_ena:1; + /** slchost_fn2_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_tohost_bit1_int_ena:1; + /** slchost_fn2_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_tohost_bit2_int_ena:1; + /** slchost_fn2_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_tohost_bit3_int_ena:1; + /** slchost_fn2_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_tohost_bit4_int_ena:1; + /** slchost_fn2_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_tohost_bit5_int_ena:1; + /** slchost_fn2_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_tohost_bit6_int_ena:1; + /** slchost_fn2_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_tohost_bit7_int_ena:1; + /** slchost_fn2_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_token0_1to0_int_ena:1; + /** slchost_fn2_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_token1_1to0_int_ena:1; + /** slchost_fn2_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_token0_0to1_int_ena:1; + /** slchost_fn2_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_token1_0to1_int_ena:1; + /** slchost_fn2_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0host_rx_sof_int_ena:1; + /** slchost_fn2_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0host_rx_eof_int_ena:1; + /** slchost_fn2_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0host_rx_start_int_ena:1; + /** slchost_fn2_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0host_tx_start_int_ena:1; + /** slchost_fn2_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_rx_udf_int_ena:1; + /** slchost_fn2_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_tx_ovf_int_ena:1; + /** slchost_fn2_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_rx_pf_valid_int_ena:1; + /** slchost_fn2_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_ext_bit0_int_ena:1; + /** slchost_fn2_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_ext_bit1_int_ena:1; + /** slchost_fn2_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_ext_bit2_int_ena:1; + /** slchost_fn2_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_ext_bit3_int_ena:1; + /** slchost_fn2_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_rx_new_packet_int_ena:1; + /** slchost_fn2_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_host_rd_retry_int_ena:1; + /** slchost_fn2_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_gpio_sdio_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_func2_int_ena_reg_t; + +/** Type of slc_host_slc1host_func2_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_fn2_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_tohost_bit0_int_ena:1; + /** slchost_fn2_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_tohost_bit1_int_ena:1; + /** slchost_fn2_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_tohost_bit2_int_ena:1; + /** slchost_fn2_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_tohost_bit3_int_ena:1; + /** slchost_fn2_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_tohost_bit4_int_ena:1; + /** slchost_fn2_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_tohost_bit5_int_ena:1; + /** slchost_fn2_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_tohost_bit6_int_ena:1; + /** slchost_fn2_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_tohost_bit7_int_ena:1; + /** slchost_fn2_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_token0_1to0_int_ena:1; + /** slchost_fn2_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_token1_1to0_int_ena:1; + /** slchost_fn2_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_token0_0to1_int_ena:1; + /** slchost_fn2_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_token1_0to1_int_ena:1; + /** slchost_fn2_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1host_rx_sof_int_ena:1; + /** slchost_fn2_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1host_rx_eof_int_ena:1; + /** slchost_fn2_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1host_rx_start_int_ena:1; + /** slchost_fn2_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1host_tx_start_int_ena:1; + /** slchost_fn2_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_rx_udf_int_ena:1; + /** slchost_fn2_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_tx_ovf_int_ena:1; + /** slchost_fn2_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_rx_pf_valid_int_ena:1; + /** slchost_fn2_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_ext_bit0_int_ena:1; + /** slchost_fn2_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_ext_bit1_int_ena:1; + /** slchost_fn2_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_ext_bit2_int_ena:1; + /** slchost_fn2_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_ext_bit3_int_ena:1; + /** slchost_fn2_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_wifi_rx_new_packet_int_ena:1; + /** slchost_fn2_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_host_rd_retry_int_ena:1; + /** slchost_fn2_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_bt_rx_new_packet_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_func2_int_ena_reg_t; + +/** Type of slc_host_slc0host_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit0_int_ena:1; + /** slchost_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit1_int_ena:1; + /** slchost_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit2_int_ena:1; + /** slchost_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit3_int_ena:1; + /** slchost_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit4_int_ena:1; + /** slchost_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit5_int_ena:1; + /** slchost_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit6_int_ena:1; + /** slchost_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit7_int_ena:1; + /** slchost_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_1to0_int_ena:1; + /** slchost_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_1to0_int_ena:1; + /** slchost_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_0to1_int_ena:1; + /** slchost_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_0to1_int_ena:1; + /** slchost_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_sof_int_ena:1; + /** slchost_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_eof_int_ena:1; + /** slchost_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_start_int_ena:1; + /** slchost_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_tx_start_int_ena:1; + /** slchost_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_udf_int_ena:1; + /** slchost_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tx_ovf_int_ena:1; + /** slchost_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_pf_valid_int_ena:1; + /** slchost_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit0_int_ena:1; + /** slchost_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit1_int_ena:1; + /** slchost_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit2_int_ena:1; + /** slchost_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit3_int_ena:1; + /** slchost_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_new_packet_int_ena:1; + /** slchost_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_host_rd_retry_int_ena:1; + /** slchost_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_gpio_sdio_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_int_ena_reg_t; + +/** Type of slc_host_slc1host_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit0_int_ena:1; + /** slchost_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit1_int_ena:1; + /** slchost_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit2_int_ena:1; + /** slchost_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit3_int_ena:1; + /** slchost_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit4_int_ena:1; + /** slchost_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit5_int_ena:1; + /** slchost_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit6_int_ena:1; + /** slchost_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit7_int_ena:1; + /** slchost_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_1to0_int_ena:1; + /** slchost_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_1to0_int_ena:1; + /** slchost_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_0to1_int_ena:1; + /** slchost_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_0to1_int_ena:1; + /** slchost_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_sof_int_ena:1; + /** slchost_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_eof_int_ena:1; + /** slchost_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_start_int_ena:1; + /** slchost_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_tx_start_int_ena:1; + /** slchost_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_udf_int_ena:1; + /** slchost_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tx_ovf_int_ena:1; + /** slchost_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_pf_valid_int_ena:1; + /** slchost_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit0_int_ena:1; + /** slchost_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit1_int_ena:1; + /** slchost_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit2_int_ena:1; + /** slchost_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit3_int_ena:1; + /** slchost_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_wifi_rx_new_packet_int_ena:1; + /** slchost_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_host_rd_retry_int_ena:1; + /** slchost_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_bt_rx_new_packet_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_int_ena_reg_t; + +/** Type of slc_host_slc0host_rx_infor register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0host_rx_infor : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_infor:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} sdio_slc_host_slc0host_rx_infor_reg_t; + +/** Type of slc_host_slc1host_rx_infor register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1host_rx_infor : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_infor:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} sdio_slc_host_slc1host_rx_infor_reg_t; + +/** Type of slc_host_slc0host_len_wd register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0host_len_wd : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_len_wd:32; + }; + uint32_t val; +} sdio_slc_host_slc0host_len_wd_reg_t; + +/** Type of slc_host_slc_apbwin_wdata register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc_apbwin_wdata : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc_apbwin_wdata:32; + }; + uint32_t val; +} sdio_slc_host_slc_apbwin_wdata_reg_t; + +/** Type of slc_host_slc_apbwin_conf register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc_apbwin_addr : R/W; bitpos: [27:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc_apbwin_addr:28; + /** slchost_slc_apbwin_wr : R/W; bitpos: [28]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc_apbwin_wr:1; + /** slchost_slc_apbwin_start : R/W/SC; bitpos: [29]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc_apbwin_start:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} sdio_slc_host_slc_apbwin_conf_reg_t; + +/** Type of slc_host_slc_apbwin_rdata register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc_apbwin_rdata : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc_apbwin_rdata:32; + }; + uint32_t val; +} sdio_slc_host_slc_apbwin_rdata_reg_t; + +/** Type of slc_host_rdclr0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_slc0_bit7_clraddr : R/W; bitpos: [8:0]; default: 68; + * *******Description*********** + */ + uint32_t slchost_slchost_slc0_bit7_clraddr:9; + /** slchost_slchost_slc0_bit6_clraddr : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ + uint32_t slchost_slchost_slc0_bit6_clraddr:9; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdio_slc_host_rdclr0_reg_t; + +/** Type of slc_host_rdclr1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_slc1_bit7_clraddr : R/W; bitpos: [8:0]; default: 480; + * *******Description*********** + */ + uint32_t slchost_slchost_slc1_bit7_clraddr:9; + /** slchost_slchost_slc1_bit6_clraddr : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ + uint32_t slchost_slchost_slc1_bit6_clraddr:9; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdio_slc_host_rdclr1_reg_t; + +/** Type of slc_host_slc0host_int_ena1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0_tohost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit0_int_ena1:1; + /** slchost_slc0_tohost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit1_int_ena1:1; + /** slchost_slc0_tohost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit2_int_ena1:1; + /** slchost_slc0_tohost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit3_int_ena1:1; + /** slchost_slc0_tohost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit4_int_ena1:1; + /** slchost_slc0_tohost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit5_int_ena1:1; + /** slchost_slc0_tohost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit6_int_ena1:1; + /** slchost_slc0_tohost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit7_int_ena1:1; + /** slchost_slc0_token0_1to0_int_ena1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_1to0_int_ena1:1; + /** slchost_slc0_token1_1to0_int_ena1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_1to0_int_ena1:1; + /** slchost_slc0_token0_0to1_int_ena1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_0to1_int_ena1:1; + /** slchost_slc0_token1_0to1_int_ena1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_0to1_int_ena1:1; + /** slchost_slc0host_rx_sof_int_ena1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_sof_int_ena1:1; + /** slchost_slc0host_rx_eof_int_ena1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_eof_int_ena1:1; + /** slchost_slc0host_rx_start_int_ena1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_start_int_ena1:1; + /** slchost_slc0host_tx_start_int_ena1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_tx_start_int_ena1:1; + /** slchost_slc0_rx_udf_int_ena1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_udf_int_ena1:1; + /** slchost_slc0_tx_ovf_int_ena1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tx_ovf_int_ena1:1; + /** slchost_slc0_rx_pf_valid_int_ena1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_pf_valid_int_ena1:1; + /** slchost_slc0_ext_bit0_int_ena1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit0_int_ena1:1; + /** slchost_slc0_ext_bit1_int_ena1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit1_int_ena1:1; + /** slchost_slc0_ext_bit2_int_ena1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit2_int_ena1:1; + /** slchost_slc0_ext_bit3_int_ena1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit3_int_ena1:1; + /** slchost_slc0_rx_new_packet_int_ena1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_new_packet_int_ena1:1; + /** slchost_slc0_host_rd_retry_int_ena1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_host_rd_retry_int_ena1:1; + /** slchost_gpio_sdio_int_ena1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_gpio_sdio_int_ena1:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_int_ena1_reg_t; + +/** Type of slc_host_slc1host_int_ena1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1_tohost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit0_int_ena1:1; + /** slchost_slc1_tohost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit1_int_ena1:1; + /** slchost_slc1_tohost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit2_int_ena1:1; + /** slchost_slc1_tohost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit3_int_ena1:1; + /** slchost_slc1_tohost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit4_int_ena1:1; + /** slchost_slc1_tohost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit5_int_ena1:1; + /** slchost_slc1_tohost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit6_int_ena1:1; + /** slchost_slc1_tohost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit7_int_ena1:1; + /** slchost_slc1_token0_1to0_int_ena1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_1to0_int_ena1:1; + /** slchost_slc1_token1_1to0_int_ena1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_1to0_int_ena1:1; + /** slchost_slc1_token0_0to1_int_ena1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_0to1_int_ena1:1; + /** slchost_slc1_token1_0to1_int_ena1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_0to1_int_ena1:1; + /** slchost_slc1host_rx_sof_int_ena1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_sof_int_ena1:1; + /** slchost_slc1host_rx_eof_int_ena1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_eof_int_ena1:1; + /** slchost_slc1host_rx_start_int_ena1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_start_int_ena1:1; + /** slchost_slc1host_tx_start_int_ena1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_tx_start_int_ena1:1; + /** slchost_slc1_rx_udf_int_ena1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_udf_int_ena1:1; + /** slchost_slc1_tx_ovf_int_ena1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tx_ovf_int_ena1:1; + /** slchost_slc1_rx_pf_valid_int_ena1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_pf_valid_int_ena1:1; + /** slchost_slc1_ext_bit0_int_ena1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit0_int_ena1:1; + /** slchost_slc1_ext_bit1_int_ena1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit1_int_ena1:1; + /** slchost_slc1_ext_bit2_int_ena1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit2_int_ena1:1; + /** slchost_slc1_ext_bit3_int_ena1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit3_int_ena1:1; + /** slchost_slc1_wifi_rx_new_packet_int_ena1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_wifi_rx_new_packet_int_ena1:1; + /** slchost_slc1_host_rd_retry_int_ena1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_host_rd_retry_int_ena1:1; + /** slchost_slc1_bt_rx_new_packet_int_ena1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_bt_rx_new_packet_int_ena1:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_int_ena1_reg_t; + +/** Type of slc_host_date register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_date : R/W; bitpos: [31:0]; default: 554043136; + * *******Description*********** + */ + uint32_t slchost_slchost_date:32; + }; + uint32_t val; +} sdio_slc_host_date_reg_t; + +/** Type of slc_host_id register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_id : R/W; bitpos: [31:0]; default: 1536; + * *******Description*********** + */ + uint32_t slchost_slchost_id:32; + }; + uint32_t val; +} sdio_slc_host_id_reg_t; + +/** Type of slc_host_conf register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_frc_sdio11 : R/W; bitpos: [4:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_frc_sdio11:5; + /** slchost_frc_sdio20 : R/W; bitpos: [9:5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_frc_sdio20:5; + /** slchost_frc_neg_samp : R/W; bitpos: [14:10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_frc_neg_samp:5; + /** slchost_frc_pos_samp : R/W; bitpos: [19:15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_frc_pos_samp:5; + /** slchost_frc_quick_in : R/W; bitpos: [24:20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_frc_quick_in:5; + /** slchost_sdio20_int_delay : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_sdio20_int_delay:1; + /** slchost_sdio_pad_pullup : R/W; bitpos: [26]; default: 0; + * *******Description*********** + */ + uint32_t slchost_sdio_pad_pullup:1; + /** slchost_hspeed_con_en : R/W; bitpos: [27]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hspeed_con_en:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_host_conf_reg_t; + +/** Type of slc_host_inf_st register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_sdio20_mode : RO; bitpos: [4:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_sdio20_mode:5; + /** slchost_sdio_neg_samp : RO; bitpos: [9:5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_sdio_neg_samp:5; + /** slchost_sdio_quick_in : RO; bitpos: [14:10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_sdio_quick_in:5; + /** slchost_dll_on_sw : R/W; bitpos: [15]; default: 0; + * dll is controlled by software + */ + uint32_t slchost_dll_on_sw:1; + /** slchost_dll_on : R/W; bitpos: [16]; default: 0; + * Software dll on + */ + uint32_t slchost_dll_on:1; + /** slchost_clk_mode_sw : R/W; bitpos: [17]; default: 0; + * dll clock mode is controlled by software + */ + uint32_t slchost_clk_mode_sw:1; + /** slchost_clk_mode : R/W; bitpos: [19:18]; default: 0; + * Software set clock mode + */ + uint32_t slchost_clk_mode:2; + uint32_t reserved_20:12; + }; + uint32_t val; +} sdio_slc_host_inf_st_reg_t; + + +typedef struct { + uint32_t reserved_000[4]; + volatile sdio_slc_host_func2_0_reg_t slc_host_func2_0; + volatile sdio_slc_host_func2_1_reg_t slc_host_func2_1; + uint32_t reserved_018[2]; + volatile sdio_slc_host_func2_2_reg_t slc_host_func2_2; + uint32_t reserved_024[4]; + volatile sdio_slc_host_gpio_status0_reg_t slc_host_gpio_status0; + volatile sdio_slc_host_gpio_status1_reg_t slc_host_gpio_status1; + volatile sdio_slc_host_gpio_in0_reg_t slc_host_gpio_in0; + volatile sdio_slc_host_gpio_in1_reg_t slc_host_gpio_in1; + volatile sdio_slc_host_slc0host_token_rdata_reg_t slc_host_slc0host_token_rdata; + volatile sdio_slc_host_slc0_host_pf_reg_t slc_host_slc0_host_pf; + volatile sdio_slc_host_slc1_host_pf_reg_t slc_host_slc1_host_pf; + volatile sdio_slc_host_slc0host_int_raw_reg_t slc_host_slc0host_int_raw; + volatile sdio_slc_host_slc1host_int_raw_reg_t slc_host_slc1host_int_raw; + volatile sdio_slc_host_slc0host_int_st_reg_t slc_host_slc0host_int_st; + volatile sdio_slc_host_slc1host_int_st_reg_t slc_host_slc1host_int_st; + volatile sdio_slc_host_pkt_len_reg_t slc_host_pkt_len; + volatile sdio_slc_host_state_w0_reg_t slc_host_state_w0; + volatile sdio_slc_host_state_w1_reg_t slc_host_state_w1; + volatile sdio_slc_host_conf_w0_reg_t slc_host_conf_w0; + volatile sdio_slc_host_conf_w1_reg_t slc_host_conf_w1; + volatile sdio_slc_host_conf_w2_reg_t slc_host_conf_w2; + volatile sdio_slc_host_conf_w3_reg_t slc_host_conf_w3; + volatile sdio_slc_host_conf_w4_reg_t slc_host_conf_w4; + volatile sdio_slc_host_conf_w5_reg_t slc_host_conf_w5; + volatile sdio_slc_host_win_cmd_reg_t slc_host_win_cmd; + volatile sdio_slc_host_conf_w6_reg_t slc_host_conf_w6; + volatile sdio_slc_host_conf_w7_reg_t slc_host_conf_w7; + volatile sdio_slc_host_pkt_len0_reg_t slc_host_pkt_len0; + volatile sdio_slc_host_pkt_len1_reg_t slc_host_pkt_len1; + volatile sdio_slc_host_pkt_len2_reg_t slc_host_pkt_len2; + volatile sdio_slc_host_conf_w8_reg_t slc_host_conf_w8; + volatile sdio_slc_host_conf_w9_reg_t slc_host_conf_w9; + volatile sdio_slc_host_conf_w10_reg_t slc_host_conf_w10; + volatile sdio_slc_host_conf_w11_reg_t slc_host_conf_w11; + volatile sdio_slc_host_conf_w12_reg_t slc_host_conf_w12; + volatile sdio_slc_host_conf_w13_reg_t slc_host_conf_w13; + volatile sdio_slc_host_conf_w14_reg_t slc_host_conf_w14; + volatile sdio_slc_host_conf_w15_reg_t slc_host_conf_w15; + volatile sdio_slc_host_check_sum0_reg_t slc_host_check_sum0; + volatile sdio_slc_host_check_sum1_reg_t slc_host_check_sum1; + volatile sdio_slc_host_slc1host_token_rdata_reg_t slc_host_slc1host_token_rdata; + volatile sdio_slc_host_slc0host_token_wdata_reg_t slc_host_slc0host_token_wdata; + volatile sdio_slc_host_slc1host_token_wdata_reg_t slc_host_slc1host_token_wdata; + volatile sdio_slc_host_token_con_reg_t slc_host_token_con; + volatile sdio_slc_host_slc0host_int_clr_reg_t slc_host_slc0host_int_clr; + volatile sdio_slc_host_slc1host_int_clr_reg_t slc_host_slc1host_int_clr; + volatile sdio_slc_host_slc0host_func1_int_ena_reg_t slc_host_slc0host_func1_int_ena; + volatile sdio_slc_host_slc1host_func1_int_ena_reg_t slc_host_slc1host_func1_int_ena; + volatile sdio_slc_host_slc0host_func2_int_ena_reg_t slc_host_slc0host_func2_int_ena; + volatile sdio_slc_host_slc1host_func2_int_ena_reg_t slc_host_slc1host_func2_int_ena; + volatile sdio_slc_host_slc0host_int_ena_reg_t slc_host_slc0host_int_ena; + volatile sdio_slc_host_slc1host_int_ena_reg_t slc_host_slc1host_int_ena; + volatile sdio_slc_host_slc0host_rx_infor_reg_t slc_host_slc0host_rx_infor; + volatile sdio_slc_host_slc1host_rx_infor_reg_t slc_host_slc1host_rx_infor; + volatile sdio_slc_host_slc0host_len_wd_reg_t slc_host_slc0host_len_wd; + volatile sdio_slc_host_slc_apbwin_wdata_reg_t slc_host_slc_apbwin_wdata; + volatile sdio_slc_host_slc_apbwin_conf_reg_t slc_host_slc_apbwin_conf; + volatile sdio_slc_host_slc_apbwin_rdata_reg_t slc_host_slc_apbwin_rdata; + volatile sdio_slc_host_rdclr0_reg_t slc_host_rdclr0; + volatile sdio_slc_host_rdclr1_reg_t slc_host_rdclr1; + volatile sdio_slc_host_slc0host_int_ena1_reg_t slc_host_slc0host_int_ena1; + volatile sdio_slc_host_slc1host_int_ena1_reg_t slc_host_slc1host_int_ena1; + uint32_t reserved_11c[23]; + volatile sdio_slc_host_date_reg_t slc_host_date; + volatile sdio_slc_host_id_reg_t slc_host_id; + uint32_t reserved_180[28]; + volatile sdio_slc_host_conf_reg_t slc_host_conf; + volatile sdio_slc_host_inf_st_reg_t slc_host_inf_st; +} host_dev_t; + +extern host_dev_t HOST; + +#ifndef __cplusplus +_Static_assert(sizeof(host_dev_t) == 0x1f8, "Invalid size of host_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/register/soc/sdio_slc_reg.h b/components/soc/esp32c61/register/soc/sdio_slc_reg.h new file mode 100644 index 0000000000..ed573412c2 --- /dev/null +++ b/components/soc/esp32c61/register/soc/sdio_slc_reg.h @@ -0,0 +1,4382 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SDIO_SLC_CONF0_REG register + * Sdio slave DMA configuration register. + */ +#define SDIO_SLC_CONF0_REG (DR_REG_SLC_BASE + 0x0) +/** SDIO_SLC0_TX_RST : R/W; bitpos: [0]; default: 0; + * Set 1 to reset receiving fsm in dma channel0. + */ +#define SDIO_SLC0_TX_RST (BIT(0)) +#define SDIO_SLC0_TX_RST_M (SDIO_SLC0_TX_RST_V << SDIO_SLC0_TX_RST_S) +#define SDIO_SLC0_TX_RST_V 0x00000001U +#define SDIO_SLC0_TX_RST_S 0 +/** SDIO_SLC0_RX_RST : R/W; bitpos: [1]; default: 0; + * Set 1 to reset transmitting fsm in dma channel0. + */ +#define SDIO_SLC0_RX_RST (BIT(1)) +#define SDIO_SLC0_RX_RST_M (SDIO_SLC0_RX_RST_V << SDIO_SLC0_RX_RST_S) +#define SDIO_SLC0_RX_RST_V 0x00000001U +#define SDIO_SLC0_RX_RST_S 1 +/** SDIO_SLC_AHBM_FIFO_RST : R/W; bitpos: [2]; default: 0; + * reset the command fifo of AHB bus of sdio slave + */ +#define SDIO_SLC_AHBM_FIFO_RST (BIT(2)) +#define SDIO_SLC_AHBM_FIFO_RST_M (SDIO_SLC_AHBM_FIFO_RST_V << SDIO_SLC_AHBM_FIFO_RST_S) +#define SDIO_SLC_AHBM_FIFO_RST_V 0x00000001U +#define SDIO_SLC_AHBM_FIFO_RST_S 2 +/** SDIO_SLC_AHBM_RST : R/W; bitpos: [3]; default: 0; + * reset the AHB bus of sdio slave + */ +#define SDIO_SLC_AHBM_RST (BIT(3)) +#define SDIO_SLC_AHBM_RST_M (SDIO_SLC_AHBM_RST_V << SDIO_SLC_AHBM_RST_S) +#define SDIO_SLC_AHBM_RST_V 0x00000001U +#define SDIO_SLC_AHBM_RST_S 3 +/** SDIO_SLC0_TX_LOOP_TEST : R/W; bitpos: [4]; default: 0; + * Loop around when the slave buffer finishes receiving packets. When set to 1, + * hardware will not change the owner bit in the linked list. + */ +#define SDIO_SLC0_TX_LOOP_TEST (BIT(4)) +#define SDIO_SLC0_TX_LOOP_TEST_M (SDIO_SLC0_TX_LOOP_TEST_V << SDIO_SLC0_TX_LOOP_TEST_S) +#define SDIO_SLC0_TX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC0_TX_LOOP_TEST_S 4 +/** SDIO_SLC0_RX_LOOP_TEST : R/W; bitpos: [5]; default: 0; + * Loop around when the slave buffer finishes sending packets. When set to 1, hardware + * will not change the owner bit in the linked list. + */ +#define SDIO_SLC0_RX_LOOP_TEST (BIT(5)) +#define SDIO_SLC0_RX_LOOP_TEST_M (SDIO_SLC0_RX_LOOP_TEST_V << SDIO_SLC0_RX_LOOP_TEST_S) +#define SDIO_SLC0_RX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC0_RX_LOOP_TEST_S 5 +/** SDIO_SLC0_RX_AUTO_WRBACK : R/W; bitpos: [6]; default: 0; + * Set 1 to enable change the owner bit of rx link descriptor + */ +#define SDIO_SLC0_RX_AUTO_WRBACK (BIT(6)) +#define SDIO_SLC0_RX_AUTO_WRBACK_M (SDIO_SLC0_RX_AUTO_WRBACK_V << SDIO_SLC0_RX_AUTO_WRBACK_S) +#define SDIO_SLC0_RX_AUTO_WRBACK_V 0x00000001U +#define SDIO_SLC0_RX_AUTO_WRBACK_S 6 +/** SDIO_SLC0_RX_NO_RESTART_CLR : R/W; bitpos: [7]; default: 0; + * Set this bit to disable the function that when slave starts to send data to host, + * the slc0_bt_rx_new_packet_int_raw or slc0_host_rd_retry_int_raw will be + * automatically cleared. + */ +#define SDIO_SLC0_RX_NO_RESTART_CLR (BIT(7)) +#define SDIO_SLC0_RX_NO_RESTART_CLR_M (SDIO_SLC0_RX_NO_RESTART_CLR_V << SDIO_SLC0_RX_NO_RESTART_CLR_S) +#define SDIO_SLC0_RX_NO_RESTART_CLR_V 0x00000001U +#define SDIO_SLC0_RX_NO_RESTART_CLR_S 7 +/** SDIO_SLC0_RXDSCR_BURST_EN : R/W; bitpos: [8]; default: 1; + * 0- AHB burst type is single when slave read rx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read rx-descriptor from memory + * through slc0 + */ +#define SDIO_SLC0_RXDSCR_BURST_EN (BIT(8)) +#define SDIO_SLC0_RXDSCR_BURST_EN_M (SDIO_SLC0_RXDSCR_BURST_EN_V << SDIO_SLC0_RXDSCR_BURST_EN_S) +#define SDIO_SLC0_RXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC0_RXDSCR_BURST_EN_S 8 +/** SDIO_SLC0_RXDATA_BURST_EN : R/W; bitpos: [9]; default: 1; + * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type + * is not single when slave receives data from memory + */ +#define SDIO_SLC0_RXDATA_BURST_EN (BIT(9)) +#define SDIO_SLC0_RXDATA_BURST_EN_M (SDIO_SLC0_RXDATA_BURST_EN_V << SDIO_SLC0_RXDATA_BURST_EN_S) +#define SDIO_SLC0_RXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC0_RXDATA_BURST_EN_S 9 +/** SDIO_SLC0_RXLINK_AUTO_RET : R/W; bitpos: [10]; default: 1; + * enable the function that when host reading packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC0_RXLINK_AUTO_RET (BIT(10)) +#define SDIO_SLC0_RXLINK_AUTO_RET_M (SDIO_SLC0_RXLINK_AUTO_RET_V << SDIO_SLC0_RXLINK_AUTO_RET_S) +#define SDIO_SLC0_RXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC0_RXLINK_AUTO_RET_S 10 +/** SDIO_SLC0_TXLINK_AUTO_RET : R/W; bitpos: [11]; default: 1; + * enable the function that when host sending packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC0_TXLINK_AUTO_RET (BIT(11)) +#define SDIO_SLC0_TXLINK_AUTO_RET_M (SDIO_SLC0_TXLINK_AUTO_RET_V << SDIO_SLC0_TXLINK_AUTO_RET_S) +#define SDIO_SLC0_TXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC0_TXLINK_AUTO_RET_S 11 +/** SDIO_SLC0_TXDSCR_BURST_EN : R/W; bitpos: [12]; default: 1; + * 0- AHB burst type is single when slave read tx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read tx-descriptor from memory + * through slc0 + */ +#define SDIO_SLC0_TXDSCR_BURST_EN (BIT(12)) +#define SDIO_SLC0_TXDSCR_BURST_EN_M (SDIO_SLC0_TXDSCR_BURST_EN_V << SDIO_SLC0_TXDSCR_BURST_EN_S) +#define SDIO_SLC0_TXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC0_TXDSCR_BURST_EN_S 12 +/** SDIO_SLC0_TXDATA_BURST_EN : R/W; bitpos: [13]; default: 1; + * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not + * single when slave send data to memory + */ +#define SDIO_SLC0_TXDATA_BURST_EN (BIT(13)) +#define SDIO_SLC0_TXDATA_BURST_EN_M (SDIO_SLC0_TXDATA_BURST_EN_V << SDIO_SLC0_TXDATA_BURST_EN_S) +#define SDIO_SLC0_TXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC0_TXDATA_BURST_EN_S 13 +/** SDIO_SLC0_TOKEN_AUTO_CLR : R/W; bitpos: [14]; default: 1; + * auto clear slc0_token1 enable + */ +#define SDIO_SLC0_TOKEN_AUTO_CLR (BIT(14)) +#define SDIO_SLC0_TOKEN_AUTO_CLR_M (SDIO_SLC0_TOKEN_AUTO_CLR_V << SDIO_SLC0_TOKEN_AUTO_CLR_S) +#define SDIO_SLC0_TOKEN_AUTO_CLR_V 0x00000001U +#define SDIO_SLC0_TOKEN_AUTO_CLR_S 14 +/** SDIO_SLC0_TOKEN_SEL : R/W; bitpos: [15]; default: 1; + * 0: choose to save slc0_token0's value, 1: choose to save the accumulative value of + * slc0_token1 + */ +#define SDIO_SLC0_TOKEN_SEL (BIT(15)) +#define SDIO_SLC0_TOKEN_SEL_M (SDIO_SLC0_TOKEN_SEL_V << SDIO_SLC0_TOKEN_SEL_S) +#define SDIO_SLC0_TOKEN_SEL_V 0x00000001U +#define SDIO_SLC0_TOKEN_SEL_S 15 +/** SDIO_SLC1_TX_RST : R/W; bitpos: [16]; default: 0; + * Set 1 to reset receiving fsm in dma slc0. + */ +#define SDIO_SLC1_TX_RST (BIT(16)) +#define SDIO_SLC1_TX_RST_M (SDIO_SLC1_TX_RST_V << SDIO_SLC1_TX_RST_S) +#define SDIO_SLC1_TX_RST_V 0x00000001U +#define SDIO_SLC1_TX_RST_S 16 +/** SDIO_SLC1_RX_RST : R/W; bitpos: [17]; default: 0; + * Set 1 to reset sending fsm in dma slc0. + */ +#define SDIO_SLC1_RX_RST (BIT(17)) +#define SDIO_SLC1_RX_RST_M (SDIO_SLC1_RX_RST_V << SDIO_SLC1_RX_RST_S) +#define SDIO_SLC1_RX_RST_V 0x00000001U +#define SDIO_SLC1_RX_RST_S 17 +/** SDIO_SLC0_WR_RETRY_MASK_EN : R/W; bitpos: [18]; default: 1; + * Set this bit to generate an interrupt when host sending retry finishes and prevent + * host still retrying after one successful retry through dma channel0 + */ +#define SDIO_SLC0_WR_RETRY_MASK_EN (BIT(18)) +#define SDIO_SLC0_WR_RETRY_MASK_EN_M (SDIO_SLC0_WR_RETRY_MASK_EN_V << SDIO_SLC0_WR_RETRY_MASK_EN_S) +#define SDIO_SLC0_WR_RETRY_MASK_EN_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_MASK_EN_S 18 +/** SDIO_SLC1_WR_RETRY_MASK_EN : R/W; bitpos: [19]; default: 1; + * Set this bit to generate an interrupt when host sending retry finishes and prevent + * host still retrying after one successful retry through dma channel0 + */ +#define SDIO_SLC1_WR_RETRY_MASK_EN (BIT(19)) +#define SDIO_SLC1_WR_RETRY_MASK_EN_M (SDIO_SLC1_WR_RETRY_MASK_EN_V << SDIO_SLC1_WR_RETRY_MASK_EN_S) +#define SDIO_SLC1_WR_RETRY_MASK_EN_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_MASK_EN_S 19 +/** SDIO_SLC1_TX_LOOP_TEST : R/W; bitpos: [20]; default: 1; + * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. + */ +#define SDIO_SLC1_TX_LOOP_TEST (BIT(20)) +#define SDIO_SLC1_TX_LOOP_TEST_M (SDIO_SLC1_TX_LOOP_TEST_V << SDIO_SLC1_TX_LOOP_TEST_S) +#define SDIO_SLC1_TX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC1_TX_LOOP_TEST_S 20 +/** SDIO_SLC1_RX_LOOP_TEST : R/W; bitpos: [21]; default: 1; + * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. + */ +#define SDIO_SLC1_RX_LOOP_TEST (BIT(21)) +#define SDIO_SLC1_RX_LOOP_TEST_M (SDIO_SLC1_RX_LOOP_TEST_V << SDIO_SLC1_RX_LOOP_TEST_S) +#define SDIO_SLC1_RX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC1_RX_LOOP_TEST_S 21 +/** SDIO_SLC1_RX_AUTO_WRBACK : R/W; bitpos: [22]; default: 0; + * Set 1 to enable change the owner bit of the transmitting buffer's linked list when + * transmitting data. + */ +#define SDIO_SLC1_RX_AUTO_WRBACK (BIT(22)) +#define SDIO_SLC1_RX_AUTO_WRBACK_M (SDIO_SLC1_RX_AUTO_WRBACK_V << SDIO_SLC1_RX_AUTO_WRBACK_S) +#define SDIO_SLC1_RX_AUTO_WRBACK_V 0x00000001U +#define SDIO_SLC1_RX_AUTO_WRBACK_S 22 +/** SDIO_SLC1_RX_NO_RESTART_CLR : R/W; bitpos: [23]; default: 0; + * Set this bit to disable the function that when slave starts to send data to host, + * the slc1_bt_rx_new_packet_int_raw, slc1_wifi_rx_new_packet_int_raw or + * slc1_host_rd_retry_int_raw will be automatically cleared. + */ +#define SDIO_SLC1_RX_NO_RESTART_CLR (BIT(23)) +#define SDIO_SLC1_RX_NO_RESTART_CLR_M (SDIO_SLC1_RX_NO_RESTART_CLR_V << SDIO_SLC1_RX_NO_RESTART_CLR_S) +#define SDIO_SLC1_RX_NO_RESTART_CLR_V 0x00000001U +#define SDIO_SLC1_RX_NO_RESTART_CLR_S 23 +/** SDIO_SLC1_RXDSCR_BURST_EN : R/W; bitpos: [24]; default: 1; + * 0- AHB burst type is single when dma channel1 fetches linked list for sending + * data,1-AHB burst type is not single when dma channel1 fetches linked list for + * sending data + */ +#define SDIO_SLC1_RXDSCR_BURST_EN (BIT(24)) +#define SDIO_SLC1_RXDSCR_BURST_EN_M (SDIO_SLC1_RXDSCR_BURST_EN_V << SDIO_SLC1_RXDSCR_BURST_EN_S) +#define SDIO_SLC1_RXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC1_RXDSCR_BURST_EN_S 24 +/** SDIO_SLC1_RXDATA_BURST_EN : R/W; bitpos: [25]; default: 1; + * 0- AHB burst type is single when slave receives data through dma channel1,1-AHB + * burst type is not single when slave receives data through dma channel1 + */ +#define SDIO_SLC1_RXDATA_BURST_EN (BIT(25)) +#define SDIO_SLC1_RXDATA_BURST_EN_M (SDIO_SLC1_RXDATA_BURST_EN_V << SDIO_SLC1_RXDATA_BURST_EN_S) +#define SDIO_SLC1_RXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC1_RXDATA_BURST_EN_S 25 +/** SDIO_SLC1_RXLINK_AUTO_RET : R/W; bitpos: [26]; default: 1; + * enable the function that when host reading packet retries, dma channel1 will + * automatically jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC1_RXLINK_AUTO_RET (BIT(26)) +#define SDIO_SLC1_RXLINK_AUTO_RET_M (SDIO_SLC1_RXLINK_AUTO_RET_V << SDIO_SLC1_RXLINK_AUTO_RET_S) +#define SDIO_SLC1_RXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC1_RXLINK_AUTO_RET_S 26 +/** SDIO_SLC1_TXLINK_AUTO_RET : R/W; bitpos: [27]; default: 1; + * enable the function that when host sending packet retries, dma channel1 will + * automatically jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC1_TXLINK_AUTO_RET (BIT(27)) +#define SDIO_SLC1_TXLINK_AUTO_RET_M (SDIO_SLC1_TXLINK_AUTO_RET_V << SDIO_SLC1_TXLINK_AUTO_RET_S) +#define SDIO_SLC1_TXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC1_TXLINK_AUTO_RET_S 27 +/** SDIO_SLC1_TXDSCR_BURST_EN : R/W; bitpos: [28]; default: 1; + * 0- AHB burst type is single when dma channel1 fetches linked list for receiving + * data, 1-AHB burst type is not single when dma channel1 fetches linked list for + * receiving data + */ +#define SDIO_SLC1_TXDSCR_BURST_EN (BIT(28)) +#define SDIO_SLC1_TXDSCR_BURST_EN_M (SDIO_SLC1_TXDSCR_BURST_EN_V << SDIO_SLC1_TXDSCR_BURST_EN_S) +#define SDIO_SLC1_TXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC1_TXDSCR_BURST_EN_S 28 +/** SDIO_SLC1_TXDATA_BURST_EN : R/W; bitpos: [29]; default: 1; + * 0- AHB burst type is single when slave sends data to memory through dma channel1, + * 1-AHB burst type is not single when slave sends data to memory through dma channel1. + */ +#define SDIO_SLC1_TXDATA_BURST_EN (BIT(29)) +#define SDIO_SLC1_TXDATA_BURST_EN_M (SDIO_SLC1_TXDATA_BURST_EN_V << SDIO_SLC1_TXDATA_BURST_EN_S) +#define SDIO_SLC1_TXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC1_TXDATA_BURST_EN_S 29 +/** SDIO_SLC1_TOKEN_SEL : R/W; bitpos: [31]; default: 1; + * reserved + */ +#define SDIO_SLC1_TOKEN_SEL (BIT(31)) +#define SDIO_SLC1_TOKEN_SEL_M (SDIO_SLC1_TOKEN_SEL_V << SDIO_SLC1_TOKEN_SEL_S) +#define SDIO_SLC1_TOKEN_SEL_V 0x00000001U +#define SDIO_SLC1_TOKEN_SEL_S 31 + +/** SDIO_SLC_SLC0INT_RAW_REG register + * Sdio slave DMA channel0 raw interrupt status register. + */ +#define SDIO_SLC_SLC0INT_RAW_REG (DR_REG_SLC_BASE + 0x4) +/** SDIO_SLC_FRHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit 0 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT0_INT_RAW (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_RAW_M (SDIO_SLC_FRHOST_BIT0_INT_RAW_V << SDIO_SLC_FRHOST_BIT0_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT0_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_RAW_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit 1 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT1_INT_RAW (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_RAW_M (SDIO_SLC_FRHOST_BIT1_INT_RAW_V << SDIO_SLC_FRHOST_BIT1_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT1_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_RAW_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit 2 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT2_INT_RAW (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_RAW_M (SDIO_SLC_FRHOST_BIT2_INT_RAW_V << SDIO_SLC_FRHOST_BIT2_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT2_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_RAW_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit 3 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT3_INT_RAW (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_RAW_M (SDIO_SLC_FRHOST_BIT3_INT_RAW_V << SDIO_SLC_FRHOST_BIT3_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT3_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_RAW_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit 4 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT4_INT_RAW (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_RAW_M (SDIO_SLC_FRHOST_BIT4_INT_RAW_V << SDIO_SLC_FRHOST_BIT4_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT4_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_RAW_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit 5 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT5_INT_RAW (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_RAW_M (SDIO_SLC_FRHOST_BIT5_INT_RAW_V << SDIO_SLC_FRHOST_BIT5_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT5_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_RAW_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit 6 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT6_INT_RAW (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_RAW_M (SDIO_SLC_FRHOST_BIT6_INT_RAW_V << SDIO_SLC_FRHOST_BIT6_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT6_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_RAW_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit 7 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT7_INT_RAW (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_RAW_M (SDIO_SLC_FRHOST_BIT7_INT_RAW_V << SDIO_SLC_FRHOST_BIT7_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT7_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_RAW_S 7 +/** SDIO_SLC0_RX_START_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit of registering dma channel0 sending initialization + */ +#define SDIO_SLC0_RX_START_INT_RAW (BIT(8)) +#define SDIO_SLC0_RX_START_INT_RAW_M (SDIO_SLC0_RX_START_INT_RAW_V << SDIO_SLC0_RX_START_INT_RAW_S) +#define SDIO_SLC0_RX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_RAW_S 8 +/** SDIO_SLC0_TX_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit of registering dma channel0 receiving initialization + */ +#define SDIO_SLC0_TX_START_INT_RAW (BIT(9)) +#define SDIO_SLC0_TX_START_INT_RAW_M (SDIO_SLC0_TX_START_INT_RAW_V << SDIO_SLC0_TX_START_INT_RAW_S) +#define SDIO_SLC0_TX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_RAW_S 9 +/** SDIO_SLC0_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit of dma channel0 sending buffer underflow. + */ +#define SDIO_SLC0_RX_UDF_INT_RAW (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_RAW_M (SDIO_SLC0_RX_UDF_INT_RAW_V << SDIO_SLC0_RX_UDF_INT_RAW_S) +#define SDIO_SLC0_RX_UDF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_RAW_S 10 +/** SDIO_SLC0_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit of dma channel0 receiving buffer overflow. + */ +#define SDIO_SLC0_TX_OVF_INT_RAW (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_RAW_M (SDIO_SLC0_TX_OVF_INT_RAW_V << SDIO_SLC0_TX_OVF_INT_RAW_S) +#define SDIO_SLC0_TX_OVF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_RAW_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit for the value of slc0_token0 becoming to zero. + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_M (SDIO_SLC0_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC0_TOKEN0_1TO0_INT_RAW_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit for the value of slc0_token1 becoming to zero. + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_M (SDIO_SLC0_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC0_TOKEN1_1TO0_INT_RAW_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_S 13 +/** SDIO_SLC0_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit of dma channel0 finishing receiving data to one single buffer. + */ +#define SDIO_SLC0_TX_DONE_INT_RAW (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_RAW_M (SDIO_SLC0_TX_DONE_INT_RAW_V << SDIO_SLC0_TX_DONE_INT_RAW_S) +#define SDIO_SLC0_TX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_RAW_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit of dma channel0 finishing receiving data + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_M (SDIO_SLC0_TX_SUC_EOF_INT_RAW_V << SDIO_SLC0_TX_SUC_EOF_INT_RAW_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_S 15 +/** SDIO_SLC0_RX_DONE_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt bit of dma channel0 finishing sending data from one single buffer + */ +#define SDIO_SLC0_RX_DONE_INT_RAW (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_RAW_M (SDIO_SLC0_RX_DONE_INT_RAW_V << SDIO_SLC0_RX_DONE_INT_RAW_S) +#define SDIO_SLC0_RX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_RAW_S 16 +/** SDIO_SLC0_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt bit of dma channel0 finishing sending data + */ +#define SDIO_SLC0_RX_EOF_INT_RAW (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_RAW_M (SDIO_SLC0_RX_EOF_INT_RAW_V << SDIO_SLC0_RX_EOF_INT_RAW_S) +#define SDIO_SLC0_RX_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_RAW_S 17 +/** SDIO_SLC0_TOHOST_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The raw interrupt bit for slave generating interrupt to host. + */ +#define SDIO_SLC0_TOHOST_INT_RAW (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_RAW_M (SDIO_SLC0_TOHOST_INT_RAW_V << SDIO_SLC0_TOHOST_INT_RAW_S) +#define SDIO_SLC0_TOHOST_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_RAW_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt bit of dma channel0 receiving descriptor error. + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_M (SDIO_SLC0_TX_DSCR_ERR_INT_RAW_V << SDIO_SLC0_TX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt bit of dma channel0 sending descriptor error. + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_M (SDIO_SLC0_RX_DSCR_ERR_INT_RAW_V << SDIO_SLC0_RX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * The raw interrupt bit of not enough buffer for slave receiving data from host + * through dma channel0. + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * The raw interrupt bit for host to acknowledge retrying receiving data from slave + * successfully through dma channel0. + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_M (SDIO_SLC0_HOST_RD_ACK_INT_RAW_V << SDIO_SLC0_HOST_RD_ACK_INT_RAW_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * The raw interrupt bit of host finishing retrying sending data to slave through dma + * channel0. + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_M (SDIO_SLC0_WR_RETRY_DONE_INT_RAW_V << SDIO_SLC0_WR_RETRY_DONE_INT_RAW_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * The raw interrupt bit of data error during host sending data to slave through dma + * channel0. + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_M (SDIO_SLC0_TX_ERR_EOF_INT_RAW_V << SDIO_SLC0_TX_ERR_EOF_INT_RAW_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_S 24 +/** SDIO_CMD_DTC_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * The raw interrupt bit for sdio slave to detect command from host. + */ +#define SDIO_CMD_DTC_INT_RAW (BIT(25)) +#define SDIO_CMD_DTC_INT_RAW_M (SDIO_CMD_DTC_INT_RAW_V << SDIO_CMD_DTC_INT_RAW_S) +#define SDIO_CMD_DTC_INT_RAW_V 0x00000001U +#define SDIO_CMD_DTC_INT_RAW_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * The raw interrupt for the linked list used reaches the number of + * slc0_rx_dscr_rec_lim when in stitch mode, or for every sending data transfer done. + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_M (SDIO_SLC0_RX_QUICK_EOF_INT_RAW_V << SDIO_SLC0_RX_QUICK_EOF_INT_RAW_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * The raw interrupt bit for the eof bit error of slave receiving data through dma + * channel0. + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_S 27 +/** SDIO_HDA_RECV_DONE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * The raw interrupt bit for slave finishes receiving one cmd53 function's all block + * data. + */ +#define SDIO_HDA_RECV_DONE_INT_RAW (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_RAW_M (SDIO_HDA_RECV_DONE_INT_RAW_V << SDIO_HDA_RECV_DONE_INT_RAW_S) +#define SDIO_HDA_RECV_DONE_INT_RAW_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_RAW_S 28 + +/** SDIO_SLC_SLC0INT_ST_REG register + * Sdio slave DMA channel0 masked interrupt status register. + */ +#define SDIO_SLC_SLC0INT_ST_REG (DR_REG_SLC_BASE + 0x8) +/** SDIO_SLC_FRHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT0_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ST (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ST_M (SDIO_SLC_FRHOST_BIT0_INT_ST_V << SDIO_SLC_FRHOST_BIT0_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ST_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT1_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ST (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ST_M (SDIO_SLC_FRHOST_BIT1_INT_ST_V << SDIO_SLC_FRHOST_BIT1_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ST_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT2_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ST (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ST_M (SDIO_SLC_FRHOST_BIT2_INT_ST_V << SDIO_SLC_FRHOST_BIT2_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ST_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT3_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ST (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ST_M (SDIO_SLC_FRHOST_BIT3_INT_ST_V << SDIO_SLC_FRHOST_BIT3_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ST_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT4_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ST (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ST_M (SDIO_SLC_FRHOST_BIT4_INT_ST_V << SDIO_SLC_FRHOST_BIT4_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ST_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT5_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ST (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ST_M (SDIO_SLC_FRHOST_BIT5_INT_ST_V << SDIO_SLC_FRHOST_BIT5_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ST_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT6_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ST (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ST_M (SDIO_SLC_FRHOST_BIT6_INT_ST_V << SDIO_SLC_FRHOST_BIT6_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ST_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT7_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ST (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ST_M (SDIO_SLC_FRHOST_BIT7_INT_ST_V << SDIO_SLC_FRHOST_BIT7_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ST_S 7 +/** SDIO_SLC0_RX_START_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for SLC0_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_RX_START_INT_ST (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ST_M (SDIO_SLC0_RX_START_INT_ST_V << SDIO_SLC0_RX_START_INT_ST_S) +#define SDIO_SLC0_RX_START_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ST_S 8 +/** SDIO_SLC0_TX_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for SLC0_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_START_INT_ST (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ST_M (SDIO_SLC0_TX_START_INT_ST_V << SDIO_SLC0_TX_START_INT_ST_S) +#define SDIO_SLC0_TX_START_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ST_S 9 +/** SDIO_SLC0_RX_UDF_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for SLC0_RX_UDF_INT interrupt. + */ +#define SDIO_SLC0_RX_UDF_INT_ST (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ST_M (SDIO_SLC0_RX_UDF_INT_ST_V << SDIO_SLC0_RX_UDF_INT_ST_S) +#define SDIO_SLC0_RX_UDF_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ST_S 10 +/** SDIO_SLC0_TX_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for SLC0_TX_OVF_INT interrupt. + */ +#define SDIO_SLC0_TX_OVF_INT_ST (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ST_M (SDIO_SLC0_TX_OVF_INT_ST_V << SDIO_SLC0_TX_OVF_INT_ST_S) +#define SDIO_SLC0_TX_OVF_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ST_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for SLC0_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_M (SDIO_SLC0_TOKEN0_1TO0_INT_ST_V << SDIO_SLC0_TOKEN0_1TO0_INT_ST_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for SLC0_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_M (SDIO_SLC0_TOKEN1_1TO0_INT_ST_V << SDIO_SLC0_TOKEN1_1TO0_INT_ST_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_S 13 +/** SDIO_SLC0_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for SLC0_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_DONE_INT_ST (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ST_M (SDIO_SLC0_TX_DONE_INT_ST_V << SDIO_SLC0_TX_DONE_INT_ST_S) +#define SDIO_SLC0_TX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ST_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for SLC0_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ST (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST_M (SDIO_SLC0_TX_SUC_EOF_INT_ST_V << SDIO_SLC0_TX_SUC_EOF_INT_ST_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ST_S 15 +/** SDIO_SLC0_RX_DONE_INT_ST : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for SLC0_RX_DONE_INT interrupt. + */ +#define SDIO_SLC0_RX_DONE_INT_ST (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ST_M (SDIO_SLC0_RX_DONE_INT_ST_V << SDIO_SLC0_RX_DONE_INT_ST_S) +#define SDIO_SLC0_RX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ST_S 16 +/** SDIO_SLC0_RX_EOF_INT_ST : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for SLC0_RX_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_EOF_INT_ST (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ST_M (SDIO_SLC0_RX_EOF_INT_ST_V << SDIO_SLC0_RX_EOF_INT_ST_S) +#define SDIO_SLC0_RX_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ST_S 17 +/** SDIO_SLC0_TOHOST_INT_ST : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for SLC0_TOHOST_INT interrupt. + */ +#define SDIO_SLC0_TOHOST_INT_ST (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ST_M (SDIO_SLC0_TOHOST_INT_ST_V << SDIO_SLC0_TOHOST_INT_ST_S) +#define SDIO_SLC0_TOHOST_INT_ST_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ST_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ST : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit for SLC0_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_M (SDIO_SLC0_TX_DSCR_ERR_INT_ST_V << SDIO_SLC0_TX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ST : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit for SLC0_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_M (SDIO_SLC0_RX_DSCR_ERR_INT_ST_V << SDIO_SLC0_RX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ST : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ST : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit for SLC0_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ST (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST_M (SDIO_SLC0_HOST_RD_ACK_INT_ST_V << SDIO_SLC0_HOST_RD_ACK_INT_ST_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ST_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ST : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit for SLC0_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_M (SDIO_SLC0_WR_RETRY_DONE_INT_ST_V << SDIO_SLC0_WR_RETRY_DONE_INT_ST_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ST : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit for SLC0_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ST (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST_M (SDIO_SLC0_TX_ERR_EOF_INT_ST_V << SDIO_SLC0_TX_ERR_EOF_INT_ST_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ST_S 24 +/** SDIO_CMD_DTC_INT_ST : RO; bitpos: [25]; default: 0; + * The masked interrupt status bit for CMD_DTC_INT interrupt. + */ +#define SDIO_CMD_DTC_INT_ST (BIT(25)) +#define SDIO_CMD_DTC_INT_ST_M (SDIO_CMD_DTC_INT_ST_V << SDIO_CMD_DTC_INT_ST_S) +#define SDIO_CMD_DTC_INT_ST_V 0x00000001U +#define SDIO_CMD_DTC_INT_ST_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ST : RO; bitpos: [26]; default: 0; + * The masked interrupt status bit for SLC0_RX_QUICK_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_M (SDIO_SLC0_RX_QUICK_EOF_INT_ST_V << SDIO_SLC0_RX_QUICK_EOF_INT_ST_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST : RO; bitpos: [27]; default: 0; + * The masked interrupt status bit for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_S 27 +/** SDIO_HDA_RECV_DONE_INT_ST : RO; bitpos: [28]; default: 0; + * The masked interrupt status bit for HDA_RECV_DONE_INT interrupt. + */ +#define SDIO_HDA_RECV_DONE_INT_ST (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ST_M (SDIO_HDA_RECV_DONE_INT_ST_V << SDIO_HDA_RECV_DONE_INT_ST_S) +#define SDIO_HDA_RECV_DONE_INT_ST_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ST_S 28 + +/** SDIO_SLC_SLC0INT_ENA_REG register + * Sdio slave DMA channel0 interrupt enable register. + */ +#define SDIO_SLC_SLC0INT_ENA_REG (DR_REG_SLC_BASE + 0xc) +/** SDIO_SLC_FRHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT0_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA_M (SDIO_SLC_FRHOST_BIT0_INT_ENA_V << SDIO_SLC_FRHOST_BIT0_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT1_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA_M (SDIO_SLC_FRHOST_BIT1_INT_ENA_V << SDIO_SLC_FRHOST_BIT1_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT2_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA_M (SDIO_SLC_FRHOST_BIT2_INT_ENA_V << SDIO_SLC_FRHOST_BIT2_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT3_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA_M (SDIO_SLC_FRHOST_BIT3_INT_ENA_V << SDIO_SLC_FRHOST_BIT3_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT4_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA_M (SDIO_SLC_FRHOST_BIT4_INT_ENA_V << SDIO_SLC_FRHOST_BIT4_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT5_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA_M (SDIO_SLC_FRHOST_BIT5_INT_ENA_V << SDIO_SLC_FRHOST_BIT5_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT6_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA_M (SDIO_SLC_FRHOST_BIT6_INT_ENA_V << SDIO_SLC_FRHOST_BIT6_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT7_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA_M (SDIO_SLC_FRHOST_BIT7_INT_ENA_V << SDIO_SLC_FRHOST_BIT7_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLC0_RX_START_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for SLC0_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_RX_START_INT_ENA (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ENA_M (SDIO_SLC0_RX_START_INT_ENA_V << SDIO_SLC0_RX_START_INT_ENA_S) +#define SDIO_SLC0_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ENA_S 8 +/** SDIO_SLC0_TX_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for SLC0_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_START_INT_ENA (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ENA_M (SDIO_SLC0_TX_START_INT_ENA_V << SDIO_SLC0_TX_START_INT_ENA_S) +#define SDIO_SLC0_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ENA_S 9 +/** SDIO_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for SLC0_RX_UDF_INT interrupt. + */ +#define SDIO_SLC0_RX_UDF_INT_ENA (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ENA_M (SDIO_SLC0_RX_UDF_INT_ENA_V << SDIO_SLC0_RX_UDF_INT_ENA_S) +#define SDIO_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ENA_S 10 +/** SDIO_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for SLC0_TX_OVF_INT interrupt. + */ +#define SDIO_SLC0_TX_OVF_INT_ENA (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ENA_M (SDIO_SLC0_TX_OVF_INT_ENA_V << SDIO_SLC0_TX_OVF_INT_ENA_S) +#define SDIO_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ENA_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for SLC0_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_M (SDIO_SLC0_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for SLC0_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_M (SDIO_SLC0_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_S 13 +/** SDIO_SLC0_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for SLC0_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_DONE_INT_ENA (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ENA_M (SDIO_SLC0_TX_DONE_INT_ENA_V << SDIO_SLC0_TX_DONE_INT_ENA_S) +#define SDIO_SLC0_TX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ENA_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for SLC0_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_M (SDIO_SLC0_TX_SUC_EOF_INT_ENA_V << SDIO_SLC0_TX_SUC_EOF_INT_ENA_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_S 15 +/** SDIO_SLC0_RX_DONE_INT_ENA : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for SLC0_RX_DONE_INT interrupt. + */ +#define SDIO_SLC0_RX_DONE_INT_ENA (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ENA_M (SDIO_SLC0_RX_DONE_INT_ENA_V << SDIO_SLC0_RX_DONE_INT_ENA_S) +#define SDIO_SLC0_RX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ENA_S 16 +/** SDIO_SLC0_RX_EOF_INT_ENA : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for SLC0_RX_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_EOF_INT_ENA (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ENA_M (SDIO_SLC0_RX_EOF_INT_ENA_V << SDIO_SLC0_RX_EOF_INT_ENA_S) +#define SDIO_SLC0_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ENA_S 17 +/** SDIO_SLC0_TOHOST_INT_ENA : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for SLC0_TOHOST_INT interrupt. + */ +#define SDIO_SLC0_TOHOST_INT_ENA (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ENA_M (SDIO_SLC0_TOHOST_INT_ENA_V << SDIO_SLC0_TOHOST_INT_ENA_S) +#define SDIO_SLC0_TOHOST_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ENA_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ENA : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for SLC0_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_M (SDIO_SLC0_TX_DSCR_ERR_INT_ENA_V << SDIO_SLC0_TX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ENA : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit for SLC0_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_M (SDIO_SLC0_RX_DSCR_ERR_INT_ENA_V << SDIO_SLC0_RX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ENA : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit for SLC0_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_M (SDIO_SLC0_HOST_RD_ACK_INT_ENA_V << SDIO_SLC0_HOST_RD_ACK_INT_ENA_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ENA : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit for SLC0_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_M (SDIO_SLC0_WR_RETRY_DONE_INT_ENA_V << SDIO_SLC0_WR_RETRY_DONE_INT_ENA_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ENA : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit for SLC0_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_M (SDIO_SLC0_TX_ERR_EOF_INT_ENA_V << SDIO_SLC0_TX_ERR_EOF_INT_ENA_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_S 24 +/** SDIO_CMD_DTC_INT_ENA : R/W; bitpos: [25]; default: 0; + * The interrupt enable bit for CMD_DTC_INT interrupt. + */ +#define SDIO_CMD_DTC_INT_ENA (BIT(25)) +#define SDIO_CMD_DTC_INT_ENA_M (SDIO_CMD_DTC_INT_ENA_V << SDIO_CMD_DTC_INT_ENA_S) +#define SDIO_CMD_DTC_INT_ENA_V 0x00000001U +#define SDIO_CMD_DTC_INT_ENA_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ENA : R/W; bitpos: [26]; default: 0; + * The interrupt enable bit for SLC0_RX_QUICK_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_M (SDIO_SLC0_RX_QUICK_EOF_INT_ENA_V << SDIO_SLC0_RX_QUICK_EOF_INT_ENA_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA : R/W; bitpos: [27]; default: 0; + * The interrupt enable bit for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_S 27 +/** SDIO_HDA_RECV_DONE_INT_ENA : R/W; bitpos: [28]; default: 0; + * The interrupt enable bit for HDA_RECV_DONE_INT interrupt. + */ +#define SDIO_HDA_RECV_DONE_INT_ENA (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ENA_M (SDIO_HDA_RECV_DONE_INT_ENA_V << SDIO_HDA_RECV_DONE_INT_ENA_S) +#define SDIO_HDA_RECV_DONE_INT_ENA_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ENA_S 28 + +/** SDIO_SLC_SLC0INT_CLR_REG register + * Sdio slave DMA channel0 interrupt clear register. + */ +#define SDIO_SLC_SLC0INT_CLR_REG (DR_REG_SLC_BASE + 0x10) +/** SDIO_SLC_FRHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT0_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT0_INT_CLR (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_CLR_M (SDIO_SLC_FRHOST_BIT0_INT_CLR_V << SDIO_SLC_FRHOST_BIT0_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT0_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_CLR_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT1_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT1_INT_CLR (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_CLR_M (SDIO_SLC_FRHOST_BIT1_INT_CLR_V << SDIO_SLC_FRHOST_BIT1_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT1_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_CLR_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT2_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT2_INT_CLR (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_CLR_M (SDIO_SLC_FRHOST_BIT2_INT_CLR_V << SDIO_SLC_FRHOST_BIT2_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT2_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_CLR_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT3_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT3_INT_CLR (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_CLR_M (SDIO_SLC_FRHOST_BIT3_INT_CLR_V << SDIO_SLC_FRHOST_BIT3_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT3_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_CLR_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT4_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT4_INT_CLR (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_CLR_M (SDIO_SLC_FRHOST_BIT4_INT_CLR_V << SDIO_SLC_FRHOST_BIT4_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT4_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_CLR_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT5_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT5_INT_CLR (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_CLR_M (SDIO_SLC_FRHOST_BIT5_INT_CLR_V << SDIO_SLC_FRHOST_BIT5_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT5_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_CLR_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT6_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT6_INT_CLR (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_CLR_M (SDIO_SLC_FRHOST_BIT6_INT_CLR_V << SDIO_SLC_FRHOST_BIT6_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT6_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_CLR_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT7_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT7_INT_CLR (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_CLR_M (SDIO_SLC_FRHOST_BIT7_INT_CLR_V << SDIO_SLC_FRHOST_BIT7_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT7_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_CLR_S 7 +/** SDIO_SLC0_RX_START_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear SLC0_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_RX_START_INT_CLR (BIT(8)) +#define SDIO_SLC0_RX_START_INT_CLR_M (SDIO_SLC0_RX_START_INT_CLR_V << SDIO_SLC0_RX_START_INT_CLR_S) +#define SDIO_SLC0_RX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_CLR_S 8 +/** SDIO_SLC0_TX_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear SLC0_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_START_INT_CLR (BIT(9)) +#define SDIO_SLC0_TX_START_INT_CLR_M (SDIO_SLC0_TX_START_INT_CLR_V << SDIO_SLC0_TX_START_INT_CLR_S) +#define SDIO_SLC0_TX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_CLR_S 9 +/** SDIO_SLC0_RX_UDF_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear SLC0_RX_UDF_INT interrupt. + */ +#define SDIO_SLC0_RX_UDF_INT_CLR (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_CLR_M (SDIO_SLC0_RX_UDF_INT_CLR_V << SDIO_SLC0_RX_UDF_INT_CLR_S) +#define SDIO_SLC0_RX_UDF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_CLR_S 10 +/** SDIO_SLC0_TX_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear SLC0_TX_OVF_INT interrupt. + */ +#define SDIO_SLC0_TX_OVF_INT_CLR (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_CLR_M (SDIO_SLC0_TX_OVF_INT_CLR_V << SDIO_SLC0_TX_OVF_INT_CLR_S) +#define SDIO_SLC0_TX_OVF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_CLR_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear SLC0_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_M (SDIO_SLC0_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC0_TOKEN0_1TO0_INT_CLR_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear SLC0_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_M (SDIO_SLC0_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC0_TOKEN1_1TO0_INT_CLR_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_S 13 +/** SDIO_SLC0_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear SLC0_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_DONE_INT_CLR (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_CLR_M (SDIO_SLC0_TX_DONE_INT_CLR_V << SDIO_SLC0_TX_DONE_INT_CLR_S) +#define SDIO_SLC0_TX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_CLR_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear SLC0_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_M (SDIO_SLC0_TX_SUC_EOF_INT_CLR_V << SDIO_SLC0_TX_SUC_EOF_INT_CLR_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_S 15 +/** SDIO_SLC0_RX_DONE_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear SLC0_RX_DONE_INT interrupt. + */ +#define SDIO_SLC0_RX_DONE_INT_CLR (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_CLR_M (SDIO_SLC0_RX_DONE_INT_CLR_V << SDIO_SLC0_RX_DONE_INT_CLR_S) +#define SDIO_SLC0_RX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_CLR_S 16 +/** SDIO_SLC0_RX_EOF_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear SLC0_RX_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_EOF_INT_CLR (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_CLR_M (SDIO_SLC0_RX_EOF_INT_CLR_V << SDIO_SLC0_RX_EOF_INT_CLR_S) +#define SDIO_SLC0_RX_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_CLR_S 17 +/** SDIO_SLC0_TOHOST_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear SLC0_TOHOST_INT interrupt. + */ +#define SDIO_SLC0_TOHOST_INT_CLR (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_CLR_M (SDIO_SLC0_TOHOST_INT_CLR_V << SDIO_SLC0_TOHOST_INT_CLR_S) +#define SDIO_SLC0_TOHOST_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_CLR_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear SLC0_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_M (SDIO_SLC0_TX_DSCR_ERR_INT_CLR_V << SDIO_SLC0_TX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_CLR : WT; bitpos: [20]; default: 0; + * Set this bit to clear SLC0_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_M (SDIO_SLC0_RX_DSCR_ERR_INT_CLR_V << SDIO_SLC0_RX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR : WT; bitpos: [21]; default: 0; + * Set this bit to clear SLC0_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_CLR : WT; bitpos: [22]; default: 0; + * Set this bit to clear SLC0_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_M (SDIO_SLC0_HOST_RD_ACK_INT_CLR_V << SDIO_SLC0_HOST_RD_ACK_INT_CLR_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_CLR : WT; bitpos: [23]; default: 0; + * Set this bit to clear SLC0_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_M (SDIO_SLC0_WR_RETRY_DONE_INT_CLR_V << SDIO_SLC0_WR_RETRY_DONE_INT_CLR_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_CLR : WT; bitpos: [24]; default: 0; + * Set this bit to clear SLC0_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_M (SDIO_SLC0_TX_ERR_EOF_INT_CLR_V << SDIO_SLC0_TX_ERR_EOF_INT_CLR_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_S 24 +/** SDIO_CMD_DTC_INT_CLR : WT; bitpos: [25]; default: 0; + * Set this bit to clear CMD_DTC_INT interrupt. + */ +#define SDIO_CMD_DTC_INT_CLR (BIT(25)) +#define SDIO_CMD_DTC_INT_CLR_M (SDIO_CMD_DTC_INT_CLR_V << SDIO_CMD_DTC_INT_CLR_S) +#define SDIO_CMD_DTC_INT_CLR_V 0x00000001U +#define SDIO_CMD_DTC_INT_CLR_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_CLR : WT; bitpos: [26]; default: 0; + * Set this bit to clear SLC0_RX_QUICK_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_M (SDIO_SLC0_RX_QUICK_EOF_INT_CLR_V << SDIO_SLC0_RX_QUICK_EOF_INT_CLR_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR : WT; bitpos: [27]; default: 0; + * Set this bit to clear SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_S 27 +/** SDIO_HDA_RECV_DONE_INT_CLR : WT; bitpos: [28]; default: 0; + * Set this bit to clear HDA_RECV_DONE_INT interrupt. + */ +#define SDIO_HDA_RECV_DONE_INT_CLR (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_CLR_M (SDIO_HDA_RECV_DONE_INT_CLR_V << SDIO_HDA_RECV_DONE_INT_CLR_S) +#define SDIO_HDA_RECV_DONE_INT_CLR_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_CLR_S 28 + +/** SDIO_SLC_SLC1INT_RAW_REG register + * Sdio slave DMA channel1 raw interrupt status register. + */ +#define SDIO_SLC_SLC1INT_RAW_REG (DR_REG_SLC_BASE + 0x14) +/** SDIO_SLC_FRHOST_BIT8_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit 8 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT8_INT_RAW (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_RAW_M (SDIO_SLC_FRHOST_BIT8_INT_RAW_V << SDIO_SLC_FRHOST_BIT8_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT8_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_RAW_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit 9 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT9_INT_RAW (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_RAW_M (SDIO_SLC_FRHOST_BIT9_INT_RAW_V << SDIO_SLC_FRHOST_BIT9_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT9_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_RAW_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit 10 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT10_INT_RAW (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_RAW_M (SDIO_SLC_FRHOST_BIT10_INT_RAW_V << SDIO_SLC_FRHOST_BIT10_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT10_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_RAW_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit 11 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT11_INT_RAW (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_RAW_M (SDIO_SLC_FRHOST_BIT11_INT_RAW_V << SDIO_SLC_FRHOST_BIT11_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT11_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_RAW_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit 12 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT12_INT_RAW (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_RAW_M (SDIO_SLC_FRHOST_BIT12_INT_RAW_V << SDIO_SLC_FRHOST_BIT12_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT12_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_RAW_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit 13 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT13_INT_RAW (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_RAW_M (SDIO_SLC_FRHOST_BIT13_INT_RAW_V << SDIO_SLC_FRHOST_BIT13_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT13_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_RAW_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit 14 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT14_INT_RAW (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_RAW_M (SDIO_SLC_FRHOST_BIT14_INT_RAW_V << SDIO_SLC_FRHOST_BIT14_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT14_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_RAW_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit 15 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT15_INT_RAW (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_RAW_M (SDIO_SLC_FRHOST_BIT15_INT_RAW_V << SDIO_SLC_FRHOST_BIT15_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT15_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_RAW_S 7 +/** SDIO_SLC1_RX_START_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit of registering dma channel1 sending initialization + */ +#define SDIO_SLC1_RX_START_INT_RAW (BIT(8)) +#define SDIO_SLC1_RX_START_INT_RAW_M (SDIO_SLC1_RX_START_INT_RAW_V << SDIO_SLC1_RX_START_INT_RAW_S) +#define SDIO_SLC1_RX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_RAW_S 8 +/** SDIO_SLC1_TX_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit of registering dma channel1 receiving initialization + */ +#define SDIO_SLC1_TX_START_INT_RAW (BIT(9)) +#define SDIO_SLC1_TX_START_INT_RAW_M (SDIO_SLC1_TX_START_INT_RAW_V << SDIO_SLC1_TX_START_INT_RAW_S) +#define SDIO_SLC1_TX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_RAW_S 9 +/** SDIO_SLC1_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit of dma channel1 sending buffer underflow. + */ +#define SDIO_SLC1_RX_UDF_INT_RAW (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_RAW_M (SDIO_SLC1_RX_UDF_INT_RAW_V << SDIO_SLC1_RX_UDF_INT_RAW_S) +#define SDIO_SLC1_RX_UDF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_RAW_S 10 +/** SDIO_SLC1_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit of dma channel1 receiving buffer overflow. + */ +#define SDIO_SLC1_TX_OVF_INT_RAW (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_RAW_M (SDIO_SLC1_TX_OVF_INT_RAW_V << SDIO_SLC1_TX_OVF_INT_RAW_S) +#define SDIO_SLC1_TX_OVF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_RAW_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit for the value of slc0_token0 becoming to zero. + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_M (SDIO_SLC1_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC1_TOKEN0_1TO0_INT_RAW_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit for the value of slc0_token1 becoming to zero. + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_M (SDIO_SLC1_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC1_TOKEN1_1TO0_INT_RAW_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_S 13 +/** SDIO_SLC1_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit of dma channel1 finishing receiving data to one single buffer. + */ +#define SDIO_SLC1_TX_DONE_INT_RAW (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_RAW_M (SDIO_SLC1_TX_DONE_INT_RAW_V << SDIO_SLC1_TX_DONE_INT_RAW_S) +#define SDIO_SLC1_TX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_RAW_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit of dma channel1 finishing receiving data + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_M (SDIO_SLC1_TX_SUC_EOF_INT_RAW_V << SDIO_SLC1_TX_SUC_EOF_INT_RAW_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_S 15 +/** SDIO_SLC1_RX_DONE_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt bit of dma channel1 finishing sending data from one single buffer + */ +#define SDIO_SLC1_RX_DONE_INT_RAW (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_RAW_M (SDIO_SLC1_RX_DONE_INT_RAW_V << SDIO_SLC1_RX_DONE_INT_RAW_S) +#define SDIO_SLC1_RX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_RAW_S 16 +/** SDIO_SLC1_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt bit of dma channel1 finishing sending data + */ +#define SDIO_SLC1_RX_EOF_INT_RAW (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_RAW_M (SDIO_SLC1_RX_EOF_INT_RAW_V << SDIO_SLC1_RX_EOF_INT_RAW_S) +#define SDIO_SLC1_RX_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_RAW_S 17 +/** SDIO_SLC1_TOHOST_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The raw interrupt bit for slave generating interrupt to host. + */ +#define SDIO_SLC1_TOHOST_INT_RAW (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_RAW_M (SDIO_SLC1_TOHOST_INT_RAW_V << SDIO_SLC1_TOHOST_INT_RAW_S) +#define SDIO_SLC1_TOHOST_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_RAW_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt bit of dma channel1 receiving descriptor error. + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_M (SDIO_SLC1_TX_DSCR_ERR_INT_RAW_V << SDIO_SLC1_TX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt bit of dma channel1 sending descriptor error. + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_M (SDIO_SLC1_RX_DSCR_ERR_INT_RAW_V << SDIO_SLC1_RX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * The raw interrupt bit of not enough buffer for slave receiving data from host + * through dma channel1. + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * The raw interrupt bit for host to acknowledge retrying receiving data from slave + * successfully through dma channel1. + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_M (SDIO_SLC1_HOST_RD_ACK_INT_RAW_V << SDIO_SLC1_HOST_RD_ACK_INT_RAW_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * The raw interrupt bit of host finishing retrying sending data to slave through dma + * channel1. + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_M (SDIO_SLC1_WR_RETRY_DONE_INT_RAW_V << SDIO_SLC1_WR_RETRY_DONE_INT_RAW_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * The raw interrupt bit of data error during host sending data to slave through dma + * channel1. + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_M (SDIO_SLC1_TX_ERR_EOF_INT_RAW_V << SDIO_SLC1_TX_ERR_EOF_INT_RAW_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_S 24 + +/** SDIO_SLC_SLC1INT_ST_REG register + * Sdio slave DMA channel1 masked interrupt status register. + */ +#define SDIO_SLC_SLC1INT_ST_REG (DR_REG_SLC_BASE + 0x18) +/** SDIO_SLC_FRHOST_BIT8_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT0_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ST (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ST_M (SDIO_SLC_FRHOST_BIT8_INT_ST_V << SDIO_SLC_FRHOST_BIT8_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ST_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT1_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ST (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ST_M (SDIO_SLC_FRHOST_BIT9_INT_ST_V << SDIO_SLC_FRHOST_BIT9_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ST_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT2_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ST (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ST_M (SDIO_SLC_FRHOST_BIT10_INT_ST_V << SDIO_SLC_FRHOST_BIT10_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ST_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT3_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ST (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ST_M (SDIO_SLC_FRHOST_BIT11_INT_ST_V << SDIO_SLC_FRHOST_BIT11_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ST_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT4_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ST (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ST_M (SDIO_SLC_FRHOST_BIT12_INT_ST_V << SDIO_SLC_FRHOST_BIT12_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ST_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT5_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ST (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ST_M (SDIO_SLC_FRHOST_BIT13_INT_ST_V << SDIO_SLC_FRHOST_BIT13_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ST_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT6_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ST (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ST_M (SDIO_SLC_FRHOST_BIT14_INT_ST_V << SDIO_SLC_FRHOST_BIT14_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ST_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT7_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ST (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ST_M (SDIO_SLC_FRHOST_BIT15_INT_ST_V << SDIO_SLC_FRHOST_BIT15_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ST_S 7 +/** SDIO_SLC1_RX_START_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for SLC1_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_RX_START_INT_ST (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ST_M (SDIO_SLC1_RX_START_INT_ST_V << SDIO_SLC1_RX_START_INT_ST_S) +#define SDIO_SLC1_RX_START_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ST_S 8 +/** SDIO_SLC1_TX_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for SLC1_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_START_INT_ST (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ST_M (SDIO_SLC1_TX_START_INT_ST_V << SDIO_SLC1_TX_START_INT_ST_S) +#define SDIO_SLC1_TX_START_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ST_S 9 +/** SDIO_SLC1_RX_UDF_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for SLC1_RX_UDF_INT interrupt. + */ +#define SDIO_SLC1_RX_UDF_INT_ST (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ST_M (SDIO_SLC1_RX_UDF_INT_ST_V << SDIO_SLC1_RX_UDF_INT_ST_S) +#define SDIO_SLC1_RX_UDF_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ST_S 10 +/** SDIO_SLC1_TX_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for SLC1_TX_OVF_INT interrupt. + */ +#define SDIO_SLC1_TX_OVF_INT_ST (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ST_M (SDIO_SLC1_TX_OVF_INT_ST_V << SDIO_SLC1_TX_OVF_INT_ST_S) +#define SDIO_SLC1_TX_OVF_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ST_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for SLC1_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_M (SDIO_SLC1_TOKEN0_1TO0_INT_ST_V << SDIO_SLC1_TOKEN0_1TO0_INT_ST_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for SLC1_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_M (SDIO_SLC1_TOKEN1_1TO0_INT_ST_V << SDIO_SLC1_TOKEN1_1TO0_INT_ST_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_S 13 +/** SDIO_SLC1_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for SLC1_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_DONE_INT_ST (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ST_M (SDIO_SLC1_TX_DONE_INT_ST_V << SDIO_SLC1_TX_DONE_INT_ST_S) +#define SDIO_SLC1_TX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ST_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for SLC1_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ST (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST_M (SDIO_SLC1_TX_SUC_EOF_INT_ST_V << SDIO_SLC1_TX_SUC_EOF_INT_ST_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ST_S 15 +/** SDIO_SLC1_RX_DONE_INT_ST : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for SLC1_RX_DONE_INT interrupt. + */ +#define SDIO_SLC1_RX_DONE_INT_ST (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ST_M (SDIO_SLC1_RX_DONE_INT_ST_V << SDIO_SLC1_RX_DONE_INT_ST_S) +#define SDIO_SLC1_RX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ST_S 16 +/** SDIO_SLC1_RX_EOF_INT_ST : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for SLC1_RX_EOF_INT interrupt. + */ +#define SDIO_SLC1_RX_EOF_INT_ST (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ST_M (SDIO_SLC1_RX_EOF_INT_ST_V << SDIO_SLC1_RX_EOF_INT_ST_S) +#define SDIO_SLC1_RX_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ST_S 17 +/** SDIO_SLC1_TOHOST_INT_ST : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for SLC1_TOHOST_INT interrupt. + */ +#define SDIO_SLC1_TOHOST_INT_ST (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ST_M (SDIO_SLC1_TOHOST_INT_ST_V << SDIO_SLC1_TOHOST_INT_ST_S) +#define SDIO_SLC1_TOHOST_INT_ST_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ST_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ST : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit for SLC1_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_M (SDIO_SLC1_TX_DSCR_ERR_INT_ST_V << SDIO_SLC1_TX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ST : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit for SLC1_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_M (SDIO_SLC1_RX_DSCR_ERR_INT_ST_V << SDIO_SLC1_RX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ST : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit for SLC1_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ST : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit for SLC1_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ST (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST_M (SDIO_SLC1_HOST_RD_ACK_INT_ST_V << SDIO_SLC1_HOST_RD_ACK_INT_ST_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ST_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ST : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit for SLC1_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_M (SDIO_SLC1_WR_RETRY_DONE_INT_ST_V << SDIO_SLC1_WR_RETRY_DONE_INT_ST_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ST : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit for SLC1_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ST (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST_M (SDIO_SLC1_TX_ERR_EOF_INT_ST_V << SDIO_SLC1_TX_ERR_EOF_INT_ST_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ST_S 24 + +/** SDIO_SLC_SLC1INT_ENA_REG register + * Sdio slave DMA channel1 interrupt enable register. + */ +#define SDIO_SLC_SLC1INT_ENA_REG (DR_REG_SLC_BASE + 0x1c) +/** SDIO_SLC_FRHOST_BIT8_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT0_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ENA (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA_M (SDIO_SLC_FRHOST_BIT8_INT_ENA_V << SDIO_SLC_FRHOST_BIT8_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ENA_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT1_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ENA (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA_M (SDIO_SLC_FRHOST_BIT9_INT_ENA_V << SDIO_SLC_FRHOST_BIT9_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ENA_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT2_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ENA (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA_M (SDIO_SLC_FRHOST_BIT10_INT_ENA_V << SDIO_SLC_FRHOST_BIT10_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ENA_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT3_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ENA (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA_M (SDIO_SLC_FRHOST_BIT11_INT_ENA_V << SDIO_SLC_FRHOST_BIT11_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ENA_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT4_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ENA (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA_M (SDIO_SLC_FRHOST_BIT12_INT_ENA_V << SDIO_SLC_FRHOST_BIT12_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ENA_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT5_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ENA (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA_M (SDIO_SLC_FRHOST_BIT13_INT_ENA_V << SDIO_SLC_FRHOST_BIT13_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ENA_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT6_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ENA (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA_M (SDIO_SLC_FRHOST_BIT14_INT_ENA_V << SDIO_SLC_FRHOST_BIT14_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ENA_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT7_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ENA (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA_M (SDIO_SLC_FRHOST_BIT15_INT_ENA_V << SDIO_SLC_FRHOST_BIT15_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ENA_S 7 +/** SDIO_SLC1_RX_START_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for SCL1_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_RX_START_INT_ENA (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ENA_M (SDIO_SLC1_RX_START_INT_ENA_V << SDIO_SLC1_RX_START_INT_ENA_S) +#define SDIO_SLC1_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ENA_S 8 +/** SDIO_SLC1_TX_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for SCL1_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_START_INT_ENA (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ENA_M (SDIO_SLC1_TX_START_INT_ENA_V << SDIO_SLC1_TX_START_INT_ENA_S) +#define SDIO_SLC1_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ENA_S 9 +/** SDIO_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for SCL1_RX_UDF_INT interrupt. + */ +#define SDIO_SLC1_RX_UDF_INT_ENA (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ENA_M (SDIO_SLC1_RX_UDF_INT_ENA_V << SDIO_SLC1_RX_UDF_INT_ENA_S) +#define SDIO_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ENA_S 10 +/** SDIO_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for SCL1_TX_OVF_INT interrupt. + */ +#define SDIO_SLC1_TX_OVF_INT_ENA (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ENA_M (SDIO_SLC1_TX_OVF_INT_ENA_V << SDIO_SLC1_TX_OVF_INT_ENA_S) +#define SDIO_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ENA_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for SCL1_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_M (SDIO_SLC1_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for SCL1_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_M (SDIO_SLC1_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_S 13 +/** SDIO_SLC1_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for SCL1_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_DONE_INT_ENA (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ENA_M (SDIO_SLC1_TX_DONE_INT_ENA_V << SDIO_SLC1_TX_DONE_INT_ENA_S) +#define SDIO_SLC1_TX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ENA_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for SCL1_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_M (SDIO_SLC1_TX_SUC_EOF_INT_ENA_V << SDIO_SLC1_TX_SUC_EOF_INT_ENA_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_S 15 +/** SDIO_SLC1_RX_DONE_INT_ENA : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for SCL1_RX_DONE_INT interrupt. + */ +#define SDIO_SLC1_RX_DONE_INT_ENA (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ENA_M (SDIO_SLC1_RX_DONE_INT_ENA_V << SDIO_SLC1_RX_DONE_INT_ENA_S) +#define SDIO_SLC1_RX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ENA_S 16 +/** SDIO_SLC1_RX_EOF_INT_ENA : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for SCL1_RX_EOF_INT interrupt. + */ +#define SDIO_SLC1_RX_EOF_INT_ENA (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ENA_M (SDIO_SLC1_RX_EOF_INT_ENA_V << SDIO_SLC1_RX_EOF_INT_ENA_S) +#define SDIO_SLC1_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ENA_S 17 +/** SDIO_SLC1_TOHOST_INT_ENA : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for SCL1_TOHOST_INT interrupt. + */ +#define SDIO_SLC1_TOHOST_INT_ENA (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ENA_M (SDIO_SLC1_TOHOST_INT_ENA_V << SDIO_SLC1_TOHOST_INT_ENA_S) +#define SDIO_SLC1_TOHOST_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ENA_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ENA : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for SCL1_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_M (SDIO_SLC1_TX_DSCR_ERR_INT_ENA_V << SDIO_SLC1_TX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ENA : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit for SCL1_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_M (SDIO_SLC1_RX_DSCR_ERR_INT_ENA_V << SDIO_SLC1_RX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit for SCL1_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ENA : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit for SCL1_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_M (SDIO_SLC1_HOST_RD_ACK_INT_ENA_V << SDIO_SLC1_HOST_RD_ACK_INT_ENA_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ENA : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit for SCL1_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_M (SDIO_SLC1_WR_RETRY_DONE_INT_ENA_V << SDIO_SLC1_WR_RETRY_DONE_INT_ENA_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ENA : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit for SCL1_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_M (SDIO_SLC1_TX_ERR_EOF_INT_ENA_V << SDIO_SLC1_TX_ERR_EOF_INT_ENA_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_S 24 + +/** SDIO_SLC_SLC1INT_CLR_REG register + * Sdio slave DMA channel1 interrupt clear register. + */ +#define SDIO_SLC_SLC1INT_CLR_REG (DR_REG_SLC_BASE + 0x20) +/** SDIO_SLC_FRHOST_BIT8_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT0_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT8_INT_CLR (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_CLR_M (SDIO_SLC_FRHOST_BIT8_INT_CLR_V << SDIO_SLC_FRHOST_BIT8_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT8_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_CLR_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT1_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT9_INT_CLR (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_CLR_M (SDIO_SLC_FRHOST_BIT9_INT_CLR_V << SDIO_SLC_FRHOST_BIT9_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT9_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_CLR_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT2_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT10_INT_CLR (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_CLR_M (SDIO_SLC_FRHOST_BIT10_INT_CLR_V << SDIO_SLC_FRHOST_BIT10_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT10_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_CLR_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT3_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT11_INT_CLR (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_CLR_M (SDIO_SLC_FRHOST_BIT11_INT_CLR_V << SDIO_SLC_FRHOST_BIT11_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT11_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_CLR_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT4_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT12_INT_CLR (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_CLR_M (SDIO_SLC_FRHOST_BIT12_INT_CLR_V << SDIO_SLC_FRHOST_BIT12_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT12_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_CLR_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT5_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT13_INT_CLR (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_CLR_M (SDIO_SLC_FRHOST_BIT13_INT_CLR_V << SDIO_SLC_FRHOST_BIT13_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT13_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_CLR_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT6_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT14_INT_CLR (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_CLR_M (SDIO_SLC_FRHOST_BIT14_INT_CLR_V << SDIO_SLC_FRHOST_BIT14_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT14_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_CLR_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT7_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT15_INT_CLR (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_CLR_M (SDIO_SLC_FRHOST_BIT15_INT_CLR_V << SDIO_SLC_FRHOST_BIT15_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT15_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_CLR_S 7 +/** SDIO_SLC1_RX_START_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear SLC1_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_RX_START_INT_CLR (BIT(8)) +#define SDIO_SLC1_RX_START_INT_CLR_M (SDIO_SLC1_RX_START_INT_CLR_V << SDIO_SLC1_RX_START_INT_CLR_S) +#define SDIO_SLC1_RX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_CLR_S 8 +/** SDIO_SLC1_TX_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear SLC1_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_START_INT_CLR (BIT(9)) +#define SDIO_SLC1_TX_START_INT_CLR_M (SDIO_SLC1_TX_START_INT_CLR_V << SDIO_SLC1_TX_START_INT_CLR_S) +#define SDIO_SLC1_TX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_CLR_S 9 +/** SDIO_SLC1_RX_UDF_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear SLC1_RX_UDF_INT interrupt. + */ +#define SDIO_SLC1_RX_UDF_INT_CLR (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_CLR_M (SDIO_SLC1_RX_UDF_INT_CLR_V << SDIO_SLC1_RX_UDF_INT_CLR_S) +#define SDIO_SLC1_RX_UDF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_CLR_S 10 +/** SDIO_SLC1_TX_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear SLC1_TX_OVF_INT interrupt. + */ +#define SDIO_SLC1_TX_OVF_INT_CLR (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_CLR_M (SDIO_SLC1_TX_OVF_INT_CLR_V << SDIO_SLC1_TX_OVF_INT_CLR_S) +#define SDIO_SLC1_TX_OVF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_CLR_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear SLC1_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_M (SDIO_SLC1_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC1_TOKEN0_1TO0_INT_CLR_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear SLC1_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_M (SDIO_SLC1_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC1_TOKEN1_1TO0_INT_CLR_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_S 13 +/** SDIO_SLC1_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear SLC1_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_DONE_INT_CLR (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_CLR_M (SDIO_SLC1_TX_DONE_INT_CLR_V << SDIO_SLC1_TX_DONE_INT_CLR_S) +#define SDIO_SLC1_TX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_CLR_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear SLC1_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_M (SDIO_SLC1_TX_SUC_EOF_INT_CLR_V << SDIO_SLC1_TX_SUC_EOF_INT_CLR_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_S 15 +/** SDIO_SLC1_RX_DONE_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear SLC1_RX_DONE_INT interrupt. + */ +#define SDIO_SLC1_RX_DONE_INT_CLR (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_CLR_M (SDIO_SLC1_RX_DONE_INT_CLR_V << SDIO_SLC1_RX_DONE_INT_CLR_S) +#define SDIO_SLC1_RX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_CLR_S 16 +/** SDIO_SLC1_RX_EOF_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear SLC1_RX_EOF_INT interrupt. + */ +#define SDIO_SLC1_RX_EOF_INT_CLR (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_CLR_M (SDIO_SLC1_RX_EOF_INT_CLR_V << SDIO_SLC1_RX_EOF_INT_CLR_S) +#define SDIO_SLC1_RX_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_CLR_S 17 +/** SDIO_SLC1_TOHOST_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear SLC1_TOHOST_INT interrupt. + */ +#define SDIO_SLC1_TOHOST_INT_CLR (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_CLR_M (SDIO_SLC1_TOHOST_INT_CLR_V << SDIO_SLC1_TOHOST_INT_CLR_S) +#define SDIO_SLC1_TOHOST_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_CLR_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear SLC1_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_M (SDIO_SLC1_TX_DSCR_ERR_INT_CLR_V << SDIO_SLC1_TX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_CLR : WT; bitpos: [20]; default: 0; + * Set this bit to clear SLC1_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_M (SDIO_SLC1_RX_DSCR_ERR_INT_CLR_V << SDIO_SLC1_RX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR : WT; bitpos: [21]; default: 0; + * Set this bit to clear SLC1_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_CLR : WT; bitpos: [22]; default: 0; + * Set this bit to clear SLC1_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_M (SDIO_SLC1_HOST_RD_ACK_INT_CLR_V << SDIO_SLC1_HOST_RD_ACK_INT_CLR_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_CLR : WT; bitpos: [23]; default: 0; + * Set this bit to clear SLC1_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_M (SDIO_SLC1_WR_RETRY_DONE_INT_CLR_V << SDIO_SLC1_WR_RETRY_DONE_INT_CLR_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_CLR : WT; bitpos: [24]; default: 0; + * Set this bit to clear SLC1_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_M (SDIO_SLC1_TX_ERR_EOF_INT_CLR_V << SDIO_SLC1_TX_ERR_EOF_INT_CLR_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_S 24 + +/** SDIO_SLC_RX_STATUS_REG register + * Sdio slave DMA rxfifo status register. + */ +#define SDIO_SLC_RX_STATUS_REG (DR_REG_SLC_BASE + 0x24) +/** SDIO_SLC0_RX_FULL : RO; bitpos: [0]; default: 0; + * The status bit for rxfifo full during slave sending data to host through dma + * channel0. + */ +#define SDIO_SLC0_RX_FULL (BIT(0)) +#define SDIO_SLC0_RX_FULL_M (SDIO_SLC0_RX_FULL_V << SDIO_SLC0_RX_FULL_S) +#define SDIO_SLC0_RX_FULL_V 0x00000001U +#define SDIO_SLC0_RX_FULL_S 0 +/** SDIO_SLC0_RX_EMPTY : RO; bitpos: [1]; default: 1; + * The status bit for rxfifo empty during slave sending data to host through dma + * channel0. + */ +#define SDIO_SLC0_RX_EMPTY (BIT(1)) +#define SDIO_SLC0_RX_EMPTY_M (SDIO_SLC0_RX_EMPTY_V << SDIO_SLC0_RX_EMPTY_S) +#define SDIO_SLC0_RX_EMPTY_V 0x00000001U +#define SDIO_SLC0_RX_EMPTY_S 1 +/** SDIO_SLC0_RX_BUF_LEN : RO; bitpos: [15:2]; default: 0; + * the current buffer length during slave sending data to host through dma channel0. + */ +#define SDIO_SLC0_RX_BUF_LEN 0x00003FFFU +#define SDIO_SLC0_RX_BUF_LEN_M (SDIO_SLC0_RX_BUF_LEN_V << SDIO_SLC0_RX_BUF_LEN_S) +#define SDIO_SLC0_RX_BUF_LEN_V 0x00003FFFU +#define SDIO_SLC0_RX_BUF_LEN_S 2 +/** SDIO_SLC1_RX_FULL : RO; bitpos: [16]; default: 0; + * The status bit for rxfifo full during slave sending data to host through dma + * channel1. + */ +#define SDIO_SLC1_RX_FULL (BIT(16)) +#define SDIO_SLC1_RX_FULL_M (SDIO_SLC1_RX_FULL_V << SDIO_SLC1_RX_FULL_S) +#define SDIO_SLC1_RX_FULL_V 0x00000001U +#define SDIO_SLC1_RX_FULL_S 16 +/** SDIO_SLC1_RX_EMPTY : RO; bitpos: [17]; default: 1; + * The status bit for rxfifo empty during slave sending data to host through dma + * channel1. + */ +#define SDIO_SLC1_RX_EMPTY (BIT(17)) +#define SDIO_SLC1_RX_EMPTY_M (SDIO_SLC1_RX_EMPTY_V << SDIO_SLC1_RX_EMPTY_S) +#define SDIO_SLC1_RX_EMPTY_V 0x00000001U +#define SDIO_SLC1_RX_EMPTY_S 17 +/** SDIO_SLC1_RX_BUF_LEN : RO; bitpos: [31:18]; default: 0; + * the current buffer length during slave sending data to host through dma channel1. + */ +#define SDIO_SLC1_RX_BUF_LEN 0x00003FFFU +#define SDIO_SLC1_RX_BUF_LEN_M (SDIO_SLC1_RX_BUF_LEN_V << SDIO_SLC1_RX_BUF_LEN_S) +#define SDIO_SLC1_RX_BUF_LEN_V 0x00003FFFU +#define SDIO_SLC1_RX_BUF_LEN_S 18 + +/** SDIO_SLC_SLC0RXFIFO_PUSH_REG register + * Sdio slave DMA channel0 rxfifo debug register. + */ +#define SDIO_SLC_SLC0RXFIFO_PUSH_REG (DR_REG_SLC_BASE + 0x28) +/** SDIO_SLC0_RXFIFO_WDATA : R/W; bitpos: [8:0]; default: 0; + * The data used to sent into rxfifo through APB bus. + */ +#define SDIO_SLC0_RXFIFO_WDATA 0x000001FFU +#define SDIO_SLC0_RXFIFO_WDATA_M (SDIO_SLC0_RXFIFO_WDATA_V << SDIO_SLC0_RXFIFO_WDATA_S) +#define SDIO_SLC0_RXFIFO_WDATA_V 0x000001FFU +#define SDIO_SLC0_RXFIFO_WDATA_S 0 +/** SDIO_SLC0_RXFIFO_PUSH : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to send slc0_rxfifo_wdata into rxfifo through APB bus. This bit is + * cleared automatically after sending one data to slc0_rxfifo through APB bus + * successfully. + */ +#define SDIO_SLC0_RXFIFO_PUSH (BIT(16)) +#define SDIO_SLC0_RXFIFO_PUSH_M (SDIO_SLC0_RXFIFO_PUSH_V << SDIO_SLC0_RXFIFO_PUSH_S) +#define SDIO_SLC0_RXFIFO_PUSH_V 0x00000001U +#define SDIO_SLC0_RXFIFO_PUSH_S 16 + +/** SDIO_SLC_SLC1RXFIFO_PUSH_REG register + * Sdio slave DMA channel1 rxfifo debug register. + */ +#define SDIO_SLC_SLC1RXFIFO_PUSH_REG (DR_REG_SLC_BASE + 0x2c) +/** SDIO_SLC1_RXFIFO_WDATA : R/W; bitpos: [8:0]; default: 0; + * The data used to sent into rxfifo through APB bus. + */ +#define SDIO_SLC1_RXFIFO_WDATA 0x000001FFU +#define SDIO_SLC1_RXFIFO_WDATA_M (SDIO_SLC1_RXFIFO_WDATA_V << SDIO_SLC1_RXFIFO_WDATA_S) +#define SDIO_SLC1_RXFIFO_WDATA_V 0x000001FFU +#define SDIO_SLC1_RXFIFO_WDATA_S 0 +/** SDIO_SLC1_RXFIFO_PUSH : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to send slc1_rxfifo_wdata into rxfifo through APB bus. This bit is + * cleared automatically after sending one data to slc1_rxfifo through APB bus + * successfully. + */ +#define SDIO_SLC1_RXFIFO_PUSH (BIT(16)) +#define SDIO_SLC1_RXFIFO_PUSH_M (SDIO_SLC1_RXFIFO_PUSH_V << SDIO_SLC1_RXFIFO_PUSH_S) +#define SDIO_SLC1_RXFIFO_PUSH_V 0x00000001U +#define SDIO_SLC1_RXFIFO_PUSH_S 16 + +/** SDIO_SLC_TX_STATUS_REG register + * Sdio slave DMA txfifo status register. + */ +#define SDIO_SLC_TX_STATUS_REG (DR_REG_SLC_BASE + 0x30) +/** SDIO_SLC0_TX_FULL : RO; bitpos: [0]; default: 0; + * The status bit for txfifo full during slave receiving data from host through dma + * channel0. + */ +#define SDIO_SLC0_TX_FULL (BIT(0)) +#define SDIO_SLC0_TX_FULL_M (SDIO_SLC0_TX_FULL_V << SDIO_SLC0_TX_FULL_S) +#define SDIO_SLC0_TX_FULL_V 0x00000001U +#define SDIO_SLC0_TX_FULL_S 0 +/** SDIO_SLC0_TX_EMPTY : RO; bitpos: [1]; default: 1; + * The status bit for txfifo empty during slave receiving data from host through dma + * channel0. + */ +#define SDIO_SLC0_TX_EMPTY (BIT(1)) +#define SDIO_SLC0_TX_EMPTY_M (SDIO_SLC0_TX_EMPTY_V << SDIO_SLC0_TX_EMPTY_S) +#define SDIO_SLC0_TX_EMPTY_V 0x00000001U +#define SDIO_SLC0_TX_EMPTY_S 1 +/** SDIO_SLC1_TX_FULL : RO; bitpos: [16]; default: 0; + * The status bit for txfifo full during slave receiving data from host through dma + * channel1. + */ +#define SDIO_SLC1_TX_FULL (BIT(16)) +#define SDIO_SLC1_TX_FULL_M (SDIO_SLC1_TX_FULL_V << SDIO_SLC1_TX_FULL_S) +#define SDIO_SLC1_TX_FULL_V 0x00000001U +#define SDIO_SLC1_TX_FULL_S 16 +/** SDIO_SLC1_TX_EMPTY : RO; bitpos: [17]; default: 1; + * The status bit for txfifo empty during slave receiving data from host through dma + * channel1. + */ +#define SDIO_SLC1_TX_EMPTY (BIT(17)) +#define SDIO_SLC1_TX_EMPTY_M (SDIO_SLC1_TX_EMPTY_V << SDIO_SLC1_TX_EMPTY_S) +#define SDIO_SLC1_TX_EMPTY_V 0x00000001U +#define SDIO_SLC1_TX_EMPTY_S 17 + +/** SDIO_SLC_SLC0TXFIFO_POP_REG register + * Sdio slave DMA channel0 txfifo debug register. + */ +#define SDIO_SLC_SLC0TXFIFO_POP_REG (DR_REG_SLC_BASE + 0x34) +/** SDIO_SLC0_TXFIFO_RDATA : RO; bitpos: [10:0]; default: 1024; + * This field saves the data read from txfifo through APB bus. + */ +#define SDIO_SLC0_TXFIFO_RDATA 0x000007FFU +#define SDIO_SLC0_TXFIFO_RDATA_M (SDIO_SLC0_TXFIFO_RDATA_V << SDIO_SLC0_TXFIFO_RDATA_S) +#define SDIO_SLC0_TXFIFO_RDATA_V 0x000007FFU +#define SDIO_SLC0_TXFIFO_RDATA_S 0 +/** SDIO_SLC0_TXFIFO_POP : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to read data from txfifo through APB bus. This bit is cleared + * automatically after reading one data from slc0_txfifo through APB bus successfully. + */ +#define SDIO_SLC0_TXFIFO_POP (BIT(16)) +#define SDIO_SLC0_TXFIFO_POP_M (SDIO_SLC0_TXFIFO_POP_V << SDIO_SLC0_TXFIFO_POP_S) +#define SDIO_SLC0_TXFIFO_POP_V 0x00000001U +#define SDIO_SLC0_TXFIFO_POP_S 16 + +/** SDIO_SLC_SLC1TXFIFO_POP_REG register + * Sdio slave DMA channel1 txfifo debug register. + */ +#define SDIO_SLC_SLC1TXFIFO_POP_REG (DR_REG_SLC_BASE + 0x38) +/** SDIO_SLC1_TXFIFO_RDATA : RO; bitpos: [10:0]; default: 1024; + * This field saves the data read from txfifo through APB bus. + */ +#define SDIO_SLC1_TXFIFO_RDATA 0x000007FFU +#define SDIO_SLC1_TXFIFO_RDATA_M (SDIO_SLC1_TXFIFO_RDATA_V << SDIO_SLC1_TXFIFO_RDATA_S) +#define SDIO_SLC1_TXFIFO_RDATA_V 0x000007FFU +#define SDIO_SLC1_TXFIFO_RDATA_S 0 +/** SDIO_SLC1_TXFIFO_POP : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to read data from txfifo through APB bus. This bit is cleared + * automatically after reading one data from slc1_txfifo through APB bus successfully. + */ +#define SDIO_SLC1_TXFIFO_POP (BIT(16)) +#define SDIO_SLC1_TXFIFO_POP_M (SDIO_SLC1_TXFIFO_POP_V << SDIO_SLC1_TXFIFO_POP_S) +#define SDIO_SLC1_TXFIFO_POP_V 0x00000001U +#define SDIO_SLC1_TXFIFO_POP_S 16 + +/** SDIO_SLC_SLC0RX_LINK_REG register + * Sdio slave DMA channel0 configuration and status register of link list for slave + * sending data. + */ +#define SDIO_SLC_SLC0RX_LINK_REG (DR_REG_SLC_BASE + 0x3c) +/** SDIO_SLC0_RXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel0 sending packets. + */ +#define SDIO_SLC0_RXLINK_STOP (BIT(28)) +#define SDIO_SLC0_RXLINK_STOP_M (SDIO_SLC0_RXLINK_STOP_V << SDIO_SLC0_RXLINK_STOP_S) +#define SDIO_SLC0_RXLINK_STOP_V 0x00000001U +#define SDIO_SLC0_RXLINK_STOP_S 28 +/** SDIO_SLC0_RXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel0 sending packets. Sending + * will start from address indicated by SLC0_RXLINK_ADDR. + */ +#define SDIO_SLC0_RXLINK_START (BIT(29)) +#define SDIO_SLC0_RXLINK_START_M (SDIO_SLC0_RXLINK_START_V << SDIO_SLC0_RXLINK_START_S) +#define SDIO_SLC0_RXLINK_START_V 0x00000001U +#define SDIO_SLC0_RXLINK_START_S 29 +/** SDIO_SLC0_RXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel0 sending + * packets. + */ +#define SDIO_SLC0_RXLINK_RESTART (BIT(30)) +#define SDIO_SLC0_RXLINK_RESTART_M (SDIO_SLC0_RXLINK_RESTART_V << SDIO_SLC0_RXLINK_RESTART_S) +#define SDIO_SLC0_RXLINK_RESTART_V 0x00000001U +#define SDIO_SLC0_RXLINK_RESTART_S 30 +/** SDIO_SLC0_RXLINK_PARK : RO; bitpos: [31]; default: 1; + * The status bit for sending link list fsm of dma channel0 in idle state + */ +#define SDIO_SLC0_RXLINK_PARK (BIT(31)) +#define SDIO_SLC0_RXLINK_PARK_M (SDIO_SLC0_RXLINK_PARK_V << SDIO_SLC0_RXLINK_PARK_S) +#define SDIO_SLC0_RXLINK_PARK_V 0x00000001U +#define SDIO_SLC0_RXLINK_PARK_S 31 + +/** SDIO_SLC_SLC0RX_LINK_ADDR_REG register + * Sdio slave DMA channel0 address of first descriptor of sending link list. + */ +#define SDIO_SLC_SLC0RX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x40) +/** SDIO_SLC0_RXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel0's sending linked list. + */ +#define SDIO_SLC0_RXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_ADDR_M (SDIO_SLC0_RXLINK_ADDR_V << SDIO_SLC0_RXLINK_ADDR_S) +#define SDIO_SLC0_RXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_ADDR_S 0 + +/** SDIO_SLC_SLC0TX_LINK_REG register + * Sdio slave DMA channel0 configuration and status register of link list for slave + * receiving data. + */ +#define SDIO_SLC_SLC0TX_LINK_REG (DR_REG_SLC_BASE + 0x44) +/** SDIO_SLC0_TXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel0 receiving packets. + */ +#define SDIO_SLC0_TXLINK_STOP (BIT(28)) +#define SDIO_SLC0_TXLINK_STOP_M (SDIO_SLC0_TXLINK_STOP_V << SDIO_SLC0_TXLINK_STOP_S) +#define SDIO_SLC0_TXLINK_STOP_V 0x00000001U +#define SDIO_SLC0_TXLINK_STOP_S 28 +/** SDIO_SLC0_TXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel0 receiving packets. + * Sending will start from address indicated by SLC0_TXLINK_ADDR. + */ +#define SDIO_SLC0_TXLINK_START (BIT(29)) +#define SDIO_SLC0_TXLINK_START_M (SDIO_SLC0_TXLINK_START_V << SDIO_SLC0_TXLINK_START_S) +#define SDIO_SLC0_TXLINK_START_V 0x00000001U +#define SDIO_SLC0_TXLINK_START_S 29 +/** SDIO_SLC0_TXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel0 receiving + * packets. + */ +#define SDIO_SLC0_TXLINK_RESTART (BIT(30)) +#define SDIO_SLC0_TXLINK_RESTART_M (SDIO_SLC0_TXLINK_RESTART_V << SDIO_SLC0_TXLINK_RESTART_S) +#define SDIO_SLC0_TXLINK_RESTART_V 0x00000001U +#define SDIO_SLC0_TXLINK_RESTART_S 30 +/** SDIO_SLC0_TXLINK_PARK : RO; bitpos: [31]; default: 1; + * The status bit for receiving link list fsm of dma channel0 in idle state + */ +#define SDIO_SLC0_TXLINK_PARK (BIT(31)) +#define SDIO_SLC0_TXLINK_PARK_M (SDIO_SLC0_TXLINK_PARK_V << SDIO_SLC0_TXLINK_PARK_S) +#define SDIO_SLC0_TXLINK_PARK_V 0x00000001U +#define SDIO_SLC0_TXLINK_PARK_S 31 + +/** SDIO_SLC_SLC0TX_LINK_ADDR_REG register + * Sdio slave DMA channel0 address of first descriptor of receiving linked list. + */ +#define SDIO_SLC_SLC0TX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x48) +/** SDIO_SLC0_TXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel0's receiving linked list. + */ +#define SDIO_SLC0_TXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_ADDR_M (SDIO_SLC0_TXLINK_ADDR_V << SDIO_SLC0_TXLINK_ADDR_S) +#define SDIO_SLC0_TXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_ADDR_S 0 + +/** SDIO_SLC_SLC1RX_LINK_REG register + * Sdio slave DMA channel1 configuration and status register of link list for slave + * sending data. + */ +#define SDIO_SLC_SLC1RX_LINK_REG (DR_REG_SLC_BASE + 0x4c) +/** SDIO_SLC1_BT_PACKET : R/W; bitpos: [20]; default: 1; + * Configure the packet type for slave to send: 0- wifi packet, 1- blue-tooth packet. + */ +#define SDIO_SLC1_BT_PACKET (BIT(20)) +#define SDIO_SLC1_BT_PACKET_M (SDIO_SLC1_BT_PACKET_V << SDIO_SLC1_BT_PACKET_S) +#define SDIO_SLC1_BT_PACKET_V 0x00000001U +#define SDIO_SLC1_BT_PACKET_S 20 +/** SDIO_SLC1_RXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel1 sending packets. + */ +#define SDIO_SLC1_RXLINK_STOP (BIT(28)) +#define SDIO_SLC1_RXLINK_STOP_M (SDIO_SLC1_RXLINK_STOP_V << SDIO_SLC1_RXLINK_STOP_S) +#define SDIO_SLC1_RXLINK_STOP_V 0x00000001U +#define SDIO_SLC1_RXLINK_STOP_S 28 +/** SDIO_SLC1_RXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel1 sending packets. Sending + * will start from address indicated by SLC0_RXLINK_ADDR. + */ +#define SDIO_SLC1_RXLINK_START (BIT(29)) +#define SDIO_SLC1_RXLINK_START_M (SDIO_SLC1_RXLINK_START_V << SDIO_SLC1_RXLINK_START_S) +#define SDIO_SLC1_RXLINK_START_V 0x00000001U +#define SDIO_SLC1_RXLINK_START_S 29 +/** SDIO_SLC1_RXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel1 sending + * packets. + */ +#define SDIO_SLC1_RXLINK_RESTART (BIT(30)) +#define SDIO_SLC1_RXLINK_RESTART_M (SDIO_SLC1_RXLINK_RESTART_V << SDIO_SLC1_RXLINK_RESTART_S) +#define SDIO_SLC1_RXLINK_RESTART_V 0x00000001U +#define SDIO_SLC1_RXLINK_RESTART_S 30 +/** SDIO_SLC1_RXLINK_PARK : RO; bitpos: [31]; default: 1; + * The status bit for sending link list fsm of dma channel1 in idle state + */ +#define SDIO_SLC1_RXLINK_PARK (BIT(31)) +#define SDIO_SLC1_RXLINK_PARK_M (SDIO_SLC1_RXLINK_PARK_V << SDIO_SLC1_RXLINK_PARK_S) +#define SDIO_SLC1_RXLINK_PARK_V 0x00000001U +#define SDIO_SLC1_RXLINK_PARK_S 31 + +/** SDIO_SLC_SLC1RX_LINK_ADDR_REG register + * Sdio slave DMA channel1 address of first descriptor of sending link list. + */ +#define SDIO_SLC_SLC1RX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x50) +/** SDIO_SLC1_RXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel1's sending linked list. + */ +#define SDIO_SLC1_RXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_ADDR_M (SDIO_SLC1_RXLINK_ADDR_V << SDIO_SLC1_RXLINK_ADDR_S) +#define SDIO_SLC1_RXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_ADDR_S 0 + +/** SDIO_SLC_SLC1TX_LINK_REG register + * Sdio slave DMA channel1 configuration and status register of link list for slave + * receiving data. + */ +#define SDIO_SLC_SLC1TX_LINK_REG (DR_REG_SLC_BASE + 0x54) +/** SDIO_SLC1_TXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel1 receiving packets. + */ +#define SDIO_SLC1_TXLINK_STOP (BIT(28)) +#define SDIO_SLC1_TXLINK_STOP_M (SDIO_SLC1_TXLINK_STOP_V << SDIO_SLC1_TXLINK_STOP_S) +#define SDIO_SLC1_TXLINK_STOP_V 0x00000001U +#define SDIO_SLC1_TXLINK_STOP_S 28 +/** SDIO_SLC1_TXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel1 receiving packets. + * Sending will start from address indicated by SLC0_TXLINK_ADDR. + */ +#define SDIO_SLC1_TXLINK_START (BIT(29)) +#define SDIO_SLC1_TXLINK_START_M (SDIO_SLC1_TXLINK_START_V << SDIO_SLC1_TXLINK_START_S) +#define SDIO_SLC1_TXLINK_START_V 0x00000001U +#define SDIO_SLC1_TXLINK_START_S 29 +/** SDIO_SLC1_TXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel1 receiving + * packets. + */ +#define SDIO_SLC1_TXLINK_RESTART (BIT(30)) +#define SDIO_SLC1_TXLINK_RESTART_M (SDIO_SLC1_TXLINK_RESTART_V << SDIO_SLC1_TXLINK_RESTART_S) +#define SDIO_SLC1_TXLINK_RESTART_V 0x00000001U +#define SDIO_SLC1_TXLINK_RESTART_S 30 +/** SDIO_SLC1_TXLINK_PARK : RO; bitpos: [31]; default: 1; + * The status bit for receiving link list fsm of dma channel1 in idle state + */ +#define SDIO_SLC1_TXLINK_PARK (BIT(31)) +#define SDIO_SLC1_TXLINK_PARK_M (SDIO_SLC1_TXLINK_PARK_V << SDIO_SLC1_TXLINK_PARK_S) +#define SDIO_SLC1_TXLINK_PARK_V 0x00000001U +#define SDIO_SLC1_TXLINK_PARK_S 31 + +/** SDIO_SLC_SLC1TX_LINK_ADDR_REG register + * Sdio slave DMA channel1 address of first descriptor of receiving linked list. + */ +#define SDIO_SLC_SLC1TX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x58) +/** SDIO_SLC1_TXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel1's receiving linked list. + */ +#define SDIO_SLC1_TXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_ADDR_M (SDIO_SLC1_TXLINK_ADDR_V << SDIO_SLC1_TXLINK_ADDR_S) +#define SDIO_SLC1_TXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_ADDR_S 0 + +/** SDIO_SLC_SLCINTVEC_TOHOST_REG register + * Sdio slave DMA channel0 address of first descriptor of receiving linked list. + */ +#define SDIO_SLC_SLCINTVEC_TOHOST_REG (DR_REG_SLC_BASE + 0x5c) +/** SDIO_SLC0_TOHOST_INTVEC : WT; bitpos: [7:0]; default: 0; + * The interrupt vector for slave to interrupt host through dma channel0. + */ +#define SDIO_SLC0_TOHOST_INTVEC 0x000000FFU +#define SDIO_SLC0_TOHOST_INTVEC_M (SDIO_SLC0_TOHOST_INTVEC_V << SDIO_SLC0_TOHOST_INTVEC_S) +#define SDIO_SLC0_TOHOST_INTVEC_V 0x000000FFU +#define SDIO_SLC0_TOHOST_INTVEC_S 0 +/** SDIO_SLC1_TOHOST_INTVEC : WT; bitpos: [23:16]; default: 0; + * The interrupt vector for slave to interrupt host through dma channel1. + */ +#define SDIO_SLC1_TOHOST_INTVEC 0x000000FFU +#define SDIO_SLC1_TOHOST_INTVEC_M (SDIO_SLC1_TOHOST_INTVEC_V << SDIO_SLC1_TOHOST_INTVEC_S) +#define SDIO_SLC1_TOHOST_INTVEC_V 0x000000FFU +#define SDIO_SLC1_TOHOST_INTVEC_S 16 + +/** SDIO_SLC_SLC0TOKEN0_REG register + * Sdio slave DMA channel0 receiving buffer configuration and status register. + */ +#define SDIO_SLC_SLC0TOKEN0_REG (DR_REG_SLC_BASE + 0x60) +/** SDIO_SLC0_TOKEN0_WDATA : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ +#define SDIO_SLC0_TOKEN0_WDATA 0x00000FFFU +#define SDIO_SLC0_TOKEN0_WDATA_M (SDIO_SLC0_TOKEN0_WDATA_V << SDIO_SLC0_TOKEN0_WDATA_S) +#define SDIO_SLC0_TOKEN0_WDATA_V 0x00000FFFU +#define SDIO_SLC0_TOKEN0_WDATA_S 0 +/** SDIO_SLC0_TOKEN0_WR : WT; bitpos: [12]; default: 0; + * update slc0_token0_wdata into slc0 token0. + */ +#define SDIO_SLC0_TOKEN0_WR (BIT(12)) +#define SDIO_SLC0_TOKEN0_WR_M (SDIO_SLC0_TOKEN0_WR_V << SDIO_SLC0_TOKEN0_WR_S) +#define SDIO_SLC0_TOKEN0_WR_V 0x00000001U +#define SDIO_SLC0_TOKEN0_WR_S 12 +/** SDIO_SLC0_TOKEN0_INC : WT; bitpos: [13]; default: 0; + * Add 1 to slc0_token0. + */ +#define SDIO_SLC0_TOKEN0_INC (BIT(13)) +#define SDIO_SLC0_TOKEN0_INC_M (SDIO_SLC0_TOKEN0_INC_V << SDIO_SLC0_TOKEN0_INC_S) +#define SDIO_SLC0_TOKEN0_INC_V 0x00000001U +#define SDIO_SLC0_TOKEN0_INC_S 13 +/** SDIO_SLC0_TOKEN0_INC_MORE : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC0TOKEN0_SLC0_TOKEN0_WDATA to + * SDIO_SLC0TOKEN0_SLC0_TOKEN0. + */ +#define SDIO_SLC0_TOKEN0_INC_MORE (BIT(14)) +#define SDIO_SLC0_TOKEN0_INC_MORE_M (SDIO_SLC0_TOKEN0_INC_MORE_V << SDIO_SLC0_TOKEN0_INC_MORE_S) +#define SDIO_SLC0_TOKEN0_INC_MORE_V 0x00000001U +#define SDIO_SLC0_TOKEN0_INC_MORE_S 14 +/** SDIO_SLC0_TOKEN0 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel0. + */ +#define SDIO_SLC0_TOKEN0 0x00000FFFU +#define SDIO_SLC0_TOKEN0_M (SDIO_SLC0_TOKEN0_V << SDIO_SLC0_TOKEN0_S) +#define SDIO_SLC0_TOKEN0_V 0x00000FFFU +#define SDIO_SLC0_TOKEN0_S 16 + +/** SDIO_SLC_SLC0TOKEN1_REG register + * Sdio slave DMA channel0 receiving buffer configuration and status register1. + */ +#define SDIO_SLC_SLC0TOKEN1_REG (DR_REG_SLC_BASE + 0x64) +/** SDIO_SLC0_TOKEN1_WDATA : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ +#define SDIO_SLC0_TOKEN1_WDATA 0x00000FFFU +#define SDIO_SLC0_TOKEN1_WDATA_M (SDIO_SLC0_TOKEN1_WDATA_V << SDIO_SLC0_TOKEN1_WDATA_S) +#define SDIO_SLC0_TOKEN1_WDATA_V 0x00000FFFU +#define SDIO_SLC0_TOKEN1_WDATA_S 0 +/** SDIO_SLC0_TOKEN1_WR : WT; bitpos: [12]; default: 0; + * update slc0_token1_wdata into slc0 token1 + */ +#define SDIO_SLC0_TOKEN1_WR (BIT(12)) +#define SDIO_SLC0_TOKEN1_WR_M (SDIO_SLC0_TOKEN1_WR_V << SDIO_SLC0_TOKEN1_WR_S) +#define SDIO_SLC0_TOKEN1_WR_V 0x00000001U +#define SDIO_SLC0_TOKEN1_WR_S 12 +/** SDIO_SLC0_TOKEN1_INC : WT; bitpos: [13]; default: 0; + * slc0_token1 becomes to 1 when auto clear slc0_token1, else add 1 to slc0_token1 + */ +#define SDIO_SLC0_TOKEN1_INC (BIT(13)) +#define SDIO_SLC0_TOKEN1_INC_M (SDIO_SLC0_TOKEN1_INC_V << SDIO_SLC0_TOKEN1_INC_S) +#define SDIO_SLC0_TOKEN1_INC_V 0x00000001U +#define SDIO_SLC0_TOKEN1_INC_S 13 +/** SDIO_SLC0_TOKEN1_INC_MORE : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC0TOKEN1_SLC0_TOKEN1_WDATA to + * SDIO_SLC0TOKEN1_SLC0_TOKEN1. + */ +#define SDIO_SLC0_TOKEN1_INC_MORE (BIT(14)) +#define SDIO_SLC0_TOKEN1_INC_MORE_M (SDIO_SLC0_TOKEN1_INC_MORE_V << SDIO_SLC0_TOKEN1_INC_MORE_S) +#define SDIO_SLC0_TOKEN1_INC_MORE_V 0x00000001U +#define SDIO_SLC0_TOKEN1_INC_MORE_S 14 +/** SDIO_SLC0_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel0. + */ +#define SDIO_SLC0_TOKEN1 0x00000FFFU +#define SDIO_SLC0_TOKEN1_M (SDIO_SLC0_TOKEN1_V << SDIO_SLC0_TOKEN1_S) +#define SDIO_SLC0_TOKEN1_V 0x00000FFFU +#define SDIO_SLC0_TOKEN1_S 16 + +/** SDIO_SLC_SLC1TOKEN0_REG register + * Sdio slave DMA channel1 receiving buffer configuration and status register. + */ +#define SDIO_SLC_SLC1TOKEN0_REG (DR_REG_SLC_BASE + 0x68) +/** SDIO_SLC1_TOKEN0_WDATA : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ +#define SDIO_SLC1_TOKEN0_WDATA 0x00000FFFU +#define SDIO_SLC1_TOKEN0_WDATA_M (SDIO_SLC1_TOKEN0_WDATA_V << SDIO_SLC1_TOKEN0_WDATA_S) +#define SDIO_SLC1_TOKEN0_WDATA_V 0x00000FFFU +#define SDIO_SLC1_TOKEN0_WDATA_S 0 +/** SDIO_SLC1_TOKEN0_WR : WT; bitpos: [12]; default: 0; + * update SLC1_token0_wdata into SLC1 token0. + */ +#define SDIO_SLC1_TOKEN0_WR (BIT(12)) +#define SDIO_SLC1_TOKEN0_WR_M (SDIO_SLC1_TOKEN0_WR_V << SDIO_SLC1_TOKEN0_WR_S) +#define SDIO_SLC1_TOKEN0_WR_V 0x00000001U +#define SDIO_SLC1_TOKEN0_WR_S 12 +/** SDIO_SLC1_TOKEN0_INC : WT; bitpos: [13]; default: 0; + * Add 1 to SLC1_token0. + */ +#define SDIO_SLC1_TOKEN0_INC (BIT(13)) +#define SDIO_SLC1_TOKEN0_INC_M (SDIO_SLC1_TOKEN0_INC_V << SDIO_SLC1_TOKEN0_INC_S) +#define SDIO_SLC1_TOKEN0_INC_V 0x00000001U +#define SDIO_SLC1_TOKEN0_INC_S 13 +/** SDIO_SLC1_TOKEN0_INC_MORE : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC1TOKEN0_SLC1_TOKEN0_WDATA to + * SDIO_SLC1TOKEN0_SLC1_TOKEN0. + */ +#define SDIO_SLC1_TOKEN0_INC_MORE (BIT(14)) +#define SDIO_SLC1_TOKEN0_INC_MORE_M (SDIO_SLC1_TOKEN0_INC_MORE_V << SDIO_SLC1_TOKEN0_INC_MORE_S) +#define SDIO_SLC1_TOKEN0_INC_MORE_V 0x00000001U +#define SDIO_SLC1_TOKEN0_INC_MORE_S 14 +/** SDIO_SLC1_TOKEN0 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel1. + */ +#define SDIO_SLC1_TOKEN0 0x00000FFFU +#define SDIO_SLC1_TOKEN0_M (SDIO_SLC1_TOKEN0_V << SDIO_SLC1_TOKEN0_S) +#define SDIO_SLC1_TOKEN0_V 0x00000FFFU +#define SDIO_SLC1_TOKEN0_S 16 + +/** SDIO_SLC_SLC1TOKEN1_REG register + * Sdio slave DMA channel1 receiving buffer configuration and status register1. + */ +#define SDIO_SLC_SLC1TOKEN1_REG (DR_REG_SLC_BASE + 0x6c) +/** SDIO_SLC1_TOKEN1_WDATA : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ +#define SDIO_SLC1_TOKEN1_WDATA 0x00000FFFU +#define SDIO_SLC1_TOKEN1_WDATA_M (SDIO_SLC1_TOKEN1_WDATA_V << SDIO_SLC1_TOKEN1_WDATA_S) +#define SDIO_SLC1_TOKEN1_WDATA_V 0x00000FFFU +#define SDIO_SLC1_TOKEN1_WDATA_S 0 +/** SDIO_SLC1_TOKEN1_WR : WT; bitpos: [12]; default: 0; + * update SLC1_token1_wdata into SLC1 token1 + */ +#define SDIO_SLC1_TOKEN1_WR (BIT(12)) +#define SDIO_SLC1_TOKEN1_WR_M (SDIO_SLC1_TOKEN1_WR_V << SDIO_SLC1_TOKEN1_WR_S) +#define SDIO_SLC1_TOKEN1_WR_V 0x00000001U +#define SDIO_SLC1_TOKEN1_WR_S 12 +/** SDIO_SLC1_TOKEN1_INC : WT; bitpos: [13]; default: 0; + * SLC1_token1 becomes to 1 when auto clear SLC1_token1, else add 1 to SLC1_token1 + */ +#define SDIO_SLC1_TOKEN1_INC (BIT(13)) +#define SDIO_SLC1_TOKEN1_INC_M (SDIO_SLC1_TOKEN1_INC_V << SDIO_SLC1_TOKEN1_INC_S) +#define SDIO_SLC1_TOKEN1_INC_V 0x00000001U +#define SDIO_SLC1_TOKEN1_INC_S 13 +/** SDIO_SLC1_TOKEN1_INC_MORE : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC1TOKEN1_SLC1_TOKEN1_WDATA to + * SDIO_SLC1TOKEN1_SLC1_TOKEN1. + */ +#define SDIO_SLC1_TOKEN1_INC_MORE (BIT(14)) +#define SDIO_SLC1_TOKEN1_INC_MORE_M (SDIO_SLC1_TOKEN1_INC_MORE_V << SDIO_SLC1_TOKEN1_INC_MORE_S) +#define SDIO_SLC1_TOKEN1_INC_MORE_V 0x00000001U +#define SDIO_SLC1_TOKEN1_INC_MORE_S 14 +/** SDIO_SLC1_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel1. + */ +#define SDIO_SLC1_TOKEN1 0x00000FFFU +#define SDIO_SLC1_TOKEN1_M (SDIO_SLC1_TOKEN1_V << SDIO_SLC1_TOKEN1_S) +#define SDIO_SLC1_TOKEN1_V 0x00000FFFU +#define SDIO_SLC1_TOKEN1_S 16 + +/** SDIO_SLC_CONF1_REG register + * Sdio slave DMA configuration1 register. + */ +#define SDIO_SLC_CONF1_REG (DR_REG_SLC_BASE + 0x70) +/** SDIO_SLC0_CHECK_OWNER : R/W; bitpos: [0]; default: 0; + * Set 1 to check the owner bit of descriptors used by dma channel0. + */ +#define SDIO_SLC0_CHECK_OWNER (BIT(0)) +#define SDIO_SLC0_CHECK_OWNER_M (SDIO_SLC0_CHECK_OWNER_V << SDIO_SLC0_CHECK_OWNER_S) +#define SDIO_SLC0_CHECK_OWNER_V 0x00000001U +#define SDIO_SLC0_CHECK_OWNER_S 0 +/** SDIO_SLC0_TX_CHECK_SUM_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to enable check sum function during slave receiving packets through dma + * channel0. + */ +#define SDIO_SLC0_TX_CHECK_SUM_EN (BIT(1)) +#define SDIO_SLC0_TX_CHECK_SUM_EN_M (SDIO_SLC0_TX_CHECK_SUM_EN_V << SDIO_SLC0_TX_CHECK_SUM_EN_S) +#define SDIO_SLC0_TX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC0_TX_CHECK_SUM_EN_S 1 +/** SDIO_SLC0_RX_CHECK_SUM_EN : R/W; bitpos: [2]; default: 0; + * Set 1 to enable check sum function during slave sending packets through dma + * channel0. + */ +#define SDIO_SLC0_RX_CHECK_SUM_EN (BIT(2)) +#define SDIO_SLC0_RX_CHECK_SUM_EN_M (SDIO_SLC0_RX_CHECK_SUM_EN_V << SDIO_SLC0_RX_CHECK_SUM_EN_S) +#define SDIO_SLC0_RX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC0_RX_CHECK_SUM_EN_S 2 +/** SDIO_SDIO_CMD_HOLD_EN : R/W; bitpos: [3]; default: 1; + * Allow host to send another cmd53 during last cmd53 operating time. + */ +#define SDIO_SDIO_CMD_HOLD_EN (BIT(3)) +#define SDIO_SDIO_CMD_HOLD_EN_M (SDIO_SDIO_CMD_HOLD_EN_V << SDIO_SDIO_CMD_HOLD_EN_S) +#define SDIO_SDIO_CMD_HOLD_EN_V 0x00000001U +#define SDIO_SDIO_CMD_HOLD_EN_S 3 +/** SDIO_SLC0_LEN_AUTO_CLR : R/W; bitpos: [4]; default: 1; + * Set 1 to automatically clear the length of buffers used to send packets ot host + * after host reads this length. (not recommended to use,should be set to 0) + */ +#define SDIO_SLC0_LEN_AUTO_CLR (BIT(4)) +#define SDIO_SLC0_LEN_AUTO_CLR_M (SDIO_SLC0_LEN_AUTO_CLR_V << SDIO_SLC0_LEN_AUTO_CLR_S) +#define SDIO_SLC0_LEN_AUTO_CLR_V 0x00000001U +#define SDIO_SLC0_LEN_AUTO_CLR_S 4 +/** SDIO_SLC0_TX_STITCH_EN : R/W; bitpos: [5]; default: 1; + * Set 1 to enable the stitch mode of dma channel0 receiving linked list . + */ +#define SDIO_SLC0_TX_STITCH_EN (BIT(5)) +#define SDIO_SLC0_TX_STITCH_EN_M (SDIO_SLC0_TX_STITCH_EN_V << SDIO_SLC0_TX_STITCH_EN_S) +#define SDIO_SLC0_TX_STITCH_EN_V 0x00000001U +#define SDIO_SLC0_TX_STITCH_EN_S 5 +/** SDIO_SLC0_RX_STITCH_EN : R/W; bitpos: [6]; default: 1; + * Set 1 to enable the stitch mode of dma channel0 sending linked list . + */ +#define SDIO_SLC0_RX_STITCH_EN (BIT(6)) +#define SDIO_SLC0_RX_STITCH_EN_M (SDIO_SLC0_RX_STITCH_EN_V << SDIO_SLC0_RX_STITCH_EN_S) +#define SDIO_SLC0_RX_STITCH_EN_V 0x00000001U +#define SDIO_SLC0_RX_STITCH_EN_S 6 +/** SDIO_SLC1_CHECK_OWNER : R/W; bitpos: [16]; default: 0; + * Set 1 to check the owner bit of descriptors used by dma channel1. + */ +#define SDIO_SLC1_CHECK_OWNER (BIT(16)) +#define SDIO_SLC1_CHECK_OWNER_M (SDIO_SLC1_CHECK_OWNER_V << SDIO_SLC1_CHECK_OWNER_S) +#define SDIO_SLC1_CHECK_OWNER_V 0x00000001U +#define SDIO_SLC1_CHECK_OWNER_S 16 +/** SDIO_SLC1_TX_CHECK_SUM_EN : R/W; bitpos: [17]; default: 0; + * Set 1 to enable check sum function during slave receiving packets through dma + * channel1. + */ +#define SDIO_SLC1_TX_CHECK_SUM_EN (BIT(17)) +#define SDIO_SLC1_TX_CHECK_SUM_EN_M (SDIO_SLC1_TX_CHECK_SUM_EN_V << SDIO_SLC1_TX_CHECK_SUM_EN_S) +#define SDIO_SLC1_TX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC1_TX_CHECK_SUM_EN_S 17 +/** SDIO_SLC1_RX_CHECK_SUM_EN : R/W; bitpos: [18]; default: 0; + * Set 1 to enable check sum function during slave sending packets through dma + * channel1. + */ +#define SDIO_SLC1_RX_CHECK_SUM_EN (BIT(18)) +#define SDIO_SLC1_RX_CHECK_SUM_EN_M (SDIO_SLC1_RX_CHECK_SUM_EN_V << SDIO_SLC1_RX_CHECK_SUM_EN_S) +#define SDIO_SLC1_RX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC1_RX_CHECK_SUM_EN_S 18 +/** SDIO_HOST_INT_LEVEL_SEL : R/W; bitpos: [19]; default: 0; + * Set the polarity of interrupt generated to host: 0-low active, 1-high active. + */ +#define SDIO_HOST_INT_LEVEL_SEL (BIT(19)) +#define SDIO_HOST_INT_LEVEL_SEL_M (SDIO_HOST_INT_LEVEL_SEL_V << SDIO_HOST_INT_LEVEL_SEL_S) +#define SDIO_HOST_INT_LEVEL_SEL_V 0x00000001U +#define SDIO_HOST_INT_LEVEL_SEL_S 19 +/** SDIO_SDIO_CLK_EN : R/W; bitpos: [22]; default: 0; + * Sdio slave dma registers' clock gating enable bit: 0-the sdio slave dma registers' + * clock is on during apb operation, 1- the sdio slave dma registers' clock is always + * on. + */ +#define SDIO_SDIO_CLK_EN (BIT(22)) +#define SDIO_SDIO_CLK_EN_M (SDIO_SDIO_CLK_EN_V << SDIO_SDIO_CLK_EN_S) +#define SDIO_SDIO_CLK_EN_V 0x00000001U +#define SDIO_SDIO_CLK_EN_S 22 + +/** SDIO_SLC_SLC0_STATE0_REG register + * Sdio slave DMA channel0 status register. + */ +#define SDIO_SLC_SLC0_STATE0_REG (DR_REG_SLC_BASE + 0x74) +/** SDIO_SLC0_STATE0 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current receiving descriptor address, [20:19] receiving descriptor fsm + * state, [23:21] receiving fsm state, [30:24] the count value of data received in + * txfifo + */ +#define SDIO_SLC0_STATE0 0xFFFFFFFFU +#define SDIO_SLC0_STATE0_M (SDIO_SLC0_STATE0_V << SDIO_SLC0_STATE0_S) +#define SDIO_SLC0_STATE0_V 0xFFFFFFFFU +#define SDIO_SLC0_STATE0_S 0 + +/** SDIO_SLC_SLC0_STATE1_REG register + * Sdio slave DMA channel0 status1 register. + */ +#define SDIO_SLC_SLC0_STATE1_REG (DR_REG_SLC_BASE + 0x78) +/** SDIO_SLC0_STATE1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current sending descriptor address, [20:19] sending descriptor fsm + * state, [23:21] sending fsm state, [30:24] the count value of data to be sent in + * rxfifo + */ +#define SDIO_SLC0_STATE1 0xFFFFFFFFU +#define SDIO_SLC0_STATE1_M (SDIO_SLC0_STATE1_V << SDIO_SLC0_STATE1_S) +#define SDIO_SLC0_STATE1_V 0xFFFFFFFFU +#define SDIO_SLC0_STATE1_S 0 + +/** SDIO_SLC_SLC1_STATE0_REG register + * Sdio slave DMA channel1 status register. + */ +#define SDIO_SLC_SLC1_STATE0_REG (DR_REG_SLC_BASE + 0x7c) +/** SDIO_SLC1_STATE0 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current receiving descriptor address, [20:19] receiving descriptor fsm + * state, [23:21] receiving fsm state, [30:24] the count value of data received in + * txfifo + */ +#define SDIO_SLC1_STATE0 0xFFFFFFFFU +#define SDIO_SLC1_STATE0_M (SDIO_SLC1_STATE0_V << SDIO_SLC1_STATE0_S) +#define SDIO_SLC1_STATE0_V 0xFFFFFFFFU +#define SDIO_SLC1_STATE0_S 0 + +/** SDIO_SLC_SLC1_STATE1_REG register + * Sdio slave DMA channel1 status1 register. + */ +#define SDIO_SLC_SLC1_STATE1_REG (DR_REG_SLC_BASE + 0x80) +/** SDIO_SLC1_STATE1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current sending descriptor address, [20:19] sending descriptor fsm + * state, [23:21] sending fsm state, [30:24] the count value of data to be sent in + * rxfifo + */ +#define SDIO_SLC1_STATE1 0xFFFFFFFFU +#define SDIO_SLC1_STATE1_M (SDIO_SLC1_STATE1_V << SDIO_SLC1_STATE1_S) +#define SDIO_SLC1_STATE1_V 0xFFFFFFFFU +#define SDIO_SLC1_STATE1_S 0 + +/** SDIO_SLC_BRIDGE_CONF_REG register + * Sdio slave DMA bridge configuration register. + */ +#define SDIO_SLC_BRIDGE_CONF_REG (DR_REG_SLC_BASE + 0x84) +/** SDIO_SLC_TXEOF_ENA : R/W; bitpos: [5:0]; default: 32; + * Configure the end-of-frame address of receiving packet. The priority from high to + * low is: if txeof_ena[0] is 1, end-of-frame address is 0xfff, if txeof_ena[1] is 1, + * end-of-frame address is 0x1fff, if txeof_ena[2] is 1, end-of-frame address is + * 0x3fff, if txeof_ena[3] is 1, end-of-frame address is 0x7fff, if txeof_ena[4] is 1, + * end-of-frame address is 0xffff, if txeof_ena[5] is 1, end-of-frame address is + * 0x1f7ff. Make sure the end-of-frame address is within the address range set by + * fifo_map_ena, otherwise the packet will be transferred without end-of-frame flag, + * which can cause unpredictable consequence. + */ +#define SDIO_SLC_TXEOF_ENA 0x0000003FU +#define SDIO_SLC_TXEOF_ENA_M (SDIO_SLC_TXEOF_ENA_V << SDIO_SLC_TXEOF_ENA_S) +#define SDIO_SLC_TXEOF_ENA_V 0x0000003FU +#define SDIO_SLC_TXEOF_ENA_S 0 +/** SDIO_SLC_FIFO_MAP_ENA : R/W; bitpos: [11:8]; default: 7; + * Configure the address range allocated to transfer packets using SDIO func1 and + * func2. The address range is from 0x400 to 0-0x3fff, 1-0x7fff, 3-0xffff, 7-0x1ffff, + * others-not allowed. + */ +#define SDIO_SLC_FIFO_MAP_ENA 0x0000000FU +#define SDIO_SLC_FIFO_MAP_ENA_M (SDIO_SLC_FIFO_MAP_ENA_V << SDIO_SLC_FIFO_MAP_ENA_S) +#define SDIO_SLC_FIFO_MAP_ENA_V 0x0000000FU +#define SDIO_SLC_FIFO_MAP_ENA_S 8 +/** SDIO_SLC0_TX_DUMMY_MODE : R/W; bitpos: [12]; default: 1; + * Set 1 not to transfer check sum data into memory through dma channel0. + */ +#define SDIO_SLC0_TX_DUMMY_MODE (BIT(12)) +#define SDIO_SLC0_TX_DUMMY_MODE_M (SDIO_SLC0_TX_DUMMY_MODE_V << SDIO_SLC0_TX_DUMMY_MODE_S) +#define SDIO_SLC0_TX_DUMMY_MODE_V 0x00000001U +#define SDIO_SLC0_TX_DUMMY_MODE_S 12 +/** SDIO_SLC_HDA_MAP_128K : R/W; bitpos: [13]; default: 1; + * If hda_map_128k is 0, map high 4 bit address to hda_4msb. When hda_map_128k is 1, + * if hda_word_en (slchost_conf12[0]) is 0, map high 4 bit address to {hda_4msb[3:1], + * addr_ext_func[16]}. Else if hda_word_en is 1, map high 4 bit address to + * {hda_4msb[3:1], addr_ext_func[14]}. + */ +#define SDIO_SLC_HDA_MAP_128K (BIT(13)) +#define SDIO_SLC_HDA_MAP_128K_M (SDIO_SLC_HDA_MAP_128K_V << SDIO_SLC_HDA_MAP_128K_S) +#define SDIO_SLC_HDA_MAP_128K_V 0x00000001U +#define SDIO_SLC_HDA_MAP_128K_S 13 +/** SDIO_SLC1_TX_DUMMY_MODE : R/W; bitpos: [14]; default: 1; + * Set 1 not to transfer check sum data into memory through dma channel1. + */ +#define SDIO_SLC1_TX_DUMMY_MODE (BIT(14)) +#define SDIO_SLC1_TX_DUMMY_MODE_M (SDIO_SLC1_TX_DUMMY_MODE_V << SDIO_SLC1_TX_DUMMY_MODE_S) +#define SDIO_SLC1_TX_DUMMY_MODE_V 0x00000001U +#define SDIO_SLC1_TX_DUMMY_MODE_S 14 +/** SDIO_SLC_TX_PUSH_IDLE_NUM : R/W; bitpos: [31:16]; default: 10; + * reserved + */ +#define SDIO_SLC_TX_PUSH_IDLE_NUM 0x0000FFFFU +#define SDIO_SLC_TX_PUSH_IDLE_NUM_M (SDIO_SLC_TX_PUSH_IDLE_NUM_V << SDIO_SLC_TX_PUSH_IDLE_NUM_S) +#define SDIO_SLC_TX_PUSH_IDLE_NUM_V 0x0000FFFFU +#define SDIO_SLC_TX_PUSH_IDLE_NUM_S 16 + +/** SDIO_SLC_SLC0_TO_EOF_DES_ADDR_REG register + * Sdio slave DMA channel0 start address of sending linked list register. + */ +#define SDIO_SLC_SLC0_TO_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x88) +/** SDIO_SLC0_TO_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last sent packet through dma channel0. + */ +#define SDIO_SLC0_TO_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_DES_ADDR_M (SDIO_SLC0_TO_EOF_DES_ADDR_V << SDIO_SLC0_TO_EOF_DES_ADDR_S) +#define SDIO_SLC0_TO_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_SLC0_TX_EOF_DES_ADDR_REG register + * Sdio slave DMA channel0 receiving packet status register. + */ +#define SDIO_SLC_SLC0_TX_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x8c) +/** SDIO_SLC0_TX_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully received packet through dma + * channel0. + */ +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_M (SDIO_SLC0_TX_SUC_EOF_DES_ADDR_V << SDIO_SLC0_TX_SUC_EOF_DES_ADDR_S) +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_SLC0_TO_EOF_BFR_DES_ADDR_REG register + * Sdio slave DMA channel0 start address of sending linked list register. + */ +#define SDIO_SLC_SLC0_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SLC_BASE + 0x90) +/** SDIO_SLC0_TO_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully sent buffer packet through dma + * channel0. + */ +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_M (SDIO_SLC0_TO_EOF_BFR_DES_ADDR_V << SDIO_SLC0_TO_EOF_BFR_DES_ADDR_S) +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_S 0 + +/** SDIO_SLC_SLC1_TO_EOF_DES_ADDR_REG register + * Sdio slave DMA channel1 start address of sending linked list register. + */ +#define SDIO_SLC_SLC1_TO_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x94) +/** SDIO_SLC1_TO_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last sent packet through dma channel1. + */ +#define SDIO_SLC1_TO_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_DES_ADDR_M (SDIO_SLC1_TO_EOF_DES_ADDR_V << SDIO_SLC1_TO_EOF_DES_ADDR_S) +#define SDIO_SLC1_TO_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_SLC1_TX_EOF_DES_ADDR_REG register + * Sdio slave DMA channel1 receiving packet status register. + */ +#define SDIO_SLC_SLC1_TX_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x98) +/** SDIO_SLC1_TX_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully received packet through dma + * channel1. + */ +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_M (SDIO_SLC1_TX_SUC_EOF_DES_ADDR_V << SDIO_SLC1_TX_SUC_EOF_DES_ADDR_S) +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_SLC1_TO_EOF_BFR_DES_ADDR_REG register + * Sdio slave DMA channel1 start address of sending linked list register. + */ +#define SDIO_SLC_SLC1_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SLC_BASE + 0x9c) +/** SDIO_SLC1_TO_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully sent buffer packet through dma + * channel1. + */ +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_M (SDIO_SLC1_TO_EOF_BFR_DES_ADDR_V << SDIO_SLC1_TO_EOF_BFR_DES_ADDR_S) +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_S 0 + +/** SDIO_SLC_AHB_TEST_REG register + * Sdio slave AHB test register. + */ +#define SDIO_SLC_AHB_TEST_REG (DR_REG_SLC_BASE + 0xa0) +/** SDIO_SLC_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; + * set bit2 to 1 to enable sdio slave ahb test. + */ +#define SDIO_SLC_AHB_TESTMODE 0x00000007U +#define SDIO_SLC_AHB_TESTMODE_M (SDIO_SLC_AHB_TESTMODE_V << SDIO_SLC_AHB_TESTMODE_S) +#define SDIO_SLC_AHB_TESTMODE_V 0x00000007U +#define SDIO_SLC_AHB_TESTMODE_S 0 +/** SDIO_SLC_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; + * Configure AHB test address. + */ +#define SDIO_SLC_AHB_TESTADDR 0x00000003U +#define SDIO_SLC_AHB_TESTADDR_M (SDIO_SLC_AHB_TESTADDR_V << SDIO_SLC_AHB_TESTADDR_S) +#define SDIO_SLC_AHB_TESTADDR_V 0x00000003U +#define SDIO_SLC_AHB_TESTADDR_S 4 + +/** SDIO_SLC_SDIO_ST_REG register + * Sdio slave function status register. + */ +#define SDIO_SLC_SDIO_ST_REG (DR_REG_SLC_BASE + 0xa4) +/** SDIO_CMD_ST : RO; bitpos: [2:0]; default: 0; + * The sdio command fsm state. + */ +#define SDIO_CMD_ST 0x00000007U +#define SDIO_CMD_ST_M (SDIO_CMD_ST_V << SDIO_CMD_ST_S) +#define SDIO_CMD_ST_V 0x00000007U +#define SDIO_CMD_ST_S 0 +/** SDIO_FUNC_ST : RO; bitpos: [7:4]; default: 0; + * The sdio cmd52/53 function fsm state. + */ +#define SDIO_FUNC_ST 0x0000000FU +#define SDIO_FUNC_ST_M (SDIO_FUNC_ST_V << SDIO_FUNC_ST_S) +#define SDIO_FUNC_ST_V 0x0000000FU +#define SDIO_FUNC_ST_S 4 +/** SDIO_SDIO_WAKEUP : RO; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SDIO_WAKEUP (BIT(8)) +#define SDIO_SDIO_WAKEUP_M (SDIO_SDIO_WAKEUP_V << SDIO_SDIO_WAKEUP_S) +#define SDIO_SDIO_WAKEUP_V 0x00000001U +#define SDIO_SDIO_WAKEUP_S 8 +/** SDIO_BUS_ST : RO; bitpos: [14:12]; default: 0; + * The sdio bus fsm state. + */ +#define SDIO_BUS_ST 0x00000007U +#define SDIO_BUS_ST_M (SDIO_BUS_ST_V << SDIO_BUS_ST_S) +#define SDIO_BUS_ST_V 0x00000007U +#define SDIO_BUS_ST_S 12 +/** SDIO_FUNC1_ACC_STATE : RO; bitpos: [20:16]; default: 0; + * The sdio func1 fsm state. + */ +#define SDIO_FUNC1_ACC_STATE 0x0000001FU +#define SDIO_FUNC1_ACC_STATE_M (SDIO_FUNC1_ACC_STATE_V << SDIO_FUNC1_ACC_STATE_S) +#define SDIO_FUNC1_ACC_STATE_V 0x0000001FU +#define SDIO_FUNC1_ACC_STATE_S 16 +/** SDIO_FUNC2_ACC_STATE : RO; bitpos: [28:24]; default: 0; + * The sdio func2 fsm state. + */ +#define SDIO_FUNC2_ACC_STATE 0x0000001FU +#define SDIO_FUNC2_ACC_STATE_M (SDIO_FUNC2_ACC_STATE_V << SDIO_FUNC2_ACC_STATE_S) +#define SDIO_FUNC2_ACC_STATE_V 0x0000001FU +#define SDIO_FUNC2_ACC_STATE_S 24 + +/** SDIO_SLC_RX_DSCR_CONF_REG register + * Sdio slave sending descriptor configuration register. + */ +#define SDIO_SLC_RX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0xa8) +/** SDIO_SLC0_TOKEN_NO_REPLACE : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN_NO_REPLACE (BIT(0)) +#define SDIO_SLC0_TOKEN_NO_REPLACE_M (SDIO_SLC0_TOKEN_NO_REPLACE_V << SDIO_SLC0_TOKEN_NO_REPLACE_S) +#define SDIO_SLC0_TOKEN_NO_REPLACE_V 0x00000001U +#define SDIO_SLC0_TOKEN_NO_REPLACE_S 0 +/** SDIO_SLC0_INFOR_NO_REPLACE : R/W; bitpos: [1]; default: 1; + * reserved + */ +#define SDIO_SLC0_INFOR_NO_REPLACE (BIT(1)) +#define SDIO_SLC0_INFOR_NO_REPLACE_M (SDIO_SLC0_INFOR_NO_REPLACE_V << SDIO_SLC0_INFOR_NO_REPLACE_S) +#define SDIO_SLC0_INFOR_NO_REPLACE_V 0x00000001U +#define SDIO_SLC0_INFOR_NO_REPLACE_S 1 +/** SDIO_SLC0_RX_FILL_MODE : R/W; bitpos: [2]; default: 0; + * slc0 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ +#define SDIO_SLC0_RX_FILL_MODE (BIT(2)) +#define SDIO_SLC0_RX_FILL_MODE_M (SDIO_SLC0_RX_FILL_MODE_V << SDIO_SLC0_RX_FILL_MODE_S) +#define SDIO_SLC0_RX_FILL_MODE_V 0x00000001U +#define SDIO_SLC0_RX_FILL_MODE_S 2 +/** SDIO_SLC0_RX_EOF_MODE : R/W; bitpos: [3]; default: 1; + * 0-slc0 rx_push_eof, 1-slc0 rx_pop_eof + */ +#define SDIO_SLC0_RX_EOF_MODE (BIT(3)) +#define SDIO_SLC0_RX_EOF_MODE_M (SDIO_SLC0_RX_EOF_MODE_V << SDIO_SLC0_RX_EOF_MODE_S) +#define SDIO_SLC0_RX_EOF_MODE_V 0x00000001U +#define SDIO_SLC0_RX_EOF_MODE_S 3 +/** SDIO_SLC0_RX_FILL_EN : R/W; bitpos: [4]; default: 1; + * reserved + */ +#define SDIO_SLC0_RX_FILL_EN (BIT(4)) +#define SDIO_SLC0_RX_FILL_EN_M (SDIO_SLC0_RX_FILL_EN_V << SDIO_SLC0_RX_FILL_EN_S) +#define SDIO_SLC0_RX_FILL_EN_V 0x00000001U +#define SDIO_SLC0_RX_FILL_EN_S 4 +/** SDIO_SLC0_RD_RETRY_THRESHOLD : R/W; bitpos: [15:5]; default: 128; + * reserved + */ +#define SDIO_SLC0_RD_RETRY_THRESHOLD 0x000007FFU +#define SDIO_SLC0_RD_RETRY_THRESHOLD_M (SDIO_SLC0_RD_RETRY_THRESHOLD_V << SDIO_SLC0_RD_RETRY_THRESHOLD_S) +#define SDIO_SLC0_RD_RETRY_THRESHOLD_V 0x000007FFU +#define SDIO_SLC0_RD_RETRY_THRESHOLD_S 5 +/** SDIO_SLC1_TOKEN_NO_REPLACE : R/W; bitpos: [16]; default: 1; + * reserved + */ +#define SDIO_SLC1_TOKEN_NO_REPLACE (BIT(16)) +#define SDIO_SLC1_TOKEN_NO_REPLACE_M (SDIO_SLC1_TOKEN_NO_REPLACE_V << SDIO_SLC1_TOKEN_NO_REPLACE_S) +#define SDIO_SLC1_TOKEN_NO_REPLACE_V 0x00000001U +#define SDIO_SLC1_TOKEN_NO_REPLACE_S 16 +/** SDIO_SLC1_INFOR_NO_REPLACE : R/W; bitpos: [17]; default: 1; + * reserved + */ +#define SDIO_SLC1_INFOR_NO_REPLACE (BIT(17)) +#define SDIO_SLC1_INFOR_NO_REPLACE_M (SDIO_SLC1_INFOR_NO_REPLACE_V << SDIO_SLC1_INFOR_NO_REPLACE_S) +#define SDIO_SLC1_INFOR_NO_REPLACE_V 0x00000001U +#define SDIO_SLC1_INFOR_NO_REPLACE_S 17 +/** SDIO_SLC1_RX_FILL_MODE : R/W; bitpos: [18]; default: 0; + * slc1 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ +#define SDIO_SLC1_RX_FILL_MODE (BIT(18)) +#define SDIO_SLC1_RX_FILL_MODE_M (SDIO_SLC1_RX_FILL_MODE_V << SDIO_SLC1_RX_FILL_MODE_S) +#define SDIO_SLC1_RX_FILL_MODE_V 0x00000001U +#define SDIO_SLC1_RX_FILL_MODE_S 18 +/** SDIO_SLC1_RX_EOF_MODE : R/W; bitpos: [19]; default: 1; + * 0-slc1 rx_push_eof, 1-slc1 rx_pop_eof + */ +#define SDIO_SLC1_RX_EOF_MODE (BIT(19)) +#define SDIO_SLC1_RX_EOF_MODE_M (SDIO_SLC1_RX_EOF_MODE_V << SDIO_SLC1_RX_EOF_MODE_S) +#define SDIO_SLC1_RX_EOF_MODE_V 0x00000001U +#define SDIO_SLC1_RX_EOF_MODE_S 19 +/** SDIO_SLC1_RX_FILL_EN : R/W; bitpos: [20]; default: 1; + * reserved + */ +#define SDIO_SLC1_RX_FILL_EN (BIT(20)) +#define SDIO_SLC1_RX_FILL_EN_M (SDIO_SLC1_RX_FILL_EN_V << SDIO_SLC1_RX_FILL_EN_S) +#define SDIO_SLC1_RX_FILL_EN_V 0x00000001U +#define SDIO_SLC1_RX_FILL_EN_S 20 +/** SDIO_SLC1_RD_RETRY_THRESHOLD : R/W; bitpos: [31:21]; default: 128; + * reserved + */ +#define SDIO_SLC1_RD_RETRY_THRESHOLD 0x000007FFU +#define SDIO_SLC1_RD_RETRY_THRESHOLD_M (SDIO_SLC1_RD_RETRY_THRESHOLD_V << SDIO_SLC1_RD_RETRY_THRESHOLD_S) +#define SDIO_SLC1_RD_RETRY_THRESHOLD_V 0x000007FFU +#define SDIO_SLC1_RD_RETRY_THRESHOLD_S 21 + +/** SDIO_SLC_SLC0_TXLINK_DSCR_REG register + * ******* Description *********** + */ +#define SDIO_SLC_SLC0_TXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xac) +/** SDIO_SLC0_TXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_M (SDIO_SLC0_TXLINK_DSCR_V << SDIO_SLC0_TXLINK_DSCR_S) +#define SDIO_SLC0_TXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_S 0 + +/** SDIO_SLC_SLC0_TXLINK_DSCR_BF0_REG register + * ******* Description *********** + */ +#define SDIO_SLC_SLC0_TXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xb0) +/** SDIO_SLC0_TXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF0_M (SDIO_SLC0_TXLINK_DSCR_BF0_V << SDIO_SLC0_TXLINK_DSCR_BF0_S) +#define SDIO_SLC0_TXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC_SLC0_TXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC_SLC0_TXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xb4) +/** SDIO_SLC0_TXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF1_M (SDIO_SLC0_TXLINK_DSCR_BF1_V << SDIO_SLC0_TXLINK_DSCR_BF1_S) +#define SDIO_SLC0_TXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC_SLC0_RXLINK_DSCR_REG register + * ******* Description *********** + */ +#define SDIO_SLC_SLC0_RXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xb8) +/** SDIO_SLC0_RXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * the third word of slc0 link descriptor, or known as the next descriptor address + */ +#define SDIO_SLC0_RXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_M (SDIO_SLC0_RXLINK_DSCR_V << SDIO_SLC0_RXLINK_DSCR_S) +#define SDIO_SLC0_RXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_S 0 + +/** SDIO_SLC_SLC0_RXLINK_DSCR_BF0_REG register + * ******* Description *********** + */ +#define SDIO_SLC_SLC0_RXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xbc) +/** SDIO_SLC0_RXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF0_M (SDIO_SLC0_RXLINK_DSCR_BF0_V << SDIO_SLC0_RXLINK_DSCR_BF0_S) +#define SDIO_SLC0_RXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC_SLC0_RXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC_SLC0_RXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xc0) +/** SDIO_SLC0_RXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF1_M (SDIO_SLC0_RXLINK_DSCR_BF1_V << SDIO_SLC0_RXLINK_DSCR_BF1_S) +#define SDIO_SLC0_RXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC_SLC1_TXLINK_DSCR_REG register + * reserved + */ +#define SDIO_SLC_SLC1_TXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xc4) +/** SDIO_SLC1_TXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_M (SDIO_SLC1_TXLINK_DSCR_V << SDIO_SLC1_TXLINK_DSCR_S) +#define SDIO_SLC1_TXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_S 0 + +/** SDIO_SLC_SLC1_TXLINK_DSCR_BF0_REG register + * reserved + */ +#define SDIO_SLC_SLC1_TXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xc8) +/** SDIO_SLC1_TXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF0_M (SDIO_SLC1_TXLINK_DSCR_BF0_V << SDIO_SLC1_TXLINK_DSCR_BF0_S) +#define SDIO_SLC1_TXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC_SLC1_TXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC_SLC1_TXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xcc) +/** SDIO_SLC1_TXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF1_M (SDIO_SLC1_TXLINK_DSCR_BF1_V << SDIO_SLC1_TXLINK_DSCR_BF1_S) +#define SDIO_SLC1_TXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC_SLC1_RXLINK_DSCR_REG register + * ******* Description *********** + */ +#define SDIO_SLC_SLC1_RXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xd0) +/** SDIO_SLC1_RXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * the third word of slc1 link descriptor, or known as the next descriptor address + */ +#define SDIO_SLC1_RXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_M (SDIO_SLC1_RXLINK_DSCR_V << SDIO_SLC1_RXLINK_DSCR_S) +#define SDIO_SLC1_RXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_S 0 + +/** SDIO_SLC_SLC1_RXLINK_DSCR_BF0_REG register + * ******* Description *********** + */ +#define SDIO_SLC_SLC1_RXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xd4) +/** SDIO_SLC1_RXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF0_M (SDIO_SLC1_RXLINK_DSCR_BF0_V << SDIO_SLC1_RXLINK_DSCR_BF0_S) +#define SDIO_SLC1_RXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC_SLC1_RXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC_SLC1_RXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xd8) +/** SDIO_SLC1_RXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF1_M (SDIO_SLC1_RXLINK_DSCR_BF1_V << SDIO_SLC1_RXLINK_DSCR_BF1_S) +#define SDIO_SLC1_RXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC_SLC0_TX_ERREOF_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC_SLC0_TX_ERREOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0xdc) +/** SDIO_SLC0_TX_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_M (SDIO_SLC0_TX_ERR_EOF_DES_ADDR_V << SDIO_SLC0_TX_ERR_EOF_DES_ADDR_S) +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_SLC1_TX_ERREOF_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC_SLC1_TX_ERREOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0xe0) +/** SDIO_SLC1_TX_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_M (SDIO_SLC1_TX_ERR_EOF_DES_ADDR_V << SDIO_SLC1_TX_ERR_EOF_DES_ADDR_S) +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_TOKEN_LAT_REG register + * reserved + */ +#define SDIO_SLC_TOKEN_LAT_REG (DR_REG_SLC_BASE + 0xe4) +/** SDIO_SLC0_TOKEN : RO; bitpos: [11:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN 0x00000FFFU +#define SDIO_SLC0_TOKEN_M (SDIO_SLC0_TOKEN_V << SDIO_SLC0_TOKEN_S) +#define SDIO_SLC0_TOKEN_V 0x00000FFFU +#define SDIO_SLC0_TOKEN_S 0 +/** SDIO_SLC1_TOKEN : RO; bitpos: [27:16]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN 0x00000FFFU +#define SDIO_SLC1_TOKEN_M (SDIO_SLC1_TOKEN_V << SDIO_SLC1_TOKEN_S) +#define SDIO_SLC1_TOKEN_V 0x00000FFFU +#define SDIO_SLC1_TOKEN_S 16 + +/** SDIO_SLC_TX_DSCR_CONF_REG register + * reserved + */ +#define SDIO_SLC_TX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0xe8) +/** SDIO_SLC_WR_RETRY_THRESHOLD : R/W; bitpos: [10:0]; default: 128; + * reserved + */ +#define SDIO_SLC_WR_RETRY_THRESHOLD 0x000007FFU +#define SDIO_SLC_WR_RETRY_THRESHOLD_M (SDIO_SLC_WR_RETRY_THRESHOLD_V << SDIO_SLC_WR_RETRY_THRESHOLD_S) +#define SDIO_SLC_WR_RETRY_THRESHOLD_V 0x000007FFU +#define SDIO_SLC_WR_RETRY_THRESHOLD_S 0 + +/** SDIO_SLC_CMD_INFOR0_REG register + * reserved + */ +#define SDIO_SLC_CMD_INFOR0_REG (DR_REG_SLC_BASE + 0xec) +/** SDIO_CMD_CONTENT0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_CMD_CONTENT0 0xFFFFFFFFU +#define SDIO_CMD_CONTENT0_M (SDIO_CMD_CONTENT0_V << SDIO_CMD_CONTENT0_S) +#define SDIO_CMD_CONTENT0_V 0xFFFFFFFFU +#define SDIO_CMD_CONTENT0_S 0 + +/** SDIO_SLC_CMD_INFOR1_REG register + * reserved + */ +#define SDIO_SLC_CMD_INFOR1_REG (DR_REG_SLC_BASE + 0xf0) +/** SDIO_CMD_CONTENT1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_CMD_CONTENT1 0xFFFFFFFFU +#define SDIO_CMD_CONTENT1_M (SDIO_CMD_CONTENT1_V << SDIO_CMD_CONTENT1_S) +#define SDIO_CMD_CONTENT1_V 0xFFFFFFFFU +#define SDIO_CMD_CONTENT1_S 0 + +/** SDIO_SLC_SLC0_LEN_CONF_REG register + * reserved + */ +#define SDIO_SLC_SLC0_LEN_CONF_REG (DR_REG_SLC_BASE + 0xf4) +/** SDIO_SLC0_LEN_WDATA : WT; bitpos: [19:0]; default: 0; + * The packet length sent by dma channel0. + */ +#define SDIO_SLC0_LEN_WDATA 0x000FFFFFU +#define SDIO_SLC0_LEN_WDATA_M (SDIO_SLC0_LEN_WDATA_V << SDIO_SLC0_LEN_WDATA_S) +#define SDIO_SLC0_LEN_WDATA_V 0x000FFFFFU +#define SDIO_SLC0_LEN_WDATA_S 0 +/** SDIO_SLC0_LEN_WR : WT; bitpos: [20]; default: 0; + * Set this bit to set SLC0_LEN as SDIO_SLC0_LEN_WDATA. + */ +#define SDIO_SLC0_LEN_WR (BIT(20)) +#define SDIO_SLC0_LEN_WR_M (SDIO_SLC0_LEN_WR_V << SDIO_SLC0_LEN_WR_S) +#define SDIO_SLC0_LEN_WR_V 0x00000001U +#define SDIO_SLC0_LEN_WR_S 20 +/** SDIO_SLC0_LEN_INC : WT; bitpos: [21]; default: 0; + * Set this bit to add 1 to SLC0_LEN. + */ +#define SDIO_SLC0_LEN_INC (BIT(21)) +#define SDIO_SLC0_LEN_INC_M (SDIO_SLC0_LEN_INC_V << SDIO_SLC0_LEN_INC_S) +#define SDIO_SLC0_LEN_INC_V 0x00000001U +#define SDIO_SLC0_LEN_INC_S 21 +/** SDIO_SLC0_LEN_INC_MORE : WT; bitpos: [22]; default: 0; + * Set this bit to add the value of SDIO_SLC0_LEN_WDATA to SLC0_LEN. + */ +#define SDIO_SLC0_LEN_INC_MORE (BIT(22)) +#define SDIO_SLC0_LEN_INC_MORE_M (SDIO_SLC0_LEN_INC_MORE_V << SDIO_SLC0_LEN_INC_MORE_S) +#define SDIO_SLC0_LEN_INC_MORE_V 0x00000001U +#define SDIO_SLC0_LEN_INC_MORE_S 22 +/** SDIO_SLC0_RX_PACKET_LOAD_EN : WT; bitpos: [23]; default: 0; + * Write 1 to stitch new linked lists to current linked lists when dma channel0 + * sending packets. + */ +#define SDIO_SLC0_RX_PACKET_LOAD_EN (BIT(23)) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_M (SDIO_SLC0_RX_PACKET_LOAD_EN_V << SDIO_SLC0_RX_PACKET_LOAD_EN_S) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_V 0x00000001U +#define SDIO_SLC0_RX_PACKET_LOAD_EN_S 23 +/** SDIO_SLC0_TX_PACKET_LOAD_EN : WT; bitpos: [24]; default: 0; + * Write 1 to stitch new linked lists to current linked lists when dma channel0 + * receiving packets. + */ +#define SDIO_SLC0_TX_PACKET_LOAD_EN (BIT(24)) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_M (SDIO_SLC0_TX_PACKET_LOAD_EN_V << SDIO_SLC0_TX_PACKET_LOAD_EN_S) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_V 0x00000001U +#define SDIO_SLC0_TX_PACKET_LOAD_EN_S 24 +/** SDIO_SLC0_RX_GET_USED_DSCR : WT; bitpos: [25]; default: 0; + * Write 1 to get the current descriptor address when dma channel0 sending packets. + */ +#define SDIO_SLC0_RX_GET_USED_DSCR (BIT(25)) +#define SDIO_SLC0_RX_GET_USED_DSCR_M (SDIO_SLC0_RX_GET_USED_DSCR_V << SDIO_SLC0_RX_GET_USED_DSCR_S) +#define SDIO_SLC0_RX_GET_USED_DSCR_V 0x00000001U +#define SDIO_SLC0_RX_GET_USED_DSCR_S 25 +/** SDIO_SLC0_TX_GET_USED_DSCR : WT; bitpos: [26]; default: 0; + * Write 1 to get the current descriptor address when dma channel0 receiving packets. + */ +#define SDIO_SLC0_TX_GET_USED_DSCR (BIT(26)) +#define SDIO_SLC0_TX_GET_USED_DSCR_M (SDIO_SLC0_TX_GET_USED_DSCR_V << SDIO_SLC0_TX_GET_USED_DSCR_S) +#define SDIO_SLC0_TX_GET_USED_DSCR_V 0x00000001U +#define SDIO_SLC0_TX_GET_USED_DSCR_S 26 +/** SDIO_SLC0_RX_NEW_PKT_IND : RO; bitpos: [27]; default: 0; + * Represents a new packet is sent by dma channel0. + */ +#define SDIO_SLC0_RX_NEW_PKT_IND (BIT(27)) +#define SDIO_SLC0_RX_NEW_PKT_IND_M (SDIO_SLC0_RX_NEW_PKT_IND_V << SDIO_SLC0_RX_NEW_PKT_IND_S) +#define SDIO_SLC0_RX_NEW_PKT_IND_V 0x00000001U +#define SDIO_SLC0_RX_NEW_PKT_IND_S 27 +/** SDIO_SLC0_TX_NEW_PKT_IND : RO; bitpos: [28]; default: 1; + * Represents a new packet is received by dma channel0. + */ +#define SDIO_SLC0_TX_NEW_PKT_IND (BIT(28)) +#define SDIO_SLC0_TX_NEW_PKT_IND_M (SDIO_SLC0_TX_NEW_PKT_IND_V << SDIO_SLC0_TX_NEW_PKT_IND_S) +#define SDIO_SLC0_TX_NEW_PKT_IND_V 0x00000001U +#define SDIO_SLC0_TX_NEW_PKT_IND_S 28 +/** SDIO_SLC0_RX_PACKET_LOAD_EN_ST : R/WTC/SC; bitpos: [29]; default: 0; + * Represents whether the dma channel0 can be stitched to new linked lists when + * sending packets. 0- allowed, 1- not allowed. + */ +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST (BIT(29)) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_M (SDIO_SLC0_RX_PACKET_LOAD_EN_ST_V << SDIO_SLC0_RX_PACKET_LOAD_EN_ST_S) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_V 0x00000001U +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_S 29 +/** SDIO_SLC0_TX_PACKET_LOAD_EN_ST : R/WTC/SC; bitpos: [30]; default: 0; + * Represents whether the dma channel0 can be stitched to new linked lists when + * receiving packets. 0- allowed, 1- not allowed. + */ +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST (BIT(30)) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_M (SDIO_SLC0_TX_PACKET_LOAD_EN_ST_V << SDIO_SLC0_TX_PACKET_LOAD_EN_ST_S) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_V 0x00000001U +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_S 30 + +/** SDIO_SLC_SLC0_LENGTH_REG register + * reserved + */ +#define SDIO_SLC_SLC0_LENGTH_REG (DR_REG_SLC_BASE + 0xf8) +/** SDIO_SLC0_LEN : RO; bitpos: [19:0]; default: 0; + * Indicates the paclet length sent by the slave through dma channel0. + */ +#define SDIO_SLC0_LEN 0x000FFFFFU +#define SDIO_SLC0_LEN_M (SDIO_SLC0_LEN_V << SDIO_SLC0_LEN_S) +#define SDIO_SLC0_LEN_V 0x000FFFFFU +#define SDIO_SLC0_LEN_S 0 + +/** SDIO_SLC_SLC0_TXPKT_H_DSCR_REG register + * Sdio slave DMA channel0 start address of receiving linked list register. + */ +#define SDIO_SLC_SLC0_TXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0xfc) +/** SDIO_SLC0_TX_PKT_H_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * Configure the start address of receiving linked list to be stitched to the current + * linked list of dma channel0. + */ +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_H_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_H_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_TXPKT_E_DSCR_REG register + * Sdio slave DMA channel0 end address of receiving linked list register. + */ +#define SDIO_SLC_SLC0_TXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0x100) +/** SDIO_SLC0_TX_PKT_E_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * Configure end address of receiving linked list to be stitched to the current linked + * list of dma channel0. + */ +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_E_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_E_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_RXPKT_H_DSCR_REG register + * Sdio slave DMA channel0 start address of sending linked list register. + */ +#define SDIO_SLC_SLC0_RXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0x104) +/** SDIO_SLC0_RX_PKT_H_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * Configure the start address of sending linked list to be stitched to the current + * linked list of dma channel0. + */ +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_H_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_H_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_RXPKT_E_DSCR_REG register + * Sdio slave DMA channel0 end address of sending linked list register. + */ +#define SDIO_SLC_SLC0_RXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0x108) +/** SDIO_SLC0_RX_PKT_E_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * Configure the end address of sending linked list to be stitched to the current + * linked list of dma channel0. + */ +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_E_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_E_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_TXPKTU_H_DSCR_REG register + * Sdio slave DMA channel0 start address of receiving linked list status register. + */ +#define SDIO_SLC_SLC0_TXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0x10c) +/** SDIO_SLC0_TX_PKT_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last received packet through dma + * channel0. + */ +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_START_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_START_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_TXPKTU_E_DSCR_REG register + * Sdio slave DMA channel0 end address of receiving linked list status register. + */ +#define SDIO_SLC_SLC0_TXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x110) +/** SDIO_SLC0_TX_PKT_END_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * The end address of the linked list of the last received packet through dma channel0. + */ +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_END_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_END_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_RXPKTU_H_DSCR_REG register + * Sdio slave DMA channel0 start address of sending linked list status register. + */ +#define SDIO_SLC_SLC0_RXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0x114) +/** SDIO_SLC0_RX_PKT_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last sent packet through dma channel0. + */ +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_START_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_START_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_RXPKTU_E_DSCR_REG register + * Sdio slave DMA channel0 end address of sending linked list status register. + */ +#define SDIO_SLC_SLC0_RXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x118) +/** SDIO_SLC0_RX_PKT_END_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * The end address of the linked list of the last sent packet through dma channel0. + */ +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_END_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_END_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_S 0 + +/** SDIO_SLC_SEQ_POSITION_REG register + * The position of receiving packet configuration register. + */ +#define SDIO_SLC_SEQ_POSITION_REG (DR_REG_SLC_BASE + 0x11c) +/** SDIO_SLC0_SEQ_POSITION : R/W; bitpos: [7:0]; default: 9; + * Configure the position of the receiving packet through dma channel0. + */ +#define SDIO_SLC0_SEQ_POSITION 0x000000FFU +#define SDIO_SLC0_SEQ_POSITION_M (SDIO_SLC0_SEQ_POSITION_V << SDIO_SLC0_SEQ_POSITION_S) +#define SDIO_SLC0_SEQ_POSITION_V 0x000000FFU +#define SDIO_SLC0_SEQ_POSITION_S 0 +/** SDIO_SLC1_SEQ_POSITION : R/W; bitpos: [15:8]; default: 5; + * Configure the position of the receiving packet through dma channel1. + */ +#define SDIO_SLC1_SEQ_POSITION 0x000000FFU +#define SDIO_SLC1_SEQ_POSITION_M (SDIO_SLC1_SEQ_POSITION_V << SDIO_SLC1_SEQ_POSITION_S) +#define SDIO_SLC1_SEQ_POSITION_V 0x000000FFU +#define SDIO_SLC1_SEQ_POSITION_S 8 + +/** SDIO_SLC_SLC0_DSCR_REC_CONF_REG register + * Sdio slave DMA sending linked list limit configuration register. + */ +#define SDIO_SLC_SLC0_DSCR_REC_CONF_REG (DR_REG_SLC_BASE + 0x120) +/** SDIO_SLC0_RX_DSCR_REC_LIM : R/W; bitpos: [9:0]; default: 1023; + * Configure the limit number of descriptors used to send one packet through dma + * channel0 in stitch mode. + */ +#define SDIO_SLC0_RX_DSCR_REC_LIM 0x000003FFU +#define SDIO_SLC0_RX_DSCR_REC_LIM_M (SDIO_SLC0_RX_DSCR_REC_LIM_V << SDIO_SLC0_RX_DSCR_REC_LIM_S) +#define SDIO_SLC0_RX_DSCR_REC_LIM_V 0x000003FFU +#define SDIO_SLC0_RX_DSCR_REC_LIM_S 0 + +/** SDIO_SLC_SDIO_CRC_ST0_REG register + * Sdio slave receiving packet data crc status register. + */ +#define SDIO_SLC_SDIO_CRC_ST0_REG (DR_REG_SLC_BASE + 0x124) +/** SDIO_DAT0_CRC_ERR_CNT : RO; bitpos: [7:0]; default: 0; + * The count value of received packet data crc errors on sd_data0 line. + */ +#define SDIO_DAT0_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT0_CRC_ERR_CNT_M (SDIO_DAT0_CRC_ERR_CNT_V << SDIO_DAT0_CRC_ERR_CNT_S) +#define SDIO_DAT0_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT0_CRC_ERR_CNT_S 0 +/** SDIO_DAT1_CRC_ERR_CNT : RO; bitpos: [15:8]; default: 0; + * The count value of received packet data crc errors on sd_data1 line. + */ +#define SDIO_DAT1_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT1_CRC_ERR_CNT_M (SDIO_DAT1_CRC_ERR_CNT_V << SDIO_DAT1_CRC_ERR_CNT_S) +#define SDIO_DAT1_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT1_CRC_ERR_CNT_S 8 +/** SDIO_DAT2_CRC_ERR_CNT : RO; bitpos: [23:16]; default: 0; + * The count value of received packet data crc errors on sd_data2 line. + */ +#define SDIO_DAT2_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT2_CRC_ERR_CNT_M (SDIO_DAT2_CRC_ERR_CNT_V << SDIO_DAT2_CRC_ERR_CNT_S) +#define SDIO_DAT2_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT2_CRC_ERR_CNT_S 16 +/** SDIO_DAT3_CRC_ERR_CNT : RO; bitpos: [31:24]; default: 0; + * The count value of received packet data crc errors on sd_data3 line. + */ +#define SDIO_DAT3_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT3_CRC_ERR_CNT_M (SDIO_DAT3_CRC_ERR_CNT_V << SDIO_DAT3_CRC_ERR_CNT_S) +#define SDIO_DAT3_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT3_CRC_ERR_CNT_S 24 + +/** SDIO_SLC_SDIO_CRC_ST1_REG register + * Sdio slave receiving command crc status register. + */ +#define SDIO_SLC_SDIO_CRC_ST1_REG (DR_REG_SLC_BASE + 0x128) +/** SDIO_CMD_CRC_ERR_CNT : RO; bitpos: [7:0]; default: 0; + * The count value of received command crc errors. + */ +#define SDIO_CMD_CRC_ERR_CNT 0x000000FFU +#define SDIO_CMD_CRC_ERR_CNT_M (SDIO_CMD_CRC_ERR_CNT_V << SDIO_CMD_CRC_ERR_CNT_S) +#define SDIO_CMD_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_CMD_CRC_ERR_CNT_S 0 +/** SDIO_ERR_CNT_CLR : R/W; bitpos: [31]; default: 0; + * Set 1 to clear the cmd_crc_err_cnt, dat0_crc_err_cnt, dat1_crc_err_cnt, + * dat2_crc_err_cnt and dat3_crc_err_cnt. + */ +#define SDIO_ERR_CNT_CLR (BIT(31)) +#define SDIO_ERR_CNT_CLR_M (SDIO_ERR_CNT_CLR_V << SDIO_ERR_CNT_CLR_S) +#define SDIO_ERR_CNT_CLR_V 0x00000001U +#define SDIO_ERR_CNT_CLR_S 31 + +/** SDIO_SLC_SLC0_EOF_START_DES_REG register + * Sdio slave DMA channel0 start address of sending linked list status register. + */ +#define SDIO_SLC_SLC0_EOF_START_DES_REG (DR_REG_SLC_BASE + 0x12c) +/** SDIO_SLC0_EOF_START_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last sent packet through dma channel0. + */ +#define SDIO_SLC0_EOF_START_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_EOF_START_DES_ADDR_M (SDIO_SLC0_EOF_START_DES_ADDR_V << SDIO_SLC0_EOF_START_DES_ADDR_S) +#define SDIO_SLC0_EOF_START_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_EOF_START_DES_ADDR_S 0 + +/** SDIO_SLC_SLC0_PUSH_DSCR_ADDR_REG register + * Sdio slave DMA channel0 address of sending linked list status register. + */ +#define SDIO_SLC_SLC0_PUSH_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x130) +/** SDIO_SLC0_RX_PUSH_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 gets a link descriptor, aligned with word + */ +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_M (SDIO_SLC0_RX_PUSH_DSCR_ADDR_V << SDIO_SLC0_RX_PUSH_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_DONE_DSCR_ADDR_REG register + * Sdio slave DMA channel0 address of sending linked list status register1. + */ +#define SDIO_SLC_SLC0_DONE_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x134) +/** SDIO_SLC0_RX_DONE_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 finishes reading data from one buffer, + * aligned with word + */ +#define SDIO_SLC0_RX_DONE_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_DONE_DSCR_ADDR_M (SDIO_SLC0_RX_DONE_DSCR_ADDR_V << SDIO_SLC0_RX_DONE_DSCR_ADDR_S) +#define SDIO_SLC0_RX_DONE_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_DONE_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_SUB_START_DES_REG register + * Sdio slave DMA channel0 start address of sending linked list status register. + */ +#define SDIO_SLC_SLC0_SUB_START_DES_REG (DR_REG_SLC_BASE + 0x138) +/** SDIO_SLC0_SUB_PAC_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last sent packet through dma channel0. + */ +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_M (SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_V << SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_S) +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_DSCR_CNT_REG register + * Sdio slave DMA channel0 descriptor status register. + */ +#define SDIO_SLC_SLC0_DSCR_CNT_REG (DR_REG_SLC_BASE + 0x13c) +/** SDIO_SLC0_RX_DSCR_CNT_LAT : RO; bitpos: [9:0]; default: 0; + * The number of descriptors got by dma channel0 for sending packets. + */ +#define SDIO_SLC0_RX_DSCR_CNT_LAT 0x000003FFU +#define SDIO_SLC0_RX_DSCR_CNT_LAT_M (SDIO_SLC0_RX_DSCR_CNT_LAT_V << SDIO_SLC0_RX_DSCR_CNT_LAT_S) +#define SDIO_SLC0_RX_DSCR_CNT_LAT_V 0x000003FFU +#define SDIO_SLC0_RX_DSCR_CNT_LAT_S 0 +/** SDIO_SLC0_RX_GET_EOF_OCC : RO; bitpos: [16]; default: 0; + * The status of last packet finishing sending to host. + */ +#define SDIO_SLC0_RX_GET_EOF_OCC (BIT(16)) +#define SDIO_SLC0_RX_GET_EOF_OCC_M (SDIO_SLC0_RX_GET_EOF_OCC_V << SDIO_SLC0_RX_GET_EOF_OCC_S) +#define SDIO_SLC0_RX_GET_EOF_OCC_V 0x00000001U +#define SDIO_SLC0_RX_GET_EOF_OCC_S 16 + +/** SDIO_SLC_SLC0_LEN_LIM_CONF_REG register + * Sdio slave DMA channel0 buffer limit configuration register. + */ +#define SDIO_SLC_SLC0_LEN_LIM_CONF_REG (DR_REG_SLC_BASE + 0x140) +/** SDIO_SLC0_LEN_LIM : R/W; bitpos: [19:0]; default: 21504; + * Every time when the number of buffers loaded for sending packets reaches the number + * of slc0_len_lim, the current number of buffers loaded is saved into the registers + * of slc0_len0, slc0_len1 and slc0_len2. + */ +#define SDIO_SLC0_LEN_LIM 0x000FFFFFU +#define SDIO_SLC0_LEN_LIM_M (SDIO_SLC0_LEN_LIM_V << SDIO_SLC0_LEN_LIM_S) +#define SDIO_SLC0_LEN_LIM_V 0x000FFFFFU +#define SDIO_SLC0_LEN_LIM_S 0 + +/** SDIO_SLC_SLC0INT_ST1_REG register + * Sdio slave DMA channel0 masked interrupt status register1. + */ +#define SDIO_SLC_SLC0INT_ST1_REG (DR_REG_SLC_BASE + 0x144) +/** SDIO_SLC_FRHOST_BIT0_INT_ST1 : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit10_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ST1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ST1_M (SDIO_SLC_FRHOST_BIT0_INT_ST1_V << SDIO_SLC_FRHOST_BIT0_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ST1_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ST1 : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit11_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ST1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ST1_M (SDIO_SLC_FRHOST_BIT1_INT_ST1_V << SDIO_SLC_FRHOST_BIT1_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ST1_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ST1 : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit12_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ST1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ST1_M (SDIO_SLC_FRHOST_BIT2_INT_ST1_V << SDIO_SLC_FRHOST_BIT2_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ST1_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ST1 : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit13_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ST1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ST1_M (SDIO_SLC_FRHOST_BIT3_INT_ST1_V << SDIO_SLC_FRHOST_BIT3_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ST1_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ST1 : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit14_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ST1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ST1_M (SDIO_SLC_FRHOST_BIT4_INT_ST1_V << SDIO_SLC_FRHOST_BIT4_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ST1_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ST1 : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit15_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ST1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ST1_M (SDIO_SLC_FRHOST_BIT5_INT_ST1_V << SDIO_SLC_FRHOST_BIT5_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ST1_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ST1 : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit16_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ST1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ST1_M (SDIO_SLC_FRHOST_BIT6_INT_ST1_V << SDIO_SLC_FRHOST_BIT6_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ST1_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ST1 : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit17_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ST1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ST1_M (SDIO_SLC_FRHOST_BIT7_INT_ST1_V << SDIO_SLC_FRHOST_BIT7_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ST1_S 7 +/** SDIO_SLC0_RX_START_INT_ST1 : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_RX_START_INT_ST1 (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ST1_M (SDIO_SLC0_RX_START_INT_ST1_V << SDIO_SLC0_RX_START_INT_ST1_S) +#define SDIO_SLC0_RX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ST1_S 8 +/** SDIO_SLC0_TX_START_INT_ST1 : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_START_INT_ST1 (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ST1_M (SDIO_SLC0_TX_START_INT_ST1_V << SDIO_SLC0_TX_START_INT_ST1_S) +#define SDIO_SLC0_TX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ST1_S 9 +/** SDIO_SLC0_RX_UDF_INT_ST1 : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_UDF_INT interrupt. + */ +#define SDIO_SLC0_RX_UDF_INT_ST1 (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ST1_M (SDIO_SLC0_RX_UDF_INT_ST1_V << SDIO_SLC0_RX_UDF_INT_ST1_S) +#define SDIO_SLC0_RX_UDF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ST1_S 10 +/** SDIO_SLC0_TX_OVF_INT_ST1 : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_OVF_INT interrupt. + */ +#define SDIO_SLC0_TX_OVF_INT_ST1 (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ST1_M (SDIO_SLC0_TX_OVF_INT_ST1_V << SDIO_SLC0_TX_OVF_INT_ST1_S) +#define SDIO_SLC0_TX_OVF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ST1_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ST1 : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit1 for SLC0_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1 (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_M (SDIO_SLC0_TOKEN0_1TO0_INT_ST1_V << SDIO_SLC0_TOKEN0_1TO0_INT_ST1_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ST1 : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit1 for SLC0_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1 (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_M (SDIO_SLC0_TOKEN1_1TO0_INT_ST1_V << SDIO_SLC0_TOKEN1_1TO0_INT_ST1_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_S 13 +/** SDIO_SLC0_TX_DONE_INT_ST1 : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_DONE_INT_ST1 (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ST1_M (SDIO_SLC0_TX_DONE_INT_ST1_V << SDIO_SLC0_TX_DONE_INT_ST1_S) +#define SDIO_SLC0_TX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ST1_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ST1 : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1 (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_M (SDIO_SLC0_TX_SUC_EOF_INT_ST1_V << SDIO_SLC0_TX_SUC_EOF_INT_ST1_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_S 15 +/** SDIO_SLC0_RX_DONE_INT_ST1 : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_DONE_INT interrupt. + */ +#define SDIO_SLC0_RX_DONE_INT_ST1 (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ST1_M (SDIO_SLC0_RX_DONE_INT_ST1_V << SDIO_SLC0_RX_DONE_INT_ST1_S) +#define SDIO_SLC0_RX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ST1_S 16 +/** SDIO_SLC0_RX_EOF_INT_ST1 : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_EOF_INT_ST1 (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ST1_M (SDIO_SLC0_RX_EOF_INT_ST1_V << SDIO_SLC0_RX_EOF_INT_ST1_S) +#define SDIO_SLC0_RX_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ST1_S 17 +/** SDIO_SLC0_TOHOST_INT_ST1 : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit1 for SLC0_TOHOST_INT interrupt. + */ +#define SDIO_SLC0_TOHOST_INT_ST1 (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ST1_M (SDIO_SLC0_TOHOST_INT_ST1_V << SDIO_SLC0_TOHOST_INT_ST1_S) +#define SDIO_SLC0_TOHOST_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ST1_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ST1 : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1 (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_M (SDIO_SLC0_TX_DSCR_ERR_INT_ST1_V << SDIO_SLC0_TX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ST1 : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1 (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_M (SDIO_SLC0_RX_DSCR_ERR_INT_ST1_V << SDIO_SLC0_RX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1 : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1 (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ST1 : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit1 for SLC0_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1 (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_M (SDIO_SLC0_HOST_RD_ACK_INT_ST1_V << SDIO_SLC0_HOST_RD_ACK_INT_ST1_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ST1 : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit1 for SLC0_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1 (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_M (SDIO_SLC0_WR_RETRY_DONE_INT_ST1_V << SDIO_SLC0_WR_RETRY_DONE_INT_ST1_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ST1 : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1 (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_M (SDIO_SLC0_TX_ERR_EOF_INT_ST1_V << SDIO_SLC0_TX_ERR_EOF_INT_ST1_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_S 24 +/** SDIO_CMD_DTC_INT_ST1 : RO; bitpos: [25]; default: 0; + * The masked interrupt status bit1 for CMD_DTC_INT interrupt. + */ +#define SDIO_CMD_DTC_INT_ST1 (BIT(25)) +#define SDIO_CMD_DTC_INT_ST1_M (SDIO_CMD_DTC_INT_ST1_V << SDIO_CMD_DTC_INT_ST1_S) +#define SDIO_CMD_DTC_INT_ST1_V 0x00000001U +#define SDIO_CMD_DTC_INT_ST1_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ST1 : RO; bitpos: [26]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_QUICK_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1 (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_M (SDIO_SLC0_RX_QUICK_EOF_INT_ST1_V << SDIO_SLC0_RX_QUICK_EOF_INT_ST1_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1 : RO; bitpos: [27]; default: 0; + * The masked interrupt status bit1 for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1 (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_S 27 +/** SDIO_HDA_RECV_DONE_INT_ST1 : RO; bitpos: [28]; default: 0; + * The masked interrupt status bit1 for HDA_RECV_DONE_INT interrupt. + */ +#define SDIO_HDA_RECV_DONE_INT_ST1 (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ST1_M (SDIO_HDA_RECV_DONE_INT_ST1_V << SDIO_HDA_RECV_DONE_INT_ST1_S) +#define SDIO_HDA_RECV_DONE_INT_ST1_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ST1_S 28 + +/** SDIO_SLC_SLC0INT_ENA1_REG register + * Sdio slave DMA channel0 interrupt enable register1. + */ +#define SDIO_SLC_SLC0INT_ENA1_REG (DR_REG_SLC_BASE + 0x148) +/** SDIO_SLC_FRHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit10_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_M (SDIO_SLC_FRHOST_BIT0_INT_ENA1_V << SDIO_SLC_FRHOST_BIT0_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit11_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_M (SDIO_SLC_FRHOST_BIT1_INT_ENA1_V << SDIO_SLC_FRHOST_BIT1_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit12_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_M (SDIO_SLC_FRHOST_BIT2_INT_ENA1_V << SDIO_SLC_FRHOST_BIT2_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit13_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_M (SDIO_SLC_FRHOST_BIT3_INT_ENA1_V << SDIO_SLC_FRHOST_BIT3_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit14_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_M (SDIO_SLC_FRHOST_BIT4_INT_ENA1_V << SDIO_SLC_FRHOST_BIT4_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit15_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_M (SDIO_SLC_FRHOST_BIT5_INT_ENA1_V << SDIO_SLC_FRHOST_BIT5_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit16_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_M (SDIO_SLC_FRHOST_BIT6_INT_ENA1_V << SDIO_SLC_FRHOST_BIT6_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit17_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_M (SDIO_SLC_FRHOST_BIT7_INT_ENA1_V << SDIO_SLC_FRHOST_BIT7_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_S 7 +/** SDIO_SLC0_RX_START_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit1 for SLC0_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_RX_START_INT_ENA1 (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ENA1_M (SDIO_SLC0_RX_START_INT_ENA1_V << SDIO_SLC0_RX_START_INT_ENA1_S) +#define SDIO_SLC0_RX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ENA1_S 8 +/** SDIO_SLC0_TX_START_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit1 for SLC0_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_START_INT_ENA1 (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ENA1_M (SDIO_SLC0_TX_START_INT_ENA1_V << SDIO_SLC0_TX_START_INT_ENA1_S) +#define SDIO_SLC0_TX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ENA1_S 9 +/** SDIO_SLC0_RX_UDF_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit1 for SLC0_RX_UDF_INT interrupt. + */ +#define SDIO_SLC0_RX_UDF_INT_ENA1 (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ENA1_M (SDIO_SLC0_RX_UDF_INT_ENA1_V << SDIO_SLC0_RX_UDF_INT_ENA1_S) +#define SDIO_SLC0_RX_UDF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ENA1_S 10 +/** SDIO_SLC0_TX_OVF_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit1 for SLC0_TX_OVF_INT interrupt. + */ +#define SDIO_SLC0_TX_OVF_INT_ENA1 (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ENA1_M (SDIO_SLC0_TX_OVF_INT_ENA1_V << SDIO_SLC0_TX_OVF_INT_ENA1_S) +#define SDIO_SLC0_TX_OVF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ENA1_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit1 for SLC0_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_M (SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit1 for SLC0_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_M (SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_S 13 +/** SDIO_SLC0_TX_DONE_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit1 for SLC0_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_DONE_INT_ENA1 (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ENA1_M (SDIO_SLC0_TX_DONE_INT_ENA1_V << SDIO_SLC0_TX_DONE_INT_ENA1_S) +#define SDIO_SLC0_TX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ENA1_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit1 for SLC0_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1 (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_M (SDIO_SLC0_TX_SUC_EOF_INT_ENA1_V << SDIO_SLC0_TX_SUC_EOF_INT_ENA1_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_S 15 +/** SDIO_SLC0_RX_DONE_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit1 for SLC0_RX_DONE_INT interrupt. + */ +#define SDIO_SLC0_RX_DONE_INT_ENA1 (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ENA1_M (SDIO_SLC0_RX_DONE_INT_ENA1_V << SDIO_SLC0_RX_DONE_INT_ENA1_S) +#define SDIO_SLC0_RX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ENA1_S 16 +/** SDIO_SLC0_RX_EOF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit1 for SLC0_RX_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_EOF_INT_ENA1 (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ENA1_M (SDIO_SLC0_RX_EOF_INT_ENA1_V << SDIO_SLC0_RX_EOF_INT_ENA1_S) +#define SDIO_SLC0_RX_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ENA1_S 17 +/** SDIO_SLC0_TOHOST_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit1 for SLC0_TOHOST_INT interrupt. + */ +#define SDIO_SLC0_TOHOST_INT_ENA1 (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ENA1_M (SDIO_SLC0_TOHOST_INT_ENA1_V << SDIO_SLC0_TOHOST_INT_ENA1_S) +#define SDIO_SLC0_TOHOST_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ENA1_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit1 for SLC0_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1 (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_M (SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_V << SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit1 for SLC0_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1 (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_M (SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_V << SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit1 for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1 (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit1 for SLC0_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1 (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_M (SDIO_SLC0_HOST_RD_ACK_INT_ENA1_V << SDIO_SLC0_HOST_RD_ACK_INT_ENA1_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit1 for SLC0_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1 (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_M (SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_V << SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit1 for SLC0_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1 (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_M (SDIO_SLC0_TX_ERR_EOF_INT_ENA1_V << SDIO_SLC0_TX_ERR_EOF_INT_ENA1_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_S 24 +/** SDIO_CMD_DTC_INT_ENA1 : R/W; bitpos: [25]; default: 0; + * The interrupt enable bit1 for CMD_DTC_INT interrupt. + */ +#define SDIO_CMD_DTC_INT_ENA1 (BIT(25)) +#define SDIO_CMD_DTC_INT_ENA1_M (SDIO_CMD_DTC_INT_ENA1_V << SDIO_CMD_DTC_INT_ENA1_S) +#define SDIO_CMD_DTC_INT_ENA1_V 0x00000001U +#define SDIO_CMD_DTC_INT_ENA1_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ENA1 : R/W; bitpos: [26]; default: 0; + * The interrupt enable bit1 for SLC0_RX_QUICK_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1 (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_M (SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_V << SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1 : R/W; bitpos: [27]; default: 0; + * The interrupt enable bit1 for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1 (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S 27 +/** SDIO_HDA_RECV_DONE_INT_ENA1 : R/W; bitpos: [28]; default: 0; + * The interrupt enable bit1 for HDA_RECV_DONE_INT interrupt. + */ +#define SDIO_HDA_RECV_DONE_INT_ENA1 (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ENA1_M (SDIO_HDA_RECV_DONE_INT_ENA1_V << SDIO_HDA_RECV_DONE_INT_ENA1_S) +#define SDIO_HDA_RECV_DONE_INT_ENA1_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ENA1_S 28 + +/** SDIO_SLC_SLC1INT_ST1_REG register + * Sdio slave DMA channel1 masked interrupt status register1. + */ +#define SDIO_SLC_SLC1INT_ST1_REG (DR_REG_SLC_BASE + 0x14c) +/** SDIO_SLC_FRHOST_BIT8_INT_ST1 : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit10_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ST1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ST1_M (SDIO_SLC_FRHOST_BIT8_INT_ST1_V << SDIO_SLC_FRHOST_BIT8_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ST1_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ST1 : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit11_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ST1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ST1_M (SDIO_SLC_FRHOST_BIT9_INT_ST1_V << SDIO_SLC_FRHOST_BIT9_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ST1_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ST1 : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit12_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ST1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ST1_M (SDIO_SLC_FRHOST_BIT10_INT_ST1_V << SDIO_SLC_FRHOST_BIT10_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ST1_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ST1 : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit13_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ST1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ST1_M (SDIO_SLC_FRHOST_BIT11_INT_ST1_V << SDIO_SLC_FRHOST_BIT11_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ST1_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ST1 : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit14_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ST1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ST1_M (SDIO_SLC_FRHOST_BIT12_INT_ST1_V << SDIO_SLC_FRHOST_BIT12_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ST1_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ST1 : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit15_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ST1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ST1_M (SDIO_SLC_FRHOST_BIT13_INT_ST1_V << SDIO_SLC_FRHOST_BIT13_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ST1_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ST1 : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit16_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ST1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ST1_M (SDIO_SLC_FRHOST_BIT14_INT_ST1_V << SDIO_SLC_FRHOST_BIT14_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ST1_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ST1 : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit17_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ST1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ST1_M (SDIO_SLC_FRHOST_BIT15_INT_ST1_V << SDIO_SLC_FRHOST_BIT15_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ST1_S 7 +/** SDIO_SLC1_RX_START_INT_ST1 : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_RX_START_INT_ST1 (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ST1_M (SDIO_SLC1_RX_START_INT_ST1_V << SDIO_SLC1_RX_START_INT_ST1_S) +#define SDIO_SLC1_RX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ST1_S 8 +/** SDIO_SLC1_TX_START_INT_ST1 : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_START_INT_ST1 (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ST1_M (SDIO_SLC1_TX_START_INT_ST1_V << SDIO_SLC1_TX_START_INT_ST1_S) +#define SDIO_SLC1_TX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ST1_S 9 +/** SDIO_SLC1_RX_UDF_INT_ST1 : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_UDF_INT interrupt. + */ +#define SDIO_SLC1_RX_UDF_INT_ST1 (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ST1_M (SDIO_SLC1_RX_UDF_INT_ST1_V << SDIO_SLC1_RX_UDF_INT_ST1_S) +#define SDIO_SLC1_RX_UDF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ST1_S 10 +/** SDIO_SLC1_TX_OVF_INT_ST1 : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_OVF_INT interrupt. + */ +#define SDIO_SLC1_TX_OVF_INT_ST1 (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ST1_M (SDIO_SLC1_TX_OVF_INT_ST1_V << SDIO_SLC1_TX_OVF_INT_ST1_S) +#define SDIO_SLC1_TX_OVF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ST1_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ST1 : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit1 for SLC1_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1 (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_M (SDIO_SLC1_TOKEN0_1TO0_INT_ST1_V << SDIO_SLC1_TOKEN0_1TO0_INT_ST1_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ST1 : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit1 for SLC1_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1 (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_M (SDIO_SLC1_TOKEN1_1TO0_INT_ST1_V << SDIO_SLC1_TOKEN1_1TO0_INT_ST1_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_S 13 +/** SDIO_SLC1_TX_DONE_INT_ST1 : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_DONE_INT_ST1 (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ST1_M (SDIO_SLC1_TX_DONE_INT_ST1_V << SDIO_SLC1_TX_DONE_INT_ST1_S) +#define SDIO_SLC1_TX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ST1_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ST1 : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1 (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_M (SDIO_SLC1_TX_SUC_EOF_INT_ST1_V << SDIO_SLC1_TX_SUC_EOF_INT_ST1_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_S 15 +/** SDIO_SLC1_RX_DONE_INT_ST1 : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_DONE_INT interrupt. + */ +#define SDIO_SLC1_RX_DONE_INT_ST1 (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ST1_M (SDIO_SLC1_RX_DONE_INT_ST1_V << SDIO_SLC1_RX_DONE_INT_ST1_S) +#define SDIO_SLC1_RX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ST1_S 16 +/** SDIO_SLC1_RX_EOF_INT_ST1 : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_EOF_INT interrupt. + */ +#define SDIO_SLC1_RX_EOF_INT_ST1 (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ST1_M (SDIO_SLC1_RX_EOF_INT_ST1_V << SDIO_SLC1_RX_EOF_INT_ST1_S) +#define SDIO_SLC1_RX_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ST1_S 17 +/** SDIO_SLC1_TOHOST_INT_ST1 : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit1 for SLC1_TOHOST_INT interrupt. + */ +#define SDIO_SLC1_TOHOST_INT_ST1 (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ST1_M (SDIO_SLC1_TOHOST_INT_ST1_V << SDIO_SLC1_TOHOST_INT_ST1_S) +#define SDIO_SLC1_TOHOST_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ST1_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ST1 : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1 (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_M (SDIO_SLC1_TX_DSCR_ERR_INT_ST1_V << SDIO_SLC1_TX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ST1 : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1 (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_M (SDIO_SLC1_RX_DSCR_ERR_INT_ST1_V << SDIO_SLC1_RX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1 : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1 (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ST1 : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit1 for SLC1_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1 (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_M (SDIO_SLC1_HOST_RD_ACK_INT_ST1_V << SDIO_SLC1_HOST_RD_ACK_INT_ST1_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ST1 : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit1 for SLC1_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1 (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_M (SDIO_SLC1_WR_RETRY_DONE_INT_ST1_V << SDIO_SLC1_WR_RETRY_DONE_INT_ST1_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ST1 : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1 (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_M (SDIO_SLC1_TX_ERR_EOF_INT_ST1_V << SDIO_SLC1_TX_ERR_EOF_INT_ST1_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_S 24 + +/** SDIO_SLC_SLC1INT_ENA1_REG register + * Sdio slave DMA channel1 interrupt enable register1. + */ +#define SDIO_SLC_SLC1INT_ENA1_REG (DR_REG_SLC_BASE + 0x150) +/** SDIO_SLC_FRHOST_BIT8_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit10_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_M (SDIO_SLC_FRHOST_BIT8_INT_ENA1_V << SDIO_SLC_FRHOST_BIT8_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit11_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_M (SDIO_SLC_FRHOST_BIT9_INT_ENA1_V << SDIO_SLC_FRHOST_BIT9_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit12_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_M (SDIO_SLC_FRHOST_BIT10_INT_ENA1_V << SDIO_SLC_FRHOST_BIT10_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit13_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_M (SDIO_SLC_FRHOST_BIT11_INT_ENA1_V << SDIO_SLC_FRHOST_BIT11_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit14_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_M (SDIO_SLC_FRHOST_BIT12_INT_ENA1_V << SDIO_SLC_FRHOST_BIT12_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit15_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_M (SDIO_SLC_FRHOST_BIT13_INT_ENA1_V << SDIO_SLC_FRHOST_BIT13_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit16_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_M (SDIO_SLC_FRHOST_BIT14_INT_ENA1_V << SDIO_SLC_FRHOST_BIT14_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit17_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_M (SDIO_SLC_FRHOST_BIT15_INT_ENA1_V << SDIO_SLC_FRHOST_BIT15_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_S 7 +/** SDIO_SLC1_RX_START_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit1 for SCL1_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_RX_START_INT_ENA1 (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ENA1_M (SDIO_SLC1_RX_START_INT_ENA1_V << SDIO_SLC1_RX_START_INT_ENA1_S) +#define SDIO_SLC1_RX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ENA1_S 8 +/** SDIO_SLC1_TX_START_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit1 for SCL1_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_START_INT_ENA1 (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ENA1_M (SDIO_SLC1_TX_START_INT_ENA1_V << SDIO_SLC1_TX_START_INT_ENA1_S) +#define SDIO_SLC1_TX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ENA1_S 9 +/** SDIO_SLC1_RX_UDF_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit1 for SCL1_RX_UDF_INT interrupt. + */ +#define SDIO_SLC1_RX_UDF_INT_ENA1 (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ENA1_M (SDIO_SLC1_RX_UDF_INT_ENA1_V << SDIO_SLC1_RX_UDF_INT_ENA1_S) +#define SDIO_SLC1_RX_UDF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ENA1_S 10 +/** SDIO_SLC1_TX_OVF_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit1 for SCL1_TX_OVF_INT interrupt. + */ +#define SDIO_SLC1_TX_OVF_INT_ENA1 (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ENA1_M (SDIO_SLC1_TX_OVF_INT_ENA1_V << SDIO_SLC1_TX_OVF_INT_ENA1_S) +#define SDIO_SLC1_TX_OVF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ENA1_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit1 for SCL1_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1 (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_M (SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit1 for SCL1_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1 (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_M (SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_S 13 +/** SDIO_SLC1_TX_DONE_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit1 for SCL1_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_DONE_INT_ENA1 (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ENA1_M (SDIO_SLC1_TX_DONE_INT_ENA1_V << SDIO_SLC1_TX_DONE_INT_ENA1_S) +#define SDIO_SLC1_TX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ENA1_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit1 for SCL1_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1 (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_M (SDIO_SLC1_TX_SUC_EOF_INT_ENA1_V << SDIO_SLC1_TX_SUC_EOF_INT_ENA1_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_S 15 +/** SDIO_SLC1_RX_DONE_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit1 for SCL1_RX_DONE_INT interrupt. + */ +#define SDIO_SLC1_RX_DONE_INT_ENA1 (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ENA1_M (SDIO_SLC1_RX_DONE_INT_ENA1_V << SDIO_SLC1_RX_DONE_INT_ENA1_S) +#define SDIO_SLC1_RX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ENA1_S 16 +/** SDIO_SLC1_RX_EOF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit1 for SCL1_RX_EOF_INT interrupt. + */ +#define SDIO_SLC1_RX_EOF_INT_ENA1 (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ENA1_M (SDIO_SLC1_RX_EOF_INT_ENA1_V << SDIO_SLC1_RX_EOF_INT_ENA1_S) +#define SDIO_SLC1_RX_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ENA1_S 17 +/** SDIO_SLC1_TOHOST_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit1 for SCL1_TOHOST_INT interrupt. + */ +#define SDIO_SLC1_TOHOST_INT_ENA1 (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ENA1_M (SDIO_SLC1_TOHOST_INT_ENA1_V << SDIO_SLC1_TOHOST_INT_ENA1_S) +#define SDIO_SLC1_TOHOST_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ENA1_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit1 for SCL1_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1 (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_M (SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_V << SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit1 for SCL1_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1 (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_M (SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_V << SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit1 for SCL1_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1 (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit1 for SCL1_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1 (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_M (SDIO_SLC1_HOST_RD_ACK_INT_ENA1_V << SDIO_SLC1_HOST_RD_ACK_INT_ENA1_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit1 for SCL1_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1 (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_M (SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_V << SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit1 for SCL1_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1 (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_M (SDIO_SLC1_TX_ERR_EOF_INT_ENA1_V << SDIO_SLC1_TX_ERR_EOF_INT_ENA1_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_S 24 + +/** SDIO_SLC_SLC0_TX_SHAREMEM_START_REG register + * Sdio slave DMA channel0 address range of receiving linked list register. + */ +#define SDIO_SLC_SLC0_TX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x154) +/** SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to receive packet through dma + * channel0. + */ +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_SLC0_TX_SHAREMEM_END_REG register + * Sdio slave DMA channel0 address range of receiving linked list register1. + */ +#define SDIO_SLC_SLC0_TX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x158) +/** SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to receive packet through dma + * channel0. + */ +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_SLC_SLC0_RX_SHAREMEM_START_REG register + * Sdio slave DMA channel0 address range of sending linked list register. + */ +#define SDIO_SLC_SLC0_RX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x15c) +/** SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to send packet through dma + * channel0. + */ +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_SLC0_RX_SHAREMEM_END_REG register + * Sdio slave DMA channel0 address range of sending linked list register1. + */ +#define SDIO_SLC_SLC0_RX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x160) +/** SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to send packet through dma + * channel0. + */ +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_SLC_SLC1_TX_SHAREMEM_START_REG register + * Sdio slave DMA channel1 address range of receiving linked list register. + */ +#define SDIO_SLC_SLC1_TX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x164) +/** SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to receive packet through dma + * channel1. + */ +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_SLC1_TX_SHAREMEM_END_REG register + * Sdio slave DMA channel1 address range of receiving linked list register1. + */ +#define SDIO_SLC_SLC1_TX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x168) +/** SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to receive packet through dma + * channel1. + */ +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_SLC_SLC1_RX_SHAREMEM_START_REG register + * Sdio slave DMA channel1 address range of sending linked list register. + */ +#define SDIO_SLC_SLC1_RX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x16c) +/** SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to send packet through dma + * channel1. + */ +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_SLC1_RX_SHAREMEM_END_REG register + * Sdio slave DMA channel1 address range of sending linked list register1. + */ +#define SDIO_SLC_SLC1_RX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x170) +/** SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to send packet through dma + * channel1. + */ +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_SLC_HDA_TX_SHAREMEM_START_REG register + * Sdio slave HAD receiving address range register. + */ +#define SDIO_SLC_HDA_TX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x174) +/** SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * Use 31 to 20 bit of this field as the higher 20 bits of 32-bit address for HAD + * receiving packets. + */ +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_M (SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_HDA_RX_SHAREMEM_START_REG register + * Sdio slave HAD sending address range register. + */ +#define SDIO_SLC_HDA_RX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x178) +/** SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * Use 31 to 20 bit of this field as the higher 20 bits of 32-bit address for HAD + * sending packets. + */ +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_M (SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_BURST_LEN_REG register + * Sdio slave AHB burst type configuration register. + */ +#define SDIO_SLC_BURST_LEN_REG (DR_REG_SLC_BASE + 0x17c) +/** SDIO_SLC0_TXDATA_BURST_LEN : R/W; bitpos: [0]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ +#define SDIO_SLC0_TXDATA_BURST_LEN (BIT(0)) +#define SDIO_SLC0_TXDATA_BURST_LEN_M (SDIO_SLC0_TXDATA_BURST_LEN_V << SDIO_SLC0_TXDATA_BURST_LEN_S) +#define SDIO_SLC0_TXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC0_TXDATA_BURST_LEN_S 0 +/** SDIO_SLC0_RXDATA_BURST_LEN : R/W; bitpos: [1]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ +#define SDIO_SLC0_RXDATA_BURST_LEN (BIT(1)) +#define SDIO_SLC0_RXDATA_BURST_LEN_M (SDIO_SLC0_RXDATA_BURST_LEN_V << SDIO_SLC0_RXDATA_BURST_LEN_S) +#define SDIO_SLC0_RXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC0_RXDATA_BURST_LEN_S 1 +/** SDIO_SLC1_TXDATA_BURST_LEN : R/W; bitpos: [2]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ +#define SDIO_SLC1_TXDATA_BURST_LEN (BIT(2)) +#define SDIO_SLC1_TXDATA_BURST_LEN_M (SDIO_SLC1_TXDATA_BURST_LEN_V << SDIO_SLC1_TXDATA_BURST_LEN_S) +#define SDIO_SLC1_TXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC1_TXDATA_BURST_LEN_S 2 +/** SDIO_SLC1_RXDATA_BURST_LEN : R/W; bitpos: [3]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ +#define SDIO_SLC1_RXDATA_BURST_LEN (BIT(3)) +#define SDIO_SLC1_RXDATA_BURST_LEN_M (SDIO_SLC1_RXDATA_BURST_LEN_V << SDIO_SLC1_RXDATA_BURST_LEN_S) +#define SDIO_SLC1_RXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC1_RXDATA_BURST_LEN_S 3 + +/** SDIO_SLC_DATE_REG register + * Sdio slave DMA version register. + */ +#define SDIO_SLC_DATE_REG (DR_REG_SLC_BASE + 0x1f8) +/** SDIO_SLC_DATE : R/W; bitpos: [31:0]; default: 554182400; + * Sdio slave DMA version register. + */ +#define SDIO_SLC_DATE 0xFFFFFFFFU +#define SDIO_SLC_DATE_M (SDIO_SLC_DATE_V << SDIO_SLC_DATE_S) +#define SDIO_SLC_DATE_V 0xFFFFFFFFU +#define SDIO_SLC_DATE_S 0 + +/** SDIO_SLC_ID_REG register + * Sdio slave ID register. + */ +#define SDIO_SLC_ID_REG (DR_REG_SLC_BASE + 0x1fc) +/** SDIO_SLC_ID : R/W; bitpos: [31:0]; default: 256; + * reserved + */ +#define SDIO_SLC_ID 0xFFFFFFFFU +#define SDIO_SLC_ID_M (SDIO_SLC_ID_V << SDIO_SLC_ID_S) +#define SDIO_SLC_ID_V 0xFFFFFFFFU +#define SDIO_SLC_ID_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/register/soc/sdio_slc_struct.h b/components/soc/esp32c61/register/soc/sdio_slc_struct.h new file mode 100644 index 0000000000..74bb9d69dd --- /dev/null +++ b/components/soc/esp32c61/register/soc/sdio_slc_struct.h @@ -0,0 +1,3345 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration registers */ +/** Type of slc_conf0 register + * Sdio slave DMA configuration register. + */ +typedef union { + struct { + /** slc0_tx_rst : R/W; bitpos: [0]; default: 0; + * Set 1 to reset receiving fsm in dma channel0. + */ + uint32_t slc0_tx_rst:1; + /** slc0_rx_rst : R/W; bitpos: [1]; default: 0; + * Set 1 to reset transmitting fsm in dma channel0. + */ + uint32_t slc0_rx_rst:1; + /** slc_ahbm_fifo_rst : R/W; bitpos: [2]; default: 0; + * reset the command fifo of AHB bus of sdio slave + */ + uint32_t slc_ahbm_fifo_rst:1; + /** slc_ahbm_rst : R/W; bitpos: [3]; default: 0; + * reset the AHB bus of sdio slave + */ + uint32_t slc_ahbm_rst:1; + /** slc0_tx_loop_test : R/W; bitpos: [4]; default: 0; + * Loop around when the slave buffer finishes receiving packets. When set to 1, + * hardware will not change the owner bit in the linked list. + */ + uint32_t slc0_tx_loop_test:1; + /** slc0_rx_loop_test : R/W; bitpos: [5]; default: 0; + * Loop around when the slave buffer finishes sending packets. When set to 1, hardware + * will not change the owner bit in the linked list. + */ + uint32_t slc0_rx_loop_test:1; + /** slc0_rx_auto_wrback : R/W; bitpos: [6]; default: 0; + * Set 1 to enable change the owner bit of rx link descriptor + */ + uint32_t slc0_rx_auto_wrback:1; + /** slc0_rx_no_restart_clr : R/W; bitpos: [7]; default: 0; + * Set this bit to disable the function that when slave starts to send data to host, + * the slc0_bt_rx_new_packet_int_raw or slc0_host_rd_retry_int_raw will be + * automatically cleared. + */ + uint32_t slc0_rx_no_restart_clr:1; + /** slc0_rxdscr_burst_en : R/W; bitpos: [8]; default: 1; + * 0- AHB burst type is single when slave read rx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read rx-descriptor from memory + * through slc0 + */ + uint32_t slc0_rxdscr_burst_en:1; + /** slc0_rxdata_burst_en : R/W; bitpos: [9]; default: 1; + * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type + * is not single when slave receives data from memory + */ + uint32_t slc0_rxdata_burst_en:1; + /** slc0_rxlink_auto_ret : R/W; bitpos: [10]; default: 1; + * enable the function that when host reading packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ + uint32_t slc0_rxlink_auto_ret:1; + /** slc0_txlink_auto_ret : R/W; bitpos: [11]; default: 1; + * enable the function that when host sending packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ + uint32_t slc0_txlink_auto_ret:1; + /** slc0_txdscr_burst_en : R/W; bitpos: [12]; default: 1; + * 0- AHB burst type is single when slave read tx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read tx-descriptor from memory + * through slc0 + */ + uint32_t slc0_txdscr_burst_en:1; + /** slc0_txdata_burst_en : R/W; bitpos: [13]; default: 1; + * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not + * single when slave send data to memory + */ + uint32_t slc0_txdata_burst_en:1; + /** slc0_token_auto_clr : R/W; bitpos: [14]; default: 1; + * auto clear slc0_token1 enable + */ + uint32_t slc0_token_auto_clr:1; + /** slc0_token_sel : R/W; bitpos: [15]; default: 1; + * 0: choose to save slc0_token0's value, 1: choose to save the accumulative value of + * slc0_token1 + */ + uint32_t slc0_token_sel:1; + /** slc1_tx_rst : R/W; bitpos: [16]; default: 0; + * Set 1 to reset receiving fsm in dma slc0. + */ + uint32_t slc1_tx_rst:1; + /** slc1_rx_rst : R/W; bitpos: [17]; default: 0; + * Set 1 to reset sending fsm in dma slc0. + */ + uint32_t slc1_rx_rst:1; + /** slc0_wr_retry_mask_en : R/W; bitpos: [18]; default: 1; + * Set this bit to generate an interrupt when host sending retry finishes and prevent + * host still retrying after one successful retry through dma channel0 + */ + uint32_t slc0_wr_retry_mask_en:1; + /** slc1_wr_retry_mask_en : R/W; bitpos: [19]; default: 1; + * Set this bit to generate an interrupt when host sending retry finishes and prevent + * host still retrying after one successful retry through dma channel0 + */ + uint32_t slc1_wr_retry_mask_en:1; + /** slc1_tx_loop_test : R/W; bitpos: [20]; default: 1; + * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. + */ + uint32_t slc1_tx_loop_test:1; + /** slc1_rx_loop_test : R/W; bitpos: [21]; default: 1; + * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. + */ + uint32_t slc1_rx_loop_test:1; + /** slc1_rx_auto_wrback : R/W; bitpos: [22]; default: 0; + * Set 1 to enable change the owner bit of the transmitting buffer's linked list when + * transmitting data. + */ + uint32_t slc1_rx_auto_wrback:1; + /** slc1_rx_no_restart_clr : R/W; bitpos: [23]; default: 0; + * Set this bit to disable the function that when slave starts to send data to host, + * the slc1_bt_rx_new_packet_int_raw, slc1_wifi_rx_new_packet_int_raw or + * slc1_host_rd_retry_int_raw will be automatically cleared. + */ + uint32_t slc1_rx_no_restart_clr:1; + /** slc1_rxdscr_burst_en : R/W; bitpos: [24]; default: 1; + * 0- AHB burst type is single when dma channel1 fetches linked list for sending + * data,1-AHB burst type is not single when dma channel1 fetches linked list for + * sending data + */ + uint32_t slc1_rxdscr_burst_en:1; + /** slc1_rxdata_burst_en : R/W; bitpos: [25]; default: 1; + * 0- AHB burst type is single when slave receives data through dma channel1,1-AHB + * burst type is not single when slave receives data through dma channel1 + */ + uint32_t slc1_rxdata_burst_en:1; + /** slc1_rxlink_auto_ret : R/W; bitpos: [26]; default: 1; + * enable the function that when host reading packet retries, dma channel1 will + * automatically jump to the start descriptor of the previous packet. + */ + uint32_t slc1_rxlink_auto_ret:1; + /** slc1_txlink_auto_ret : R/W; bitpos: [27]; default: 1; + * enable the function that when host sending packet retries, dma channel1 will + * automatically jump to the start descriptor of the previous packet. + */ + uint32_t slc1_txlink_auto_ret:1; + /** slc1_txdscr_burst_en : R/W; bitpos: [28]; default: 1; + * 0- AHB burst type is single when dma channel1 fetches linked list for receiving + * data, 1-AHB burst type is not single when dma channel1 fetches linked list for + * receiving data + */ + uint32_t slc1_txdscr_burst_en:1; + /** slc1_txdata_burst_en : R/W; bitpos: [29]; default: 1; + * 0- AHB burst type is single when slave sends data to memory through dma channel1, + * 1-AHB burst type is not single when slave sends data to memory through dma channel1. + */ + uint32_t slc1_txdata_burst_en:1; + uint32_t reserved_30:1; + /** slc1_token_sel : R/W; bitpos: [31]; default: 1; + * reserved + */ + uint32_t slc1_token_sel:1; + }; + uint32_t val; +} sdio_slc_conf0_reg_t; + +/** Type of slc_slc0rxfifo_push register + * Sdio slave DMA channel0 rxfifo debug register. + */ +typedef union { + struct { + /** slc0_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0; + * The data used to sent into rxfifo through APB bus. + */ + uint32_t slc0_rxfifo_wdata:9; + uint32_t reserved_9:7; + /** slc0_rxfifo_push : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to send slc0_rxfifo_wdata into rxfifo through APB bus. This bit is + * cleared automatically after sending one data to slc0_rxfifo through APB bus + * successfully. + */ + uint32_t slc0_rxfifo_push:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc_slc0rxfifo_push_reg_t; + +/** Type of slc_slc1rxfifo_push register + * Sdio slave DMA channel1 rxfifo debug register. + */ +typedef union { + struct { + /** slc1_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0; + * The data used to sent into rxfifo through APB bus. + */ + uint32_t slc1_rxfifo_wdata:9; + uint32_t reserved_9:7; + /** slc1_rxfifo_push : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to send slc1_rxfifo_wdata into rxfifo through APB bus. This bit is + * cleared automatically after sending one data to slc1_rxfifo through APB bus + * successfully. + */ + uint32_t slc1_rxfifo_push:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc_slc1rxfifo_push_reg_t; + +/** Type of slc_slc0rx_link register + * Sdio slave DMA channel0 configuration and status register of link list for slave + * sending data. + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** slc0_rxlink_stop : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel0 sending packets. + */ + uint32_t slc0_rxlink_stop:1; + /** slc0_rxlink_start : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel0 sending packets. Sending + * will start from address indicated by SLC0_RXLINK_ADDR. + */ + uint32_t slc0_rxlink_start:1; + /** slc0_rxlink_restart : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel0 sending + * packets. + */ + uint32_t slc0_rxlink_restart:1; + /** slc0_rxlink_park : RO; bitpos: [31]; default: 1; + * The status bit for sending link list fsm of dma channel0 in idle state + */ + uint32_t slc0_rxlink_park:1; + }; + uint32_t val; +} sdio_slc_slc0rx_link_reg_t; + +/** Type of slc_slc0rx_link_addr register + * Sdio slave DMA channel0 address of first descriptor of sending link list. + */ +typedef union { + struct { + /** slc0_rxlink_addr : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel0's sending linked list. + */ + uint32_t slc0_rxlink_addr:32; + }; + uint32_t val; +} sdio_slc_slc0rx_link_addr_reg_t; + +/** Type of slc_slc0tx_link register + * Sdio slave DMA channel0 configuration and status register of link list for slave + * receiving data. + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** slc0_txlink_stop : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel0 receiving packets. + */ + uint32_t slc0_txlink_stop:1; + /** slc0_txlink_start : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel0 receiving packets. + * Sending will start from address indicated by SLC0_TXLINK_ADDR. + */ + uint32_t slc0_txlink_start:1; + /** slc0_txlink_restart : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel0 receiving + * packets. + */ + uint32_t slc0_txlink_restart:1; + /** slc0_txlink_park : RO; bitpos: [31]; default: 1; + * The status bit for receiving link list fsm of dma channel0 in idle state + */ + uint32_t slc0_txlink_park:1; + }; + uint32_t val; +} sdio_slc_slc0tx_link_reg_t; + +/** Type of slc_slc0tx_link_addr register + * Sdio slave DMA channel0 address of first descriptor of receiving linked list. + */ +typedef union { + struct { + /** slc0_txlink_addr : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel0's receiving linked list. + */ + uint32_t slc0_txlink_addr:32; + }; + uint32_t val; +} sdio_slc_slc0tx_link_addr_reg_t; + +/** Type of slc_slc1rx_link register + * Sdio slave DMA channel1 configuration and status register of link list for slave + * sending data. + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** slc1_bt_packet : R/W; bitpos: [20]; default: 1; + * Configure the packet type for slave to send: 0- wifi packet, 1- blue-tooth packet. + */ + uint32_t slc1_bt_packet:1; + uint32_t reserved_21:7; + /** slc1_rxlink_stop : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel1 sending packets. + */ + uint32_t slc1_rxlink_stop:1; + /** slc1_rxlink_start : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel1 sending packets. Sending + * will start from address indicated by SLC0_RXLINK_ADDR. + */ + uint32_t slc1_rxlink_start:1; + /** slc1_rxlink_restart : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel1 sending + * packets. + */ + uint32_t slc1_rxlink_restart:1; + /** slc1_rxlink_park : RO; bitpos: [31]; default: 1; + * The status bit for sending link list fsm of dma channel1 in idle state + */ + uint32_t slc1_rxlink_park:1; + }; + uint32_t val; +} sdio_slc_slc1rx_link_reg_t; + +/** Type of slc_slc1rx_link_addr register + * Sdio slave DMA channel1 address of first descriptor of sending link list. + */ +typedef union { + struct { + /** slc1_rxlink_addr : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel1's sending linked list. + */ + uint32_t slc1_rxlink_addr:32; + }; + uint32_t val; +} sdio_slc_slc1rx_link_addr_reg_t; + +/** Type of slc_slc1tx_link register + * Sdio slave DMA channel1 configuration and status register of link list for slave + * receiving data. + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** slc1_txlink_stop : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel1 receiving packets. + */ + uint32_t slc1_txlink_stop:1; + /** slc1_txlink_start : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel1 receiving packets. + * Sending will start from address indicated by SLC0_TXLINK_ADDR. + */ + uint32_t slc1_txlink_start:1; + /** slc1_txlink_restart : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel1 receiving + * packets. + */ + uint32_t slc1_txlink_restart:1; + /** slc1_txlink_park : RO; bitpos: [31]; default: 1; + * The status bit for receiving link list fsm of dma channel1 in idle state + */ + uint32_t slc1_txlink_park:1; + }; + uint32_t val; +} sdio_slc_slc1tx_link_reg_t; + +/** Type of slc_slc1tx_link_addr register + * Sdio slave DMA channel1 address of first descriptor of receiving linked list. + */ +typedef union { + struct { + /** slc1_txlink_addr : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel1's receiving linked list. + */ + uint32_t slc1_txlink_addr:32; + }; + uint32_t val; +} sdio_slc_slc1tx_link_addr_reg_t; + +/** Type of slc_slcintvec_tohost register + * Sdio slave DMA channel0 address of first descriptor of receiving linked list. + */ +typedef union { + struct { + /** slc0_tohost_intvec : WT; bitpos: [7:0]; default: 0; + * The interrupt vector for slave to interrupt host through dma channel0. + */ + uint32_t slc0_tohost_intvec:8; + uint32_t reserved_8:8; + /** slc1_tohost_intvec : WT; bitpos: [23:16]; default: 0; + * The interrupt vector for slave to interrupt host through dma channel1. + */ + uint32_t slc1_tohost_intvec:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} sdio_slc_slcintvec_tohost_reg_t; + +/** Type of slc_slc0token0 register + * Sdio slave DMA channel0 receiving buffer configuration and status register. + */ +typedef union { + struct { + /** slc0_token0_wdata : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ + uint32_t slc0_token0_wdata:12; + /** slc0_token0_wr : WT; bitpos: [12]; default: 0; + * update slc0_token0_wdata into slc0 token0. + */ + uint32_t slc0_token0_wr:1; + /** slc0_token0_inc : WT; bitpos: [13]; default: 0; + * Add 1 to slc0_token0. + */ + uint32_t slc0_token0_inc:1; + /** slc0_token0_inc_more : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC0TOKEN0_SLC0_TOKEN0_WDATA to + * SDIO_SLC0TOKEN0_SLC0_TOKEN0. + */ + uint32_t slc0_token0_inc_more:1; + uint32_t reserved_15:1; + /** slc0_token0 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel0. + */ + uint32_t slc0_token0:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_slc0token0_reg_t; + +/** Type of slc_slc0token1 register + * Sdio slave DMA channel0 receiving buffer configuration and status register1. + */ +typedef union { + struct { + /** slc0_token1_wdata : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ + uint32_t slc0_token1_wdata:12; + /** slc0_token1_wr : WT; bitpos: [12]; default: 0; + * update slc0_token1_wdata into slc0 token1 + */ + uint32_t slc0_token1_wr:1; + /** slc0_token1_inc : WT; bitpos: [13]; default: 0; + * slc0_token1 becomes to 1 when auto clear slc0_token1, else add 1 to slc0_token1 + */ + uint32_t slc0_token1_inc:1; + /** slc0_token1_inc_more : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC0TOKEN1_SLC0_TOKEN1_WDATA to + * SDIO_SLC0TOKEN1_SLC0_TOKEN1. + */ + uint32_t slc0_token1_inc_more:1; + uint32_t reserved_15:1; + /** slc0_token1 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel0. + */ + uint32_t slc0_token1:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_slc0token1_reg_t; + +/** Type of slc_slc1token0 register + * Sdio slave DMA channel1 receiving buffer configuration and status register. + */ +typedef union { + struct { + /** slc1_token0_wdata : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ + uint32_t slc1_token0_wdata:12; + /** slc1_token0_wr : WT; bitpos: [12]; default: 0; + * update SLC1_token0_wdata into SLC1 token0. + */ + uint32_t slc1_token0_wr:1; + /** slc1_token0_inc : WT; bitpos: [13]; default: 0; + * Add 1 to SLC1_token0. + */ + uint32_t slc1_token0_inc:1; + /** slc1_token0_inc_more : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC1TOKEN0_SLC1_TOKEN0_WDATA to + * SDIO_SLC1TOKEN0_SLC1_TOKEN0. + */ + uint32_t slc1_token0_inc_more:1; + uint32_t reserved_15:1; + /** slc1_token0 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel1. + */ + uint32_t slc1_token0:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_slc1token0_reg_t; + +/** Type of slc_slc1token1 register + * Sdio slave DMA channel1 receiving buffer configuration and status register1. + */ +typedef union { + struct { + /** slc1_token1_wdata : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ + uint32_t slc1_token1_wdata:12; + /** slc1_token1_wr : WT; bitpos: [12]; default: 0; + * update SLC1_token1_wdata into SLC1 token1 + */ + uint32_t slc1_token1_wr:1; + /** slc1_token1_inc : WT; bitpos: [13]; default: 0; + * SLC1_token1 becomes to 1 when auto clear SLC1_token1, else add 1 to SLC1_token1 + */ + uint32_t slc1_token1_inc:1; + /** slc1_token1_inc_more : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC1TOKEN1_SLC1_TOKEN1_WDATA to + * SDIO_SLC1TOKEN1_SLC1_TOKEN1. + */ + uint32_t slc1_token1_inc_more:1; + uint32_t reserved_15:1; + /** slc1_token1 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel1. + */ + uint32_t slc1_token1:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_slc1token1_reg_t; + +/** Type of slc_conf1 register + * Sdio slave DMA configuration1 register. + */ +typedef union { + struct { + /** slc0_check_owner : R/W; bitpos: [0]; default: 0; + * Set 1 to check the owner bit of descriptors used by dma channel0. + */ + uint32_t slc0_check_owner:1; + /** slc0_tx_check_sum_en : R/W; bitpos: [1]; default: 0; + * Set 1 to enable check sum function during slave receiving packets through dma + * channel0. + */ + uint32_t slc0_tx_check_sum_en:1; + /** slc0_rx_check_sum_en : R/W; bitpos: [2]; default: 0; + * Set 1 to enable check sum function during slave sending packets through dma + * channel0. + */ + uint32_t slc0_rx_check_sum_en:1; + /** sdio_cmd_hold_en : R/W; bitpos: [3]; default: 1; + * Allow host to send another cmd53 during last cmd53 operating time. + */ + uint32_t sdio_cmd_hold_en:1; + /** slc0_len_auto_clr : R/W; bitpos: [4]; default: 1; + * Set 1 to automatically clear the length of buffers used to send packets ot host + * after host reads this length. (not recommended to use,should be set to 0) + */ + uint32_t slc0_len_auto_clr:1; + /** slc0_tx_stitch_en : R/W; bitpos: [5]; default: 1; + * Set 1 to enable the stitch mode of dma channel0 receiving linked list . + */ + uint32_t slc0_tx_stitch_en:1; + /** slc0_rx_stitch_en : R/W; bitpos: [6]; default: 1; + * Set 1 to enable the stitch mode of dma channel0 sending linked list . + */ + uint32_t slc0_rx_stitch_en:1; + uint32_t reserved_7:9; + /** slc1_check_owner : R/W; bitpos: [16]; default: 0; + * Set 1 to check the owner bit of descriptors used by dma channel1. + */ + uint32_t slc1_check_owner:1; + /** slc1_tx_check_sum_en : R/W; bitpos: [17]; default: 0; + * Set 1 to enable check sum function during slave receiving packets through dma + * channel1. + */ + uint32_t slc1_tx_check_sum_en:1; + /** slc1_rx_check_sum_en : R/W; bitpos: [18]; default: 0; + * Set 1 to enable check sum function during slave sending packets through dma + * channel1. + */ + uint32_t slc1_rx_check_sum_en:1; + /** host_int_level_sel : R/W; bitpos: [19]; default: 0; + * Set the polarity of interrupt generated to host: 0-low active, 1-high active. + */ + uint32_t host_int_level_sel:1; + uint32_t reserved_20:2; + /** sdio_clk_en : R/W; bitpos: [22]; default: 0; + * Sdio slave dma registers' clock gating enable bit: 0-the sdio slave dma registers' + * clock is on during apb operation, 1- the sdio slave dma registers' clock is always + * on. + */ + uint32_t sdio_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} sdio_slc_conf1_reg_t; + +/** Type of slc_bridge_conf register + * Sdio slave DMA bridge configuration register. + */ +typedef union { + struct { + /** slc_txeof_ena : R/W; bitpos: [5:0]; default: 32; + * Configure the end-of-frame address of receiving packet. The priority from high to + * low is: if txeof_ena[0] is 1, end-of-frame address is 0xfff, if txeof_ena[1] is 1, + * end-of-frame address is 0x1fff, if txeof_ena[2] is 1, end-of-frame address is + * 0x3fff, if txeof_ena[3] is 1, end-of-frame address is 0x7fff, if txeof_ena[4] is 1, + * end-of-frame address is 0xffff, if txeof_ena[5] is 1, end-of-frame address is + * 0x1f7ff. Make sure the end-of-frame address is within the address range set by + * fifo_map_ena, otherwise the packet will be transferred without end-of-frame flag, + * which can cause unpredictable consequence. + */ + uint32_t slc_txeof_ena:6; + uint32_t reserved_6:2; + /** slc_fifo_map_ena : R/W; bitpos: [11:8]; default: 7; + * Configure the address range allocated to transfer packets using SDIO func1 and + * func2. The address range is from 0x400 to 0-0x3fff, 1-0x7fff, 3-0xffff, 7-0x1ffff, + * others-not allowed. + */ + uint32_t slc_fifo_map_ena:4; + /** slc0_tx_dummy_mode : R/W; bitpos: [12]; default: 1; + * Set 1 not to transfer check sum data into memory through dma channel0. + */ + uint32_t slc0_tx_dummy_mode:1; + /** slc_hda_map_128k : R/W; bitpos: [13]; default: 1; + * If hda_map_128k is 0, map high 4 bit address to hda_4msb. When hda_map_128k is 1, + * if hda_word_en (slchost_conf12[0]) is 0, map high 4 bit address to {hda_4msb[3:1], + * addr_ext_func[16]}. Else if hda_word_en is 1, map high 4 bit address to + * {hda_4msb[3:1], addr_ext_func[14]}. + */ + uint32_t slc_hda_map_128k:1; + /** slc1_tx_dummy_mode : R/W; bitpos: [14]; default: 1; + * Set 1 not to transfer check sum data into memory through dma channel1. + */ + uint32_t slc1_tx_dummy_mode:1; + uint32_t reserved_15:1; + /** slc_tx_push_idle_num : R/W; bitpos: [31:16]; default: 10; + * reserved + */ + uint32_t slc_tx_push_idle_num:16; + }; + uint32_t val; +} sdio_slc_bridge_conf_reg_t; + +/** Type of slc_slc0_to_eof_des_addr register + * Sdio slave DMA channel0 start address of sending linked list register. + */ +typedef union { + struct { + /** slc0_to_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last sent packet through dma channel0. + */ + uint32_t slc0_to_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_to_eof_des_addr_reg_t; + +/** Type of slc_slc0_tx_eof_des_addr register + * Sdio slave DMA channel0 receiving packet status register. + */ +typedef union { + struct { + /** slc0_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully received packet through dma + * channel0. + */ + uint32_t slc0_tx_suc_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_tx_eof_des_addr_reg_t; + +/** Type of slc_slc0_to_eof_bfr_des_addr register + * Sdio slave DMA channel0 start address of sending linked list register. + */ +typedef union { + struct { + /** slc0_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully sent buffer packet through dma + * channel0. + */ + uint32_t slc0_to_eof_bfr_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_to_eof_bfr_des_addr_reg_t; + +/** Type of slc_slc1_to_eof_des_addr register + * Sdio slave DMA channel1 start address of sending linked list register. + */ +typedef union { + struct { + /** slc1_to_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last sent packet through dma channel1. + */ + uint32_t slc1_to_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_to_eof_des_addr_reg_t; + +/** Type of slc_slc1_tx_eof_des_addr register + * Sdio slave DMA channel1 receiving packet status register. + */ +typedef union { + struct { + /** slc1_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully received packet through dma + * channel1. + */ + uint32_t slc1_tx_suc_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_tx_eof_des_addr_reg_t; + +/** Type of slc_slc1_to_eof_bfr_des_addr register + * Sdio slave DMA channel1 start address of sending linked list register. + */ +typedef union { + struct { + /** slc1_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully sent buffer packet through dma + * channel1. + */ + uint32_t slc1_to_eof_bfr_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_to_eof_bfr_des_addr_reg_t; + +/** Type of slc_rx_dscr_conf register + * Sdio slave sending descriptor configuration register. + */ +typedef union { + struct { + /** slc0_token_no_replace : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc0_token_no_replace:1; + /** slc0_infor_no_replace : R/W; bitpos: [1]; default: 1; + * reserved + */ + uint32_t slc0_infor_no_replace:1; + /** slc0_rx_fill_mode : R/W; bitpos: [2]; default: 0; + * slc0 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ + uint32_t slc0_rx_fill_mode:1; + /** slc0_rx_eof_mode : R/W; bitpos: [3]; default: 1; + * 0-slc0 rx_push_eof, 1-slc0 rx_pop_eof + */ + uint32_t slc0_rx_eof_mode:1; + /** slc0_rx_fill_en : R/W; bitpos: [4]; default: 1; + * reserved + */ + uint32_t slc0_rx_fill_en:1; + /** slc0_rd_retry_threshold : R/W; bitpos: [15:5]; default: 128; + * reserved + */ + uint32_t slc0_rd_retry_threshold:11; + /** slc1_token_no_replace : R/W; bitpos: [16]; default: 1; + * reserved + */ + uint32_t slc1_token_no_replace:1; + /** slc1_infor_no_replace : R/W; bitpos: [17]; default: 1; + * reserved + */ + uint32_t slc1_infor_no_replace:1; + /** slc1_rx_fill_mode : R/W; bitpos: [18]; default: 0; + * slc1 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ + uint32_t slc1_rx_fill_mode:1; + /** slc1_rx_eof_mode : R/W; bitpos: [19]; default: 1; + * 0-slc1 rx_push_eof, 1-slc1 rx_pop_eof + */ + uint32_t slc1_rx_eof_mode:1; + /** slc1_rx_fill_en : R/W; bitpos: [20]; default: 1; + * reserved + */ + uint32_t slc1_rx_fill_en:1; + /** slc1_rd_retry_threshold : R/W; bitpos: [31:21]; default: 128; + * reserved + */ + uint32_t slc1_rd_retry_threshold:11; + }; + uint32_t val; +} sdio_slc_rx_dscr_conf_reg_t; + +/** Type of slc_tx_dscr_conf register + * reserved + */ +typedef union { + struct { + /** slc_wr_retry_threshold : R/W; bitpos: [10:0]; default: 128; + * reserved + */ + uint32_t slc_wr_retry_threshold:11; + uint32_t reserved_11:21; + }; + uint32_t val; +} sdio_slc_tx_dscr_conf_reg_t; + +/** Type of slc_slc0_len_conf register + * reserved + */ +typedef union { + struct { + /** slc0_len_wdata : WT; bitpos: [19:0]; default: 0; + * The packet length sent by dma channel0. + */ + uint32_t slc0_len_wdata:20; + /** slc0_len_wr : WT; bitpos: [20]; default: 0; + * Set this bit to set SLC0_LEN as SDIO_SLC0_LEN_WDATA. + */ + uint32_t slc0_len_wr:1; + /** slc0_len_inc : WT; bitpos: [21]; default: 0; + * Set this bit to add 1 to SLC0_LEN. + */ + uint32_t slc0_len_inc:1; + /** slc0_len_inc_more : WT; bitpos: [22]; default: 0; + * Set this bit to add the value of SDIO_SLC0_LEN_WDATA to SLC0_LEN. + */ + uint32_t slc0_len_inc_more:1; + /** slc0_rx_packet_load_en : WT; bitpos: [23]; default: 0; + * Write 1 to stitch new linked lists to current linked lists when dma channel0 + * sending packets. + */ + uint32_t slc0_rx_packet_load_en:1; + /** slc0_tx_packet_load_en : WT; bitpos: [24]; default: 0; + * Write 1 to stitch new linked lists to current linked lists when dma channel0 + * receiving packets. + */ + uint32_t slc0_tx_packet_load_en:1; + /** slc0_rx_get_used_dscr : WT; bitpos: [25]; default: 0; + * Write 1 to get the current descriptor address when dma channel0 sending packets. + */ + uint32_t slc0_rx_get_used_dscr:1; + /** slc0_tx_get_used_dscr : WT; bitpos: [26]; default: 0; + * Write 1 to get the current descriptor address when dma channel0 receiving packets. + */ + uint32_t slc0_tx_get_used_dscr:1; + /** slc0_rx_new_pkt_ind : RO; bitpos: [27]; default: 0; + * Represents a new packet is sent by dma channel0. + */ + uint32_t slc0_rx_new_pkt_ind:1; + /** slc0_tx_new_pkt_ind : RO; bitpos: [28]; default: 1; + * Represents a new packet is received by dma channel0. + */ + uint32_t slc0_tx_new_pkt_ind:1; + /** slc0_rx_packet_load_en_st : R/WTC/SC; bitpos: [29]; default: 0; + * Represents whether the dma channel0 can be stitched to new linked lists when + * sending packets. 0- allowed, 1- not allowed. + */ + uint32_t slc0_rx_packet_load_en_st:1; + /** slc0_tx_packet_load_en_st : R/WTC/SC; bitpos: [30]; default: 0; + * Represents whether the dma channel0 can be stitched to new linked lists when + * receiving packets. 0- allowed, 1- not allowed. + */ + uint32_t slc0_tx_packet_load_en_st:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} sdio_slc_slc0_len_conf_reg_t; + +/** Type of slc_slc0_txpkt_h_dscr register + * Sdio slave DMA channel0 start address of receiving linked list register. + */ +typedef union { + struct { + /** slc0_tx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * Configure the start address of receiving linked list to be stitched to the current + * linked list of dma channel0. + */ + uint32_t slc0_tx_pkt_h_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_txpkt_h_dscr_reg_t; + +/** Type of slc_slc0_txpkt_e_dscr register + * Sdio slave DMA channel0 end address of receiving linked list register. + */ +typedef union { + struct { + /** slc0_tx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * Configure end address of receiving linked list to be stitched to the current linked + * list of dma channel0. + */ + uint32_t slc0_tx_pkt_e_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_txpkt_e_dscr_reg_t; + +/** Type of slc_slc0_rxpkt_h_dscr register + * Sdio slave DMA channel0 start address of sending linked list register. + */ +typedef union { + struct { + /** slc0_rx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * Configure the start address of sending linked list to be stitched to the current + * linked list of dma channel0. + */ + uint32_t slc0_rx_pkt_h_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_rxpkt_h_dscr_reg_t; + +/** Type of slc_slc0_rxpkt_e_dscr register + * Sdio slave DMA channel0 end address of sending linked list register. + */ +typedef union { + struct { + /** slc0_rx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * Configure the end address of sending linked list to be stitched to the current + * linked list of dma channel0. + */ + uint32_t slc0_rx_pkt_e_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_rxpkt_e_dscr_reg_t; + +/** Type of slc_slc0_txpktu_h_dscr register + * Sdio slave DMA channel0 start address of receiving linked list status register. + */ +typedef union { + struct { + /** slc0_tx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last received packet through dma + * channel0. + */ + uint32_t slc0_tx_pkt_start_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_txpktu_h_dscr_reg_t; + +/** Type of slc_slc0_txpktu_e_dscr register + * Sdio slave DMA channel0 end address of receiving linked list status register. + */ +typedef union { + struct { + /** slc0_tx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0; + * The end address of the linked list of the last received packet through dma channel0. + */ + uint32_t slc0_tx_pkt_end_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_txpktu_e_dscr_reg_t; + +/** Type of slc_slc0_rxpktu_h_dscr register + * Sdio slave DMA channel0 start address of sending linked list status register. + */ +typedef union { + struct { + /** slc0_rx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last sent packet through dma channel0. + */ + uint32_t slc0_rx_pkt_start_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_rxpktu_h_dscr_reg_t; + +/** Type of slc_slc0_rxpktu_e_dscr register + * Sdio slave DMA channel0 end address of sending linked list status register. + */ +typedef union { + struct { + /** slc0_rx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0; + * The end address of the linked list of the last sent packet through dma channel0. + */ + uint32_t slc0_rx_pkt_end_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_rxpktu_e_dscr_reg_t; + +/** Type of slc_seq_position register + * The position of receiving packet configuration register. + */ +typedef union { + struct { + /** slc0_seq_position : R/W; bitpos: [7:0]; default: 9; + * Configure the position of the receiving packet through dma channel0. + */ + uint32_t slc0_seq_position:8; + /** slc1_seq_position : R/W; bitpos: [15:8]; default: 5; + * Configure the position of the receiving packet through dma channel1. + */ + uint32_t slc1_seq_position:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} sdio_slc_seq_position_reg_t; + +/** Type of slc_slc0_dscr_rec_conf register + * Sdio slave DMA sending linked list limit configuration register. + */ +typedef union { + struct { + /** slc0_rx_dscr_rec_lim : R/W; bitpos: [9:0]; default: 1023; + * Configure the limit number of descriptors used to send one packet through dma + * channel0 in stitch mode. + */ + uint32_t slc0_rx_dscr_rec_lim:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} sdio_slc_slc0_dscr_rec_conf_reg_t; + +/** Type of slc_sdio_crc_st1 register + * Sdio slave receiving command crc status register. + */ +typedef union { + struct { + /** cmd_crc_err_cnt : RO; bitpos: [7:0]; default: 0; + * The count value of received command crc errors. + */ + uint32_t cmd_crc_err_cnt:8; + uint32_t reserved_8:23; + /** err_cnt_clr : R/W; bitpos: [31]; default: 0; + * Set 1 to clear the cmd_crc_err_cnt, dat0_crc_err_cnt, dat1_crc_err_cnt, + * dat2_crc_err_cnt and dat3_crc_err_cnt. + */ + uint32_t err_cnt_clr:1; + }; + uint32_t val; +} sdio_slc_sdio_crc_st1_reg_t; + +/** Type of slc_slc0_len_lim_conf register + * Sdio slave DMA channel0 buffer limit configuration register. + */ +typedef union { + struct { + /** slc0_len_lim : R/W; bitpos: [19:0]; default: 21504; + * Every time when the number of buffers loaded for sending packets reaches the number + * of slc0_len_lim, the current number of buffers loaded is saved into the registers + * of slc0_len0, slc0_len1 and slc0_len2. + */ + uint32_t slc0_len_lim:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} sdio_slc_slc0_len_lim_conf_reg_t; + +/** Type of slc_slc0_tx_sharemem_start register + * Sdio slave DMA channel0 address range of receiving linked list register. + */ +typedef union { + struct { + /** sdio_slc0_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to receive packet through dma + * channel0. + */ + uint32_t sdio_slc0_tx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_tx_sharemem_start_reg_t; + +/** Type of slc_slc0_tx_sharemem_end register + * Sdio slave DMA channel0 address range of receiving linked list register1. + */ +typedef union { + struct { + /** sdio_slc0_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to receive packet through dma + * channel0. + */ + uint32_t sdio_slc0_tx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_tx_sharemem_end_reg_t; + +/** Type of slc_slc0_rx_sharemem_start register + * Sdio slave DMA channel0 address range of sending linked list register. + */ +typedef union { + struct { + /** sdio_slc0_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to send packet through dma + * channel0. + */ + uint32_t sdio_slc0_rx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_rx_sharemem_start_reg_t; + +/** Type of slc_slc0_rx_sharemem_end register + * Sdio slave DMA channel0 address range of sending linked list register1. + */ +typedef union { + struct { + /** sdio_slc0_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to send packet through dma + * channel0. + */ + uint32_t sdio_slc0_rx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_rx_sharemem_end_reg_t; + +/** Type of slc_slc1_tx_sharemem_start register + * Sdio slave DMA channel1 address range of receiving linked list register. + */ +typedef union { + struct { + /** sdio_slc1_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to receive packet through dma + * channel1. + */ + uint32_t sdio_slc1_tx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_tx_sharemem_start_reg_t; + +/** Type of slc_slc1_tx_sharemem_end register + * Sdio slave DMA channel1 address range of receiving linked list register1. + */ +typedef union { + struct { + /** sdio_slc1_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to receive packet through dma + * channel1. + */ + uint32_t sdio_slc1_tx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_tx_sharemem_end_reg_t; + +/** Type of slc_slc1_rx_sharemem_start register + * Sdio slave DMA channel1 address range of sending linked list register. + */ +typedef union { + struct { + /** sdio_slc1_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to send packet through dma + * channel1. + */ + uint32_t sdio_slc1_rx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_rx_sharemem_start_reg_t; + +/** Type of slc_slc1_rx_sharemem_end register + * Sdio slave DMA channel1 address range of sending linked list register1. + */ +typedef union { + struct { + /** sdio_slc1_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to send packet through dma + * channel1. + */ + uint32_t sdio_slc1_rx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_rx_sharemem_end_reg_t; + +/** Type of slc_hda_tx_sharemem_start register + * Sdio slave HAD receiving address range register. + */ +typedef union { + struct { + /** sdio_hda_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * Use 31 to 20 bit of this field as the higher 20 bits of 32-bit address for HAD + * receiving packets. + */ + uint32_t sdio_hda_tx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc_hda_tx_sharemem_start_reg_t; + +/** Type of slc_hda_rx_sharemem_start register + * Sdio slave HAD sending address range register. + */ +typedef union { + struct { + /** sdio_hda_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * Use 31 to 20 bit of this field as the higher 20 bits of 32-bit address for HAD + * sending packets. + */ + uint32_t sdio_hda_rx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc_hda_rx_sharemem_start_reg_t; + +/** Type of slc_burst_len register + * Sdio slave AHB burst type configuration register. + */ +typedef union { + struct { + /** slc0_txdata_burst_len : R/W; bitpos: [0]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ + uint32_t slc0_txdata_burst_len:1; + /** slc0_rxdata_burst_len : R/W; bitpos: [1]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ + uint32_t slc0_rxdata_burst_len:1; + /** slc1_txdata_burst_len : R/W; bitpos: [2]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ + uint32_t slc1_txdata_burst_len:1; + /** slc1_rxdata_burst_len : R/W; bitpos: [3]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ + uint32_t slc1_rxdata_burst_len:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} sdio_slc_burst_len_reg_t; + + +/** Group: Interrupt registers */ +/** Type of slc_slc0int_raw register + * Sdio slave DMA channel0 raw interrupt status register. + */ +typedef union { + struct { + /** slc_frhost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit 0 for host to interrupt slave. + */ + uint32_t slc_frhost_bit0_int_raw:1; + /** slc_frhost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit 1 for host to interrupt slave. + */ + uint32_t slc_frhost_bit1_int_raw:1; + /** slc_frhost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit 2 for host to interrupt slave. + */ + uint32_t slc_frhost_bit2_int_raw:1; + /** slc_frhost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit 3 for host to interrupt slave. + */ + uint32_t slc_frhost_bit3_int_raw:1; + /** slc_frhost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit 4 for host to interrupt slave. + */ + uint32_t slc_frhost_bit4_int_raw:1; + /** slc_frhost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit 5 for host to interrupt slave. + */ + uint32_t slc_frhost_bit5_int_raw:1; + /** slc_frhost_bit6_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit 6 for host to interrupt slave. + */ + uint32_t slc_frhost_bit6_int_raw:1; + /** slc_frhost_bit7_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit 7 for host to interrupt slave. + */ + uint32_t slc_frhost_bit7_int_raw:1; + /** slc0_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit of registering dma channel0 sending initialization + */ + uint32_t slc0_rx_start_int_raw:1; + /** slc0_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit of registering dma channel0 receiving initialization + */ + uint32_t slc0_tx_start_int_raw:1; + /** slc0_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit of dma channel0 sending buffer underflow. + */ + uint32_t slc0_rx_udf_int_raw:1; + /** slc0_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit of dma channel0 receiving buffer overflow. + */ + uint32_t slc0_tx_ovf_int_raw:1; + /** slc0_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit for the value of slc0_token0 becoming to zero. + */ + uint32_t slc0_token0_1to0_int_raw:1; + /** slc0_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit for the value of slc0_token1 becoming to zero. + */ + uint32_t slc0_token1_1to0_int_raw:1; + /** slc0_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit of dma channel0 finishing receiving data to one single buffer. + */ + uint32_t slc0_tx_done_int_raw:1; + /** slc0_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit of dma channel0 finishing receiving data + */ + uint32_t slc0_tx_suc_eof_int_raw:1; + /** slc0_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt bit of dma channel0 finishing sending data from one single buffer + */ + uint32_t slc0_rx_done_int_raw:1; + /** slc0_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt bit of dma channel0 finishing sending data + */ + uint32_t slc0_rx_eof_int_raw:1; + /** slc0_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw interrupt bit for slave generating interrupt to host. + */ + uint32_t slc0_tohost_int_raw:1; + /** slc0_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt bit of dma channel0 receiving descriptor error. + */ + uint32_t slc0_tx_dscr_err_int_raw:1; + /** slc0_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt bit of dma channel0 sending descriptor error. + */ + uint32_t slc0_rx_dscr_err_int_raw:1; + /** slc0_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * The raw interrupt bit of not enough buffer for slave receiving data from host + * through dma channel0. + */ + uint32_t slc0_tx_dscr_empty_int_raw:1; + /** slc0_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * The raw interrupt bit for host to acknowledge retrying receiving data from slave + * successfully through dma channel0. + */ + uint32_t slc0_host_rd_ack_int_raw:1; + /** slc0_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * The raw interrupt bit of host finishing retrying sending data to slave through dma + * channel0. + */ + uint32_t slc0_wr_retry_done_int_raw:1; + /** slc0_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * The raw interrupt bit of data error during host sending data to slave through dma + * channel0. + */ + uint32_t slc0_tx_err_eof_int_raw:1; + /** cmd_dtc_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * The raw interrupt bit for sdio slave to detect command from host. + */ + uint32_t cmd_dtc_int_raw:1; + /** slc0_rx_quick_eof_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * The raw interrupt for the linked list used reaches the number of + * slc0_rx_dscr_rec_lim when in stitch mode, or for every sending data transfer done. + */ + uint32_t slc0_rx_quick_eof_int_raw:1; + /** slc0_host_pop_eof_err_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * The raw interrupt bit for the eof bit error of slave receiving data through dma + * channel0. + */ + uint32_t slc0_host_pop_eof_err_int_raw:1; + /** hda_recv_done_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * The raw interrupt bit for slave finishes receiving one cmd53 function's all block + * data. + */ + uint32_t hda_recv_done_int_raw:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_slc0int_raw_reg_t; + +/** Type of slc_slc0int_st register + * Sdio slave DMA channel0 masked interrupt status register. + */ +typedef union { + struct { + /** slc_frhost_bit0_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT0_INT interrupt. + */ + uint32_t slc_frhost_bit0_int_st:1; + /** slc_frhost_bit1_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT1_INT interrupt. + */ + uint32_t slc_frhost_bit1_int_st:1; + /** slc_frhost_bit2_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT2_INT interrupt. + */ + uint32_t slc_frhost_bit2_int_st:1; + /** slc_frhost_bit3_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT3_INT interrupt. + */ + uint32_t slc_frhost_bit3_int_st:1; + /** slc_frhost_bit4_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT4_INT interrupt. + */ + uint32_t slc_frhost_bit4_int_st:1; + /** slc_frhost_bit5_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT5_INT interrupt. + */ + uint32_t slc_frhost_bit5_int_st:1; + /** slc_frhost_bit6_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT6_INT interrupt. + */ + uint32_t slc_frhost_bit6_int_st:1; + /** slc_frhost_bit7_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT7_INT interrupt. + */ + uint32_t slc_frhost_bit7_int_st:1; + /** slc0_rx_start_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for SLC0_RX_START_INT_ST interrupt. + */ + uint32_t slc0_rx_start_int_st:1; + /** slc0_tx_start_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for SLC0_TX_START_INT_ST interrupt. + */ + uint32_t slc0_tx_start_int_st:1; + /** slc0_rx_udf_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for SLC0_RX_UDF_INT interrupt. + */ + uint32_t slc0_rx_udf_int_st:1; + /** slc0_tx_ovf_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for SLC0_TX_OVF_INT interrupt. + */ + uint32_t slc0_tx_ovf_int_st:1; + /** slc0_token0_1to0_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for SLC0_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc0_token0_1to0_int_st:1; + /** slc0_token1_1to0_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for SLC0_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc0_token1_1to0_int_st:1; + /** slc0_tx_done_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for SLC0_TX_DONE_INT_ST interrupt. + */ + uint32_t slc0_tx_done_int_st:1; + /** slc0_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for SLC0_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc0_tx_suc_eof_int_st:1; + /** slc0_rx_done_int_st : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for SLC0_RX_DONE_INT interrupt. + */ + uint32_t slc0_rx_done_int_st:1; + /** slc0_rx_eof_int_st : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for SLC0_RX_EOF_INT interrupt. + */ + uint32_t slc0_rx_eof_int_st:1; + /** slc0_tohost_int_st : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for SLC0_TOHOST_INT interrupt. + */ + uint32_t slc0_tohost_int_st:1; + /** slc0_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit for SLC0_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_tx_dscr_err_int_st:1; + /** slc0_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit for SLC0_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_rx_dscr_err_int_st:1; + /** slc0_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc0_tx_dscr_empty_int_st:1; + /** slc0_host_rd_ack_int_st : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit for SLC0_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc0_host_rd_ack_int_st:1; + /** slc0_wr_retry_done_int_st : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit for SLC0_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc0_wr_retry_done_int_st:1; + /** slc0_tx_err_eof_int_st : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit for SLC0_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc0_tx_err_eof_int_st:1; + /** cmd_dtc_int_st : RO; bitpos: [25]; default: 0; + * The masked interrupt status bit for CMD_DTC_INT interrupt. + */ + uint32_t cmd_dtc_int_st:1; + /** slc0_rx_quick_eof_int_st : RO; bitpos: [26]; default: 0; + * The masked interrupt status bit for SLC0_RX_QUICK_EOF_INT interrupt. + */ + uint32_t slc0_rx_quick_eof_int_st:1; + /** slc0_host_pop_eof_err_int_st : RO; bitpos: [27]; default: 0; + * The masked interrupt status bit for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ + uint32_t slc0_host_pop_eof_err_int_st:1; + /** hda_recv_done_int_st : RO; bitpos: [28]; default: 0; + * The masked interrupt status bit for HDA_RECV_DONE_INT interrupt. + */ + uint32_t hda_recv_done_int_st:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_slc0int_st_reg_t; + +/** Type of slc_slc0int_ena register + * Sdio slave DMA channel0 interrupt enable register. + */ +typedef union { + struct { + /** slc_frhost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT0_INT interrupt. + */ + uint32_t slc_frhost_bit0_int_ena:1; + /** slc_frhost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT1_INT interrupt. + */ + uint32_t slc_frhost_bit1_int_ena:1; + /** slc_frhost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT2_INT interrupt. + */ + uint32_t slc_frhost_bit2_int_ena:1; + /** slc_frhost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT3_INT interrupt. + */ + uint32_t slc_frhost_bit3_int_ena:1; + /** slc_frhost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT4_INT interrupt. + */ + uint32_t slc_frhost_bit4_int_ena:1; + /** slc_frhost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT5_INT interrupt. + */ + uint32_t slc_frhost_bit5_int_ena:1; + /** slc_frhost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT6_INT interrupt. + */ + uint32_t slc_frhost_bit6_int_ena:1; + /** slc_frhost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT7_INT interrupt. + */ + uint32_t slc_frhost_bit7_int_ena:1; + /** slc0_rx_start_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for SLC0_RX_START_INT_ST interrupt. + */ + uint32_t slc0_rx_start_int_ena:1; + /** slc0_tx_start_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for SLC0_TX_START_INT_ST interrupt. + */ + uint32_t slc0_tx_start_int_ena:1; + /** slc0_rx_udf_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for SLC0_RX_UDF_INT interrupt. + */ + uint32_t slc0_rx_udf_int_ena:1; + /** slc0_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for SLC0_TX_OVF_INT interrupt. + */ + uint32_t slc0_tx_ovf_int_ena:1; + /** slc0_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for SLC0_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc0_token0_1to0_int_ena:1; + /** slc0_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for SLC0_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc0_token1_1to0_int_ena:1; + /** slc0_tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for SLC0_TX_DONE_INT_ST interrupt. + */ + uint32_t slc0_tx_done_int_ena:1; + /** slc0_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for SLC0_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc0_tx_suc_eof_int_ena:1; + /** slc0_rx_done_int_ena : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for SLC0_RX_DONE_INT interrupt. + */ + uint32_t slc0_rx_done_int_ena:1; + /** slc0_rx_eof_int_ena : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for SLC0_RX_EOF_INT interrupt. + */ + uint32_t slc0_rx_eof_int_ena:1; + /** slc0_tohost_int_ena : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for SLC0_TOHOST_INT interrupt. + */ + uint32_t slc0_tohost_int_ena:1; + /** slc0_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for SLC0_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_tx_dscr_err_int_ena:1; + /** slc0_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit for SLC0_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_rx_dscr_err_int_ena:1; + /** slc0_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc0_tx_dscr_empty_int_ena:1; + /** slc0_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit for SLC0_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc0_host_rd_ack_int_ena:1; + /** slc0_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit for SLC0_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc0_wr_retry_done_int_ena:1; + /** slc0_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit for SLC0_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc0_tx_err_eof_int_ena:1; + /** cmd_dtc_int_ena : R/W; bitpos: [25]; default: 0; + * The interrupt enable bit for CMD_DTC_INT interrupt. + */ + uint32_t cmd_dtc_int_ena:1; + /** slc0_rx_quick_eof_int_ena : R/W; bitpos: [26]; default: 0; + * The interrupt enable bit for SLC0_RX_QUICK_EOF_INT interrupt. + */ + uint32_t slc0_rx_quick_eof_int_ena:1; + /** slc0_host_pop_eof_err_int_ena : R/W; bitpos: [27]; default: 0; + * The interrupt enable bit for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ + uint32_t slc0_host_pop_eof_err_int_ena:1; + /** hda_recv_done_int_ena : R/W; bitpos: [28]; default: 0; + * The interrupt enable bit for HDA_RECV_DONE_INT interrupt. + */ + uint32_t hda_recv_done_int_ena:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_slc0int_ena_reg_t; + +/** Type of slc_slc0int_clr register + * Sdio slave DMA channel0 interrupt clear register. + */ +typedef union { + struct { + /** slc_frhost_bit0_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT0_INT interrupt. + */ + uint32_t slc_frhost_bit0_int_clr:1; + /** slc_frhost_bit1_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT1_INT interrupt. + */ + uint32_t slc_frhost_bit1_int_clr:1; + /** slc_frhost_bit2_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT2_INT interrupt. + */ + uint32_t slc_frhost_bit2_int_clr:1; + /** slc_frhost_bit3_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT3_INT interrupt. + */ + uint32_t slc_frhost_bit3_int_clr:1; + /** slc_frhost_bit4_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT4_INT interrupt. + */ + uint32_t slc_frhost_bit4_int_clr:1; + /** slc_frhost_bit5_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT5_INT interrupt. + */ + uint32_t slc_frhost_bit5_int_clr:1; + /** slc_frhost_bit6_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT6_INT interrupt. + */ + uint32_t slc_frhost_bit6_int_clr:1; + /** slc_frhost_bit7_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT7_INT interrupt. + */ + uint32_t slc_frhost_bit7_int_clr:1; + /** slc0_rx_start_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear SLC0_RX_START_INT_ST interrupt. + */ + uint32_t slc0_rx_start_int_clr:1; + /** slc0_tx_start_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear SLC0_TX_START_INT_ST interrupt. + */ + uint32_t slc0_tx_start_int_clr:1; + /** slc0_rx_udf_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear SLC0_RX_UDF_INT interrupt. + */ + uint32_t slc0_rx_udf_int_clr:1; + /** slc0_tx_ovf_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear SLC0_TX_OVF_INT interrupt. + */ + uint32_t slc0_tx_ovf_int_clr:1; + /** slc0_token0_1to0_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear SLC0_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc0_token0_1to0_int_clr:1; + /** slc0_token1_1to0_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear SLC0_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc0_token1_1to0_int_clr:1; + /** slc0_tx_done_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear SLC0_TX_DONE_INT_ST interrupt. + */ + uint32_t slc0_tx_done_int_clr:1; + /** slc0_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear SLC0_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc0_tx_suc_eof_int_clr:1; + /** slc0_rx_done_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear SLC0_RX_DONE_INT interrupt. + */ + uint32_t slc0_rx_done_int_clr:1; + /** slc0_rx_eof_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear SLC0_RX_EOF_INT interrupt. + */ + uint32_t slc0_rx_eof_int_clr:1; + /** slc0_tohost_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear SLC0_TOHOST_INT interrupt. + */ + uint32_t slc0_tohost_int_clr:1; + /** slc0_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear SLC0_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_tx_dscr_err_int_clr:1; + /** slc0_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0; + * Set this bit to clear SLC0_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_rx_dscr_err_int_clr:1; + /** slc0_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0; + * Set this bit to clear SLC0_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc0_tx_dscr_empty_int_clr:1; + /** slc0_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0; + * Set this bit to clear SLC0_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc0_host_rd_ack_int_clr:1; + /** slc0_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0; + * Set this bit to clear SLC0_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc0_wr_retry_done_int_clr:1; + /** slc0_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0; + * Set this bit to clear SLC0_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc0_tx_err_eof_int_clr:1; + /** cmd_dtc_int_clr : WT; bitpos: [25]; default: 0; + * Set this bit to clear CMD_DTC_INT interrupt. + */ + uint32_t cmd_dtc_int_clr:1; + /** slc0_rx_quick_eof_int_clr : WT; bitpos: [26]; default: 0; + * Set this bit to clear SLC0_RX_QUICK_EOF_INT interrupt. + */ + uint32_t slc0_rx_quick_eof_int_clr:1; + /** slc0_host_pop_eof_err_int_clr : WT; bitpos: [27]; default: 0; + * Set this bit to clear SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ + uint32_t slc0_host_pop_eof_err_int_clr:1; + /** hda_recv_done_int_clr : WT; bitpos: [28]; default: 0; + * Set this bit to clear HDA_RECV_DONE_INT interrupt. + */ + uint32_t hda_recv_done_int_clr:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_slc0int_clr_reg_t; + +/** Type of slc_slc1int_raw register + * Sdio slave DMA channel1 raw interrupt status register. + */ +typedef union { + struct { + /** slc_frhost_bit8_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit 8 for host to interrupt slave. + */ + uint32_t slc_frhost_bit8_int_raw:1; + /** slc_frhost_bit9_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit 9 for host to interrupt slave. + */ + uint32_t slc_frhost_bit9_int_raw:1; + /** slc_frhost_bit10_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit 10 for host to interrupt slave. + */ + uint32_t slc_frhost_bit10_int_raw:1; + /** slc_frhost_bit11_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit 11 for host to interrupt slave. + */ + uint32_t slc_frhost_bit11_int_raw:1; + /** slc_frhost_bit12_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit 12 for host to interrupt slave. + */ + uint32_t slc_frhost_bit12_int_raw:1; + /** slc_frhost_bit13_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit 13 for host to interrupt slave. + */ + uint32_t slc_frhost_bit13_int_raw:1; + /** slc_frhost_bit14_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit 14 for host to interrupt slave. + */ + uint32_t slc_frhost_bit14_int_raw:1; + /** slc_frhost_bit15_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit 15 for host to interrupt slave. + */ + uint32_t slc_frhost_bit15_int_raw:1; + /** slc1_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit of registering dma channel1 sending initialization + */ + uint32_t slc1_rx_start_int_raw:1; + /** slc1_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit of registering dma channel1 receiving initialization + */ + uint32_t slc1_tx_start_int_raw:1; + /** slc1_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit of dma channel1 sending buffer underflow. + */ + uint32_t slc1_rx_udf_int_raw:1; + /** slc1_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit of dma channel1 receiving buffer overflow. + */ + uint32_t slc1_tx_ovf_int_raw:1; + /** slc1_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit for the value of slc0_token0 becoming to zero. + */ + uint32_t slc1_token0_1to0_int_raw:1; + /** slc1_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit for the value of slc0_token1 becoming to zero. + */ + uint32_t slc1_token1_1to0_int_raw:1; + /** slc1_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit of dma channel1 finishing receiving data to one single buffer. + */ + uint32_t slc1_tx_done_int_raw:1; + /** slc1_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit of dma channel1 finishing receiving data + */ + uint32_t slc1_tx_suc_eof_int_raw:1; + /** slc1_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt bit of dma channel1 finishing sending data from one single buffer + */ + uint32_t slc1_rx_done_int_raw:1; + /** slc1_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt bit of dma channel1 finishing sending data + */ + uint32_t slc1_rx_eof_int_raw:1; + /** slc1_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw interrupt bit for slave generating interrupt to host. + */ + uint32_t slc1_tohost_int_raw:1; + /** slc1_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt bit of dma channel1 receiving descriptor error. + */ + uint32_t slc1_tx_dscr_err_int_raw:1; + /** slc1_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt bit of dma channel1 sending descriptor error. + */ + uint32_t slc1_rx_dscr_err_int_raw:1; + /** slc1_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * The raw interrupt bit of not enough buffer for slave receiving data from host + * through dma channel1. + */ + uint32_t slc1_tx_dscr_empty_int_raw:1; + /** slc1_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * The raw interrupt bit for host to acknowledge retrying receiving data from slave + * successfully through dma channel1. + */ + uint32_t slc1_host_rd_ack_int_raw:1; + /** slc1_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * The raw interrupt bit of host finishing retrying sending data to slave through dma + * channel1. + */ + uint32_t slc1_wr_retry_done_int_raw:1; + /** slc1_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * The raw interrupt bit of data error during host sending data to slave through dma + * channel1. + */ + uint32_t slc1_tx_err_eof_int_raw:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_slc1int_raw_reg_t; + +/** Type of slc_slc1int_st register + * Sdio slave DMA channel1 masked interrupt status register. + */ +typedef union { + struct { + /** slc_frhost_bit8_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT0_INT interrupt. + */ + uint32_t slc_frhost_bit8_int_st:1; + /** slc_frhost_bit9_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT1_INT interrupt. + */ + uint32_t slc_frhost_bit9_int_st:1; + /** slc_frhost_bit10_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT2_INT interrupt. + */ + uint32_t slc_frhost_bit10_int_st:1; + /** slc_frhost_bit11_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT3_INT interrupt. + */ + uint32_t slc_frhost_bit11_int_st:1; + /** slc_frhost_bit12_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT4_INT interrupt. + */ + uint32_t slc_frhost_bit12_int_st:1; + /** slc_frhost_bit13_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT5_INT interrupt. + */ + uint32_t slc_frhost_bit13_int_st:1; + /** slc_frhost_bit14_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT6_INT interrupt. + */ + uint32_t slc_frhost_bit14_int_st:1; + /** slc_frhost_bit15_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT7_INT interrupt. + */ + uint32_t slc_frhost_bit15_int_st:1; + /** slc1_rx_start_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for SLC1_RX_START_INT_ST interrupt. + */ + uint32_t slc1_rx_start_int_st:1; + /** slc1_tx_start_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for SLC1_TX_START_INT_ST interrupt. + */ + uint32_t slc1_tx_start_int_st:1; + /** slc1_rx_udf_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for SLC1_RX_UDF_INT interrupt. + */ + uint32_t slc1_rx_udf_int_st:1; + /** slc1_tx_ovf_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for SLC1_TX_OVF_INT interrupt. + */ + uint32_t slc1_tx_ovf_int_st:1; + /** slc1_token0_1to0_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for SLC1_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc1_token0_1to0_int_st:1; + /** slc1_token1_1to0_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for SLC1_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc1_token1_1to0_int_st:1; + /** slc1_tx_done_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for SLC1_TX_DONE_INT_ST interrupt. + */ + uint32_t slc1_tx_done_int_st:1; + /** slc1_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for SLC1_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc1_tx_suc_eof_int_st:1; + /** slc1_rx_done_int_st : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for SLC1_RX_DONE_INT interrupt. + */ + uint32_t slc1_rx_done_int_st:1; + /** slc1_rx_eof_int_st : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for SLC1_RX_EOF_INT interrupt. + */ + uint32_t slc1_rx_eof_int_st:1; + /** slc1_tohost_int_st : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for SLC1_TOHOST_INT interrupt. + */ + uint32_t slc1_tohost_int_st:1; + /** slc1_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit for SLC1_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_tx_dscr_err_int_st:1; + /** slc1_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit for SLC1_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_rx_dscr_err_int_st:1; + /** slc1_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit for SLC1_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc1_tx_dscr_empty_int_st:1; + /** slc1_host_rd_ack_int_st : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit for SLC1_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc1_host_rd_ack_int_st:1; + /** slc1_wr_retry_done_int_st : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit for SLC1_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc1_wr_retry_done_int_st:1; + /** slc1_tx_err_eof_int_st : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit for SLC1_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc1_tx_err_eof_int_st:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_slc1int_st_reg_t; + +/** Type of slc_slc1int_ena register + * Sdio slave DMA channel1 interrupt enable register. + */ +typedef union { + struct { + /** slc_frhost_bit8_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT0_INT interrupt. + */ + uint32_t slc_frhost_bit8_int_ena:1; + /** slc_frhost_bit9_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT1_INT interrupt. + */ + uint32_t slc_frhost_bit9_int_ena:1; + /** slc_frhost_bit10_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT2_INT interrupt. + */ + uint32_t slc_frhost_bit10_int_ena:1; + /** slc_frhost_bit11_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT3_INT interrupt. + */ + uint32_t slc_frhost_bit11_int_ena:1; + /** slc_frhost_bit12_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT4_INT interrupt. + */ + uint32_t slc_frhost_bit12_int_ena:1; + /** slc_frhost_bit13_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT5_INT interrupt. + */ + uint32_t slc_frhost_bit13_int_ena:1; + /** slc_frhost_bit14_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT6_INT interrupt. + */ + uint32_t slc_frhost_bit14_int_ena:1; + /** slc_frhost_bit15_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT7_INT interrupt. + */ + uint32_t slc_frhost_bit15_int_ena:1; + /** slc1_rx_start_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for SCL1_RX_START_INT_ST interrupt. + */ + uint32_t slc1_rx_start_int_ena:1; + /** slc1_tx_start_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for SCL1_TX_START_INT_ST interrupt. + */ + uint32_t slc1_tx_start_int_ena:1; + /** slc1_rx_udf_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for SCL1_RX_UDF_INT interrupt. + */ + uint32_t slc1_rx_udf_int_ena:1; + /** slc1_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for SCL1_TX_OVF_INT interrupt. + */ + uint32_t slc1_tx_ovf_int_ena:1; + /** slc1_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for SCL1_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc1_token0_1to0_int_ena:1; + /** slc1_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for SCL1_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc1_token1_1to0_int_ena:1; + /** slc1_tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for SCL1_TX_DONE_INT_ST interrupt. + */ + uint32_t slc1_tx_done_int_ena:1; + /** slc1_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for SCL1_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc1_tx_suc_eof_int_ena:1; + /** slc1_rx_done_int_ena : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for SCL1_RX_DONE_INT interrupt. + */ + uint32_t slc1_rx_done_int_ena:1; + /** slc1_rx_eof_int_ena : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for SCL1_RX_EOF_INT interrupt. + */ + uint32_t slc1_rx_eof_int_ena:1; + /** slc1_tohost_int_ena : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for SCL1_TOHOST_INT interrupt. + */ + uint32_t slc1_tohost_int_ena:1; + /** slc1_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for SCL1_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_tx_dscr_err_int_ena:1; + /** slc1_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit for SCL1_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_rx_dscr_err_int_ena:1; + /** slc1_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit for SCL1_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc1_tx_dscr_empty_int_ena:1; + /** slc1_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit for SCL1_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc1_host_rd_ack_int_ena:1; + /** slc1_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit for SCL1_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc1_wr_retry_done_int_ena:1; + /** slc1_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit for SCL1_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc1_tx_err_eof_int_ena:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_slc1int_ena_reg_t; + +/** Type of slc_slc1int_clr register + * Sdio slave DMA channel1 interrupt clear register. + */ +typedef union { + struct { + /** slc_frhost_bit8_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT0_INT interrupt. + */ + uint32_t slc_frhost_bit8_int_clr:1; + /** slc_frhost_bit9_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT1_INT interrupt. + */ + uint32_t slc_frhost_bit9_int_clr:1; + /** slc_frhost_bit10_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT2_INT interrupt. + */ + uint32_t slc_frhost_bit10_int_clr:1; + /** slc_frhost_bit11_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT3_INT interrupt. + */ + uint32_t slc_frhost_bit11_int_clr:1; + /** slc_frhost_bit12_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT4_INT interrupt. + */ + uint32_t slc_frhost_bit12_int_clr:1; + /** slc_frhost_bit13_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT5_INT interrupt. + */ + uint32_t slc_frhost_bit13_int_clr:1; + /** slc_frhost_bit14_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT6_INT interrupt. + */ + uint32_t slc_frhost_bit14_int_clr:1; + /** slc_frhost_bit15_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT7_INT interrupt. + */ + uint32_t slc_frhost_bit15_int_clr:1; + /** slc1_rx_start_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear SLC1_RX_START_INT_ST interrupt. + */ + uint32_t slc1_rx_start_int_clr:1; + /** slc1_tx_start_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear SLC1_TX_START_INT_ST interrupt. + */ + uint32_t slc1_tx_start_int_clr:1; + /** slc1_rx_udf_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear SLC1_RX_UDF_INT interrupt. + */ + uint32_t slc1_rx_udf_int_clr:1; + /** slc1_tx_ovf_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear SLC1_TX_OVF_INT interrupt. + */ + uint32_t slc1_tx_ovf_int_clr:1; + /** slc1_token0_1to0_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear SLC1_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc1_token0_1to0_int_clr:1; + /** slc1_token1_1to0_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear SLC1_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc1_token1_1to0_int_clr:1; + /** slc1_tx_done_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear SLC1_TX_DONE_INT_ST interrupt. + */ + uint32_t slc1_tx_done_int_clr:1; + /** slc1_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear SLC1_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc1_tx_suc_eof_int_clr:1; + /** slc1_rx_done_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear SLC1_RX_DONE_INT interrupt. + */ + uint32_t slc1_rx_done_int_clr:1; + /** slc1_rx_eof_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear SLC1_RX_EOF_INT interrupt. + */ + uint32_t slc1_rx_eof_int_clr:1; + /** slc1_tohost_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear SLC1_TOHOST_INT interrupt. + */ + uint32_t slc1_tohost_int_clr:1; + /** slc1_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear SLC1_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_tx_dscr_err_int_clr:1; + /** slc1_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0; + * Set this bit to clear SLC1_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_rx_dscr_err_int_clr:1; + /** slc1_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0; + * Set this bit to clear SLC1_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc1_tx_dscr_empty_int_clr:1; + /** slc1_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0; + * Set this bit to clear SLC1_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc1_host_rd_ack_int_clr:1; + /** slc1_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0; + * Set this bit to clear SLC1_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc1_wr_retry_done_int_clr:1; + /** slc1_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0; + * Set this bit to clear SLC1_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc1_tx_err_eof_int_clr:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_slc1int_clr_reg_t; + +/** Type of slc_slc0int_st1 register + * Sdio slave DMA channel0 masked interrupt status register1. + */ +typedef union { + struct { + /** slc_frhost_bit0_int_st1 : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit10_INT interrupt. + */ + uint32_t slc_frhost_bit0_int_st1:1; + /** slc_frhost_bit1_int_st1 : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit11_INT interrupt. + */ + uint32_t slc_frhost_bit1_int_st1:1; + /** slc_frhost_bit2_int_st1 : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit12_INT interrupt. + */ + uint32_t slc_frhost_bit2_int_st1:1; + /** slc_frhost_bit3_int_st1 : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit13_INT interrupt. + */ + uint32_t slc_frhost_bit3_int_st1:1; + /** slc_frhost_bit4_int_st1 : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit14_INT interrupt. + */ + uint32_t slc_frhost_bit4_int_st1:1; + /** slc_frhost_bit5_int_st1 : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit15_INT interrupt. + */ + uint32_t slc_frhost_bit5_int_st1:1; + /** slc_frhost_bit6_int_st1 : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit16_INT interrupt. + */ + uint32_t slc_frhost_bit6_int_st1:1; + /** slc_frhost_bit7_int_st1 : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit17_INT interrupt. + */ + uint32_t slc_frhost_bit7_int_st1:1; + /** slc0_rx_start_int_st1 : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_START_INT_ST interrupt. + */ + uint32_t slc0_rx_start_int_st1:1; + /** slc0_tx_start_int_st1 : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_START_INT_ST interrupt. + */ + uint32_t slc0_tx_start_int_st1:1; + /** slc0_rx_udf_int_st1 : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_UDF_INT interrupt. + */ + uint32_t slc0_rx_udf_int_st1:1; + /** slc0_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_OVF_INT interrupt. + */ + uint32_t slc0_tx_ovf_int_st1:1; + /** slc0_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit1 for SLC0_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc0_token0_1to0_int_st1:1; + /** slc0_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit1 for SLC0_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc0_token1_1to0_int_st1:1; + /** slc0_tx_done_int_st1 : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_DONE_INT_ST interrupt. + */ + uint32_t slc0_tx_done_int_st1:1; + /** slc0_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc0_tx_suc_eof_int_st1:1; + /** slc0_rx_done_int_st1 : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_DONE_INT interrupt. + */ + uint32_t slc0_rx_done_int_st1:1; + /** slc0_rx_eof_int_st1 : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_EOF_INT interrupt. + */ + uint32_t slc0_rx_eof_int_st1:1; + /** slc0_tohost_int_st1 : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit1 for SLC0_TOHOST_INT interrupt. + */ + uint32_t slc0_tohost_int_st1:1; + /** slc0_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_tx_dscr_err_int_st1:1; + /** slc0_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_rx_dscr_err_int_st1:1; + /** slc0_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc0_tx_dscr_empty_int_st1:1; + /** slc0_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit1 for SLC0_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc0_host_rd_ack_int_st1:1; + /** slc0_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit1 for SLC0_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc0_wr_retry_done_int_st1:1; + /** slc0_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc0_tx_err_eof_int_st1:1; + /** cmd_dtc_int_st1 : RO; bitpos: [25]; default: 0; + * The masked interrupt status bit1 for CMD_DTC_INT interrupt. + */ + uint32_t cmd_dtc_int_st1:1; + /** slc0_rx_quick_eof_int_st1 : RO; bitpos: [26]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_QUICK_EOF_INT interrupt. + */ + uint32_t slc0_rx_quick_eof_int_st1:1; + /** slc0_host_pop_eof_err_int_st1 : RO; bitpos: [27]; default: 0; + * The masked interrupt status bit1 for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ + uint32_t slc0_host_pop_eof_err_int_st1:1; + /** hda_recv_done_int_st1 : RO; bitpos: [28]; default: 0; + * The masked interrupt status bit1 for HDA_RECV_DONE_INT interrupt. + */ + uint32_t hda_recv_done_int_st1:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_slc0int_st1_reg_t; + +/** Type of slc_slc0int_ena1 register + * Sdio slave DMA channel0 interrupt enable register1. + */ +typedef union { + struct { + /** slc_frhost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit10_INT interrupt. + */ + uint32_t slc_frhost_bit0_int_ena1:1; + /** slc_frhost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit11_INT interrupt. + */ + uint32_t slc_frhost_bit1_int_ena1:1; + /** slc_frhost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit12_INT interrupt. + */ + uint32_t slc_frhost_bit2_int_ena1:1; + /** slc_frhost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit13_INT interrupt. + */ + uint32_t slc_frhost_bit3_int_ena1:1; + /** slc_frhost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit14_INT interrupt. + */ + uint32_t slc_frhost_bit4_int_ena1:1; + /** slc_frhost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit15_INT interrupt. + */ + uint32_t slc_frhost_bit5_int_ena1:1; + /** slc_frhost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit16_INT interrupt. + */ + uint32_t slc_frhost_bit6_int_ena1:1; + /** slc_frhost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit17_INT interrupt. + */ + uint32_t slc_frhost_bit7_int_ena1:1; + /** slc0_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit1 for SLC0_RX_START_INT_ST interrupt. + */ + uint32_t slc0_rx_start_int_ena1:1; + /** slc0_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit1 for SLC0_TX_START_INT_ST interrupt. + */ + uint32_t slc0_tx_start_int_ena1:1; + /** slc0_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit1 for SLC0_RX_UDF_INT interrupt. + */ + uint32_t slc0_rx_udf_int_ena1:1; + /** slc0_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit1 for SLC0_TX_OVF_INT interrupt. + */ + uint32_t slc0_tx_ovf_int_ena1:1; + /** slc0_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit1 for SLC0_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc0_token0_1to0_int_ena1:1; + /** slc0_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit1 for SLC0_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc0_token1_1to0_int_ena1:1; + /** slc0_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit1 for SLC0_TX_DONE_INT_ST interrupt. + */ + uint32_t slc0_tx_done_int_ena1:1; + /** slc0_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit1 for SLC0_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc0_tx_suc_eof_int_ena1:1; + /** slc0_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit1 for SLC0_RX_DONE_INT interrupt. + */ + uint32_t slc0_rx_done_int_ena1:1; + /** slc0_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit1 for SLC0_RX_EOF_INT interrupt. + */ + uint32_t slc0_rx_eof_int_ena1:1; + /** slc0_tohost_int_ena1 : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit1 for SLC0_TOHOST_INT interrupt. + */ + uint32_t slc0_tohost_int_ena1:1; + /** slc0_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit1 for SLC0_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_tx_dscr_err_int_ena1:1; + /** slc0_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit1 for SLC0_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_rx_dscr_err_int_ena1:1; + /** slc0_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit1 for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc0_tx_dscr_empty_int_ena1:1; + /** slc0_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit1 for SLC0_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc0_host_rd_ack_int_ena1:1; + /** slc0_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit1 for SLC0_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc0_wr_retry_done_int_ena1:1; + /** slc0_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit1 for SLC0_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc0_tx_err_eof_int_ena1:1; + /** cmd_dtc_int_ena1 : R/W; bitpos: [25]; default: 0; + * The interrupt enable bit1 for CMD_DTC_INT interrupt. + */ + uint32_t cmd_dtc_int_ena1:1; + /** slc0_rx_quick_eof_int_ena1 : R/W; bitpos: [26]; default: 0; + * The interrupt enable bit1 for SLC0_RX_QUICK_EOF_INT interrupt. + */ + uint32_t slc0_rx_quick_eof_int_ena1:1; + /** slc0_host_pop_eof_err_int_ena1 : R/W; bitpos: [27]; default: 0; + * The interrupt enable bit1 for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ + uint32_t slc0_host_pop_eof_err_int_ena1:1; + /** hda_recv_done_int_ena1 : R/W; bitpos: [28]; default: 0; + * The interrupt enable bit1 for HDA_RECV_DONE_INT interrupt. + */ + uint32_t hda_recv_done_int_ena1:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_slc0int_ena1_reg_t; + +/** Type of slc_slc1int_st1 register + * Sdio slave DMA channel1 masked interrupt status register1. + */ +typedef union { + struct { + /** slc_frhost_bit8_int_st1 : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit10_INT interrupt. + */ + uint32_t slc_frhost_bit8_int_st1:1; + /** slc_frhost_bit9_int_st1 : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit11_INT interrupt. + */ + uint32_t slc_frhost_bit9_int_st1:1; + /** slc_frhost_bit10_int_st1 : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit12_INT interrupt. + */ + uint32_t slc_frhost_bit10_int_st1:1; + /** slc_frhost_bit11_int_st1 : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit13_INT interrupt. + */ + uint32_t slc_frhost_bit11_int_st1:1; + /** slc_frhost_bit12_int_st1 : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit14_INT interrupt. + */ + uint32_t slc_frhost_bit12_int_st1:1; + /** slc_frhost_bit13_int_st1 : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit15_INT interrupt. + */ + uint32_t slc_frhost_bit13_int_st1:1; + /** slc_frhost_bit14_int_st1 : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit16_INT interrupt. + */ + uint32_t slc_frhost_bit14_int_st1:1; + /** slc_frhost_bit15_int_st1 : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit17_INT interrupt. + */ + uint32_t slc_frhost_bit15_int_st1:1; + /** slc1_rx_start_int_st1 : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_START_INT_ST interrupt. + */ + uint32_t slc1_rx_start_int_st1:1; + /** slc1_tx_start_int_st1 : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_START_INT_ST interrupt. + */ + uint32_t slc1_tx_start_int_st1:1; + /** slc1_rx_udf_int_st1 : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_UDF_INT interrupt. + */ + uint32_t slc1_rx_udf_int_st1:1; + /** slc1_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_OVF_INT interrupt. + */ + uint32_t slc1_tx_ovf_int_st1:1; + /** slc1_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit1 for SLC1_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc1_token0_1to0_int_st1:1; + /** slc1_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit1 for SLC1_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc1_token1_1to0_int_st1:1; + /** slc1_tx_done_int_st1 : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_DONE_INT_ST interrupt. + */ + uint32_t slc1_tx_done_int_st1:1; + /** slc1_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc1_tx_suc_eof_int_st1:1; + /** slc1_rx_done_int_st1 : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_DONE_INT interrupt. + */ + uint32_t slc1_rx_done_int_st1:1; + /** slc1_rx_eof_int_st1 : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_EOF_INT interrupt. + */ + uint32_t slc1_rx_eof_int_st1:1; + /** slc1_tohost_int_st1 : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit1 for SLC1_TOHOST_INT interrupt. + */ + uint32_t slc1_tohost_int_st1:1; + /** slc1_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_tx_dscr_err_int_st1:1; + /** slc1_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_rx_dscr_err_int_st1:1; + /** slc1_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc1_tx_dscr_empty_int_st1:1; + /** slc1_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit1 for SLC1_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc1_host_rd_ack_int_st1:1; + /** slc1_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit1 for SLC1_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc1_wr_retry_done_int_st1:1; + /** slc1_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc1_tx_err_eof_int_st1:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_slc1int_st1_reg_t; + +/** Type of slc_slc1int_ena1 register + * Sdio slave DMA channel1 interrupt enable register1. + */ +typedef union { + struct { + /** slc_frhost_bit8_int_ena1 : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit10_INT interrupt. + */ + uint32_t slc_frhost_bit8_int_ena1:1; + /** slc_frhost_bit9_int_ena1 : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit11_INT interrupt. + */ + uint32_t slc_frhost_bit9_int_ena1:1; + /** slc_frhost_bit10_int_ena1 : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit12_INT interrupt. + */ + uint32_t slc_frhost_bit10_int_ena1:1; + /** slc_frhost_bit11_int_ena1 : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit13_INT interrupt. + */ + uint32_t slc_frhost_bit11_int_ena1:1; + /** slc_frhost_bit12_int_ena1 : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit14_INT interrupt. + */ + uint32_t slc_frhost_bit12_int_ena1:1; + /** slc_frhost_bit13_int_ena1 : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit15_INT interrupt. + */ + uint32_t slc_frhost_bit13_int_ena1:1; + /** slc_frhost_bit14_int_ena1 : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit16_INT interrupt. + */ + uint32_t slc_frhost_bit14_int_ena1:1; + /** slc_frhost_bit15_int_ena1 : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit17_INT interrupt. + */ + uint32_t slc_frhost_bit15_int_ena1:1; + /** slc1_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit1 for SCL1_RX_START_INT_ST interrupt. + */ + uint32_t slc1_rx_start_int_ena1:1; + /** slc1_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit1 for SCL1_TX_START_INT_ST interrupt. + */ + uint32_t slc1_tx_start_int_ena1:1; + /** slc1_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit1 for SCL1_RX_UDF_INT interrupt. + */ + uint32_t slc1_rx_udf_int_ena1:1; + /** slc1_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit1 for SCL1_TX_OVF_INT interrupt. + */ + uint32_t slc1_tx_ovf_int_ena1:1; + /** slc1_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit1 for SCL1_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc1_token0_1to0_int_ena1:1; + /** slc1_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit1 for SCL1_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc1_token1_1to0_int_ena1:1; + /** slc1_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit1 for SCL1_TX_DONE_INT_ST interrupt. + */ + uint32_t slc1_tx_done_int_ena1:1; + /** slc1_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit1 for SCL1_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc1_tx_suc_eof_int_ena1:1; + /** slc1_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit1 for SCL1_RX_DONE_INT interrupt. + */ + uint32_t slc1_rx_done_int_ena1:1; + /** slc1_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit1 for SCL1_RX_EOF_INT interrupt. + */ + uint32_t slc1_rx_eof_int_ena1:1; + /** slc1_tohost_int_ena1 : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit1 for SCL1_TOHOST_INT interrupt. + */ + uint32_t slc1_tohost_int_ena1:1; + /** slc1_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit1 for SCL1_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_tx_dscr_err_int_ena1:1; + /** slc1_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit1 for SCL1_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_rx_dscr_err_int_ena1:1; + /** slc1_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit1 for SCL1_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc1_tx_dscr_empty_int_ena1:1; + /** slc1_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit1 for SCL1_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc1_host_rd_ack_int_ena1:1; + /** slc1_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit1 for SCL1_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc1_wr_retry_done_int_ena1:1; + /** slc1_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit1 for SCL1_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc1_tx_err_eof_int_ena1:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_slc1int_ena1_reg_t; + + +/** Group: Status registers */ +/** Type of slc_rx_status register + * Sdio slave DMA rxfifo status register. + */ +typedef union { + struct { + /** slc0_rx_full : RO; bitpos: [0]; default: 0; + * The status bit for rxfifo full during slave sending data to host through dma + * channel0. + */ + uint32_t slc0_rx_full:1; + /** slc0_rx_empty : RO; bitpos: [1]; default: 1; + * The status bit for rxfifo empty during slave sending data to host through dma + * channel0. + */ + uint32_t slc0_rx_empty:1; + /** slc0_rx_buf_len : RO; bitpos: [15:2]; default: 0; + * the current buffer length during slave sending data to host through dma channel0. + */ + uint32_t slc0_rx_buf_len:14; + /** slc1_rx_full : RO; bitpos: [16]; default: 0; + * The status bit for rxfifo full during slave sending data to host through dma + * channel1. + */ + uint32_t slc1_rx_full:1; + /** slc1_rx_empty : RO; bitpos: [17]; default: 1; + * The status bit for rxfifo empty during slave sending data to host through dma + * channel1. + */ + uint32_t slc1_rx_empty:1; + /** slc1_rx_buf_len : RO; bitpos: [31:18]; default: 0; + * the current buffer length during slave sending data to host through dma channel1. + */ + uint32_t slc1_rx_buf_len:14; + }; + uint32_t val; +} sdio_slc_rx_status_reg_t; + +/** Type of slc_tx_status register + * Sdio slave DMA txfifo status register. + */ +typedef union { + struct { + /** slc0_tx_full : RO; bitpos: [0]; default: 0; + * The status bit for txfifo full during slave receiving data from host through dma + * channel0. + */ + uint32_t slc0_tx_full:1; + /** slc0_tx_empty : RO; bitpos: [1]; default: 1; + * The status bit for txfifo empty during slave receiving data from host through dma + * channel0. + */ + uint32_t slc0_tx_empty:1; + uint32_t reserved_2:14; + /** slc1_tx_full : RO; bitpos: [16]; default: 0; + * The status bit for txfifo full during slave receiving data from host through dma + * channel1. + */ + uint32_t slc1_tx_full:1; + /** slc1_tx_empty : RO; bitpos: [17]; default: 1; + * The status bit for txfifo empty during slave receiving data from host through dma + * channel1. + */ + uint32_t slc1_tx_empty:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdio_slc_tx_status_reg_t; + +/** Type of slc_slc0_state0 register + * Sdio slave DMA channel0 status register. + */ +typedef union { + struct { + /** slc0_state0 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current receiving descriptor address, [20:19] receiving descriptor fsm + * state, [23:21] receiving fsm state, [30:24] the count value of data received in + * txfifo + */ + uint32_t slc0_state0:32; + }; + uint32_t val; +} sdio_slc_slc0_state0_reg_t; + +/** Type of slc_slc0_state1 register + * Sdio slave DMA channel0 status1 register. + */ +typedef union { + struct { + /** slc0_state1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current sending descriptor address, [20:19] sending descriptor fsm + * state, [23:21] sending fsm state, [30:24] the count value of data to be sent in + * rxfifo + */ + uint32_t slc0_state1:32; + }; + uint32_t val; +} sdio_slc_slc0_state1_reg_t; + +/** Type of slc_slc1_state0 register + * Sdio slave DMA channel1 status register. + */ +typedef union { + struct { + /** slc1_state0 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current receiving descriptor address, [20:19] receiving descriptor fsm + * state, [23:21] receiving fsm state, [30:24] the count value of data received in + * txfifo + */ + uint32_t slc1_state0:32; + }; + uint32_t val; +} sdio_slc_slc1_state0_reg_t; + +/** Type of slc_slc1_state1 register + * Sdio slave DMA channel1 status1 register. + */ +typedef union { + struct { + /** slc1_state1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current sending descriptor address, [20:19] sending descriptor fsm + * state, [23:21] sending fsm state, [30:24] the count value of data to be sent in + * rxfifo + */ + uint32_t slc1_state1:32; + }; + uint32_t val; +} sdio_slc_slc1_state1_reg_t; + +/** Type of slc_sdio_st register + * Sdio slave function status register. + */ +typedef union { + struct { + /** cmd_st : RO; bitpos: [2:0]; default: 0; + * The sdio command fsm state. + */ + uint32_t cmd_st:3; + uint32_t reserved_3:1; + /** func_st : RO; bitpos: [7:4]; default: 0; + * The sdio cmd52/53 function fsm state. + */ + uint32_t func_st:4; + /** sdio_wakeup : RO; bitpos: [8]; default: 0; + * reserved + */ + uint32_t sdio_wakeup:1; + uint32_t reserved_9:3; + /** bus_st : RO; bitpos: [14:12]; default: 0; + * The sdio bus fsm state. + */ + uint32_t bus_st:3; + uint32_t reserved_15:1; + /** func1_acc_state : RO; bitpos: [20:16]; default: 0; + * The sdio func1 fsm state. + */ + uint32_t func1_acc_state:5; + uint32_t reserved_21:3; + /** func2_acc_state : RO; bitpos: [28:24]; default: 0; + * The sdio func2 fsm state. + */ + uint32_t func2_acc_state:5; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_sdio_st_reg_t; + +/** Type of slc_slc0_txlink_dscr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_txlink_dscr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_txlink_dscr:32; + }; + uint32_t val; +} sdio_slc_slc0_txlink_dscr_reg_t; + +/** Type of slc_slc0_txlink_dscr_bf0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_txlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc_slc0_txlink_dscr_bf0_reg_t; + +/** Type of slc_slc0_txlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc0_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_txlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc_slc0_txlink_dscr_bf1_reg_t; + +/** Type of slc_slc0_rxlink_dscr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rxlink_dscr : RO; bitpos: [31:0]; default: 0; + * the third word of slc0 link descriptor, or known as the next descriptor address + */ + uint32_t slc0_rxlink_dscr:32; + }; + uint32_t val; +} sdio_slc_slc0_rxlink_dscr_reg_t; + +/** Type of slc_slc0_rxlink_dscr_bf0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rxlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc_slc0_rxlink_dscr_bf0_reg_t; + +/** Type of slc_slc0_rxlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc0_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rxlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc_slc0_rxlink_dscr_bf1_reg_t; + +/** Type of slc_slc1_txlink_dscr register + * reserved + */ +typedef union { + struct { + /** slc1_txlink_dscr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_txlink_dscr:32; + }; + uint32_t val; +} sdio_slc_slc1_txlink_dscr_reg_t; + +/** Type of slc_slc1_txlink_dscr_bf0 register + * reserved + */ +typedef union { + struct { + /** slc1_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_txlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc_slc1_txlink_dscr_bf0_reg_t; + +/** Type of slc_slc1_txlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc1_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_txlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc_slc1_txlink_dscr_bf1_reg_t; + +/** Type of slc_slc1_rxlink_dscr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc1_rxlink_dscr : RO; bitpos: [31:0]; default: 0; + * the third word of slc1 link descriptor, or known as the next descriptor address + */ + uint32_t slc1_rxlink_dscr:32; + }; + uint32_t val; +} sdio_slc_slc1_rxlink_dscr_reg_t; + +/** Type of slc_slc1_rxlink_dscr_bf0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc1_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_rxlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc_slc1_rxlink_dscr_bf0_reg_t; + +/** Type of slc_slc1_rxlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc1_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_rxlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc_slc1_rxlink_dscr_bf1_reg_t; + +/** Type of slc_slc0_tx_erreof_des_addr register + * reserved + */ +typedef union { + struct { + /** slc0_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_tx_err_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_tx_erreof_des_addr_reg_t; + +/** Type of slc_slc1_tx_erreof_des_addr register + * reserved + */ +typedef union { + struct { + /** slc1_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_tx_err_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_tx_erreof_des_addr_reg_t; + +/** Type of slc_token_lat register + * reserved + */ +typedef union { + struct { + /** slc0_token : RO; bitpos: [11:0]; default: 0; + * reserved + */ + uint32_t slc0_token:12; + uint32_t reserved_12:4; + /** slc1_token : RO; bitpos: [27:16]; default: 0; + * reserved + */ + uint32_t slc1_token:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_token_lat_reg_t; + +/** Type of slc_cmd_infor0 register + * reserved + */ +typedef union { + struct { + /** cmd_content0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t cmd_content0:32; + }; + uint32_t val; +} sdio_slc_cmd_infor0_reg_t; + +/** Type of slc_cmd_infor1 register + * reserved + */ +typedef union { + struct { + /** cmd_content1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t cmd_content1:32; + }; + uint32_t val; +} sdio_slc_cmd_infor1_reg_t; + +/** Type of slc_slc0_length register + * reserved + */ +typedef union { + struct { + /** slc0_len : RO; bitpos: [19:0]; default: 0; + * Indicates the paclet length sent by the slave through dma channel0. + */ + uint32_t slc0_len:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} sdio_slc_slc0_length_reg_t; + +/** Type of slc_sdio_crc_st0 register + * Sdio slave receiving packet data crc status register. + */ +typedef union { + struct { + /** dat0_crc_err_cnt : RO; bitpos: [7:0]; default: 0; + * The count value of received packet data crc errors on sd_data0 line. + */ + uint32_t dat0_crc_err_cnt:8; + /** dat1_crc_err_cnt : RO; bitpos: [15:8]; default: 0; + * The count value of received packet data crc errors on sd_data1 line. + */ + uint32_t dat1_crc_err_cnt:8; + /** dat2_crc_err_cnt : RO; bitpos: [23:16]; default: 0; + * The count value of received packet data crc errors on sd_data2 line. + */ + uint32_t dat2_crc_err_cnt:8; + /** dat3_crc_err_cnt : RO; bitpos: [31:24]; default: 0; + * The count value of received packet data crc errors on sd_data3 line. + */ + uint32_t dat3_crc_err_cnt:8; + }; + uint32_t val; +} sdio_slc_sdio_crc_st0_reg_t; + +/** Type of slc_slc0_eof_start_des register + * Sdio slave DMA channel0 start address of sending linked list status register. + */ +typedef union { + struct { + /** slc0_eof_start_des_addr : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last sent packet through dma channel0. + */ + uint32_t slc0_eof_start_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_eof_start_des_reg_t; + +/** Type of slc_slc0_push_dscr_addr register + * Sdio slave DMA channel0 address of sending linked list status register. + */ +typedef union { + struct { + /** slc0_rx_push_dscr_addr : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 gets a link descriptor, aligned with word + */ + uint32_t slc0_rx_push_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_push_dscr_addr_reg_t; + +/** Type of slc_slc0_done_dscr_addr register + * Sdio slave DMA channel0 address of sending linked list status register1. + */ +typedef union { + struct { + /** slc0_rx_done_dscr_addr : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 finishes reading data from one buffer, + * aligned with word + */ + uint32_t slc0_rx_done_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_done_dscr_addr_reg_t; + +/** Type of slc_slc0_sub_start_des register + * Sdio slave DMA channel0 start address of sending linked list status register. + */ +typedef union { + struct { + /** slc0_sub_pac_start_dscr_addr : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last sent packet through dma channel0. + */ + uint32_t slc0_sub_pac_start_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_sub_start_des_reg_t; + +/** Type of slc_slc0_dscr_cnt register + * Sdio slave DMA channel0 descriptor status register. + */ +typedef union { + struct { + /** slc0_rx_dscr_cnt_lat : RO; bitpos: [9:0]; default: 0; + * The number of descriptors got by dma channel0 for sending packets. + */ + uint32_t slc0_rx_dscr_cnt_lat:10; + uint32_t reserved_10:6; + /** slc0_rx_get_eof_occ : RO; bitpos: [16]; default: 0; + * The status of last packet finishing sending to host. + */ + uint32_t slc0_rx_get_eof_occ:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc_slc0_dscr_cnt_reg_t; + + +/** Group: Debud registers */ +/** Type of slc_slc0txfifo_pop register + * Sdio slave DMA channel0 txfifo debug register. + */ +typedef union { + struct { + /** slc0_txfifo_rdata : RO; bitpos: [10:0]; default: 1024; + * This field saves the data read from txfifo through APB bus. + */ + uint32_t slc0_txfifo_rdata:11; + uint32_t reserved_11:5; + /** slc0_txfifo_pop : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to read data from txfifo through APB bus. This bit is cleared + * automatically after reading one data from slc0_txfifo through APB bus successfully. + */ + uint32_t slc0_txfifo_pop:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc_slc0txfifo_pop_reg_t; + +/** Type of slc_slc1txfifo_pop register + * Sdio slave DMA channel1 txfifo debug register. + */ +typedef union { + struct { + /** slc1_txfifo_rdata : RO; bitpos: [10:0]; default: 1024; + * This field saves the data read from txfifo through APB bus. + */ + uint32_t slc1_txfifo_rdata:11; + uint32_t reserved_11:5; + /** slc1_txfifo_pop : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to read data from txfifo through APB bus. This bit is cleared + * automatically after reading one data from slc1_txfifo through APB bus successfully. + */ + uint32_t slc1_txfifo_pop:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc_slc1txfifo_pop_reg_t; + +/** Type of slc_ahb_test register + * Sdio slave AHB test register. + */ +typedef union { + struct { + /** slc_ahb_testmode : R/W; bitpos: [2:0]; default: 0; + * set bit2 to 1 to enable sdio slave ahb test. + */ + uint32_t slc_ahb_testmode:3; + uint32_t reserved_3:1; + /** slc_ahb_testaddr : R/W; bitpos: [5:4]; default: 0; + * Configure AHB test address. + */ + uint32_t slc_ahb_testaddr:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} sdio_slc_ahb_test_reg_t; + + +/** Group: Version registers */ +/** Type of slc_date register + * Sdio slave DMA version register. + */ +typedef union { + struct { + /** slc_date : R/W; bitpos: [31:0]; default: 554182400; + * Sdio slave DMA version register. + */ + uint32_t slc_date:32; + }; + uint32_t val; +} sdio_slc_date_reg_t; + +/** Type of slc_id register + * Sdio slave ID register. + */ +typedef union { + struct { + /** slc_id : R/W; bitpos: [31:0]; default: 256; + * reserved + */ + uint32_t slc_id:32; + }; + uint32_t val; +} sdio_slc_id_reg_t; + + +typedef struct { + volatile sdio_slc_conf0_reg_t slc_conf0; + volatile sdio_slc_slc0int_raw_reg_t slc_slc0int_raw; + volatile sdio_slc_slc0int_st_reg_t slc_slc0int_st; + volatile sdio_slc_slc0int_ena_reg_t slc_slc0int_ena; + volatile sdio_slc_slc0int_clr_reg_t slc_slc0int_clr; + volatile sdio_slc_slc1int_raw_reg_t slc_slc1int_raw; + volatile sdio_slc_slc1int_st_reg_t slc_slc1int_st; + volatile sdio_slc_slc1int_ena_reg_t slc_slc1int_ena; + volatile sdio_slc_slc1int_clr_reg_t slc_slc1int_clr; + volatile sdio_slc_rx_status_reg_t slc_rx_status; + volatile sdio_slc_slc0rxfifo_push_reg_t slc_slc0rxfifo_push; + volatile sdio_slc_slc1rxfifo_push_reg_t slc_slc1rxfifo_push; + volatile sdio_slc_tx_status_reg_t slc_tx_status; + volatile sdio_slc_slc0txfifo_pop_reg_t slc_slc0txfifo_pop; + volatile sdio_slc_slc1txfifo_pop_reg_t slc_slc1txfifo_pop; + volatile sdio_slc_slc0rx_link_reg_t slc_slc0rx_link; + volatile sdio_slc_slc0rx_link_addr_reg_t slc_slc0rx_link_addr; + volatile sdio_slc_slc0tx_link_reg_t slc_slc0tx_link; + volatile sdio_slc_slc0tx_link_addr_reg_t slc_slc0tx_link_addr; + volatile sdio_slc_slc1rx_link_reg_t slc_slc1rx_link; + volatile sdio_slc_slc1rx_link_addr_reg_t slc_slc1rx_link_addr; + volatile sdio_slc_slc1tx_link_reg_t slc_slc1tx_link; + volatile sdio_slc_slc1tx_link_addr_reg_t slc_slc1tx_link_addr; + volatile sdio_slc_slcintvec_tohost_reg_t slc_slcintvec_tohost; + volatile sdio_slc_slc0token0_reg_t slc_slc0token0; + volatile sdio_slc_slc0token1_reg_t slc_slc0token1; + volatile sdio_slc_slc1token0_reg_t slc_slc1token0; + volatile sdio_slc_slc1token1_reg_t slc_slc1token1; + volatile sdio_slc_conf1_reg_t slc_conf1; + volatile sdio_slc_slc0_state0_reg_t slc_slc0_state0; + volatile sdio_slc_slc0_state1_reg_t slc_slc0_state1; + volatile sdio_slc_slc1_state0_reg_t slc_slc1_state0; + volatile sdio_slc_slc1_state1_reg_t slc_slc1_state1; + volatile sdio_slc_bridge_conf_reg_t slc_bridge_conf; + volatile sdio_slc_slc0_to_eof_des_addr_reg_t slc_slc0_to_eof_des_addr; + volatile sdio_slc_slc0_tx_eof_des_addr_reg_t slc_slc0_tx_eof_des_addr; + volatile sdio_slc_slc0_to_eof_bfr_des_addr_reg_t slc_slc0_to_eof_bfr_des_addr; + volatile sdio_slc_slc1_to_eof_des_addr_reg_t slc_slc1_to_eof_des_addr; + volatile sdio_slc_slc1_tx_eof_des_addr_reg_t slc_slc1_tx_eof_des_addr; + volatile sdio_slc_slc1_to_eof_bfr_des_addr_reg_t slc_slc1_to_eof_bfr_des_addr; + volatile sdio_slc_ahb_test_reg_t slc_ahb_test; + volatile sdio_slc_sdio_st_reg_t slc_sdio_st; + volatile sdio_slc_rx_dscr_conf_reg_t slc_rx_dscr_conf; + volatile sdio_slc_slc0_txlink_dscr_reg_t slc_slc0_txlink_dscr; + volatile sdio_slc_slc0_txlink_dscr_bf0_reg_t slc_slc0_txlink_dscr_bf0; + volatile sdio_slc_slc0_txlink_dscr_bf1_reg_t slc_slc0_txlink_dscr_bf1; + volatile sdio_slc_slc0_rxlink_dscr_reg_t slc_slc0_rxlink_dscr; + volatile sdio_slc_slc0_rxlink_dscr_bf0_reg_t slc_slc0_rxlink_dscr_bf0; + volatile sdio_slc_slc0_rxlink_dscr_bf1_reg_t slc_slc0_rxlink_dscr_bf1; + volatile sdio_slc_slc1_txlink_dscr_reg_t slc_slc1_txlink_dscr; + volatile sdio_slc_slc1_txlink_dscr_bf0_reg_t slc_slc1_txlink_dscr_bf0; + volatile sdio_slc_slc1_txlink_dscr_bf1_reg_t slc_slc1_txlink_dscr_bf1; + volatile sdio_slc_slc1_rxlink_dscr_reg_t slc_slc1_rxlink_dscr; + volatile sdio_slc_slc1_rxlink_dscr_bf0_reg_t slc_slc1_rxlink_dscr_bf0; + volatile sdio_slc_slc1_rxlink_dscr_bf1_reg_t slc_slc1_rxlink_dscr_bf1; + volatile sdio_slc_slc0_tx_erreof_des_addr_reg_t slc_slc0_tx_erreof_des_addr; + volatile sdio_slc_slc1_tx_erreof_des_addr_reg_t slc_slc1_tx_erreof_des_addr; + volatile sdio_slc_token_lat_reg_t slc_token_lat; + volatile sdio_slc_tx_dscr_conf_reg_t slc_tx_dscr_conf; + volatile sdio_slc_cmd_infor0_reg_t slc_cmd_infor0; + volatile sdio_slc_cmd_infor1_reg_t slc_cmd_infor1; + volatile sdio_slc_slc0_len_conf_reg_t slc_slc0_len_conf; + volatile sdio_slc_slc0_length_reg_t slc_slc0_length; + volatile sdio_slc_slc0_txpkt_h_dscr_reg_t slc_slc0_txpkt_h_dscr; + volatile sdio_slc_slc0_txpkt_e_dscr_reg_t slc_slc0_txpkt_e_dscr; + volatile sdio_slc_slc0_rxpkt_h_dscr_reg_t slc_slc0_rxpkt_h_dscr; + volatile sdio_slc_slc0_rxpkt_e_dscr_reg_t slc_slc0_rxpkt_e_dscr; + volatile sdio_slc_slc0_txpktu_h_dscr_reg_t slc_slc0_txpktu_h_dscr; + volatile sdio_slc_slc0_txpktu_e_dscr_reg_t slc_slc0_txpktu_e_dscr; + volatile sdio_slc_slc0_rxpktu_h_dscr_reg_t slc_slc0_rxpktu_h_dscr; + volatile sdio_slc_slc0_rxpktu_e_dscr_reg_t slc_slc0_rxpktu_e_dscr; + volatile sdio_slc_seq_position_reg_t slc_seq_position; + volatile sdio_slc_slc0_dscr_rec_conf_reg_t slc_slc0_dscr_rec_conf; + volatile sdio_slc_sdio_crc_st0_reg_t slc_sdio_crc_st0; + volatile sdio_slc_sdio_crc_st1_reg_t slc_sdio_crc_st1; + volatile sdio_slc_slc0_eof_start_des_reg_t slc_slc0_eof_start_des; + volatile sdio_slc_slc0_push_dscr_addr_reg_t slc_slc0_push_dscr_addr; + volatile sdio_slc_slc0_done_dscr_addr_reg_t slc_slc0_done_dscr_addr; + volatile sdio_slc_slc0_sub_start_des_reg_t slc_slc0_sub_start_des; + volatile sdio_slc_slc0_dscr_cnt_reg_t slc_slc0_dscr_cnt; + volatile sdio_slc_slc0_len_lim_conf_reg_t slc_slc0_len_lim_conf; + volatile sdio_slc_slc0int_st1_reg_t slc_slc0int_st1; + volatile sdio_slc_slc0int_ena1_reg_t slc_slc0int_ena1; + volatile sdio_slc_slc1int_st1_reg_t slc_slc1int_st1; + volatile sdio_slc_slc1int_ena1_reg_t slc_slc1int_ena1; + volatile sdio_slc_slc0_tx_sharemem_start_reg_t slc_slc0_tx_sharemem_start; + volatile sdio_slc_slc0_tx_sharemem_end_reg_t slc_slc0_tx_sharemem_end; + volatile sdio_slc_slc0_rx_sharemem_start_reg_t slc_slc0_rx_sharemem_start; + volatile sdio_slc_slc0_rx_sharemem_end_reg_t slc_slc0_rx_sharemem_end; + volatile sdio_slc_slc1_tx_sharemem_start_reg_t slc_slc1_tx_sharemem_start; + volatile sdio_slc_slc1_tx_sharemem_end_reg_t slc_slc1_tx_sharemem_end; + volatile sdio_slc_slc1_rx_sharemem_start_reg_t slc_slc1_rx_sharemem_start; + volatile sdio_slc_slc1_rx_sharemem_end_reg_t slc_slc1_rx_sharemem_end; + volatile sdio_slc_hda_tx_sharemem_start_reg_t slc_hda_tx_sharemem_start; + volatile sdio_slc_hda_rx_sharemem_start_reg_t slc_hda_rx_sharemem_start; + volatile sdio_slc_burst_len_reg_t slc_burst_len; + uint32_t reserved_180[30]; + volatile sdio_slc_date_reg_t slc_date; + volatile sdio_slc_id_reg_t slc_id; +} slc_dev_t; + +extern slc_dev_t SLC; + +#ifndef __cplusplus +_Static_assert(sizeof(slc_dev_t) == 0x200, "Invalid size of slc_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/register/soc/soc_etm_reg.h b/components/soc/esp32c61/register/soc/soc_etm_reg.h index faea3b3cf5..5d62fd5a1d 100644 --- a/components/soc/esp32c61/register/soc/soc_etm_reg.h +++ b/components/soc/esp32c61/register/soc/soc_etm_reg.h @@ -1,7 +1,7 @@ /** - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -15,8 +15,8 @@ extern "C" { * Channel enable status register */ #define SOC_ETM_CH_ENA_AD0_REG (DR_REG_SOC_ETM_BASE + 0x0) -/** SOC_ETM_CH_ENABLED0 : R/WTC/WS; bitpos: [0]; default: 0; - * Represents channel0 enable status. +/** SOC_ETM_CH_ENABLED0 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch0 enable status. * 0: Disable * 1: Enable */ @@ -24,8 +24,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED0_M (SOC_ETM_CH_ENABLED0_V << SOC_ETM_CH_ENABLED0_S) #define SOC_ETM_CH_ENABLED0_V 0x00000001U #define SOC_ETM_CH_ENABLED0_S 0 -/** SOC_ETM_CH_ENABLED1 : R/WTC/WS; bitpos: [1]; default: 0; - * Represents channel1 enable status. +/** SOC_ETM_CH_ENABLED1 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch1 enable status. * 0: Disable * 1: Enable */ @@ -33,8 +33,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED1_M (SOC_ETM_CH_ENABLED1_V << SOC_ETM_CH_ENABLED1_S) #define SOC_ETM_CH_ENABLED1_V 0x00000001U #define SOC_ETM_CH_ENABLED1_S 1 -/** SOC_ETM_CH_ENABLED2 : R/WTC/WS; bitpos: [2]; default: 0; - * Represents channel2 enable status. +/** SOC_ETM_CH_ENABLED2 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch2 enable status. * 0: Disable * 1: Enable */ @@ -42,8 +42,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED2_M (SOC_ETM_CH_ENABLED2_V << SOC_ETM_CH_ENABLED2_S) #define SOC_ETM_CH_ENABLED2_V 0x00000001U #define SOC_ETM_CH_ENABLED2_S 2 -/** SOC_ETM_CH_ENABLED3 : R/WTC/WS; bitpos: [3]; default: 0; - * Represents channel3 enable status. +/** SOC_ETM_CH_ENABLED3 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch3 enable status. * 0: Disable * 1: Enable */ @@ -51,8 +51,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED3_M (SOC_ETM_CH_ENABLED3_V << SOC_ETM_CH_ENABLED3_S) #define SOC_ETM_CH_ENABLED3_V 0x00000001U #define SOC_ETM_CH_ENABLED3_S 3 -/** SOC_ETM_CH_ENABLED4 : R/WTC/WS; bitpos: [4]; default: 0; - * Represents channel4 enable status. +/** SOC_ETM_CH_ENABLED4 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch4 enable status. * 0: Disable * 1: Enable */ @@ -60,8 +60,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED4_M (SOC_ETM_CH_ENABLED4_V << SOC_ETM_CH_ENABLED4_S) #define SOC_ETM_CH_ENABLED4_V 0x00000001U #define SOC_ETM_CH_ENABLED4_S 4 -/** SOC_ETM_CH_ENABLED5 : R/WTC/WS; bitpos: [5]; default: 0; - * Represents channel5 enable status. +/** SOC_ETM_CH_ENABLED5 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch5 enable status. * 0: Disable * 1: Enable */ @@ -69,8 +69,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED5_M (SOC_ETM_CH_ENABLED5_V << SOC_ETM_CH_ENABLED5_S) #define SOC_ETM_CH_ENABLED5_V 0x00000001U #define SOC_ETM_CH_ENABLED5_S 5 -/** SOC_ETM_CH_ENABLED6 : R/WTC/WS; bitpos: [6]; default: 0; - * Represents channel6 enable status. +/** SOC_ETM_CH_ENABLED6 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch6 enable status. * 0: Disable * 1: Enable */ @@ -78,8 +78,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED6_M (SOC_ETM_CH_ENABLED6_V << SOC_ETM_CH_ENABLED6_S) #define SOC_ETM_CH_ENABLED6_V 0x00000001U #define SOC_ETM_CH_ENABLED6_S 6 -/** SOC_ETM_CH_ENABLED7 : R/WTC/WS; bitpos: [7]; default: 0; - * Represents channel7 enable status. +/** SOC_ETM_CH_ENABLED7 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch7 enable status. * 0: Disable * 1: Enable */ @@ -87,8 +87,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED7_M (SOC_ETM_CH_ENABLED7_V << SOC_ETM_CH_ENABLED7_S) #define SOC_ETM_CH_ENABLED7_V 0x00000001U #define SOC_ETM_CH_ENABLED7_S 7 -/** SOC_ETM_CH_ENABLED8 : R/WTC/WS; bitpos: [8]; default: 0; - * Represents channel8 enable status. +/** SOC_ETM_CH_ENABLED8 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch8 enable status. * 0: Disable * 1: Enable */ @@ -96,8 +96,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED8_M (SOC_ETM_CH_ENABLED8_V << SOC_ETM_CH_ENABLED8_S) #define SOC_ETM_CH_ENABLED8_V 0x00000001U #define SOC_ETM_CH_ENABLED8_S 8 -/** SOC_ETM_CH_ENABLED9 : R/WTC/WS; bitpos: [9]; default: 0; - * Represents channel9 enable status. +/** SOC_ETM_CH_ENABLED9 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch9 enable status. * 0: Disable * 1: Enable */ @@ -105,8 +105,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED9_M (SOC_ETM_CH_ENABLED9_V << SOC_ETM_CH_ENABLED9_S) #define SOC_ETM_CH_ENABLED9_V 0x00000001U #define SOC_ETM_CH_ENABLED9_S 9 -/** SOC_ETM_CH_ENABLED10 : R/WTC/WS; bitpos: [10]; default: 0; - * Represents channel10 enable status. +/** SOC_ETM_CH_ENABLED10 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch10 enable status. * 0: Disable * 1: Enable */ @@ -114,8 +114,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED10_M (SOC_ETM_CH_ENABLED10_V << SOC_ETM_CH_ENABLED10_S) #define SOC_ETM_CH_ENABLED10_V 0x00000001U #define SOC_ETM_CH_ENABLED10_S 10 -/** SOC_ETM_CH_ENABLED11 : R/WTC/WS; bitpos: [11]; default: 0; - * Represents channel11 enable status. +/** SOC_ETM_CH_ENABLED11 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch11 enable status. * 0: Disable * 1: Enable */ @@ -123,8 +123,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED11_M (SOC_ETM_CH_ENABLED11_V << SOC_ETM_CH_ENABLED11_S) #define SOC_ETM_CH_ENABLED11_V 0x00000001U #define SOC_ETM_CH_ENABLED11_S 11 -/** SOC_ETM_CH_ENABLED12 : R/WTC/WS; bitpos: [12]; default: 0; - * Represents channel12 enable status. +/** SOC_ETM_CH_ENABLED12 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch12 enable status. * 0: Disable * 1: Enable */ @@ -132,8 +132,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED12_M (SOC_ETM_CH_ENABLED12_V << SOC_ETM_CH_ENABLED12_S) #define SOC_ETM_CH_ENABLED12_V 0x00000001U #define SOC_ETM_CH_ENABLED12_S 12 -/** SOC_ETM_CH_ENABLED13 : R/WTC/WS; bitpos: [13]; default: 0; - * Represents channel13 enable status. +/** SOC_ETM_CH_ENABLED13 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch13 enable status. * 0: Disable * 1: Enable */ @@ -141,8 +141,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED13_M (SOC_ETM_CH_ENABLED13_V << SOC_ETM_CH_ENABLED13_S) #define SOC_ETM_CH_ENABLED13_V 0x00000001U #define SOC_ETM_CH_ENABLED13_S 13 -/** SOC_ETM_CH_ENABLED14 : R/WTC/WS; bitpos: [14]; default: 0; - * Represents channel14 enable status. +/** SOC_ETM_CH_ENABLED14 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch14 enable status. * 0: Disable * 1: Enable */ @@ -150,8 +150,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED14_M (SOC_ETM_CH_ENABLED14_V << SOC_ETM_CH_ENABLED14_S) #define SOC_ETM_CH_ENABLED14_V 0x00000001U #define SOC_ETM_CH_ENABLED14_S 14 -/** SOC_ETM_CH_ENABLED15 : R/WTC/WS; bitpos: [15]; default: 0; - * Represents channel15 enable status. +/** SOC_ETM_CH_ENABLED15 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch15 enable status. * 0: Disable * 1: Enable */ @@ -159,8 +159,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED15_M (SOC_ETM_CH_ENABLED15_V << SOC_ETM_CH_ENABLED15_S) #define SOC_ETM_CH_ENABLED15_V 0x00000001U #define SOC_ETM_CH_ENABLED15_S 15 -/** SOC_ETM_CH_ENABLED16 : R/WTC/WS; bitpos: [16]; default: 0; - * Represents channel16 enable status. +/** SOC_ETM_CH_ENABLED16 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch16 enable status. * 0: Disable * 1: Enable */ @@ -168,8 +168,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED16_M (SOC_ETM_CH_ENABLED16_V << SOC_ETM_CH_ENABLED16_S) #define SOC_ETM_CH_ENABLED16_V 0x00000001U #define SOC_ETM_CH_ENABLED16_S 16 -/** SOC_ETM_CH_ENABLED17 : R/WTC/WS; bitpos: [17]; default: 0; - * Represents channel17 enable status. +/** SOC_ETM_CH_ENABLED17 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch17 enable status. * 0: Disable * 1: Enable */ @@ -177,8 +177,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED17_M (SOC_ETM_CH_ENABLED17_V << SOC_ETM_CH_ENABLED17_S) #define SOC_ETM_CH_ENABLED17_V 0x00000001U #define SOC_ETM_CH_ENABLED17_S 17 -/** SOC_ETM_CH_ENABLED18 : R/WTC/WS; bitpos: [18]; default: 0; - * Represents channel18 enable status. +/** SOC_ETM_CH_ENABLED18 : R/WTC/WTS; bitpos: [18]; default: 0; + * Represents ch18 enable status. * 0: Disable * 1: Enable */ @@ -186,8 +186,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED18_M (SOC_ETM_CH_ENABLED18_V << SOC_ETM_CH_ENABLED18_S) #define SOC_ETM_CH_ENABLED18_V 0x00000001U #define SOC_ETM_CH_ENABLED18_S 18 -/** SOC_ETM_CH_ENABLED19 : R/WTC/WS; bitpos: [19]; default: 0; - * Represents channel19 enable status. +/** SOC_ETM_CH_ENABLED19 : R/WTC/WTS; bitpos: [19]; default: 0; + * Represents ch19 enable status. * 0: Disable * 1: Enable */ @@ -195,8 +195,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED19_M (SOC_ETM_CH_ENABLED19_V << SOC_ETM_CH_ENABLED19_S) #define SOC_ETM_CH_ENABLED19_V 0x00000001U #define SOC_ETM_CH_ENABLED19_S 19 -/** SOC_ETM_CH_ENABLED20 : R/WTC/WS; bitpos: [20]; default: 0; - * Represents channel20 enable status. +/** SOC_ETM_CH_ENABLED20 : R/WTC/WTS; bitpos: [20]; default: 0; + * Represents ch20 enable status. * 0: Disable * 1: Enable */ @@ -204,8 +204,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED20_M (SOC_ETM_CH_ENABLED20_V << SOC_ETM_CH_ENABLED20_S) #define SOC_ETM_CH_ENABLED20_V 0x00000001U #define SOC_ETM_CH_ENABLED20_S 20 -/** SOC_ETM_CH_ENABLED21 : R/WTC/WS; bitpos: [21]; default: 0; - * Represents channel21 enable status. +/** SOC_ETM_CH_ENABLED21 : R/WTC/WTS; bitpos: [21]; default: 0; + * Represents ch21 enable status. * 0: Disable * 1: Enable */ @@ -213,8 +213,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED21_M (SOC_ETM_CH_ENABLED21_V << SOC_ETM_CH_ENABLED21_S) #define SOC_ETM_CH_ENABLED21_V 0x00000001U #define SOC_ETM_CH_ENABLED21_S 21 -/** SOC_ETM_CH_ENABLED22 : R/WTC/WS; bitpos: [22]; default: 0; - * Represents channel22 enable status. +/** SOC_ETM_CH_ENABLED22 : R/WTC/WTS; bitpos: [22]; default: 0; + * Represents ch22 enable status. * 0: Disable * 1: Enable */ @@ -222,8 +222,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED22_M (SOC_ETM_CH_ENABLED22_V << SOC_ETM_CH_ENABLED22_S) #define SOC_ETM_CH_ENABLED22_V 0x00000001U #define SOC_ETM_CH_ENABLED22_S 22 -/** SOC_ETM_CH_ENABLED23 : R/WTC/WS; bitpos: [23]; default: 0; - * Represents channel23 enable status. +/** SOC_ETM_CH_ENABLED23 : R/WTC/WTS; bitpos: [23]; default: 0; + * Represents ch23 enable status. * 0: Disable * 1: Enable */ @@ -231,8 +231,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED23_M (SOC_ETM_CH_ENABLED23_V << SOC_ETM_CH_ENABLED23_S) #define SOC_ETM_CH_ENABLED23_V 0x00000001U #define SOC_ETM_CH_ENABLED23_S 23 -/** SOC_ETM_CH_ENABLED24 : R/WTC/WS; bitpos: [24]; default: 0; - * Represents channel24 enable status. +/** SOC_ETM_CH_ENABLED24 : R/WTC/WTS; bitpos: [24]; default: 0; + * Represents ch24 enable status. * 0: Disable * 1: Enable */ @@ -240,8 +240,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED24_M (SOC_ETM_CH_ENABLED24_V << SOC_ETM_CH_ENABLED24_S) #define SOC_ETM_CH_ENABLED24_V 0x00000001U #define SOC_ETM_CH_ENABLED24_S 24 -/** SOC_ETM_CH_ENABLED25 : R/WTC/WS; bitpos: [25]; default: 0; - * Represents channel25 enable status. +/** SOC_ETM_CH_ENABLED25 : R/WTC/WTS; bitpos: [25]; default: 0; + * Represents ch25 enable status. * 0: Disable * 1: Enable */ @@ -249,8 +249,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED25_M (SOC_ETM_CH_ENABLED25_V << SOC_ETM_CH_ENABLED25_S) #define SOC_ETM_CH_ENABLED25_V 0x00000001U #define SOC_ETM_CH_ENABLED25_S 25 -/** SOC_ETM_CH_ENABLED26 : R/WTC/WS; bitpos: [26]; default: 0; - * Represents channel26 enable status. +/** SOC_ETM_CH_ENABLED26 : R/WTC/WTS; bitpos: [26]; default: 0; + * Represents ch26 enable status. * 0: Disable * 1: Enable */ @@ -258,8 +258,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED26_M (SOC_ETM_CH_ENABLED26_V << SOC_ETM_CH_ENABLED26_S) #define SOC_ETM_CH_ENABLED26_V 0x00000001U #define SOC_ETM_CH_ENABLED26_S 26 -/** SOC_ETM_CH_ENABLED27 : R/WTC/WS; bitpos: [27]; default: 0; - * Represents channel27 enable status. +/** SOC_ETM_CH_ENABLED27 : R/WTC/WTS; bitpos: [27]; default: 0; + * Represents ch27 enable status. * 0: Disable * 1: Enable */ @@ -267,8 +267,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED27_M (SOC_ETM_CH_ENABLED27_V << SOC_ETM_CH_ENABLED27_S) #define SOC_ETM_CH_ENABLED27_V 0x00000001U #define SOC_ETM_CH_ENABLED27_S 27 -/** SOC_ETM_CH_ENABLED28 : R/WTC/WS; bitpos: [28]; default: 0; - * Represents channel28 enable status. +/** SOC_ETM_CH_ENABLED28 : R/WTC/WTS; bitpos: [28]; default: 0; + * Represents ch28 enable status. * 0: Disable * 1: Enable */ @@ -276,8 +276,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED28_M (SOC_ETM_CH_ENABLED28_V << SOC_ETM_CH_ENABLED28_S) #define SOC_ETM_CH_ENABLED28_V 0x00000001U #define SOC_ETM_CH_ENABLED28_S 28 -/** SOC_ETM_CH_ENABLED29 : R/WTC/WS; bitpos: [29]; default: 0; - * Represents channel29 enable status. +/** SOC_ETM_CH_ENABLED29 : R/WTC/WTS; bitpos: [29]; default: 0; + * Represents ch29 enable status. * 0: Disable * 1: Enable */ @@ -285,8 +285,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED29_M (SOC_ETM_CH_ENABLED29_V << SOC_ETM_CH_ENABLED29_S) #define SOC_ETM_CH_ENABLED29_V 0x00000001U #define SOC_ETM_CH_ENABLED29_S 29 -/** SOC_ETM_CH_ENABLED30 : R/WTC/WS; bitpos: [30]; default: 0; - * Represents channel30 enable status. +/** SOC_ETM_CH_ENABLED30 : R/WTC/WTS; bitpos: [30]; default: 0; + * Represents ch30 enable status. * 0: Disable * 1: Enable */ @@ -294,8 +294,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED30_M (SOC_ETM_CH_ENABLED30_V << SOC_ETM_CH_ENABLED30_S) #define SOC_ETM_CH_ENABLED30_V 0x00000001U #define SOC_ETM_CH_ENABLED30_S 30 -/** SOC_ETM_CH_ENABLED31 : R/WTC/WS; bitpos: [31]; default: 0; - * Represents channel31 enable status. +/** SOC_ETM_CH_ENABLED31 : R/WTC/WTS; bitpos: [31]; default: 0; + * Represents ch31 enable status. * 0: Disable * 1: Enable */ @@ -305,12 +305,12 @@ extern "C" { #define SOC_ETM_CH_ENABLED31_S 31 /** SOC_ETM_CH_ENA_AD0_SET_REG register - * Channel enable register + * Channel enable set register */ #define SOC_ETM_CH_ENA_AD0_SET_REG (DR_REG_SOC_ETM_BASE + 0x4) /** SOC_ETM_CH_ENABLE0 : WT; bitpos: [0]; default: 0; - * Configures whether or not to enable channel0. - * 0: Invalid. No effect + * Configures whether or not to enable ch0. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE0 (BIT(0)) @@ -318,8 +318,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE0_V 0x00000001U #define SOC_ETM_CH_ENABLE0_S 0 /** SOC_ETM_CH_ENABLE1 : WT; bitpos: [1]; default: 0; - * Configures whether or not to enable channel1. - * 0: Invalid. No effect + * Configures whether or not to enable ch1. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE1 (BIT(1)) @@ -327,8 +327,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE1_V 0x00000001U #define SOC_ETM_CH_ENABLE1_S 1 /** SOC_ETM_CH_ENABLE2 : WT; bitpos: [2]; default: 0; - * Configures whether or not to enable channel2. - * 0: Invalid. No effect + * Configures whether or not to enable ch2. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE2 (BIT(2)) @@ -336,8 +336,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE2_V 0x00000001U #define SOC_ETM_CH_ENABLE2_S 2 /** SOC_ETM_CH_ENABLE3 : WT; bitpos: [3]; default: 0; - * Configures whether or not to enable channel3. - * 0: Invalid. No effect + * Configures whether or not to enable ch3. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE3 (BIT(3)) @@ -345,8 +345,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE3_V 0x00000001U #define SOC_ETM_CH_ENABLE3_S 3 /** SOC_ETM_CH_ENABLE4 : WT; bitpos: [4]; default: 0; - * Configures whether or not to enable channel4. - * 0: Invalid. No effect + * Configures whether or not to enable ch4. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE4 (BIT(4)) @@ -354,8 +354,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE4_V 0x00000001U #define SOC_ETM_CH_ENABLE4_S 4 /** SOC_ETM_CH_ENABLE5 : WT; bitpos: [5]; default: 0; - * Configures whether or not to enable channel5. - * 0: Invalid. No effect + * Configures whether or not to enable ch5. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE5 (BIT(5)) @@ -363,8 +363,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE5_V 0x00000001U #define SOC_ETM_CH_ENABLE5_S 5 /** SOC_ETM_CH_ENABLE6 : WT; bitpos: [6]; default: 0; - * Configures whether or not to enable channel6. - * 0: Invalid. No effect + * Configures whether or not to enable ch6. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE6 (BIT(6)) @@ -372,8 +372,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE6_V 0x00000001U #define SOC_ETM_CH_ENABLE6_S 6 /** SOC_ETM_CH_ENABLE7 : WT; bitpos: [7]; default: 0; - * Configures whether or not to enable channel7. - * 0: Invalid. No effect + * Configures whether or not to enable ch7. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE7 (BIT(7)) @@ -381,8 +381,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE7_V 0x00000001U #define SOC_ETM_CH_ENABLE7_S 7 /** SOC_ETM_CH_ENABLE8 : WT; bitpos: [8]; default: 0; - * Configures whether or not to enable channel8. - * 0: Invalid. No effect + * Configures whether or not to enable ch8. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE8 (BIT(8)) @@ -390,8 +390,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE8_V 0x00000001U #define SOC_ETM_CH_ENABLE8_S 8 /** SOC_ETM_CH_ENABLE9 : WT; bitpos: [9]; default: 0; - * Configures whether or not to enable channel9. - * 0: Invalid. No effect + * Configures whether or not to enable ch9. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE9 (BIT(9)) @@ -399,8 +399,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE9_V 0x00000001U #define SOC_ETM_CH_ENABLE9_S 9 /** SOC_ETM_CH_ENABLE10 : WT; bitpos: [10]; default: 0; - * Configures whether or not to enable channel10. - * 0: Invalid. No effect + * Configures whether or not to enable ch10. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE10 (BIT(10)) @@ -408,8 +408,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE10_V 0x00000001U #define SOC_ETM_CH_ENABLE10_S 10 /** SOC_ETM_CH_ENABLE11 : WT; bitpos: [11]; default: 0; - * Configures whether or not to enable channel11. - * 0: Invalid. No effect + * Configures whether or not to enable ch11. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE11 (BIT(11)) @@ -417,8 +417,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE11_V 0x00000001U #define SOC_ETM_CH_ENABLE11_S 11 /** SOC_ETM_CH_ENABLE12 : WT; bitpos: [12]; default: 0; - * Configures whether or not to enable channel12. - * 0: Invalid. No effect + * Configures whether or not to enable ch12. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE12 (BIT(12)) @@ -426,8 +426,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE12_V 0x00000001U #define SOC_ETM_CH_ENABLE12_S 12 /** SOC_ETM_CH_ENABLE13 : WT; bitpos: [13]; default: 0; - * Configures whether or not to enable channel13. - * 0: Invalid. No effect + * Configures whether or not to enable ch13. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE13 (BIT(13)) @@ -435,8 +435,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE13_V 0x00000001U #define SOC_ETM_CH_ENABLE13_S 13 /** SOC_ETM_CH_ENABLE14 : WT; bitpos: [14]; default: 0; - * Configures whether or not to enable channel14. - * 0: Invalid. No effect + * Configures whether or not to enable ch14. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE14 (BIT(14)) @@ -444,8 +444,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE14_V 0x00000001U #define SOC_ETM_CH_ENABLE14_S 14 /** SOC_ETM_CH_ENABLE15 : WT; bitpos: [15]; default: 0; - * Configures whether or not to enable channel15. - * 0: Invalid. No effect + * Configures whether or not to enable ch15. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE15 (BIT(15)) @@ -453,8 +453,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE15_V 0x00000001U #define SOC_ETM_CH_ENABLE15_S 15 /** SOC_ETM_CH_ENABLE16 : WT; bitpos: [16]; default: 0; - * Configures whether or not to enable channel16. - * 0: Invalid. No effect + * Configures whether or not to enable ch16. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE16 (BIT(16)) @@ -462,8 +462,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE16_V 0x00000001U #define SOC_ETM_CH_ENABLE16_S 16 /** SOC_ETM_CH_ENABLE17 : WT; bitpos: [17]; default: 0; - * Configures whether or not to enable channel17. - * 0: Invalid. No effect + * Configures whether or not to enable ch17. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE17 (BIT(17)) @@ -471,8 +471,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE17_V 0x00000001U #define SOC_ETM_CH_ENABLE17_S 17 /** SOC_ETM_CH_ENABLE18 : WT; bitpos: [18]; default: 0; - * Configures whether or not to enable channel18. - * 0: Invalid. No effect + * Configures whether or not to enable ch18. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE18 (BIT(18)) @@ -480,8 +480,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE18_V 0x00000001U #define SOC_ETM_CH_ENABLE18_S 18 /** SOC_ETM_CH_ENABLE19 : WT; bitpos: [19]; default: 0; - * Configures whether or not to enable channel19. - * 0: Invalid. No effect + * Configures whether or not to enable ch19. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE19 (BIT(19)) @@ -489,8 +489,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE19_V 0x00000001U #define SOC_ETM_CH_ENABLE19_S 19 /** SOC_ETM_CH_ENABLE20 : WT; bitpos: [20]; default: 0; - * Configures whether or not to enable channel20. - * 0: Invalid. No effect + * Configures whether or not to enable ch20. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE20 (BIT(20)) @@ -498,8 +498,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE20_V 0x00000001U #define SOC_ETM_CH_ENABLE20_S 20 /** SOC_ETM_CH_ENABLE21 : WT; bitpos: [21]; default: 0; - * Configures whether or not to enable channel21. - * 0: Invalid. No effect + * Configures whether or not to enable ch21. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE21 (BIT(21)) @@ -507,8 +507,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE21_V 0x00000001U #define SOC_ETM_CH_ENABLE21_S 21 /** SOC_ETM_CH_ENABLE22 : WT; bitpos: [22]; default: 0; - * Configures whether or not to enable channel22. - * 0: Invalid. No effect + * Configures whether or not to enable ch22. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE22 (BIT(22)) @@ -516,8 +516,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE22_V 0x00000001U #define SOC_ETM_CH_ENABLE22_S 22 /** SOC_ETM_CH_ENABLE23 : WT; bitpos: [23]; default: 0; - * Configures whether or not to enable channel23. - * 0: Invalid. No effect + * Configures whether or not to enable ch23. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE23 (BIT(23)) @@ -525,8 +525,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE23_V 0x00000001U #define SOC_ETM_CH_ENABLE23_S 23 /** SOC_ETM_CH_ENABLE24 : WT; bitpos: [24]; default: 0; - * Configures whether or not to enable channel24. - * 0: Invalid. No effect + * Configures whether or not to enable ch24. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE24 (BIT(24)) @@ -534,8 +534,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE24_V 0x00000001U #define SOC_ETM_CH_ENABLE24_S 24 /** SOC_ETM_CH_ENABLE25 : WT; bitpos: [25]; default: 0; - * Configures whether or not to enable channel25. - * 0: Invalid. No effect + * Configures whether or not to enable ch25. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE25 (BIT(25)) @@ -543,8 +543,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE25_V 0x00000001U #define SOC_ETM_CH_ENABLE25_S 25 /** SOC_ETM_CH_ENABLE26 : WT; bitpos: [26]; default: 0; - * Configures whether or not to enable channel26. - * 0: Invalid. No effect + * Configures whether or not to enable ch26. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE26 (BIT(26)) @@ -552,8 +552,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE26_V 0x00000001U #define SOC_ETM_CH_ENABLE26_S 26 /** SOC_ETM_CH_ENABLE27 : WT; bitpos: [27]; default: 0; - * Configures whether or not to enable channel27. - * 0: Invalid. No effect + * Configures whether or not to enable ch27. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE27 (BIT(27)) @@ -561,8 +561,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE27_V 0x00000001U #define SOC_ETM_CH_ENABLE27_S 27 /** SOC_ETM_CH_ENABLE28 : WT; bitpos: [28]; default: 0; - * Configures whether or not to enable channel28. - * 0: Invalid. No effect + * Configures whether or not to enable ch28. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE28 (BIT(28)) @@ -570,8 +570,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE28_V 0x00000001U #define SOC_ETM_CH_ENABLE28_S 28 /** SOC_ETM_CH_ENABLE29 : WT; bitpos: [29]; default: 0; - * Configures whether or not to enable channel29. - * 0: Invalid. No effect + * Configures whether or not to enable ch29. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE29 (BIT(29)) @@ -579,8 +579,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE29_V 0x00000001U #define SOC_ETM_CH_ENABLE29_S 29 /** SOC_ETM_CH_ENABLE30 : WT; bitpos: [30]; default: 0; - * Configures whether or not to enable channel30. - * 0: Invalid. No effect + * Configures whether or not to enable ch30. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE30 (BIT(30)) @@ -588,8 +588,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE30_V 0x00000001U #define SOC_ETM_CH_ENABLE30_S 30 /** SOC_ETM_CH_ENABLE31 : WT; bitpos: [31]; default: 0; - * Configures whether or not to enable channel31. - * 0: Invalid. No effect + * Configures whether or not to enable ch31. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE31 (BIT(31)) @@ -598,12 +598,12 @@ extern "C" { #define SOC_ETM_CH_ENABLE31_S 31 /** SOC_ETM_CH_ENA_AD0_CLR_REG register - * Channel disable register + * Channel enable clear register */ #define SOC_ETM_CH_ENA_AD0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x8) /** SOC_ETM_CH_DISABLE0 : WT; bitpos: [0]; default: 0; - * Configures whether or not to disable channel0. - * 0: Invalid. No effect + * Configures whether or not to clear ch0 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE0 (BIT(0)) @@ -611,8 +611,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE0_V 0x00000001U #define SOC_ETM_CH_DISABLE0_S 0 /** SOC_ETM_CH_DISABLE1 : WT; bitpos: [1]; default: 0; - * Configures whether or not to disable channel1. - * 0: Invalid. No effect + * Configures whether or not to clear ch1 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE1 (BIT(1)) @@ -620,8 +620,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE1_V 0x00000001U #define SOC_ETM_CH_DISABLE1_S 1 /** SOC_ETM_CH_DISABLE2 : WT; bitpos: [2]; default: 0; - * Configures whether or not to disable channel2. - * 0: Invalid. No effect + * Configures whether or not to clear ch2 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE2 (BIT(2)) @@ -629,8 +629,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE2_V 0x00000001U #define SOC_ETM_CH_DISABLE2_S 2 /** SOC_ETM_CH_DISABLE3 : WT; bitpos: [3]; default: 0; - * Configures whether or not to disable channel3. - * 0: Invalid. No effect + * Configures whether or not to clear ch3 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE3 (BIT(3)) @@ -638,8 +638,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE3_V 0x00000001U #define SOC_ETM_CH_DISABLE3_S 3 /** SOC_ETM_CH_DISABLE4 : WT; bitpos: [4]; default: 0; - * Configures whether or not to disable channel4. - * 0: Invalid. No effect + * Configures whether or not to clear ch4 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE4 (BIT(4)) @@ -647,8 +647,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE4_V 0x00000001U #define SOC_ETM_CH_DISABLE4_S 4 /** SOC_ETM_CH_DISABLE5 : WT; bitpos: [5]; default: 0; - * Configures whether or not to disable channel5. - * 0: Invalid. No effect + * Configures whether or not to clear ch5 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE5 (BIT(5)) @@ -656,8 +656,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE5_V 0x00000001U #define SOC_ETM_CH_DISABLE5_S 5 /** SOC_ETM_CH_DISABLE6 : WT; bitpos: [6]; default: 0; - * Configures whether or not to disable channel6. - * 0: Invalid. No effect + * Configures whether or not to clear ch6 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE6 (BIT(6)) @@ -665,8 +665,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE6_V 0x00000001U #define SOC_ETM_CH_DISABLE6_S 6 /** SOC_ETM_CH_DISABLE7 : WT; bitpos: [7]; default: 0; - * Configures whether or not to disable channel7. - * 0: Invalid. No effect + * Configures whether or not to clear ch7 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE7 (BIT(7)) @@ -674,8 +674,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE7_V 0x00000001U #define SOC_ETM_CH_DISABLE7_S 7 /** SOC_ETM_CH_DISABLE8 : WT; bitpos: [8]; default: 0; - * Configures whether or not to disable channel8. - * 0: Invalid. No effect + * Configures whether or not to clear ch8 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE8 (BIT(8)) @@ -683,8 +683,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE8_V 0x00000001U #define SOC_ETM_CH_DISABLE8_S 8 /** SOC_ETM_CH_DISABLE9 : WT; bitpos: [9]; default: 0; - * Configures whether or not to disable channel9. - * 0: Invalid. No effect + * Configures whether or not to clear ch9 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE9 (BIT(9)) @@ -692,8 +692,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE9_V 0x00000001U #define SOC_ETM_CH_DISABLE9_S 9 /** SOC_ETM_CH_DISABLE10 : WT; bitpos: [10]; default: 0; - * Configures whether or not to disable channel10. - * 0: Invalid. No effect + * Configures whether or not to clear ch10 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE10 (BIT(10)) @@ -701,8 +701,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE10_V 0x00000001U #define SOC_ETM_CH_DISABLE10_S 10 /** SOC_ETM_CH_DISABLE11 : WT; bitpos: [11]; default: 0; - * Configures whether or not to disable channel11. - * 0: Invalid. No effect + * Configures whether or not to clear ch11 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE11 (BIT(11)) @@ -710,8 +710,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE11_V 0x00000001U #define SOC_ETM_CH_DISABLE11_S 11 /** SOC_ETM_CH_DISABLE12 : WT; bitpos: [12]; default: 0; - * Configures whether or not to disable channel12. - * 0: Invalid. No effect + * Configures whether or not to clear ch12 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE12 (BIT(12)) @@ -719,8 +719,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE12_V 0x00000001U #define SOC_ETM_CH_DISABLE12_S 12 /** SOC_ETM_CH_DISABLE13 : WT; bitpos: [13]; default: 0; - * Configures whether or not to disable channel13. - * 0: Invalid. No effect + * Configures whether or not to clear ch13 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE13 (BIT(13)) @@ -728,8 +728,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE13_V 0x00000001U #define SOC_ETM_CH_DISABLE13_S 13 /** SOC_ETM_CH_DISABLE14 : WT; bitpos: [14]; default: 0; - * Configures whether or not to disable channel14. - * 0: Invalid. No effect + * Configures whether or not to clear ch14 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE14 (BIT(14)) @@ -737,8 +737,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE14_V 0x00000001U #define SOC_ETM_CH_DISABLE14_S 14 /** SOC_ETM_CH_DISABLE15 : WT; bitpos: [15]; default: 0; - * Configures whether or not to disable channel15. - * 0: Invalid. No effect + * Configures whether or not to clear ch15 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE15 (BIT(15)) @@ -746,8 +746,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE15_V 0x00000001U #define SOC_ETM_CH_DISABLE15_S 15 /** SOC_ETM_CH_DISABLE16 : WT; bitpos: [16]; default: 0; - * Configures whether or not to disable channel16. - * 0: Invalid. No effect + * Configures whether or not to clear ch16 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE16 (BIT(16)) @@ -755,8 +755,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE16_V 0x00000001U #define SOC_ETM_CH_DISABLE16_S 16 /** SOC_ETM_CH_DISABLE17 : WT; bitpos: [17]; default: 0; - * Configures whether or not to disable channel17. - * 0: Invalid. No effect + * Configures whether or not to clear ch17 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE17 (BIT(17)) @@ -764,8 +764,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE17_V 0x00000001U #define SOC_ETM_CH_DISABLE17_S 17 /** SOC_ETM_CH_DISABLE18 : WT; bitpos: [18]; default: 0; - * Configures whether or not to disable channel18. - * 0: Invalid. No effect + * Configures whether or not to clear ch18 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE18 (BIT(18)) @@ -773,8 +773,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE18_V 0x00000001U #define SOC_ETM_CH_DISABLE18_S 18 /** SOC_ETM_CH_DISABLE19 : WT; bitpos: [19]; default: 0; - * Configures whether or not to disable channel19. - * 0: Invalid. No effect + * Configures whether or not to clear ch19 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE19 (BIT(19)) @@ -782,8 +782,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE19_V 0x00000001U #define SOC_ETM_CH_DISABLE19_S 19 /** SOC_ETM_CH_DISABLE20 : WT; bitpos: [20]; default: 0; - * Configures whether or not to disable channel20. - * 0: Invalid. No effect + * Configures whether or not to clear ch20 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE20 (BIT(20)) @@ -791,8 +791,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE20_V 0x00000001U #define SOC_ETM_CH_DISABLE20_S 20 /** SOC_ETM_CH_DISABLE21 : WT; bitpos: [21]; default: 0; - * Configures whether or not to disable channel21. - * 0: Invalid. No effect + * Configures whether or not to clear ch21 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE21 (BIT(21)) @@ -800,8 +800,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE21_V 0x00000001U #define SOC_ETM_CH_DISABLE21_S 21 /** SOC_ETM_CH_DISABLE22 : WT; bitpos: [22]; default: 0; - * Configures whether or not to disable channel22. - * 0: Invalid. No effect + * Configures whether or not to clear ch22 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE22 (BIT(22)) @@ -809,8 +809,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE22_V 0x00000001U #define SOC_ETM_CH_DISABLE22_S 22 /** SOC_ETM_CH_DISABLE23 : WT; bitpos: [23]; default: 0; - * Configures whether or not to disable channel23. - * 0: Invalid. No effect + * Configures whether or not to clear ch23 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE23 (BIT(23)) @@ -818,8 +818,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE23_V 0x00000001U #define SOC_ETM_CH_DISABLE23_S 23 /** SOC_ETM_CH_DISABLE24 : WT; bitpos: [24]; default: 0; - * Configures whether or not to disable channel24. - * 0: Invalid. No effect + * Configures whether or not to clear ch24 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE24 (BIT(24)) @@ -827,8 +827,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE24_V 0x00000001U #define SOC_ETM_CH_DISABLE24_S 24 /** SOC_ETM_CH_DISABLE25 : WT; bitpos: [25]; default: 0; - * Configures whether or not to disable channel25. - * 0: Invalid. No effect + * Configures whether or not to clear ch25 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE25 (BIT(25)) @@ -836,8 +836,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE25_V 0x00000001U #define SOC_ETM_CH_DISABLE25_S 25 /** SOC_ETM_CH_DISABLE26 : WT; bitpos: [26]; default: 0; - * Configures whether or not to disable channel26. - * 0: Invalid. No effect + * Configures whether or not to clear ch26 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE26 (BIT(26)) @@ -845,8 +845,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE26_V 0x00000001U #define SOC_ETM_CH_DISABLE26_S 26 /** SOC_ETM_CH_DISABLE27 : WT; bitpos: [27]; default: 0; - * Configures whether or not to disable channel27. - * 0: Invalid. No effect + * Configures whether or not to clear ch27 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE27 (BIT(27)) @@ -854,8 +854,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE27_V 0x00000001U #define SOC_ETM_CH_DISABLE27_S 27 /** SOC_ETM_CH_DISABLE28 : WT; bitpos: [28]; default: 0; - * Configures whether or not to disable channel28. - * 0: Invalid. No effect + * Configures whether or not to clear ch28 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE28 (BIT(28)) @@ -863,8 +863,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE28_V 0x00000001U #define SOC_ETM_CH_DISABLE28_S 28 /** SOC_ETM_CH_DISABLE29 : WT; bitpos: [29]; default: 0; - * Configures whether or not to disable channel29. - * 0: Invalid. No effect + * Configures whether or not to clear ch29 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE29 (BIT(29)) @@ -872,8 +872,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE29_V 0x00000001U #define SOC_ETM_CH_DISABLE29_S 29 /** SOC_ETM_CH_DISABLE30 : WT; bitpos: [30]; default: 0; - * Configures whether or not to disable channel30. - * 0: Invalid. No effect + * Configures whether or not to clear ch30 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE30 (BIT(30)) @@ -881,8 +881,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE30_V 0x00000001U #define SOC_ETM_CH_DISABLE30_S 30 /** SOC_ETM_CH_DISABLE31 : WT; bitpos: [31]; default: 0; - * Configures whether or not to disable channel31. - * 0: Invalid. No effect + * Configures whether or not to clear ch31 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE31 (BIT(31)) @@ -894,8 +894,8 @@ extern "C" { * Channel enable status register */ #define SOC_ETM_CH_ENA_AD1_REG (DR_REG_SOC_ETM_BASE + 0xc) -/** SOC_ETM_CH_ENABLED32 : R/WTC/WS; bitpos: [0]; default: 0; - * Represents channel32 enable status. +/** SOC_ETM_CH_ENABLED32 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch32 enable status. * 0: Disable * 1: Enable */ @@ -903,8 +903,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED32_M (SOC_ETM_CH_ENABLED32_V << SOC_ETM_CH_ENABLED32_S) #define SOC_ETM_CH_ENABLED32_V 0x00000001U #define SOC_ETM_CH_ENABLED32_S 0 -/** SOC_ETM_CH_ENABLED33 : R/WTC/WS; bitpos: [1]; default: 0; - * Represents channel33 enable status. +/** SOC_ETM_CH_ENABLED33 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch33 enable status. * 0: Disable * 1: Enable */ @@ -912,8 +912,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED33_M (SOC_ETM_CH_ENABLED33_V << SOC_ETM_CH_ENABLED33_S) #define SOC_ETM_CH_ENABLED33_V 0x00000001U #define SOC_ETM_CH_ENABLED33_S 1 -/** SOC_ETM_CH_ENABLED34 : R/WTC/WS; bitpos: [2]; default: 0; - * Represents channel34 enable status. +/** SOC_ETM_CH_ENABLED34 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch34 enable status. * 0: Disable * 1: Enable */ @@ -921,8 +921,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED34_M (SOC_ETM_CH_ENABLED34_V << SOC_ETM_CH_ENABLED34_S) #define SOC_ETM_CH_ENABLED34_V 0x00000001U #define SOC_ETM_CH_ENABLED34_S 2 -/** SOC_ETM_CH_ENABLED35 : R/WTC/WS; bitpos: [3]; default: 0; - * Represents channel35 enable status. +/** SOC_ETM_CH_ENABLED35 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch35 enable status. * 0: Disable * 1: Enable */ @@ -930,8 +930,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED35_M (SOC_ETM_CH_ENABLED35_V << SOC_ETM_CH_ENABLED35_S) #define SOC_ETM_CH_ENABLED35_V 0x00000001U #define SOC_ETM_CH_ENABLED35_S 3 -/** SOC_ETM_CH_ENABLED36 : R/WTC/WS; bitpos: [4]; default: 0; - * Represents channel36 enable status. +/** SOC_ETM_CH_ENABLED36 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch36 enable status. * 0: Disable * 1: Enable */ @@ -939,8 +939,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED36_M (SOC_ETM_CH_ENABLED36_V << SOC_ETM_CH_ENABLED36_S) #define SOC_ETM_CH_ENABLED36_V 0x00000001U #define SOC_ETM_CH_ENABLED36_S 4 -/** SOC_ETM_CH_ENABLED37 : R/WTC/WS; bitpos: [5]; default: 0; - * Represents channel37 enable status. +/** SOC_ETM_CH_ENABLED37 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch37 enable status. * 0: Disable * 1: Enable */ @@ -948,8 +948,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED37_M (SOC_ETM_CH_ENABLED37_V << SOC_ETM_CH_ENABLED37_S) #define SOC_ETM_CH_ENABLED37_V 0x00000001U #define SOC_ETM_CH_ENABLED37_S 5 -/** SOC_ETM_CH_ENABLED38 : R/WTC/WS; bitpos: [6]; default: 0; - * Represents channel38 enable status. +/** SOC_ETM_CH_ENABLED38 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch38 enable status. * 0: Disable * 1: Enable */ @@ -957,8 +957,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED38_M (SOC_ETM_CH_ENABLED38_V << SOC_ETM_CH_ENABLED38_S) #define SOC_ETM_CH_ENABLED38_V 0x00000001U #define SOC_ETM_CH_ENABLED38_S 6 -/** SOC_ETM_CH_ENABLED39 : R/WTC/WS; bitpos: [7]; default: 0; - * Represents channel39 enable status. +/** SOC_ETM_CH_ENABLED39 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch39 enable status. * 0: Disable * 1: Enable */ @@ -966,8 +966,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED39_M (SOC_ETM_CH_ENABLED39_V << SOC_ETM_CH_ENABLED39_S) #define SOC_ETM_CH_ENABLED39_V 0x00000001U #define SOC_ETM_CH_ENABLED39_S 7 -/** SOC_ETM_CH_ENABLED40 : R/WTC/WS; bitpos: [8]; default: 0; - * Represents channel40 enable status. +/** SOC_ETM_CH_ENABLED40 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch40 enable status. * 0: Disable * 1: Enable */ @@ -975,8 +975,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED40_M (SOC_ETM_CH_ENABLED40_V << SOC_ETM_CH_ENABLED40_S) #define SOC_ETM_CH_ENABLED40_V 0x00000001U #define SOC_ETM_CH_ENABLED40_S 8 -/** SOC_ETM_CH_ENABLED41 : R/WTC/WS; bitpos: [9]; default: 0; - * Represents channel41 enable status. +/** SOC_ETM_CH_ENABLED41 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch41 enable status. * 0: Disable * 1: Enable */ @@ -984,8 +984,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED41_M (SOC_ETM_CH_ENABLED41_V << SOC_ETM_CH_ENABLED41_S) #define SOC_ETM_CH_ENABLED41_V 0x00000001U #define SOC_ETM_CH_ENABLED41_S 9 -/** SOC_ETM_CH_ENABLED42 : R/WTC/WS; bitpos: [10]; default: 0; - * Represents channel42 enable status. +/** SOC_ETM_CH_ENABLED42 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch42 enable status. * 0: Disable * 1: Enable */ @@ -993,8 +993,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED42_M (SOC_ETM_CH_ENABLED42_V << SOC_ETM_CH_ENABLED42_S) #define SOC_ETM_CH_ENABLED42_V 0x00000001U #define SOC_ETM_CH_ENABLED42_S 10 -/** SOC_ETM_CH_ENABLED43 : R/WTC/WS; bitpos: [11]; default: 0; - * Represents channel43 enable status. +/** SOC_ETM_CH_ENABLED43 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch43 enable status. * 0: Disable * 1: Enable */ @@ -1002,8 +1002,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED43_M (SOC_ETM_CH_ENABLED43_V << SOC_ETM_CH_ENABLED43_S) #define SOC_ETM_CH_ENABLED43_V 0x00000001U #define SOC_ETM_CH_ENABLED43_S 11 -/** SOC_ETM_CH_ENABLED44 : R/WTC/WS; bitpos: [12]; default: 0; - * Represents channel44 enable status. +/** SOC_ETM_CH_ENABLED44 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch44 enable status. * 0: Disable * 1: Enable */ @@ -1011,8 +1011,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED44_M (SOC_ETM_CH_ENABLED44_V << SOC_ETM_CH_ENABLED44_S) #define SOC_ETM_CH_ENABLED44_V 0x00000001U #define SOC_ETM_CH_ENABLED44_S 12 -/** SOC_ETM_CH_ENABLED45 : R/WTC/WS; bitpos: [13]; default: 0; - * Represents channel45 enable status. +/** SOC_ETM_CH_ENABLED45 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch45 enable status. * 0: Disable * 1: Enable */ @@ -1020,8 +1020,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED45_M (SOC_ETM_CH_ENABLED45_V << SOC_ETM_CH_ENABLED45_S) #define SOC_ETM_CH_ENABLED45_V 0x00000001U #define SOC_ETM_CH_ENABLED45_S 13 -/** SOC_ETM_CH_ENABLED46 : R/WTC/WS; bitpos: [14]; default: 0; - * Represents channel46 enable status. +/** SOC_ETM_CH_ENABLED46 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch46 enable status. * 0: Disable * 1: Enable */ @@ -1029,8 +1029,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED46_M (SOC_ETM_CH_ENABLED46_V << SOC_ETM_CH_ENABLED46_S) #define SOC_ETM_CH_ENABLED46_V 0x00000001U #define SOC_ETM_CH_ENABLED46_S 14 -/** SOC_ETM_CH_ENABLED47 : R/WTC/WS; bitpos: [15]; default: 0; - * Represents channel47 enable status. +/** SOC_ETM_CH_ENABLED47 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch47 enable status. * 0: Disable * 1: Enable */ @@ -1038,8 +1038,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED47_M (SOC_ETM_CH_ENABLED47_V << SOC_ETM_CH_ENABLED47_S) #define SOC_ETM_CH_ENABLED47_V 0x00000001U #define SOC_ETM_CH_ENABLED47_S 15 -/** SOC_ETM_CH_ENABLED48 : R/WTC/WS; bitpos: [16]; default: 0; - * Represents channel48 enable status. +/** SOC_ETM_CH_ENABLED48 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch48 enable status. * 0: Disable * 1: Enable */ @@ -1047,8 +1047,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED48_M (SOC_ETM_CH_ENABLED48_V << SOC_ETM_CH_ENABLED48_S) #define SOC_ETM_CH_ENABLED48_V 0x00000001U #define SOC_ETM_CH_ENABLED48_S 16 -/** SOC_ETM_CH_ENABLED49 : R/WTC/WS; bitpos: [17]; default: 0; - * Represents channel49 enable status. +/** SOC_ETM_CH_ENABLED49 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch49 enable status. * 0: Disable * 1: Enable */ @@ -1058,12 +1058,12 @@ extern "C" { #define SOC_ETM_CH_ENABLED49_S 17 /** SOC_ETM_CH_ENA_AD1_SET_REG register - * Channel enable register + * Channel enable set register */ #define SOC_ETM_CH_ENA_AD1_SET_REG (DR_REG_SOC_ETM_BASE + 0x10) /** SOC_ETM_CH_ENABLE32 : WT; bitpos: [0]; default: 0; - * Configures whether or not to enable channel32. - * 0: Invalid. No effect + * Configures whether or not to enable ch32. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE32 (BIT(0)) @@ -1071,8 +1071,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE32_V 0x00000001U #define SOC_ETM_CH_ENABLE32_S 0 /** SOC_ETM_CH_ENABLE33 : WT; bitpos: [1]; default: 0; - * Configures whether or not to enable channel33. - * 0: Invalid. No effect + * Configures whether or not to enable ch33. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE33 (BIT(1)) @@ -1080,8 +1080,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE33_V 0x00000001U #define SOC_ETM_CH_ENABLE33_S 1 /** SOC_ETM_CH_ENABLE34 : WT; bitpos: [2]; default: 0; - * Configures whether or not to enable channel34. - * 0: Invalid. No effect + * Configures whether or not to enable ch34. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE34 (BIT(2)) @@ -1089,8 +1089,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE34_V 0x00000001U #define SOC_ETM_CH_ENABLE34_S 2 /** SOC_ETM_CH_ENABLE35 : WT; bitpos: [3]; default: 0; - * Configures whether or not to enable channel35. - * 0: Invalid. No effect + * Configures whether or not to enable ch35. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE35 (BIT(3)) @@ -1098,8 +1098,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE35_V 0x00000001U #define SOC_ETM_CH_ENABLE35_S 3 /** SOC_ETM_CH_ENABLE36 : WT; bitpos: [4]; default: 0; - * Configures whether or not to enable channel36. - * 0: Invalid. No effect + * Configures whether or not to enable ch36. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE36 (BIT(4)) @@ -1107,8 +1107,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE36_V 0x00000001U #define SOC_ETM_CH_ENABLE36_S 4 /** SOC_ETM_CH_ENABLE37 : WT; bitpos: [5]; default: 0; - * Configures whether or not to enable channel37. - * 0: Invalid. No effect + * Configures whether or not to enable ch37. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE37 (BIT(5)) @@ -1116,8 +1116,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE37_V 0x00000001U #define SOC_ETM_CH_ENABLE37_S 5 /** SOC_ETM_CH_ENABLE38 : WT; bitpos: [6]; default: 0; - * Configures whether or not to enable channel38. - * 0: Invalid. No effect + * Configures whether or not to enable ch38. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE38 (BIT(6)) @@ -1125,8 +1125,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE38_V 0x00000001U #define SOC_ETM_CH_ENABLE38_S 6 /** SOC_ETM_CH_ENABLE39 : WT; bitpos: [7]; default: 0; - * Configures whether or not to enable channel39. - * 0: Invalid. No effect + * Configures whether or not to enable ch39. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE39 (BIT(7)) @@ -1134,8 +1134,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE39_V 0x00000001U #define SOC_ETM_CH_ENABLE39_S 7 /** SOC_ETM_CH_ENABLE40 : WT; bitpos: [8]; default: 0; - * Configures whether or not to enable channel40. - * 0: Invalid. No effect + * Configures whether or not to enable ch40. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE40 (BIT(8)) @@ -1143,8 +1143,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE40_V 0x00000001U #define SOC_ETM_CH_ENABLE40_S 8 /** SOC_ETM_CH_ENABLE41 : WT; bitpos: [9]; default: 0; - * Configures whether or not to enable channel41. - * 0: Invalid. No effect + * Configures whether or not to enable ch41. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE41 (BIT(9)) @@ -1152,8 +1152,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE41_V 0x00000001U #define SOC_ETM_CH_ENABLE41_S 9 /** SOC_ETM_CH_ENABLE42 : WT; bitpos: [10]; default: 0; - * Configures whether or not to enable channel42. - * 0: Invalid. No effect + * Configures whether or not to enable ch42. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE42 (BIT(10)) @@ -1161,8 +1161,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE42_V 0x00000001U #define SOC_ETM_CH_ENABLE42_S 10 /** SOC_ETM_CH_ENABLE43 : WT; bitpos: [11]; default: 0; - * Configures whether or not to enable channel43. - * 0: Invalid. No effect + * Configures whether or not to enable ch43. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE43 (BIT(11)) @@ -1170,8 +1170,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE43_V 0x00000001U #define SOC_ETM_CH_ENABLE43_S 11 /** SOC_ETM_CH_ENABLE44 : WT; bitpos: [12]; default: 0; - * Configures whether or not to enable channel44. - * 0: Invalid. No effect + * Configures whether or not to enable ch44. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE44 (BIT(12)) @@ -1179,8 +1179,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE44_V 0x00000001U #define SOC_ETM_CH_ENABLE44_S 12 /** SOC_ETM_CH_ENABLE45 : WT; bitpos: [13]; default: 0; - * Configures whether or not to enable channel45. - * 0: Invalid. No effect + * Configures whether or not to enable ch45. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE45 (BIT(13)) @@ -1188,8 +1188,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE45_V 0x00000001U #define SOC_ETM_CH_ENABLE45_S 13 /** SOC_ETM_CH_ENABLE46 : WT; bitpos: [14]; default: 0; - * Configures whether or not to enable channel46. - * 0: Invalid. No effect + * Configures whether or not to enable ch46. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE46 (BIT(14)) @@ -1197,8 +1197,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE46_V 0x00000001U #define SOC_ETM_CH_ENABLE46_S 14 /** SOC_ETM_CH_ENABLE47 : WT; bitpos: [15]; default: 0; - * Configures whether or not to enable channel47. - * 0: Invalid. No effect + * Configures whether or not to enable ch47. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE47 (BIT(15)) @@ -1206,8 +1206,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE47_V 0x00000001U #define SOC_ETM_CH_ENABLE47_S 15 /** SOC_ETM_CH_ENABLE48 : WT; bitpos: [16]; default: 0; - * Configures whether or not to enable channel48. - * 0: Invalid. No effect + * Configures whether or not to enable ch48. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE48 (BIT(16)) @@ -1215,8 +1215,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE48_V 0x00000001U #define SOC_ETM_CH_ENABLE48_S 16 /** SOC_ETM_CH_ENABLE49 : WT; bitpos: [17]; default: 0; - * Configures whether or not to enable channel49. - * 0: Invalid. No effect + * Configures whether or not to enable ch49. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE49 (BIT(17)) @@ -1225,12 +1225,12 @@ extern "C" { #define SOC_ETM_CH_ENABLE49_S 17 /** SOC_ETM_CH_ENA_AD1_CLR_REG register - * Channel disable register + * Channel enable clear register */ #define SOC_ETM_CH_ENA_AD1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x14) /** SOC_ETM_CH_DISABLE32 : WT; bitpos: [0]; default: 0; - * Configures whether or not to disable channel32. - * 0: Invalid. No effect + * Configures whether or not to clear ch32 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE32 (BIT(0)) @@ -1238,8 +1238,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE32_V 0x00000001U #define SOC_ETM_CH_DISABLE32_S 0 /** SOC_ETM_CH_DISABLE33 : WT; bitpos: [1]; default: 0; - * Configures whether or not to disable channel33. - * 0: Invalid. No effect + * Configures whether or not to clear ch33 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE33 (BIT(1)) @@ -1247,8 +1247,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE33_V 0x00000001U #define SOC_ETM_CH_DISABLE33_S 1 /** SOC_ETM_CH_DISABLE34 : WT; bitpos: [2]; default: 0; - * Configures whether or not to disable channel34. - * 0: Invalid. No effect + * Configures whether or not to clear ch34 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE34 (BIT(2)) @@ -1256,8 +1256,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE34_V 0x00000001U #define SOC_ETM_CH_DISABLE34_S 2 /** SOC_ETM_CH_DISABLE35 : WT; bitpos: [3]; default: 0; - * Configures whether or not to disable channel35. - * 0: Invalid. No effect + * Configures whether or not to clear ch35 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE35 (BIT(3)) @@ -1265,8 +1265,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE35_V 0x00000001U #define SOC_ETM_CH_DISABLE35_S 3 /** SOC_ETM_CH_DISABLE36 : WT; bitpos: [4]; default: 0; - * Configures whether or not to disable channel36. - * 0: Invalid. No effect + * Configures whether or not to clear ch36 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE36 (BIT(4)) @@ -1274,8 +1274,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE36_V 0x00000001U #define SOC_ETM_CH_DISABLE36_S 4 /** SOC_ETM_CH_DISABLE37 : WT; bitpos: [5]; default: 0; - * Configures whether or not to disable channel37. - * 0: Invalid. No effect + * Configures whether or not to clear ch37 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE37 (BIT(5)) @@ -1283,8 +1283,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE37_V 0x00000001U #define SOC_ETM_CH_DISABLE37_S 5 /** SOC_ETM_CH_DISABLE38 : WT; bitpos: [6]; default: 0; - * Configures whether or not to disable channel38. - * 0: Invalid. No effect + * Configures whether or not to clear ch38 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE38 (BIT(6)) @@ -1292,8 +1292,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE38_V 0x00000001U #define SOC_ETM_CH_DISABLE38_S 6 /** SOC_ETM_CH_DISABLE39 : WT; bitpos: [7]; default: 0; - * Configures whether or not to disable channel39. - * 0: Invalid. No effect + * Configures whether or not to clear ch39 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE39 (BIT(7)) @@ -1301,8 +1301,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE39_V 0x00000001U #define SOC_ETM_CH_DISABLE39_S 7 /** SOC_ETM_CH_DISABLE40 : WT; bitpos: [8]; default: 0; - * Configures whether or not to disable channel40. - * 0: Invalid. No effect + * Configures whether or not to clear ch40 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE40 (BIT(8)) @@ -1310,8 +1310,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE40_V 0x00000001U #define SOC_ETM_CH_DISABLE40_S 8 /** SOC_ETM_CH_DISABLE41 : WT; bitpos: [9]; default: 0; - * Configures whether or not to disable channel41. - * 0: Invalid. No effect + * Configures whether or not to clear ch41 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE41 (BIT(9)) @@ -1319,8 +1319,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE41_V 0x00000001U #define SOC_ETM_CH_DISABLE41_S 9 /** SOC_ETM_CH_DISABLE42 : WT; bitpos: [10]; default: 0; - * Configures whether or not to disable channel42. - * 0: Invalid. No effect + * Configures whether or not to clear ch42 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE42 (BIT(10)) @@ -1328,8 +1328,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE42_V 0x00000001U #define SOC_ETM_CH_DISABLE42_S 10 /** SOC_ETM_CH_DISABLE43 : WT; bitpos: [11]; default: 0; - * Configures whether or not to disable channel43. - * 0: Invalid. No effect + * Configures whether or not to clear ch43 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE43 (BIT(11)) @@ -1337,8 +1337,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE43_V 0x00000001U #define SOC_ETM_CH_DISABLE43_S 11 /** SOC_ETM_CH_DISABLE44 : WT; bitpos: [12]; default: 0; - * Configures whether or not to disable channel44. - * 0: Invalid. No effect + * Configures whether or not to clear ch44 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE44 (BIT(12)) @@ -1346,8 +1346,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE44_V 0x00000001U #define SOC_ETM_CH_DISABLE44_S 12 /** SOC_ETM_CH_DISABLE45 : WT; bitpos: [13]; default: 0; - * Configures whether or not to disable channel45. - * 0: Invalid. No effect + * Configures whether or not to clear ch45 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE45 (BIT(13)) @@ -1355,8 +1355,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE45_V 0x00000001U #define SOC_ETM_CH_DISABLE45_S 13 /** SOC_ETM_CH_DISABLE46 : WT; bitpos: [14]; default: 0; - * Configures whether or not to disable channel46. - * 0: Invalid. No effect + * Configures whether or not to clear ch46 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE46 (BIT(14)) @@ -1364,8 +1364,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE46_V 0x00000001U #define SOC_ETM_CH_DISABLE46_S 14 /** SOC_ETM_CH_DISABLE47 : WT; bitpos: [15]; default: 0; - * Configures whether or not to disable channel47. - * 0: Invalid. No effect + * Configures whether or not to clear ch47 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE47 (BIT(15)) @@ -1373,8 +1373,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE47_V 0x00000001U #define SOC_ETM_CH_DISABLE47_S 15 /** SOC_ETM_CH_DISABLE48 : WT; bitpos: [16]; default: 0; - * Configures whether or not to disable channel48. - * 0: Invalid. No effect + * Configures whether or not to clear ch48 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE48 (BIT(16)) @@ -1382,8 +1382,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE48_V 0x00000001U #define SOC_ETM_CH_DISABLE48_S 16 /** SOC_ETM_CH_DISABLE49 : WT; bitpos: [17]; default: 0; - * Configures whether or not to disable channel49. - * 0: Invalid. No effect + * Configures whether or not to clear ch49 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE49 (BIT(17)) @@ -1392,11 +1392,11 @@ extern "C" { #define SOC_ETM_CH_DISABLE49_S 17 /** SOC_ETM_CH0_EVT_ID_REG register - * Channel0 event ID register + * Channel0 event id register */ #define SOC_ETM_CH0_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x18) /** SOC_ETM_CH0_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel0 event ID. + * Configures ch0_evt_id */ #define SOC_ETM_CH0_EVT_ID 0x0000007FU #define SOC_ETM_CH0_EVT_ID_M (SOC_ETM_CH0_EVT_ID_V << SOC_ETM_CH0_EVT_ID_S) @@ -1404,11 +1404,11 @@ extern "C" { #define SOC_ETM_CH0_EVT_ID_S 0 /** SOC_ETM_CH0_TASK_ID_REG register - * Channel0 task ID register + * Channel0 task id register */ #define SOC_ETM_CH0_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1c) /** SOC_ETM_CH0_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel0 task ID. + * Configures ch0_task_id */ #define SOC_ETM_CH0_TASK_ID 0x000000FFU #define SOC_ETM_CH0_TASK_ID_M (SOC_ETM_CH0_TASK_ID_V << SOC_ETM_CH0_TASK_ID_S) @@ -1416,11 +1416,11 @@ extern "C" { #define SOC_ETM_CH0_TASK_ID_S 0 /** SOC_ETM_CH1_EVT_ID_REG register - * Channel1 event ID register + * Channel1 event id register */ #define SOC_ETM_CH1_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x20) /** SOC_ETM_CH1_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel1 event ID. + * Configures ch1_evt_id */ #define SOC_ETM_CH1_EVT_ID 0x0000007FU #define SOC_ETM_CH1_EVT_ID_M (SOC_ETM_CH1_EVT_ID_V << SOC_ETM_CH1_EVT_ID_S) @@ -1428,11 +1428,11 @@ extern "C" { #define SOC_ETM_CH1_EVT_ID_S 0 /** SOC_ETM_CH1_TASK_ID_REG register - * Channel1 task ID register + * Channel1 task id register */ #define SOC_ETM_CH1_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x24) /** SOC_ETM_CH1_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel1 task ID. + * Configures ch1_task_id */ #define SOC_ETM_CH1_TASK_ID 0x000000FFU #define SOC_ETM_CH1_TASK_ID_M (SOC_ETM_CH1_TASK_ID_V << SOC_ETM_CH1_TASK_ID_S) @@ -1440,11 +1440,11 @@ extern "C" { #define SOC_ETM_CH1_TASK_ID_S 0 /** SOC_ETM_CH2_EVT_ID_REG register - * Channel2 event ID register + * Channel2 event id register */ #define SOC_ETM_CH2_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x28) /** SOC_ETM_CH2_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel2 event ID. + * Configures ch2_evt_id */ #define SOC_ETM_CH2_EVT_ID 0x0000007FU #define SOC_ETM_CH2_EVT_ID_M (SOC_ETM_CH2_EVT_ID_V << SOC_ETM_CH2_EVT_ID_S) @@ -1452,11 +1452,11 @@ extern "C" { #define SOC_ETM_CH2_EVT_ID_S 0 /** SOC_ETM_CH2_TASK_ID_REG register - * Channel2 task ID register + * Channel2 task id register */ #define SOC_ETM_CH2_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x2c) /** SOC_ETM_CH2_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel2 task ID. + * Configures ch2_task_id */ #define SOC_ETM_CH2_TASK_ID 0x000000FFU #define SOC_ETM_CH2_TASK_ID_M (SOC_ETM_CH2_TASK_ID_V << SOC_ETM_CH2_TASK_ID_S) @@ -1464,11 +1464,11 @@ extern "C" { #define SOC_ETM_CH2_TASK_ID_S 0 /** SOC_ETM_CH3_EVT_ID_REG register - * Channel3 event ID register + * Channel3 event id register */ #define SOC_ETM_CH3_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x30) /** SOC_ETM_CH3_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel3 event ID. + * Configures ch3_evt_id */ #define SOC_ETM_CH3_EVT_ID 0x0000007FU #define SOC_ETM_CH3_EVT_ID_M (SOC_ETM_CH3_EVT_ID_V << SOC_ETM_CH3_EVT_ID_S) @@ -1476,11 +1476,11 @@ extern "C" { #define SOC_ETM_CH3_EVT_ID_S 0 /** SOC_ETM_CH3_TASK_ID_REG register - * Channel3 task ID register + * Channel3 task id register */ #define SOC_ETM_CH3_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x34) /** SOC_ETM_CH3_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel3 task ID. + * Configures ch3_task_id */ #define SOC_ETM_CH3_TASK_ID 0x000000FFU #define SOC_ETM_CH3_TASK_ID_M (SOC_ETM_CH3_TASK_ID_V << SOC_ETM_CH3_TASK_ID_S) @@ -1488,11 +1488,11 @@ extern "C" { #define SOC_ETM_CH3_TASK_ID_S 0 /** SOC_ETM_CH4_EVT_ID_REG register - * Channel4 event ID register + * Channel4 event id register */ #define SOC_ETM_CH4_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x38) /** SOC_ETM_CH4_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel4 event ID. + * Configures ch4_evt_id */ #define SOC_ETM_CH4_EVT_ID 0x0000007FU #define SOC_ETM_CH4_EVT_ID_M (SOC_ETM_CH4_EVT_ID_V << SOC_ETM_CH4_EVT_ID_S) @@ -1500,11 +1500,11 @@ extern "C" { #define SOC_ETM_CH4_EVT_ID_S 0 /** SOC_ETM_CH4_TASK_ID_REG register - * Channel4 task ID register + * Channel4 task id register */ #define SOC_ETM_CH4_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x3c) /** SOC_ETM_CH4_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel4 task ID. + * Configures ch4_task_id */ #define SOC_ETM_CH4_TASK_ID 0x000000FFU #define SOC_ETM_CH4_TASK_ID_M (SOC_ETM_CH4_TASK_ID_V << SOC_ETM_CH4_TASK_ID_S) @@ -1512,11 +1512,11 @@ extern "C" { #define SOC_ETM_CH4_TASK_ID_S 0 /** SOC_ETM_CH5_EVT_ID_REG register - * Channel5 event ID register + * Channel5 event id register */ #define SOC_ETM_CH5_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x40) /** SOC_ETM_CH5_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel5 event ID. + * Configures ch5_evt_id */ #define SOC_ETM_CH5_EVT_ID 0x0000007FU #define SOC_ETM_CH5_EVT_ID_M (SOC_ETM_CH5_EVT_ID_V << SOC_ETM_CH5_EVT_ID_S) @@ -1524,11 +1524,11 @@ extern "C" { #define SOC_ETM_CH5_EVT_ID_S 0 /** SOC_ETM_CH5_TASK_ID_REG register - * Channel5 task ID register + * Channel5 task id register */ #define SOC_ETM_CH5_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x44) /** SOC_ETM_CH5_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel5 task ID. + * Configures ch5_task_id */ #define SOC_ETM_CH5_TASK_ID 0x000000FFU #define SOC_ETM_CH5_TASK_ID_M (SOC_ETM_CH5_TASK_ID_V << SOC_ETM_CH5_TASK_ID_S) @@ -1536,11 +1536,11 @@ extern "C" { #define SOC_ETM_CH5_TASK_ID_S 0 /** SOC_ETM_CH6_EVT_ID_REG register - * Channel6 event ID register + * Channel6 event id register */ #define SOC_ETM_CH6_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x48) /** SOC_ETM_CH6_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel6 event ID. + * Configures ch6_evt_id */ #define SOC_ETM_CH6_EVT_ID 0x0000007FU #define SOC_ETM_CH6_EVT_ID_M (SOC_ETM_CH6_EVT_ID_V << SOC_ETM_CH6_EVT_ID_S) @@ -1548,11 +1548,11 @@ extern "C" { #define SOC_ETM_CH6_EVT_ID_S 0 /** SOC_ETM_CH6_TASK_ID_REG register - * Channel6 task ID register + * Channel6 task id register */ #define SOC_ETM_CH6_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x4c) /** SOC_ETM_CH6_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel6 task ID. + * Configures ch6_task_id */ #define SOC_ETM_CH6_TASK_ID 0x000000FFU #define SOC_ETM_CH6_TASK_ID_M (SOC_ETM_CH6_TASK_ID_V << SOC_ETM_CH6_TASK_ID_S) @@ -1560,11 +1560,11 @@ extern "C" { #define SOC_ETM_CH6_TASK_ID_S 0 /** SOC_ETM_CH7_EVT_ID_REG register - * Channel7 event ID register + * Channel7 event id register */ #define SOC_ETM_CH7_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x50) /** SOC_ETM_CH7_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel7 event ID. + * Configures ch7_evt_id */ #define SOC_ETM_CH7_EVT_ID 0x0000007FU #define SOC_ETM_CH7_EVT_ID_M (SOC_ETM_CH7_EVT_ID_V << SOC_ETM_CH7_EVT_ID_S) @@ -1572,11 +1572,11 @@ extern "C" { #define SOC_ETM_CH7_EVT_ID_S 0 /** SOC_ETM_CH7_TASK_ID_REG register - * Channel7 task ID register + * Channel7 task id register */ #define SOC_ETM_CH7_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x54) /** SOC_ETM_CH7_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel7 task ID. + * Configures ch7_task_id */ #define SOC_ETM_CH7_TASK_ID 0x000000FFU #define SOC_ETM_CH7_TASK_ID_M (SOC_ETM_CH7_TASK_ID_V << SOC_ETM_CH7_TASK_ID_S) @@ -1584,11 +1584,11 @@ extern "C" { #define SOC_ETM_CH7_TASK_ID_S 0 /** SOC_ETM_CH8_EVT_ID_REG register - * Channel8 event ID register + * Channel8 event id register */ #define SOC_ETM_CH8_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x58) /** SOC_ETM_CH8_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel8 event ID. + * Configures ch8_evt_id */ #define SOC_ETM_CH8_EVT_ID 0x0000007FU #define SOC_ETM_CH8_EVT_ID_M (SOC_ETM_CH8_EVT_ID_V << SOC_ETM_CH8_EVT_ID_S) @@ -1596,11 +1596,11 @@ extern "C" { #define SOC_ETM_CH8_EVT_ID_S 0 /** SOC_ETM_CH8_TASK_ID_REG register - * Channel8 task ID register + * Channel8 task id register */ #define SOC_ETM_CH8_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x5c) /** SOC_ETM_CH8_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel8 task ID. + * Configures ch8_task_id */ #define SOC_ETM_CH8_TASK_ID 0x000000FFU #define SOC_ETM_CH8_TASK_ID_M (SOC_ETM_CH8_TASK_ID_V << SOC_ETM_CH8_TASK_ID_S) @@ -1608,11 +1608,11 @@ extern "C" { #define SOC_ETM_CH8_TASK_ID_S 0 /** SOC_ETM_CH9_EVT_ID_REG register - * Channel9 event ID register + * Channel9 event id register */ #define SOC_ETM_CH9_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x60) /** SOC_ETM_CH9_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel9 event ID. + * Configures ch9_evt_id */ #define SOC_ETM_CH9_EVT_ID 0x0000007FU #define SOC_ETM_CH9_EVT_ID_M (SOC_ETM_CH9_EVT_ID_V << SOC_ETM_CH9_EVT_ID_S) @@ -1620,11 +1620,11 @@ extern "C" { #define SOC_ETM_CH9_EVT_ID_S 0 /** SOC_ETM_CH9_TASK_ID_REG register - * Channel9 task ID register + * Channel9 task id register */ #define SOC_ETM_CH9_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x64) /** SOC_ETM_CH9_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel9 task ID. + * Configures ch9_task_id */ #define SOC_ETM_CH9_TASK_ID 0x000000FFU #define SOC_ETM_CH9_TASK_ID_M (SOC_ETM_CH9_TASK_ID_V << SOC_ETM_CH9_TASK_ID_S) @@ -1632,11 +1632,11 @@ extern "C" { #define SOC_ETM_CH9_TASK_ID_S 0 /** SOC_ETM_CH10_EVT_ID_REG register - * Channel10 event ID register + * Channel10 event id register */ #define SOC_ETM_CH10_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x68) /** SOC_ETM_CH10_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel10 event ID. + * Configures ch10_evt_id */ #define SOC_ETM_CH10_EVT_ID 0x0000007FU #define SOC_ETM_CH10_EVT_ID_M (SOC_ETM_CH10_EVT_ID_V << SOC_ETM_CH10_EVT_ID_S) @@ -1644,11 +1644,11 @@ extern "C" { #define SOC_ETM_CH10_EVT_ID_S 0 /** SOC_ETM_CH10_TASK_ID_REG register - * Channel10 task ID register + * Channel10 task id register */ #define SOC_ETM_CH10_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x6c) /** SOC_ETM_CH10_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel10 task ID. + * Configures ch10_task_id */ #define SOC_ETM_CH10_TASK_ID 0x000000FFU #define SOC_ETM_CH10_TASK_ID_M (SOC_ETM_CH10_TASK_ID_V << SOC_ETM_CH10_TASK_ID_S) @@ -1656,11 +1656,11 @@ extern "C" { #define SOC_ETM_CH10_TASK_ID_S 0 /** SOC_ETM_CH11_EVT_ID_REG register - * Channel11 event ID register + * Channel11 event id register */ #define SOC_ETM_CH11_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x70) /** SOC_ETM_CH11_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel11 event ID. + * Configures ch11_evt_id */ #define SOC_ETM_CH11_EVT_ID 0x0000007FU #define SOC_ETM_CH11_EVT_ID_M (SOC_ETM_CH11_EVT_ID_V << SOC_ETM_CH11_EVT_ID_S) @@ -1668,11 +1668,11 @@ extern "C" { #define SOC_ETM_CH11_EVT_ID_S 0 /** SOC_ETM_CH11_TASK_ID_REG register - * Channel11 task ID register + * Channel11 task id register */ #define SOC_ETM_CH11_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x74) /** SOC_ETM_CH11_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel11 task ID. + * Configures ch11_task_id */ #define SOC_ETM_CH11_TASK_ID 0x000000FFU #define SOC_ETM_CH11_TASK_ID_M (SOC_ETM_CH11_TASK_ID_V << SOC_ETM_CH11_TASK_ID_S) @@ -1680,11 +1680,11 @@ extern "C" { #define SOC_ETM_CH11_TASK_ID_S 0 /** SOC_ETM_CH12_EVT_ID_REG register - * Channel12 event ID register + * Channel12 event id register */ #define SOC_ETM_CH12_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x78) /** SOC_ETM_CH12_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel12 event ID. + * Configures ch12_evt_id */ #define SOC_ETM_CH12_EVT_ID 0x0000007FU #define SOC_ETM_CH12_EVT_ID_M (SOC_ETM_CH12_EVT_ID_V << SOC_ETM_CH12_EVT_ID_S) @@ -1692,11 +1692,11 @@ extern "C" { #define SOC_ETM_CH12_EVT_ID_S 0 /** SOC_ETM_CH12_TASK_ID_REG register - * Channel12 task ID register + * Channel12 task id register */ #define SOC_ETM_CH12_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x7c) /** SOC_ETM_CH12_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel12 task ID. + * Configures ch12_task_id */ #define SOC_ETM_CH12_TASK_ID 0x000000FFU #define SOC_ETM_CH12_TASK_ID_M (SOC_ETM_CH12_TASK_ID_V << SOC_ETM_CH12_TASK_ID_S) @@ -1704,11 +1704,11 @@ extern "C" { #define SOC_ETM_CH12_TASK_ID_S 0 /** SOC_ETM_CH13_EVT_ID_REG register - * Channel13 event ID register + * Channel13 event id register */ #define SOC_ETM_CH13_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x80) /** SOC_ETM_CH13_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel13 event ID. + * Configures ch13_evt_id */ #define SOC_ETM_CH13_EVT_ID 0x0000007FU #define SOC_ETM_CH13_EVT_ID_M (SOC_ETM_CH13_EVT_ID_V << SOC_ETM_CH13_EVT_ID_S) @@ -1716,11 +1716,11 @@ extern "C" { #define SOC_ETM_CH13_EVT_ID_S 0 /** SOC_ETM_CH13_TASK_ID_REG register - * Channel13 task ID register + * Channel13 task id register */ #define SOC_ETM_CH13_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x84) /** SOC_ETM_CH13_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel13 task ID. + * Configures ch13_task_id */ #define SOC_ETM_CH13_TASK_ID 0x000000FFU #define SOC_ETM_CH13_TASK_ID_M (SOC_ETM_CH13_TASK_ID_V << SOC_ETM_CH13_TASK_ID_S) @@ -1728,11 +1728,11 @@ extern "C" { #define SOC_ETM_CH13_TASK_ID_S 0 /** SOC_ETM_CH14_EVT_ID_REG register - * Channel14 event ID register + * Channel14 event id register */ #define SOC_ETM_CH14_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x88) /** SOC_ETM_CH14_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel14 event ID. + * Configures ch14_evt_id */ #define SOC_ETM_CH14_EVT_ID 0x0000007FU #define SOC_ETM_CH14_EVT_ID_M (SOC_ETM_CH14_EVT_ID_V << SOC_ETM_CH14_EVT_ID_S) @@ -1740,11 +1740,11 @@ extern "C" { #define SOC_ETM_CH14_EVT_ID_S 0 /** SOC_ETM_CH14_TASK_ID_REG register - * Channel14 task ID register + * Channel14 task id register */ #define SOC_ETM_CH14_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x8c) /** SOC_ETM_CH14_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel14 task ID. + * Configures ch14_task_id */ #define SOC_ETM_CH14_TASK_ID 0x000000FFU #define SOC_ETM_CH14_TASK_ID_M (SOC_ETM_CH14_TASK_ID_V << SOC_ETM_CH14_TASK_ID_S) @@ -1752,11 +1752,11 @@ extern "C" { #define SOC_ETM_CH14_TASK_ID_S 0 /** SOC_ETM_CH15_EVT_ID_REG register - * Channel15 event ID register + * Channel15 event id register */ #define SOC_ETM_CH15_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x90) /** SOC_ETM_CH15_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel15 event ID. + * Configures ch15_evt_id */ #define SOC_ETM_CH15_EVT_ID 0x0000007FU #define SOC_ETM_CH15_EVT_ID_M (SOC_ETM_CH15_EVT_ID_V << SOC_ETM_CH15_EVT_ID_S) @@ -1764,11 +1764,11 @@ extern "C" { #define SOC_ETM_CH15_EVT_ID_S 0 /** SOC_ETM_CH15_TASK_ID_REG register - * Channel15 task ID register + * Channel15 task id register */ #define SOC_ETM_CH15_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x94) /** SOC_ETM_CH15_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel15 task ID. + * Configures ch15_task_id */ #define SOC_ETM_CH15_TASK_ID 0x000000FFU #define SOC_ETM_CH15_TASK_ID_M (SOC_ETM_CH15_TASK_ID_V << SOC_ETM_CH15_TASK_ID_S) @@ -1776,11 +1776,11 @@ extern "C" { #define SOC_ETM_CH15_TASK_ID_S 0 /** SOC_ETM_CH16_EVT_ID_REG register - * Channel16 event ID register + * Channel16 event id register */ #define SOC_ETM_CH16_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x98) /** SOC_ETM_CH16_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel16 event ID. + * Configures ch16_evt_id */ #define SOC_ETM_CH16_EVT_ID 0x0000007FU #define SOC_ETM_CH16_EVT_ID_M (SOC_ETM_CH16_EVT_ID_V << SOC_ETM_CH16_EVT_ID_S) @@ -1788,11 +1788,11 @@ extern "C" { #define SOC_ETM_CH16_EVT_ID_S 0 /** SOC_ETM_CH16_TASK_ID_REG register - * Channel16 task ID register + * Channel16 task id register */ #define SOC_ETM_CH16_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x9c) /** SOC_ETM_CH16_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel16 task ID. + * Configures ch16_task_id */ #define SOC_ETM_CH16_TASK_ID 0x000000FFU #define SOC_ETM_CH16_TASK_ID_M (SOC_ETM_CH16_TASK_ID_V << SOC_ETM_CH16_TASK_ID_S) @@ -1800,11 +1800,11 @@ extern "C" { #define SOC_ETM_CH16_TASK_ID_S 0 /** SOC_ETM_CH17_EVT_ID_REG register - * Channel17 event ID register + * Channel17 event id register */ #define SOC_ETM_CH17_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa0) /** SOC_ETM_CH17_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel17 event ID. + * Configures ch17_evt_id */ #define SOC_ETM_CH17_EVT_ID 0x0000007FU #define SOC_ETM_CH17_EVT_ID_M (SOC_ETM_CH17_EVT_ID_V << SOC_ETM_CH17_EVT_ID_S) @@ -1812,11 +1812,11 @@ extern "C" { #define SOC_ETM_CH17_EVT_ID_S 0 /** SOC_ETM_CH17_TASK_ID_REG register - * Channel17 task ID register + * Channel17 task id register */ #define SOC_ETM_CH17_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xa4) /** SOC_ETM_CH17_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel17 task ID. + * Configures ch17_task_id */ #define SOC_ETM_CH17_TASK_ID 0x000000FFU #define SOC_ETM_CH17_TASK_ID_M (SOC_ETM_CH17_TASK_ID_V << SOC_ETM_CH17_TASK_ID_S) @@ -1824,11 +1824,11 @@ extern "C" { #define SOC_ETM_CH17_TASK_ID_S 0 /** SOC_ETM_CH18_EVT_ID_REG register - * Channel18 event ID register + * Channel18 event id register */ #define SOC_ETM_CH18_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa8) /** SOC_ETM_CH18_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel18 event ID. + * Configures ch18_evt_id */ #define SOC_ETM_CH18_EVT_ID 0x0000007FU #define SOC_ETM_CH18_EVT_ID_M (SOC_ETM_CH18_EVT_ID_V << SOC_ETM_CH18_EVT_ID_S) @@ -1836,11 +1836,11 @@ extern "C" { #define SOC_ETM_CH18_EVT_ID_S 0 /** SOC_ETM_CH18_TASK_ID_REG register - * Channel18 task ID register + * Channel18 task id register */ #define SOC_ETM_CH18_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xac) /** SOC_ETM_CH18_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel18 task ID. + * Configures ch18_task_id */ #define SOC_ETM_CH18_TASK_ID 0x000000FFU #define SOC_ETM_CH18_TASK_ID_M (SOC_ETM_CH18_TASK_ID_V << SOC_ETM_CH18_TASK_ID_S) @@ -1848,11 +1848,11 @@ extern "C" { #define SOC_ETM_CH18_TASK_ID_S 0 /** SOC_ETM_CH19_EVT_ID_REG register - * Channel19 event ID register + * Channel19 event id register */ #define SOC_ETM_CH19_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb0) /** SOC_ETM_CH19_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel19 event ID. + * Configures ch19_evt_id */ #define SOC_ETM_CH19_EVT_ID 0x0000007FU #define SOC_ETM_CH19_EVT_ID_M (SOC_ETM_CH19_EVT_ID_V << SOC_ETM_CH19_EVT_ID_S) @@ -1860,11 +1860,11 @@ extern "C" { #define SOC_ETM_CH19_EVT_ID_S 0 /** SOC_ETM_CH19_TASK_ID_REG register - * Channel19 task ID register + * Channel19 task id register */ #define SOC_ETM_CH19_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xb4) /** SOC_ETM_CH19_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel19 task ID. + * Configures ch19_task_id */ #define SOC_ETM_CH19_TASK_ID 0x000000FFU #define SOC_ETM_CH19_TASK_ID_M (SOC_ETM_CH19_TASK_ID_V << SOC_ETM_CH19_TASK_ID_S) @@ -1872,11 +1872,11 @@ extern "C" { #define SOC_ETM_CH19_TASK_ID_S 0 /** SOC_ETM_CH20_EVT_ID_REG register - * Channel20 event ID register + * Channel20 event id register */ #define SOC_ETM_CH20_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb8) /** SOC_ETM_CH20_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel20 event ID. + * Configures ch20_evt_id */ #define SOC_ETM_CH20_EVT_ID 0x0000007FU #define SOC_ETM_CH20_EVT_ID_M (SOC_ETM_CH20_EVT_ID_V << SOC_ETM_CH20_EVT_ID_S) @@ -1884,11 +1884,11 @@ extern "C" { #define SOC_ETM_CH20_EVT_ID_S 0 /** SOC_ETM_CH20_TASK_ID_REG register - * Channel20 task ID register + * Channel20 task id register */ #define SOC_ETM_CH20_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xbc) /** SOC_ETM_CH20_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel20 task ID. + * Configures ch20_task_id */ #define SOC_ETM_CH20_TASK_ID 0x000000FFU #define SOC_ETM_CH20_TASK_ID_M (SOC_ETM_CH20_TASK_ID_V << SOC_ETM_CH20_TASK_ID_S) @@ -1896,11 +1896,11 @@ extern "C" { #define SOC_ETM_CH20_TASK_ID_S 0 /** SOC_ETM_CH21_EVT_ID_REG register - * Channel21 event ID register + * Channel21 event id register */ #define SOC_ETM_CH21_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc0) /** SOC_ETM_CH21_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel21 event ID. + * Configures ch21_evt_id */ #define SOC_ETM_CH21_EVT_ID 0x0000007FU #define SOC_ETM_CH21_EVT_ID_M (SOC_ETM_CH21_EVT_ID_V << SOC_ETM_CH21_EVT_ID_S) @@ -1908,11 +1908,11 @@ extern "C" { #define SOC_ETM_CH21_EVT_ID_S 0 /** SOC_ETM_CH21_TASK_ID_REG register - * Channel21 task ID register + * Channel21 task id register */ #define SOC_ETM_CH21_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xc4) /** SOC_ETM_CH21_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel21 task ID. + * Configures ch21_task_id */ #define SOC_ETM_CH21_TASK_ID 0x000000FFU #define SOC_ETM_CH21_TASK_ID_M (SOC_ETM_CH21_TASK_ID_V << SOC_ETM_CH21_TASK_ID_S) @@ -1920,11 +1920,11 @@ extern "C" { #define SOC_ETM_CH21_TASK_ID_S 0 /** SOC_ETM_CH22_EVT_ID_REG register - * Channel22 event ID register + * Channel22 event id register */ #define SOC_ETM_CH22_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc8) /** SOC_ETM_CH22_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel22 event ID. + * Configures ch22_evt_id */ #define SOC_ETM_CH22_EVT_ID 0x0000007FU #define SOC_ETM_CH22_EVT_ID_M (SOC_ETM_CH22_EVT_ID_V << SOC_ETM_CH22_EVT_ID_S) @@ -1932,11 +1932,11 @@ extern "C" { #define SOC_ETM_CH22_EVT_ID_S 0 /** SOC_ETM_CH22_TASK_ID_REG register - * Channel22 task ID register + * Channel22 task id register */ #define SOC_ETM_CH22_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xcc) /** SOC_ETM_CH22_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel22 task ID. + * Configures ch22_task_id */ #define SOC_ETM_CH22_TASK_ID 0x000000FFU #define SOC_ETM_CH22_TASK_ID_M (SOC_ETM_CH22_TASK_ID_V << SOC_ETM_CH22_TASK_ID_S) @@ -1944,11 +1944,11 @@ extern "C" { #define SOC_ETM_CH22_TASK_ID_S 0 /** SOC_ETM_CH23_EVT_ID_REG register - * Channel23 event ID register + * Channel23 event id register */ #define SOC_ETM_CH23_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd0) /** SOC_ETM_CH23_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel23 event ID. + * Configures ch23_evt_id */ #define SOC_ETM_CH23_EVT_ID 0x0000007FU #define SOC_ETM_CH23_EVT_ID_M (SOC_ETM_CH23_EVT_ID_V << SOC_ETM_CH23_EVT_ID_S) @@ -1956,11 +1956,11 @@ extern "C" { #define SOC_ETM_CH23_EVT_ID_S 0 /** SOC_ETM_CH23_TASK_ID_REG register - * Channel23 task ID register + * Channel23 task id register */ #define SOC_ETM_CH23_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xd4) /** SOC_ETM_CH23_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel23 task ID. + * Configures ch23_task_id */ #define SOC_ETM_CH23_TASK_ID 0x000000FFU #define SOC_ETM_CH23_TASK_ID_M (SOC_ETM_CH23_TASK_ID_V << SOC_ETM_CH23_TASK_ID_S) @@ -1968,11 +1968,11 @@ extern "C" { #define SOC_ETM_CH23_TASK_ID_S 0 /** SOC_ETM_CH24_EVT_ID_REG register - * Channel24 event ID register + * Channel24 event id register */ #define SOC_ETM_CH24_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd8) /** SOC_ETM_CH24_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel24 event ID. + * Configures ch24_evt_id */ #define SOC_ETM_CH24_EVT_ID 0x0000007FU #define SOC_ETM_CH24_EVT_ID_M (SOC_ETM_CH24_EVT_ID_V << SOC_ETM_CH24_EVT_ID_S) @@ -1980,11 +1980,11 @@ extern "C" { #define SOC_ETM_CH24_EVT_ID_S 0 /** SOC_ETM_CH24_TASK_ID_REG register - * Channel24 task ID register + * Channel24 task id register */ #define SOC_ETM_CH24_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xdc) /** SOC_ETM_CH24_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel24 task ID. + * Configures ch24_task_id */ #define SOC_ETM_CH24_TASK_ID 0x000000FFU #define SOC_ETM_CH24_TASK_ID_M (SOC_ETM_CH24_TASK_ID_V << SOC_ETM_CH24_TASK_ID_S) @@ -1992,11 +1992,11 @@ extern "C" { #define SOC_ETM_CH24_TASK_ID_S 0 /** SOC_ETM_CH25_EVT_ID_REG register - * Channel25 event ID register + * Channel25 event id register */ #define SOC_ETM_CH25_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe0) /** SOC_ETM_CH25_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel25 event ID. + * Configures ch25_evt_id */ #define SOC_ETM_CH25_EVT_ID 0x0000007FU #define SOC_ETM_CH25_EVT_ID_M (SOC_ETM_CH25_EVT_ID_V << SOC_ETM_CH25_EVT_ID_S) @@ -2004,11 +2004,11 @@ extern "C" { #define SOC_ETM_CH25_EVT_ID_S 0 /** SOC_ETM_CH25_TASK_ID_REG register - * Channel25 task ID register + * Channel25 task id register */ #define SOC_ETM_CH25_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xe4) /** SOC_ETM_CH25_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel25 task ID. + * Configures ch25_task_id */ #define SOC_ETM_CH25_TASK_ID 0x000000FFU #define SOC_ETM_CH25_TASK_ID_M (SOC_ETM_CH25_TASK_ID_V << SOC_ETM_CH25_TASK_ID_S) @@ -2016,11 +2016,11 @@ extern "C" { #define SOC_ETM_CH25_TASK_ID_S 0 /** SOC_ETM_CH26_EVT_ID_REG register - * Channel26 event ID register + * Channel26 event id register */ #define SOC_ETM_CH26_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe8) /** SOC_ETM_CH26_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel26 event ID. + * Configures ch26_evt_id */ #define SOC_ETM_CH26_EVT_ID 0x0000007FU #define SOC_ETM_CH26_EVT_ID_M (SOC_ETM_CH26_EVT_ID_V << SOC_ETM_CH26_EVT_ID_S) @@ -2028,11 +2028,11 @@ extern "C" { #define SOC_ETM_CH26_EVT_ID_S 0 /** SOC_ETM_CH26_TASK_ID_REG register - * Channel26 task ID register + * Channel26 task id register */ #define SOC_ETM_CH26_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xec) /** SOC_ETM_CH26_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel26 task ID. + * Configures ch26_task_id */ #define SOC_ETM_CH26_TASK_ID 0x000000FFU #define SOC_ETM_CH26_TASK_ID_M (SOC_ETM_CH26_TASK_ID_V << SOC_ETM_CH26_TASK_ID_S) @@ -2040,11 +2040,11 @@ extern "C" { #define SOC_ETM_CH26_TASK_ID_S 0 /** SOC_ETM_CH27_EVT_ID_REG register - * Channel27 event ID register + * Channel27 event id register */ #define SOC_ETM_CH27_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf0) /** SOC_ETM_CH27_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel27 event ID. + * Configures ch27_evt_id */ #define SOC_ETM_CH27_EVT_ID 0x0000007FU #define SOC_ETM_CH27_EVT_ID_M (SOC_ETM_CH27_EVT_ID_V << SOC_ETM_CH27_EVT_ID_S) @@ -2052,11 +2052,11 @@ extern "C" { #define SOC_ETM_CH27_EVT_ID_S 0 /** SOC_ETM_CH27_TASK_ID_REG register - * Channel27 task ID register + * Channel27 task id register */ #define SOC_ETM_CH27_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xf4) /** SOC_ETM_CH27_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel27 task ID. + * Configures ch27_task_id */ #define SOC_ETM_CH27_TASK_ID 0x000000FFU #define SOC_ETM_CH27_TASK_ID_M (SOC_ETM_CH27_TASK_ID_V << SOC_ETM_CH27_TASK_ID_S) @@ -2064,11 +2064,11 @@ extern "C" { #define SOC_ETM_CH27_TASK_ID_S 0 /** SOC_ETM_CH28_EVT_ID_REG register - * Channel28 event ID register + * Channel28 event id register */ #define SOC_ETM_CH28_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf8) /** SOC_ETM_CH28_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel28 event ID. + * Configures ch28_evt_id */ #define SOC_ETM_CH28_EVT_ID 0x0000007FU #define SOC_ETM_CH28_EVT_ID_M (SOC_ETM_CH28_EVT_ID_V << SOC_ETM_CH28_EVT_ID_S) @@ -2076,11 +2076,11 @@ extern "C" { #define SOC_ETM_CH28_EVT_ID_S 0 /** SOC_ETM_CH28_TASK_ID_REG register - * Channel28 task ID register + * Channel28 task id register */ #define SOC_ETM_CH28_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xfc) /** SOC_ETM_CH28_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel28 task ID. + * Configures ch28_task_id */ #define SOC_ETM_CH28_TASK_ID 0x000000FFU #define SOC_ETM_CH28_TASK_ID_M (SOC_ETM_CH28_TASK_ID_V << SOC_ETM_CH28_TASK_ID_S) @@ -2088,11 +2088,11 @@ extern "C" { #define SOC_ETM_CH28_TASK_ID_S 0 /** SOC_ETM_CH29_EVT_ID_REG register - * Channel29 event ID register + * Channel29 event id register */ #define SOC_ETM_CH29_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x100) /** SOC_ETM_CH29_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel29 event ID. + * Configures ch29_evt_id */ #define SOC_ETM_CH29_EVT_ID 0x0000007FU #define SOC_ETM_CH29_EVT_ID_M (SOC_ETM_CH29_EVT_ID_V << SOC_ETM_CH29_EVT_ID_S) @@ -2100,11 +2100,11 @@ extern "C" { #define SOC_ETM_CH29_EVT_ID_S 0 /** SOC_ETM_CH29_TASK_ID_REG register - * Channel29 task ID register + * Channel29 task id register */ #define SOC_ETM_CH29_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x104) /** SOC_ETM_CH29_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel29 task ID. + * Configures ch29_task_id */ #define SOC_ETM_CH29_TASK_ID 0x000000FFU #define SOC_ETM_CH29_TASK_ID_M (SOC_ETM_CH29_TASK_ID_V << SOC_ETM_CH29_TASK_ID_S) @@ -2112,11 +2112,11 @@ extern "C" { #define SOC_ETM_CH29_TASK_ID_S 0 /** SOC_ETM_CH30_EVT_ID_REG register - * Channel30 event ID register + * Channel30 event id register */ #define SOC_ETM_CH30_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x108) /** SOC_ETM_CH30_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel30 event ID. + * Configures ch30_evt_id */ #define SOC_ETM_CH30_EVT_ID 0x0000007FU #define SOC_ETM_CH30_EVT_ID_M (SOC_ETM_CH30_EVT_ID_V << SOC_ETM_CH30_EVT_ID_S) @@ -2124,11 +2124,11 @@ extern "C" { #define SOC_ETM_CH30_EVT_ID_S 0 /** SOC_ETM_CH30_TASK_ID_REG register - * Channel30 task ID register + * Channel30 task id register */ #define SOC_ETM_CH30_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x10c) /** SOC_ETM_CH30_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel30 task ID. + * Configures ch30_task_id */ #define SOC_ETM_CH30_TASK_ID 0x000000FFU #define SOC_ETM_CH30_TASK_ID_M (SOC_ETM_CH30_TASK_ID_V << SOC_ETM_CH30_TASK_ID_S) @@ -2136,11 +2136,11 @@ extern "C" { #define SOC_ETM_CH30_TASK_ID_S 0 /** SOC_ETM_CH31_EVT_ID_REG register - * Channel31 event ID register + * Channel31 event id register */ #define SOC_ETM_CH31_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x110) /** SOC_ETM_CH31_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel31 event ID. + * Configures ch31_evt_id */ #define SOC_ETM_CH31_EVT_ID 0x0000007FU #define SOC_ETM_CH31_EVT_ID_M (SOC_ETM_CH31_EVT_ID_V << SOC_ETM_CH31_EVT_ID_S) @@ -2148,11 +2148,11 @@ extern "C" { #define SOC_ETM_CH31_EVT_ID_S 0 /** SOC_ETM_CH31_TASK_ID_REG register - * Channel31 task ID register + * Channel31 task id register */ #define SOC_ETM_CH31_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x114) /** SOC_ETM_CH31_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel31 task ID. + * Configures ch31_task_id */ #define SOC_ETM_CH31_TASK_ID 0x000000FFU #define SOC_ETM_CH31_TASK_ID_M (SOC_ETM_CH31_TASK_ID_V << SOC_ETM_CH31_TASK_ID_S) @@ -2160,11 +2160,11 @@ extern "C" { #define SOC_ETM_CH31_TASK_ID_S 0 /** SOC_ETM_CH32_EVT_ID_REG register - * Channel32 event ID register + * Channel32 event id register */ #define SOC_ETM_CH32_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x118) /** SOC_ETM_CH32_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel32 event ID. + * Configures ch32_evt_id */ #define SOC_ETM_CH32_EVT_ID 0x0000007FU #define SOC_ETM_CH32_EVT_ID_M (SOC_ETM_CH32_EVT_ID_V << SOC_ETM_CH32_EVT_ID_S) @@ -2172,11 +2172,11 @@ extern "C" { #define SOC_ETM_CH32_EVT_ID_S 0 /** SOC_ETM_CH32_TASK_ID_REG register - * Channel32 task ID register + * Channel32 task id register */ #define SOC_ETM_CH32_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x11c) /** SOC_ETM_CH32_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel32 task ID. + * Configures ch32_task_id */ #define SOC_ETM_CH32_TASK_ID 0x000000FFU #define SOC_ETM_CH32_TASK_ID_M (SOC_ETM_CH32_TASK_ID_V << SOC_ETM_CH32_TASK_ID_S) @@ -2184,11 +2184,11 @@ extern "C" { #define SOC_ETM_CH32_TASK_ID_S 0 /** SOC_ETM_CH33_EVT_ID_REG register - * Channel33 event ID register + * Channel33 event id register */ #define SOC_ETM_CH33_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x120) /** SOC_ETM_CH33_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel33 event ID. + * Configures ch33_evt_id */ #define SOC_ETM_CH33_EVT_ID 0x0000007FU #define SOC_ETM_CH33_EVT_ID_M (SOC_ETM_CH33_EVT_ID_V << SOC_ETM_CH33_EVT_ID_S) @@ -2196,11 +2196,11 @@ extern "C" { #define SOC_ETM_CH33_EVT_ID_S 0 /** SOC_ETM_CH33_TASK_ID_REG register - * Channel33 task ID register + * Channel33 task id register */ #define SOC_ETM_CH33_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x124) /** SOC_ETM_CH33_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel33 task ID. + * Configures ch33_task_id */ #define SOC_ETM_CH33_TASK_ID 0x000000FFU #define SOC_ETM_CH33_TASK_ID_M (SOC_ETM_CH33_TASK_ID_V << SOC_ETM_CH33_TASK_ID_S) @@ -2208,11 +2208,11 @@ extern "C" { #define SOC_ETM_CH33_TASK_ID_S 0 /** SOC_ETM_CH34_EVT_ID_REG register - * Channel34 event ID register + * Channel34 event id register */ #define SOC_ETM_CH34_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x128) /** SOC_ETM_CH34_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel34 event ID. + * Configures ch34_evt_id */ #define SOC_ETM_CH34_EVT_ID 0x0000007FU #define SOC_ETM_CH34_EVT_ID_M (SOC_ETM_CH34_EVT_ID_V << SOC_ETM_CH34_EVT_ID_S) @@ -2220,11 +2220,11 @@ extern "C" { #define SOC_ETM_CH34_EVT_ID_S 0 /** SOC_ETM_CH34_TASK_ID_REG register - * Channel34 task ID register + * Channel34 task id register */ #define SOC_ETM_CH34_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x12c) /** SOC_ETM_CH34_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel34 task ID. + * Configures ch34_task_id */ #define SOC_ETM_CH34_TASK_ID 0x000000FFU #define SOC_ETM_CH34_TASK_ID_M (SOC_ETM_CH34_TASK_ID_V << SOC_ETM_CH34_TASK_ID_S) @@ -2232,11 +2232,11 @@ extern "C" { #define SOC_ETM_CH34_TASK_ID_S 0 /** SOC_ETM_CH35_EVT_ID_REG register - * Channel35 event ID register + * Channel35 event id register */ #define SOC_ETM_CH35_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x130) /** SOC_ETM_CH35_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel35 event ID. + * Configures ch35_evt_id */ #define SOC_ETM_CH35_EVT_ID 0x0000007FU #define SOC_ETM_CH35_EVT_ID_M (SOC_ETM_CH35_EVT_ID_V << SOC_ETM_CH35_EVT_ID_S) @@ -2244,11 +2244,11 @@ extern "C" { #define SOC_ETM_CH35_EVT_ID_S 0 /** SOC_ETM_CH35_TASK_ID_REG register - * Channel35 task ID register + * Channel35 task id register */ #define SOC_ETM_CH35_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x134) /** SOC_ETM_CH35_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel35 task ID. + * Configures ch35_task_id */ #define SOC_ETM_CH35_TASK_ID 0x000000FFU #define SOC_ETM_CH35_TASK_ID_M (SOC_ETM_CH35_TASK_ID_V << SOC_ETM_CH35_TASK_ID_S) @@ -2256,11 +2256,11 @@ extern "C" { #define SOC_ETM_CH35_TASK_ID_S 0 /** SOC_ETM_CH36_EVT_ID_REG register - * Channel36 event ID register + * Channel36 event id register */ #define SOC_ETM_CH36_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x138) /** SOC_ETM_CH36_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel36 event ID. + * Configures ch36_evt_id */ #define SOC_ETM_CH36_EVT_ID 0x0000007FU #define SOC_ETM_CH36_EVT_ID_M (SOC_ETM_CH36_EVT_ID_V << SOC_ETM_CH36_EVT_ID_S) @@ -2268,11 +2268,11 @@ extern "C" { #define SOC_ETM_CH36_EVT_ID_S 0 /** SOC_ETM_CH36_TASK_ID_REG register - * Channel36 task ID register + * Channel36 task id register */ #define SOC_ETM_CH36_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x13c) /** SOC_ETM_CH36_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel36 task ID. + * Configures ch36_task_id */ #define SOC_ETM_CH36_TASK_ID 0x000000FFU #define SOC_ETM_CH36_TASK_ID_M (SOC_ETM_CH36_TASK_ID_V << SOC_ETM_CH36_TASK_ID_S) @@ -2280,11 +2280,11 @@ extern "C" { #define SOC_ETM_CH36_TASK_ID_S 0 /** SOC_ETM_CH37_EVT_ID_REG register - * Channel37 event ID register + * Channel37 event id register */ #define SOC_ETM_CH37_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x140) /** SOC_ETM_CH37_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel37 event ID. + * Configures ch37_evt_id */ #define SOC_ETM_CH37_EVT_ID 0x0000007FU #define SOC_ETM_CH37_EVT_ID_M (SOC_ETM_CH37_EVT_ID_V << SOC_ETM_CH37_EVT_ID_S) @@ -2292,11 +2292,11 @@ extern "C" { #define SOC_ETM_CH37_EVT_ID_S 0 /** SOC_ETM_CH37_TASK_ID_REG register - * Channel37 task ID register + * Channel37 task id register */ #define SOC_ETM_CH37_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x144) /** SOC_ETM_CH37_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel37 task ID. + * Configures ch37_task_id */ #define SOC_ETM_CH37_TASK_ID 0x000000FFU #define SOC_ETM_CH37_TASK_ID_M (SOC_ETM_CH37_TASK_ID_V << SOC_ETM_CH37_TASK_ID_S) @@ -2304,11 +2304,11 @@ extern "C" { #define SOC_ETM_CH37_TASK_ID_S 0 /** SOC_ETM_CH38_EVT_ID_REG register - * Channel38 event ID register + * Channel38 event id register */ #define SOC_ETM_CH38_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x148) /** SOC_ETM_CH38_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel38 event ID. + * Configures ch38_evt_id */ #define SOC_ETM_CH38_EVT_ID 0x0000007FU #define SOC_ETM_CH38_EVT_ID_M (SOC_ETM_CH38_EVT_ID_V << SOC_ETM_CH38_EVT_ID_S) @@ -2316,11 +2316,11 @@ extern "C" { #define SOC_ETM_CH38_EVT_ID_S 0 /** SOC_ETM_CH38_TASK_ID_REG register - * Channel38 task ID register + * Channel38 task id register */ #define SOC_ETM_CH38_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x14c) /** SOC_ETM_CH38_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel38 task ID. + * Configures ch38_task_id */ #define SOC_ETM_CH38_TASK_ID 0x000000FFU #define SOC_ETM_CH38_TASK_ID_M (SOC_ETM_CH38_TASK_ID_V << SOC_ETM_CH38_TASK_ID_S) @@ -2328,11 +2328,11 @@ extern "C" { #define SOC_ETM_CH38_TASK_ID_S 0 /** SOC_ETM_CH39_EVT_ID_REG register - * Channel39 event ID register + * Channel39 event id register */ #define SOC_ETM_CH39_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x150) /** SOC_ETM_CH39_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel39 event ID. + * Configures ch39_evt_id */ #define SOC_ETM_CH39_EVT_ID 0x0000007FU #define SOC_ETM_CH39_EVT_ID_M (SOC_ETM_CH39_EVT_ID_V << SOC_ETM_CH39_EVT_ID_S) @@ -2340,11 +2340,11 @@ extern "C" { #define SOC_ETM_CH39_EVT_ID_S 0 /** SOC_ETM_CH39_TASK_ID_REG register - * Channel39 task ID register + * Channel39 task id register */ #define SOC_ETM_CH39_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x154) /** SOC_ETM_CH39_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel39 task ID. + * Configures ch39_task_id */ #define SOC_ETM_CH39_TASK_ID 0x000000FFU #define SOC_ETM_CH39_TASK_ID_M (SOC_ETM_CH39_TASK_ID_V << SOC_ETM_CH39_TASK_ID_S) @@ -2352,11 +2352,11 @@ extern "C" { #define SOC_ETM_CH39_TASK_ID_S 0 /** SOC_ETM_CH40_EVT_ID_REG register - * Channel40 event ID register + * Channel40 event id register */ #define SOC_ETM_CH40_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x158) /** SOC_ETM_CH40_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel40 event ID. + * Configures ch40_evt_id */ #define SOC_ETM_CH40_EVT_ID 0x0000007FU #define SOC_ETM_CH40_EVT_ID_M (SOC_ETM_CH40_EVT_ID_V << SOC_ETM_CH40_EVT_ID_S) @@ -2364,11 +2364,11 @@ extern "C" { #define SOC_ETM_CH40_EVT_ID_S 0 /** SOC_ETM_CH40_TASK_ID_REG register - * Channel40 task ID register + * Channel40 task id register */ #define SOC_ETM_CH40_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x15c) /** SOC_ETM_CH40_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel40 task ID. + * Configures ch40_task_id */ #define SOC_ETM_CH40_TASK_ID 0x000000FFU #define SOC_ETM_CH40_TASK_ID_M (SOC_ETM_CH40_TASK_ID_V << SOC_ETM_CH40_TASK_ID_S) @@ -2376,11 +2376,11 @@ extern "C" { #define SOC_ETM_CH40_TASK_ID_S 0 /** SOC_ETM_CH41_EVT_ID_REG register - * Channel41 event ID register + * Channel41 event id register */ #define SOC_ETM_CH41_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x160) /** SOC_ETM_CH41_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel41 event ID. + * Configures ch41_evt_id */ #define SOC_ETM_CH41_EVT_ID 0x0000007FU #define SOC_ETM_CH41_EVT_ID_M (SOC_ETM_CH41_EVT_ID_V << SOC_ETM_CH41_EVT_ID_S) @@ -2388,11 +2388,11 @@ extern "C" { #define SOC_ETM_CH41_EVT_ID_S 0 /** SOC_ETM_CH41_TASK_ID_REG register - * Channel41 task ID register + * Channel41 task id register */ #define SOC_ETM_CH41_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x164) /** SOC_ETM_CH41_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel41 task ID. + * Configures ch41_task_id */ #define SOC_ETM_CH41_TASK_ID 0x000000FFU #define SOC_ETM_CH41_TASK_ID_M (SOC_ETM_CH41_TASK_ID_V << SOC_ETM_CH41_TASK_ID_S) @@ -2400,11 +2400,11 @@ extern "C" { #define SOC_ETM_CH41_TASK_ID_S 0 /** SOC_ETM_CH42_EVT_ID_REG register - * Channel42 event ID register + * Channel42 event id register */ #define SOC_ETM_CH42_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x168) /** SOC_ETM_CH42_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel42 event ID. + * Configures ch42_evt_id */ #define SOC_ETM_CH42_EVT_ID 0x0000007FU #define SOC_ETM_CH42_EVT_ID_M (SOC_ETM_CH42_EVT_ID_V << SOC_ETM_CH42_EVT_ID_S) @@ -2412,11 +2412,11 @@ extern "C" { #define SOC_ETM_CH42_EVT_ID_S 0 /** SOC_ETM_CH42_TASK_ID_REG register - * Channel42 task ID register + * Channel42 task id register */ #define SOC_ETM_CH42_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x16c) /** SOC_ETM_CH42_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel42 task ID. + * Configures ch42_task_id */ #define SOC_ETM_CH42_TASK_ID 0x000000FFU #define SOC_ETM_CH42_TASK_ID_M (SOC_ETM_CH42_TASK_ID_V << SOC_ETM_CH42_TASK_ID_S) @@ -2424,11 +2424,11 @@ extern "C" { #define SOC_ETM_CH42_TASK_ID_S 0 /** SOC_ETM_CH43_EVT_ID_REG register - * Channel43 event ID register + * Channel43 event id register */ #define SOC_ETM_CH43_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x170) /** SOC_ETM_CH43_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel43 event ID. + * Configures ch43_evt_id */ #define SOC_ETM_CH43_EVT_ID 0x0000007FU #define SOC_ETM_CH43_EVT_ID_M (SOC_ETM_CH43_EVT_ID_V << SOC_ETM_CH43_EVT_ID_S) @@ -2436,11 +2436,11 @@ extern "C" { #define SOC_ETM_CH43_EVT_ID_S 0 /** SOC_ETM_CH43_TASK_ID_REG register - * Channel43 task ID register + * Channel43 task id register */ #define SOC_ETM_CH43_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x174) /** SOC_ETM_CH43_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel43 task ID. + * Configures ch43_task_id */ #define SOC_ETM_CH43_TASK_ID 0x000000FFU #define SOC_ETM_CH43_TASK_ID_M (SOC_ETM_CH43_TASK_ID_V << SOC_ETM_CH43_TASK_ID_S) @@ -2448,11 +2448,11 @@ extern "C" { #define SOC_ETM_CH43_TASK_ID_S 0 /** SOC_ETM_CH44_EVT_ID_REG register - * Channel44 event ID register + * Channel44 event id register */ #define SOC_ETM_CH44_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x178) /** SOC_ETM_CH44_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel44 event ID. + * Configures ch44_evt_id */ #define SOC_ETM_CH44_EVT_ID 0x0000007FU #define SOC_ETM_CH44_EVT_ID_M (SOC_ETM_CH44_EVT_ID_V << SOC_ETM_CH44_EVT_ID_S) @@ -2460,11 +2460,11 @@ extern "C" { #define SOC_ETM_CH44_EVT_ID_S 0 /** SOC_ETM_CH44_TASK_ID_REG register - * Channel44 task ID register + * Channel44 task id register */ #define SOC_ETM_CH44_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x17c) /** SOC_ETM_CH44_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel44 task ID. + * Configures ch44_task_id */ #define SOC_ETM_CH44_TASK_ID 0x000000FFU #define SOC_ETM_CH44_TASK_ID_M (SOC_ETM_CH44_TASK_ID_V << SOC_ETM_CH44_TASK_ID_S) @@ -2472,11 +2472,11 @@ extern "C" { #define SOC_ETM_CH44_TASK_ID_S 0 /** SOC_ETM_CH45_EVT_ID_REG register - * Channel45 event ID register + * Channel45 event id register */ #define SOC_ETM_CH45_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x180) /** SOC_ETM_CH45_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel45 event ID. + * Configures ch45_evt_id */ #define SOC_ETM_CH45_EVT_ID 0x0000007FU #define SOC_ETM_CH45_EVT_ID_M (SOC_ETM_CH45_EVT_ID_V << SOC_ETM_CH45_EVT_ID_S) @@ -2484,11 +2484,11 @@ extern "C" { #define SOC_ETM_CH45_EVT_ID_S 0 /** SOC_ETM_CH45_TASK_ID_REG register - * Channel45 task ID register + * Channel45 task id register */ #define SOC_ETM_CH45_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x184) /** SOC_ETM_CH45_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel45 task ID. + * Configures ch45_task_id */ #define SOC_ETM_CH45_TASK_ID 0x000000FFU #define SOC_ETM_CH45_TASK_ID_M (SOC_ETM_CH45_TASK_ID_V << SOC_ETM_CH45_TASK_ID_S) @@ -2496,11 +2496,11 @@ extern "C" { #define SOC_ETM_CH45_TASK_ID_S 0 /** SOC_ETM_CH46_EVT_ID_REG register - * Channel46 event ID register + * Channel46 event id register */ #define SOC_ETM_CH46_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x188) /** SOC_ETM_CH46_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel46 event ID. + * Configures ch46_evt_id */ #define SOC_ETM_CH46_EVT_ID 0x0000007FU #define SOC_ETM_CH46_EVT_ID_M (SOC_ETM_CH46_EVT_ID_V << SOC_ETM_CH46_EVT_ID_S) @@ -2508,11 +2508,11 @@ extern "C" { #define SOC_ETM_CH46_EVT_ID_S 0 /** SOC_ETM_CH46_TASK_ID_REG register - * Channel46 task ID register + * Channel46 task id register */ #define SOC_ETM_CH46_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x18c) /** SOC_ETM_CH46_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel46 task ID. + * Configures ch46_task_id */ #define SOC_ETM_CH46_TASK_ID 0x000000FFU #define SOC_ETM_CH46_TASK_ID_M (SOC_ETM_CH46_TASK_ID_V << SOC_ETM_CH46_TASK_ID_S) @@ -2520,11 +2520,11 @@ extern "C" { #define SOC_ETM_CH46_TASK_ID_S 0 /** SOC_ETM_CH47_EVT_ID_REG register - * Channel47 event ID register + * Channel47 event id register */ #define SOC_ETM_CH47_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x190) /** SOC_ETM_CH47_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel47 event ID. + * Configures ch47_evt_id */ #define SOC_ETM_CH47_EVT_ID 0x0000007FU #define SOC_ETM_CH47_EVT_ID_M (SOC_ETM_CH47_EVT_ID_V << SOC_ETM_CH47_EVT_ID_S) @@ -2532,11 +2532,11 @@ extern "C" { #define SOC_ETM_CH47_EVT_ID_S 0 /** SOC_ETM_CH47_TASK_ID_REG register - * Channel47 task ID register + * Channel47 task id register */ #define SOC_ETM_CH47_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x194) /** SOC_ETM_CH47_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel47 task ID. + * Configures ch47_task_id */ #define SOC_ETM_CH47_TASK_ID 0x000000FFU #define SOC_ETM_CH47_TASK_ID_M (SOC_ETM_CH47_TASK_ID_V << SOC_ETM_CH47_TASK_ID_S) @@ -2544,11 +2544,11 @@ extern "C" { #define SOC_ETM_CH47_TASK_ID_S 0 /** SOC_ETM_CH48_EVT_ID_REG register - * Channel48 event ID register + * Channel48 event id register */ #define SOC_ETM_CH48_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x198) /** SOC_ETM_CH48_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel48 event ID. + * Configures ch48_evt_id */ #define SOC_ETM_CH48_EVT_ID 0x0000007FU #define SOC_ETM_CH48_EVT_ID_M (SOC_ETM_CH48_EVT_ID_V << SOC_ETM_CH48_EVT_ID_S) @@ -2556,11 +2556,11 @@ extern "C" { #define SOC_ETM_CH48_EVT_ID_S 0 /** SOC_ETM_CH48_TASK_ID_REG register - * Channel48 task ID register + * Channel48 task id register */ #define SOC_ETM_CH48_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x19c) /** SOC_ETM_CH48_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel48 task ID. + * Configures ch48_task_id */ #define SOC_ETM_CH48_TASK_ID 0x000000FFU #define SOC_ETM_CH48_TASK_ID_M (SOC_ETM_CH48_TASK_ID_V << SOC_ETM_CH48_TASK_ID_S) @@ -2568,11 +2568,11 @@ extern "C" { #define SOC_ETM_CH48_TASK_ID_S 0 /** SOC_ETM_CH49_EVT_ID_REG register - * Channel49 event ID register + * Channel49 event id register */ #define SOC_ETM_CH49_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a0) /** SOC_ETM_CH49_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel49 event ID. + * Configures ch49_evt_id */ #define SOC_ETM_CH49_EVT_ID 0x0000007FU #define SOC_ETM_CH49_EVT_ID_M (SOC_ETM_CH49_EVT_ID_V << SOC_ETM_CH49_EVT_ID_S) @@ -2580,11 +2580,11 @@ extern "C" { #define SOC_ETM_CH49_EVT_ID_S 0 /** SOC_ETM_CH49_TASK_ID_REG register - * Channel49 task ID register + * Channel49 task id register */ #define SOC_ETM_CH49_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a4) /** SOC_ETM_CH49_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel49 task ID. + * Configures ch49_task_id */ #define SOC_ETM_CH49_TASK_ID 0x000000FFU #define SOC_ETM_CH49_TASK_ID_M (SOC_ETM_CH49_TASK_ID_V << SOC_ETM_CH49_TASK_ID_S) @@ -2592,11 +2592,11 @@ extern "C" { #define SOC_ETM_CH49_TASK_ID_S 0 /** SOC_ETM_EVT_ST0_REG register - * Event trigger status register + * Events trigger status register */ #define SOC_ETM_EVT_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1a8) /** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST : R/WTC/SS; bitpos: [0]; default: 0; - * Represents GPIO_EVT_CH0_RISE_EDGE trigger status. + * Represents GPIO_evt_ch0_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2605,7 +2605,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_S 0 /** SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST : R/WTC/SS; bitpos: [1]; default: 0; - * Represents GPIO_EVT_CH1_RISE_EDGE trigger status. + * Represents GPIO_evt_ch1_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2614,7 +2614,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_S 1 /** SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST : R/WTC/SS; bitpos: [2]; default: 0; - * Represents GPIO_EVT_CH2_RISE_EDGE trigger status. + * Represents GPIO_evt_ch2_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2623,7 +2623,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_S 2 /** SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST : R/WTC/SS; bitpos: [3]; default: 0; - * Represents GPIO_EVT_CH3_RISE_EDGE trigger status. + * Represents GPIO_evt_ch3_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2632,7 +2632,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_S 3 /** SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST : R/WTC/SS; bitpos: [4]; default: 0; - * Represents GPIO_EVT_CH4_RISE_EDGE trigger status. + * Represents GPIO_evt_ch4_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2641,7 +2641,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_S 4 /** SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST : R/WTC/SS; bitpos: [5]; default: 0; - * Represents GPIO_EVT_CH5_RISE_EDGE trigger status. + * Represents GPIO_evt_ch5_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2650,7 +2650,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_S 5 /** SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST : R/WTC/SS; bitpos: [6]; default: 0; - * Represents GPIO_EVT_CH6_RISE_EDGE trigger status. + * Represents GPIO_evt_ch6_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2659,7 +2659,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_S 6 /** SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST : R/WTC/SS; bitpos: [7]; default: 0; - * Represents GPIO_EVT_CH7_RISE_EDGE trigger status. + * Represents GPIO_evt_ch7_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2668,7 +2668,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_S 7 /** SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST : R/WTC/SS; bitpos: [8]; default: 0; - * Represents GPIO_EVT_CH0_FALL_EDGE trigger status. + * Represents GPIO_evt_ch0_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2677,7 +2677,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_S 8 /** SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST : R/WTC/SS; bitpos: [9]; default: 0; - * Represents GPIO_EVT_CH1_FALL_EDGE trigger status. + * Represents GPIO_evt_ch1_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2686,7 +2686,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_S 9 /** SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST : R/WTC/SS; bitpos: [10]; default: 0; - * Represents GPIO_EVT_CH2_FALL_EDGE trigger status. + * Represents GPIO_evt_ch2_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2695,7 +2695,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_S 10 /** SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST : R/WTC/SS; bitpos: [11]; default: 0; - * Represents GPIO_EVT_CH3_FALL_EDGE trigger status. + * Represents GPIO_evt_ch3_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2704,7 +2704,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_S 11 /** SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST : R/WTC/SS; bitpos: [12]; default: 0; - * Represents GPIO_EVT_CH4_FALL_EDGE trigger status. + * Represents GPIO_evt_ch4_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2713,7 +2713,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_S 12 /** SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST : R/WTC/SS; bitpos: [13]; default: 0; - * Represents GPIO_EVT_CH5_FALL_EDGE trigger status. + * Represents GPIO_evt_ch5_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2722,7 +2722,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_S 13 /** SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST : R/WTC/SS; bitpos: [14]; default: 0; - * Represents GPIO_EVT_CH6_FALL_EDGE trigger status. + * Represents GPIO_evt_ch6_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2731,7 +2731,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_S 14 /** SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST : R/WTC/SS; bitpos: [15]; default: 0; - * Represents GPIO_EVT_CH7_FALL_EDGE trigger status. + * Represents GPIO_evt_ch7_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2740,7 +2740,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_S 15 /** SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST : R/WTC/SS; bitpos: [16]; default: 0; - * Represents GPIO_EVT_CH0_ANY_EDGE trigger status. + * Represents GPIO_evt_ch0_any_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2749,7 +2749,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_S 16 /** SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST : R/WTC/SS; bitpos: [17]; default: 0; - * Represents GPIO_EVT_CH1_ANY_EDGE trigger status. + * Represents GPIO_evt_ch1_any_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2758,7 +2758,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_S 17 /** SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST : R/WTC/SS; bitpos: [18]; default: 0; - * Represents GPIO_EVT_CH2_ANY_EDGE trigger status. + * Represents GPIO_evt_ch2_any_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2767,7 +2767,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_S 18 /** SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST : R/WTC/SS; bitpos: [19]; default: 0; - * Represents GPIO_EVT_CH3_ANY_EDGE trigger status. + * Represents GPIO_evt_ch3_any_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2776,7 +2776,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_S 19 /** SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST : R/WTC/SS; bitpos: [20]; default: 0; - * Represents GPIO_EVT_CH4_ANY_EDGE trigger status. + * Represents GPIO_evt_ch4_any_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2785,7 +2785,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_S 20 /** SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST : R/WTC/SS; bitpos: [21]; default: 0; - * Represents GPIO_EVT_CH5_ANY_EDGE trigger status. + * Represents GPIO_evt_ch5_any_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2794,7 +2794,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_S 21 /** SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST : R/WTC/SS; bitpos: [22]; default: 0; - * Represents GPIO_EVT_CH6_ANY_EDGE trigger status. + * Represents GPIO_evt_ch6_any_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2803,7 +2803,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_S 22 /** SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST : R/WTC/SS; bitpos: [23]; default: 0; - * Represents GPIO_EVT_CH7_ANY_EDGE trigger status. + * Represents GPIO_evt_ch7_any_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2812,7 +2812,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_S 23 /** SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST : R/WTC/SS; bitpos: [24]; default: 0; - * Represents GPIO_EVT_ZERO_DET_POS0 trigger status. + * Represents GPIO_evt_zero_det_pos0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -2821,7 +2821,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_S 24 /** SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST : R/WTC/SS; bitpos: [25]; default: 0; - * Represents GPIO_EVT_ZERO_DET_NEG0 trigger status. + * Represents GPIO_evt_zero_det_neg0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -2829,8 +2829,26 @@ extern "C" { #define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_S) #define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_S 25 +/** SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents GPIO_evt_zero_det_pos1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST (BIT(26)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_M (SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_S 26 +/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents GPIO_evt_zero_det_neg1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST (BIT(27)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_S 27 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST : R/WTC/SS; bitpos: [28]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH0 trigger status. + * Represents LEDC_evt_duty_chng_end_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -2839,7 +2857,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_S 28 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST : R/WTC/SS; bitpos: [29]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH1 trigger status. + * Represents LEDC_evt_duty_chng_end_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -2848,7 +2866,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_S 29 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST : R/WTC/SS; bitpos: [30]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH2 trigger status. + * Represents LEDC_evt_duty_chng_end_ch2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -2857,7 +2875,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_S 30 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST : R/WTC/SS; bitpos: [31]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH3 trigger status. + * Represents LEDC_evt_duty_chng_end_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -2867,12 +2885,12 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_S 31 /** SOC_ETM_EVT_ST0_CLR_REG register - * Event trigger status clear register + * Events trigger status clear register */ #define SOC_ETM_EVT_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ac) /** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH0_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR (BIT(0)) @@ -2880,8 +2898,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_S 0 /** SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH1_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR (BIT(1)) @@ -2889,8 +2907,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_S 1 /** SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH2_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR (BIT(2)) @@ -2898,8 +2916,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_S 2 /** SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH3_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR (BIT(3)) @@ -2907,8 +2925,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_S 3 /** SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH4_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR (BIT(4)) @@ -2916,8 +2934,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_S 4 /** SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH5_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR (BIT(5)) @@ -2925,8 +2943,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_S 5 /** SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH6_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR (BIT(6)) @@ -2934,8 +2952,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_S 6 /** SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH7_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR (BIT(7)) @@ -2943,8 +2961,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_S 7 /** SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH0_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR (BIT(8)) @@ -2952,8 +2970,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_S 8 /** SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH1_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR (BIT(9)) @@ -2961,8 +2979,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_S 9 /** SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH2_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR (BIT(10)) @@ -2970,8 +2988,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_S 10 /** SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH3_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR (BIT(11)) @@ -2979,8 +2997,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_S 11 /** SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH4_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR (BIT(12)) @@ -2988,8 +3006,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_S 12 /** SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH5_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR (BIT(13)) @@ -2997,8 +3015,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_S 13 /** SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH6_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR (BIT(14)) @@ -3006,8 +3024,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_S 14 /** SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH7_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR (BIT(15)) @@ -3015,8 +3033,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_S 15 /** SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH0_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR (BIT(16)) @@ -3024,8 +3042,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_S 16 /** SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH1_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR (BIT(17)) @@ -3033,8 +3051,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_S 17 /** SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH2_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR (BIT(18)) @@ -3042,8 +3060,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_S 18 /** SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH3_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR (BIT(19)) @@ -3051,8 +3069,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_S 19 /** SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH4_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR (BIT(20)) @@ -3060,8 +3078,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_S 20 /** SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH5_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR (BIT(21)) @@ -3069,8 +3087,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_S 21 /** SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH6_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR (BIT(22)) @@ -3078,8 +3096,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_S 22 /** SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH7_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR (BIT(23)) @@ -3087,8 +3105,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_S 23 /** SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear GPIO_EVT_ZERO_DET_POS0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR (BIT(24)) @@ -3096,17 +3114,35 @@ extern "C" { #define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR_S 24 /** SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear GPIO_EVT_ZERO_DET_NEG0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR (BIT(25)) #define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_S) #define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_S 25 +/** SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR (BIT(26)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_M (SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_S 26 +/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR (BIT(27)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_S 27 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR (BIT(28)) @@ -3114,8 +3150,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_S 28 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR (BIT(29)) @@ -3123,8 +3159,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_S 29 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR (BIT(30)) @@ -3132,8 +3168,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_S 30 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR (BIT(31)) @@ -3142,11 +3178,11 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_S 31 /** SOC_ETM_EVT_ST1_REG register - * Event trigger status register + * Events trigger status register */ #define SOC_ETM_EVT_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1b0) /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST : R/WTC/SS; bitpos: [0]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH4 trigger status. + * Represents LEDC_evt_duty_chng_end_ch4 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3155,7 +3191,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_S 0 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST : R/WTC/SS; bitpos: [1]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH5 trigger status. + * Represents LEDC_evt_duty_chng_end_ch5 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3164,7 +3200,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_S 1 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST : R/WTC/SS; bitpos: [2]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH0 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3173,7 +3209,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_S 2 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST : R/WTC/SS; bitpos: [3]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH1 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3182,7 +3218,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_S 3 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST : R/WTC/SS; bitpos: [4]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH2 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3191,7 +3227,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_S 4 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST : R/WTC/SS; bitpos: [5]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH3 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3200,7 +3236,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_S 5 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST : R/WTC/SS; bitpos: [6]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH4 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3209,7 +3245,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_S 6 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST : R/WTC/SS; bitpos: [7]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH5 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3218,7 +3254,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_S 7 /** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST : R/WTC/SS; bitpos: [8]; default: 0; - * Represents LEDC_EVT_TIME_OVF_TIMER0 trigger status. + * Represents LEDC_evt_time_ovf_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3227,7 +3263,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_S 8 /** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST : R/WTC/SS; bitpos: [9]; default: 0; - * Represents LEDC_EVT_TIME_OVF_TIMER1 trigger status. + * Represents LEDC_evt_time_ovf_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3236,7 +3272,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_S 9 /** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST : R/WTC/SS; bitpos: [10]; default: 0; - * Represents LEDC_EVT_TIME_OVF_TIMER2 trigger status. + * Represents LEDC_evt_time_ovf_timer2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3245,7 +3281,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_S 10 /** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST : R/WTC/SS; bitpos: [11]; default: 0; - * Represents LEDC_EVT_TIME_OVF_TIMER3 trigger status. + * Represents LEDC_evt_time_ovf_timer3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3254,7 +3290,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_S 11 /** SOC_ETM_LEDC_EVT_TIMER0_CMP_ST : R/WTC/SS; bitpos: [12]; default: 0; - * Represents LEDC_EVT_TIMER0_CMP trigger status. + * Represents LEDC_evt_timer0_cmp trigger status. * 0: Not triggered * 1: Triggered */ @@ -3263,7 +3299,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_S 12 /** SOC_ETM_LEDC_EVT_TIMER1_CMP_ST : R/WTC/SS; bitpos: [13]; default: 0; - * Represents LEDC_EVT_TIMER1_CMP trigger status. + * Represents LEDC_evt_timer1_cmp trigger status. * 0: Not triggered * 1: Triggered */ @@ -3272,7 +3308,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_S 13 /** SOC_ETM_LEDC_EVT_TIMER2_CMP_ST : R/WTC/SS; bitpos: [14]; default: 0; - * Represents LEDC_EVT_TIMER2_CMP trigger status. + * Represents LEDC_evt_timer2_cmp trigger status. * 0: Not triggered * 1: Triggered */ @@ -3281,7 +3317,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_S 14 /** SOC_ETM_LEDC_EVT_TIMER3_CMP_ST : R/WTC/SS; bitpos: [15]; default: 0; - * Represents LEDC_EVT_TIMER3_CMP trigger status. + * Represents LEDC_evt_timer3_cmp trigger status. * 0: Not triggered * 1: Triggered */ @@ -3290,7 +3326,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_S 15 /** SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST : R/WTC/SS; bitpos: [16]; default: 0; - * Represents TG0_EVT_CNT_CMP_TIMER0 trigger status. + * Represents TG0_evt_cnt_cmp_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3299,7 +3335,7 @@ extern "C" { #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_S 16 /** SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST : R/WTC/SS; bitpos: [17]; default: 0; - * Represents TG0_EVT_CNT_CMP_TIMER1 trigger status. + * Represents TG0_evt_cnt_cmp_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3308,7 +3344,7 @@ extern "C" { #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_S 17 /** SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST : R/WTC/SS; bitpos: [18]; default: 0; - * Represents TG1_EVT_CNT_CMP_TIMER0 trigger status. + * Represents TG1_evt_cnt_cmp_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3317,7 +3353,7 @@ extern "C" { #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_S 18 /** SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST : R/WTC/SS; bitpos: [19]; default: 0; - * Represents TG1_EVT_CNT_CMP_TIMER1 trigger status. + * Represents TG1_evt_cnt_cmp_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3326,7 +3362,7 @@ extern "C" { #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_S 19 /** SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST : R/WTC/SS; bitpos: [20]; default: 0; - * Represents SYSTIMER_EVT_CNT_CMP0 trigger status. + * Represents SYSTIMER_evt_cnt_cmp0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3335,7 +3371,7 @@ extern "C" { #define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_V 0x00000001U #define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_S 20 /** SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST : R/WTC/SS; bitpos: [21]; default: 0; - * Represents SYSTIMER_EVT_CNT_CMP1 trigger status. + * Represents SYSTIMER_evt_cnt_cmp1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3344,7 +3380,7 @@ extern "C" { #define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_V 0x00000001U #define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_S 21 /** SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST : R/WTC/SS; bitpos: [22]; default: 0; - * Represents SYSTIMER_EVT_CNT_CMP2 trigger status. + * Represents SYSTIMER_evt_cnt_cmp2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3353,7 +3389,7 @@ extern "C" { #define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_V 0x00000001U #define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_S 22 /** SOC_ETM_ADC_EVT_CONV_CMPLT0_ST : R/WTC/SS; bitpos: [23]; default: 0; - * Represents ADC_EVT_CONV_CMPLT0 trigger status. + * Represents ADC_evt_conv_cmplt0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3362,7 +3398,7 @@ extern "C" { #define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_V 0x00000001U #define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_S 23 /** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST : R/WTC/SS; bitpos: [24]; default: 0; - * Represents ADC_EVT_EQ_ABOVE_THRESH0 trigger status. + * Represents ADC_evt_eq_above_thresh0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3371,7 +3407,7 @@ extern "C" { #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_V 0x00000001U #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_S 24 /** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST : R/WTC/SS; bitpos: [25]; default: 0; - * Represents ADC_EVT_EQ_ABOVE_THRESH1 trigger status. + * Represents ADC_evt_eq_above_thresh1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3380,7 +3416,7 @@ extern "C" { #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_V 0x00000001U #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_S 25 /** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST : R/WTC/SS; bitpos: [26]; default: 0; - * Represents ADC_EVT_EQ_BELOW_THRESH0 trigger status. + * Represents ADC_evt_eq_below_thresh0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3389,7 +3425,7 @@ extern "C" { #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_V 0x00000001U #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_S 26 /** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST : R/WTC/SS; bitpos: [27]; default: 0; - * Represents ADC_EVT_EQ_BELOW_THRESH1 trigger status. + * Represents ADC_evt_eq_below_thresh1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3398,7 +3434,7 @@ extern "C" { #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_V 0x00000001U #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_S 27 /** SOC_ETM_ADC_EVT_RESULT_DONE0_ST : R/WTC/SS; bitpos: [28]; default: 0; - * Represents ADC_EVT_RESULT_DONE0 trigger status. + * Represents ADC_evt_result_done0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3407,7 +3443,7 @@ extern "C" { #define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_V 0x00000001U #define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_S 28 /** SOC_ETM_ADC_EVT_STOPPED0_ST : R/WTC/SS; bitpos: [29]; default: 0; - * Represents ADC_EVT_STOPPED0 trigger status. + * Represents ADC_evt_stopped0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3416,7 +3452,7 @@ extern "C" { #define SOC_ETM_ADC_EVT_STOPPED0_ST_V 0x00000001U #define SOC_ETM_ADC_EVT_STOPPED0_ST_S 29 /** SOC_ETM_ADC_EVT_STARTED0_ST : R/WTC/SS; bitpos: [30]; default: 0; - * Represents ADC_EVT_STARTED0 trigger status. + * Represents ADC_evt_started0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3424,14 +3460,23 @@ extern "C" { #define SOC_ETM_ADC_EVT_STARTED0_ST_M (SOC_ETM_ADC_EVT_STARTED0_ST_V << SOC_ETM_ADC_EVT_STARTED0_ST_S) #define SOC_ETM_ADC_EVT_STARTED0_ST_V 0x00000001U #define SOC_ETM_ADC_EVT_STARTED0_ST_S 30 +/** SOC_ETM_REGDMA_EVT_DONE0_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents REGDMA_evt_done0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE0_ST (BIT(31)) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_M (SOC_ETM_REGDMA_EVT_DONE0_ST_V << SOC_ETM_REGDMA_EVT_DONE0_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE0_ST_S 31 /** SOC_ETM_EVT_ST1_CLR_REG register - * Event trigger status clear register + * Events trigger status clear register */ #define SOC_ETM_EVT_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1b4) /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR (BIT(0)) @@ -3439,8 +3484,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_S 0 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR (BIT(1)) @@ -3448,8 +3493,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_S 1 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR (BIT(2)) @@ -3457,8 +3502,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_S 2 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR (BIT(3)) @@ -3466,8 +3511,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_S 3 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR (BIT(4)) @@ -3475,8 +3520,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_S 4 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR (BIT(5)) @@ -3484,8 +3529,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_S 5 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR (BIT(6)) @@ -3493,8 +3538,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_S 6 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR (BIT(7)) @@ -3502,8 +3547,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_S 7 /** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR (BIT(8)) @@ -3511,8 +3556,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_S 8 /** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR (BIT(9)) @@ -3520,8 +3565,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_S 9 /** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR (BIT(10)) @@ -3529,8 +3574,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_S 10 /** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR (BIT(11)) @@ -3538,8 +3583,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_S 11 /** SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIMER0_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_timer0_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR (BIT(12)) @@ -3547,8 +3592,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_S 12 /** SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIMER1_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_timer1_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR (BIT(13)) @@ -3556,8 +3601,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_S 13 /** SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIMER2_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_timer2_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR (BIT(14)) @@ -3565,8 +3610,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_S 14 /** SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIMER3_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_timer3_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR (BIT(15)) @@ -3574,8 +3619,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_S 15 /** SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear TG0_EVT_CNT_CMP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR (BIT(16)) @@ -3583,8 +3628,8 @@ extern "C" { #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_S 16 /** SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear TG0_EVT_CNT_CMP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR (BIT(17)) @@ -3592,8 +3637,8 @@ extern "C" { #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_S 17 /** SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear TG1_EVT_CNT_CMP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR (BIT(18)) @@ -3601,8 +3646,8 @@ extern "C" { #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_S 18 /** SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear TG1_EVT_CNT_CMP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR (BIT(19)) @@ -3610,8 +3655,8 @@ extern "C" { #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_S 19 /** SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear SYSTIMER_EVT_CNT_CMP0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR (BIT(20)) @@ -3619,8 +3664,8 @@ extern "C" { #define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_V 0x00000001U #define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_S 20 /** SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear SYSTIMER_EVT_CNT_CMP1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR (BIT(21)) @@ -3628,8 +3673,8 @@ extern "C" { #define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_V 0x00000001U #define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_S 21 /** SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear SYSTIMER_EVT_CNT_CMP2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR (BIT(22)) @@ -3637,8 +3682,8 @@ extern "C" { #define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_V 0x00000001U #define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_S 22 /** SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear ADC_EVT_CONV_CMPLT0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR (BIT(23)) @@ -3646,8 +3691,8 @@ extern "C" { #define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_S 23 /** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear ADC_EVT_EQ_ABOVE_THRESH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR (BIT(24)) @@ -3655,8 +3700,8 @@ extern "C" { #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_S 24 /** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear ADC_EVT_EQ_ABOVE_THRESH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR (BIT(25)) @@ -3664,8 +3709,8 @@ extern "C" { #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_S 25 /** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear ADC_EVT_EQ_BELOW_THRESH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR (BIT(26)) @@ -3673,8 +3718,8 @@ extern "C" { #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_S 26 /** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR : WT; bitpos: [27]; default: 0; - * Configures whether or not to clear ADC_EVT_EQ_BELOW_THRESH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR (BIT(27)) @@ -3682,8 +3727,8 @@ extern "C" { #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_S 27 /** SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear ADC_EVT_RESULT_DONE0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_result_done0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR (BIT(28)) @@ -3691,8 +3736,8 @@ extern "C" { #define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_S 28 /** SOC_ETM_ADC_EVT_STOPPED0_ST_CLR : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear ADC_EVT_STOPPED0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_stopped0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR (BIT(29)) @@ -3700,21 +3745,93 @@ extern "C" { #define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_S 29 /** SOC_ETM_ADC_EVT_STARTED0_ST_CLR : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear ADC_EVT_STARTED0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_started0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_EVT_STARTED0_ST_CLR (BIT(30)) #define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_M (SOC_ETM_ADC_EVT_STARTED0_ST_CLR_V << SOC_ETM_ADC_EVT_STARTED0_ST_CLR_S) #define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_S 30 +/** SOC_ETM_REGDMA_EVT_DONE0_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear REGDMA_evt_done0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR (BIT(31)) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_S 31 /** SOC_ETM_EVT_ST2_REG register - * Event trigger status register + * Events trigger status register */ #define SOC_ETM_EVT_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1b8) +/** SOC_ETM_REGDMA_EVT_DONE1_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents REGDMA_evt_done1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE1_ST (BIT(0)) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_M (SOC_ETM_REGDMA_EVT_DONE1_ST_V << SOC_ETM_REGDMA_EVT_DONE1_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE1_ST_S 0 +/** SOC_ETM_REGDMA_EVT_DONE2_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents REGDMA_evt_done2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE2_ST (BIT(1)) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_M (SOC_ETM_REGDMA_EVT_DONE2_ST_V << SOC_ETM_REGDMA_EVT_DONE2_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE2_ST_S 1 +/** SOC_ETM_REGDMA_EVT_DONE3_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents REGDMA_evt_done3 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE3_ST (BIT(2)) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_M (SOC_ETM_REGDMA_EVT_DONE3_ST_V << SOC_ETM_REGDMA_EVT_DONE3_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE3_ST_S 2 +/** SOC_ETM_REGDMA_EVT_ERR0_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents REGDMA_evt_err0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR0_ST (BIT(3)) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_M (SOC_ETM_REGDMA_EVT_ERR0_ST_V << SOC_ETM_REGDMA_EVT_ERR0_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR0_ST_S 3 +/** SOC_ETM_REGDMA_EVT_ERR1_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents REGDMA_evt_err1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR1_ST (BIT(4)) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_M (SOC_ETM_REGDMA_EVT_ERR1_ST_V << SOC_ETM_REGDMA_EVT_ERR1_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR1_ST_S 4 +/** SOC_ETM_REGDMA_EVT_ERR2_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents REGDMA_evt_err2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR2_ST (BIT(5)) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_M (SOC_ETM_REGDMA_EVT_ERR2_ST_V << SOC_ETM_REGDMA_EVT_ERR2_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR2_ST_S 5 +/** SOC_ETM_REGDMA_EVT_ERR3_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents REGDMA_evt_err3 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR3_ST (BIT(6)) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_M (SOC_ETM_REGDMA_EVT_ERR3_ST_V << SOC_ETM_REGDMA_EVT_ERR3_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR3_ST_S 6 /** SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST : R/WTC/SS; bitpos: [7]; default: 0; - * Represents TMPSNSR_EVT_OVER_LIMIT trigger status. + * Represents TMPSNSR_evt_over_limit trigger status. * 0: Not triggered * 1: Triggered */ @@ -3723,7 +3840,7 @@ extern "C" { #define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_V 0x00000001U #define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_S 7 /** SOC_ETM_I2S0_EVT_RX_DONE_ST : R/WTC/SS; bitpos: [8]; default: 0; - * Represents I2S0_EVT_RX_DONE trigger status. + * Represents I2S0_evt_rx_done trigger status. * 0: Not triggered * 1: Triggered */ @@ -3732,7 +3849,7 @@ extern "C" { #define SOC_ETM_I2S0_EVT_RX_DONE_ST_V 0x00000001U #define SOC_ETM_I2S0_EVT_RX_DONE_ST_S 8 /** SOC_ETM_I2S0_EVT_TX_DONE_ST : R/WTC/SS; bitpos: [9]; default: 0; - * Represents I2S0_EVT_TX_DONE trigger status. + * Represents I2S0_evt_tx_done trigger status. * 0: Not triggered * 1: Triggered */ @@ -3741,7 +3858,7 @@ extern "C" { #define SOC_ETM_I2S0_EVT_TX_DONE_ST_V 0x00000001U #define SOC_ETM_I2S0_EVT_TX_DONE_ST_S 9 /** SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST : R/WTC/SS; bitpos: [10]; default: 0; - * Represents I2S0_EVT_X_WORDS_RECEIVED trigger status. + * Represents I2S0_evt_x_words_received trigger status. * 0: Not triggered * 1: Triggered */ @@ -3750,7 +3867,7 @@ extern "C" { #define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_V 0x00000001U #define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_S 10 /** SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST : R/WTC/SS; bitpos: [11]; default: 0; - * Represents I2S0_EVT_X_WORDS_SENT trigger status. + * Represents I2S0_evt_x_words_sent trigger status. * 0: Not triggered * 1: Triggered */ @@ -3758,8 +3875,71 @@ extern "C" { #define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_M (SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_V << SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_S) #define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_V 0x00000001U #define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_S 11 +/** SOC_ETM_I2S1_EVT_RX_DONE_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents I2S1_evt_rx_done trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_EVT_RX_DONE_ST (BIT(12)) +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_M (SOC_ETM_I2S1_EVT_RX_DONE_ST_V << SOC_ETM_I2S1_EVT_RX_DONE_ST_S) +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_V 0x00000001U +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_S 12 +/** SOC_ETM_I2S1_EVT_TX_DONE_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents I2S1_evt_tx_done trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_EVT_TX_DONE_ST (BIT(13)) +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_M (SOC_ETM_I2S1_EVT_TX_DONE_ST_V << SOC_ETM_I2S1_EVT_TX_DONE_ST_S) +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_V 0x00000001U +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_S 13 +/** SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents I2S1_evt_x_words_received trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST (BIT(14)) +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_M (SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_V << SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_S) +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_V 0x00000001U +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_S 14 +/** SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents I2S1_evt_x_words_sent trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST (BIT(15)) +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_M (SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_V << SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_S) +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_V 0x00000001U +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_S 15 +/** SOC_ETM_ULP_EVT_ERR_INTR_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents ULP_evt_err_intr trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ULP_EVT_ERR_INTR_ST (BIT(16)) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_M (SOC_ETM_ULP_EVT_ERR_INTR_ST_V << SOC_ETM_ULP_EVT_ERR_INTR_ST_S) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_V 0x00000001U +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_S 16 +/** SOC_ETM_ULP_EVT_HALT_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents ULP_evt_halt trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ULP_EVT_HALT_ST (BIT(17)) +#define SOC_ETM_ULP_EVT_HALT_ST_M (SOC_ETM_ULP_EVT_HALT_ST_V << SOC_ETM_ULP_EVT_HALT_ST_S) +#define SOC_ETM_ULP_EVT_HALT_ST_V 0x00000001U +#define SOC_ETM_ULP_EVT_HALT_ST_S 17 +/** SOC_ETM_ULP_EVT_START_INTR_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents ULP_evt_start_intr trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ULP_EVT_START_INTR_ST (BIT(18)) +#define SOC_ETM_ULP_EVT_START_INTR_ST_M (SOC_ETM_ULP_EVT_START_INTR_ST_V << SOC_ETM_ULP_EVT_START_INTR_ST_S) +#define SOC_ETM_ULP_EVT_START_INTR_ST_V 0x00000001U +#define SOC_ETM_ULP_EVT_START_INTR_ST_S 18 /** SOC_ETM_RTC_EVT_TICK_ST : R/WTC/SS; bitpos: [19]; default: 0; - * Represents RTC_EVT_TICK trigger status. + * Represents RTC_evt_tick trigger status. * 0: Not triggered * 1: Triggered */ @@ -3768,7 +3948,7 @@ extern "C" { #define SOC_ETM_RTC_EVT_TICK_ST_V 0x00000001U #define SOC_ETM_RTC_EVT_TICK_ST_S 19 /** SOC_ETM_RTC_EVT_OVF_ST : R/WTC/SS; bitpos: [20]; default: 0; - * Represents RTC_EVT_OVF trigger status. + * Represents RTC_evt_ovf trigger status. * 0: Not triggered * 1: Triggered */ @@ -3777,7 +3957,7 @@ extern "C" { #define SOC_ETM_RTC_EVT_OVF_ST_V 0x00000001U #define SOC_ETM_RTC_EVT_OVF_ST_S 20 /** SOC_ETM_RTC_EVT_CMP_ST : R/WTC/SS; bitpos: [21]; default: 0; - * Represents RTC_EVT_CMP trigger status. + * Represents RTC_evt_cmp trigger status. * 0: Not triggered * 1: Triggered */ @@ -3786,7 +3966,7 @@ extern "C" { #define SOC_ETM_RTC_EVT_CMP_ST_V 0x00000001U #define SOC_ETM_RTC_EVT_CMP_ST_S 21 /** SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST : R/WTC/SS; bitpos: [22]; default: 0; - * Represents GDMA_AHB_EVT_IN_DONE_CH0 trigger status. + * Represents GDMA_AHB_evt_in_done_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3795,7 +3975,7 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_S 22 /** SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST : R/WTC/SS; bitpos: [23]; default: 0; - * Represents GDMA_AHB_EVT_IN_DONE_CH1 trigger status. + * Represents GDMA_AHB_evt_in_done_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3803,8 +3983,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_S) #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_S 23 +/** SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents GDMA_AHB_evt_in_done_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST (BIT(24)) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_S 24 /** SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST : R/WTC/SS; bitpos: [25]; default: 0; - * Represents GDMA_AHB_EVT_IN_SUC_EOF_CH0 trigger status. + * Represents GDMA_AHB_evt_in_suc_eof_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3813,7 +4002,7 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_S 25 /** SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST : R/WTC/SS; bitpos: [26]; default: 0; - * Represents GDMA_AHB_EVT_IN_SUC_EOF_CH1 trigger status. + * Represents GDMA_AHB_evt_in_suc_eof_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3821,8 +4010,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_S) #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_S 26 +/** SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents GDMA_AHB_evt_in_suc_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST (BIT(27)) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_S 27 /** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [28]; default: 0; - * Represents GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0 trigger status. + * Represents GDMA_AHB_evt_in_fifo_empty_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3831,7 +4029,7 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_S 28 /** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [29]; default: 0; - * Represents GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1 trigger status. + * Represents GDMA_AHB_evt_in_fifo_empty_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3839,8 +4037,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_S) #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_S 29 +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_empty_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST (BIT(30)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_S 30 /** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [31]; default: 0; - * Represents GDMA_AHB_EVT_IN_FIFO_FULL_CH0 trigger status. + * Represents GDMA_AHB_evt_in_fifo_full_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3850,12 +4057,75 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_S 31 /** SOC_ETM_EVT_ST2_CLR_REG register - * Event trigger status clear register + * Events trigger status clear register */ #define SOC_ETM_EVT_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1bc) +/** SOC_ETM_REGDMA_EVT_DONE1_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear REGDMA_evt_done1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR (BIT(0)) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_S 0 +/** SOC_ETM_REGDMA_EVT_DONE2_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear REGDMA_evt_done2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR (BIT(1)) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_S 1 +/** SOC_ETM_REGDMA_EVT_DONE3_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear REGDMA_evt_done3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR (BIT(2)) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_S 2 +/** SOC_ETM_REGDMA_EVT_ERR0_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear REGDMA_evt_err0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR (BIT(3)) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_S 3 +/** SOC_ETM_REGDMA_EVT_ERR1_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear REGDMA_evt_err1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR (BIT(4)) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_S 4 +/** SOC_ETM_REGDMA_EVT_ERR2_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear REGDMA_evt_err2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR (BIT(5)) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_S 5 +/** SOC_ETM_REGDMA_EVT_ERR3_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear REGDMA_evt_err3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR (BIT(6)) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_S 6 /** SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear TMPSNSR_EVT_OVER_LIMIT trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TMPSNSR_evt_over_limit trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR (BIT(7)) @@ -3863,8 +4133,8 @@ extern "C" { #define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_V 0x00000001U #define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_S 7 /** SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear I2S0_EVT_RX_DONE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_evt_rx_done trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR (BIT(8)) @@ -3872,8 +4142,8 @@ extern "C" { #define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_V 0x00000001U #define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_S 8 /** SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear I2S0_EVT_TX_DONE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_evt_tx_done trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR (BIT(9)) @@ -3881,8 +4151,8 @@ extern "C" { #define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_V 0x00000001U #define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_S 9 /** SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear I2S0_EVT_X_WORDS_RECEIVED trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_evt_x_words_received trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR (BIT(10)) @@ -3890,17 +4160,80 @@ extern "C" { #define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_V 0x00000001U #define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_S 10 /** SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear I2S0_EVT_X_WORDS_SENT trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_evt_x_words_sent trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR (BIT(11)) #define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_M (SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_V << SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_S) #define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_V 0x00000001U #define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_S 11 +/** SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear I2S1_evt_rx_done trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR (BIT(12)) +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_M (SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_V << SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_S) +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_S 12 +/** SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear I2S1_evt_tx_done trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR (BIT(13)) +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_M (SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_V << SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_S) +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_S 13 +/** SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear I2S1_evt_x_words_received trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR (BIT(14)) +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_M (SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_V << SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_S) +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_S 14 +/** SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear I2S1_evt_x_words_sent trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR (BIT(15)) +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_M (SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_V << SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_S) +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_S 15 +/** SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ULP_evt_err_intr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR (BIT(16)) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_M (SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_V << SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_S) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_S 16 +/** SOC_ETM_ULP_EVT_HALT_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ULP_evt_halt trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ULP_EVT_HALT_ST_CLR (BIT(17)) +#define SOC_ETM_ULP_EVT_HALT_ST_CLR_M (SOC_ETM_ULP_EVT_HALT_ST_CLR_V << SOC_ETM_ULP_EVT_HALT_ST_CLR_S) +#define SOC_ETM_ULP_EVT_HALT_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_EVT_HALT_ST_CLR_S 17 +/** SOC_ETM_ULP_EVT_START_INTR_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear ULP_evt_start_intr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR (BIT(18)) +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_M (SOC_ETM_ULP_EVT_START_INTR_ST_CLR_V << SOC_ETM_ULP_EVT_START_INTR_ST_CLR_S) +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_S 18 /** SOC_ETM_RTC_EVT_TICK_ST_CLR : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear RTC_EVT_TICK trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear RTC_evt_tick trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_RTC_EVT_TICK_ST_CLR (BIT(19)) @@ -3908,8 +4241,8 @@ extern "C" { #define SOC_ETM_RTC_EVT_TICK_ST_CLR_V 0x00000001U #define SOC_ETM_RTC_EVT_TICK_ST_CLR_S 19 /** SOC_ETM_RTC_EVT_OVF_ST_CLR : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear RTC_EVT_OVF trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear RTC_evt_ovf trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_RTC_EVT_OVF_ST_CLR (BIT(20)) @@ -3917,8 +4250,8 @@ extern "C" { #define SOC_ETM_RTC_EVT_OVF_ST_CLR_V 0x00000001U #define SOC_ETM_RTC_EVT_OVF_ST_CLR_S 20 /** SOC_ETM_RTC_EVT_CMP_ST_CLR : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear RTC_EVT_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear RTC_evt_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_RTC_EVT_CMP_ST_CLR (BIT(21)) @@ -3926,8 +4259,8 @@ extern "C" { #define SOC_ETM_RTC_EVT_CMP_ST_CLR_V 0x00000001U #define SOC_ETM_RTC_EVT_CMP_ST_CLR_S 21 /** SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_CLR : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_DONE_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_done_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_CLR (BIT(22)) @@ -3935,17 +4268,26 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_S 22 /** SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_DONE_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_done_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR (BIT(23)) #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_S 23 +/** SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_done_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR (BIT(24)) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_S 24 /** SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_SUC_EOF_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_suc_eof_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR (BIT(25)) @@ -3953,17 +4295,26 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_S 25 /** SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_SUC_EOF_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_suc_eof_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR (BIT(26)) #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_S 26 +/** SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_suc_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR (BIT(27)) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_S 27 /** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_empty_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR (BIT(28)) @@ -3971,17 +4322,26 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_S 28 /** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_empty_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR (BIT(29)) #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S 29 +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_empty_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR (BIT(30)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S 30 /** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_FIFO_FULL_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_full_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR (BIT(31)) @@ -3990,11 +4350,11 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_S 31 /** SOC_ETM_EVT_ST3_REG register - * Event trigger status register + * Events trigger status register */ #define SOC_ETM_EVT_ST3_REG (DR_REG_SOC_ETM_BASE + 0x1c0) /** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [0]; default: 0; - * Represents GDMA_AHB_EVT_IN_FIFO_FULL_CH1 trigger status. + * Represents GDMA_AHB_evt_in_fifo_full_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4002,8 +4362,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_S) #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_S 0 +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_full_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST (BIT(1)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_S 1 /** SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST : R/WTC/SS; bitpos: [2]; default: 0; - * Represents GDMA_AHB_EVT_OUT_DONE_CH0 trigger status. + * Represents GDMA_AHB_evt_out_done_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4012,7 +4381,7 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_S 2 /** SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST : R/WTC/SS; bitpos: [3]; default: 0; - * Represents GDMA_AHB_EVT_OUT_DONE_CH1 trigger status. + * Represents GDMA_AHB_evt_out_done_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4020,8 +4389,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_S 3 +/** SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GDMA_AHB_evt_out_done_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST (BIT(4)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_S 4 /** SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST : R/WTC/SS; bitpos: [5]; default: 0; - * Represents GDMA_AHB_EVT_OUT_EOF_CH0 trigger status. + * Represents GDMA_AHB_evt_out_eof_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4030,7 +4408,7 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_S 5 /** SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST : R/WTC/SS; bitpos: [6]; default: 0; - * Represents GDMA_AHB_EVT_OUT_EOF_CH1 trigger status. + * Represents GDMA_AHB_evt_out_eof_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4038,8 +4416,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_S 6 +/** SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GDMA_AHB_evt_out_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST (BIT(7)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_S 7 /** SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST : R/WTC/SS; bitpos: [8]; default: 0; - * Represents GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0 trigger status. + * Represents GDMA_AHB_evt_out_total_eof_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4048,7 +4435,7 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_S 8 /** SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST : R/WTC/SS; bitpos: [9]; default: 0; - * Represents GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1 trigger status. + * Represents GDMA_AHB_evt_out_total_eof_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4056,8 +4443,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_S 9 +/** SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GDMA_AHB_evt_out_total_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST (BIT(10)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_S 10 /** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [11]; default: 0; - * Represents GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0 trigger status. + * Represents GDMA_AHB_evt_out_fifo_empty_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4066,7 +4462,7 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_S 11 /** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [12]; default: 0; - * Represents GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1 trigger status. + * Represents GDMA_AHB_evt_out_fifo_empty_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4074,8 +4470,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_S 12 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_empty_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST (BIT(13)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_S 13 /** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [14]; default: 0; - * Represents GDMA_AHB_EVT_OUT_FIFO_FULL_CH0 trigger status. + * Represents GDMA_AHB_evt_out_fifo_full_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4084,7 +4489,7 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_S 14 /** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [15]; default: 0; - * Represents GDMA_AHB_EVT_OUT_FIFO_FULL_CH1 trigger status. + * Represents GDMA_AHB_evt_out_fifo_full_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4092,8 +4497,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_S 15 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_full_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST (BIT(16)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_S 16 /** SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST : R/WTC/SS; bitpos: [17]; default: 0; - * Represents PMU_EVT_SLEEP_WEEKUP trigger status. + * Represents PMU_evt_sleep_weekup trigger status. * 0: Not triggered * 1: Triggered */ @@ -4103,21 +4517,30 @@ extern "C" { #define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_S 17 /** SOC_ETM_EVT_ST3_CLR_REG register - * Event trigger status clear register + * Events trigger status clear register */ #define SOC_ETM_EVT_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1c4) /** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_FIFO_FULL_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_full_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR (BIT(0)) #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_S 0 +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_full_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR (BIT(1)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_S 1 /** SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_DONE_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_done_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR (BIT(2)) @@ -4125,17 +4548,26 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_S 2 /** SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_DONE_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_done_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR (BIT(3)) #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_S 3 +/** SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_done_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR (BIT(4)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_S 4 /** SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_EOF_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_eof_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR (BIT(5)) @@ -4143,17 +4575,26 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_S 5 /** SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_EOF_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_eof_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR (BIT(6)) #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_S 6 +/** SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR (BIT(7)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_S 7 /** SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_total_eof_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR (BIT(8)) @@ -4161,17 +4602,26 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S 8 /** SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_total_eof_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR (BIT(9)) #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S 9 +/** SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_total_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR (BIT(10)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S 10 /** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_empty_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR (BIT(11)) @@ -4179,17 +4629,26 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_S 11 /** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_empty_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR (BIT(12)) #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S 12 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_empty_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR (BIT(13)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S 13 /** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_FIFO_FULL_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_full_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR (BIT(14)) @@ -4197,17 +4656,26 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_S 14 /** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_FIFO_FULL_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_full_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR (BIT(15)) #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S 15 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_full_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR (BIT(16)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S 16 /** SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear PMU_EVT_SLEEP_WEEKUP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear PMU_evt_sleep_weekup trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR (BIT(17)) @@ -4216,11 +4684,11 @@ extern "C" { #define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_S 17 /** SOC_ETM_TASK_ST0_REG register - * Task trigger status register + * Tasks trigger status register */ #define SOC_ETM_TASK_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1c8) /** SOC_ETM_GPIO_TASK_CH0_SET_ST : R/WTC/SS; bitpos: [0]; default: 0; - * Represents GPIO_TASK_CH0_SET trigger status. + * Represents GPIO_task_ch0_set trigger status. * 0: Not triggered * 1: Triggered */ @@ -4229,7 +4697,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH0_SET_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH0_SET_ST_S 0 /** SOC_ETM_GPIO_TASK_CH1_SET_ST : R/WTC/SS; bitpos: [1]; default: 0; - * Represents GPIO_TASK_CH1_SET trigger status. + * Represents GPIO_task_ch1_set trigger status. * 0: Not triggered * 1: Triggered */ @@ -4238,7 +4706,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH1_SET_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH1_SET_ST_S 1 /** SOC_ETM_GPIO_TASK_CH2_SET_ST : R/WTC/SS; bitpos: [2]; default: 0; - * Represents GPIO_TASK_CH2_SET trigger status. + * Represents GPIO_task_ch2_set trigger status. * 0: Not triggered * 1: Triggered */ @@ -4247,7 +4715,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH2_SET_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH2_SET_ST_S 2 /** SOC_ETM_GPIO_TASK_CH3_SET_ST : R/WTC/SS; bitpos: [3]; default: 0; - * Represents GPIO_TASK_CH3_SET trigger status. + * Represents GPIO_task_ch3_set trigger status. * 0: Not triggered * 1: Triggered */ @@ -4256,7 +4724,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH3_SET_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH3_SET_ST_S 3 /** SOC_ETM_GPIO_TASK_CH4_SET_ST : R/WTC/SS; bitpos: [4]; default: 0; - * Represents GPIO_TASK_CH4_SET trigger status. + * Represents GPIO_task_ch4_set trigger status. * 0: Not triggered * 1: Triggered */ @@ -4265,7 +4733,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH4_SET_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH4_SET_ST_S 4 /** SOC_ETM_GPIO_TASK_CH5_SET_ST : R/WTC/SS; bitpos: [5]; default: 0; - * Represents GPIO_TASK_CH5_SET trigger status. + * Represents GPIO_task_ch5_set trigger status. * 0: Not triggered * 1: Triggered */ @@ -4274,7 +4742,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH5_SET_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH5_SET_ST_S 5 /** SOC_ETM_GPIO_TASK_CH6_SET_ST : R/WTC/SS; bitpos: [6]; default: 0; - * Represents GPIO_TASK_CH6_SET trigger status. + * Represents GPIO_task_ch6_set trigger status. * 0: Not triggered * 1: Triggered */ @@ -4283,7 +4751,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH6_SET_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH6_SET_ST_S 6 /** SOC_ETM_GPIO_TASK_CH7_SET_ST : R/WTC/SS; bitpos: [7]; default: 0; - * Represents GPIO_TASK_CH7_SET trigger status. + * Represents GPIO_task_ch7_set trigger status. * 0: Not triggered * 1: Triggered */ @@ -4292,7 +4760,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH7_SET_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH7_SET_ST_S 7 /** SOC_ETM_GPIO_TASK_CH0_CLEAR_ST : R/WTC/SS; bitpos: [8]; default: 0; - * Represents GPIO_TASK_CH0_CLEAR trigger status. + * Represents GPIO_task_ch0_clear trigger status. * 0: Not triggered * 1: Triggered */ @@ -4301,7 +4769,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_S 8 /** SOC_ETM_GPIO_TASK_CH1_CLEAR_ST : R/WTC/SS; bitpos: [9]; default: 0; - * Represents GPIO_TASK_CH1_CLEAR trigger status. + * Represents GPIO_task_ch1_clear trigger status. * 0: Not triggered * 1: Triggered */ @@ -4310,7 +4778,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_S 9 /** SOC_ETM_GPIO_TASK_CH2_CLEAR_ST : R/WTC/SS; bitpos: [10]; default: 0; - * Represents GPIO_TASK_CH2_CLEAR trigger status. + * Represents GPIO_task_ch2_clear trigger status. * 0: Not triggered * 1: Triggered */ @@ -4319,7 +4787,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_S 10 /** SOC_ETM_GPIO_TASK_CH3_CLEAR_ST : R/WTC/SS; bitpos: [11]; default: 0; - * Represents GPIO_TASK_CH3_CLEAR trigger status. + * Represents GPIO_task_ch3_clear trigger status. * 0: Not triggered * 1: Triggered */ @@ -4328,7 +4796,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_S 11 /** SOC_ETM_GPIO_TASK_CH4_CLEAR_ST : R/WTC/SS; bitpos: [12]; default: 0; - * Represents GPIO_TASK_CH4_CLEAR trigger status. + * Represents GPIO_task_ch4_clear trigger status. * 0: Not triggered * 1: Triggered */ @@ -4337,7 +4805,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_S 12 /** SOC_ETM_GPIO_TASK_CH5_CLEAR_ST : R/WTC/SS; bitpos: [13]; default: 0; - * Represents GPIO_TASK_CH5_CLEAR trigger status. + * Represents GPIO_task_ch5_clear trigger status. * 0: Not triggered * 1: Triggered */ @@ -4346,7 +4814,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_S 13 /** SOC_ETM_GPIO_TASK_CH6_CLEAR_ST : R/WTC/SS; bitpos: [14]; default: 0; - * Represents GPIO_TASK_CH6_CLEAR trigger status. + * Represents GPIO_task_ch6_clear trigger status. * 0: Not triggered * 1: Triggered */ @@ -4355,7 +4823,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_S 14 /** SOC_ETM_GPIO_TASK_CH7_CLEAR_ST : R/WTC/SS; bitpos: [15]; default: 0; - * Represents GPIO_TASK_CH7_CLEAR trigger status. + * Represents GPIO_task_ch7_clear trigger status. * 0: Not triggered * 1: Triggered */ @@ -4364,7 +4832,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_S 15 /** SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST : R/WTC/SS; bitpos: [16]; default: 0; - * Represents GPIO_TASK_CH0_TOGGLE trigger status. + * Represents GPIO_task_ch0_toggle trigger status. * 0: Not triggered * 1: Triggered */ @@ -4373,7 +4841,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_S 16 /** SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST : R/WTC/SS; bitpos: [17]; default: 0; - * Represents GPIO_TASK_CH1_TOGGLE trigger status. + * Represents GPIO_task_ch1_toggle trigger status. * 0: Not triggered * 1: Triggered */ @@ -4382,7 +4850,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_S 17 /** SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST : R/WTC/SS; bitpos: [18]; default: 0; - * Represents GPIO_TASK_CH2_TOGGLE trigger status. + * Represents GPIO_task_ch2_toggle trigger status. * 0: Not triggered * 1: Triggered */ @@ -4391,7 +4859,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_S 18 /** SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST : R/WTC/SS; bitpos: [19]; default: 0; - * Represents GPIO_TASK_CH3_TOGGLE trigger status. + * Represents GPIO_task_ch3_toggle trigger status. * 0: Not triggered * 1: Triggered */ @@ -4400,7 +4868,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_S 19 /** SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST : R/WTC/SS; bitpos: [20]; default: 0; - * Represents GPIO_TASK_CH4_TOGGLE trigger status. + * Represents GPIO_task_ch4_toggle trigger status. * 0: Not triggered * 1: Triggered */ @@ -4409,7 +4877,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_S 20 /** SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST : R/WTC/SS; bitpos: [21]; default: 0; - * Represents GPIO_TASK_CH5_TOGGLE trigger status. + * Represents GPIO_task_ch5_toggle trigger status. * 0: Not triggered * 1: Triggered */ @@ -4418,7 +4886,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_S 21 /** SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST : R/WTC/SS; bitpos: [22]; default: 0; - * Represents GPIO_TASK_CH6_TOGGLE trigger status. + * Represents GPIO_task_ch6_toggle trigger status. * 0: Not triggered * 1: Triggered */ @@ -4427,7 +4895,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_S 22 /** SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST : R/WTC/SS; bitpos: [23]; default: 0; - * Represents GPIO_TASK_CH7_TOGGLE trigger status. + * Represents GPIO_task_ch7_toggle trigger status. * 0: Not triggered * 1: Triggered */ @@ -4436,7 +4904,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_S 23 /** SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST : R/WTC/SS; bitpos: [24]; default: 0; - * Represents LEDC_TASK_TIMER0_RES_UPDATE trigger status. + * Represents LEDC_task_timer0_res_update trigger status. * 0: Not triggered * 1: Triggered */ @@ -4445,7 +4913,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_S 24 /** SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST : R/WTC/SS; bitpos: [25]; default: 0; - * Represents LEDC_TASK_TIMER1_RES_UPDATE trigger status. + * Represents LEDC_task_timer1_res_update trigger status. * 0: Not triggered * 1: Triggered */ @@ -4454,7 +4922,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_S 25 /** SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST : R/WTC/SS; bitpos: [26]; default: 0; - * Represents LEDC_TASK_TIMER2_RES_UPDATE trigger status. + * Represents LEDC_task_timer2_res_update trigger status. * 0: Not triggered * 1: Triggered */ @@ -4463,7 +4931,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_S 26 /** SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST : R/WTC/SS; bitpos: [27]; default: 0; - * Represents LEDC_TASK_TIMER3_RES_UPDATE trigger status. + * Represents LEDC_task_timer3_res_update trigger status. * 0: Not triggered * 1: Triggered */ @@ -4472,7 +4940,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_S 27 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST : R/WTC/SS; bitpos: [28]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH0 trigger status. + * Represents LEDC_task_duty_scale_update_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4481,7 +4949,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_S 28 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST : R/WTC/SS; bitpos: [29]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH1 trigger status. + * Represents LEDC_task_duty_scale_update_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4490,7 +4958,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_S 29 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST : R/WTC/SS; bitpos: [30]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH2 trigger status. + * Represents LEDC_task_duty_scale_update_ch2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4499,7 +4967,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_S 30 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST : R/WTC/SS; bitpos: [31]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH3 trigger status. + * Represents LEDC_task_duty_scale_update_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4509,12 +4977,12 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_S 31 /** SOC_ETM_TASK_ST0_CLR_REG register - * Task trigger status clear register + * Tasks trigger status clear register */ #define SOC_ETM_TASK_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1cc) /** SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH0_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch0_set trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR (BIT(0)) @@ -4522,8 +4990,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_S 0 /** SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH1_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch1_set trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR (BIT(1)) @@ -4531,8 +4999,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_S 1 /** SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH2_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch2_set trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR (BIT(2)) @@ -4540,8 +5008,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_S 2 /** SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH3_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch3_set trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR (BIT(3)) @@ -4549,8 +5017,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_S 3 /** SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH4_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch4_set trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR (BIT(4)) @@ -4558,8 +5026,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_S 4 /** SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH5_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch5_set trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR (BIT(5)) @@ -4567,8 +5035,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_S 5 /** SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH6_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch6_set trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR (BIT(6)) @@ -4576,8 +5044,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_S 6 /** SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH7_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch7_set trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR (BIT(7)) @@ -4585,8 +5053,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_S 7 /** SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH0_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch0_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR (BIT(8)) @@ -4594,8 +5062,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_S 8 /** SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH1_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch1_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR (BIT(9)) @@ -4603,8 +5071,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_S 9 /** SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH2_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch2_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR (BIT(10)) @@ -4612,8 +5080,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_S 10 /** SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH3_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch3_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR (BIT(11)) @@ -4621,8 +5089,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_S 11 /** SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH4_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch4_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR (BIT(12)) @@ -4630,8 +5098,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_S 12 /** SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH5_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch5_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR (BIT(13)) @@ -4639,8 +5107,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_S 13 /** SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH6_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch6_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR (BIT(14)) @@ -4648,8 +5116,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_S 14 /** SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH7_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch7_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR (BIT(15)) @@ -4657,8 +5125,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_S 15 /** SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH0_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch0_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR (BIT(16)) @@ -4666,8 +5134,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_S 16 /** SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH1_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch1_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR (BIT(17)) @@ -4675,8 +5143,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_S 17 /** SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH2_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch2_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR (BIT(18)) @@ -4684,8 +5152,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_S 18 /** SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH3_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch3_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR (BIT(19)) @@ -4693,8 +5161,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_S 19 /** SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH4_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch4_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR (BIT(20)) @@ -4702,8 +5170,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_S 20 /** SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH5_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch5_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR (BIT(21)) @@ -4711,8 +5179,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_S 21 /** SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH6_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch6_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR (BIT(22)) @@ -4720,8 +5188,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_S 22 /** SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH7_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch7_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR (BIT(23)) @@ -4729,8 +5197,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_S 23 /** SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_RES_UPDATE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_res_update trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR (BIT(24)) @@ -4738,8 +5206,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_S 24 /** SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_RES_UPDATE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_res_update trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR (BIT(25)) @@ -4747,8 +5215,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_S 25 /** SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_RES_UPDATE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_res_update trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR (BIT(26)) @@ -4756,8 +5224,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_S 26 /** SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR : WT; bitpos: [27]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_RES_UPDATE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_res_update trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR (BIT(27)) @@ -4765,8 +5233,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_S 27 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR (BIT(28)) @@ -4774,8 +5242,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_S 28 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR (BIT(29)) @@ -4783,8 +5251,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_S 29 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR (BIT(30)) @@ -4792,8 +5260,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_S 30 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR (BIT(31)) @@ -4802,11 +5270,11 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_S 31 /** SOC_ETM_TASK_ST1_REG register - * Task trigger status register + * Tasks trigger status register */ #define SOC_ETM_TASK_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1d0) /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST : R/WTC/SS; bitpos: [0]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH4 trigger status. + * Represents LEDC_task_duty_scale_update_ch4 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4815,7 +5283,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_S 0 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST : R/WTC/SS; bitpos: [1]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH5 trigger status. + * Represents LEDC_task_duty_scale_update_ch5 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4824,7 +5292,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_S 1 /** SOC_ETM_LEDC_TASK_TIMER0_CAP_ST : R/WTC/SS; bitpos: [2]; default: 0; - * Represents LEDC_TASK_TIMER0_CAP trigger status. + * Represents LEDC_task_timer0_cap trigger status. * 0: Not triggered * 1: Triggered */ @@ -4833,7 +5301,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_S 2 /** SOC_ETM_LEDC_TASK_TIMER1_CAP_ST : R/WTC/SS; bitpos: [3]; default: 0; - * Represents LEDC_TASK_TIMER1_CAP trigger status. + * Represents LEDC_task_timer1_cap trigger status. * 0: Not triggered * 1: Triggered */ @@ -4842,7 +5310,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_S 3 /** SOC_ETM_LEDC_TASK_TIMER2_CAP_ST : R/WTC/SS; bitpos: [4]; default: 0; - * Represents LEDC_TASK_TIMER2_CAP trigger status. + * Represents LEDC_task_timer2_cap trigger status. * 0: Not triggered * 1: Triggered */ @@ -4851,7 +5319,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_S 4 /** SOC_ETM_LEDC_TASK_TIMER3_CAP_ST : R/WTC/SS; bitpos: [5]; default: 0; - * Represents LEDC_TASK_TIMER3_CAP trigger status. + * Represents LEDC_task_timer3_cap trigger status. * 0: Not triggered * 1: Triggered */ @@ -4860,7 +5328,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_S 5 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST : R/WTC/SS; bitpos: [6]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH0 trigger status. + * Represents LEDC_task_sig_out_dis_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4869,7 +5337,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_S 6 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST : R/WTC/SS; bitpos: [7]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH1 trigger status. + * Represents LEDC_task_sig_out_dis_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4878,7 +5346,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_S 7 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST : R/WTC/SS; bitpos: [8]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH2 trigger status. + * Represents LEDC_task_sig_out_dis_ch2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4887,7 +5355,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_S 8 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST : R/WTC/SS; bitpos: [9]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH3 trigger status. + * Represents LEDC_task_sig_out_dis_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4896,7 +5364,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_S 9 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST : R/WTC/SS; bitpos: [10]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH4 trigger status. + * Represents LEDC_task_sig_out_dis_ch4 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4905,7 +5373,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_S 10 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST : R/WTC/SS; bitpos: [11]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH5 trigger status. + * Represents LEDC_task_sig_out_dis_ch5 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4914,7 +5382,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_S 11 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST : R/WTC/SS; bitpos: [12]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH0 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4923,7 +5391,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_S 12 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST : R/WTC/SS; bitpos: [13]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH1 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4932,7 +5400,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_S 13 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST : R/WTC/SS; bitpos: [14]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH2 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4941,7 +5409,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_S 14 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST : R/WTC/SS; bitpos: [15]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH3 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4950,7 +5418,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_S 15 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST : R/WTC/SS; bitpos: [16]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH4 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch4 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4959,7 +5427,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_S 16 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST : R/WTC/SS; bitpos: [17]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH5 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch5 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4968,7 +5436,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_S 17 /** SOC_ETM_LEDC_TASK_TIMER0_RST_ST : R/WTC/SS; bitpos: [18]; default: 0; - * Represents LEDC_TASK_TIMER0_RST trigger status. + * Represents LEDC_task_timer0_rst trigger status. * 0: Not triggered * 1: Triggered */ @@ -4977,7 +5445,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_S 18 /** SOC_ETM_LEDC_TASK_TIMER1_RST_ST : R/WTC/SS; bitpos: [19]; default: 0; - * Represents LEDC_TASK_TIMER1_RST trigger status. + * Represents LEDC_task_timer1_rst trigger status. * 0: Not triggered * 1: Triggered */ @@ -4986,7 +5454,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_S 19 /** SOC_ETM_LEDC_TASK_TIMER2_RST_ST : R/WTC/SS; bitpos: [20]; default: 0; - * Represents LEDC_TASK_TIMER2_RST trigger status. + * Represents LEDC_task_timer2_rst trigger status. * 0: Not triggered * 1: Triggered */ @@ -4995,7 +5463,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_S 20 /** SOC_ETM_LEDC_TASK_TIMER3_RST_ST : R/WTC/SS; bitpos: [21]; default: 0; - * Represents LEDC_TASK_TIMER3_RST trigger status. + * Represents LEDC_task_timer3_rst trigger status. * 0: Not triggered * 1: Triggered */ @@ -5004,7 +5472,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_S 21 /** SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST : R/WTC/SS; bitpos: [22]; default: 0; - * Represents LEDC_TASK_TIMER0_RESUME trigger status. + * Represents LEDC_task_timer0_resume trigger status. * 0: Not triggered * 1: Triggered */ @@ -5013,7 +5481,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_S 22 /** SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST : R/WTC/SS; bitpos: [23]; default: 0; - * Represents LEDC_TASK_TIMER1_RESUME trigger status. + * Represents LEDC_task_timer1_resume trigger status. * 0: Not triggered * 1: Triggered */ @@ -5022,7 +5490,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_S 23 /** SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST : R/WTC/SS; bitpos: [24]; default: 0; - * Represents LEDC_TASK_TIMER2_RESUME trigger status. + * Represents LEDC_task_timer2_resume trigger status. * 0: Not triggered * 1: Triggered */ @@ -5031,7 +5499,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_S 24 /** SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST : R/WTC/SS; bitpos: [25]; default: 0; - * Represents LEDC_TASK_TIMER3_RESUME trigger status. + * Represents LEDC_task_timer3_resume trigger status. * 0: Not triggered * 1: Triggered */ @@ -5040,7 +5508,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_S 25 /** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST : R/WTC/SS; bitpos: [26]; default: 0; - * Represents LEDC_TASK_TIMER0_PAUSE trigger status. + * Represents LEDC_task_timer0_pause trigger status. * 0: Not triggered * 1: Triggered */ @@ -5049,7 +5517,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_S 26 /** SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST : R/WTC/SS; bitpos: [27]; default: 0; - * Represents LEDC_TASK_TIMER1_PAUSE trigger status. + * Represents LEDC_task_timer1_pause trigger status. * 0: Not triggered * 1: Triggered */ @@ -5058,7 +5526,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_S 27 /** SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST : R/WTC/SS; bitpos: [28]; default: 0; - * Represents LEDC_TASK_TIMER2_PAUSE trigger status. + * Represents LEDC_task_timer2_pause trigger status. * 0: Not triggered * 1: Triggered */ @@ -5067,7 +5535,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_S 28 /** SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST : R/WTC/SS; bitpos: [29]; default: 0; - * Represents LEDC_TASK_TIMER3_PAUSE trigger status. + * Represents LEDC_task_timer3_pause trigger status. * 0: Not triggered * 1: Triggered */ @@ -5076,7 +5544,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_S 29 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST : R/WTC/SS; bitpos: [30]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH0 trigger status. + * Represents LEDC_task_gamma_restart_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5085,7 +5553,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_S 30 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST : R/WTC/SS; bitpos: [31]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH1 trigger status. + * Represents LEDC_task_gamma_restart_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5095,12 +5563,12 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_S 31 /** SOC_ETM_TASK_ST1_CLR_REG register - * Task trigger status clear register + * Tasks trigger status clear register */ #define SOC_ETM_TASK_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1d4) /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR (BIT(0)) @@ -5108,8 +5576,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_S 0 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR (BIT(1)) @@ -5117,8 +5585,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_S 1 /** SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_CAP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_cap trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR (BIT(2)) @@ -5126,8 +5594,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_S 2 /** SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_CAP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_cap trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR (BIT(3)) @@ -5135,8 +5603,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_S 3 /** SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_CAP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_cap trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR (BIT(4)) @@ -5144,8 +5612,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_S 4 /** SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_CAP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_cap trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR (BIT(5)) @@ -5153,8 +5621,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_S 5 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR (BIT(6)) @@ -5162,8 +5630,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_S 6 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR (BIT(7)) @@ -5171,8 +5639,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_S 7 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR (BIT(8)) @@ -5180,8 +5648,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_S 8 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR (BIT(9)) @@ -5189,8 +5657,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_S 9 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR (BIT(10)) @@ -5198,8 +5666,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_S 10 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR (BIT(11)) @@ -5207,8 +5675,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_S 11 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR (BIT(12)) @@ -5216,8 +5684,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_S 12 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR (BIT(13)) @@ -5225,8 +5693,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_S 13 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR (BIT(14)) @@ -5234,8 +5702,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_S 14 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR (BIT(15)) @@ -5243,8 +5711,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_S 15 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR (BIT(16)) @@ -5252,8 +5720,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_S 16 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR (BIT(17)) @@ -5261,8 +5729,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_S 17 /** SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_RST trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_rst trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR (BIT(18)) @@ -5270,8 +5738,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_S 18 /** SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_RST trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_rst trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR (BIT(19)) @@ -5279,8 +5747,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_S 19 /** SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_RST trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_rst trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR (BIT(20)) @@ -5288,8 +5756,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_S 20 /** SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_RST trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_rst trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR (BIT(21)) @@ -5297,8 +5765,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_S 21 /** SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_RESUME trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_resume trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR (BIT(22)) @@ -5306,8 +5774,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_S 22 /** SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_RESUME trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_resume trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR (BIT(23)) @@ -5315,8 +5783,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_S 23 /** SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_RESUME trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_resume trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR (BIT(24)) @@ -5324,8 +5792,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_S 24 /** SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_RESUME trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_resume trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR (BIT(25)) @@ -5333,8 +5801,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_S 25 /** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_PAUSE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_pause trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR (BIT(26)) @@ -5342,8 +5810,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_S 26 /** SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR : WT; bitpos: [27]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_PAUSE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_pause trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR (BIT(27)) @@ -5351,8 +5819,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_S 27 /** SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_PAUSE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_pause trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR (BIT(28)) @@ -5360,8 +5828,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_S 28 /** SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_PAUSE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_pause trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR (BIT(29)) @@ -5369,8 +5837,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_S 29 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR (BIT(30)) @@ -5378,8 +5846,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_S 30 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR (BIT(31)) @@ -5388,11 +5856,11 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_S 31 /** SOC_ETM_TASK_ST2_REG register - * Task trigger status register + * Tasks trigger status register */ #define SOC_ETM_TASK_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1d8) /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST : R/WTC/SS; bitpos: [0]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH2 trigger status. + * Represents LEDC_task_gamma_restart_ch2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5401,7 +5869,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_S 0 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST : R/WTC/SS; bitpos: [1]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH3 trigger status. + * Represents LEDC_task_gamma_restart_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5410,7 +5878,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_S 1 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST : R/WTC/SS; bitpos: [2]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH4 trigger status. + * Represents LEDC_task_gamma_restart_ch4 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5419,7 +5887,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_S 2 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST : R/WTC/SS; bitpos: [3]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH5 trigger status. + * Represents LEDC_task_gamma_restart_ch5 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5428,7 +5896,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_S 3 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST : R/WTC/SS; bitpos: [4]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH0 trigger status. + * Represents LEDC_task_gamma_pause_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5437,7 +5905,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_S 4 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST : R/WTC/SS; bitpos: [5]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH1 trigger status. + * Represents LEDC_task_gamma_pause_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5446,7 +5914,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_S 5 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST : R/WTC/SS; bitpos: [6]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH2 trigger status. + * Represents LEDC_task_gamma_pause_ch2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5455,7 +5923,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_S 6 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST : R/WTC/SS; bitpos: [7]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH3 trigger status. + * Represents LEDC_task_gamma_pause_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5464,7 +5932,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_S 7 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST : R/WTC/SS; bitpos: [8]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH4 trigger status. + * Represents LEDC_task_gamma_pause_ch4 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5473,7 +5941,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_S 8 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST : R/WTC/SS; bitpos: [9]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH5 trigger status. + * Represents LEDC_task_gamma_pause_ch5 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5482,7 +5950,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_S 9 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST : R/WTC/SS; bitpos: [10]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH0 trigger status. + * Represents LEDC_task_gamma_resume_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5491,7 +5959,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_S 10 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST : R/WTC/SS; bitpos: [11]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH1 trigger status. + * Represents LEDC_task_gamma_resume_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5500,7 +5968,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_S 11 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST : R/WTC/SS; bitpos: [12]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH2 trigger status. + * Represents LEDC_task_gamma_resume_ch2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5509,7 +5977,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_S 12 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST : R/WTC/SS; bitpos: [13]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH3 trigger status. + * Represents LEDC_task_gamma_resume_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5518,7 +5986,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_S 13 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST : R/WTC/SS; bitpos: [14]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH4 trigger status. + * Represents LEDC_task_gamma_resume_ch4 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5527,7 +5995,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_S 14 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST : R/WTC/SS; bitpos: [15]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH5 trigger status. + * Represents LEDC_task_gamma_resume_ch5 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5536,7 +6004,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_S 15 /** SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST : R/WTC/SS; bitpos: [16]; default: 0; - * Represents TG0_TASK_CNT_START_TIMER0 trigger status. + * Represents TG0_task_cnt_start_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5545,7 +6013,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_S 16 /** SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST : R/WTC/SS; bitpos: [17]; default: 0; - * Represents TG0_TASK_ALARM_START_TIMER0 trigger status. + * Represents TG0_task_alarm_start_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5554,7 +6022,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_S 17 /** SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST : R/WTC/SS; bitpos: [18]; default: 0; - * Represents TG0_TASK_CNT_STOP_TIMER0 trigger status. + * Represents TG0_task_cnt_stop_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5563,7 +6031,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_S 18 /** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST : R/WTC/SS; bitpos: [19]; default: 0; - * Represents TG0_TASK_CNT_RELOAD_TIMER0 trigger status. + * Represents TG0_task_cnt_reload_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5572,7 +6040,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_S 19 /** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST : R/WTC/SS; bitpos: [20]; default: 0; - * Represents TG0_TASK_CNT_CAP_TIMER0 trigger status. + * Represents TG0_task_cnt_cap_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5581,7 +6049,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_S 20 /** SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST : R/WTC/SS; bitpos: [21]; default: 0; - * Represents TG0_TASK_CNT_START_TIMER1 trigger status. + * Represents TG0_task_cnt_start_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5590,7 +6058,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_S 21 /** SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST : R/WTC/SS; bitpos: [22]; default: 0; - * Represents TG0_TASK_ALARM_START_TIMER1 trigger status. + * Represents TG0_task_alarm_start_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5599,7 +6067,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_S 22 /** SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST : R/WTC/SS; bitpos: [23]; default: 0; - * Represents TG0_TASK_CNT_STOP_TIMER1 trigger status. + * Represents TG0_task_cnt_stop_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5608,7 +6076,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_S 23 /** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST : R/WTC/SS; bitpos: [24]; default: 0; - * Represents TG0_TASK_CNT_RELOAD_TIMER1 trigger status. + * Represents TG0_task_cnt_reload_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5617,7 +6085,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_S 24 /** SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST : R/WTC/SS; bitpos: [25]; default: 0; - * Represents TG0_TASK_CNT_CAP_TIMER1 trigger status. + * Represents TG0_task_cnt_cap_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5626,7 +6094,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_S 25 /** SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST : R/WTC/SS; bitpos: [26]; default: 0; - * Represents TG1_TASK_CNT_START_TIMER0 trigger status. + * Represents TG1_task_cnt_start_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5635,7 +6103,7 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_S 26 /** SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST : R/WTC/SS; bitpos: [27]; default: 0; - * Represents TG1_TASK_ALARM_START_TIMER0 trigger status. + * Represents TG1_task_alarm_start_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5644,7 +6112,7 @@ extern "C" { #define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_S 27 /** SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST : R/WTC/SS; bitpos: [28]; default: 0; - * Represents TG1_TASK_CNT_STOP_TIMER0 trigger status. + * Represents TG1_task_cnt_stop_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5653,7 +6121,7 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_S 28 /** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST : R/WTC/SS; bitpos: [29]; default: 0; - * Represents TG1_TASK_CNT_RELOAD_TIMER0 trigger status. + * Represents TG1_task_cnt_reload_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5662,7 +6130,7 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_S 29 /** SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST : R/WTC/SS; bitpos: [30]; default: 0; - * Represents TG1_TASK_CNT_CAP_TIMER0 trigger status. + * Represents TG1_task_cnt_cap_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5671,7 +6139,7 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_S 30 /** SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST : R/WTC/SS; bitpos: [31]; default: 0; - * Represents TG1_TASK_CNT_START_TIMER1 trigger status. + * Represents TG1_task_cnt_start_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5681,12 +6149,12 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_S 31 /** SOC_ETM_TASK_ST2_CLR_REG register - * Task trigger status clear register + * Tasks trigger status clear register */ #define SOC_ETM_TASK_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1dc) /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR (BIT(0)) @@ -5694,8 +6162,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_S 0 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR (BIT(1)) @@ -5703,8 +6171,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_S 1 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR (BIT(2)) @@ -5712,8 +6180,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_S 2 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR (BIT(3)) @@ -5721,8 +6189,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_S 3 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR (BIT(4)) @@ -5730,8 +6198,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_S 4 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR (BIT(5)) @@ -5739,8 +6207,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_S 5 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR (BIT(6)) @@ -5748,8 +6216,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_S 6 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR (BIT(7)) @@ -5757,8 +6225,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_S 7 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR (BIT(8)) @@ -5766,8 +6234,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_S 8 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR (BIT(9)) @@ -5775,8 +6243,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_S 9 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR (BIT(10)) @@ -5784,8 +6252,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_S 10 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR (BIT(11)) @@ -5793,8 +6261,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_S 11 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR (BIT(12)) @@ -5802,8 +6270,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_S 12 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR (BIT(13)) @@ -5811,8 +6279,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_S 13 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR (BIT(14)) @@ -5820,8 +6288,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_S 14 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR (BIT(15)) @@ -5829,8 +6297,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_S 15 /** SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_START_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR (BIT(16)) @@ -5838,8 +6306,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_S 16 /** SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear TG0_TASK_ALARM_START_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR (BIT(17)) @@ -5847,8 +6315,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_S 17 /** SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_STOP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR (BIT(18)) @@ -5856,8 +6324,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_S 18 /** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_RELOAD_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR (BIT(19)) @@ -5865,8 +6333,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_S 19 /** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_CAP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR (BIT(20)) @@ -5874,8 +6342,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_S 20 /** SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_START_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR (BIT(21)) @@ -5883,8 +6351,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_S 21 /** SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear TG0_TASK_ALARM_START_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR (BIT(22)) @@ -5892,8 +6360,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_S 22 /** SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_STOP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR (BIT(23)) @@ -5901,8 +6369,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_S 23 /** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_RELOAD_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR (BIT(24)) @@ -5910,8 +6378,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_S 24 /** SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_CAP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR (BIT(25)) @@ -5919,8 +6387,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_S 25 /** SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_START_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR (BIT(26)) @@ -5928,8 +6396,8 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_S 26 /** SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR : WT; bitpos: [27]; default: 0; - * Configures whether or not to clear TG1_TASK_ALARM_START_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR (BIT(27)) @@ -5937,8 +6405,8 @@ extern "C" { #define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_S 27 /** SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_STOP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR (BIT(28)) @@ -5946,8 +6414,8 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_S 28 /** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_RELOAD_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR (BIT(29)) @@ -5955,8 +6423,8 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_S 29 /** SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_CAP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR (BIT(30)) @@ -5964,8 +6432,8 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_S 30 /** SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_START_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR (BIT(31)) @@ -5974,11 +6442,11 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_S 31 /** SOC_ETM_TASK_ST3_REG register - * Task trigger status register + * Tasks trigger status register */ #define SOC_ETM_TASK_ST3_REG (DR_REG_SOC_ETM_BASE + 0x1e0) /** SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST : R/WTC/SS; bitpos: [0]; default: 0; - * Represents TG1_TASK_ALARM_START_TIMER1 trigger status. + * Represents TG1_task_alarm_start_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5987,7 +6455,7 @@ extern "C" { #define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_S 0 /** SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST : R/WTC/SS; bitpos: [1]; default: 0; - * Represents TG1_TASK_CNT_STOP_TIMER1 trigger status. + * Represents TG1_task_cnt_stop_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5996,7 +6464,7 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_S 1 /** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST : R/WTC/SS; bitpos: [2]; default: 0; - * Represents TG1_TASK_CNT_RELOAD_TIMER1 trigger status. + * Represents TG1_task_cnt_reload_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -6005,7 +6473,7 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_S 2 /** SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST : R/WTC/SS; bitpos: [3]; default: 0; - * Represents TG1_TASK_CNT_CAP_TIMER1 trigger status. + * Represents TG1_task_cnt_cap_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -6014,7 +6482,7 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_S 3 /** SOC_ETM_ADC_TASK_SAMPLE0_ST : R/WTC/SS; bitpos: [4]; default: 0; - * Represents ADC_TASK_SAMPLE0 trigger status. + * Represents ADC_task_sample0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -6022,8 +6490,17 @@ extern "C" { #define SOC_ETM_ADC_TASK_SAMPLE0_ST_M (SOC_ETM_ADC_TASK_SAMPLE0_ST_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_S) #define SOC_ETM_ADC_TASK_SAMPLE0_ST_V 0x00000001U #define SOC_ETM_ADC_TASK_SAMPLE0_ST_S 4 +/** SOC_ETM_ADC_TASK_SAMPLE1_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents ADC_task_sample1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ADC_TASK_SAMPLE1_ST (BIT(5)) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_M (SOC_ETM_ADC_TASK_SAMPLE1_ST_V << SOC_ETM_ADC_TASK_SAMPLE1_ST_S) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_S 5 /** SOC_ETM_ADC_TASK_START0_ST : R/WTC/SS; bitpos: [6]; default: 0; - * Represents ADC_TASK_START0 trigger status. + * Represents ADC_task_start0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -6032,7 +6509,7 @@ extern "C" { #define SOC_ETM_ADC_TASK_START0_ST_V 0x00000001U #define SOC_ETM_ADC_TASK_START0_ST_S 6 /** SOC_ETM_ADC_TASK_STOP0_ST : R/WTC/SS; bitpos: [7]; default: 0; - * Represents ADC_TASK_STOP0 trigger status. + * Represents ADC_task_stop0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -6040,8 +6517,44 @@ extern "C" { #define SOC_ETM_ADC_TASK_STOP0_ST_M (SOC_ETM_ADC_TASK_STOP0_ST_V << SOC_ETM_ADC_TASK_STOP0_ST_S) #define SOC_ETM_ADC_TASK_STOP0_ST_V 0x00000001U #define SOC_ETM_ADC_TASK_STOP0_ST_S 7 +/** SOC_ETM_REGDMA_TASK_START0_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents REGDMA_task_start0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START0_ST (BIT(8)) +#define SOC_ETM_REGDMA_TASK_START0_ST_M (SOC_ETM_REGDMA_TASK_START0_ST_V << SOC_ETM_REGDMA_TASK_START0_ST_S) +#define SOC_ETM_REGDMA_TASK_START0_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START0_ST_S 8 +/** SOC_ETM_REGDMA_TASK_START1_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents REGDMA_task_start1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START1_ST (BIT(9)) +#define SOC_ETM_REGDMA_TASK_START1_ST_M (SOC_ETM_REGDMA_TASK_START1_ST_V << SOC_ETM_REGDMA_TASK_START1_ST_S) +#define SOC_ETM_REGDMA_TASK_START1_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START1_ST_S 9 +/** SOC_ETM_REGDMA_TASK_START2_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents REGDMA_task_start2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START2_ST (BIT(10)) +#define SOC_ETM_REGDMA_TASK_START2_ST_M (SOC_ETM_REGDMA_TASK_START2_ST_V << SOC_ETM_REGDMA_TASK_START2_ST_S) +#define SOC_ETM_REGDMA_TASK_START2_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START2_ST_S 10 +/** SOC_ETM_REGDMA_TASK_START3_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents REGDMA_task_start3 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START3_ST (BIT(11)) +#define SOC_ETM_REGDMA_TASK_START3_ST_M (SOC_ETM_REGDMA_TASK_START3_ST_V << SOC_ETM_REGDMA_TASK_START3_ST_S) +#define SOC_ETM_REGDMA_TASK_START3_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START3_ST_S 11 /** SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST : R/WTC/SS; bitpos: [12]; default: 0; - * Represents TMPSNSR_TASK_START_SAMPLE trigger status. + * Represents TMPSNSR_task_start_sample trigger status. * 0: Not triggered * 1: Triggered */ @@ -6050,7 +6563,7 @@ extern "C" { #define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_V 0x00000001U #define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_S 12 /** SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST : R/WTC/SS; bitpos: [13]; default: 0; - * Represents TMPSNSR_TASK_STOP_SAMPLE trigger status. + * Represents TMPSNSR_task_stop_sample trigger status. * 0: Not triggered * 1: Triggered */ @@ -6059,7 +6572,7 @@ extern "C" { #define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_V 0x00000001U #define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_S 13 /** SOC_ETM_I2S0_TASK_START_RX_ST : R/WTC/SS; bitpos: [14]; default: 0; - * Represents I2S0_TASK_START_RX trigger status. + * Represents I2S0_task_start_rx trigger status. * 0: Not triggered * 1: Triggered */ @@ -6068,7 +6581,7 @@ extern "C" { #define SOC_ETM_I2S0_TASK_START_RX_ST_V 0x00000001U #define SOC_ETM_I2S0_TASK_START_RX_ST_S 14 /** SOC_ETM_I2S0_TASK_START_TX_ST : R/WTC/SS; bitpos: [15]; default: 0; - * Represents I2S0_TASK_START_TX trigger status. + * Represents I2S0_task_start_tx trigger status. * 0: Not triggered * 1: Triggered */ @@ -6077,7 +6590,7 @@ extern "C" { #define SOC_ETM_I2S0_TASK_START_TX_ST_V 0x00000001U #define SOC_ETM_I2S0_TASK_START_TX_ST_S 15 /** SOC_ETM_I2S0_TASK_STOP_RX_ST : R/WTC/SS; bitpos: [16]; default: 0; - * Represents I2S0_TASK_STOP_RX trigger status. + * Represents I2S0_task_stop_rx trigger status. * 0: Not triggered * 1: Triggered */ @@ -6086,7 +6599,7 @@ extern "C" { #define SOC_ETM_I2S0_TASK_STOP_RX_ST_V 0x00000001U #define SOC_ETM_I2S0_TASK_STOP_RX_ST_S 16 /** SOC_ETM_I2S0_TASK_STOP_TX_ST : R/WTC/SS; bitpos: [17]; default: 0; - * Represents I2S0_TASK_STOP_TX trigger status. + * Represents I2S0_task_stop_tx trigger status. * 0: Not triggered * 1: Triggered */ @@ -6094,8 +6607,98 @@ extern "C" { #define SOC_ETM_I2S0_TASK_STOP_TX_ST_M (SOC_ETM_I2S0_TASK_STOP_TX_ST_V << SOC_ETM_I2S0_TASK_STOP_TX_ST_S) #define SOC_ETM_I2S0_TASK_STOP_TX_ST_V 0x00000001U #define SOC_ETM_I2S0_TASK_STOP_TX_ST_S 17 +/** SOC_ETM_I2S1_TASK_START_RX_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents I2S1_task_start_rx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_TASK_START_RX_ST (BIT(18)) +#define SOC_ETM_I2S1_TASK_START_RX_ST_M (SOC_ETM_I2S1_TASK_START_RX_ST_V << SOC_ETM_I2S1_TASK_START_RX_ST_S) +#define SOC_ETM_I2S1_TASK_START_RX_ST_V 0x00000001U +#define SOC_ETM_I2S1_TASK_START_RX_ST_S 18 +/** SOC_ETM_I2S1_TASK_START_TX_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents I2S1_task_start_tx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_TASK_START_TX_ST (BIT(19)) +#define SOC_ETM_I2S1_TASK_START_TX_ST_M (SOC_ETM_I2S1_TASK_START_TX_ST_V << SOC_ETM_I2S1_TASK_START_TX_ST_S) +#define SOC_ETM_I2S1_TASK_START_TX_ST_V 0x00000001U +#define SOC_ETM_I2S1_TASK_START_TX_ST_S 19 +/** SOC_ETM_I2S1_TASK_STOP_RX_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents I2S1_task_stop_rx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_TASK_STOP_RX_ST (BIT(20)) +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_M (SOC_ETM_I2S1_TASK_STOP_RX_ST_V << SOC_ETM_I2S1_TASK_STOP_RX_ST_S) +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_V 0x00000001U +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_S 20 +/** SOC_ETM_I2S1_TASK_STOP_TX_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents I2S1_task_stop_tx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_TASK_STOP_TX_ST (BIT(21)) +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_M (SOC_ETM_I2S1_TASK_STOP_TX_ST_V << SOC_ETM_I2S1_TASK_STOP_TX_ST_S) +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_V 0x00000001U +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_S 21 +/** SOC_ETM_ULP_TASK_WAKEUP_CPU_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents ULP_task_wakeup_cpu trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST (BIT(22)) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_M (SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_V << SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_S) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_V 0x00000001U +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_S 22 +/** SOC_ETM_ULP_TASK_INT_CPU_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents ULP_task_int_cpu trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ULP_TASK_INT_CPU_ST (BIT(23)) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_M (SOC_ETM_ULP_TASK_INT_CPU_ST_V << SOC_ETM_ULP_TASK_INT_CPU_ST_S) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_V 0x00000001U +#define SOC_ETM_ULP_TASK_INT_CPU_ST_S 23 +/** SOC_ETM_RTC_TASK_START_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents RTC_task_start trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_RTC_TASK_START_ST (BIT(24)) +#define SOC_ETM_RTC_TASK_START_ST_M (SOC_ETM_RTC_TASK_START_ST_V << SOC_ETM_RTC_TASK_START_ST_S) +#define SOC_ETM_RTC_TASK_START_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_START_ST_S 24 +/** SOC_ETM_RTC_TASK_STOP_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents RTC_task_stop trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_RTC_TASK_STOP_ST (BIT(25)) +#define SOC_ETM_RTC_TASK_STOP_ST_M (SOC_ETM_RTC_TASK_STOP_ST_V << SOC_ETM_RTC_TASK_STOP_ST_S) +#define SOC_ETM_RTC_TASK_STOP_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_STOP_ST_S 25 +/** SOC_ETM_RTC_TASK_CLR_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents RTC_task_clr trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_RTC_TASK_CLR_ST (BIT(26)) +#define SOC_ETM_RTC_TASK_CLR_ST_M (SOC_ETM_RTC_TASK_CLR_ST_V << SOC_ETM_RTC_TASK_CLR_ST_S) +#define SOC_ETM_RTC_TASK_CLR_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_CLR_ST_S 26 +/** SOC_ETM_RTC_TASK_TRIGGERFLW_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents RTC_task_triggerflw trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST (BIT(27)) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_M (SOC_ETM_RTC_TASK_TRIGGERFLW_ST_V << SOC_ETM_RTC_TASK_TRIGGERFLW_ST_S) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_S 27 /** SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST : R/WTC/SS; bitpos: [28]; default: 0; - * Represents GDMA_AHB_TASK_IN_START_CH0 trigger status. + * Represents GDMA_AHB_task_in_start_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -6104,7 +6707,7 @@ extern "C" { #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_S 28 /** SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST : R/WTC/SS; bitpos: [29]; default: 0; - * Represents GDMA_AHB_TASK_IN_START_CH1 trigger status. + * Represents GDMA_AHB_task_in_start_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -6112,8 +6715,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_M (SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_V << SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_S) #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_S 29 +/** SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents GDMA_AHB_task_in_start_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST (BIT(30)) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_M (SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_V << SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_S 30 /** SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST : R/WTC/SS; bitpos: [31]; default: 0; - * Represents GDMA_AHB_TASK_OUT_START_CH0 trigger status. + * Represents GDMA_AHB_task_out_start_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -6123,12 +6735,12 @@ extern "C" { #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_S 31 /** SOC_ETM_TASK_ST3_CLR_REG register - * Task trigger status clear register + * Tasks trigger status clear register */ #define SOC_ETM_TASK_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1e4) /** SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear TG1_TASK_ALARM_START_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR (BIT(0)) @@ -6136,8 +6748,8 @@ extern "C" { #define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_S 0 /** SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_STOP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR (BIT(1)) @@ -6145,8 +6757,8 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_S 1 /** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_RELOAD_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR (BIT(2)) @@ -6154,8 +6766,8 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_S 2 /** SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_CAP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR (BIT(3)) @@ -6163,17 +6775,26 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_S 3 /** SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear ADC_TASK_SAMPLE0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_task_sample0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR (BIT(4)) #define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_M (SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S) #define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S 4 +/** SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ADC_task_sample1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR (BIT(5)) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_M (SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_V << SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_S) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_S 5 /** SOC_ETM_ADC_TASK_START0_ST_CLR : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear ADC_TASK_START0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_task_start0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_TASK_START0_ST_CLR (BIT(6)) @@ -6181,17 +6802,53 @@ extern "C" { #define SOC_ETM_ADC_TASK_START0_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_TASK_START0_ST_CLR_S 6 /** SOC_ETM_ADC_TASK_STOP0_ST_CLR : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear ADC_TASK_STOP0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_task_stop0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_TASK_STOP0_ST_CLR (BIT(7)) #define SOC_ETM_ADC_TASK_STOP0_ST_CLR_M (SOC_ETM_ADC_TASK_STOP0_ST_CLR_V << SOC_ETM_ADC_TASK_STOP0_ST_CLR_S) #define SOC_ETM_ADC_TASK_STOP0_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_TASK_STOP0_ST_CLR_S 7 +/** SOC_ETM_REGDMA_TASK_START0_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear REGDMA_task_start0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR (BIT(8)) +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_M (SOC_ETM_REGDMA_TASK_START0_ST_CLR_V << SOC_ETM_REGDMA_TASK_START0_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_S 8 +/** SOC_ETM_REGDMA_TASK_START1_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear REGDMA_task_start1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR (BIT(9)) +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_M (SOC_ETM_REGDMA_TASK_START1_ST_CLR_V << SOC_ETM_REGDMA_TASK_START1_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_S 9 +/** SOC_ETM_REGDMA_TASK_START2_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear REGDMA_task_start2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR (BIT(10)) +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_M (SOC_ETM_REGDMA_TASK_START2_ST_CLR_V << SOC_ETM_REGDMA_TASK_START2_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_S 10 +/** SOC_ETM_REGDMA_TASK_START3_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear REGDMA_task_start3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR (BIT(11)) +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_M (SOC_ETM_REGDMA_TASK_START3_ST_CLR_V << SOC_ETM_REGDMA_TASK_START3_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_S 11 /** SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear TMPSNSR_TASK_START_SAMPLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TMPSNSR_task_start_sample trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR (BIT(12)) @@ -6199,8 +6856,8 @@ extern "C" { #define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_V 0x00000001U #define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_S 12 /** SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear TMPSNSR_TASK_STOP_SAMPLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TMPSNSR_task_stop_sample trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR (BIT(13)) @@ -6208,8 +6865,8 @@ extern "C" { #define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_V 0x00000001U #define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_S 13 /** SOC_ETM_I2S0_TASK_START_RX_ST_CLR : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear I2S0_TASK_START_RX trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_task_start_rx trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_I2S0_TASK_START_RX_ST_CLR (BIT(14)) @@ -6217,8 +6874,8 @@ extern "C" { #define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_V 0x00000001U #define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_S 14 /** SOC_ETM_I2S0_TASK_START_TX_ST_CLR : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear I2S0_TASK_START_TX trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_task_start_tx trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_I2S0_TASK_START_TX_ST_CLR (BIT(15)) @@ -6226,8 +6883,8 @@ extern "C" { #define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_V 0x00000001U #define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_S 15 /** SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear I2S0_TASK_STOP_RX trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_task_stop_rx trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR (BIT(16)) @@ -6235,17 +6892,107 @@ extern "C" { #define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_V 0x00000001U #define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_S 16 /** SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear I2S0_TASK_STOP_TX trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_task_stop_tx trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR (BIT(17)) #define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_M (SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_V << SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_S) #define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_V 0x00000001U #define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_S 17 +/** SOC_ETM_I2S1_TASK_START_RX_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear I2S1_task_start_rx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR (BIT(18)) +#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR_M (SOC_ETM_I2S1_TASK_START_RX_ST_CLR_V << SOC_ETM_I2S1_TASK_START_RX_ST_CLR_S) +#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR_S 18 +/** SOC_ETM_I2S1_TASK_START_TX_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear I2S1_task_start_tx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR (BIT(19)) +#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR_M (SOC_ETM_I2S1_TASK_START_TX_ST_CLR_V << SOC_ETM_I2S1_TASK_START_TX_ST_CLR_S) +#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR_S 19 +/** SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear I2S1_task_stop_rx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR (BIT(20)) +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_M (SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_V << SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_S) +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_S 20 +/** SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear I2S1_task_stop_tx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR (BIT(21)) +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_M (SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_V << SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_S) +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_S 21 +/** SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear ULP_task_wakeup_cpu trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR (BIT(22)) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_M (SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_V << SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_S) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_S 22 +/** SOC_ETM_ULP_TASK_INT_CPU_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear ULP_task_int_cpu trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR (BIT(23)) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_M (SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_V << SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_S) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_S 23 +/** SOC_ETM_RTC_TASK_START_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear RTC_task_start trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_RTC_TASK_START_ST_CLR (BIT(24)) +#define SOC_ETM_RTC_TASK_START_ST_CLR_M (SOC_ETM_RTC_TASK_START_ST_CLR_V << SOC_ETM_RTC_TASK_START_ST_CLR_S) +#define SOC_ETM_RTC_TASK_START_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_START_ST_CLR_S 24 +/** SOC_ETM_RTC_TASK_STOP_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear RTC_task_stop trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_RTC_TASK_STOP_ST_CLR (BIT(25)) +#define SOC_ETM_RTC_TASK_STOP_ST_CLR_M (SOC_ETM_RTC_TASK_STOP_ST_CLR_V << SOC_ETM_RTC_TASK_STOP_ST_CLR_S) +#define SOC_ETM_RTC_TASK_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_STOP_ST_CLR_S 25 +/** SOC_ETM_RTC_TASK_CLR_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear RTC_task_clr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_RTC_TASK_CLR_ST_CLR (BIT(26)) +#define SOC_ETM_RTC_TASK_CLR_ST_CLR_M (SOC_ETM_RTC_TASK_CLR_ST_CLR_V << SOC_ETM_RTC_TASK_CLR_ST_CLR_S) +#define SOC_ETM_RTC_TASK_CLR_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_CLR_ST_CLR_S 26 +/** SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear RTC_task_triggerflw trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR (BIT(27)) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_M (SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_V << SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_S) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_S 27 /** SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_CLR : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear GDMA_AHB_TASK_IN_START_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_task_in_start_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_CLR (BIT(28)) @@ -6253,17 +7000,26 @@ extern "C" { #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_CLR_S 28 /** SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear GDMA_AHB_TASK_IN_START_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_task_in_start_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR (BIT(29)) #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR_S 29 +/** SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_in_start_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR (BIT(30)) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR_S 30 /** SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_CLR : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear GDMA_AHB_TASK_OUT_START_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_task_out_start_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_CLR (BIT(31)) @@ -6272,11 +7028,11 @@ extern "C" { #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_CLR_S 31 /** SOC_ETM_TASK_ST4_REG register - * Task trigger status register + * Tasks trigger status register */ #define SOC_ETM_TASK_ST4_REG (DR_REG_SOC_ETM_BASE + 0x1e8) /** SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST : R/WTC/SS; bitpos: [0]; default: 0; - * Represents GDMA_AHB_TASK_OUT_START_CH1 trigger status. + * Represents GDMA_AHB_task_out_start_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -6284,8 +7040,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_M (SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_V << SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_S) #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_S 0 +/** SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GDMA_AHB_task_out_start_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST (BIT(1)) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_M (SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_V << SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_S 1 /** SOC_ETM_PMU_TASK_SLEEP_REQ_ST : R/WTC/SS; bitpos: [2]; default: 0; - * Represents PMU_TASK_SLEEP_REQ trigger status. + * Represents PMU_task_sleep_req trigger status. * 0: Not triggered * 1: Triggered */ @@ -6295,21 +7060,30 @@ extern "C" { #define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_S 2 /** SOC_ETM_TASK_ST4_CLR_REG register - * Task trigger status clear register + * Tasks trigger status clear register */ #define SOC_ETM_TASK_ST4_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ec) /** SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear GDMA_AHB_TASK_OUT_START_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_task_out_start_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR (BIT(0)) #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR_S 0 +/** SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_out_start_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR (BIT(1)) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR_S 1 /** SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear PMU_TASK_SLEEP_REQ trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear PMU_task_sleep_req trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR (BIT(2)) @@ -6332,11 +7106,11 @@ extern "C" { #define SOC_ETM_CLK_EN_S 0 /** SOC_ETM_DATE_REG register - * Version control register + * ETM date register */ #define SOC_ETM_DATE_REG (DR_REG_SOC_ETM_BASE + 0x1f4) /** SOC_ETM_DATE : R/W; bitpos: [27:0]; default: 36737361; - * Version control register. + * Configures the version. */ #define SOC_ETM_DATE 0x0FFFFFFFU #define SOC_ETM_DATE_M (SOC_ETM_DATE_V << SOC_ETM_DATE_S) diff --git a/components/soc/esp32c61/register/soc/soc_etm_struct.h b/components/soc/esp32c61/register/soc/soc_etm_struct.h index 397d823bd9..42dca6dc89 100644 --- a/components/soc/esp32c61/register/soc/soc_etm_struct.h +++ b/components/soc/esp32c61/register/soc/soc_etm_struct.h @@ -1,7 +1,7 @@ /** - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -16,194 +16,194 @@ extern "C" { */ typedef union { struct { - /** ch_enabled0 : R/WTC/WS; bitpos: [0]; default: 0; - * Represents channel0 enable status. + /** ch_enabled0 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch0 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled0:1; - /** ch_enabled1 : R/WTC/WS; bitpos: [1]; default: 0; - * Represents channel1 enable status. + /** ch_enabled1 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch1 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled1:1; - /** ch_enabled2 : R/WTC/WS; bitpos: [2]; default: 0; - * Represents channel2 enable status. + /** ch_enabled2 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch2 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled2:1; - /** ch_enabled3 : R/WTC/WS; bitpos: [3]; default: 0; - * Represents channel3 enable status. + /** ch_enabled3 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch3 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled3:1; - /** ch_enabled4 : R/WTC/WS; bitpos: [4]; default: 0; - * Represents channel4 enable status. + /** ch_enabled4 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch4 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled4:1; - /** ch_enabled5 : R/WTC/WS; bitpos: [5]; default: 0; - * Represents channel5 enable status. + /** ch_enabled5 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch5 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled5:1; - /** ch_enabled6 : R/WTC/WS; bitpos: [6]; default: 0; - * Represents channel6 enable status. + /** ch_enabled6 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch6 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled6:1; - /** ch_enabled7 : R/WTC/WS; bitpos: [7]; default: 0; - * Represents channel7 enable status. + /** ch_enabled7 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch7 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled7:1; - /** ch_enabled8 : R/WTC/WS; bitpos: [8]; default: 0; - * Represents channel8 enable status. + /** ch_enabled8 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch8 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled8:1; - /** ch_enabled9 : R/WTC/WS; bitpos: [9]; default: 0; - * Represents channel9 enable status. + /** ch_enabled9 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch9 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled9:1; - /** ch_enabled10 : R/WTC/WS; bitpos: [10]; default: 0; - * Represents channel10 enable status. + /** ch_enabled10 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch10 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled10:1; - /** ch_enabled11 : R/WTC/WS; bitpos: [11]; default: 0; - * Represents channel11 enable status. + /** ch_enabled11 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch11 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled11:1; - /** ch_enabled12 : R/WTC/WS; bitpos: [12]; default: 0; - * Represents channel12 enable status. + /** ch_enabled12 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch12 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled12:1; - /** ch_enabled13 : R/WTC/WS; bitpos: [13]; default: 0; - * Represents channel13 enable status. + /** ch_enabled13 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch13 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled13:1; - /** ch_enabled14 : R/WTC/WS; bitpos: [14]; default: 0; - * Represents channel14 enable status. + /** ch_enabled14 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch14 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled14:1; - /** ch_enabled15 : R/WTC/WS; bitpos: [15]; default: 0; - * Represents channel15 enable status. + /** ch_enabled15 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch15 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled15:1; - /** ch_enabled16 : R/WTC/WS; bitpos: [16]; default: 0; - * Represents channel16 enable status. + /** ch_enabled16 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch16 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled16:1; - /** ch_enabled17 : R/WTC/WS; bitpos: [17]; default: 0; - * Represents channel17 enable status. + /** ch_enabled17 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch17 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled17:1; - /** ch_enabled18 : R/WTC/WS; bitpos: [18]; default: 0; - * Represents channel18 enable status. + /** ch_enabled18 : R/WTC/WTS; bitpos: [18]; default: 0; + * Represents ch18 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled18:1; - /** ch_enabled19 : R/WTC/WS; bitpos: [19]; default: 0; - * Represents channel19 enable status. + /** ch_enabled19 : R/WTC/WTS; bitpos: [19]; default: 0; + * Represents ch19 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled19:1; - /** ch_enabled20 : R/WTC/WS; bitpos: [20]; default: 0; - * Represents channel20 enable status. + /** ch_enabled20 : R/WTC/WTS; bitpos: [20]; default: 0; + * Represents ch20 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled20:1; - /** ch_enabled21 : R/WTC/WS; bitpos: [21]; default: 0; - * Represents channel21 enable status. + /** ch_enabled21 : R/WTC/WTS; bitpos: [21]; default: 0; + * Represents ch21 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled21:1; - /** ch_enabled22 : R/WTC/WS; bitpos: [22]; default: 0; - * Represents channel22 enable status. + /** ch_enabled22 : R/WTC/WTS; bitpos: [22]; default: 0; + * Represents ch22 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled22:1; - /** ch_enabled23 : R/WTC/WS; bitpos: [23]; default: 0; - * Represents channel23 enable status. + /** ch_enabled23 : R/WTC/WTS; bitpos: [23]; default: 0; + * Represents ch23 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled23:1; - /** ch_enabled24 : R/WTC/WS; bitpos: [24]; default: 0; - * Represents channel24 enable status. + /** ch_enabled24 : R/WTC/WTS; bitpos: [24]; default: 0; + * Represents ch24 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled24:1; - /** ch_enabled25 : R/WTC/WS; bitpos: [25]; default: 0; - * Represents channel25 enable status. + /** ch_enabled25 : R/WTC/WTS; bitpos: [25]; default: 0; + * Represents ch25 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled25:1; - /** ch_enabled26 : R/WTC/WS; bitpos: [26]; default: 0; - * Represents channel26 enable status. + /** ch_enabled26 : R/WTC/WTS; bitpos: [26]; default: 0; + * Represents ch26 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled26:1; - /** ch_enabled27 : R/WTC/WS; bitpos: [27]; default: 0; - * Represents channel27 enable status. + /** ch_enabled27 : R/WTC/WTS; bitpos: [27]; default: 0; + * Represents ch27 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled27:1; - /** ch_enabled28 : R/WTC/WS; bitpos: [28]; default: 0; - * Represents channel28 enable status. + /** ch_enabled28 : R/WTC/WTS; bitpos: [28]; default: 0; + * Represents ch28 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled28:1; - /** ch_enabled29 : R/WTC/WS; bitpos: [29]; default: 0; - * Represents channel29 enable status. + /** ch_enabled29 : R/WTC/WTS; bitpos: [29]; default: 0; + * Represents ch29 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled29:1; - /** ch_enabled30 : R/WTC/WS; bitpos: [30]; default: 0; - * Represents channel30 enable status. + /** ch_enabled30 : R/WTC/WTS; bitpos: [30]; default: 0; + * Represents ch30 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled30:1; - /** ch_enabled31 : R/WTC/WS; bitpos: [31]; default: 0; - * Represents channel31 enable status. + /** ch_enabled31 : R/WTC/WTS; bitpos: [31]; default: 0; + * Represents ch31 enable status. * 0: Disable * 1: Enable */ @@ -217,110 +217,110 @@ typedef union { */ typedef union { struct { - /** ch_enabled32 : R/WTC/WS; bitpos: [0]; default: 0; - * Represents channel32 enable status. + /** ch_enabled32 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch32 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled32:1; - /** ch_enabled33 : R/WTC/WS; bitpos: [1]; default: 0; - * Represents channel33 enable status. + /** ch_enabled33 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch33 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled33:1; - /** ch_enabled34 : R/WTC/WS; bitpos: [2]; default: 0; - * Represents channel34 enable status. + /** ch_enabled34 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch34 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled34:1; - /** ch_enabled35 : R/WTC/WS; bitpos: [3]; default: 0; - * Represents channel35 enable status. + /** ch_enabled35 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch35 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled35:1; - /** ch_enabled36 : R/WTC/WS; bitpos: [4]; default: 0; - * Represents channel36 enable status. + /** ch_enabled36 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch36 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled36:1; - /** ch_enabled37 : R/WTC/WS; bitpos: [5]; default: 0; - * Represents channel37 enable status. + /** ch_enabled37 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch37 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled37:1; - /** ch_enabled38 : R/WTC/WS; bitpos: [6]; default: 0; - * Represents channel38 enable status. + /** ch_enabled38 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch38 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled38:1; - /** ch_enabled39 : R/WTC/WS; bitpos: [7]; default: 0; - * Represents channel39 enable status. + /** ch_enabled39 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch39 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled39:1; - /** ch_enabled40 : R/WTC/WS; bitpos: [8]; default: 0; - * Represents channel40 enable status. + /** ch_enabled40 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch40 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled40:1; - /** ch_enabled41 : R/WTC/WS; bitpos: [9]; default: 0; - * Represents channel41 enable status. + /** ch_enabled41 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch41 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled41:1; - /** ch_enabled42 : R/WTC/WS; bitpos: [10]; default: 0; - * Represents channel42 enable status. + /** ch_enabled42 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch42 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled42:1; - /** ch_enabled43 : R/WTC/WS; bitpos: [11]; default: 0; - * Represents channel43 enable status. + /** ch_enabled43 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch43 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled43:1; - /** ch_enabled44 : R/WTC/WS; bitpos: [12]; default: 0; - * Represents channel44 enable status. + /** ch_enabled44 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch44 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled44:1; - /** ch_enabled45 : R/WTC/WS; bitpos: [13]; default: 0; - * Represents channel45 enable status. + /** ch_enabled45 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch45 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled45:1; - /** ch_enabled46 : R/WTC/WS; bitpos: [14]; default: 0; - * Represents channel46 enable status. + /** ch_enabled46 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch46 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled46:1; - /** ch_enabled47 : R/WTC/WS; bitpos: [15]; default: 0; - * Represents channel47 enable status. + /** ch_enabled47 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch47 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled47:1; - /** ch_enabled48 : R/WTC/WS; bitpos: [16]; default: 0; - * Represents channel48 enable status. + /** ch_enabled48 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch48 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled48:1; - /** ch_enabled49 : R/WTC/WS; bitpos: [17]; default: 0; - * Represents channel49 enable status. + /** ch_enabled49 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch49 enable status. * 0: Disable * 1: Enable */ @@ -331,187 +331,198 @@ typedef union { } soc_etm_ch_ena_ad1_reg_t; /** Type of evt_st0 register - * Event trigger status register + * Events trigger status register */ typedef union { struct { /** gpio_evt_ch0_rise_edge_st : R/WTC/SS; bitpos: [0]; default: 0; - * Represents GPIO_EVT_CH0_RISE_EDGE trigger status. + * Represents GPIO_evt_ch0_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch0_rise_edge_st:1; /** gpio_evt_ch1_rise_edge_st : R/WTC/SS; bitpos: [1]; default: 0; - * Represents GPIO_EVT_CH1_RISE_EDGE trigger status. + * Represents GPIO_evt_ch1_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch1_rise_edge_st:1; /** gpio_evt_ch2_rise_edge_st : R/WTC/SS; bitpos: [2]; default: 0; - * Represents GPIO_EVT_CH2_RISE_EDGE trigger status. + * Represents GPIO_evt_ch2_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch2_rise_edge_st:1; /** gpio_evt_ch3_rise_edge_st : R/WTC/SS; bitpos: [3]; default: 0; - * Represents GPIO_EVT_CH3_RISE_EDGE trigger status. + * Represents GPIO_evt_ch3_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch3_rise_edge_st:1; /** gpio_evt_ch4_rise_edge_st : R/WTC/SS; bitpos: [4]; default: 0; - * Represents GPIO_EVT_CH4_RISE_EDGE trigger status. + * Represents GPIO_evt_ch4_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch4_rise_edge_st:1; /** gpio_evt_ch5_rise_edge_st : R/WTC/SS; bitpos: [5]; default: 0; - * Represents GPIO_EVT_CH5_RISE_EDGE trigger status. + * Represents GPIO_evt_ch5_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch5_rise_edge_st:1; /** gpio_evt_ch6_rise_edge_st : R/WTC/SS; bitpos: [6]; default: 0; - * Represents GPIO_EVT_CH6_RISE_EDGE trigger status. + * Represents GPIO_evt_ch6_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch6_rise_edge_st:1; /** gpio_evt_ch7_rise_edge_st : R/WTC/SS; bitpos: [7]; default: 0; - * Represents GPIO_EVT_CH7_RISE_EDGE trigger status. + * Represents GPIO_evt_ch7_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch7_rise_edge_st:1; /** gpio_evt_ch0_fall_edge_st : R/WTC/SS; bitpos: [8]; default: 0; - * Represents GPIO_EVT_CH0_FALL_EDGE trigger status. + * Represents GPIO_evt_ch0_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch0_fall_edge_st:1; /** gpio_evt_ch1_fall_edge_st : R/WTC/SS; bitpos: [9]; default: 0; - * Represents GPIO_EVT_CH1_FALL_EDGE trigger status. + * Represents GPIO_evt_ch1_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch1_fall_edge_st:1; /** gpio_evt_ch2_fall_edge_st : R/WTC/SS; bitpos: [10]; default: 0; - * Represents GPIO_EVT_CH2_FALL_EDGE trigger status. + * Represents GPIO_evt_ch2_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch2_fall_edge_st:1; /** gpio_evt_ch3_fall_edge_st : R/WTC/SS; bitpos: [11]; default: 0; - * Represents GPIO_EVT_CH3_FALL_EDGE trigger status. + * Represents GPIO_evt_ch3_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch3_fall_edge_st:1; /** gpio_evt_ch4_fall_edge_st : R/WTC/SS; bitpos: [12]; default: 0; - * Represents GPIO_EVT_CH4_FALL_EDGE trigger status. + * Represents GPIO_evt_ch4_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch4_fall_edge_st:1; /** gpio_evt_ch5_fall_edge_st : R/WTC/SS; bitpos: [13]; default: 0; - * Represents GPIO_EVT_CH5_FALL_EDGE trigger status. + * Represents GPIO_evt_ch5_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch5_fall_edge_st:1; /** gpio_evt_ch6_fall_edge_st : R/WTC/SS; bitpos: [14]; default: 0; - * Represents GPIO_EVT_CH6_FALL_EDGE trigger status. + * Represents GPIO_evt_ch6_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch6_fall_edge_st:1; /** gpio_evt_ch7_fall_edge_st : R/WTC/SS; bitpos: [15]; default: 0; - * Represents GPIO_EVT_CH7_FALL_EDGE trigger status. + * Represents GPIO_evt_ch7_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch7_fall_edge_st:1; /** gpio_evt_ch0_any_edge_st : R/WTC/SS; bitpos: [16]; default: 0; - * Represents GPIO_EVT_CH0_ANY_EDGE trigger status. + * Represents GPIO_evt_ch0_any_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch0_any_edge_st:1; /** gpio_evt_ch1_any_edge_st : R/WTC/SS; bitpos: [17]; default: 0; - * Represents GPIO_EVT_CH1_ANY_EDGE trigger status. + * Represents GPIO_evt_ch1_any_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch1_any_edge_st:1; /** gpio_evt_ch2_any_edge_st : R/WTC/SS; bitpos: [18]; default: 0; - * Represents GPIO_EVT_CH2_ANY_EDGE trigger status. + * Represents GPIO_evt_ch2_any_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch2_any_edge_st:1; /** gpio_evt_ch3_any_edge_st : R/WTC/SS; bitpos: [19]; default: 0; - * Represents GPIO_EVT_CH3_ANY_EDGE trigger status. + * Represents GPIO_evt_ch3_any_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch3_any_edge_st:1; /** gpio_evt_ch4_any_edge_st : R/WTC/SS; bitpos: [20]; default: 0; - * Represents GPIO_EVT_CH4_ANY_EDGE trigger status. + * Represents GPIO_evt_ch4_any_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch4_any_edge_st:1; /** gpio_evt_ch5_any_edge_st : R/WTC/SS; bitpos: [21]; default: 0; - * Represents GPIO_EVT_CH5_ANY_EDGE trigger status. + * Represents GPIO_evt_ch5_any_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch5_any_edge_st:1; /** gpio_evt_ch6_any_edge_st : R/WTC/SS; bitpos: [22]; default: 0; - * Represents GPIO_EVT_CH6_ANY_EDGE trigger status. + * Represents GPIO_evt_ch6_any_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch6_any_edge_st:1; /** gpio_evt_ch7_any_edge_st : R/WTC/SS; bitpos: [23]; default: 0; - * Represents GPIO_EVT_CH7_ANY_EDGE trigger status. + * Represents GPIO_evt_ch7_any_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch7_any_edge_st:1; /** gpio_evt_zero_det_pos0_st : R/WTC/SS; bitpos: [24]; default: 0; - * Represents GPIO_EVT_ZERO_DET_POS0 trigger status. + * Represents GPIO_evt_zero_det_pos0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_zero_det_pos0_st:1; /** gpio_evt_zero_det_neg0_st : R/WTC/SS; bitpos: [25]; default: 0; - * Represents GPIO_EVT_ZERO_DET_NEG0 trigger status. + * Represents GPIO_evt_zero_det_neg0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_zero_det_neg0_st:1; - uint32_t reserved_26:2; + /** gpio_evt_zero_det_pos1_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents GPIO_evt_zero_det_pos1 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gpio_evt_zero_det_pos1_st:1; + /** gpio_evt_zero_det_neg1_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents GPIO_evt_zero_det_neg1 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gpio_evt_zero_det_neg1_st:1; /** ledc_evt_duty_chng_end_ch0_st : R/WTC/SS; bitpos: [28]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH0 trigger status. + * Represents LEDC_evt_duty_chng_end_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_duty_chng_end_ch0_st:1; /** ledc_evt_duty_chng_end_ch1_st : R/WTC/SS; bitpos: [29]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH1 trigger status. + * Represents LEDC_evt_duty_chng_end_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_duty_chng_end_ch1_st:1; /** ledc_evt_duty_chng_end_ch2_st : R/WTC/SS; bitpos: [30]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH2 trigger status. + * Represents LEDC_evt_duty_chng_end_ch2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_duty_chng_end_ch2_st:1; /** ledc_evt_duty_chng_end_ch3_st : R/WTC/SS; bitpos: [31]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH3 trigger status. + * Represents LEDC_evt_duty_chng_end_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -521,297 +532,399 @@ typedef union { } soc_etm_evt_st0_reg_t; /** Type of evt_st1 register - * Event trigger status register + * Events trigger status register */ typedef union { struct { /** ledc_evt_duty_chng_end_ch4_st : R/WTC/SS; bitpos: [0]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH4 trigger status. + * Represents LEDC_evt_duty_chng_end_ch4 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_duty_chng_end_ch4_st:1; /** ledc_evt_duty_chng_end_ch5_st : R/WTC/SS; bitpos: [1]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH5 trigger status. + * Represents LEDC_evt_duty_chng_end_ch5 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_duty_chng_end_ch5_st:1; /** ledc_evt_ovf_cnt_pls_ch0_st : R/WTC/SS; bitpos: [2]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH0 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_ovf_cnt_pls_ch0_st:1; /** ledc_evt_ovf_cnt_pls_ch1_st : R/WTC/SS; bitpos: [3]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH1 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_ovf_cnt_pls_ch1_st:1; /** ledc_evt_ovf_cnt_pls_ch2_st : R/WTC/SS; bitpos: [4]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH2 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_ovf_cnt_pls_ch2_st:1; /** ledc_evt_ovf_cnt_pls_ch3_st : R/WTC/SS; bitpos: [5]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH3 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_ovf_cnt_pls_ch3_st:1; /** ledc_evt_ovf_cnt_pls_ch4_st : R/WTC/SS; bitpos: [6]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH4 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_ovf_cnt_pls_ch4_st:1; /** ledc_evt_ovf_cnt_pls_ch5_st : R/WTC/SS; bitpos: [7]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH5 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_ovf_cnt_pls_ch5_st:1; /** ledc_evt_time_ovf_timer0_st : R/WTC/SS; bitpos: [8]; default: 0; - * Represents LEDC_EVT_TIME_OVF_TIMER0 trigger status. + * Represents LEDC_evt_time_ovf_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_time_ovf_timer0_st:1; /** ledc_evt_time_ovf_timer1_st : R/WTC/SS; bitpos: [9]; default: 0; - * Represents LEDC_EVT_TIME_OVF_TIMER1 trigger status. + * Represents LEDC_evt_time_ovf_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_time_ovf_timer1_st:1; /** ledc_evt_time_ovf_timer2_st : R/WTC/SS; bitpos: [10]; default: 0; - * Represents LEDC_EVT_TIME_OVF_TIMER2 trigger status. + * Represents LEDC_evt_time_ovf_timer2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_time_ovf_timer2_st:1; /** ledc_evt_time_ovf_timer3_st : R/WTC/SS; bitpos: [11]; default: 0; - * Represents LEDC_EVT_TIME_OVF_TIMER3 trigger status. + * Represents LEDC_evt_time_ovf_timer3 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_time_ovf_timer3_st:1; /** ledc_evt_timer0_cmp_st : R/WTC/SS; bitpos: [12]; default: 0; - * Represents LEDC_EVT_TIMER0_CMP trigger status. + * Represents LEDC_evt_timer0_cmp trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_timer0_cmp_st:1; /** ledc_evt_timer1_cmp_st : R/WTC/SS; bitpos: [13]; default: 0; - * Represents LEDC_EVT_TIMER1_CMP trigger status. + * Represents LEDC_evt_timer1_cmp trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_timer1_cmp_st:1; /** ledc_evt_timer2_cmp_st : R/WTC/SS; bitpos: [14]; default: 0; - * Represents LEDC_EVT_TIMER2_CMP trigger status. + * Represents LEDC_evt_timer2_cmp trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_timer2_cmp_st:1; /** ledc_evt_timer3_cmp_st : R/WTC/SS; bitpos: [15]; default: 0; - * Represents LEDC_EVT_TIMER3_CMP trigger status. + * Represents LEDC_evt_timer3_cmp trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_timer3_cmp_st:1; /** tg0_evt_cnt_cmp_timer0_st : R/WTC/SS; bitpos: [16]; default: 0; - * Represents TG0_EVT_CNT_CMP_TIMER0 trigger status. + * Represents TG0_evt_cnt_cmp_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_evt_cnt_cmp_timer0_st:1; /** tg0_evt_cnt_cmp_timer1_st : R/WTC/SS; bitpos: [17]; default: 0; - * Represents TG0_EVT_CNT_CMP_TIMER1 trigger status. + * Represents TG0_evt_cnt_cmp_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_evt_cnt_cmp_timer1_st:1; /** tg1_evt_cnt_cmp_timer0_st : R/WTC/SS; bitpos: [18]; default: 0; - * Represents TG1_EVT_CNT_CMP_TIMER0 trigger status. + * Represents TG1_evt_cnt_cmp_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_evt_cnt_cmp_timer0_st:1; /** tg1_evt_cnt_cmp_timer1_st : R/WTC/SS; bitpos: [19]; default: 0; - * Represents TG1_EVT_CNT_CMP_TIMER1 trigger status. + * Represents TG1_evt_cnt_cmp_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_evt_cnt_cmp_timer1_st:1; /** systimer_evt_cnt_cmp0_st : R/WTC/SS; bitpos: [20]; default: 0; - * Represents SYSTIMER_EVT_CNT_CMP0 trigger status. + * Represents SYSTIMER_evt_cnt_cmp0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t systimer_evt_cnt_cmp0_st:1; /** systimer_evt_cnt_cmp1_st : R/WTC/SS; bitpos: [21]; default: 0; - * Represents SYSTIMER_EVT_CNT_CMP1 trigger status. + * Represents SYSTIMER_evt_cnt_cmp1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t systimer_evt_cnt_cmp1_st:1; /** systimer_evt_cnt_cmp2_st : R/WTC/SS; bitpos: [22]; default: 0; - * Represents SYSTIMER_EVT_CNT_CMP2 trigger status. + * Represents SYSTIMER_evt_cnt_cmp2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t systimer_evt_cnt_cmp2_st:1; /** adc_evt_conv_cmplt0_st : R/WTC/SS; bitpos: [23]; default: 0; - * Represents ADC_EVT_CONV_CMPLT0 trigger status. + * Represents ADC_evt_conv_cmplt0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_evt_conv_cmplt0_st:1; /** adc_evt_eq_above_thresh0_st : R/WTC/SS; bitpos: [24]; default: 0; - * Represents ADC_EVT_EQ_ABOVE_THRESH0 trigger status. + * Represents ADC_evt_eq_above_thresh0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_evt_eq_above_thresh0_st:1; /** adc_evt_eq_above_thresh1_st : R/WTC/SS; bitpos: [25]; default: 0; - * Represents ADC_EVT_EQ_ABOVE_THRESH1 trigger status. + * Represents ADC_evt_eq_above_thresh1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_evt_eq_above_thresh1_st:1; /** adc_evt_eq_below_thresh0_st : R/WTC/SS; bitpos: [26]; default: 0; - * Represents ADC_EVT_EQ_BELOW_THRESH0 trigger status. + * Represents ADC_evt_eq_below_thresh0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_evt_eq_below_thresh0_st:1; /** adc_evt_eq_below_thresh1_st : R/WTC/SS; bitpos: [27]; default: 0; - * Represents ADC_EVT_EQ_BELOW_THRESH1 trigger status. + * Represents ADC_evt_eq_below_thresh1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_evt_eq_below_thresh1_st:1; /** adc_evt_result_done0_st : R/WTC/SS; bitpos: [28]; default: 0; - * Represents ADC_EVT_RESULT_DONE0 trigger status. + * Represents ADC_evt_result_done0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_evt_result_done0_st:1; /** adc_evt_stopped0_st : R/WTC/SS; bitpos: [29]; default: 0; - * Represents ADC_EVT_STOPPED0 trigger status. + * Represents ADC_evt_stopped0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_evt_stopped0_st:1; /** adc_evt_started0_st : R/WTC/SS; bitpos: [30]; default: 0; - * Represents ADC_EVT_STARTED0 trigger status. + * Represents ADC_evt_started0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_evt_started0_st:1; - uint32_t reserved_31:1; + /** regdma_evt_done0_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents REGDMA_evt_done0 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_evt_done0_st:1; }; uint32_t val; } soc_etm_evt_st1_reg_t; /** Type of evt_st2 register - * Event trigger status register + * Events trigger status register */ typedef union { struct { - uint32_t reserved_0:7; + /** regdma_evt_done1_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents REGDMA_evt_done1 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_evt_done1_st:1; + /** regdma_evt_done2_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents REGDMA_evt_done2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_evt_done2_st:1; + /** regdma_evt_done3_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents REGDMA_evt_done3 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_evt_done3_st:1; + /** regdma_evt_err0_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents REGDMA_evt_err0 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_evt_err0_st:1; + /** regdma_evt_err1_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents REGDMA_evt_err1 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_evt_err1_st:1; + /** regdma_evt_err2_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents REGDMA_evt_err2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_evt_err2_st:1; + /** regdma_evt_err3_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents REGDMA_evt_err3 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_evt_err3_st:1; /** tmpsnsr_evt_over_limit_st : R/WTC/SS; bitpos: [7]; default: 0; - * Represents TMPSNSR_EVT_OVER_LIMIT trigger status. + * Represents TMPSNSR_evt_over_limit trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tmpsnsr_evt_over_limit_st:1; /** i2s0_evt_rx_done_st : R/WTC/SS; bitpos: [8]; default: 0; - * Represents I2S0_EVT_RX_DONE trigger status. + * Represents I2S0_evt_rx_done trigger status. * 0: Not triggered * 1: Triggered */ uint32_t i2s0_evt_rx_done_st:1; /** i2s0_evt_tx_done_st : R/WTC/SS; bitpos: [9]; default: 0; - * Represents I2S0_EVT_TX_DONE trigger status. + * Represents I2S0_evt_tx_done trigger status. * 0: Not triggered * 1: Triggered */ uint32_t i2s0_evt_tx_done_st:1; /** i2s0_evt_x_words_received_st : R/WTC/SS; bitpos: [10]; default: 0; - * Represents I2S0_EVT_X_WORDS_RECEIVED trigger status. + * Represents I2S0_evt_x_words_received trigger status. * 0: Not triggered * 1: Triggered */ uint32_t i2s0_evt_x_words_received_st:1; /** i2s0_evt_x_words_sent_st : R/WTC/SS; bitpos: [11]; default: 0; - * Represents I2S0_EVT_X_WORDS_SENT trigger status. + * Represents I2S0_evt_x_words_sent trigger status. * 0: Not triggered * 1: Triggered */ uint32_t i2s0_evt_x_words_sent_st:1; - uint32_t reserved_12:7; + /** i2s1_evt_rx_done_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents I2S1_evt_rx_done trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t i2s1_evt_rx_done_st:1; + /** i2s1_evt_tx_done_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents I2S1_evt_tx_done trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t i2s1_evt_tx_done_st:1; + /** i2s1_evt_x_words_received_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents I2S1_evt_x_words_received trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t i2s1_evt_x_words_received_st:1; + /** i2s1_evt_x_words_sent_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents I2S1_evt_x_words_sent trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t i2s1_evt_x_words_sent_st:1; + /** ulp_evt_err_intr_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents ULP_evt_err_intr trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t ulp_evt_err_intr_st:1; + /** ulp_evt_halt_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents ULP_evt_halt trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t ulp_evt_halt_st:1; + /** ulp_evt_start_intr_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents ULP_evt_start_intr trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t ulp_evt_start_intr_st:1; /** rtc_evt_tick_st : R/WTC/SS; bitpos: [19]; default: 0; - * Represents RTC_EVT_TICK trigger status. + * Represents RTC_evt_tick trigger status. * 0: Not triggered * 1: Triggered */ uint32_t rtc_evt_tick_st:1; /** rtc_evt_ovf_st : R/WTC/SS; bitpos: [20]; default: 0; - * Represents RTC_EVT_OVF trigger status. + * Represents RTC_evt_ovf trigger status. * 0: Not triggered * 1: Triggered */ uint32_t rtc_evt_ovf_st:1; /** rtc_evt_cmp_st : R/WTC/SS; bitpos: [21]; default: 0; - * Represents RTC_EVT_CMP trigger status. + * Represents RTC_evt_cmp trigger status. * 0: Not triggered * 1: Triggered */ uint32_t rtc_evt_cmp_st:1; /** gdma_ahb_evt_in_done_ch0_st : R/WTC/SS; bitpos: [22]; default: 0; - * Represents GDMA_AHB_EVT_IN_DONE_CH0 trigger status. + * Represents GDMA_AHB_evt_in_done_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_in_done_ch0_st:1; /** gdma_ahb_evt_in_done_ch1_st : R/WTC/SS; bitpos: [23]; default: 0; - * Represents GDMA_AHB_EVT_IN_DONE_CH1 trigger status. + * Represents GDMA_AHB_evt_in_done_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_in_done_ch1_st:1; - uint32_t reserved_24:1; + /** gdma_ahb_evt_in_done_ch2_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents GDMA_AHB_evt_in_done_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_evt_in_done_ch2_st:1; /** gdma_ahb_evt_in_suc_eof_ch0_st : R/WTC/SS; bitpos: [25]; default: 0; - * Represents GDMA_AHB_EVT_IN_SUC_EOF_CH0 trigger status. + * Represents GDMA_AHB_evt_in_suc_eof_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_in_suc_eof_ch0_st:1; /** gdma_ahb_evt_in_suc_eof_ch1_st : R/WTC/SS; bitpos: [26]; default: 0; - * Represents GDMA_AHB_EVT_IN_SUC_EOF_CH1 trigger status. + * Represents GDMA_AHB_evt_in_suc_eof_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_in_suc_eof_ch1_st:1; - uint32_t reserved_27:1; + /** gdma_ahb_evt_in_suc_eof_ch2_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents GDMA_AHB_evt_in_suc_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_evt_in_suc_eof_ch2_st:1; /** gdma_ahb_evt_in_fifo_empty_ch0_st : R/WTC/SS; bitpos: [28]; default: 0; - * Represents GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0 trigger status. + * Represents GDMA_AHB_evt_in_fifo_empty_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_in_fifo_empty_ch0_st:1; /** gdma_ahb_evt_in_fifo_empty_ch1_st : R/WTC/SS; bitpos: [29]; default: 0; - * Represents GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1 trigger status. + * Represents GDMA_AHB_evt_in_fifo_empty_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_in_fifo_empty_ch1_st:1; - uint32_t reserved_30:1; + /** gdma_ahb_evt_in_fifo_empty_ch2_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_empty_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_evt_in_fifo_empty_ch2_st:1; /** gdma_ahb_evt_in_fifo_full_ch0_st : R/WTC/SS; bitpos: [31]; default: 0; - * Represents GDMA_AHB_EVT_IN_FIFO_FULL_CH0 trigger status. + * Represents GDMA_AHB_evt_in_fifo_full_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -821,84 +934,114 @@ typedef union { } soc_etm_evt_st2_reg_t; /** Type of evt_st3 register - * Event trigger status register + * Events trigger status register */ typedef union { struct { /** gdma_ahb_evt_in_fifo_full_ch1_st : R/WTC/SS; bitpos: [0]; default: 0; - * Represents GDMA_AHB_EVT_IN_FIFO_FULL_CH1 trigger status. + * Represents GDMA_AHB_evt_in_fifo_full_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_in_fifo_full_ch1_st:1; - uint32_t reserved_1:1; + /** gdma_ahb_evt_in_fifo_full_ch2_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_full_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_evt_in_fifo_full_ch2_st:1; /** gdma_ahb_evt_out_done_ch0_st : R/WTC/SS; bitpos: [2]; default: 0; - * Represents GDMA_AHB_EVT_OUT_DONE_CH0 trigger status. + * Represents GDMA_AHB_evt_out_done_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_done_ch0_st:1; /** gdma_ahb_evt_out_done_ch1_st : R/WTC/SS; bitpos: [3]; default: 0; - * Represents GDMA_AHB_EVT_OUT_DONE_CH1 trigger status. + * Represents GDMA_AHB_evt_out_done_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_done_ch1_st:1; - uint32_t reserved_4:1; + /** gdma_ahb_evt_out_done_ch2_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GDMA_AHB_evt_out_done_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_evt_out_done_ch2_st:1; /** gdma_ahb_evt_out_eof_ch0_st : R/WTC/SS; bitpos: [5]; default: 0; - * Represents GDMA_AHB_EVT_OUT_EOF_CH0 trigger status. + * Represents GDMA_AHB_evt_out_eof_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_eof_ch0_st:1; /** gdma_ahb_evt_out_eof_ch1_st : R/WTC/SS; bitpos: [6]; default: 0; - * Represents GDMA_AHB_EVT_OUT_EOF_CH1 trigger status. + * Represents GDMA_AHB_evt_out_eof_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_eof_ch1_st:1; - uint32_t reserved_7:1; + /** gdma_ahb_evt_out_eof_ch2_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GDMA_AHB_evt_out_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_evt_out_eof_ch2_st:1; /** gdma_ahb_evt_out_total_eof_ch0_st : R/WTC/SS; bitpos: [8]; default: 0; - * Represents GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0 trigger status. + * Represents GDMA_AHB_evt_out_total_eof_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_total_eof_ch0_st:1; /** gdma_ahb_evt_out_total_eof_ch1_st : R/WTC/SS; bitpos: [9]; default: 0; - * Represents GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1 trigger status. + * Represents GDMA_AHB_evt_out_total_eof_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_total_eof_ch1_st:1; - uint32_t reserved_10:1; + /** gdma_ahb_evt_out_total_eof_ch2_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GDMA_AHB_evt_out_total_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_evt_out_total_eof_ch2_st:1; /** gdma_ahb_evt_out_fifo_empty_ch0_st : R/WTC/SS; bitpos: [11]; default: 0; - * Represents GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0 trigger status. + * Represents GDMA_AHB_evt_out_fifo_empty_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_fifo_empty_ch0_st:1; /** gdma_ahb_evt_out_fifo_empty_ch1_st : R/WTC/SS; bitpos: [12]; default: 0; - * Represents GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1 trigger status. + * Represents GDMA_AHB_evt_out_fifo_empty_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_fifo_empty_ch1_st:1; - uint32_t reserved_13:1; + /** gdma_ahb_evt_out_fifo_empty_ch2_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_empty_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_evt_out_fifo_empty_ch2_st:1; /** gdma_ahb_evt_out_fifo_full_ch0_st : R/WTC/SS; bitpos: [14]; default: 0; - * Represents GDMA_AHB_EVT_OUT_FIFO_FULL_CH0 trigger status. + * Represents GDMA_AHB_evt_out_fifo_full_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_fifo_full_ch0_st:1; /** gdma_ahb_evt_out_fifo_full_ch1_st : R/WTC/SS; bitpos: [15]; default: 0; - * Represents GDMA_AHB_EVT_OUT_FIFO_FULL_CH1 trigger status. + * Represents GDMA_AHB_evt_out_fifo_full_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_fifo_full_ch1_st:1; - uint32_t reserved_16:1; + /** gdma_ahb_evt_out_fifo_full_ch2_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_full_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_evt_out_fifo_full_ch2_st:1; /** pmu_evt_sleep_weekup_st : R/WTC/SS; bitpos: [17]; default: 0; - * Represents PMU_EVT_SLEEP_WEEKUP trigger status. + * Represents PMU_evt_sleep_weekup trigger status. * 0: Not triggered * 1: Triggered */ @@ -909,198 +1052,198 @@ typedef union { } soc_etm_evt_st3_reg_t; /** Type of task_st0 register - * Task trigger status register + * Tasks trigger status register */ typedef union { struct { /** gpio_task_ch0_set_st : R/WTC/SS; bitpos: [0]; default: 0; - * Represents GPIO_TASK_CH0_SET trigger status. + * Represents GPIO_task_ch0_set trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch0_set_st:1; /** gpio_task_ch1_set_st : R/WTC/SS; bitpos: [1]; default: 0; - * Represents GPIO_TASK_CH1_SET trigger status. + * Represents GPIO_task_ch1_set trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch1_set_st:1; /** gpio_task_ch2_set_st : R/WTC/SS; bitpos: [2]; default: 0; - * Represents GPIO_TASK_CH2_SET trigger status. + * Represents GPIO_task_ch2_set trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch2_set_st:1; /** gpio_task_ch3_set_st : R/WTC/SS; bitpos: [3]; default: 0; - * Represents GPIO_TASK_CH3_SET trigger status. + * Represents GPIO_task_ch3_set trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch3_set_st:1; /** gpio_task_ch4_set_st : R/WTC/SS; bitpos: [4]; default: 0; - * Represents GPIO_TASK_CH4_SET trigger status. + * Represents GPIO_task_ch4_set trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch4_set_st:1; /** gpio_task_ch5_set_st : R/WTC/SS; bitpos: [5]; default: 0; - * Represents GPIO_TASK_CH5_SET trigger status. + * Represents GPIO_task_ch5_set trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch5_set_st:1; /** gpio_task_ch6_set_st : R/WTC/SS; bitpos: [6]; default: 0; - * Represents GPIO_TASK_CH6_SET trigger status. + * Represents GPIO_task_ch6_set trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch6_set_st:1; /** gpio_task_ch7_set_st : R/WTC/SS; bitpos: [7]; default: 0; - * Represents GPIO_TASK_CH7_SET trigger status. + * Represents GPIO_task_ch7_set trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch7_set_st:1; /** gpio_task_ch0_clear_st : R/WTC/SS; bitpos: [8]; default: 0; - * Represents GPIO_TASK_CH0_CLEAR trigger status. + * Represents GPIO_task_ch0_clear trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch0_clear_st:1; /** gpio_task_ch1_clear_st : R/WTC/SS; bitpos: [9]; default: 0; - * Represents GPIO_TASK_CH1_CLEAR trigger status. + * Represents GPIO_task_ch1_clear trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch1_clear_st:1; /** gpio_task_ch2_clear_st : R/WTC/SS; bitpos: [10]; default: 0; - * Represents GPIO_TASK_CH2_CLEAR trigger status. + * Represents GPIO_task_ch2_clear trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch2_clear_st:1; /** gpio_task_ch3_clear_st : R/WTC/SS; bitpos: [11]; default: 0; - * Represents GPIO_TASK_CH3_CLEAR trigger status. + * Represents GPIO_task_ch3_clear trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch3_clear_st:1; /** gpio_task_ch4_clear_st : R/WTC/SS; bitpos: [12]; default: 0; - * Represents GPIO_TASK_CH4_CLEAR trigger status. + * Represents GPIO_task_ch4_clear trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch4_clear_st:1; /** gpio_task_ch5_clear_st : R/WTC/SS; bitpos: [13]; default: 0; - * Represents GPIO_TASK_CH5_CLEAR trigger status. + * Represents GPIO_task_ch5_clear trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch5_clear_st:1; /** gpio_task_ch6_clear_st : R/WTC/SS; bitpos: [14]; default: 0; - * Represents GPIO_TASK_CH6_CLEAR trigger status. + * Represents GPIO_task_ch6_clear trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch6_clear_st:1; /** gpio_task_ch7_clear_st : R/WTC/SS; bitpos: [15]; default: 0; - * Represents GPIO_TASK_CH7_CLEAR trigger status. + * Represents GPIO_task_ch7_clear trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch7_clear_st:1; /** gpio_task_ch0_toggle_st : R/WTC/SS; bitpos: [16]; default: 0; - * Represents GPIO_TASK_CH0_TOGGLE trigger status. + * Represents GPIO_task_ch0_toggle trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch0_toggle_st:1; /** gpio_task_ch1_toggle_st : R/WTC/SS; bitpos: [17]; default: 0; - * Represents GPIO_TASK_CH1_TOGGLE trigger status. + * Represents GPIO_task_ch1_toggle trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch1_toggle_st:1; /** gpio_task_ch2_toggle_st : R/WTC/SS; bitpos: [18]; default: 0; - * Represents GPIO_TASK_CH2_TOGGLE trigger status. + * Represents GPIO_task_ch2_toggle trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch2_toggle_st:1; /** gpio_task_ch3_toggle_st : R/WTC/SS; bitpos: [19]; default: 0; - * Represents GPIO_TASK_CH3_TOGGLE trigger status. + * Represents GPIO_task_ch3_toggle trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch3_toggle_st:1; /** gpio_task_ch4_toggle_st : R/WTC/SS; bitpos: [20]; default: 0; - * Represents GPIO_TASK_CH4_TOGGLE trigger status. + * Represents GPIO_task_ch4_toggle trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch4_toggle_st:1; /** gpio_task_ch5_toggle_st : R/WTC/SS; bitpos: [21]; default: 0; - * Represents GPIO_TASK_CH5_TOGGLE trigger status. + * Represents GPIO_task_ch5_toggle trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch5_toggle_st:1; /** gpio_task_ch6_toggle_st : R/WTC/SS; bitpos: [22]; default: 0; - * Represents GPIO_TASK_CH6_TOGGLE trigger status. + * Represents GPIO_task_ch6_toggle trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch6_toggle_st:1; /** gpio_task_ch7_toggle_st : R/WTC/SS; bitpos: [23]; default: 0; - * Represents GPIO_TASK_CH7_TOGGLE trigger status. + * Represents GPIO_task_ch7_toggle trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch7_toggle_st:1; /** ledc_task_timer0_res_update_st : R/WTC/SS; bitpos: [24]; default: 0; - * Represents LEDC_TASK_TIMER0_RES_UPDATE trigger status. + * Represents LEDC_task_timer0_res_update trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer0_res_update_st:1; /** ledc_task_timer1_res_update_st : R/WTC/SS; bitpos: [25]; default: 0; - * Represents LEDC_TASK_TIMER1_RES_UPDATE trigger status. + * Represents LEDC_task_timer1_res_update trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer1_res_update_st:1; /** ledc_task_timer2_res_update_st : R/WTC/SS; bitpos: [26]; default: 0; - * Represents LEDC_TASK_TIMER2_RES_UPDATE trigger status. + * Represents LEDC_task_timer2_res_update trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer2_res_update_st:1; /** ledc_task_timer3_res_update_st : R/WTC/SS; bitpos: [27]; default: 0; - * Represents LEDC_TASK_TIMER3_RES_UPDATE trigger status. + * Represents LEDC_task_timer3_res_update trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer3_res_update_st:1; /** ledc_task_duty_scale_update_ch0_st : R/WTC/SS; bitpos: [28]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH0 trigger status. + * Represents LEDC_task_duty_scale_update_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_duty_scale_update_ch0_st:1; /** ledc_task_duty_scale_update_ch1_st : R/WTC/SS; bitpos: [29]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH1 trigger status. + * Represents LEDC_task_duty_scale_update_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_duty_scale_update_ch1_st:1; /** ledc_task_duty_scale_update_ch2_st : R/WTC/SS; bitpos: [30]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH2 trigger status. + * Represents LEDC_task_duty_scale_update_ch2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_duty_scale_update_ch2_st:1; /** ledc_task_duty_scale_update_ch3_st : R/WTC/SS; bitpos: [31]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH3 trigger status. + * Represents LEDC_task_duty_scale_update_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -1110,198 +1253,198 @@ typedef union { } soc_etm_task_st0_reg_t; /** Type of task_st1 register - * Task trigger status register + * Tasks trigger status register */ typedef union { struct { /** ledc_task_duty_scale_update_ch4_st : R/WTC/SS; bitpos: [0]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH4 trigger status. + * Represents LEDC_task_duty_scale_update_ch4 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_duty_scale_update_ch4_st:1; /** ledc_task_duty_scale_update_ch5_st : R/WTC/SS; bitpos: [1]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH5 trigger status. + * Represents LEDC_task_duty_scale_update_ch5 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_duty_scale_update_ch5_st:1; /** ledc_task_timer0_cap_st : R/WTC/SS; bitpos: [2]; default: 0; - * Represents LEDC_TASK_TIMER0_CAP trigger status. + * Represents LEDC_task_timer0_cap trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer0_cap_st:1; /** ledc_task_timer1_cap_st : R/WTC/SS; bitpos: [3]; default: 0; - * Represents LEDC_TASK_TIMER1_CAP trigger status. + * Represents LEDC_task_timer1_cap trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer1_cap_st:1; /** ledc_task_timer2_cap_st : R/WTC/SS; bitpos: [4]; default: 0; - * Represents LEDC_TASK_TIMER2_CAP trigger status. + * Represents LEDC_task_timer2_cap trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer2_cap_st:1; /** ledc_task_timer3_cap_st : R/WTC/SS; bitpos: [5]; default: 0; - * Represents LEDC_TASK_TIMER3_CAP trigger status. + * Represents LEDC_task_timer3_cap trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer3_cap_st:1; /** ledc_task_sig_out_dis_ch0_st : R/WTC/SS; bitpos: [6]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH0 trigger status. + * Represents LEDC_task_sig_out_dis_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_sig_out_dis_ch0_st:1; /** ledc_task_sig_out_dis_ch1_st : R/WTC/SS; bitpos: [7]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH1 trigger status. + * Represents LEDC_task_sig_out_dis_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_sig_out_dis_ch1_st:1; /** ledc_task_sig_out_dis_ch2_st : R/WTC/SS; bitpos: [8]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH2 trigger status. + * Represents LEDC_task_sig_out_dis_ch2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_sig_out_dis_ch2_st:1; /** ledc_task_sig_out_dis_ch3_st : R/WTC/SS; bitpos: [9]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH3 trigger status. + * Represents LEDC_task_sig_out_dis_ch3 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_sig_out_dis_ch3_st:1; /** ledc_task_sig_out_dis_ch4_st : R/WTC/SS; bitpos: [10]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH4 trigger status. + * Represents LEDC_task_sig_out_dis_ch4 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_sig_out_dis_ch4_st:1; /** ledc_task_sig_out_dis_ch5_st : R/WTC/SS; bitpos: [11]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH5 trigger status. + * Represents LEDC_task_sig_out_dis_ch5 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_sig_out_dis_ch5_st:1; /** ledc_task_ovf_cnt_rst_ch0_st : R/WTC/SS; bitpos: [12]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH0 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_ovf_cnt_rst_ch0_st:1; /** ledc_task_ovf_cnt_rst_ch1_st : R/WTC/SS; bitpos: [13]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH1 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_ovf_cnt_rst_ch1_st:1; /** ledc_task_ovf_cnt_rst_ch2_st : R/WTC/SS; bitpos: [14]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH2 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_ovf_cnt_rst_ch2_st:1; /** ledc_task_ovf_cnt_rst_ch3_st : R/WTC/SS; bitpos: [15]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH3 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch3 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_ovf_cnt_rst_ch3_st:1; /** ledc_task_ovf_cnt_rst_ch4_st : R/WTC/SS; bitpos: [16]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH4 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch4 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_ovf_cnt_rst_ch4_st:1; /** ledc_task_ovf_cnt_rst_ch5_st : R/WTC/SS; bitpos: [17]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH5 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch5 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_ovf_cnt_rst_ch5_st:1; /** ledc_task_timer0_rst_st : R/WTC/SS; bitpos: [18]; default: 0; - * Represents LEDC_TASK_TIMER0_RST trigger status. + * Represents LEDC_task_timer0_rst trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer0_rst_st:1; /** ledc_task_timer1_rst_st : R/WTC/SS; bitpos: [19]; default: 0; - * Represents LEDC_TASK_TIMER1_RST trigger status. + * Represents LEDC_task_timer1_rst trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer1_rst_st:1; /** ledc_task_timer2_rst_st : R/WTC/SS; bitpos: [20]; default: 0; - * Represents LEDC_TASK_TIMER2_RST trigger status. + * Represents LEDC_task_timer2_rst trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer2_rst_st:1; /** ledc_task_timer3_rst_st : R/WTC/SS; bitpos: [21]; default: 0; - * Represents LEDC_TASK_TIMER3_RST trigger status. + * Represents LEDC_task_timer3_rst trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer3_rst_st:1; /** ledc_task_timer0_resume_st : R/WTC/SS; bitpos: [22]; default: 0; - * Represents LEDC_TASK_TIMER0_RESUME trigger status. + * Represents LEDC_task_timer0_resume trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer0_resume_st:1; /** ledc_task_timer1_resume_st : R/WTC/SS; bitpos: [23]; default: 0; - * Represents LEDC_TASK_TIMER1_RESUME trigger status. + * Represents LEDC_task_timer1_resume trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer1_resume_st:1; /** ledc_task_timer2_resume_st : R/WTC/SS; bitpos: [24]; default: 0; - * Represents LEDC_TASK_TIMER2_RESUME trigger status. + * Represents LEDC_task_timer2_resume trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer2_resume_st:1; /** ledc_task_timer3_resume_st : R/WTC/SS; bitpos: [25]; default: 0; - * Represents LEDC_TASK_TIMER3_RESUME trigger status. + * Represents LEDC_task_timer3_resume trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer3_resume_st:1; /** ledc_task_timer0_pause_st : R/WTC/SS; bitpos: [26]; default: 0; - * Represents LEDC_TASK_TIMER0_PAUSE trigger status. + * Represents LEDC_task_timer0_pause trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer0_pause_st:1; /** ledc_task_timer1_pause_st : R/WTC/SS; bitpos: [27]; default: 0; - * Represents LEDC_TASK_TIMER1_PAUSE trigger status. + * Represents LEDC_task_timer1_pause trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer1_pause_st:1; /** ledc_task_timer2_pause_st : R/WTC/SS; bitpos: [28]; default: 0; - * Represents LEDC_TASK_TIMER2_PAUSE trigger status. + * Represents LEDC_task_timer2_pause trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer2_pause_st:1; /** ledc_task_timer3_pause_st : R/WTC/SS; bitpos: [29]; default: 0; - * Represents LEDC_TASK_TIMER3_PAUSE trigger status. + * Represents LEDC_task_timer3_pause trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer3_pause_st:1; /** ledc_task_gamma_restart_ch0_st : R/WTC/SS; bitpos: [30]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH0 trigger status. + * Represents LEDC_task_gamma_restart_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_restart_ch0_st:1; /** ledc_task_gamma_restart_ch1_st : R/WTC/SS; bitpos: [31]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH1 trigger status. + * Represents LEDC_task_gamma_restart_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -1311,198 +1454,198 @@ typedef union { } soc_etm_task_st1_reg_t; /** Type of task_st2 register - * Task trigger status register + * Tasks trigger status register */ typedef union { struct { /** ledc_task_gamma_restart_ch2_st : R/WTC/SS; bitpos: [0]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH2 trigger status. + * Represents LEDC_task_gamma_restart_ch2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_restart_ch2_st:1; /** ledc_task_gamma_restart_ch3_st : R/WTC/SS; bitpos: [1]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH3 trigger status. + * Represents LEDC_task_gamma_restart_ch3 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_restart_ch3_st:1; /** ledc_task_gamma_restart_ch4_st : R/WTC/SS; bitpos: [2]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH4 trigger status. + * Represents LEDC_task_gamma_restart_ch4 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_restart_ch4_st:1; /** ledc_task_gamma_restart_ch5_st : R/WTC/SS; bitpos: [3]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH5 trigger status. + * Represents LEDC_task_gamma_restart_ch5 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_restart_ch5_st:1; /** ledc_task_gamma_pause_ch0_st : R/WTC/SS; bitpos: [4]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH0 trigger status. + * Represents LEDC_task_gamma_pause_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_pause_ch0_st:1; /** ledc_task_gamma_pause_ch1_st : R/WTC/SS; bitpos: [5]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH1 trigger status. + * Represents LEDC_task_gamma_pause_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_pause_ch1_st:1; /** ledc_task_gamma_pause_ch2_st : R/WTC/SS; bitpos: [6]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH2 trigger status. + * Represents LEDC_task_gamma_pause_ch2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_pause_ch2_st:1; /** ledc_task_gamma_pause_ch3_st : R/WTC/SS; bitpos: [7]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH3 trigger status. + * Represents LEDC_task_gamma_pause_ch3 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_pause_ch3_st:1; /** ledc_task_gamma_pause_ch4_st : R/WTC/SS; bitpos: [8]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH4 trigger status. + * Represents LEDC_task_gamma_pause_ch4 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_pause_ch4_st:1; /** ledc_task_gamma_pause_ch5_st : R/WTC/SS; bitpos: [9]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH5 trigger status. + * Represents LEDC_task_gamma_pause_ch5 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_pause_ch5_st:1; /** ledc_task_gamma_resume_ch0_st : R/WTC/SS; bitpos: [10]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH0 trigger status. + * Represents LEDC_task_gamma_resume_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_resume_ch0_st:1; /** ledc_task_gamma_resume_ch1_st : R/WTC/SS; bitpos: [11]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH1 trigger status. + * Represents LEDC_task_gamma_resume_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_resume_ch1_st:1; /** ledc_task_gamma_resume_ch2_st : R/WTC/SS; bitpos: [12]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH2 trigger status. + * Represents LEDC_task_gamma_resume_ch2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_resume_ch2_st:1; /** ledc_task_gamma_resume_ch3_st : R/WTC/SS; bitpos: [13]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH3 trigger status. + * Represents LEDC_task_gamma_resume_ch3 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_resume_ch3_st:1; /** ledc_task_gamma_resume_ch4_st : R/WTC/SS; bitpos: [14]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH4 trigger status. + * Represents LEDC_task_gamma_resume_ch4 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_resume_ch4_st:1; /** ledc_task_gamma_resume_ch5_st : R/WTC/SS; bitpos: [15]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH5 trigger status. + * Represents LEDC_task_gamma_resume_ch5 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_resume_ch5_st:1; /** tg0_task_cnt_start_timer0_st : R/WTC/SS; bitpos: [16]; default: 0; - * Represents TG0_TASK_CNT_START_TIMER0 trigger status. + * Represents TG0_task_cnt_start_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_cnt_start_timer0_st:1; /** tg0_task_alarm_start_timer0_st : R/WTC/SS; bitpos: [17]; default: 0; - * Represents TG0_TASK_ALARM_START_TIMER0 trigger status. + * Represents TG0_task_alarm_start_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_alarm_start_timer0_st:1; /** tg0_task_cnt_stop_timer0_st : R/WTC/SS; bitpos: [18]; default: 0; - * Represents TG0_TASK_CNT_STOP_TIMER0 trigger status. + * Represents TG0_task_cnt_stop_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_cnt_stop_timer0_st:1; /** tg0_task_cnt_reload_timer0_st : R/WTC/SS; bitpos: [19]; default: 0; - * Represents TG0_TASK_CNT_RELOAD_TIMER0 trigger status. + * Represents TG0_task_cnt_reload_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_cnt_reload_timer0_st:1; /** tg0_task_cnt_cap_timer0_st : R/WTC/SS; bitpos: [20]; default: 0; - * Represents TG0_TASK_CNT_CAP_TIMER0 trigger status. + * Represents TG0_task_cnt_cap_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_cnt_cap_timer0_st:1; /** tg0_task_cnt_start_timer1_st : R/WTC/SS; bitpos: [21]; default: 0; - * Represents TG0_TASK_CNT_START_TIMER1 trigger status. + * Represents TG0_task_cnt_start_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_cnt_start_timer1_st:1; /** tg0_task_alarm_start_timer1_st : R/WTC/SS; bitpos: [22]; default: 0; - * Represents TG0_TASK_ALARM_START_TIMER1 trigger status. + * Represents TG0_task_alarm_start_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_alarm_start_timer1_st:1; /** tg0_task_cnt_stop_timer1_st : R/WTC/SS; bitpos: [23]; default: 0; - * Represents TG0_TASK_CNT_STOP_TIMER1 trigger status. + * Represents TG0_task_cnt_stop_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_cnt_stop_timer1_st:1; /** tg0_task_cnt_reload_timer1_st : R/WTC/SS; bitpos: [24]; default: 0; - * Represents TG0_TASK_CNT_RELOAD_TIMER1 trigger status. + * Represents TG0_task_cnt_reload_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_cnt_reload_timer1_st:1; /** tg0_task_cnt_cap_timer1_st : R/WTC/SS; bitpos: [25]; default: 0; - * Represents TG0_TASK_CNT_CAP_TIMER1 trigger status. + * Represents TG0_task_cnt_cap_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_cnt_cap_timer1_st:1; /** tg1_task_cnt_start_timer0_st : R/WTC/SS; bitpos: [26]; default: 0; - * Represents TG1_TASK_CNT_START_TIMER0 trigger status. + * Represents TG1_task_cnt_start_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_task_cnt_start_timer0_st:1; /** tg1_task_alarm_start_timer0_st : R/WTC/SS; bitpos: [27]; default: 0; - * Represents TG1_TASK_ALARM_START_TIMER0 trigger status. + * Represents TG1_task_alarm_start_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_task_alarm_start_timer0_st:1; /** tg1_task_cnt_stop_timer0_st : R/WTC/SS; bitpos: [28]; default: 0; - * Represents TG1_TASK_CNT_STOP_TIMER0 trigger status. + * Represents TG1_task_cnt_stop_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_task_cnt_stop_timer0_st:1; /** tg1_task_cnt_reload_timer0_st : R/WTC/SS; bitpos: [29]; default: 0; - * Represents TG1_TASK_CNT_RELOAD_TIMER0 trigger status. + * Represents TG1_task_cnt_reload_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_task_cnt_reload_timer0_st:1; /** tg1_task_cnt_cap_timer0_st : R/WTC/SS; bitpos: [30]; default: 0; - * Represents TG1_TASK_CNT_CAP_TIMER0 trigger status. + * Represents TG1_task_cnt_cap_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_task_cnt_cap_timer0_st:1; /** tg1_task_cnt_start_timer1_st : R/WTC/SS; bitpos: [31]; default: 0; - * Represents TG1_TASK_CNT_START_TIMER1 trigger status. + * Represents TG1_task_cnt_start_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -1512,106 +1655,198 @@ typedef union { } soc_etm_task_st2_reg_t; /** Type of task_st3 register - * Task trigger status register + * Tasks trigger status register */ typedef union { struct { /** tg1_task_alarm_start_timer1_st : R/WTC/SS; bitpos: [0]; default: 0; - * Represents TG1_TASK_ALARM_START_TIMER1 trigger status. + * Represents TG1_task_alarm_start_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_task_alarm_start_timer1_st:1; /** tg1_task_cnt_stop_timer1_st : R/WTC/SS; bitpos: [1]; default: 0; - * Represents TG1_TASK_CNT_STOP_TIMER1 trigger status. + * Represents TG1_task_cnt_stop_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_task_cnt_stop_timer1_st:1; /** tg1_task_cnt_reload_timer1_st : R/WTC/SS; bitpos: [2]; default: 0; - * Represents TG1_TASK_CNT_RELOAD_TIMER1 trigger status. + * Represents TG1_task_cnt_reload_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_task_cnt_reload_timer1_st:1; /** tg1_task_cnt_cap_timer1_st : R/WTC/SS; bitpos: [3]; default: 0; - * Represents TG1_TASK_CNT_CAP_TIMER1 trigger status. + * Represents TG1_task_cnt_cap_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_task_cnt_cap_timer1_st:1; /** adc_task_sample0_st : R/WTC/SS; bitpos: [4]; default: 0; - * Represents ADC_TASK_SAMPLE0 trigger status. + * Represents ADC_task_sample0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_task_sample0_st:1; - uint32_t reserved_5:1; + /** adc_task_sample1_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents ADC_task_sample1 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t adc_task_sample1_st:1; /** adc_task_start0_st : R/WTC/SS; bitpos: [6]; default: 0; - * Represents ADC_TASK_START0 trigger status. + * Represents ADC_task_start0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_task_start0_st:1; /** adc_task_stop0_st : R/WTC/SS; bitpos: [7]; default: 0; - * Represents ADC_TASK_STOP0 trigger status. + * Represents ADC_task_stop0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_task_stop0_st:1; - uint32_t reserved_8:4; + /** regdma_task_start0_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents REGDMA_task_start0 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_task_start0_st:1; + /** regdma_task_start1_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents REGDMA_task_start1 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_task_start1_st:1; + /** regdma_task_start2_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents REGDMA_task_start2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_task_start2_st:1; + /** regdma_task_start3_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents REGDMA_task_start3 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_task_start3_st:1; /** tmpsnsr_task_start_sample_st : R/WTC/SS; bitpos: [12]; default: 0; - * Represents TMPSNSR_TASK_START_SAMPLE trigger status. + * Represents TMPSNSR_task_start_sample trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tmpsnsr_task_start_sample_st:1; /** tmpsnsr_task_stop_sample_st : R/WTC/SS; bitpos: [13]; default: 0; - * Represents TMPSNSR_TASK_STOP_SAMPLE trigger status. + * Represents TMPSNSR_task_stop_sample trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tmpsnsr_task_stop_sample_st:1; /** i2s0_task_start_rx_st : R/WTC/SS; bitpos: [14]; default: 0; - * Represents I2S0_TASK_START_RX trigger status. + * Represents I2S0_task_start_rx trigger status. * 0: Not triggered * 1: Triggered */ uint32_t i2s0_task_start_rx_st:1; /** i2s0_task_start_tx_st : R/WTC/SS; bitpos: [15]; default: 0; - * Represents I2S0_TASK_START_TX trigger status. + * Represents I2S0_task_start_tx trigger status. * 0: Not triggered * 1: Triggered */ uint32_t i2s0_task_start_tx_st:1; /** i2s0_task_stop_rx_st : R/WTC/SS; bitpos: [16]; default: 0; - * Represents I2S0_TASK_STOP_RX trigger status. + * Represents I2S0_task_stop_rx trigger status. * 0: Not triggered * 1: Triggered */ uint32_t i2s0_task_stop_rx_st:1; /** i2s0_task_stop_tx_st : R/WTC/SS; bitpos: [17]; default: 0; - * Represents I2S0_TASK_STOP_TX trigger status. + * Represents I2S0_task_stop_tx trigger status. * 0: Not triggered * 1: Triggered */ uint32_t i2s0_task_stop_tx_st:1; - uint32_t reserved_18:10; + /** i2s1_task_start_rx_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents I2S1_task_start_rx trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t i2s1_task_start_rx_st:1; + /** i2s1_task_start_tx_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents I2S1_task_start_tx trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t i2s1_task_start_tx_st:1; + /** i2s1_task_stop_rx_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents I2S1_task_stop_rx trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t i2s1_task_stop_rx_st:1; + /** i2s1_task_stop_tx_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents I2S1_task_stop_tx trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t i2s1_task_stop_tx_st:1; + /** ulp_task_wakeup_cpu_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents ULP_task_wakeup_cpu trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t ulp_task_wakeup_cpu_st:1; + /** ulp_task_int_cpu_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents ULP_task_int_cpu trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t ulp_task_int_cpu_st:1; + /** rtc_task_start_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents RTC_task_start trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t rtc_task_start_st:1; + /** rtc_task_stop_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents RTC_task_stop trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t rtc_task_stop_st:1; + /** rtc_task_clr_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents RTC_task_clr trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t rtc_task_clr_st:1; + /** rtc_task_triggerflw_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents RTC_task_triggerflw trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t rtc_task_triggerflw_st:1; /** gdma_ahb_task_in_start_ch0_st : R/WTC/SS; bitpos: [28]; default: 0; - * Represents GDMA_AHB_TASK_IN_START_CH0 trigger status. + * Represents GDMA_AHB_task_in_start_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_task_in_start_ch0_st:1; /** gdma_ahb_task_in_start_ch1_st : R/WTC/SS; bitpos: [29]; default: 0; - * Represents GDMA_AHB_TASK_IN_START_CH1 trigger status. + * Represents GDMA_AHB_task_in_start_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_task_in_start_ch1_st:1; - uint32_t reserved_30:1; + /** gdma_ahb_task_in_start_ch2_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents GDMA_AHB_task_in_start_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_task_in_start_ch2_st:1; /** gdma_ahb_task_out_start_ch0_st : R/WTC/SS; bitpos: [31]; default: 0; - * Represents GDMA_AHB_TASK_OUT_START_CH0 trigger status. + * Represents GDMA_AHB_task_out_start_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -1621,19 +1856,24 @@ typedef union { } soc_etm_task_st3_reg_t; /** Type of task_st4 register - * Task trigger status register + * Tasks trigger status register */ typedef union { struct { /** gdma_ahb_task_out_start_ch1_st : R/WTC/SS; bitpos: [0]; default: 0; - * Represents GDMA_AHB_TASK_OUT_START_CH1 trigger status. + * Represents GDMA_AHB_task_out_start_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_task_out_start_ch1_st:1; - uint32_t reserved_1:1; + /** gdma_ahb_task_out_start_ch2_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GDMA_AHB_task_out_start_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_task_out_start_ch2_st:1; /** pmu_task_sleep_req_st : R/WTC/SS; bitpos: [2]; default: 0; - * Represents PMU_TASK_SLEEP_REQ trigger status. + * Represents PMU_task_sleep_req trigger status. * 0: Not triggered * 1: Triggered */ @@ -1646,199 +1886,199 @@ typedef union { /** Group: Configuration Register */ /** Type of ch_ena_ad0_set register - * Channel enable register + * Channel enable set register */ typedef union { struct { /** ch_enable0 : WT; bitpos: [0]; default: 0; - * Configures whether or not to enable channel0. - * 0: Invalid. No effect + * Configures whether or not to enable ch0. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable0:1; /** ch_enable1 : WT; bitpos: [1]; default: 0; - * Configures whether or not to enable channel1. - * 0: Invalid. No effect + * Configures whether or not to enable ch1. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable1:1; /** ch_enable2 : WT; bitpos: [2]; default: 0; - * Configures whether or not to enable channel2. - * 0: Invalid. No effect + * Configures whether or not to enable ch2. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable2:1; /** ch_enable3 : WT; bitpos: [3]; default: 0; - * Configures whether or not to enable channel3. - * 0: Invalid. No effect + * Configures whether or not to enable ch3. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable3:1; /** ch_enable4 : WT; bitpos: [4]; default: 0; - * Configures whether or not to enable channel4. - * 0: Invalid. No effect + * Configures whether or not to enable ch4. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable4:1; /** ch_enable5 : WT; bitpos: [5]; default: 0; - * Configures whether or not to enable channel5. - * 0: Invalid. No effect + * Configures whether or not to enable ch5. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable5:1; /** ch_enable6 : WT; bitpos: [6]; default: 0; - * Configures whether or not to enable channel6. - * 0: Invalid. No effect + * Configures whether or not to enable ch6. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable6:1; /** ch_enable7 : WT; bitpos: [7]; default: 0; - * Configures whether or not to enable channel7. - * 0: Invalid. No effect + * Configures whether or not to enable ch7. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable7:1; /** ch_enable8 : WT; bitpos: [8]; default: 0; - * Configures whether or not to enable channel8. - * 0: Invalid. No effect + * Configures whether or not to enable ch8. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable8:1; /** ch_enable9 : WT; bitpos: [9]; default: 0; - * Configures whether or not to enable channel9. - * 0: Invalid. No effect + * Configures whether or not to enable ch9. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable9:1; /** ch_enable10 : WT; bitpos: [10]; default: 0; - * Configures whether or not to enable channel10. - * 0: Invalid. No effect + * Configures whether or not to enable ch10. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable10:1; /** ch_enable11 : WT; bitpos: [11]; default: 0; - * Configures whether or not to enable channel11. - * 0: Invalid. No effect + * Configures whether or not to enable ch11. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable11:1; /** ch_enable12 : WT; bitpos: [12]; default: 0; - * Configures whether or not to enable channel12. - * 0: Invalid. No effect + * Configures whether or not to enable ch12. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable12:1; /** ch_enable13 : WT; bitpos: [13]; default: 0; - * Configures whether or not to enable channel13. - * 0: Invalid. No effect + * Configures whether or not to enable ch13. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable13:1; /** ch_enable14 : WT; bitpos: [14]; default: 0; - * Configures whether or not to enable channel14. - * 0: Invalid. No effect + * Configures whether or not to enable ch14. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable14:1; /** ch_enable15 : WT; bitpos: [15]; default: 0; - * Configures whether or not to enable channel15. - * 0: Invalid. No effect + * Configures whether or not to enable ch15. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable15:1; /** ch_enable16 : WT; bitpos: [16]; default: 0; - * Configures whether or not to enable channel16. - * 0: Invalid. No effect + * Configures whether or not to enable ch16. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable16:1; /** ch_enable17 : WT; bitpos: [17]; default: 0; - * Configures whether or not to enable channel17. - * 0: Invalid. No effect + * Configures whether or not to enable ch17. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable17:1; /** ch_enable18 : WT; bitpos: [18]; default: 0; - * Configures whether or not to enable channel18. - * 0: Invalid. No effect + * Configures whether or not to enable ch18. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable18:1; /** ch_enable19 : WT; bitpos: [19]; default: 0; - * Configures whether or not to enable channel19. - * 0: Invalid. No effect + * Configures whether or not to enable ch19. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable19:1; /** ch_enable20 : WT; bitpos: [20]; default: 0; - * Configures whether or not to enable channel20. - * 0: Invalid. No effect + * Configures whether or not to enable ch20. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable20:1; /** ch_enable21 : WT; bitpos: [21]; default: 0; - * Configures whether or not to enable channel21. - * 0: Invalid. No effect + * Configures whether or not to enable ch21. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable21:1; /** ch_enable22 : WT; bitpos: [22]; default: 0; - * Configures whether or not to enable channel22. - * 0: Invalid. No effect + * Configures whether or not to enable ch22. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable22:1; /** ch_enable23 : WT; bitpos: [23]; default: 0; - * Configures whether or not to enable channel23. - * 0: Invalid. No effect + * Configures whether or not to enable ch23. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable23:1; /** ch_enable24 : WT; bitpos: [24]; default: 0; - * Configures whether or not to enable channel24. - * 0: Invalid. No effect + * Configures whether or not to enable ch24. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable24:1; /** ch_enable25 : WT; bitpos: [25]; default: 0; - * Configures whether or not to enable channel25. - * 0: Invalid. No effect + * Configures whether or not to enable ch25. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable25:1; /** ch_enable26 : WT; bitpos: [26]; default: 0; - * Configures whether or not to enable channel26. - * 0: Invalid. No effect + * Configures whether or not to enable ch26. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable26:1; /** ch_enable27 : WT; bitpos: [27]; default: 0; - * Configures whether or not to enable channel27. - * 0: Invalid. No effect + * Configures whether or not to enable ch27. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable27:1; /** ch_enable28 : WT; bitpos: [28]; default: 0; - * Configures whether or not to enable channel28. - * 0: Invalid. No effect + * Configures whether or not to enable ch28. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable28:1; /** ch_enable29 : WT; bitpos: [29]; default: 0; - * Configures whether or not to enable channel29. - * 0: Invalid. No effect + * Configures whether or not to enable ch29. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable29:1; /** ch_enable30 : WT; bitpos: [30]; default: 0; - * Configures whether or not to enable channel30. - * 0: Invalid. No effect + * Configures whether or not to enable ch30. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable30:1; /** ch_enable31 : WT; bitpos: [31]; default: 0; - * Configures whether or not to enable channel31. - * 0: Invalid. No effect + * Configures whether or not to enable ch31. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable31:1; @@ -1847,199 +2087,199 @@ typedef union { } soc_etm_ch_ena_ad0_set_reg_t; /** Type of ch_ena_ad0_clr register - * Channel disable register + * Channel enable clear register */ typedef union { struct { /** ch_disable0 : WT; bitpos: [0]; default: 0; - * Configures whether or not to disable channel0. - * 0: Invalid. No effect + * Configures whether or not to clear ch0 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable0:1; /** ch_disable1 : WT; bitpos: [1]; default: 0; - * Configures whether or not to disable channel1. - * 0: Invalid. No effect + * Configures whether or not to clear ch1 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable1:1; /** ch_disable2 : WT; bitpos: [2]; default: 0; - * Configures whether or not to disable channel2. - * 0: Invalid. No effect + * Configures whether or not to clear ch2 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable2:1; /** ch_disable3 : WT; bitpos: [3]; default: 0; - * Configures whether or not to disable channel3. - * 0: Invalid. No effect + * Configures whether or not to clear ch3 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable3:1; /** ch_disable4 : WT; bitpos: [4]; default: 0; - * Configures whether or not to disable channel4. - * 0: Invalid. No effect + * Configures whether or not to clear ch4 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable4:1; /** ch_disable5 : WT; bitpos: [5]; default: 0; - * Configures whether or not to disable channel5. - * 0: Invalid. No effect + * Configures whether or not to clear ch5 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable5:1; /** ch_disable6 : WT; bitpos: [6]; default: 0; - * Configures whether or not to disable channel6. - * 0: Invalid. No effect + * Configures whether or not to clear ch6 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable6:1; /** ch_disable7 : WT; bitpos: [7]; default: 0; - * Configures whether or not to disable channel7. - * 0: Invalid. No effect + * Configures whether or not to clear ch7 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable7:1; /** ch_disable8 : WT; bitpos: [8]; default: 0; - * Configures whether or not to disable channel8. - * 0: Invalid. No effect + * Configures whether or not to clear ch8 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable8:1; /** ch_disable9 : WT; bitpos: [9]; default: 0; - * Configures whether or not to disable channel9. - * 0: Invalid. No effect + * Configures whether or not to clear ch9 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable9:1; /** ch_disable10 : WT; bitpos: [10]; default: 0; - * Configures whether or not to disable channel10. - * 0: Invalid. No effect + * Configures whether or not to clear ch10 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable10:1; /** ch_disable11 : WT; bitpos: [11]; default: 0; - * Configures whether or not to disable channel11. - * 0: Invalid. No effect + * Configures whether or not to clear ch11 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable11:1; /** ch_disable12 : WT; bitpos: [12]; default: 0; - * Configures whether or not to disable channel12. - * 0: Invalid. No effect + * Configures whether or not to clear ch12 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable12:1; /** ch_disable13 : WT; bitpos: [13]; default: 0; - * Configures whether or not to disable channel13. - * 0: Invalid. No effect + * Configures whether or not to clear ch13 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable13:1; /** ch_disable14 : WT; bitpos: [14]; default: 0; - * Configures whether or not to disable channel14. - * 0: Invalid. No effect + * Configures whether or not to clear ch14 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable14:1; /** ch_disable15 : WT; bitpos: [15]; default: 0; - * Configures whether or not to disable channel15. - * 0: Invalid. No effect + * Configures whether or not to clear ch15 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable15:1; /** ch_disable16 : WT; bitpos: [16]; default: 0; - * Configures whether or not to disable channel16. - * 0: Invalid. No effect + * Configures whether or not to clear ch16 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable16:1; /** ch_disable17 : WT; bitpos: [17]; default: 0; - * Configures whether or not to disable channel17. - * 0: Invalid. No effect + * Configures whether or not to clear ch17 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable17:1; /** ch_disable18 : WT; bitpos: [18]; default: 0; - * Configures whether or not to disable channel18. - * 0: Invalid. No effect + * Configures whether or not to clear ch18 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable18:1; /** ch_disable19 : WT; bitpos: [19]; default: 0; - * Configures whether or not to disable channel19. - * 0: Invalid. No effect + * Configures whether or not to clear ch19 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable19:1; /** ch_disable20 : WT; bitpos: [20]; default: 0; - * Configures whether or not to disable channel20. - * 0: Invalid. No effect + * Configures whether or not to clear ch20 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable20:1; /** ch_disable21 : WT; bitpos: [21]; default: 0; - * Configures whether or not to disable channel21. - * 0: Invalid. No effect + * Configures whether or not to clear ch21 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable21:1; /** ch_disable22 : WT; bitpos: [22]; default: 0; - * Configures whether or not to disable channel22. - * 0: Invalid. No effect + * Configures whether or not to clear ch22 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable22:1; /** ch_disable23 : WT; bitpos: [23]; default: 0; - * Configures whether or not to disable channel23. - * 0: Invalid. No effect + * Configures whether or not to clear ch23 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable23:1; /** ch_disable24 : WT; bitpos: [24]; default: 0; - * Configures whether or not to disable channel24. - * 0: Invalid. No effect + * Configures whether or not to clear ch24 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable24:1; /** ch_disable25 : WT; bitpos: [25]; default: 0; - * Configures whether or not to disable channel25. - * 0: Invalid. No effect + * Configures whether or not to clear ch25 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable25:1; /** ch_disable26 : WT; bitpos: [26]; default: 0; - * Configures whether or not to disable channel26. - * 0: Invalid. No effect + * Configures whether or not to clear ch26 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable26:1; /** ch_disable27 : WT; bitpos: [27]; default: 0; - * Configures whether or not to disable channel27. - * 0: Invalid. No effect + * Configures whether or not to clear ch27 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable27:1; /** ch_disable28 : WT; bitpos: [28]; default: 0; - * Configures whether or not to disable channel28. - * 0: Invalid. No effect + * Configures whether or not to clear ch28 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable28:1; /** ch_disable29 : WT; bitpos: [29]; default: 0; - * Configures whether or not to disable channel29. - * 0: Invalid. No effect + * Configures whether or not to clear ch29 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable29:1; /** ch_disable30 : WT; bitpos: [30]; default: 0; - * Configures whether or not to disable channel30. - * 0: Invalid. No effect + * Configures whether or not to clear ch30 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable30:1; /** ch_disable31 : WT; bitpos: [31]; default: 0; - * Configures whether or not to disable channel31. - * 0: Invalid. No effect + * Configures whether or not to clear ch31 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable31:1; @@ -2048,115 +2288,115 @@ typedef union { } soc_etm_ch_ena_ad0_clr_reg_t; /** Type of ch_ena_ad1_set register - * Channel enable register + * Channel enable set register */ typedef union { struct { /** ch_enable32 : WT; bitpos: [0]; default: 0; - * Configures whether or not to enable channel32. - * 0: Invalid. No effect + * Configures whether or not to enable ch32. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable32:1; /** ch_enable33 : WT; bitpos: [1]; default: 0; - * Configures whether or not to enable channel33. - * 0: Invalid. No effect + * Configures whether or not to enable ch33. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable33:1; /** ch_enable34 : WT; bitpos: [2]; default: 0; - * Configures whether or not to enable channel34. - * 0: Invalid. No effect + * Configures whether or not to enable ch34. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable34:1; /** ch_enable35 : WT; bitpos: [3]; default: 0; - * Configures whether or not to enable channel35. - * 0: Invalid. No effect + * Configures whether or not to enable ch35. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable35:1; /** ch_enable36 : WT; bitpos: [4]; default: 0; - * Configures whether or not to enable channel36. - * 0: Invalid. No effect + * Configures whether or not to enable ch36. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable36:1; /** ch_enable37 : WT; bitpos: [5]; default: 0; - * Configures whether or not to enable channel37. - * 0: Invalid. No effect + * Configures whether or not to enable ch37. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable37:1; /** ch_enable38 : WT; bitpos: [6]; default: 0; - * Configures whether or not to enable channel38. - * 0: Invalid. No effect + * Configures whether or not to enable ch38. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable38:1; /** ch_enable39 : WT; bitpos: [7]; default: 0; - * Configures whether or not to enable channel39. - * 0: Invalid. No effect + * Configures whether or not to enable ch39. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable39:1; /** ch_enable40 : WT; bitpos: [8]; default: 0; - * Configures whether or not to enable channel40. - * 0: Invalid. No effect + * Configures whether or not to enable ch40. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable40:1; /** ch_enable41 : WT; bitpos: [9]; default: 0; - * Configures whether or not to enable channel41. - * 0: Invalid. No effect + * Configures whether or not to enable ch41. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable41:1; /** ch_enable42 : WT; bitpos: [10]; default: 0; - * Configures whether or not to enable channel42. - * 0: Invalid. No effect + * Configures whether or not to enable ch42. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable42:1; /** ch_enable43 : WT; bitpos: [11]; default: 0; - * Configures whether or not to enable channel43. - * 0: Invalid. No effect + * Configures whether or not to enable ch43. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable43:1; /** ch_enable44 : WT; bitpos: [12]; default: 0; - * Configures whether or not to enable channel44. - * 0: Invalid. No effect + * Configures whether or not to enable ch44. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable44:1; /** ch_enable45 : WT; bitpos: [13]; default: 0; - * Configures whether or not to enable channel45. - * 0: Invalid. No effect + * Configures whether or not to enable ch45. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable45:1; /** ch_enable46 : WT; bitpos: [14]; default: 0; - * Configures whether or not to enable channel46. - * 0: Invalid. No effect + * Configures whether or not to enable ch46. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable46:1; /** ch_enable47 : WT; bitpos: [15]; default: 0; - * Configures whether or not to enable channel47. - * 0: Invalid. No effect + * Configures whether or not to enable ch47. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable47:1; /** ch_enable48 : WT; bitpos: [16]; default: 0; - * Configures whether or not to enable channel48. - * 0: Invalid. No effect + * Configures whether or not to enable ch48. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable48:1; /** ch_enable49 : WT; bitpos: [17]; default: 0; - * Configures whether or not to enable channel49. - * 0: Invalid. No effect + * Configures whether or not to enable ch49. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable49:1; @@ -2166,115 +2406,115 @@ typedef union { } soc_etm_ch_ena_ad1_set_reg_t; /** Type of ch_ena_ad1_clr register - * Channel disable register + * Channel enable clear register */ typedef union { struct { /** ch_disable32 : WT; bitpos: [0]; default: 0; - * Configures whether or not to disable channel32. - * 0: Invalid. No effect + * Configures whether or not to clear ch32 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable32:1; /** ch_disable33 : WT; bitpos: [1]; default: 0; - * Configures whether or not to disable channel33. - * 0: Invalid. No effect + * Configures whether or not to clear ch33 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable33:1; /** ch_disable34 : WT; bitpos: [2]; default: 0; - * Configures whether or not to disable channel34. - * 0: Invalid. No effect + * Configures whether or not to clear ch34 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable34:1; /** ch_disable35 : WT; bitpos: [3]; default: 0; - * Configures whether or not to disable channel35. - * 0: Invalid. No effect + * Configures whether or not to clear ch35 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable35:1; /** ch_disable36 : WT; bitpos: [4]; default: 0; - * Configures whether or not to disable channel36. - * 0: Invalid. No effect + * Configures whether or not to clear ch36 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable36:1; /** ch_disable37 : WT; bitpos: [5]; default: 0; - * Configures whether or not to disable channel37. - * 0: Invalid. No effect + * Configures whether or not to clear ch37 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable37:1; /** ch_disable38 : WT; bitpos: [6]; default: 0; - * Configures whether or not to disable channel38. - * 0: Invalid. No effect + * Configures whether or not to clear ch38 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable38:1; /** ch_disable39 : WT; bitpos: [7]; default: 0; - * Configures whether or not to disable channel39. - * 0: Invalid. No effect + * Configures whether or not to clear ch39 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable39:1; /** ch_disable40 : WT; bitpos: [8]; default: 0; - * Configures whether or not to disable channel40. - * 0: Invalid. No effect + * Configures whether or not to clear ch40 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable40:1; /** ch_disable41 : WT; bitpos: [9]; default: 0; - * Configures whether or not to disable channel41. - * 0: Invalid. No effect + * Configures whether or not to clear ch41 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable41:1; /** ch_disable42 : WT; bitpos: [10]; default: 0; - * Configures whether or not to disable channel42. - * 0: Invalid. No effect + * Configures whether or not to clear ch42 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable42:1; /** ch_disable43 : WT; bitpos: [11]; default: 0; - * Configures whether or not to disable channel43. - * 0: Invalid. No effect + * Configures whether or not to clear ch43 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable43:1; /** ch_disable44 : WT; bitpos: [12]; default: 0; - * Configures whether or not to disable channel44. - * 0: Invalid. No effect + * Configures whether or not to clear ch44 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable44:1; /** ch_disable45 : WT; bitpos: [13]; default: 0; - * Configures whether or not to disable channel45. - * 0: Invalid. No effect + * Configures whether or not to clear ch45 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable45:1; /** ch_disable46 : WT; bitpos: [14]; default: 0; - * Configures whether or not to disable channel46. - * 0: Invalid. No effect + * Configures whether or not to clear ch46 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable46:1; /** ch_disable47 : WT; bitpos: [15]; default: 0; - * Configures whether or not to disable channel47. - * 0: Invalid. No effect + * Configures whether or not to clear ch47 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable47:1; /** ch_disable48 : WT; bitpos: [16]; default: 0; - * Configures whether or not to disable channel48. - * 0: Invalid. No effect + * Configures whether or not to clear ch48 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable48:1; /** ch_disable49 : WT; bitpos: [17]; default: 0; - * Configures whether or not to disable channel49. - * 0: Invalid. No effect + * Configures whether or not to clear ch49 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable49:1; @@ -2283,13 +2523,13 @@ typedef union { uint32_t val; } soc_etm_ch_ena_ad1_clr_reg_t; -/** Type of chn_evt_id register - * Channeln event ID register +/** Type of ch_evt_id register + * Channel0 event id register */ typedef union { struct { - /** chn_evt_id : R/W; bitpos: [6:0]; default: 0; - * Configures channeln event ID. + /** ch_evt_id : R/W; bitpos: [6:0]; default: 0; + * Configures ch_evt_id */ uint32_t chn_evt_id:7; uint32_t reserved_7:25; @@ -2297,13 +2537,13 @@ typedef union { uint32_t val; } soc_etm_chn_evt_id_reg_t; -/** Type of chn_task_id register - * Channeln task ID register +/** Type of ch_task_id register + * Channel0 task id register */ typedef union { struct { - /** chn_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures channeln task ID. + /** ch_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch_task_id */ uint32_t chn_task_id:8; uint32_t reserved_8:24; @@ -2312,188 +2552,199 @@ typedef union { } soc_etm_chn_task_id_reg_t; /** Type of evt_st0_clr register - * Event trigger status clear register + * Events trigger status clear register */ typedef union { struct { /** gpio_evt_ch0_rise_edge_st_clr : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH0_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch0_rise_edge_st_clr:1; /** gpio_evt_ch1_rise_edge_st_clr : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH1_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch1_rise_edge_st_clr:1; /** gpio_evt_ch2_rise_edge_st_clr : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH2_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch2_rise_edge_st_clr:1; /** gpio_evt_ch3_rise_edge_st_clr : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH3_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch3_rise_edge_st_clr:1; /** gpio_evt_ch4_rise_edge_st_clr : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH4_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch4_rise_edge_st_clr:1; /** gpio_evt_ch5_rise_edge_st_clr : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH5_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch5_rise_edge_st_clr:1; /** gpio_evt_ch6_rise_edge_st_clr : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH6_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch6_rise_edge_st_clr:1; /** gpio_evt_ch7_rise_edge_st_clr : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH7_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch7_rise_edge_st_clr:1; /** gpio_evt_ch0_fall_edge_st_clr : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH0_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch0_fall_edge_st_clr:1; /** gpio_evt_ch1_fall_edge_st_clr : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH1_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch1_fall_edge_st_clr:1; /** gpio_evt_ch2_fall_edge_st_clr : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH2_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch2_fall_edge_st_clr:1; /** gpio_evt_ch3_fall_edge_st_clr : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH3_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch3_fall_edge_st_clr:1; /** gpio_evt_ch4_fall_edge_st_clr : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH4_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch4_fall_edge_st_clr:1; /** gpio_evt_ch5_fall_edge_st_clr : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH5_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch5_fall_edge_st_clr:1; /** gpio_evt_ch6_fall_edge_st_clr : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH6_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch6_fall_edge_st_clr:1; /** gpio_evt_ch7_fall_edge_st_clr : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH7_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch7_fall_edge_st_clr:1; /** gpio_evt_ch0_any_edge_st_clr : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH0_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch0_any_edge_st_clr:1; /** gpio_evt_ch1_any_edge_st_clr : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH1_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch1_any_edge_st_clr:1; /** gpio_evt_ch2_any_edge_st_clr : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH2_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch2_any_edge_st_clr:1; /** gpio_evt_ch3_any_edge_st_clr : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH3_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch3_any_edge_st_clr:1; /** gpio_evt_ch4_any_edge_st_clr : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH4_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch4_any_edge_st_clr:1; /** gpio_evt_ch5_any_edge_st_clr : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH5_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch5_any_edge_st_clr:1; /** gpio_evt_ch6_any_edge_st_clr : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH6_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch6_any_edge_st_clr:1; /** gpio_evt_ch7_any_edge_st_clr : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH7_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch7_any_edge_st_clr:1; /** gpio_evt_zero_det_pos0_st_clr : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear GPIO_EVT_ZERO_DET_POS0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_zero_det_pos0_st_clr:1; /** gpio_evt_zero_det_neg0_st_clr : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear GPIO_EVT_ZERO_DET_NEG0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_zero_det_neg0_st_clr:1; - uint32_t reserved_26:2; + /** gpio_evt_zero_det_pos1_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gpio_evt_zero_det_pos1_st_clr:1; + /** gpio_evt_zero_det_neg1_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gpio_evt_zero_det_neg1_st_clr:1; /** ledc_evt_duty_chng_end_ch0_st_clr : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_duty_chng_end_ch0_st_clr:1; /** ledc_evt_duty_chng_end_ch1_st_clr : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_duty_chng_end_ch1_st_clr:1; /** ledc_evt_duty_chng_end_ch2_st_clr : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_duty_chng_end_ch2_st_clr:1; /** ledc_evt_duty_chng_end_ch3_st_clr : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_duty_chng_end_ch3_st_clr:1; @@ -2502,298 +2753,400 @@ typedef union { } soc_etm_evt_st0_clr_reg_t; /** Type of evt_st1_clr register - * Event trigger status clear register + * Events trigger status clear register */ typedef union { struct { /** ledc_evt_duty_chng_end_ch4_st_clr : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_duty_chng_end_ch4_st_clr:1; /** ledc_evt_duty_chng_end_ch5_st_clr : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_duty_chng_end_ch5_st_clr:1; /** ledc_evt_ovf_cnt_pls_ch0_st_clr : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_ovf_cnt_pls_ch0_st_clr:1; /** ledc_evt_ovf_cnt_pls_ch1_st_clr : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_ovf_cnt_pls_ch1_st_clr:1; /** ledc_evt_ovf_cnt_pls_ch2_st_clr : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_ovf_cnt_pls_ch2_st_clr:1; /** ledc_evt_ovf_cnt_pls_ch3_st_clr : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_ovf_cnt_pls_ch3_st_clr:1; /** ledc_evt_ovf_cnt_pls_ch4_st_clr : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_ovf_cnt_pls_ch4_st_clr:1; /** ledc_evt_ovf_cnt_pls_ch5_st_clr : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_ovf_cnt_pls_ch5_st_clr:1; /** ledc_evt_time_ovf_timer0_st_clr : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_time_ovf_timer0_st_clr:1; /** ledc_evt_time_ovf_timer1_st_clr : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_time_ovf_timer1_st_clr:1; /** ledc_evt_time_ovf_timer2_st_clr : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_time_ovf_timer2_st_clr:1; /** ledc_evt_time_ovf_timer3_st_clr : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_time_ovf_timer3_st_clr:1; /** ledc_evt_timer0_cmp_st_clr : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIMER0_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_timer0_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_timer0_cmp_st_clr:1; /** ledc_evt_timer1_cmp_st_clr : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIMER1_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_timer1_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_timer1_cmp_st_clr:1; /** ledc_evt_timer2_cmp_st_clr : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIMER2_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_timer2_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_timer2_cmp_st_clr:1; /** ledc_evt_timer3_cmp_st_clr : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIMER3_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_timer3_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_timer3_cmp_st_clr:1; /** tg0_evt_cnt_cmp_timer0_st_clr : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear TG0_EVT_CNT_CMP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_evt_cnt_cmp_timer0_st_clr:1; /** tg0_evt_cnt_cmp_timer1_st_clr : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear TG0_EVT_CNT_CMP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_evt_cnt_cmp_timer1_st_clr:1; /** tg1_evt_cnt_cmp_timer0_st_clr : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear TG1_EVT_CNT_CMP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_evt_cnt_cmp_timer0_st_clr:1; /** tg1_evt_cnt_cmp_timer1_st_clr : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear TG1_EVT_CNT_CMP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_evt_cnt_cmp_timer1_st_clr:1; /** systimer_evt_cnt_cmp0_st_clr : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear SYSTIMER_EVT_CNT_CMP0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t systimer_evt_cnt_cmp0_st_clr:1; /** systimer_evt_cnt_cmp1_st_clr : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear SYSTIMER_EVT_CNT_CMP1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t systimer_evt_cnt_cmp1_st_clr:1; /** systimer_evt_cnt_cmp2_st_clr : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear SYSTIMER_EVT_CNT_CMP2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t systimer_evt_cnt_cmp2_st_clr:1; /** adc_evt_conv_cmplt0_st_clr : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear ADC_EVT_CONV_CMPLT0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_evt_conv_cmplt0_st_clr:1; /** adc_evt_eq_above_thresh0_st_clr : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear ADC_EVT_EQ_ABOVE_THRESH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_evt_eq_above_thresh0_st_clr:1; /** adc_evt_eq_above_thresh1_st_clr : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear ADC_EVT_EQ_ABOVE_THRESH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_evt_eq_above_thresh1_st_clr:1; /** adc_evt_eq_below_thresh0_st_clr : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear ADC_EVT_EQ_BELOW_THRESH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_evt_eq_below_thresh0_st_clr:1; /** adc_evt_eq_below_thresh1_st_clr : WT; bitpos: [27]; default: 0; - * Configures whether or not to clear ADC_EVT_EQ_BELOW_THRESH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_evt_eq_below_thresh1_st_clr:1; /** adc_evt_result_done0_st_clr : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear ADC_EVT_RESULT_DONE0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_result_done0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_evt_result_done0_st_clr:1; /** adc_evt_stopped0_st_clr : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear ADC_EVT_STOPPED0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_stopped0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_evt_stopped0_st_clr:1; /** adc_evt_started0_st_clr : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear ADC_EVT_STARTED0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_started0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_evt_started0_st_clr:1; - uint32_t reserved_31:1; + /** regdma_evt_done0_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear REGDMA_evt_done0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_evt_done0_st_clr:1; }; uint32_t val; } soc_etm_evt_st1_clr_reg_t; /** Type of evt_st2_clr register - * Event trigger status clear register + * Events trigger status clear register */ typedef union { struct { - uint32_t reserved_0:7; + /** regdma_evt_done1_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear REGDMA_evt_done1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_evt_done1_st_clr:1; + /** regdma_evt_done2_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear REGDMA_evt_done2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_evt_done2_st_clr:1; + /** regdma_evt_done3_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear REGDMA_evt_done3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_evt_done3_st_clr:1; + /** regdma_evt_err0_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear REGDMA_evt_err0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_evt_err0_st_clr:1; + /** regdma_evt_err1_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear REGDMA_evt_err1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_evt_err1_st_clr:1; + /** regdma_evt_err2_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear REGDMA_evt_err2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_evt_err2_st_clr:1; + /** regdma_evt_err3_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear REGDMA_evt_err3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_evt_err3_st_clr:1; /** tmpsnsr_evt_over_limit_st_clr : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear TMPSNSR_EVT_OVER_LIMIT trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TMPSNSR_evt_over_limit trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tmpsnsr_evt_over_limit_st_clr:1; /** i2s0_evt_rx_done_st_clr : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear I2S0_EVT_RX_DONE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_evt_rx_done trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t i2s0_evt_rx_done_st_clr:1; /** i2s0_evt_tx_done_st_clr : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear I2S0_EVT_TX_DONE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_evt_tx_done trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t i2s0_evt_tx_done_st_clr:1; /** i2s0_evt_x_words_received_st_clr : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear I2S0_EVT_X_WORDS_RECEIVED trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_evt_x_words_received trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t i2s0_evt_x_words_received_st_clr:1; /** i2s0_evt_x_words_sent_st_clr : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear I2S0_EVT_X_WORDS_SENT trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_evt_x_words_sent trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t i2s0_evt_x_words_sent_st_clr:1; - uint32_t reserved_12:7; + /** i2s1_evt_rx_done_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear I2S1_evt_rx_done trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t i2s1_evt_rx_done_st_clr:1; + /** i2s1_evt_tx_done_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear I2S1_evt_tx_done trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t i2s1_evt_tx_done_st_clr:1; + /** i2s1_evt_x_words_received_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear I2S1_evt_x_words_received trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t i2s1_evt_x_words_received_st_clr:1; + /** i2s1_evt_x_words_sent_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear I2S1_evt_x_words_sent trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t i2s1_evt_x_words_sent_st_clr:1; + /** ulp_evt_err_intr_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ULP_evt_err_intr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t ulp_evt_err_intr_st_clr:1; + /** ulp_evt_halt_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ULP_evt_halt trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t ulp_evt_halt_st_clr:1; + /** ulp_evt_start_intr_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear ULP_evt_start_intr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t ulp_evt_start_intr_st_clr:1; /** rtc_evt_tick_st_clr : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear RTC_EVT_TICK trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear RTC_evt_tick trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t rtc_evt_tick_st_clr:1; /** rtc_evt_ovf_st_clr : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear RTC_EVT_OVF trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear RTC_evt_ovf trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t rtc_evt_ovf_st_clr:1; /** rtc_evt_cmp_st_clr : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear RTC_EVT_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear RTC_evt_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t rtc_evt_cmp_st_clr:1; /** gdma_ahb_evt_in_done_ch0_st_clr : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_DONE_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_done_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_in_done_ch0_st_clr:1; /** gdma_ahb_evt_in_done_ch1_st_clr : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_DONE_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_done_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_in_done_ch1_st_clr:1; - uint32_t reserved_24:1; + /** gdma_ahb_evt_in_done_ch2_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_done_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_evt_in_done_ch2_st_clr:1; /** gdma_ahb_evt_in_suc_eof_ch0_st_clr : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_SUC_EOF_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_suc_eof_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_in_suc_eof_ch0_st_clr:1; /** gdma_ahb_evt_in_suc_eof_ch1_st_clr : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_SUC_EOF_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_suc_eof_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_in_suc_eof_ch1_st_clr:1; - uint32_t reserved_27:1; + /** gdma_ahb_evt_in_suc_eof_ch2_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_suc_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_evt_in_suc_eof_ch2_st_clr:1; /** gdma_ahb_evt_in_fifo_empty_ch0_st_clr : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_empty_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_in_fifo_empty_ch0_st_clr:1; /** gdma_ahb_evt_in_fifo_empty_ch1_st_clr : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_empty_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_in_fifo_empty_ch1_st_clr:1; - uint32_t reserved_30:1; + /** gdma_ahb_evt_in_fifo_empty_ch2_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_empty_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_evt_in_fifo_empty_ch2_st_clr:1; /** gdma_ahb_evt_in_fifo_full_ch0_st_clr : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_FIFO_FULL_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_full_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_in_fifo_full_ch0_st_clr:1; @@ -2802,85 +3155,115 @@ typedef union { } soc_etm_evt_st2_clr_reg_t; /** Type of evt_st3_clr register - * Event trigger status clear register + * Events trigger status clear register */ typedef union { struct { /** gdma_ahb_evt_in_fifo_full_ch1_st_clr : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_FIFO_FULL_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_full_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_in_fifo_full_ch1_st_clr:1; - uint32_t reserved_1:1; + /** gdma_ahb_evt_in_fifo_full_ch2_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_full_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_evt_in_fifo_full_ch2_st_clr:1; /** gdma_ahb_evt_out_done_ch0_st_clr : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_DONE_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_done_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_done_ch0_st_clr:1; /** gdma_ahb_evt_out_done_ch1_st_clr : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_DONE_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_done_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_done_ch1_st_clr:1; - uint32_t reserved_4:1; + /** gdma_ahb_evt_out_done_ch2_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_done_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_evt_out_done_ch2_st_clr:1; /** gdma_ahb_evt_out_eof_ch0_st_clr : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_EOF_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_eof_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_eof_ch0_st_clr:1; /** gdma_ahb_evt_out_eof_ch1_st_clr : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_EOF_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_eof_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_eof_ch1_st_clr:1; - uint32_t reserved_7:1; + /** gdma_ahb_evt_out_eof_ch2_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_evt_out_eof_ch2_st_clr:1; /** gdma_ahb_evt_out_total_eof_ch0_st_clr : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_total_eof_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_total_eof_ch0_st_clr:1; /** gdma_ahb_evt_out_total_eof_ch1_st_clr : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_total_eof_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_total_eof_ch1_st_clr:1; - uint32_t reserved_10:1; + /** gdma_ahb_evt_out_total_eof_ch2_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_total_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_evt_out_total_eof_ch2_st_clr:1; /** gdma_ahb_evt_out_fifo_empty_ch0_st_clr : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_empty_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_fifo_empty_ch0_st_clr:1; /** gdma_ahb_evt_out_fifo_empty_ch1_st_clr : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_empty_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_fifo_empty_ch1_st_clr:1; - uint32_t reserved_13:1; + /** gdma_ahb_evt_out_fifo_empty_ch2_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_empty_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_evt_out_fifo_empty_ch2_st_clr:1; /** gdma_ahb_evt_out_fifo_full_ch0_st_clr : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_FIFO_FULL_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_full_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_fifo_full_ch0_st_clr:1; /** gdma_ahb_evt_out_fifo_full_ch1_st_clr : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_FIFO_FULL_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_full_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_fifo_full_ch1_st_clr:1; - uint32_t reserved_16:1; + /** gdma_ahb_evt_out_fifo_full_ch2_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_full_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_evt_out_fifo_full_ch2_st_clr:1; /** pmu_evt_sleep_weekup_st_clr : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear PMU_EVT_SLEEP_WEEKUP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear PMU_evt_sleep_weekup trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t pmu_evt_sleep_weekup_st_clr:1; @@ -2890,199 +3273,199 @@ typedef union { } soc_etm_evt_st3_clr_reg_t; /** Type of task_st0_clr register - * Task trigger status clear register + * Tasks trigger status clear register */ typedef union { struct { /** gpio_task_ch0_set_st_clr : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH0_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch0_set trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch0_set_st_clr:1; /** gpio_task_ch1_set_st_clr : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH1_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch1_set trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch1_set_st_clr:1; /** gpio_task_ch2_set_st_clr : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH2_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch2_set trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch2_set_st_clr:1; /** gpio_task_ch3_set_st_clr : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH3_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch3_set trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch3_set_st_clr:1; /** gpio_task_ch4_set_st_clr : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH4_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch4_set trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch4_set_st_clr:1; /** gpio_task_ch5_set_st_clr : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH5_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch5_set trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch5_set_st_clr:1; /** gpio_task_ch6_set_st_clr : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH6_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch6_set trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch6_set_st_clr:1; /** gpio_task_ch7_set_st_clr : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH7_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch7_set trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch7_set_st_clr:1; /** gpio_task_ch0_clear_st_clr : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH0_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch0_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch0_clear_st_clr:1; /** gpio_task_ch1_clear_st_clr : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH1_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch1_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch1_clear_st_clr:1; /** gpio_task_ch2_clear_st_clr : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH2_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch2_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch2_clear_st_clr:1; /** gpio_task_ch3_clear_st_clr : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH3_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch3_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch3_clear_st_clr:1; /** gpio_task_ch4_clear_st_clr : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH4_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch4_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch4_clear_st_clr:1; /** gpio_task_ch5_clear_st_clr : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH5_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch5_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch5_clear_st_clr:1; /** gpio_task_ch6_clear_st_clr : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH6_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch6_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch6_clear_st_clr:1; /** gpio_task_ch7_clear_st_clr : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH7_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch7_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch7_clear_st_clr:1; /** gpio_task_ch0_toggle_st_clr : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH0_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch0_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch0_toggle_st_clr:1; /** gpio_task_ch1_toggle_st_clr : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH1_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch1_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch1_toggle_st_clr:1; /** gpio_task_ch2_toggle_st_clr : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH2_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch2_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch2_toggle_st_clr:1; /** gpio_task_ch3_toggle_st_clr : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH3_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch3_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch3_toggle_st_clr:1; /** gpio_task_ch4_toggle_st_clr : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH4_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch4_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch4_toggle_st_clr:1; /** gpio_task_ch5_toggle_st_clr : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH5_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch5_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch5_toggle_st_clr:1; /** gpio_task_ch6_toggle_st_clr : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH6_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch6_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch6_toggle_st_clr:1; /** gpio_task_ch7_toggle_st_clr : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH7_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch7_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch7_toggle_st_clr:1; /** ledc_task_timer0_res_update_st_clr : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_RES_UPDATE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_res_update trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer0_res_update_st_clr:1; /** ledc_task_timer1_res_update_st_clr : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_RES_UPDATE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_res_update trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer1_res_update_st_clr:1; /** ledc_task_timer2_res_update_st_clr : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_RES_UPDATE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_res_update trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer2_res_update_st_clr:1; /** ledc_task_timer3_res_update_st_clr : WT; bitpos: [27]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_RES_UPDATE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_res_update trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer3_res_update_st_clr:1; /** ledc_task_duty_scale_update_ch0_st_clr : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_duty_scale_update_ch0_st_clr:1; /** ledc_task_duty_scale_update_ch1_st_clr : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_duty_scale_update_ch1_st_clr:1; /** ledc_task_duty_scale_update_ch2_st_clr : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_duty_scale_update_ch2_st_clr:1; /** ledc_task_duty_scale_update_ch3_st_clr : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_duty_scale_update_ch3_st_clr:1; @@ -3091,199 +3474,199 @@ typedef union { } soc_etm_task_st0_clr_reg_t; /** Type of task_st1_clr register - * Task trigger status clear register + * Tasks trigger status clear register */ typedef union { struct { /** ledc_task_duty_scale_update_ch4_st_clr : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_duty_scale_update_ch4_st_clr:1; /** ledc_task_duty_scale_update_ch5_st_clr : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_duty_scale_update_ch5_st_clr:1; /** ledc_task_timer0_cap_st_clr : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_CAP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_cap trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer0_cap_st_clr:1; /** ledc_task_timer1_cap_st_clr : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_CAP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_cap trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer1_cap_st_clr:1; /** ledc_task_timer2_cap_st_clr : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_CAP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_cap trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer2_cap_st_clr:1; /** ledc_task_timer3_cap_st_clr : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_CAP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_cap trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer3_cap_st_clr:1; /** ledc_task_sig_out_dis_ch0_st_clr : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_sig_out_dis_ch0_st_clr:1; /** ledc_task_sig_out_dis_ch1_st_clr : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_sig_out_dis_ch1_st_clr:1; /** ledc_task_sig_out_dis_ch2_st_clr : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_sig_out_dis_ch2_st_clr:1; /** ledc_task_sig_out_dis_ch3_st_clr : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_sig_out_dis_ch3_st_clr:1; /** ledc_task_sig_out_dis_ch4_st_clr : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_sig_out_dis_ch4_st_clr:1; /** ledc_task_sig_out_dis_ch5_st_clr : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_sig_out_dis_ch5_st_clr:1; /** ledc_task_ovf_cnt_rst_ch0_st_clr : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_ovf_cnt_rst_ch0_st_clr:1; /** ledc_task_ovf_cnt_rst_ch1_st_clr : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_ovf_cnt_rst_ch1_st_clr:1; /** ledc_task_ovf_cnt_rst_ch2_st_clr : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_ovf_cnt_rst_ch2_st_clr:1; /** ledc_task_ovf_cnt_rst_ch3_st_clr : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_ovf_cnt_rst_ch3_st_clr:1; /** ledc_task_ovf_cnt_rst_ch4_st_clr : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_ovf_cnt_rst_ch4_st_clr:1; /** ledc_task_ovf_cnt_rst_ch5_st_clr : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_ovf_cnt_rst_ch5_st_clr:1; /** ledc_task_timer0_rst_st_clr : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_RST trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_rst trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer0_rst_st_clr:1; /** ledc_task_timer1_rst_st_clr : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_RST trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_rst trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer1_rst_st_clr:1; /** ledc_task_timer2_rst_st_clr : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_RST trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_rst trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer2_rst_st_clr:1; /** ledc_task_timer3_rst_st_clr : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_RST trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_rst trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer3_rst_st_clr:1; /** ledc_task_timer0_resume_st_clr : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_RESUME trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_resume trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer0_resume_st_clr:1; /** ledc_task_timer1_resume_st_clr : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_RESUME trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_resume trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer1_resume_st_clr:1; /** ledc_task_timer2_resume_st_clr : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_RESUME trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_resume trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer2_resume_st_clr:1; /** ledc_task_timer3_resume_st_clr : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_RESUME trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_resume trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer3_resume_st_clr:1; /** ledc_task_timer0_pause_st_clr : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_PAUSE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_pause trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer0_pause_st_clr:1; /** ledc_task_timer1_pause_st_clr : WT; bitpos: [27]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_PAUSE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_pause trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer1_pause_st_clr:1; /** ledc_task_timer2_pause_st_clr : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_PAUSE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_pause trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer2_pause_st_clr:1; /** ledc_task_timer3_pause_st_clr : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_PAUSE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_pause trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer3_pause_st_clr:1; /** ledc_task_gamma_restart_ch0_st_clr : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_restart_ch0_st_clr:1; /** ledc_task_gamma_restart_ch1_st_clr : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_restart_ch1_st_clr:1; @@ -3292,199 +3675,199 @@ typedef union { } soc_etm_task_st1_clr_reg_t; /** Type of task_st2_clr register - * Task trigger status clear register + * Tasks trigger status clear register */ typedef union { struct { /** ledc_task_gamma_restart_ch2_st_clr : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_restart_ch2_st_clr:1; /** ledc_task_gamma_restart_ch3_st_clr : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_restart_ch3_st_clr:1; /** ledc_task_gamma_restart_ch4_st_clr : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_restart_ch4_st_clr:1; /** ledc_task_gamma_restart_ch5_st_clr : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_restart_ch5_st_clr:1; /** ledc_task_gamma_pause_ch0_st_clr : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_pause_ch0_st_clr:1; /** ledc_task_gamma_pause_ch1_st_clr : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_pause_ch1_st_clr:1; /** ledc_task_gamma_pause_ch2_st_clr : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_pause_ch2_st_clr:1; /** ledc_task_gamma_pause_ch3_st_clr : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_pause_ch3_st_clr:1; /** ledc_task_gamma_pause_ch4_st_clr : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_pause_ch4_st_clr:1; /** ledc_task_gamma_pause_ch5_st_clr : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_pause_ch5_st_clr:1; /** ledc_task_gamma_resume_ch0_st_clr : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_resume_ch0_st_clr:1; /** ledc_task_gamma_resume_ch1_st_clr : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_resume_ch1_st_clr:1; /** ledc_task_gamma_resume_ch2_st_clr : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_resume_ch2_st_clr:1; /** ledc_task_gamma_resume_ch3_st_clr : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_resume_ch3_st_clr:1; /** ledc_task_gamma_resume_ch4_st_clr : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_resume_ch4_st_clr:1; /** ledc_task_gamma_resume_ch5_st_clr : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_resume_ch5_st_clr:1; /** tg0_task_cnt_start_timer0_st_clr : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_START_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_cnt_start_timer0_st_clr:1; /** tg0_task_alarm_start_timer0_st_clr : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear TG0_TASK_ALARM_START_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_alarm_start_timer0_st_clr:1; /** tg0_task_cnt_stop_timer0_st_clr : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_STOP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_cnt_stop_timer0_st_clr:1; /** tg0_task_cnt_reload_timer0_st_clr : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_RELOAD_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_cnt_reload_timer0_st_clr:1; /** tg0_task_cnt_cap_timer0_st_clr : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_CAP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_cnt_cap_timer0_st_clr:1; /** tg0_task_cnt_start_timer1_st_clr : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_START_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_cnt_start_timer1_st_clr:1; /** tg0_task_alarm_start_timer1_st_clr : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear TG0_TASK_ALARM_START_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_alarm_start_timer1_st_clr:1; /** tg0_task_cnt_stop_timer1_st_clr : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_STOP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_cnt_stop_timer1_st_clr:1; /** tg0_task_cnt_reload_timer1_st_clr : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_RELOAD_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_cnt_reload_timer1_st_clr:1; /** tg0_task_cnt_cap_timer1_st_clr : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_CAP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_cnt_cap_timer1_st_clr:1; /** tg1_task_cnt_start_timer0_st_clr : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_START_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_cnt_start_timer0_st_clr:1; /** tg1_task_alarm_start_timer0_st_clr : WT; bitpos: [27]; default: 0; - * Configures whether or not to clear TG1_TASK_ALARM_START_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_alarm_start_timer0_st_clr:1; /** tg1_task_cnt_stop_timer0_st_clr : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_STOP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_cnt_stop_timer0_st_clr:1; /** tg1_task_cnt_reload_timer0_st_clr : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_RELOAD_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_cnt_reload_timer0_st_clr:1; /** tg1_task_cnt_cap_timer0_st_clr : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_CAP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_cnt_cap_timer0_st_clr:1; /** tg1_task_cnt_start_timer1_st_clr : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_START_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_cnt_start_timer1_st_clr:1; @@ -3493,107 +3876,199 @@ typedef union { } soc_etm_task_st2_clr_reg_t; /** Type of task_st3_clr register - * Task trigger status clear register + * Tasks trigger status clear register */ typedef union { struct { /** tg1_task_alarm_start_timer1_st_clr : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear TG1_TASK_ALARM_START_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_alarm_start_timer1_st_clr:1; /** tg1_task_cnt_stop_timer1_st_clr : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_STOP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_cnt_stop_timer1_st_clr:1; /** tg1_task_cnt_reload_timer1_st_clr : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_RELOAD_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_cnt_reload_timer1_st_clr:1; /** tg1_task_cnt_cap_timer1_st_clr : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_CAP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_cnt_cap_timer1_st_clr:1; /** adc_task_sample0_st_clr : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear ADC_TASK_SAMPLE0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_task_sample0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_task_sample0_st_clr:1; - uint32_t reserved_5:1; + /** adc_task_sample1_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ADC_task_sample1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t adc_task_sample1_st_clr:1; /** adc_task_start0_st_clr : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear ADC_TASK_START0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_task_start0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_task_start0_st_clr:1; /** adc_task_stop0_st_clr : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear ADC_TASK_STOP0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_task_stop0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_task_stop0_st_clr:1; - uint32_t reserved_8:4; + /** regdma_task_start0_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear REGDMA_task_start0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_task_start0_st_clr:1; + /** regdma_task_start1_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear REGDMA_task_start1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_task_start1_st_clr:1; + /** regdma_task_start2_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear REGDMA_task_start2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_task_start2_st_clr:1; + /** regdma_task_start3_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear REGDMA_task_start3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_task_start3_st_clr:1; /** tmpsnsr_task_start_sample_st_clr : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear TMPSNSR_TASK_START_SAMPLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TMPSNSR_task_start_sample trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tmpsnsr_task_start_sample_st_clr:1; /** tmpsnsr_task_stop_sample_st_clr : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear TMPSNSR_TASK_STOP_SAMPLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TMPSNSR_task_stop_sample trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tmpsnsr_task_stop_sample_st_clr:1; /** i2s0_task_start_rx_st_clr : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear I2S0_TASK_START_RX trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_task_start_rx trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t i2s0_task_start_rx_st_clr:1; /** i2s0_task_start_tx_st_clr : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear I2S0_TASK_START_TX trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_task_start_tx trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t i2s0_task_start_tx_st_clr:1; /** i2s0_task_stop_rx_st_clr : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear I2S0_TASK_STOP_RX trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_task_stop_rx trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t i2s0_task_stop_rx_st_clr:1; /** i2s0_task_stop_tx_st_clr : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear I2S0_TASK_STOP_TX trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_task_stop_tx trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t i2s0_task_stop_tx_st_clr:1; - uint32_t reserved_18:10; + /** i2s1_task_start_rx_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear I2S1_task_start_rx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t i2s1_task_start_rx_st_clr:1; + /** i2s1_task_start_tx_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear I2S1_task_start_tx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t i2s1_task_start_tx_st_clr:1; + /** i2s1_task_stop_rx_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear I2S1_task_stop_rx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t i2s1_task_stop_rx_st_clr:1; + /** i2s1_task_stop_tx_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear I2S1_task_stop_tx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t i2s1_task_stop_tx_st_clr:1; + /** ulp_task_wakeup_cpu_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear ULP_task_wakeup_cpu trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t ulp_task_wakeup_cpu_st_clr:1; + /** ulp_task_int_cpu_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear ULP_task_int_cpu trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t ulp_task_int_cpu_st_clr:1; + /** rtc_task_start_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear RTC_task_start trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t rtc_task_start_st_clr:1; + /** rtc_task_stop_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear RTC_task_stop trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t rtc_task_stop_st_clr:1; + /** rtc_task_clr_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear RTC_task_clr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t rtc_task_clr_st_clr:1; + /** rtc_task_triggerflw_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear RTC_task_triggerflw trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t rtc_task_triggerflw_st_clr:1; /** gdma_ahb_task_in_start_ch0_st_clr : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear GDMA_AHB_TASK_IN_START_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_task_in_start_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_task_in_start_ch0_st_clr:1; /** gdma_ahb_task_in_start_ch1_st_clr : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear GDMA_AHB_TASK_IN_START_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_task_in_start_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_task_in_start_ch1_st_clr:1; - uint32_t reserved_30:1; + /** gdma_ahb_task_in_start_ch2_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_in_start_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_task_in_start_ch2_st_clr:1; /** gdma_ahb_task_out_start_ch0_st_clr : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear GDMA_AHB_TASK_OUT_START_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_task_out_start_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_task_out_start_ch0_st_clr:1; @@ -3602,20 +4077,25 @@ typedef union { } soc_etm_task_st3_clr_reg_t; /** Type of task_st4_clr register - * Task trigger status clear register + * Tasks trigger status clear register */ typedef union { struct { /** gdma_ahb_task_out_start_ch1_st_clr : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear GDMA_AHB_TASK_OUT_START_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_task_out_start_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_task_out_start_ch1_st_clr:1; - uint32_t reserved_1:1; + /** gdma_ahb_task_out_start_ch2_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_out_start_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_task_out_start_ch2_st_clr:1; /** pmu_task_sleep_req_st_clr : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear PMU_TASK_SLEEP_REQ trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear PMU_task_sleep_req trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t pmu_task_sleep_req_st_clr:1; @@ -3643,12 +4123,12 @@ typedef union { /** Group: Version Register */ /** Type of date register - * Version control register + * ETM date register */ typedef union { struct { /** date : R/W; bitpos: [27:0]; default: 36737361; - * Version control register. + * Configures the version. */ uint32_t date:28; uint32_t reserved_28:4; diff --git a/components/soc/esp32c61/register/soc/spi1_mem_reg.h b/components/soc/esp32c61/register/soc/spi1_mem_reg.h index 73d7b8f526..92bd65ae03 100644 --- a/components/soc/esp32c61/register/soc/spi1_mem_reg.h +++ b/components/soc/esp32c61/register/soc/spi1_mem_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -35,6 +35,7 @@ extern "C" { * In user mode, it is set to indicate that program/erase operation will be triggered. * The bit is combined with spi_mem_usr bit. The bit will be cleared once the * operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_PE (BIT(17)) #define SPI_MEM_FLASH_PE_M (SPI_MEM_FLASH_PE_V << SPI_MEM_FLASH_PE_S) @@ -51,6 +52,7 @@ extern "C" { /** SPI_MEM_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0; * Drive Flash into high performance mode. The bit will be cleared once the operation * done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_HPM (BIT(19)) #define SPI_MEM_FLASH_HPM_M (SPI_MEM_FLASH_HPM_V << SPI_MEM_FLASH_HPM_S) @@ -60,6 +62,7 @@ extern "C" { * This bit combined with reg_resandres bit releases Flash from the power-down state * or high performance mode and obtains the devices ID. The bit will be cleared once * the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_RES (BIT(20)) #define SPI_MEM_FLASH_RES_M (SPI_MEM_FLASH_RES_V << SPI_MEM_FLASH_RES_S) @@ -68,6 +71,7 @@ extern "C" { /** SPI_MEM_FLASH_DP : R/W/SC; bitpos: [21]; default: 0; * Drive Flash into power down. An operation will be triggered when the bit is set. * The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_DP (BIT(21)) #define SPI_MEM_FLASH_DP_M (SPI_MEM_FLASH_DP_V << SPI_MEM_FLASH_DP_S) @@ -76,6 +80,7 @@ extern "C" { /** SPI_MEM_FLASH_CE : R/W/SC; bitpos: [22]; default: 0; * Chip erase enable. Chip erase operation will be triggered when the bit is set. The * bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_CE (BIT(22)) #define SPI_MEM_FLASH_CE_M (SPI_MEM_FLASH_CE_V << SPI_MEM_FLASH_CE_S) @@ -84,6 +89,7 @@ extern "C" { /** SPI_MEM_FLASH_BE : R/W/SC; bitpos: [23]; default: 0; * Block erase enable(32KB) . Block erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_BE (BIT(23)) #define SPI_MEM_FLASH_BE_M (SPI_MEM_FLASH_BE_V << SPI_MEM_FLASH_BE_S) @@ -92,6 +98,7 @@ extern "C" { /** SPI_MEM_FLASH_SE : R/W/SC; bitpos: [24]; default: 0; * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_SE (BIT(24)) #define SPI_MEM_FLASH_SE_M (SPI_MEM_FLASH_SE_V << SPI_MEM_FLASH_SE_S) @@ -101,6 +108,7 @@ extern "C" { * Page program enable(1 byte ~256 bytes data to be programmed). Page program * operation will be triggered when the bit is set. The bit will be cleared once the * operation done .1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_PP (BIT(25)) #define SPI_MEM_FLASH_PP_M (SPI_MEM_FLASH_PP_V << SPI_MEM_FLASH_PP_S) @@ -109,6 +117,7 @@ extern "C" { /** SPI_MEM_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0; * Write status register enable. Write status operation will be triggered when the * bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_WRSR (BIT(26)) #define SPI_MEM_FLASH_WRSR_M (SPI_MEM_FLASH_WRSR_V << SPI_MEM_FLASH_WRSR_S) @@ -117,6 +126,7 @@ extern "C" { /** SPI_MEM_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0; * Read status register-1. Read status operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_RDSR (BIT(27)) #define SPI_MEM_FLASH_RDSR_M (SPI_MEM_FLASH_RDSR_V << SPI_MEM_FLASH_RDSR_S) @@ -125,6 +135,7 @@ extern "C" { /** SPI_MEM_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0; * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be * cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_RDID (BIT(28)) #define SPI_MEM_FLASH_RDID_M (SPI_MEM_FLASH_RDID_V << SPI_MEM_FLASH_RDID_S) @@ -133,6 +144,7 @@ extern "C" { /** SPI_MEM_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0; * Write flash disable. Write disable command will be sent when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_WRDI (BIT(29)) #define SPI_MEM_FLASH_WRDI_M (SPI_MEM_FLASH_WRDI_V << SPI_MEM_FLASH_WRDI_S) @@ -141,6 +153,7 @@ extern "C" { /** SPI_MEM_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0; * Write flash enable. Write enable command will be sent when the bit is set. The bit * will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_WREN (BIT(30)) #define SPI_MEM_FLASH_WREN_M (SPI_MEM_FLASH_WREN_V << SPI_MEM_FLASH_WREN_S) @@ -149,6 +162,7 @@ extern "C" { /** SPI_MEM_FLASH_READ : R/W/SC; bitpos: [31]; default: 0; * Read flash enable. Read flash operation will be triggered when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_READ (BIT(31)) #define SPI_MEM_FLASH_READ_M (SPI_MEM_FLASH_READ_V << SPI_MEM_FLASH_READ_S) @@ -226,6 +240,7 @@ extern "C" { /** SPI_MEM_FCS_CRC_EN : R/W; bitpos: [10]; default: 0; * For SPI1, initialize crc32 module before writing encrypted data to flash. Active * low. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FCS_CRC_EN (BIT(10)) #define SPI_MEM_FCS_CRC_EN_M (SPI_MEM_FCS_CRC_EN_V << SPI_MEM_FCS_CRC_EN_S) @@ -233,6 +248,7 @@ extern "C" { #define SPI_MEM_FCS_CRC_EN_S 10 /** SPI_MEM_TX_CRC_EN : R/W; bitpos: [11]; default: 0; * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_TX_CRC_EN (BIT(11)) #define SPI_MEM_TX_CRC_EN_M (SPI_MEM_TX_CRC_EN_V << SPI_MEM_TX_CRC_EN_S) @@ -256,6 +272,7 @@ extern "C" { /** SPI_MEM_RESANDRES : R/W; bitpos: [15]; default: 1; * The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with * spi_mem_flash_res bit. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_RESANDRES (BIT(15)) #define SPI_MEM_RESANDRES_M (SPI_MEM_RESANDRES_V << SPI_MEM_RESANDRES_S) @@ -292,6 +309,7 @@ extern "C" { /** SPI_MEM_WRSR_2B : R/W; bitpos: [22]; default: 0; * two bytes data will be written to status register when it is set. 1: enable 0: * disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_WRSR_2B (BIT(22)) #define SPI_MEM_WRSR_2B_M (SPI_MEM_WRSR_2B_V << SPI_MEM_WRSR_2B_S) @@ -328,13 +346,21 @@ extern "C" { #define SPI_MEM_CLK_MODE_V 0x00000003U #define SPI_MEM_CLK_MODE_S 0 /** SPI_MEM_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023; - * After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) - * SPI_CLK cycles. + * After RES/DP/HPM/PES command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * + * 128) SPI_CLK cycles. */ #define SPI_MEM_CS_HOLD_DLY_RES 0x000003FFU #define SPI_MEM_CS_HOLD_DLY_RES_M (SPI_MEM_CS_HOLD_DLY_RES_V << SPI_MEM_CS_HOLD_DLY_RES_S) #define SPI_MEM_CS_HOLD_DLY_RES_V 0x000003FFU #define SPI_MEM_CS_HOLD_DLY_RES_S 2 +/** SPI_MEM_CS_HOLD_DLY_PER : R/W; bitpos: [21:12]; default: 1023; + * After PER command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DLY_PER[9:0] * 128) SPI_CLK + * cycles. + */ +#define SPI_MEM_CS_HOLD_DLY_PER 0x000003FFU +#define SPI_MEM_CS_HOLD_DLY_PER_M (SPI_MEM_CS_HOLD_DLY_PER_V << SPI_MEM_CS_HOLD_DLY_PER_S) +#define SPI_MEM_CS_HOLD_DLY_PER_V 0x000003FFU +#define SPI_MEM_CS_HOLD_DLY_PER_S 12 /** SPI_MEM_CTRL2_REG register * SPI1 control2 register. @@ -353,14 +379,14 @@ extern "C" { */ #define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) /** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_CLKCNT_N. */ #define SPI_MEM_CLKCNT_L 0x000000FFU #define SPI_MEM_CLKCNT_L_M (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S) #define SPI_MEM_CLKCNT_L_V 0x000000FFU #define SPI_MEM_CLKCNT_L_S 0 /** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). */ #define SPI_MEM_CLKCNT_H 0x000000FFU #define SPI_MEM_CLKCNT_H_M (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S) @@ -368,7 +394,7 @@ extern "C" { #define SPI_MEM_CLKCNT_H_S 8 /** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(spi_mem_clkcnt_N+1) + * system/(SPI_MEM_CLKCNT_N+1) */ #define SPI_MEM_CLKCNT_N 0x000000FFU #define SPI_MEM_CLKCNT_N_M (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S) @@ -556,6 +582,7 @@ extern "C" { #define SPI_MEM_STATUS_S 0 /** SPI_MEM_WB_MODE : R/W; bitpos: [23:16]; default: 0; * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_WB_MODE 0x000000FFU #define SPI_MEM_WB_MODE_M (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S) @@ -563,6 +590,7 @@ extern "C" { #define SPI_MEM_WB_MODE_S 16 /** SPI_MEM_WB_MODE_BITLEN : R/W; bitpos: [26:24]; default: 0; * Mode bits length for flash fast read mode. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_WB_MODE_BITLEN 0x00000007U #define SPI_MEM_WB_MODE_BITLEN_M (SPI_MEM_WB_MODE_BITLEN_V << SPI_MEM_WB_MODE_BITLEN_S) @@ -570,6 +598,7 @@ extern "C" { #define SPI_MEM_WB_MODE_BITLEN_S 24 /** SPI_MEM_WB_MODE_EN : R/W; bitpos: [27]; default: 0; * Mode bits is valid while this bit is enable. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_WB_MODE_EN (BIT(27)) #define SPI_MEM_WB_MODE_EN_M (SPI_MEM_WB_MODE_EN_V << SPI_MEM_WB_MODE_EN_S) @@ -625,10 +654,13 @@ extern "C" { /** SPI_MEM_CACHE_FCTRL_REG register * SPI1 bit mode control register. + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3c) /** SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_CACHE_USR_ADDR_4BYTE (BIT(1)) #define SPI_MEM_CACHE_USR_ADDR_4BYTE_M (SPI_MEM_CACHE_USR_ADDR_4BYTE_V << SPI_MEM_CACHE_USR_ADDR_4BYTE_S) @@ -637,6 +669,7 @@ extern "C" { /** SPI_MEM_FDIN_DUAL : R/W; bitpos: [3]; default: 0; * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with * spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FDIN_DUAL (BIT(3)) #define SPI_MEM_FDIN_DUAL_M (SPI_MEM_FDIN_DUAL_V << SPI_MEM_FDIN_DUAL_S) @@ -645,6 +678,7 @@ extern "C" { /** SPI_MEM_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FDOUT_DUAL (BIT(4)) #define SPI_MEM_FDOUT_DUAL_M (SPI_MEM_FDOUT_DUAL_V << SPI_MEM_FDOUT_DUAL_S) @@ -653,6 +687,7 @@ extern "C" { /** SPI_MEM_FADDR_DUAL : R/W; bitpos: [5]; default: 0; * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FADDR_DUAL (BIT(5)) #define SPI_MEM_FADDR_DUAL_M (SPI_MEM_FADDR_DUAL_V << SPI_MEM_FADDR_DUAL_S) @@ -661,6 +696,7 @@ extern "C" { /** SPI_MEM_FDIN_QUAD : R/W; bitpos: [6]; default: 0; * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FDIN_QUAD (BIT(6)) #define SPI_MEM_FDIN_QUAD_M (SPI_MEM_FDIN_QUAD_V << SPI_MEM_FDIN_QUAD_S) @@ -669,6 +705,7 @@ extern "C" { /** SPI_MEM_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FDOUT_QUAD (BIT(7)) #define SPI_MEM_FDOUT_QUAD_M (SPI_MEM_FDOUT_QUAD_V << SPI_MEM_FDOUT_QUAD_S) @@ -677,6 +714,7 @@ extern "C" { /** SPI_MEM_FADDR_QUAD : R/W; bitpos: [8]; default: 0; * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FADDR_QUAD (BIT(8)) #define SPI_MEM_FADDR_QUAD_M (SPI_MEM_FADDR_QUAD_V << SPI_MEM_FADDR_QUAD_S) @@ -999,14 +1037,14 @@ extern "C" { #define SPI_MEM_PESR_END_MSK_M (SPI_MEM_PESR_END_MSK_V << SPI_MEM_PESR_END_MSK_S) #define SPI_MEM_PESR_END_MSK_V 0x0000FFFFU #define SPI_MEM_PESR_END_MSK_S 6 -/** SPI_MEM_FMEM_RD_SUS_2B : R/W; bitpos: [22]; default: 0; +/** SPI_FMEM_RD_SUS_2B : R/W; bitpos: [22]; default: 0; * 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when * check flash SUS/SUS1/SUS2 status bit */ -#define SPI_MEM_FMEM_RD_SUS_2B (BIT(22)) -#define SPI_MEM_FMEM_RD_SUS_2B_M (SPI_MEM_FMEM_RD_SUS_2B_V << SPI_MEM_FMEM_RD_SUS_2B_S) -#define SPI_MEM_FMEM_RD_SUS_2B_V 0x00000001U -#define SPI_MEM_FMEM_RD_SUS_2B_S 22 +#define SPI_FMEM_RD_SUS_2B (BIT(22)) +#define SPI_FMEM_RD_SUS_2B_M (SPI_FMEM_RD_SUS_2B_V << SPI_FMEM_RD_SUS_2B_S) +#define SPI_FMEM_RD_SUS_2B_V 0x00000001U +#define SPI_FMEM_RD_SUS_2B_S 22 /** SPI_MEM_PER_END_EN : R/W; bitpos: [23]; default: 0; * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of * flash. 0: Only need to check WIP is 0. @@ -1361,110 +1399,110 @@ extern "C" { * SPI1 DDR control register */ #define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xd4) -/** SPI_MEM_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0; +/** SPI_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0; * 1: in ddr mode, 0 in sdr mode */ -#define SPI_MEM_FMEM_DDR_EN (BIT(0)) -#define SPI_MEM_FMEM_DDR_EN_M (SPI_MEM_FMEM_DDR_EN_V << SPI_MEM_FMEM_DDR_EN_S) -#define SPI_MEM_FMEM_DDR_EN_V 0x00000001U -#define SPI_MEM_FMEM_DDR_EN_S 0 -/** SPI_MEM_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; +#define SPI_FMEM_DDR_EN (BIT(0)) +#define SPI_FMEM_DDR_EN_M (SPI_FMEM_DDR_EN_V << SPI_FMEM_DDR_EN_S) +#define SPI_FMEM_DDR_EN_V 0x00000001U +#define SPI_FMEM_DDR_EN_S 0 +/** SPI_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; * Set the bit to enable variable dummy cycle in spi ddr mode. */ -#define SPI_MEM_FMEM_VAR_DUMMY (BIT(1)) -#define SPI_MEM_FMEM_VAR_DUMMY_M (SPI_MEM_FMEM_VAR_DUMMY_V << SPI_MEM_FMEM_VAR_DUMMY_S) -#define SPI_MEM_FMEM_VAR_DUMMY_V 0x00000001U -#define SPI_MEM_FMEM_VAR_DUMMY_S 1 -/** SPI_MEM_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; +#define SPI_FMEM_VAR_DUMMY (BIT(1)) +#define SPI_FMEM_VAR_DUMMY_M (SPI_FMEM_VAR_DUMMY_V << SPI_FMEM_VAR_DUMMY_S) +#define SPI_FMEM_VAR_DUMMY_V 0x00000001U +#define SPI_FMEM_VAR_DUMMY_S 1 +/** SPI_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; * Set the bit to reorder rx data of the word in spi ddr mode. */ -#define SPI_MEM_FMEM_DDR_RDAT_SWP (BIT(2)) -#define SPI_MEM_FMEM_DDR_RDAT_SWP_M (SPI_MEM_FMEM_DDR_RDAT_SWP_V << SPI_MEM_FMEM_DDR_RDAT_SWP_S) -#define SPI_MEM_FMEM_DDR_RDAT_SWP_V 0x00000001U -#define SPI_MEM_FMEM_DDR_RDAT_SWP_S 2 -/** SPI_MEM_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; +#define SPI_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_FMEM_DDR_RDAT_SWP_M (SPI_FMEM_DDR_RDAT_SWP_V << SPI_FMEM_DDR_RDAT_SWP_S) +#define SPI_FMEM_DDR_RDAT_SWP_V 0x00000001U +#define SPI_FMEM_DDR_RDAT_SWP_S 2 +/** SPI_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; * Set the bit to reorder tx data of the word in spi ddr mode. */ -#define SPI_MEM_FMEM_DDR_WDAT_SWP (BIT(3)) -#define SPI_MEM_FMEM_DDR_WDAT_SWP_M (SPI_MEM_FMEM_DDR_WDAT_SWP_V << SPI_MEM_FMEM_DDR_WDAT_SWP_S) -#define SPI_MEM_FMEM_DDR_WDAT_SWP_V 0x00000001U -#define SPI_MEM_FMEM_DDR_WDAT_SWP_S 3 -/** SPI_MEM_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; +#define SPI_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_FMEM_DDR_WDAT_SWP_M (SPI_FMEM_DDR_WDAT_SWP_V << SPI_FMEM_DDR_WDAT_SWP_S) +#define SPI_FMEM_DDR_WDAT_SWP_V 0x00000001U +#define SPI_FMEM_DDR_WDAT_SWP_S 3 +/** SPI_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; * the bit is used to disable dual edge in command phase when ddr mode. */ -#define SPI_MEM_FMEM_DDR_CMD_DIS (BIT(4)) -#define SPI_MEM_FMEM_DDR_CMD_DIS_M (SPI_MEM_FMEM_DDR_CMD_DIS_V << SPI_MEM_FMEM_DDR_CMD_DIS_S) -#define SPI_MEM_FMEM_DDR_CMD_DIS_V 0x00000001U -#define SPI_MEM_FMEM_DDR_CMD_DIS_S 4 -/** SPI_MEM_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; +#define SPI_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_FMEM_DDR_CMD_DIS_M (SPI_FMEM_DDR_CMD_DIS_V << SPI_FMEM_DDR_CMD_DIS_S) +#define SPI_FMEM_DDR_CMD_DIS_V 0x00000001U +#define SPI_FMEM_DDR_CMD_DIS_S 4 +/** SPI_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; * It is the minimum output data length in the panda device. */ -#define SPI_MEM_FMEM_OUTMINBYTELEN 0x0000007FU -#define SPI_MEM_FMEM_OUTMINBYTELEN_M (SPI_MEM_FMEM_OUTMINBYTELEN_V << SPI_MEM_FMEM_OUTMINBYTELEN_S) -#define SPI_MEM_FMEM_OUTMINBYTELEN_V 0x0000007FU -#define SPI_MEM_FMEM_OUTMINBYTELEN_S 5 -/** SPI_MEM_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; +#define SPI_FMEM_OUTMINBYTELEN 0x0000007FU +#define SPI_FMEM_OUTMINBYTELEN_M (SPI_FMEM_OUTMINBYTELEN_V << SPI_FMEM_OUTMINBYTELEN_S) +#define SPI_FMEM_OUTMINBYTELEN_V 0x0000007FU +#define SPI_FMEM_OUTMINBYTELEN_S 5 +/** SPI_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; * The delay number of data strobe which from memory based on SPI clock. */ -#define SPI_MEM_FMEM_USR_DDR_DQS_THD 0x0000007FU -#define SPI_MEM_FMEM_USR_DDR_DQS_THD_M (SPI_MEM_FMEM_USR_DDR_DQS_THD_V << SPI_MEM_FMEM_USR_DDR_DQS_THD_S) -#define SPI_MEM_FMEM_USR_DDR_DQS_THD_V 0x0000007FU -#define SPI_MEM_FMEM_USR_DDR_DQS_THD_S 14 -/** SPI_MEM_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; +#define SPI_FMEM_USR_DDR_DQS_THD 0x0000007FU +#define SPI_FMEM_USR_DDR_DQS_THD_M (SPI_FMEM_USR_DDR_DQS_THD_V << SPI_FMEM_USR_DDR_DQS_THD_S) +#define SPI_FMEM_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI_FMEM_USR_DDR_DQS_THD_S 14 +/** SPI_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ -#define SPI_MEM_FMEM_DDR_DQS_LOOP (BIT(21)) -#define SPI_MEM_FMEM_DDR_DQS_LOOP_M (SPI_MEM_FMEM_DDR_DQS_LOOP_V << SPI_MEM_FMEM_DDR_DQS_LOOP_S) -#define SPI_MEM_FMEM_DDR_DQS_LOOP_V 0x00000001U -#define SPI_MEM_FMEM_DDR_DQS_LOOP_S 21 -/** SPI_MEM_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; +#define SPI_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_FMEM_DDR_DQS_LOOP_M (SPI_FMEM_DDR_DQS_LOOP_V << SPI_FMEM_DDR_DQS_LOOP_S) +#define SPI_FMEM_DDR_DQS_LOOP_V 0x00000001U +#define SPI_FMEM_DDR_DQS_LOOP_S 21 +/** SPI_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; * Set this bit to enable the differential SPI_CLK#. */ -#define SPI_MEM_FMEM_CLK_DIFF_EN (BIT(24)) -#define SPI_MEM_FMEM_CLK_DIFF_EN_M (SPI_MEM_FMEM_CLK_DIFF_EN_V << SPI_MEM_FMEM_CLK_DIFF_EN_S) -#define SPI_MEM_FMEM_CLK_DIFF_EN_V 0x00000001U -#define SPI_MEM_FMEM_CLK_DIFF_EN_S 24 -/** SPI_MEM_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; +#define SPI_FMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_FMEM_CLK_DIFF_EN_M (SPI_FMEM_CLK_DIFF_EN_V << SPI_FMEM_CLK_DIFF_EN_S) +#define SPI_FMEM_CLK_DIFF_EN_V 0x00000001U +#define SPI_FMEM_CLK_DIFF_EN_S 24 +/** SPI_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. */ -#define SPI_MEM_FMEM_DQS_CA_IN (BIT(26)) -#define SPI_MEM_FMEM_DQS_CA_IN_M (SPI_MEM_FMEM_DQS_CA_IN_V << SPI_MEM_FMEM_DQS_CA_IN_S) -#define SPI_MEM_FMEM_DQS_CA_IN_V 0x00000001U -#define SPI_MEM_FMEM_DQS_CA_IN_S 26 -/** SPI_MEM_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; +#define SPI_FMEM_DQS_CA_IN (BIT(26)) +#define SPI_FMEM_DQS_CA_IN_M (SPI_FMEM_DQS_CA_IN_V << SPI_FMEM_DQS_CA_IN_S) +#define SPI_FMEM_DQS_CA_IN_V 0x00000001U +#define SPI_FMEM_DQS_CA_IN_S 26 +/** SPI_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 * accesses flash or SPI1 accesses flash or sram. */ -#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) -#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_M (SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V << SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S) -#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U -#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S 27 -/** SPI_MEM_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; +#define SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_FMEM_HYPERBUS_DUMMY_2X_M (SPI_FMEM_HYPERBUS_DUMMY_2X_V << SPI_FMEM_HYPERBUS_DUMMY_2X_S) +#define SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 +/** SPI_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; * Set this bit to invert SPI_DIFF when accesses to flash. . */ -#define SPI_MEM_FMEM_CLK_DIFF_INV (BIT(28)) -#define SPI_MEM_FMEM_CLK_DIFF_INV_M (SPI_MEM_FMEM_CLK_DIFF_INV_V << SPI_MEM_FMEM_CLK_DIFF_INV_S) -#define SPI_MEM_FMEM_CLK_DIFF_INV_V 0x00000001U -#define SPI_MEM_FMEM_CLK_DIFF_INV_S 28 -/** SPI_MEM_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; +#define SPI_FMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_FMEM_CLK_DIFF_INV_M (SPI_FMEM_CLK_DIFF_INV_V << SPI_FMEM_CLK_DIFF_INV_S) +#define SPI_FMEM_CLK_DIFF_INV_V 0x00000001U +#define SPI_FMEM_CLK_DIFF_INV_S 28 +/** SPI_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; * Set this bit to enable octa_ram address out when accesses to flash, which means * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. */ -#define SPI_MEM_FMEM_OCTA_RAM_ADDR (BIT(29)) -#define SPI_MEM_FMEM_OCTA_RAM_ADDR_M (SPI_MEM_FMEM_OCTA_RAM_ADDR_V << SPI_MEM_FMEM_OCTA_RAM_ADDR_S) -#define SPI_MEM_FMEM_OCTA_RAM_ADDR_V 0x00000001U -#define SPI_MEM_FMEM_OCTA_RAM_ADDR_S 29 -/** SPI_MEM_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; +#define SPI_FMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_FMEM_OCTA_RAM_ADDR_M (SPI_FMEM_OCTA_RAM_ADDR_V << SPI_FMEM_OCTA_RAM_ADDR_S) +#define SPI_FMEM_OCTA_RAM_ADDR_V 0x00000001U +#define SPI_FMEM_OCTA_RAM_ADDR_S 29 +/** SPI_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; * Set this bit to enable HyperRAM address out when accesses to flash, which means * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. */ -#define SPI_MEM_FMEM_HYPERBUS_CA (BIT(30)) -#define SPI_MEM_FMEM_HYPERBUS_CA_M (SPI_MEM_FMEM_HYPERBUS_CA_V << SPI_MEM_FMEM_HYPERBUS_CA_S) -#define SPI_MEM_FMEM_HYPERBUS_CA_V 0x00000001U -#define SPI_MEM_FMEM_HYPERBUS_CA_S 30 +#define SPI_FMEM_HYPERBUS_CA (BIT(30)) +#define SPI_FMEM_HYPERBUS_CA_M (SPI_FMEM_HYPERBUS_CA_V << SPI_FMEM_HYPERBUS_CA_S) +#define SPI_FMEM_HYPERBUS_CA_V 0x00000001U +#define SPI_FMEM_HYPERBUS_CA_S 30 /** SPI_MEM_TIMING_CALI_REG register * SPI1 timing control register @@ -1501,7 +1539,7 @@ extern "C" { * Version control register */ #define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3fc) -/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 36774400; +/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37823232; * Version control register */ #define SPI_MEM_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c61/register/soc/spi1_mem_struct.h b/components/soc/esp32c61/register/soc/spi1_mem_struct.h index 9ff190d0d5..f89e1d3d17 100644 --- a/components/soc/esp32c61/register/soc/spi1_mem_struct.h +++ b/components/soc/esp32c61/register/soc/spi1_mem_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -31,6 +31,7 @@ typedef union { * In user mode, it is set to indicate that program/erase operation will be triggered. * The bit is combined with spi_mem_usr bit. The bit will be cleared once the * operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_pe:1; /** usr : R/W/SC; bitpos: [18]; default: 0; @@ -41,68 +42,81 @@ typedef union { /** flash_hpm : R/W/SC; bitpos: [19]; default: 0; * Drive Flash into high performance mode. The bit will be cleared once the operation * done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_hpm:1; /** flash_res : R/W/SC; bitpos: [20]; default: 0; * This bit combined with reg_resandres bit releases Flash from the power-down state * or high performance mode and obtains the devices ID. The bit will be cleared once * the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_res:1; /** flash_dp : R/W/SC; bitpos: [21]; default: 0; * Drive Flash into power down. An operation will be triggered when the bit is set. * The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_dp:1; /** flash_ce : R/W/SC; bitpos: [22]; default: 0; * Chip erase enable. Chip erase operation will be triggered when the bit is set. The * bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_ce:1; /** flash_be : R/W/SC; bitpos: [23]; default: 0; * Block erase enable(32KB) . Block erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_be:1; /** flash_se : R/W/SC; bitpos: [24]; default: 0; * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_se:1; /** flash_pp : R/W/SC; bitpos: [25]; default: 0; * Page program enable(1 byte ~256 bytes data to be programmed). Page program * operation will be triggered when the bit is set. The bit will be cleared once the * operation done .1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_pp:1; /** flash_wrsr : R/W/SC; bitpos: [26]; default: 0; * Write status register enable. Write status operation will be triggered when the * bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_wrsr:1; /** flash_rdsr : R/W/SC; bitpos: [27]; default: 0; * Read status register-1. Read status operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_rdsr:1; /** flash_rdid : R/W/SC; bitpos: [28]; default: 0; * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be * cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_rdid:1; /** flash_wrdi : R/W/SC; bitpos: [29]; default: 0; * Write flash disable. Write disable command will be sent when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_wrdi:1; /** flash_wren : R/W/SC; bitpos: [30]; default: 0; * Write flash enable. Write enable command will be sent when the bit is set. The bit * will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_wren:1; /** flash_read : R/W/SC; bitpos: [31]; default: 0; * Read flash enable. Read flash operation will be triggered when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_read:1; }; @@ -268,10 +282,12 @@ typedef union { /** fcs_crc_en : R/W; bitpos: [10]; default: 0; * For SPI1, initialize crc32 module before writing encrypted data to flash. Active * low. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fcs_crc_en:1; /** tx_crc_en : R/W; bitpos: [11]; default: 0; * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t tx_crc_en:1; uint32_t reserved_12:1; @@ -287,6 +303,7 @@ typedef union { /** resandres : R/W; bitpos: [15]; default: 1; * The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with * spi_mem_flash_res bit. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t resandres:1; uint32_t reserved_16:2; @@ -309,6 +326,7 @@ typedef union { /** wrsr_2b : R/W; bitpos: [22]; default: 0; * two bytes data will be written to status register when it is set. 1: enable 0: * disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wrsr_2b:1; /** fread_dio : R/W; bitpos: [23]; default: 0; @@ -338,11 +356,16 @@ typedef union { */ uint32_t clk_mode:2; /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023; - * After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) - * SPI_CLK cycles. + * After RES/DP/HPM/PES command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * + * 128) SPI_CLK cycles. */ uint32_t cs_hold_dly_res:10; - uint32_t reserved_12:20; + /** cs_hold_dly_per : R/W; bitpos: [21:12]; default: 1023; + * After PER command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DLY_PER[9:0] * 128) SPI_CLK + * cycles. + */ + uint32_t cs_hold_dly_per:10; + uint32_t reserved_22:10; }; uint32_t val; } spi_mem_ctrl1_reg_t; @@ -367,16 +390,16 @@ typedef union { typedef union { struct { /** clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_CLKCNT_N. */ uint32_t clkcnt_l:8; /** clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). */ uint32_t clkcnt_h:8; /** clkcnt_n : R/W; bitpos: [23:16]; default: 3; * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(spi_mem_clkcnt_N+1) + * system/(SPI_MEM_CLKCNT_N+1) */ uint32_t clkcnt_n:8; uint32_t reserved_24:7; @@ -427,14 +450,17 @@ typedef union { uint32_t status:16; /** wb_mode : R/W; bitpos: [23:16]; default: 0; * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wb_mode:8; /** wb_mode_bitlen : R/W; bitpos: [26:24]; default: 0; * Mode bits length for flash fast read mode. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wb_mode_bitlen:3; /** wb_mode_en : R/W; bitpos: [27]; default: 0; * Mode bits is valid while this bit is enable. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wb_mode_en:1; uint32_t reserved_28:4; @@ -479,37 +505,44 @@ typedef union { uint32_t reserved_0:1; /** cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t cache_usr_addr_4byte:1; uint32_t reserved_2:1; /** fdin_dual : R/W; bitpos: [3]; default: 0; * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with * spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdin_dual:1; /** fdout_dual : R/W; bitpos: [4]; default: 0; * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdout_dual:1; /** faddr_dual : R/W; bitpos: [5]; default: 0; * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t faddr_dual:1; /** fdin_quad : R/W; bitpos: [6]; default: 0; * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdin_quad:1; /** fdout_quad : R/W; bitpos: [7]; default: 0; * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdout_quad:1; /** faddr_quad : R/W; bitpos: [8]; default: 0; * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t faddr_quad:1; uint32_t reserved_9:23; @@ -834,216 +867,6 @@ typedef union { } spi_mem_tx_crc_reg_t; -/** Group: Memory data buffer register */ -/** Type of word buffer register - * SPI1 memory data buffer_n - */ -typedef union { - struct { - /** buf0 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf0:32; - }; - uint32_t val; -} spi_mem_buffer_reg_t; - -/** Type of w1 register - * SPI1 memory data buffer1 - */ -typedef union { - struct { - /** buf1 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf1:32; - }; - uint32_t val; -} spi_mem_w1_reg_t; - -/** Type of w2 register - * SPI1 memory data buffer2 - */ -typedef union { - struct { - /** buf2 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf2:32; - }; - uint32_t val; -} spi_mem_w2_reg_t; - -/** Type of w3 register - * SPI1 memory data buffer3 - */ -typedef union { - struct { - /** buf3 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf3:32; - }; - uint32_t val; -} spi_mem_w3_reg_t; - -/** Type of w4 register - * SPI1 memory data buffer4 - */ -typedef union { - struct { - /** buf4 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf4:32; - }; - uint32_t val; -} spi_mem_w4_reg_t; - -/** Type of w5 register - * SPI1 memory data buffer5 - */ -typedef union { - struct { - /** buf5 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf5:32; - }; - uint32_t val; -} spi_mem_w5_reg_t; - -/** Type of w6 register - * SPI1 memory data buffer6 - */ -typedef union { - struct { - /** buf6 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf6:32; - }; - uint32_t val; -} spi_mem_w6_reg_t; - -/** Type of w7 register - * SPI1 memory data buffer7 - */ -typedef union { - struct { - /** buf7 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf7:32; - }; - uint32_t val; -} spi_mem_w7_reg_t; - -/** Type of w8 register - * SPI1 memory data buffer8 - */ -typedef union { - struct { - /** buf8 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf8:32; - }; - uint32_t val; -} spi_mem_w8_reg_t; - -/** Type of w9 register - * SPI1 memory data buffer9 - */ -typedef union { - struct { - /** buf9 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf9:32; - }; - uint32_t val; -} spi_mem_w9_reg_t; - -/** Type of w10 register - * SPI1 memory data buffer10 - */ -typedef union { - struct { - /** buf10 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf10:32; - }; - uint32_t val; -} spi_mem_w10_reg_t; - -/** Type of w11 register - * SPI1 memory data buffer11 - */ -typedef union { - struct { - /** buf11 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf11:32; - }; - uint32_t val; -} spi_mem_w11_reg_t; - -/** Type of w12 register - * SPI1 memory data buffer12 - */ -typedef union { - struct { - /** buf12 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf12:32; - }; - uint32_t val; -} spi_mem_w12_reg_t; - -/** Type of w13 register - * SPI1 memory data buffer13 - */ -typedef union { - struct { - /** buf13 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf13:32; - }; - uint32_t val; -} spi_mem_w13_reg_t; - -/** Type of w14 register - * SPI1 memory data buffer14 - */ -typedef union { - struct { - /** buf14 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf14:32; - }; - uint32_t val; -} spi_mem_w14_reg_t; - -/** Type of w15 register - * SPI1 memory data buffer15 - */ -typedef union { - struct { - /** buf15 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf15:32; - }; - uint32_t val; -} spi_mem_w15_reg_t; - - /** Group: Interrupt registers */ /** Type of int_ena register * SPI1 interrupt enable register @@ -1222,7 +1045,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36774400; + /** date : R/W; bitpos: [27:0]; default: 37823232; * Version control register */ uint32_t date:28; diff --git a/components/soc/esp32c61/register/soc/spi_mem_c_reg.h b/components/soc/esp32c61/register/soc/spi_mem_c_reg.h index 6bde89aefd..7d3370c582 100644 --- a/components/soc/esp32c61/register/soc/spi_mem_c_reg.h +++ b/components/soc/esp32c61/register/soc/spi_mem_c_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -47,7 +47,7 @@ extern "C" { * SPI0 control register. */ #define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8) -/** SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [0]; default: 0; +/** SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [0]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to flash, the level * of SPI_DQS is output by the MSPI controller. */ @@ -81,21 +81,21 @@ extern "C" { #define SPI_MEM_FDUMMY_WOUT_M (SPI_MEM_FDUMMY_WOUT_V << SPI_MEM_FDUMMY_WOUT_S) #define SPI_MEM_FDUMMY_WOUT_V 0x00000001U #define SPI_MEM_FDUMMY_WOUT_S 3 -/** SPI_MEM_FDOUT_OCT : HRO; bitpos: [4]; default: 0; +/** SPI_MEM_FDOUT_OCT : R/W; bitpos: [4]; default: 0; * Apply 8 signals during write-data phase 1:enable 0: disable */ #define SPI_MEM_FDOUT_OCT (BIT(4)) #define SPI_MEM_FDOUT_OCT_M (SPI_MEM_FDOUT_OCT_V << SPI_MEM_FDOUT_OCT_S) #define SPI_MEM_FDOUT_OCT_V 0x00000001U #define SPI_MEM_FDOUT_OCT_S 4 -/** SPI_MEM_FDIN_OCT : HRO; bitpos: [5]; default: 0; +/** SPI_MEM_FDIN_OCT : R/W; bitpos: [5]; default: 0; * Apply 8 signals during read-data phase 1:enable 0: disable */ #define SPI_MEM_FDIN_OCT (BIT(5)) #define SPI_MEM_FDIN_OCT_M (SPI_MEM_FDIN_OCT_V << SPI_MEM_FDIN_OCT_S) #define SPI_MEM_FDIN_OCT_V 0x00000001U #define SPI_MEM_FDIN_OCT_S 5 -/** SPI_MEM_FADDR_OCT : HRO; bitpos: [6]; default: 0; +/** SPI_MEM_FADDR_OCT : R/W; bitpos: [6]; default: 0; * Apply 8 signals during address phase 1:enable 0: disable */ #define SPI_MEM_FADDR_OCT (BIT(6)) @@ -109,7 +109,7 @@ extern "C" { #define SPI_MEM_FCMD_QUAD_M (SPI_MEM_FCMD_QUAD_V << SPI_MEM_FCMD_QUAD_S) #define SPI_MEM_FCMD_QUAD_V 0x00000001U #define SPI_MEM_FCMD_QUAD_S 8 -/** SPI_MEM_FCMD_OCT : HRO; bitpos: [9]; default: 0; +/** SPI_MEM_FCMD_OCT : R/W; bitpos: [9]; default: 0; * Apply 8 signals during command phase 1:enable 0: disable */ #define SPI_MEM_FCMD_OCT (BIT(9)) @@ -175,7 +175,7 @@ extern "C" { #define SPI_MEM_FREAD_QIO_M (SPI_MEM_FREAD_QIO_V << SPI_MEM_FREAD_QIO_S) #define SPI_MEM_FREAD_QIO_V 0x00000001U #define SPI_MEM_FREAD_QIO_S 24 -/** SPI_MEM_DQS_IE_ALWAYS_ON : HRO; bitpos: [30]; default: 0; +/** SPI_MEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always * 1. 0: Others. */ @@ -205,29 +205,21 @@ extern "C" { #define SPI_MEM_CLK_MODE_M (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S) #define SPI_MEM_CLK_MODE_V 0x00000003U #define SPI_MEM_CLK_MODE_S 0 -/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1; +/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1; * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. */ -#define SPI_AR_SIZE0_1_SUPPORT_EN (BIT(21)) +#define SPI_AR_SIZE0_1_SUPPORT_EN (BIT(22)) #define SPI_AR_SIZE0_1_SUPPORT_EN_M (SPI_AR_SIZE0_1_SUPPORT_EN_V << SPI_AR_SIZE0_1_SUPPORT_EN_S) #define SPI_AR_SIZE0_1_SUPPORT_EN_V 0x00000001U -#define SPI_AR_SIZE0_1_SUPPORT_EN_S 21 -/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1; +#define SPI_AR_SIZE0_1_SUPPORT_EN_S 22 +/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [23]; default: 1; * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. */ -#define SPI_AW_SIZE0_1_SUPPORT_EN (BIT(22)) +#define SPI_AW_SIZE0_1_SUPPORT_EN (BIT(23)) #define SPI_AW_SIZE0_1_SUPPORT_EN_M (SPI_AW_SIZE0_1_SUPPORT_EN_V << SPI_AW_SIZE0_1_SUPPORT_EN_S) #define SPI_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U -#define SPI_AW_SIZE0_1_SUPPORT_EN_S 22 -/** SPI_AXI_RDATA_BACK_FAST : HRO; bitpos: [23]; default: 1; - * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: - * Reply AXI read data to AXI bus when all the read data is available. - */ -#define SPI_AXI_RDATA_BACK_FAST (BIT(23)) -#define SPI_AXI_RDATA_BACK_FAST_M (SPI_AXI_RDATA_BACK_FAST_V << SPI_AXI_RDATA_BACK_FAST_S) -#define SPI_AXI_RDATA_BACK_FAST_V 0x00000001U -#define SPI_AXI_RDATA_BACK_FAST_S 23 +#define SPI_AW_SIZE0_1_SUPPORT_EN_S 23 /** SPI_MEM_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0; * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * when there is a ECC error in AXI read data. The ECC error information is recorded @@ -237,14 +229,14 @@ extern "C" { #define SPI_MEM_RRESP_ECC_ERR_EN_M (SPI_MEM_RRESP_ECC_ERR_EN_V << SPI_MEM_RRESP_ECC_ERR_EN_S) #define SPI_MEM_RRESP_ECC_ERR_EN_V 0x00000001U #define SPI_MEM_RRESP_ECC_ERR_EN_S 24 -/** SPI_MEM_AR_SPLICE_EN : HRO; bitpos: [25]; default: 0; +/** SPI_MEM_AR_SPLICE_EN : R/W; bitpos: [25]; default: 0; * Set this bit to enable AXI Read Splice-transfer. */ #define SPI_MEM_AR_SPLICE_EN (BIT(25)) #define SPI_MEM_AR_SPLICE_EN_M (SPI_MEM_AR_SPLICE_EN_V << SPI_MEM_AR_SPLICE_EN_S) #define SPI_MEM_AR_SPLICE_EN_V 0x00000001U #define SPI_MEM_AR_SPLICE_EN_S 25 -/** SPI_MEM_AW_SPLICE_EN : HRO; bitpos: [26]; default: 0; +/** SPI_MEM_AW_SPLICE_EN : R/W; bitpos: [26]; default: 0; * Set this bit to enable AXI Write Splice-transfer. */ #define SPI_MEM_AW_SPLICE_EN (BIT(26)) @@ -315,7 +307,7 @@ extern "C" { #define SPI_MEM_CS_HOLD_TIME_M (SPI_MEM_CS_HOLD_TIME_V << SPI_MEM_CS_HOLD_TIME_S) #define SPI_MEM_CS_HOLD_TIME_V 0x0000001FU #define SPI_MEM_CS_HOLD_TIME_S 5 -/** SPI_MEM_ECC_CS_HOLD_TIME : HRO; bitpos: [12:10]; default: 3; +/** SPI_MEM_ECC_CS_HOLD_TIME : R/W; bitpos: [12:10]; default: 3; * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC * mode when accessed flash. */ @@ -323,7 +315,7 @@ extern "C" { #define SPI_MEM_ECC_CS_HOLD_TIME_M (SPI_MEM_ECC_CS_HOLD_TIME_V << SPI_MEM_ECC_CS_HOLD_TIME_S) #define SPI_MEM_ECC_CS_HOLD_TIME_V 0x00000007U #define SPI_MEM_ECC_CS_HOLD_TIME_S 10 -/** SPI_MEM_ECC_SKIP_PAGE_CORNER : HRO; bitpos: [13]; default: 1; +/** SPI_MEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [13]; default: 1; * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when * accesses flash. */ @@ -331,7 +323,7 @@ extern "C" { #define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (SPI_MEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_ECC_SKIP_PAGE_CORNER_S) #define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U #define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 -/** SPI_MEM_ECC_16TO18_BYTE_EN : HRO; bitpos: [14]; default: 0; +/** SPI_MEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [14]; default: 0; * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when * accesses flash. */ @@ -370,14 +362,14 @@ extern "C" { */ #define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) /** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_CLKCNT_N. */ #define SPI_MEM_CLKCNT_L 0x000000FFU #define SPI_MEM_CLKCNT_L_M (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S) #define SPI_MEM_CLKCNT_L_V 0x000000FFU #define SPI_MEM_CLKCNT_L_S 0 /** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). */ #define SPI_MEM_CLKCNT_H 0x000000FFU #define SPI_MEM_CLKCNT_H_M (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S) @@ -385,7 +377,7 @@ extern "C" { #define SPI_MEM_CLKCNT_H_S 8 /** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(spi_mem_clkcnt_N+1) + * system/(SPI_MEM_CLKCNT_N+1) */ #define SPI_MEM_CLKCNT_N 0x000000FFU #define SPI_MEM_CLKCNT_N_M (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S) @@ -452,12 +444,12 @@ extern "C" { #define SPI_MEM_USR_DUMMY_CYCLELEN_M (SPI_MEM_USR_DUMMY_CYCLELEN_V << SPI_MEM_USR_DUMMY_CYCLELEN_S) #define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x0000003FU #define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 -/** SPI_MEM_USR_DBYTELEN : HRO; bitpos: [8:6]; default: 1; +/** SPI_MEM_USR_DBYTELEN : HRO; bitpos: [11:6]; default: 1; * SPI0 USR_CMD read or write data byte length -1 */ -#define SPI_MEM_USR_DBYTELEN 0x00000007U +#define SPI_MEM_USR_DBYTELEN 0x0000003FU #define SPI_MEM_USR_DBYTELEN_M (SPI_MEM_USR_DBYTELEN_V << SPI_MEM_USR_DBYTELEN_S) -#define SPI_MEM_USR_DBYTELEN_V 0x00000007U +#define SPI_MEM_USR_DBYTELEN_V 0x0000003FU #define SPI_MEM_USR_DBYTELEN_S 6 /** SPI_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23; * The length in bits of address phase. The register value shall be (bit_num-1). @@ -500,6 +492,22 @@ extern "C" { #define SPI_MEM_WB_MODE_M (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S) #define SPI_MEM_WB_MODE_V 0x000000FFU #define SPI_MEM_WB_MODE_S 16 +/** SPI_MEM_WB_MODE_BITLEN : R/W; bitpos: [26:24]; default: 0; + * Mode bits length for flash fast read mode. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_WB_MODE_BITLEN 0x00000007U +#define SPI_MEM_WB_MODE_BITLEN_M (SPI_MEM_WB_MODE_BITLEN_V << SPI_MEM_WB_MODE_BITLEN_S) +#define SPI_MEM_WB_MODE_BITLEN_V 0x00000007U +#define SPI_MEM_WB_MODE_BITLEN_S 24 +/** SPI_MEM_WB_MODE_EN : R/W; bitpos: [27]; default: 0; + * Mode bits is valid while this bit is enable. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_WB_MODE_EN (BIT(27)) +#define SPI_MEM_WB_MODE_EN_M (SPI_MEM_WB_MODE_EN_V << SPI_MEM_WB_MODE_EN_S) +#define SPI_MEM_WB_MODE_EN_V 0x00000001U +#define SPI_MEM_WB_MODE_EN_S 27 /** SPI_MEM_MISC_REG register * SPI0 misc register @@ -616,7 +624,7 @@ extern "C" { #define SPI_MEM_FADDR_QUAD_M (SPI_MEM_FADDR_QUAD_V << SPI_MEM_FADDR_QUAD_S) #define SPI_MEM_FADDR_QUAD_V 0x00000001U #define SPI_MEM_FADDR_QUAD_S 8 -/** SPI_SAME_AW_AR_ADDR_CHK_EN : HRO; bitpos: [30]; default: 1; +/** SPI_SAME_AW_AR_ADDR_CHK_EN : R/W; bitpos: [30]; default: 1; * Set this bit to check AXI read/write the same address region. */ #define SPI_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) @@ -638,7 +646,7 @@ extern "C" { * applications. */ #define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x40) -/** SPI_MEM_CACHE_USR_SADDR_4BYTE : HRO; bitpos: [0]; default: 0; +/** SPI_MEM_CACHE_USR_SADDR_4BYTE : R/W; bitpos: [0]; default: 0; * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: * enable, 0:disable. * This field is only for internal debugging purposes. Do not use it in applications. @@ -647,7 +655,7 @@ extern "C" { #define SPI_MEM_CACHE_USR_SADDR_4BYTE_M (SPI_MEM_CACHE_USR_SADDR_4BYTE_V << SPI_MEM_CACHE_USR_SADDR_4BYTE_S) #define SPI_MEM_CACHE_USR_SADDR_4BYTE_V 0x00000001U #define SPI_MEM_CACHE_USR_SADDR_4BYTE_S 0 -/** SPI_MEM_USR_SRAM_DIO : HRO; bitpos: [1]; default: 0; +/** SPI_MEM_USR_SRAM_DIO : R/W; bitpos: [1]; default: 0; * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -655,7 +663,7 @@ extern "C" { #define SPI_MEM_USR_SRAM_DIO_M (SPI_MEM_USR_SRAM_DIO_V << SPI_MEM_USR_SRAM_DIO_S) #define SPI_MEM_USR_SRAM_DIO_V 0x00000001U #define SPI_MEM_USR_SRAM_DIO_S 1 -/** SPI_MEM_USR_SRAM_QIO : HRO; bitpos: [2]; default: 0; +/** SPI_MEM_USR_SRAM_QIO : R/W; bitpos: [2]; default: 0; * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -663,7 +671,7 @@ extern "C" { #define SPI_MEM_USR_SRAM_QIO_M (SPI_MEM_USR_SRAM_QIO_V << SPI_MEM_USR_SRAM_QIO_S) #define SPI_MEM_USR_SRAM_QIO_V 0x00000001U #define SPI_MEM_USR_SRAM_QIO_S 2 -/** SPI_MEM_USR_WR_SRAM_DUMMY : HRO; bitpos: [3]; default: 0; +/** SPI_MEM_USR_WR_SRAM_DUMMY : R/W; bitpos: [3]; default: 0; * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write * operations. * This field is only for internal debugging purposes. Do not use it in applications. @@ -672,7 +680,7 @@ extern "C" { #define SPI_MEM_USR_WR_SRAM_DUMMY_M (SPI_MEM_USR_WR_SRAM_DUMMY_V << SPI_MEM_USR_WR_SRAM_DUMMY_S) #define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x00000001U #define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 -/** SPI_MEM_USR_RD_SRAM_DUMMY : HRO; bitpos: [4]; default: 1; +/** SPI_MEM_USR_RD_SRAM_DUMMY : R/W; bitpos: [4]; default: 1; * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read * operations. * This field is only for internal debugging purposes. Do not use it in applications. @@ -681,7 +689,7 @@ extern "C" { #define SPI_MEM_USR_RD_SRAM_DUMMY_M (SPI_MEM_USR_RD_SRAM_DUMMY_V << SPI_MEM_USR_RD_SRAM_DUMMY_S) #define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x00000001U #define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 -/** SPI_MEM_CACHE_SRAM_USR_RCMD : HRO; bitpos: [5]; default: 1; +/** SPI_MEM_CACHE_SRAM_USR_RCMD : R/W; bitpos: [5]; default: 1; * For SPI0, In the external RAM mode cache read external RAM for user define command. * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -689,7 +697,7 @@ extern "C" { #define SPI_MEM_CACHE_SRAM_USR_RCMD_M (SPI_MEM_CACHE_SRAM_USR_RCMD_V << SPI_MEM_CACHE_SRAM_USR_RCMD_S) #define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x00000001U #define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 -/** SPI_MEM_SRAM_RDUMMY_CYCLELEN : HRO; bitpos: [11:6]; default: 1; +/** SPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W; bitpos: [11:6]; default: 1; * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. * The register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. @@ -698,7 +706,7 @@ extern "C" { #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M (SPI_MEM_SRAM_RDUMMY_CYCLELEN_V << SPI_MEM_SRAM_RDUMMY_CYCLELEN_S) #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x0000003FU #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 -/** SPI_MEM_SRAM_ADDR_BITLEN : HRO; bitpos: [19:14]; default: 23; +/** SPI_MEM_SRAM_ADDR_BITLEN : R/W; bitpos: [19:14]; default: 23; * For SPI0, In the external RAM mode, it is the length in bits of address phase. The * register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. @@ -707,7 +715,7 @@ extern "C" { #define SPI_MEM_SRAM_ADDR_BITLEN_M (SPI_MEM_SRAM_ADDR_BITLEN_V << SPI_MEM_SRAM_ADDR_BITLEN_S) #define SPI_MEM_SRAM_ADDR_BITLEN_V 0x0000003FU #define SPI_MEM_SRAM_ADDR_BITLEN_S 14 -/** SPI_MEM_CACHE_SRAM_USR_WCMD : HRO; bitpos: [20]; default: 1; +/** SPI_MEM_CACHE_SRAM_USR_WCMD : R/W; bitpos: [20]; default: 1; * For SPI0, In the external RAM mode cache write sram for user define command * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -715,7 +723,7 @@ extern "C" { #define SPI_MEM_CACHE_SRAM_USR_WCMD_M (SPI_MEM_CACHE_SRAM_USR_WCMD_V << SPI_MEM_CACHE_SRAM_USR_WCMD_S) #define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x00000001U #define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 -/** SPI_MEM_SRAM_OCT : HRO; bitpos: [21]; default: 0; +/** SPI_MEM_SRAM_OCT : R/W; bitpos: [21]; default: 0; * reserved * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -723,7 +731,7 @@ extern "C" { #define SPI_MEM_SRAM_OCT_M (SPI_MEM_SRAM_OCT_V << SPI_MEM_SRAM_OCT_S) #define SPI_MEM_SRAM_OCT_V 0x00000001U #define SPI_MEM_SRAM_OCT_S 21 -/** SPI_MEM_SRAM_WDUMMY_CYCLELEN : HRO; bitpos: [27:22]; default: 1; +/** SPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W; bitpos: [27:22]; default: 1; * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. * The register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. @@ -737,7 +745,7 @@ extern "C" { * SPI0 external RAM mode control register */ #define SPI_MEM_SRAM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x44) -/** SPI_MEM_SCLK_MODE : HRO; bitpos: [1:0]; default: 0; +/** SPI_MEM_SCLK_MODE : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: * SPI clock is always on. @@ -747,7 +755,7 @@ extern "C" { #define SPI_MEM_SCLK_MODE_M (SPI_MEM_SCLK_MODE_V << SPI_MEM_SCLK_MODE_S) #define SPI_MEM_SCLK_MODE_V 0x00000003U #define SPI_MEM_SCLK_MODE_S 0 -/** SPI_MEM_SWB_MODE : HRO; bitpos: [9:2]; default: 0; +/** SPI_MEM_SWB_MODE : R/W; bitpos: [9:2]; default: 0; * Mode bits in the external RAM fast read mode it is combined with * spi_mem_fastrd_mode bit. * This field is only for internal debugging purposes. Do not use it in applications. @@ -756,7 +764,7 @@ extern "C" { #define SPI_MEM_SWB_MODE_M (SPI_MEM_SWB_MODE_V << SPI_MEM_SWB_MODE_S) #define SPI_MEM_SWB_MODE_V 0x000000FFU #define SPI_MEM_SWB_MODE_S 2 -/** SPI_MEM_SDIN_DUAL : HRO; bitpos: [10]; default: 0; +/** SPI_MEM_SDIN_DUAL : R/W; bitpos: [10]; default: 0; * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is * the same with spi_mem_usr_sram_dio. * This field is only for internal debugging purposes. Do not use it in applications. @@ -765,7 +773,7 @@ extern "C" { #define SPI_MEM_SDIN_DUAL_M (SPI_MEM_SDIN_DUAL_V << SPI_MEM_SDIN_DUAL_S) #define SPI_MEM_SDIN_DUAL_V 0x00000001U #define SPI_MEM_SDIN_DUAL_S 10 -/** SPI_MEM_SDOUT_DUAL : HRO; bitpos: [11]; default: 0; +/** SPI_MEM_SDOUT_DUAL : R/W; bitpos: [11]; default: 0; * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit * is the same with spi_mem_usr_sram_dio. * This field is only for internal debugging purposes. Do not use it in applications. @@ -774,7 +782,7 @@ extern "C" { #define SPI_MEM_SDOUT_DUAL_M (SPI_MEM_SDOUT_DUAL_V << SPI_MEM_SDOUT_DUAL_S) #define SPI_MEM_SDOUT_DUAL_V 0x00000001U #define SPI_MEM_SDOUT_DUAL_S 11 -/** SPI_MEM_SADDR_DUAL : HRO; bitpos: [12]; default: 0; +/** SPI_MEM_SADDR_DUAL : R/W; bitpos: [12]; default: 0; * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The * bit is the same with spi_mem_usr_sram_dio. * This field is only for internal debugging purposes. Do not use it in applications. @@ -783,7 +791,7 @@ extern "C" { #define SPI_MEM_SADDR_DUAL_M (SPI_MEM_SADDR_DUAL_V << SPI_MEM_SADDR_DUAL_S) #define SPI_MEM_SADDR_DUAL_V 0x00000001U #define SPI_MEM_SADDR_DUAL_S 12 -/** SPI_MEM_SDIN_QUAD : HRO; bitpos: [14]; default: 0; +/** SPI_MEM_SDIN_QUAD : R/W; bitpos: [14]; default: 0; * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is * the same with spi_mem_usr_sram_qio. * This field is only for internal debugging purposes. Do not use it in applications. @@ -792,7 +800,7 @@ extern "C" { #define SPI_MEM_SDIN_QUAD_M (SPI_MEM_SDIN_QUAD_V << SPI_MEM_SDIN_QUAD_S) #define SPI_MEM_SDIN_QUAD_V 0x00000001U #define SPI_MEM_SDIN_QUAD_S 14 -/** SPI_MEM_SDOUT_QUAD : HRO; bitpos: [15]; default: 0; +/** SPI_MEM_SDOUT_QUAD : R/W; bitpos: [15]; default: 0; * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit * is the same with spi_mem_usr_sram_qio. * This field is only for internal debugging purposes. Do not use it in applications. @@ -801,7 +809,7 @@ extern "C" { #define SPI_MEM_SDOUT_QUAD_M (SPI_MEM_SDOUT_QUAD_V << SPI_MEM_SDOUT_QUAD_S) #define SPI_MEM_SDOUT_QUAD_V 0x00000001U #define SPI_MEM_SDOUT_QUAD_S 15 -/** SPI_MEM_SADDR_QUAD : HRO; bitpos: [16]; default: 0; +/** SPI_MEM_SADDR_QUAD : R/W; bitpos: [16]; default: 0; * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The * bit is the same with spi_mem_usr_sram_qio. * This field is only for internal debugging purposes. Do not use it in applications. @@ -810,7 +818,7 @@ extern "C" { #define SPI_MEM_SADDR_QUAD_M (SPI_MEM_SADDR_QUAD_V << SPI_MEM_SADDR_QUAD_S) #define SPI_MEM_SADDR_QUAD_V 0x00000001U #define SPI_MEM_SADDR_QUAD_S 16 -/** SPI_MEM_SCMD_QUAD : HRO; bitpos: [17]; default: 0; +/** SPI_MEM_SCMD_QUAD : R/W; bitpos: [17]; default: 0; * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is * the same with spi_mem_usr_sram_qio. * This field is only for internal debugging purposes. Do not use it in applications. @@ -819,7 +827,7 @@ extern "C" { #define SPI_MEM_SCMD_QUAD_M (SPI_MEM_SCMD_QUAD_V << SPI_MEM_SCMD_QUAD_S) #define SPI_MEM_SCMD_QUAD_V 0x00000001U #define SPI_MEM_SCMD_QUAD_S 17 -/** SPI_MEM_SDIN_OCT : HRO; bitpos: [18]; default: 0; +/** SPI_MEM_SDIN_OCT : R/W; bitpos: [18]; default: 0; * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -827,7 +835,7 @@ extern "C" { #define SPI_MEM_SDIN_OCT_M (SPI_MEM_SDIN_OCT_V << SPI_MEM_SDIN_OCT_S) #define SPI_MEM_SDIN_OCT_V 0x00000001U #define SPI_MEM_SDIN_OCT_S 18 -/** SPI_MEM_SDOUT_OCT : HRO; bitpos: [19]; default: 0; +/** SPI_MEM_SDOUT_OCT : R/W; bitpos: [19]; default: 0; * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -835,7 +843,7 @@ extern "C" { #define SPI_MEM_SDOUT_OCT_M (SPI_MEM_SDOUT_OCT_V << SPI_MEM_SDOUT_OCT_S) #define SPI_MEM_SDOUT_OCT_V 0x00000001U #define SPI_MEM_SDOUT_OCT_S 19 -/** SPI_MEM_SADDR_OCT : HRO; bitpos: [20]; default: 0; +/** SPI_MEM_SADDR_OCT : R/W; bitpos: [20]; default: 0; * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -843,7 +851,7 @@ extern "C" { #define SPI_MEM_SADDR_OCT_M (SPI_MEM_SADDR_OCT_V << SPI_MEM_SADDR_OCT_S) #define SPI_MEM_SADDR_OCT_V 0x00000001U #define SPI_MEM_SADDR_OCT_S 20 -/** SPI_MEM_SCMD_OCT : HRO; bitpos: [21]; default: 0; +/** SPI_MEM_SCMD_OCT : R/W; bitpos: [21]; default: 0; * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -860,7 +868,7 @@ extern "C" { #define SPI_MEM_SDUMMY_RIN_M (SPI_MEM_SDUMMY_RIN_V << SPI_MEM_SDUMMY_RIN_S) #define SPI_MEM_SDUMMY_RIN_V 0x00000001U #define SPI_MEM_SDUMMY_RIN_S 22 -/** SPI_MEM_SDUMMY_WOUT : HRO; bitpos: [23]; default: 0; +/** SPI_MEM_SDUMMY_WOUT : R/W; bitpos: [23]; default: 1; * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the * signal level of SPI bus is output by the MSPI controller. * This field is only for internal debugging purposes. Do not use it in applications. @@ -869,7 +877,7 @@ extern "C" { #define SPI_MEM_SDUMMY_WOUT_M (SPI_MEM_SDUMMY_WOUT_V << SPI_MEM_SDUMMY_WOUT_S) #define SPI_MEM_SDUMMY_WOUT_V 0x00000001U #define SPI_MEM_SDUMMY_WOUT_S 23 -/** SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [24]; default: 0; +/** SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [24]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, * the level of SPI_DQS is output by the MSPI controller. */ @@ -877,7 +885,7 @@ extern "C" { #define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S) #define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U #define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 -/** SPI_SMEM_WDUMMY_ALWAYS_OUT : HRO; bitpos: [25]; default: 0; +/** SPI_SMEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [25]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, * the level of SPI_IO[7:0] is output by the MSPI controller. */ @@ -885,7 +893,7 @@ extern "C" { #define SPI_SMEM_WDUMMY_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_ALWAYS_OUT_S) #define SPI_SMEM_WDUMMY_ALWAYS_OUT_V 0x00000001U #define SPI_SMEM_WDUMMY_ALWAYS_OUT_S 25 -/** SPI_SMEM_DQS_IE_ALWAYS_ON : HRO; bitpos: [30]; default: 1; +/** SPI_SMEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are * always 1. 0: Others. */ @@ -893,7 +901,7 @@ extern "C" { #define SPI_SMEM_DQS_IE_ALWAYS_ON_M (SPI_SMEM_DQS_IE_ALWAYS_ON_V << SPI_SMEM_DQS_IE_ALWAYS_ON_S) #define SPI_SMEM_DQS_IE_ALWAYS_ON_V 0x00000001U #define SPI_SMEM_DQS_IE_ALWAYS_ON_S 30 -/** SPI_SMEM_DATA_IE_ALWAYS_ON : HRO; bitpos: [31]; default: 1; +/** SPI_SMEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] * are always 1. 0: Others. */ @@ -908,7 +916,7 @@ extern "C" { * applications. */ #define SPI_MEM_SRAM_DRD_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x48) -/** SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : HRO; bitpos: [15:0]; default: 0; +/** SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; * For SPI0,When cache mode is enable it is the read command value of command phase * for sram. * This field is only for internal debugging purposes. Do not use it in applications. @@ -917,7 +925,7 @@ extern "C" { #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M (SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V << SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S) #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0x0000FFFFU #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 -/** SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : HRO; bitpos: [31:28]; default: 0; +/** SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; * For SPI0,When cache mode is enable it is the length in bits of command phase for * sram. The register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. @@ -933,7 +941,7 @@ extern "C" { * applications. */ #define SPI_MEM_SRAM_DWR_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x4c) -/** SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : HRO; bitpos: [15:0]; default: 0; +/** SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; * For SPI0,When cache mode is enable it is the write command value of command phase * for sram. * This field is only for internal debugging purposes. Do not use it in applications. @@ -942,7 +950,7 @@ extern "C" { #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M (SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V << SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S) #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0x0000FFFFU #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 -/** SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : HRO; bitpos: [31:28]; default: 0; +/** SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; * For SPI0,When cache mode is enable it is the in bits of command phase for sram. * The register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. @@ -958,32 +966,32 @@ extern "C" { * applications. */ #define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x50) -/** SPI_MEM_SCLKCNT_L : HRO; bitpos: [7:0]; default: 3; - * For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. +/** SPI_MEM_SCLKCNT_L : R/W; bitpos: [7:0]; default: 3; + * For SPI0 external RAM interface, it must be equal to SPI_MEM_SCLKCNT_N. * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_SCLKCNT_L 0x000000FFU #define SPI_MEM_SCLKCNT_L_M (SPI_MEM_SCLKCNT_L_V << SPI_MEM_SCLKCNT_L_S) #define SPI_MEM_SCLKCNT_L_V 0x000000FFU #define SPI_MEM_SCLKCNT_L_S 0 -/** SPI_MEM_SCLKCNT_H : HRO; bitpos: [15:8]; default: 1; - * For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). +/** SPI_MEM_SCLKCNT_H : R/W; bitpos: [15:8]; default: 1; + * For SPI0 external RAM interface, it must be floor((SPI_MEM_SCLKCNT_N+1)/2-1). * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_SCLKCNT_H 0x000000FFU #define SPI_MEM_SCLKCNT_H_M (SPI_MEM_SCLKCNT_H_V << SPI_MEM_SCLKCNT_H_S) #define SPI_MEM_SCLKCNT_H_V 0x000000FFU #define SPI_MEM_SCLKCNT_H_S 8 -/** SPI_MEM_SCLKCNT_N : HRO; bitpos: [23:16]; default: 3; +/** SPI_MEM_SCLKCNT_N : R/W; bitpos: [23:16]; default: 3; * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk - * frequency is system/(spi_mem_clkcnt_N+1) + * frequency is system/(SPI_MEM_SCLKCNT_N+1) * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_SCLKCNT_N 0x000000FFU #define SPI_MEM_SCLKCNT_N_M (SPI_MEM_SCLKCNT_N_V << SPI_MEM_SCLKCNT_N_S) #define SPI_MEM_SCLKCNT_N_V 0x000000FFU #define SPI_MEM_SCLKCNT_N_S 16 -/** SPI_MEM_SCLK_EQU_SYSCLK : HRO; bitpos: [31]; default: 0; +/** SPI_MEM_SCLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk * is divided from system clock. * This field is only for internal debugging purposes. Do not use it in applications. @@ -997,13 +1005,27 @@ extern "C" { * SPI0 FSM status register */ #define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x54) -/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4; +/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [18:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ -#define SPI_MEM_LOCK_DELAY_TIME 0x0000001FU +#define SPI_MEM_LOCK_DELAY_TIME 0x00000FFFU #define SPI_MEM_LOCK_DELAY_TIME_M (SPI_MEM_LOCK_DELAY_TIME_V << SPI_MEM_LOCK_DELAY_TIME_S) -#define SPI_MEM_LOCK_DELAY_TIME_V 0x0000001FU +#define SPI_MEM_LOCK_DELAY_TIME_V 0x00000FFFU #define SPI_MEM_LOCK_DELAY_TIME_S 7 +/** SPI_MEM_FLASH_LOCK_EN : R/W; bitpos: [19]; default: 0; + * The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable. + */ +#define SPI_MEM_FLASH_LOCK_EN (BIT(19)) +#define SPI_MEM_FLASH_LOCK_EN_M (SPI_MEM_FLASH_LOCK_EN_V << SPI_MEM_FLASH_LOCK_EN_S) +#define SPI_MEM_FLASH_LOCK_EN_V 0x00000001U +#define SPI_MEM_FLASH_LOCK_EN_S 19 +/** SPI_MEM_SRAM_LOCK_EN : R/W; bitpos: [20]; default: 0; + * The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable. + */ +#define SPI_MEM_SRAM_LOCK_EN (BIT(20)) +#define SPI_MEM_SRAM_LOCK_EN_M (SPI_MEM_SRAM_LOCK_EN_V << SPI_MEM_SRAM_LOCK_EN_S) +#define SPI_MEM_SRAM_LOCK_EN_V 0x00000001U +#define SPI_MEM_SRAM_LOCK_EN_S 20 /** SPI_MEM_INT_ENA_REG register * SPI0 interrupt enable register @@ -1023,7 +1045,7 @@ extern "C" { #define SPI_MEM_MST_ST_END_INT_ENA_M (SPI_MEM_MST_ST_END_INT_ENA_V << SPI_MEM_MST_ST_END_INT_ENA_S) #define SPI_MEM_MST_ST_END_INT_ENA_V 0x00000001U #define SPI_MEM_MST_ST_END_INT_ENA_S 4 -/** SPI_MEM_ECC_ERR_INT_ENA : HRO; bitpos: [5]; default: 0; +/** SPI_MEM_ECC_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. */ #define SPI_MEM_ECC_ERR_INT_ENA (BIT(5)) @@ -1044,20 +1066,48 @@ extern "C" { #define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M (SPI_MEM_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_AXI_RADDR_ERR_INT_ENA_S) #define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V 0x00000001U #define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : HRO; bitpos: [8]; default: 0; +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : R/W; bitpos: [8]; default: 0; * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA (BIT(8)) #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S) #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V 0x00000001U #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT__ENA : HRO; bitpos: [9]; default: 0; +/** SPI_MEM_AXI_WADDR_ERR_INT__ENA : R/W; bitpos: [9]; default: 0; * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ #define SPI_MEM_AXI_WADDR_ERR_INT__ENA (BIT(9)) #define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M (SPI_MEM_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_AXI_WADDR_ERR_INT__ENA_S) #define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V 0x00000001U #define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S 9 +/** SPI_MEM_DQS0_AFIFO_OVF_INT_ENA : R/W; bitpos: [28]; default: 0; + * The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_M (SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V << SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V 0x00000001U +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S 28 +/** SPI_MEM_DQS1_AFIFO_OVF_INT_ENA : R/W; bitpos: [29]; default: 0; + * The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_M (SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V << SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V 0x00000001U +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S 29 +/** SPI_MEM_BUS_FIFO1_UDF_INT_ENA : R/W; bitpos: [30]; default: 0; + * The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_M (SPI_MEM_BUS_FIFO1_UDF_INT_ENA_V << SPI_MEM_BUS_FIFO1_UDF_INT_ENA_S) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_V 0x00000001U +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_S 30 +/** SPI_MEM_BUS_FIFO0_UDF_INT_ENA : R/W; bitpos: [31]; default: 0; + * The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_M (SPI_MEM_BUS_FIFO0_UDF_INT_ENA_V << SPI_MEM_BUS_FIFO0_UDF_INT_ENA_S) +#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_S 31 /** SPI_MEM_INT_CLR_REG register * SPI0 interrupt clear register @@ -1077,7 +1127,7 @@ extern "C" { #define SPI_MEM_MST_ST_END_INT_CLR_M (SPI_MEM_MST_ST_END_INT_CLR_V << SPI_MEM_MST_ST_END_INT_CLR_S) #define SPI_MEM_MST_ST_END_INT_CLR_V 0x00000001U #define SPI_MEM_MST_ST_END_INT_CLR_S 4 -/** SPI_MEM_ECC_ERR_INT_CLR : HRO; bitpos: [5]; default: 0; +/** SPI_MEM_ECC_ERR_INT_CLR : WT; bitpos: [5]; default: 0; * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. */ #define SPI_MEM_ECC_ERR_INT_CLR (BIT(5)) @@ -1098,20 +1148,48 @@ extern "C" { #define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M (SPI_MEM_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_AXI_RADDR_ERR_INT_CLR_S) #define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V 0x00000001U #define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : HRO; bitpos: [8]; default: 0; +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : WT; bitpos: [8]; default: 0; * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ #define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR (BIT(8)) #define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S) #define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V 0x00000001U #define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT_CLR : HRO; bitpos: [9]; default: 0; +/** SPI_MEM_AXI_WADDR_ERR_INT_CLR : WT; bitpos: [9]; default: 0; * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ #define SPI_MEM_AXI_WADDR_ERR_INT_CLR (BIT(9)) #define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M (SPI_MEM_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_AXI_WADDR_ERR_INT_CLR_S) #define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V 0x00000001U #define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S 9 +/** SPI_MEM_DQS0_AFIFO_OVF_INT_CLR : WT; bitpos: [28]; default: 0; + * The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_M (SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V << SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V 0x00000001U +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S 28 +/** SPI_MEM_DQS1_AFIFO_OVF_INT_CLR : WT; bitpos: [29]; default: 0; + * The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_M (SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V << SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V 0x00000001U +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S 29 +/** SPI_MEM_BUS_FIFO1_UDF_INT_CLR : WT; bitpos: [30]; default: 0; + * The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_M (SPI_MEM_BUS_FIFO1_UDF_INT_CLR_V << SPI_MEM_BUS_FIFO1_UDF_INT_CLR_S) +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_V 0x00000001U +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_S 30 +/** SPI_MEM_BUS_FIFO0_UDF_INT_CLR : WT; bitpos: [31]; default: 0; + * The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_M (SPI_MEM_BUS_FIFO0_UDF_INT_CLR_V << SPI_MEM_BUS_FIFO0_UDF_INT_CLR_S) +#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_S 31 /** SPI_MEM_INT_RAW_REG register * SPI0 interrupt raw register @@ -1134,7 +1212,7 @@ extern "C" { #define SPI_MEM_MST_ST_END_INT_RAW_M (SPI_MEM_MST_ST_END_INT_RAW_V << SPI_MEM_MST_ST_END_INT_RAW_S) #define SPI_MEM_MST_ST_END_INT_RAW_V 0x00000001U #define SPI_MEM_MST_ST_END_INT_RAW_S 4 -/** SPI_MEM_ECC_ERR_INT_RAW : HRO; bitpos: [5]; default: 0; +/** SPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When @@ -1166,7 +1244,7 @@ extern "C" { #define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M (SPI_MEM_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_AXI_RADDR_ERR_INT_RAW_S) #define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V 0x00000001U #define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : HRO; bitpos: [8]; default: 0; +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write * flash request is received. 0: Others. */ @@ -1174,7 +1252,7 @@ extern "C" { #define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S) #define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V 0x00000001U #define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT_RAW : HRO; bitpos: [9]; default: 0; +/** SPI_MEM_AXI_WADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write * address is invalid by compared to MMU configuration. 0: Others. */ @@ -1182,6 +1260,38 @@ extern "C" { #define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M (SPI_MEM_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_AXI_WADDR_ERR_INT_RAW_S) #define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V 0x00000001U #define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S 9 +/** SPI_MEM_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS1 is overflow. + */ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_M (SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V << SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V 0x00000001U +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S 28 +/** SPI_MEM_DQS1_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS is overflow. + */ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_M (SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V << SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V 0x00000001U +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S 29 +/** SPI_MEM_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is + * underflow. + */ +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_M (SPI_MEM_BUS_FIFO1_UDF_INT_RAW_V << SPI_MEM_BUS_FIFO1_UDF_INT_RAW_S) +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_V 0x00000001U +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_S 30 +/** SPI_MEM_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is + * underflow. + */ +#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_M (SPI_MEM_BUS_FIFO0_UDF_INT_RAW_V << SPI_MEM_BUS_FIFO0_UDF_INT_RAW_S) +#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_S 31 /** SPI_MEM_INT_ST_REG register * SPI0 interrupt status register @@ -1201,7 +1311,7 @@ extern "C" { #define SPI_MEM_MST_ST_END_INT_ST_M (SPI_MEM_MST_ST_END_INT_ST_V << SPI_MEM_MST_ST_END_INT_ST_S) #define SPI_MEM_MST_ST_END_INT_ST_V 0x00000001U #define SPI_MEM_MST_ST_END_INT_ST_S 4 -/** SPI_MEM_ECC_ERR_INT_ST : HRO; bitpos: [5]; default: 0; +/** SPI_MEM_ECC_ERR_INT_ST : RO; bitpos: [5]; default: 0; * The status bit for SPI_MEM_ECC_ERR_INT interrupt. */ #define SPI_MEM_ECC_ERR_INT_ST (BIT(5)) @@ -1222,68 +1332,96 @@ extern "C" { #define SPI_MEM_AXI_RADDR_ERR_INT_ST_M (SPI_MEM_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_AXI_RADDR_ERR_INT_ST_S) #define SPI_MEM_AXI_RADDR_ERR_INT_ST_V 0x00000001U #define SPI_MEM_AXI_RADDR_ERR_INT_ST_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : HRO; bitpos: [8]; default: 0; +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : RO; bitpos: [8]; default: 0; * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST (BIT(8)) #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S) #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V 0x00000001U #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT_ST : HRO; bitpos: [9]; default: 0; +/** SPI_MEM_AXI_WADDR_ERR_INT_ST : RO; bitpos: [9]; default: 0; * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ #define SPI_MEM_AXI_WADDR_ERR_INT_ST (BIT(9)) #define SPI_MEM_AXI_WADDR_ERR_INT_ST_M (SPI_MEM_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_AXI_WADDR_ERR_INT_ST_S) #define SPI_MEM_AXI_WADDR_ERR_INT_ST_V 0x00000001U #define SPI_MEM_AXI_WADDR_ERR_INT_ST_S 9 +/** SPI_MEM_DQS0_AFIFO_OVF_INT_ST : RO; bitpos: [28]; default: 0; + * The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_M (SPI_MEM_DQS0_AFIFO_OVF_INT_ST_V << SPI_MEM_DQS0_AFIFO_OVF_INT_ST_S) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_V 0x00000001U +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_S 28 +/** SPI_MEM_DQS1_AFIFO_OVF_INT_ST : RO; bitpos: [29]; default: 0; + * The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_M (SPI_MEM_DQS1_AFIFO_OVF_INT_ST_V << SPI_MEM_DQS1_AFIFO_OVF_INT_ST_S) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_V 0x00000001U +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_S 29 +/** SPI_MEM_BUS_FIFO1_UDF_INT_ST : RO; bitpos: [30]; default: 0; + * The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_M (SPI_MEM_BUS_FIFO1_UDF_INT_ST_V << SPI_MEM_BUS_FIFO1_UDF_INT_ST_S) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_V 0x00000001U +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_S 30 +/** SPI_MEM_BUS_FIFO0_UDF_INT_ST : RO; bitpos: [31]; default: 0; + * The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO0_UDF_INT_ST (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_M (SPI_MEM_BUS_FIFO0_UDF_INT_ST_V << SPI_MEM_BUS_FIFO0_UDF_INT_ST_S) +#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_S 31 /** SPI_MEM_DDR_REG register * SPI0 flash DDR mode control register */ #define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xd4) -/** SPI_FMEM_DDR_EN : HRO; bitpos: [0]; default: 0; +/** SPI_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0; * 1: in DDR mode, 0 in SDR mode */ #define SPI_FMEM_DDR_EN (BIT(0)) #define SPI_FMEM_DDR_EN_M (SPI_FMEM_DDR_EN_V << SPI_FMEM_DDR_EN_S) #define SPI_FMEM_DDR_EN_V 0x00000001U #define SPI_FMEM_DDR_EN_S 0 -/** SPI_FMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0; +/** SPI_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; * Set the bit to enable variable dummy cycle in spi DDR mode. */ #define SPI_FMEM_VAR_DUMMY (BIT(1)) #define SPI_FMEM_VAR_DUMMY_M (SPI_FMEM_VAR_DUMMY_V << SPI_FMEM_VAR_DUMMY_S) #define SPI_FMEM_VAR_DUMMY_V 0x00000001U #define SPI_FMEM_VAR_DUMMY_S 1 -/** SPI_FMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0; +/** SPI_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; * Set the bit to reorder rx data of the word in spi DDR mode. */ #define SPI_FMEM_DDR_RDAT_SWP (BIT(2)) #define SPI_FMEM_DDR_RDAT_SWP_M (SPI_FMEM_DDR_RDAT_SWP_V << SPI_FMEM_DDR_RDAT_SWP_S) #define SPI_FMEM_DDR_RDAT_SWP_V 0x00000001U #define SPI_FMEM_DDR_RDAT_SWP_S 2 -/** SPI_FMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0; +/** SPI_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; * Set the bit to reorder tx data of the word in spi DDR mode. */ #define SPI_FMEM_DDR_WDAT_SWP (BIT(3)) #define SPI_FMEM_DDR_WDAT_SWP_M (SPI_FMEM_DDR_WDAT_SWP_V << SPI_FMEM_DDR_WDAT_SWP_S) #define SPI_FMEM_DDR_WDAT_SWP_V 0x00000001U #define SPI_FMEM_DDR_WDAT_SWP_S 3 -/** SPI_FMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0; +/** SPI_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; * the bit is used to disable dual edge in command phase when DDR mode. */ #define SPI_FMEM_DDR_CMD_DIS (BIT(4)) #define SPI_FMEM_DDR_CMD_DIS_M (SPI_FMEM_DDR_CMD_DIS_V << SPI_FMEM_DDR_CMD_DIS_S) #define SPI_FMEM_DDR_CMD_DIS_V 0x00000001U #define SPI_FMEM_DDR_CMD_DIS_S 4 -/** SPI_FMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1; +/** SPI_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; * It is the minimum output data length in the panda device. */ #define SPI_FMEM_OUTMINBYTELEN 0x0000007FU #define SPI_FMEM_OUTMINBYTELEN_M (SPI_FMEM_OUTMINBYTELEN_V << SPI_FMEM_OUTMINBYTELEN_S) #define SPI_FMEM_OUTMINBYTELEN_V 0x0000007FU #define SPI_FMEM_OUTMINBYTELEN_S 5 -/** SPI_FMEM_TX_DDR_MSK_EN : HRO; bitpos: [12]; default: 1; +/** SPI_FMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when * accesses to flash. */ @@ -1291,7 +1429,7 @@ extern "C" { #define SPI_FMEM_TX_DDR_MSK_EN_M (SPI_FMEM_TX_DDR_MSK_EN_V << SPI_FMEM_TX_DDR_MSK_EN_S) #define SPI_FMEM_TX_DDR_MSK_EN_V 0x00000001U #define SPI_FMEM_TX_DDR_MSK_EN_S 12 -/** SPI_FMEM_RX_DDR_MSK_EN : HRO; bitpos: [13]; default: 1; +/** SPI_FMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when * accesses to flash. */ @@ -1299,14 +1437,14 @@ extern "C" { #define SPI_FMEM_RX_DDR_MSK_EN_M (SPI_FMEM_RX_DDR_MSK_EN_V << SPI_FMEM_RX_DDR_MSK_EN_S) #define SPI_FMEM_RX_DDR_MSK_EN_V 0x00000001U #define SPI_FMEM_RX_DDR_MSK_EN_S 13 -/** SPI_FMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0; +/** SPI_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; * The delay number of data strobe which from memory based on SPI clock. */ #define SPI_FMEM_USR_DDR_DQS_THD 0x0000007FU #define SPI_FMEM_USR_DDR_DQS_THD_M (SPI_FMEM_USR_DDR_DQS_THD_V << SPI_FMEM_USR_DDR_DQS_THD_S) #define SPI_FMEM_USR_DDR_DQS_THD_V 0x0000007FU #define SPI_FMEM_USR_DDR_DQS_THD_S 14 -/** SPI_FMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; +/** SPI_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and @@ -1316,21 +1454,21 @@ extern "C" { #define SPI_FMEM_DDR_DQS_LOOP_M (SPI_FMEM_DDR_DQS_LOOP_V << SPI_FMEM_DDR_DQS_LOOP_S) #define SPI_FMEM_DDR_DQS_LOOP_V 0x00000001U #define SPI_FMEM_DDR_DQS_LOOP_S 21 -/** SPI_FMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0; +/** SPI_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; * Set this bit to enable the differential SPI_CLK#. */ #define SPI_FMEM_CLK_DIFF_EN (BIT(24)) #define SPI_FMEM_CLK_DIFF_EN_M (SPI_FMEM_CLK_DIFF_EN_V << SPI_FMEM_CLK_DIFF_EN_S) #define SPI_FMEM_CLK_DIFF_EN_V 0x00000001U #define SPI_FMEM_CLK_DIFF_EN_S 24 -/** SPI_FMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0; +/** SPI_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. */ #define SPI_FMEM_DQS_CA_IN (BIT(26)) #define SPI_FMEM_DQS_CA_IN_M (SPI_FMEM_DQS_CA_IN_V << SPI_FMEM_DQS_CA_IN_S) #define SPI_FMEM_DQS_CA_IN_V 0x00000001U #define SPI_FMEM_DQS_CA_IN_S 26 -/** SPI_FMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0; +/** SPI_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 * accesses flash or SPI1 accesses flash or sram. */ @@ -1338,14 +1476,14 @@ extern "C" { #define SPI_FMEM_HYPERBUS_DUMMY_2X_M (SPI_FMEM_HYPERBUS_DUMMY_2X_V << SPI_FMEM_HYPERBUS_DUMMY_2X_S) #define SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U #define SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 -/** SPI_FMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0; +/** SPI_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; * Set this bit to invert SPI_DIFF when accesses to flash. . */ #define SPI_FMEM_CLK_DIFF_INV (BIT(28)) #define SPI_FMEM_CLK_DIFF_INV_M (SPI_FMEM_CLK_DIFF_INV_V << SPI_FMEM_CLK_DIFF_INV_S) #define SPI_FMEM_CLK_DIFF_INV_V 0x00000001U #define SPI_FMEM_CLK_DIFF_INV_S 28 -/** SPI_FMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0; +/** SPI_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; * Set this bit to enable octa_ram address out when accesses to flash, which means * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. */ @@ -1353,7 +1491,7 @@ extern "C" { #define SPI_FMEM_OCTA_RAM_ADDR_M (SPI_FMEM_OCTA_RAM_ADDR_V << SPI_FMEM_OCTA_RAM_ADDR_S) #define SPI_FMEM_OCTA_RAM_ADDR_V 0x00000001U #define SPI_FMEM_OCTA_RAM_ADDR_S 29 -/** SPI_FMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0; +/** SPI_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; * Set this bit to enable HyperRAM address out when accesses to flash, which means * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. */ @@ -1366,49 +1504,49 @@ extern "C" { * SPI0 external RAM DDR mode control register */ #define SPI_SMEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xd8) -/** SPI_SMEM_DDR_EN : HRO; bitpos: [0]; default: 0; +/** SPI_SMEM_DDR_EN : R/W; bitpos: [0]; default: 0; * 1: in DDR mode, 0 in SDR mode */ #define SPI_SMEM_DDR_EN (BIT(0)) #define SPI_SMEM_DDR_EN_M (SPI_SMEM_DDR_EN_V << SPI_SMEM_DDR_EN_S) #define SPI_SMEM_DDR_EN_V 0x00000001U #define SPI_SMEM_DDR_EN_S 0 -/** SPI_SMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0; +/** SPI_SMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; * Set the bit to enable variable dummy cycle in spi DDR mode. */ #define SPI_SMEM_VAR_DUMMY (BIT(1)) #define SPI_SMEM_VAR_DUMMY_M (SPI_SMEM_VAR_DUMMY_V << SPI_SMEM_VAR_DUMMY_S) #define SPI_SMEM_VAR_DUMMY_V 0x00000001U #define SPI_SMEM_VAR_DUMMY_S 1 -/** SPI_SMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0; +/** SPI_SMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; * Set the bit to reorder rx data of the word in spi DDR mode. */ #define SPI_SMEM_DDR_RDAT_SWP (BIT(2)) #define SPI_SMEM_DDR_RDAT_SWP_M (SPI_SMEM_DDR_RDAT_SWP_V << SPI_SMEM_DDR_RDAT_SWP_S) #define SPI_SMEM_DDR_RDAT_SWP_V 0x00000001U #define SPI_SMEM_DDR_RDAT_SWP_S 2 -/** SPI_SMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0; +/** SPI_SMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; * Set the bit to reorder tx data of the word in spi DDR mode. */ #define SPI_SMEM_DDR_WDAT_SWP (BIT(3)) #define SPI_SMEM_DDR_WDAT_SWP_M (SPI_SMEM_DDR_WDAT_SWP_V << SPI_SMEM_DDR_WDAT_SWP_S) #define SPI_SMEM_DDR_WDAT_SWP_V 0x00000001U #define SPI_SMEM_DDR_WDAT_SWP_S 3 -/** SPI_SMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0; +/** SPI_SMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; * the bit is used to disable dual edge in command phase when DDR mode. */ #define SPI_SMEM_DDR_CMD_DIS (BIT(4)) #define SPI_SMEM_DDR_CMD_DIS_M (SPI_SMEM_DDR_CMD_DIS_V << SPI_SMEM_DDR_CMD_DIS_S) #define SPI_SMEM_DDR_CMD_DIS_V 0x00000001U #define SPI_SMEM_DDR_CMD_DIS_S 4 -/** SPI_SMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1; +/** SPI_SMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; * It is the minimum output data length in the DDR psram. */ #define SPI_SMEM_OUTMINBYTELEN 0x0000007FU #define SPI_SMEM_OUTMINBYTELEN_M (SPI_SMEM_OUTMINBYTELEN_V << SPI_SMEM_OUTMINBYTELEN_S) #define SPI_SMEM_OUTMINBYTELEN_V 0x0000007FU #define SPI_SMEM_OUTMINBYTELEN_S 5 -/** SPI_SMEM_TX_DDR_MSK_EN : HRO; bitpos: [12]; default: 1; +/** SPI_SMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when * accesses to external RAM. */ @@ -1416,7 +1554,7 @@ extern "C" { #define SPI_SMEM_TX_DDR_MSK_EN_M (SPI_SMEM_TX_DDR_MSK_EN_V << SPI_SMEM_TX_DDR_MSK_EN_S) #define SPI_SMEM_TX_DDR_MSK_EN_V 0x00000001U #define SPI_SMEM_TX_DDR_MSK_EN_S 12 -/** SPI_SMEM_RX_DDR_MSK_EN : HRO; bitpos: [13]; default: 1; +/** SPI_SMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when * accesses to external RAM. */ @@ -1424,14 +1562,14 @@ extern "C" { #define SPI_SMEM_RX_DDR_MSK_EN_M (SPI_SMEM_RX_DDR_MSK_EN_V << SPI_SMEM_RX_DDR_MSK_EN_S) #define SPI_SMEM_RX_DDR_MSK_EN_V 0x00000001U #define SPI_SMEM_RX_DDR_MSK_EN_S 13 -/** SPI_SMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0; +/** SPI_SMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; * The delay number of data strobe which from memory based on SPI clock. */ #define SPI_SMEM_USR_DDR_DQS_THD 0x0000007FU #define SPI_SMEM_USR_DDR_DQS_THD_M (SPI_SMEM_USR_DDR_DQS_THD_V << SPI_SMEM_USR_DDR_DQS_THD_S) #define SPI_SMEM_USR_DDR_DQS_THD_V 0x0000007FU #define SPI_SMEM_USR_DDR_DQS_THD_S 14 -/** SPI_SMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; +/** SPI_SMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and @@ -1441,21 +1579,21 @@ extern "C" { #define SPI_SMEM_DDR_DQS_LOOP_M (SPI_SMEM_DDR_DQS_LOOP_V << SPI_SMEM_DDR_DQS_LOOP_S) #define SPI_SMEM_DDR_DQS_LOOP_V 0x00000001U #define SPI_SMEM_DDR_DQS_LOOP_S 21 -/** SPI_SMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0; +/** SPI_SMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; * Set this bit to enable the differential SPI_CLK#. */ #define SPI_SMEM_CLK_DIFF_EN (BIT(24)) #define SPI_SMEM_CLK_DIFF_EN_M (SPI_SMEM_CLK_DIFF_EN_V << SPI_SMEM_CLK_DIFF_EN_S) #define SPI_SMEM_CLK_DIFF_EN_V 0x00000001U #define SPI_SMEM_CLK_DIFF_EN_S 24 -/** SPI_SMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0; +/** SPI_SMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. */ #define SPI_SMEM_DQS_CA_IN (BIT(26)) #define SPI_SMEM_DQS_CA_IN_M (SPI_SMEM_DQS_CA_IN_V << SPI_SMEM_DQS_CA_IN_S) #define SPI_SMEM_DQS_CA_IN_V 0x00000001U #define SPI_SMEM_DQS_CA_IN_S 26 -/** SPI_SMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0; +/** SPI_SMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 * accesses flash or SPI1 accesses flash or sram. */ @@ -1463,14 +1601,14 @@ extern "C" { #define SPI_SMEM_HYPERBUS_DUMMY_2X_M (SPI_SMEM_HYPERBUS_DUMMY_2X_V << SPI_SMEM_HYPERBUS_DUMMY_2X_S) #define SPI_SMEM_HYPERBUS_DUMMY_2X_V 0x00000001U #define SPI_SMEM_HYPERBUS_DUMMY_2X_S 27 -/** SPI_SMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0; +/** SPI_SMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; * Set this bit to invert SPI_DIFF when accesses to external RAM. . */ #define SPI_SMEM_CLK_DIFF_INV (BIT(28)) #define SPI_SMEM_CLK_DIFF_INV_M (SPI_SMEM_CLK_DIFF_INV_V << SPI_SMEM_CLK_DIFF_INV_S) #define SPI_SMEM_CLK_DIFF_INV_V 0x00000001U #define SPI_SMEM_CLK_DIFF_INV_S 28 -/** SPI_SMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0; +/** SPI_SMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; * Set this bit to enable octa_ram address out when accesses to external RAM, which * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], * 1'b0}. @@ -1479,7 +1617,7 @@ extern "C" { #define SPI_SMEM_OCTA_RAM_ADDR_M (SPI_SMEM_OCTA_RAM_ADDR_V << SPI_SMEM_OCTA_RAM_ADDR_S) #define SPI_SMEM_OCTA_RAM_ADDR_V 0x00000001U #define SPI_SMEM_OCTA_RAM_ADDR_S 29 -/** SPI_SMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0; +/** SPI_SMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; * Set this bit to enable HyperRAM address out when accesses to external RAM, which * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. */ @@ -1604,100 +1742,100 @@ extern "C" { * SPI1 flash PMS section 0 start address register */ #define SPI_FMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x110) -/** SPI_FMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; +/** SPI_FMEM_PMS0_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 flash PMS section 0 start address value */ -#define SPI_FMEM_PMS0_ADDR_S 0x07FFFFFFU +#define SPI_FMEM_PMS0_ADDR_S 0x1FFFFFFFU #define SPI_FMEM_PMS0_ADDR_S_M (SPI_FMEM_PMS0_ADDR_S_V << SPI_FMEM_PMS0_ADDR_S_S) -#define SPI_FMEM_PMS0_ADDR_S_V 0x07FFFFFFU +#define SPI_FMEM_PMS0_ADDR_S_V 0x1FFFFFFFU #define SPI_FMEM_PMS0_ADDR_S_S 0 /** SPI_FMEM_PMS1_ADDR_REG register * SPI1 flash PMS section 1 start address register */ #define SPI_FMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x114) -/** SPI_FMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0; +/** SPI_FMEM_PMS1_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 flash PMS section 1 start address value */ -#define SPI_FMEM_PMS1_ADDR_S 0x07FFFFFFU +#define SPI_FMEM_PMS1_ADDR_S 0x1FFFFFFFU #define SPI_FMEM_PMS1_ADDR_S_M (SPI_FMEM_PMS1_ADDR_S_V << SPI_FMEM_PMS1_ADDR_S_S) -#define SPI_FMEM_PMS1_ADDR_S_V 0x07FFFFFFU +#define SPI_FMEM_PMS1_ADDR_S_V 0x1FFFFFFFU #define SPI_FMEM_PMS1_ADDR_S_S 0 /** SPI_FMEM_PMS2_ADDR_REG register * SPI1 flash PMS section 2 start address register */ #define SPI_FMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x118) -/** SPI_FMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0; +/** SPI_FMEM_PMS2_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 flash PMS section 2 start address value */ -#define SPI_FMEM_PMS2_ADDR_S 0x07FFFFFFU +#define SPI_FMEM_PMS2_ADDR_S 0x1FFFFFFFU #define SPI_FMEM_PMS2_ADDR_S_M (SPI_FMEM_PMS2_ADDR_S_V << SPI_FMEM_PMS2_ADDR_S_S) -#define SPI_FMEM_PMS2_ADDR_S_V 0x07FFFFFFU +#define SPI_FMEM_PMS2_ADDR_S_V 0x1FFFFFFFU #define SPI_FMEM_PMS2_ADDR_S_S 0 /** SPI_FMEM_PMS3_ADDR_REG register * SPI1 flash PMS section 3 start address register */ #define SPI_FMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x11c) -/** SPI_FMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0; +/** SPI_FMEM_PMS3_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 flash PMS section 3 start address value */ -#define SPI_FMEM_PMS3_ADDR_S 0x07FFFFFFU +#define SPI_FMEM_PMS3_ADDR_S 0x1FFFFFFFU #define SPI_FMEM_PMS3_ADDR_S_M (SPI_FMEM_PMS3_ADDR_S_V << SPI_FMEM_PMS3_ADDR_S_S) -#define SPI_FMEM_PMS3_ADDR_S_V 0x07FFFFFFU +#define SPI_FMEM_PMS3_ADDR_S_V 0x1FFFFFFFU #define SPI_FMEM_PMS3_ADDR_S_S 0 /** SPI_FMEM_PMS0_SIZE_REG register * SPI1 flash PMS section 0 start address register */ #define SPI_FMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x120) -/** SPI_FMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; +/** SPI_FMEM_PMS0_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 flash PMS section 0 address region is (SPI_FMEM_PMS0_ADDR_S, * SPI_FMEM_PMS0_ADDR_S + SPI_FMEM_PMS0_SIZE) */ -#define SPI_FMEM_PMS0_SIZE 0x00007FFFU +#define SPI_FMEM_PMS0_SIZE 0x0001FFFFU #define SPI_FMEM_PMS0_SIZE_M (SPI_FMEM_PMS0_SIZE_V << SPI_FMEM_PMS0_SIZE_S) -#define SPI_FMEM_PMS0_SIZE_V 0x00007FFFU +#define SPI_FMEM_PMS0_SIZE_V 0x0001FFFFU #define SPI_FMEM_PMS0_SIZE_S 0 /** SPI_FMEM_PMS1_SIZE_REG register * SPI1 flash PMS section 1 start address register */ #define SPI_FMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x124) -/** SPI_FMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; +/** SPI_FMEM_PMS1_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 flash PMS section 1 address region is (SPI_FMEM_PMS1_ADDR_S, * SPI_FMEM_PMS1_ADDR_S + SPI_FMEM_PMS1_SIZE) */ -#define SPI_FMEM_PMS1_SIZE 0x00007FFFU +#define SPI_FMEM_PMS1_SIZE 0x0001FFFFU #define SPI_FMEM_PMS1_SIZE_M (SPI_FMEM_PMS1_SIZE_V << SPI_FMEM_PMS1_SIZE_S) -#define SPI_FMEM_PMS1_SIZE_V 0x00007FFFU +#define SPI_FMEM_PMS1_SIZE_V 0x0001FFFFU #define SPI_FMEM_PMS1_SIZE_S 0 /** SPI_FMEM_PMS2_SIZE_REG register * SPI1 flash PMS section 2 start address register */ #define SPI_FMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x128) -/** SPI_FMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; +/** SPI_FMEM_PMS2_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 flash PMS section 2 address region is (SPI_FMEM_PMS2_ADDR_S, * SPI_FMEM_PMS2_ADDR_S + SPI_FMEM_PMS2_SIZE) */ -#define SPI_FMEM_PMS2_SIZE 0x00007FFFU +#define SPI_FMEM_PMS2_SIZE 0x0001FFFFU #define SPI_FMEM_PMS2_SIZE_M (SPI_FMEM_PMS2_SIZE_V << SPI_FMEM_PMS2_SIZE_S) -#define SPI_FMEM_PMS2_SIZE_V 0x00007FFFU +#define SPI_FMEM_PMS2_SIZE_V 0x0001FFFFU #define SPI_FMEM_PMS2_SIZE_S 0 /** SPI_FMEM_PMS3_SIZE_REG register * SPI1 flash PMS section 3 start address register */ #define SPI_FMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x12c) -/** SPI_FMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; +/** SPI_FMEM_PMS3_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 flash PMS section 3 address region is (SPI_FMEM_PMS3_ADDR_S, * SPI_FMEM_PMS3_ADDR_S + SPI_FMEM_PMS3_SIZE) */ -#define SPI_FMEM_PMS3_SIZE 0x00007FFFU +#define SPI_FMEM_PMS3_SIZE 0x0001FFFFU #define SPI_FMEM_PMS3_SIZE_M (SPI_FMEM_PMS3_SIZE_V << SPI_FMEM_PMS3_SIZE_S) -#define SPI_FMEM_PMS3_SIZE_V 0x00007FFFU +#define SPI_FMEM_PMS3_SIZE_V 0x0001FFFFU #define SPI_FMEM_PMS3_SIZE_S 0 /** SPI_SMEM_PMS0_ATTR_REG register @@ -1816,114 +1954,106 @@ extern "C" { * SPI1 external RAM PMS section 0 start address register */ #define SPI_SMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x140) -/** SPI_SMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; +/** SPI_SMEM_PMS0_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 external RAM PMS section 0 start address value */ -#define SPI_SMEM_PMS0_ADDR_S 0x07FFFFFFU +#define SPI_SMEM_PMS0_ADDR_S 0x1FFFFFFFU #define SPI_SMEM_PMS0_ADDR_S_M (SPI_SMEM_PMS0_ADDR_S_V << SPI_SMEM_PMS0_ADDR_S_S) -#define SPI_SMEM_PMS0_ADDR_S_V 0x07FFFFFFU +#define SPI_SMEM_PMS0_ADDR_S_V 0x1FFFFFFFU #define SPI_SMEM_PMS0_ADDR_S_S 0 /** SPI_SMEM_PMS1_ADDR_REG register * SPI1 external RAM PMS section 1 start address register */ #define SPI_SMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x144) -/** SPI_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0; +/** SPI_SMEM_PMS1_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 external RAM PMS section 1 start address value */ -#define SPI_SMEM_PMS1_ADDR_S 0x07FFFFFFU +#define SPI_SMEM_PMS1_ADDR_S 0x1FFFFFFFU #define SPI_SMEM_PMS1_ADDR_S_M (SPI_SMEM_PMS1_ADDR_S_V << SPI_SMEM_PMS1_ADDR_S_S) -#define SPI_SMEM_PMS1_ADDR_S_V 0x07FFFFFFU +#define SPI_SMEM_PMS1_ADDR_S_V 0x1FFFFFFFU #define SPI_SMEM_PMS1_ADDR_S_S 0 /** SPI_SMEM_PMS2_ADDR_REG register * SPI1 external RAM PMS section 2 start address register */ #define SPI_SMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x148) -/** SPI_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0; +/** SPI_SMEM_PMS2_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 external RAM PMS section 2 start address value */ -#define SPI_SMEM_PMS2_ADDR_S 0x07FFFFFFU +#define SPI_SMEM_PMS2_ADDR_S 0x1FFFFFFFU #define SPI_SMEM_PMS2_ADDR_S_M (SPI_SMEM_PMS2_ADDR_S_V << SPI_SMEM_PMS2_ADDR_S_S) -#define SPI_SMEM_PMS2_ADDR_S_V 0x07FFFFFFU +#define SPI_SMEM_PMS2_ADDR_S_V 0x1FFFFFFFU #define SPI_SMEM_PMS2_ADDR_S_S 0 /** SPI_SMEM_PMS3_ADDR_REG register * SPI1 external RAM PMS section 3 start address register */ #define SPI_SMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x14c) -/** SPI_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0; +/** SPI_SMEM_PMS3_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 external RAM PMS section 3 start address value */ -#define SPI_SMEM_PMS3_ADDR_S 0x07FFFFFFU +#define SPI_SMEM_PMS3_ADDR_S 0x1FFFFFFFU #define SPI_SMEM_PMS3_ADDR_S_M (SPI_SMEM_PMS3_ADDR_S_V << SPI_SMEM_PMS3_ADDR_S_S) -#define SPI_SMEM_PMS3_ADDR_S_V 0x07FFFFFFU +#define SPI_SMEM_PMS3_ADDR_S_V 0x1FFFFFFFU #define SPI_SMEM_PMS3_ADDR_S_S 0 /** SPI_SMEM_PMS0_SIZE_REG register * SPI1 external RAM PMS section 0 start address register */ #define SPI_SMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x150) -/** SPI_SMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; +/** SPI_SMEM_PMS0_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 external RAM PMS section 0 address region is (SPI_SMEM_PMS0_ADDR_S, * SPI_SMEM_PMS0_ADDR_S + SPI_SMEM_PMS0_SIZE) */ -#define SPI_SMEM_PMS0_SIZE 0x00007FFFU +#define SPI_SMEM_PMS0_SIZE 0x0001FFFFU #define SPI_SMEM_PMS0_SIZE_M (SPI_SMEM_PMS0_SIZE_V << SPI_SMEM_PMS0_SIZE_S) -#define SPI_SMEM_PMS0_SIZE_V 0x00007FFFU +#define SPI_SMEM_PMS0_SIZE_V 0x0001FFFFU #define SPI_SMEM_PMS0_SIZE_S 0 /** SPI_SMEM_PMS1_SIZE_REG register * SPI1 external RAM PMS section 1 start address register */ #define SPI_SMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x154) -/** SPI_SMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; +/** SPI_SMEM_PMS1_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 external RAM PMS section 1 address region is (SPI_SMEM_PMS1_ADDR_S, * SPI_SMEM_PMS1_ADDR_S + SPI_SMEM_PMS1_SIZE) */ -#define SPI_SMEM_PMS1_SIZE 0x00007FFFU +#define SPI_SMEM_PMS1_SIZE 0x0001FFFFU #define SPI_SMEM_PMS1_SIZE_M (SPI_SMEM_PMS1_SIZE_V << SPI_SMEM_PMS1_SIZE_S) -#define SPI_SMEM_PMS1_SIZE_V 0x00007FFFU +#define SPI_SMEM_PMS1_SIZE_V 0x0001FFFFU #define SPI_SMEM_PMS1_SIZE_S 0 /** SPI_SMEM_PMS2_SIZE_REG register * SPI1 external RAM PMS section 2 start address register */ #define SPI_SMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x158) -/** SPI_SMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; +/** SPI_SMEM_PMS2_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 external RAM PMS section 2 address region is (SPI_SMEM_PMS2_ADDR_S, * SPI_SMEM_PMS2_ADDR_S + SPI_SMEM_PMS2_SIZE) */ -#define SPI_SMEM_PMS2_SIZE 0x00007FFFU +#define SPI_SMEM_PMS2_SIZE 0x0001FFFFU #define SPI_SMEM_PMS2_SIZE_M (SPI_SMEM_PMS2_SIZE_V << SPI_SMEM_PMS2_SIZE_S) -#define SPI_SMEM_PMS2_SIZE_V 0x00007FFFU +#define SPI_SMEM_PMS2_SIZE_V 0x0001FFFFU #define SPI_SMEM_PMS2_SIZE_S 0 /** SPI_SMEM_PMS3_SIZE_REG register * SPI1 external RAM PMS section 3 start address register */ #define SPI_SMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x15c) -/** SPI_SMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; +/** SPI_SMEM_PMS3_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 external RAM PMS section 3 address region is (SPI_SMEM_PMS3_ADDR_S, * SPI_SMEM_PMS3_ADDR_S + SPI_SMEM_PMS3_SIZE) */ -#define SPI_SMEM_PMS3_SIZE 0x00007FFFU +#define SPI_SMEM_PMS3_SIZE 0x0001FFFFU #define SPI_SMEM_PMS3_SIZE_M (SPI_SMEM_PMS3_SIZE_V << SPI_SMEM_PMS3_SIZE_S) -#define SPI_SMEM_PMS3_SIZE_V 0x00007FFFU +#define SPI_SMEM_PMS3_SIZE_V 0x0001FFFFU #define SPI_SMEM_PMS3_SIZE_S 0 /** SPI_MEM_PMS_REJECT_REG register * SPI1 access reject register */ -#define SPI_MEM_PMS_REJECT_REG(i) (REG_SPI_MEM_BASE(i) + 0x164) -/** SPI_MEM_REJECT_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0; - * This bits show the first SPI1 access error address. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ -#define SPI_MEM_REJECT_ADDR 0x07FFFFFFU -#define SPI_MEM_REJECT_ADDR_M (SPI_MEM_REJECT_ADDR_V << SPI_MEM_REJECT_ADDR_S) -#define SPI_MEM_REJECT_ADDR_V 0x07FFFFFFU -#define SPI_MEM_REJECT_ADDR_S 0 +#define SPI_MEM_PMS_REJECT_REG(i) (REG_SPI_MEM_BASE(i) + 0x160) /** SPI_MEM_PM_EN : R/W; bitpos: [27]; default: 0; * Set this bit to enable SPI0/1 transfer permission control function. */ @@ -1964,11 +2094,24 @@ extern "C" { #define SPI_MEM_PMS_IVD_V 0x00000001U #define SPI_MEM_PMS_IVD_S 31 +/** SPI_MEM_PMS_REJECT_ADDR_REG register + * SPI1 access reject addr register + */ +#define SPI_MEM_PMS_REJECT_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x164) +/** SPI_MEM_REJECT_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; + * This bits show the first SPI1 access error address. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_REJECT_ADDR 0x1FFFFFFFU +#define SPI_MEM_REJECT_ADDR_M (SPI_MEM_REJECT_ADDR_V << SPI_MEM_REJECT_ADDR_S) +#define SPI_MEM_REJECT_ADDR_V 0x1FFFFFFFU +#define SPI_MEM_REJECT_ADDR_S 0 + /** SPI_MEM_ECC_CTRL_REG register * MSPI ECC control register */ #define SPI_MEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x168) -/** SPI_MEM_ECC_ERR_CNT : HRO; bitpos: [10:5]; default: 0; +/** SPI_MEM_ECC_ERR_CNT : R/SS/WTC; bitpos: [10:5]; default: 0; * This bits show the error times of MSPI ECC read. It is cleared by when * SPI_MEM_ECC_ERR_INT_CLR bit is set. */ @@ -1976,14 +2119,14 @@ extern "C" { #define SPI_MEM_ECC_ERR_CNT_M (SPI_MEM_ECC_ERR_CNT_V << SPI_MEM_ECC_ERR_CNT_S) #define SPI_MEM_ECC_ERR_CNT_V 0x0000003FU #define SPI_MEM_ECC_ERR_CNT_S 5 -/** SPI_FMEM_ECC_ERR_INT_NUM : HRO; bitpos: [16:11]; default: 10; +/** SPI_FMEM_ECC_ERR_INT_NUM : R/W; bitpos: [16:11]; default: 10; * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. */ #define SPI_FMEM_ECC_ERR_INT_NUM 0x0000003FU #define SPI_FMEM_ECC_ERR_INT_NUM_M (SPI_FMEM_ECC_ERR_INT_NUM_V << SPI_FMEM_ECC_ERR_INT_NUM_S) #define SPI_FMEM_ECC_ERR_INT_NUM_V 0x0000003FU #define SPI_FMEM_ECC_ERR_INT_NUM_S 11 -/** SPI_FMEM_ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0; +/** SPI_FMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. */ #define SPI_FMEM_ECC_ERR_INT_EN (BIT(17)) @@ -1998,23 +2141,23 @@ extern "C" { #define SPI_FMEM_PAGE_SIZE_M (SPI_FMEM_PAGE_SIZE_V << SPI_FMEM_PAGE_SIZE_S) #define SPI_FMEM_PAGE_SIZE_V 0x00000003U #define SPI_FMEM_PAGE_SIZE_S 18 -/** SPI_FMEM_ECC_ADDR_EN : HRO; bitpos: [20]; default: 0; +/** SPI_FMEM_ECC_ADDR_EN : R/W; bitpos: [21]; default: 0; * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit * should be 0. Otherwise, this bit should be 1. */ -#define SPI_FMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_FMEM_ECC_ADDR_EN (BIT(21)) #define SPI_FMEM_ECC_ADDR_EN_M (SPI_FMEM_ECC_ADDR_EN_V << SPI_FMEM_ECC_ADDR_EN_S) #define SPI_FMEM_ECC_ADDR_EN_V 0x00000001U -#define SPI_FMEM_ECC_ADDR_EN_S 20 -/** SPI_MEM_USR_ECC_ADDR_EN : HRO; bitpos: [21]; default: 0; +#define SPI_FMEM_ECC_ADDR_EN_S 21 +/** SPI_MEM_USR_ECC_ADDR_EN : R/W; bitpos: [22]; default: 0; * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. */ -#define SPI_MEM_USR_ECC_ADDR_EN (BIT(21)) +#define SPI_MEM_USR_ECC_ADDR_EN (BIT(22)) #define SPI_MEM_USR_ECC_ADDR_EN_M (SPI_MEM_USR_ECC_ADDR_EN_V << SPI_MEM_USR_ECC_ADDR_EN_S) #define SPI_MEM_USR_ECC_ADDR_EN_V 0x00000001U -#define SPI_MEM_USR_ECC_ADDR_EN_S 21 -/** SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : HRO; bitpos: [24]; default: 1; +#define SPI_MEM_USR_ECC_ADDR_EN_S 22 +/** SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : R/W; bitpos: [24]; default: 1; * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. @@ -2023,7 +2166,7 @@ extern "C" { #define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M (SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S) #define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V 0x00000001U #define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S 24 -/** SPI_MEM_ECC_ERR_BITS : HRO; bitpos: [31:25]; default: 0; +/** SPI_MEM_ECC_ERR_BITS : R/SS/WTC; bitpos: [31:25]; default: 0; * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to * byte 0 bit 0 to byte 15 bit 7) */ @@ -2036,34 +2179,34 @@ extern "C" { * MSPI ECC error address register */ #define SPI_MEM_ECC_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x16c) -/** SPI_MEM_ECC_ERR_ADDR : HRO; bitpos: [26:0]; default: 0; +/** SPI_MEM_ECC_ERR_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; * This bits show the first MSPI ECC error address. It is cleared by when * SPI_MEM_ECC_ERR_INT_CLR bit is set. */ -#define SPI_MEM_ECC_ERR_ADDR 0x07FFFFFFU +#define SPI_MEM_ECC_ERR_ADDR 0x1FFFFFFFU #define SPI_MEM_ECC_ERR_ADDR_M (SPI_MEM_ECC_ERR_ADDR_V << SPI_MEM_ECC_ERR_ADDR_S) -#define SPI_MEM_ECC_ERR_ADDR_V 0x07FFFFFFU +#define SPI_MEM_ECC_ERR_ADDR_V 0x1FFFFFFFU #define SPI_MEM_ECC_ERR_ADDR_S 0 /** SPI_MEM_AXI_ERR_ADDR_REG register * SPI0 AXI request error address. */ #define SPI_MEM_AXI_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x170) -/** SPI_MEM_AXI_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0; +/** SPI_MEM_AXI_ERR_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; * This bits show the first AXI write/read invalid error or AXI write flash error * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */ -#define SPI_MEM_AXI_ERR_ADDR 0x07FFFFFFU +#define SPI_MEM_AXI_ERR_ADDR 0x1FFFFFFFU #define SPI_MEM_AXI_ERR_ADDR_M (SPI_MEM_AXI_ERR_ADDR_V << SPI_MEM_AXI_ERR_ADDR_S) -#define SPI_MEM_AXI_ERR_ADDR_V 0x07FFFFFFU +#define SPI_MEM_AXI_ERR_ADDR_V 0x1FFFFFFFU #define SPI_MEM_AXI_ERR_ADDR_S 0 /** SPI_SMEM_ECC_CTRL_REG register * MSPI ECC control register */ #define SPI_SMEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x174) -/** SPI_SMEM_ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0; +/** SPI_SMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; * Set this bit to calculate the error times of MSPI ECC read when accesses to * external RAM. */ @@ -2071,7 +2214,7 @@ extern "C" { #define SPI_SMEM_ECC_ERR_INT_EN_M (SPI_SMEM_ECC_ERR_INT_EN_V << SPI_SMEM_ECC_ERR_INT_EN_S) #define SPI_SMEM_ECC_ERR_INT_EN_V 0x00000001U #define SPI_SMEM_ECC_ERR_INT_EN_S 17 -/** SPI_SMEM_PAGE_SIZE : HRO; bitpos: [19:18]; default: 2; +/** SPI_SMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 2; * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. * 2: 1024 bytes. 3: 2048 bytes. */ @@ -2079,7 +2222,7 @@ extern "C" { #define SPI_SMEM_PAGE_SIZE_M (SPI_SMEM_PAGE_SIZE_V << SPI_SMEM_PAGE_SIZE_S) #define SPI_SMEM_PAGE_SIZE_V 0x00000003U #define SPI_SMEM_PAGE_SIZE_S 18 -/** SPI_SMEM_ECC_ADDR_EN : HRO; bitpos: [20]; default: 0; +/** SPI_SMEM_ECC_ADDR_EN : R/W; bitpos: [20]; default: 0; * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the * ECC region or non-ECC region of external RAM. If there is no ECC region in external * RAM, this bit should be 0. Otherwise, this bit should be 1. @@ -2142,49 +2285,49 @@ extern "C" { * SPI0 AXI error response enable register */ #define SPI_MEM_AXI_ERR_RESP_EN_REG(i) (REG_SPI_MEM_BASE(i) + 0x17c) -/** SPI_MEM_AW_RESP_EN_MMU_VLD : HRO; bitpos: [0]; default: 0; +/** SPI_MEM_AW_RESP_EN_MMU_VLD : R/W; bitpos: [0]; default: 0; * Set this bit to enable AXI response function for mmu valid err in axi write trans. */ #define SPI_MEM_AW_RESP_EN_MMU_VLD (BIT(0)) #define SPI_MEM_AW_RESP_EN_MMU_VLD_M (SPI_MEM_AW_RESP_EN_MMU_VLD_V << SPI_MEM_AW_RESP_EN_MMU_VLD_S) #define SPI_MEM_AW_RESP_EN_MMU_VLD_V 0x00000001U #define SPI_MEM_AW_RESP_EN_MMU_VLD_S 0 -/** SPI_MEM_AW_RESP_EN_MMU_GID : HRO; bitpos: [1]; default: 0; +/** SPI_MEM_AW_RESP_EN_MMU_GID : R/W; bitpos: [1]; default: 0; * Set this bit to enable AXI response function for mmu gid err in axi write trans. */ #define SPI_MEM_AW_RESP_EN_MMU_GID (BIT(1)) #define SPI_MEM_AW_RESP_EN_MMU_GID_M (SPI_MEM_AW_RESP_EN_MMU_GID_V << SPI_MEM_AW_RESP_EN_MMU_GID_S) #define SPI_MEM_AW_RESP_EN_MMU_GID_V 0x00000001U #define SPI_MEM_AW_RESP_EN_MMU_GID_S 1 -/** SPI_MEM_AW_RESP_EN_AXI_SIZE : HRO; bitpos: [2]; default: 0; +/** SPI_MEM_AW_RESP_EN_AXI_SIZE : R/W; bitpos: [2]; default: 0; * Set this bit to enable AXI response function for axi size err in axi write trans. */ #define SPI_MEM_AW_RESP_EN_AXI_SIZE (BIT(2)) #define SPI_MEM_AW_RESP_EN_AXI_SIZE_M (SPI_MEM_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_AW_RESP_EN_AXI_SIZE_S) #define SPI_MEM_AW_RESP_EN_AXI_SIZE_V 0x00000001U #define SPI_MEM_AW_RESP_EN_AXI_SIZE_S 2 -/** SPI_MEM_AW_RESP_EN_AXI_FLASH : HRO; bitpos: [3]; default: 0; +/** SPI_MEM_AW_RESP_EN_AXI_FLASH : R/W; bitpos: [3]; default: 0; * Set this bit to enable AXI response function for axi flash err in axi write trans. */ #define SPI_MEM_AW_RESP_EN_AXI_FLASH (BIT(3)) #define SPI_MEM_AW_RESP_EN_AXI_FLASH_M (SPI_MEM_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_AW_RESP_EN_AXI_FLASH_S) #define SPI_MEM_AW_RESP_EN_AXI_FLASH_V 0x00000001U #define SPI_MEM_AW_RESP_EN_AXI_FLASH_S 3 -/** SPI_MEM_AW_RESP_EN_MMU_ECC : HRO; bitpos: [4]; default: 0; +/** SPI_MEM_AW_RESP_EN_MMU_ECC : R/W; bitpos: [4]; default: 0; * Set this bit to enable AXI response function for mmu ecc err in axi write trans. */ #define SPI_MEM_AW_RESP_EN_MMU_ECC (BIT(4)) #define SPI_MEM_AW_RESP_EN_MMU_ECC_M (SPI_MEM_AW_RESP_EN_MMU_ECC_V << SPI_MEM_AW_RESP_EN_MMU_ECC_S) #define SPI_MEM_AW_RESP_EN_MMU_ECC_V 0x00000001U #define SPI_MEM_AW_RESP_EN_MMU_ECC_S 4 -/** SPI_MEM_AW_RESP_EN_MMU_SENS : HRO; bitpos: [5]; default: 0; +/** SPI_MEM_AW_RESP_EN_MMU_SENS : R/W; bitpos: [5]; default: 0; * Set this bit to enable AXI response function for mmu sens in err axi write trans. */ #define SPI_MEM_AW_RESP_EN_MMU_SENS (BIT(5)) #define SPI_MEM_AW_RESP_EN_MMU_SENS_M (SPI_MEM_AW_RESP_EN_MMU_SENS_V << SPI_MEM_AW_RESP_EN_MMU_SENS_S) #define SPI_MEM_AW_RESP_EN_MMU_SENS_V 0x00000001U #define SPI_MEM_AW_RESP_EN_MMU_SENS_S 5 -/** SPI_MEM_AW_RESP_EN_AXI_WSTRB : HRO; bitpos: [6]; default: 0; +/** SPI_MEM_AW_RESP_EN_AXI_WSTRB : R/W; bitpos: [6]; default: 0; * Set this bit to enable AXI response function for axi wstrb err in axi write trans. */ #define SPI_MEM_AW_RESP_EN_AXI_WSTRB (BIT(6)) @@ -2253,7 +2396,7 @@ extern "C" { #define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M (SPI_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_EXTRA_DUMMY_CYCLELEN_S) #define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U #define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 -/** SPI_MEM_DLL_TIMING_CALI : HRO; bitpos: [5]; default: 0; +/** SPI_MEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; * Set this bit to enable DLL for timing calibration in DDR mode when accessed to * flash. */ @@ -2530,14 +2673,14 @@ extern "C" { * MSPI external RAM timing calibration register */ #define SPI_SMEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x190) -/** SPI_SMEM_TIMING_CLK_ENA : HRO; bitpos: [0]; default: 1; +/** SPI_SMEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; * For sram, the bit is used to enable timing adjust clock for all reading operations. */ #define SPI_SMEM_TIMING_CLK_ENA (BIT(0)) #define SPI_SMEM_TIMING_CLK_ENA_M (SPI_SMEM_TIMING_CLK_ENA_V << SPI_SMEM_TIMING_CLK_ENA_S) #define SPI_SMEM_TIMING_CLK_ENA_V 0x00000001U #define SPI_SMEM_TIMING_CLK_ENA_S 0 -/** SPI_SMEM_TIMING_CALI : HRO; bitpos: [1]; default: 0; +/** SPI_SMEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; * For sram, the bit is used to enable timing auto-calibration for all reading * operations. */ @@ -2545,14 +2688,14 @@ extern "C" { #define SPI_SMEM_TIMING_CALI_M (SPI_SMEM_TIMING_CALI_V << SPI_SMEM_TIMING_CALI_S) #define SPI_SMEM_TIMING_CALI_V 0x00000001U #define SPI_SMEM_TIMING_CALI_S 1 -/** SPI_SMEM_EXTRA_DUMMY_CYCLELEN : HRO; bitpos: [4:2]; default: 0; +/** SPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; * For sram, add extra dummy spi clock cycle length for spi clock calibration. */ #define SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007U #define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M (SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S) #define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U #define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 -/** SPI_SMEM_DLL_TIMING_CALI : HRO; bitpos: [5]; default: 0; +/** SPI_SMEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; * Set this bit to enable DLL for timing calibration in DDR mode when accessed to * EXT_RAM. */ @@ -2560,12 +2703,28 @@ extern "C" { #define SPI_SMEM_DLL_TIMING_CALI_M (SPI_SMEM_DLL_TIMING_CALI_V << SPI_SMEM_DLL_TIMING_CALI_S) #define SPI_SMEM_DLL_TIMING_CALI_V 0x00000001U #define SPI_SMEM_DLL_TIMING_CALI_S 5 +/** SPI_SMEM_DQS0_270_SEL : R/W; bitpos: [8:7]; default: 1; + * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. + * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. + */ +#define SPI_SMEM_DQS0_270_SEL 0x00000003U +#define SPI_SMEM_DQS0_270_SEL_M (SPI_SMEM_DQS0_270_SEL_V << SPI_SMEM_DQS0_270_SEL_S) +#define SPI_SMEM_DQS0_270_SEL_V 0x00000003U +#define SPI_SMEM_DQS0_270_SEL_S 7 +/** SPI_SMEM_DQS0_90_SEL : R/W; bitpos: [10:9]; default: 1; + * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, + * 2'd2: 1.5ns 2'd3: 2.0ns. + */ +#define SPI_SMEM_DQS0_90_SEL 0x00000003U +#define SPI_SMEM_DQS0_90_SEL_M (SPI_SMEM_DQS0_90_SEL_V << SPI_SMEM_DQS0_90_SEL_S) +#define SPI_SMEM_DQS0_90_SEL_V 0x00000003U +#define SPI_SMEM_DQS0_90_SEL_S 9 /** SPI_SMEM_DIN_MODE_REG register * MSPI external RAM input timing delay mode control register */ #define SPI_SMEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x194) -/** SPI_SMEM_DIN0_MODE : HRO; bitpos: [2:0]; default: 0; +/** SPI_SMEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -2575,7 +2734,7 @@ extern "C" { #define SPI_SMEM_DIN0_MODE_M (SPI_SMEM_DIN0_MODE_V << SPI_SMEM_DIN0_MODE_S) #define SPI_SMEM_DIN0_MODE_V 0x00000007U #define SPI_SMEM_DIN0_MODE_S 0 -/** SPI_SMEM_DIN1_MODE : HRO; bitpos: [5:3]; default: 0; +/** SPI_SMEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -2585,7 +2744,7 @@ extern "C" { #define SPI_SMEM_DIN1_MODE_M (SPI_SMEM_DIN1_MODE_V << SPI_SMEM_DIN1_MODE_S) #define SPI_SMEM_DIN1_MODE_V 0x00000007U #define SPI_SMEM_DIN1_MODE_S 3 -/** SPI_SMEM_DIN2_MODE : HRO; bitpos: [8:6]; default: 0; +/** SPI_SMEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -2595,7 +2754,7 @@ extern "C" { #define SPI_SMEM_DIN2_MODE_M (SPI_SMEM_DIN2_MODE_V << SPI_SMEM_DIN2_MODE_S) #define SPI_SMEM_DIN2_MODE_V 0x00000007U #define SPI_SMEM_DIN2_MODE_S 6 -/** SPI_SMEM_DIN3_MODE : HRO; bitpos: [11:9]; default: 0; +/** SPI_SMEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -2605,7 +2764,7 @@ extern "C" { #define SPI_SMEM_DIN3_MODE_M (SPI_SMEM_DIN3_MODE_V << SPI_SMEM_DIN3_MODE_S) #define SPI_SMEM_DIN3_MODE_V 0x00000007U #define SPI_SMEM_DIN3_MODE_S 9 -/** SPI_SMEM_DIN4_MODE : HRO; bitpos: [14:12]; default: 0; +/** SPI_SMEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -2615,7 +2774,7 @@ extern "C" { #define SPI_SMEM_DIN4_MODE_M (SPI_SMEM_DIN4_MODE_V << SPI_SMEM_DIN4_MODE_S) #define SPI_SMEM_DIN4_MODE_V 0x00000007U #define SPI_SMEM_DIN4_MODE_S 12 -/** SPI_SMEM_DIN5_MODE : HRO; bitpos: [17:15]; default: 0; +/** SPI_SMEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -2625,7 +2784,7 @@ extern "C" { #define SPI_SMEM_DIN5_MODE_M (SPI_SMEM_DIN5_MODE_V << SPI_SMEM_DIN5_MODE_S) #define SPI_SMEM_DIN5_MODE_V 0x00000007U #define SPI_SMEM_DIN5_MODE_S 15 -/** SPI_SMEM_DIN6_MODE : HRO; bitpos: [20:18]; default: 0; +/** SPI_SMEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -2635,7 +2794,7 @@ extern "C" { #define SPI_SMEM_DIN6_MODE_M (SPI_SMEM_DIN6_MODE_V << SPI_SMEM_DIN6_MODE_S) #define SPI_SMEM_DIN6_MODE_V 0x00000007U #define SPI_SMEM_DIN6_MODE_S 18 -/** SPI_SMEM_DIN7_MODE : HRO; bitpos: [23:21]; default: 0; +/** SPI_SMEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -2645,7 +2804,7 @@ extern "C" { #define SPI_SMEM_DIN7_MODE_M (SPI_SMEM_DIN7_MODE_V << SPI_SMEM_DIN7_MODE_S) #define SPI_SMEM_DIN7_MODE_V 0x00000007U #define SPI_SMEM_DIN7_MODE_S 21 -/** SPI_SMEM_DINS_MODE : HRO; bitpos: [26:24]; default: 0; +/** SPI_SMEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -2660,7 +2819,7 @@ extern "C" { * MSPI external RAM input timing delay number control register */ #define SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x198) -/** SPI_SMEM_DIN0_NUM : HRO; bitpos: [1:0]; default: 0; +/** SPI_SMEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -2668,7 +2827,7 @@ extern "C" { #define SPI_SMEM_DIN0_NUM_M (SPI_SMEM_DIN0_NUM_V << SPI_SMEM_DIN0_NUM_S) #define SPI_SMEM_DIN0_NUM_V 0x00000003U #define SPI_SMEM_DIN0_NUM_S 0 -/** SPI_SMEM_DIN1_NUM : HRO; bitpos: [3:2]; default: 0; +/** SPI_SMEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -2676,7 +2835,7 @@ extern "C" { #define SPI_SMEM_DIN1_NUM_M (SPI_SMEM_DIN1_NUM_V << SPI_SMEM_DIN1_NUM_S) #define SPI_SMEM_DIN1_NUM_V 0x00000003U #define SPI_SMEM_DIN1_NUM_S 2 -/** SPI_SMEM_DIN2_NUM : HRO; bitpos: [5:4]; default: 0; +/** SPI_SMEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -2684,7 +2843,7 @@ extern "C" { #define SPI_SMEM_DIN2_NUM_M (SPI_SMEM_DIN2_NUM_V << SPI_SMEM_DIN2_NUM_S) #define SPI_SMEM_DIN2_NUM_V 0x00000003U #define SPI_SMEM_DIN2_NUM_S 4 -/** SPI_SMEM_DIN3_NUM : HRO; bitpos: [7:6]; default: 0; +/** SPI_SMEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -2692,7 +2851,7 @@ extern "C" { #define SPI_SMEM_DIN3_NUM_M (SPI_SMEM_DIN3_NUM_V << SPI_SMEM_DIN3_NUM_S) #define SPI_SMEM_DIN3_NUM_V 0x00000003U #define SPI_SMEM_DIN3_NUM_S 6 -/** SPI_SMEM_DIN4_NUM : HRO; bitpos: [9:8]; default: 0; +/** SPI_SMEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -2700,7 +2859,7 @@ extern "C" { #define SPI_SMEM_DIN4_NUM_M (SPI_SMEM_DIN4_NUM_V << SPI_SMEM_DIN4_NUM_S) #define SPI_SMEM_DIN4_NUM_V 0x00000003U #define SPI_SMEM_DIN4_NUM_S 8 -/** SPI_SMEM_DIN5_NUM : HRO; bitpos: [11:10]; default: 0; +/** SPI_SMEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -2708,7 +2867,7 @@ extern "C" { #define SPI_SMEM_DIN5_NUM_M (SPI_SMEM_DIN5_NUM_V << SPI_SMEM_DIN5_NUM_S) #define SPI_SMEM_DIN5_NUM_V 0x00000003U #define SPI_SMEM_DIN5_NUM_S 10 -/** SPI_SMEM_DIN6_NUM : HRO; bitpos: [13:12]; default: 0; +/** SPI_SMEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -2716,7 +2875,7 @@ extern "C" { #define SPI_SMEM_DIN6_NUM_M (SPI_SMEM_DIN6_NUM_V << SPI_SMEM_DIN6_NUM_S) #define SPI_SMEM_DIN6_NUM_V 0x00000003U #define SPI_SMEM_DIN6_NUM_S 12 -/** SPI_SMEM_DIN7_NUM : HRO; bitpos: [15:14]; default: 0; +/** SPI_SMEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -2724,7 +2883,7 @@ extern "C" { #define SPI_SMEM_DIN7_NUM_M (SPI_SMEM_DIN7_NUM_V << SPI_SMEM_DIN7_NUM_S) #define SPI_SMEM_DIN7_NUM_V 0x00000003U #define SPI_SMEM_DIN7_NUM_S 14 -/** SPI_SMEM_DINS_NUM : HRO; bitpos: [17:16]; default: 0; +/** SPI_SMEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -2737,7 +2896,7 @@ extern "C" { * MSPI external RAM output timing adjustment control register */ #define SPI_SMEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x19c) -/** SPI_SMEM_DOUT0_MODE : HRO; bitpos: [0]; default: 0; +/** SPI_SMEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -2747,7 +2906,7 @@ extern "C" { #define SPI_SMEM_DOUT0_MODE_M (SPI_SMEM_DOUT0_MODE_V << SPI_SMEM_DOUT0_MODE_S) #define SPI_SMEM_DOUT0_MODE_V 0x00000001U #define SPI_SMEM_DOUT0_MODE_S 0 -/** SPI_SMEM_DOUT1_MODE : HRO; bitpos: [1]; default: 0; +/** SPI_SMEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -2757,7 +2916,7 @@ extern "C" { #define SPI_SMEM_DOUT1_MODE_M (SPI_SMEM_DOUT1_MODE_V << SPI_SMEM_DOUT1_MODE_S) #define SPI_SMEM_DOUT1_MODE_V 0x00000001U #define SPI_SMEM_DOUT1_MODE_S 1 -/** SPI_SMEM_DOUT2_MODE : HRO; bitpos: [2]; default: 0; +/** SPI_SMEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -2767,7 +2926,7 @@ extern "C" { #define SPI_SMEM_DOUT2_MODE_M (SPI_SMEM_DOUT2_MODE_V << SPI_SMEM_DOUT2_MODE_S) #define SPI_SMEM_DOUT2_MODE_V 0x00000001U #define SPI_SMEM_DOUT2_MODE_S 2 -/** SPI_SMEM_DOUT3_MODE : HRO; bitpos: [3]; default: 0; +/** SPI_SMEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -2777,7 +2936,7 @@ extern "C" { #define SPI_SMEM_DOUT3_MODE_M (SPI_SMEM_DOUT3_MODE_V << SPI_SMEM_DOUT3_MODE_S) #define SPI_SMEM_DOUT3_MODE_V 0x00000001U #define SPI_SMEM_DOUT3_MODE_S 3 -/** SPI_SMEM_DOUT4_MODE : HRO; bitpos: [4]; default: 0; +/** SPI_SMEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -2787,7 +2946,7 @@ extern "C" { #define SPI_SMEM_DOUT4_MODE_M (SPI_SMEM_DOUT4_MODE_V << SPI_SMEM_DOUT4_MODE_S) #define SPI_SMEM_DOUT4_MODE_V 0x00000001U #define SPI_SMEM_DOUT4_MODE_S 4 -/** SPI_SMEM_DOUT5_MODE : HRO; bitpos: [5]; default: 0; +/** SPI_SMEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -2797,7 +2956,7 @@ extern "C" { #define SPI_SMEM_DOUT5_MODE_M (SPI_SMEM_DOUT5_MODE_V << SPI_SMEM_DOUT5_MODE_S) #define SPI_SMEM_DOUT5_MODE_V 0x00000001U #define SPI_SMEM_DOUT5_MODE_S 5 -/** SPI_SMEM_DOUT6_MODE : HRO; bitpos: [6]; default: 0; +/** SPI_SMEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -2807,7 +2966,7 @@ extern "C" { #define SPI_SMEM_DOUT6_MODE_M (SPI_SMEM_DOUT6_MODE_V << SPI_SMEM_DOUT6_MODE_S) #define SPI_SMEM_DOUT6_MODE_V 0x00000001U #define SPI_SMEM_DOUT6_MODE_S 6 -/** SPI_SMEM_DOUT7_MODE : HRO; bitpos: [7]; default: 0; +/** SPI_SMEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -2817,7 +2976,7 @@ extern "C" { #define SPI_SMEM_DOUT7_MODE_M (SPI_SMEM_DOUT7_MODE_V << SPI_SMEM_DOUT7_MODE_S) #define SPI_SMEM_DOUT7_MODE_V 0x00000001U #define SPI_SMEM_DOUT7_MODE_S 7 -/** SPI_SMEM_DOUTS_MODE : HRO; bitpos: [8]; default: 0; +/** SPI_SMEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -2832,7 +2991,7 @@ extern "C" { * MSPI external RAM ECC and SPI CS timing control register */ #define SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0x1a0) -/** SPI_SMEM_CS_SETUP : HRO; bitpos: [0]; default: 0; +/** SPI_SMEM_CS_SETUP : R/W; bitpos: [0]; default: 0; * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: * disable. */ @@ -2840,14 +2999,14 @@ extern "C" { #define SPI_SMEM_CS_SETUP_M (SPI_SMEM_CS_SETUP_V << SPI_SMEM_CS_SETUP_S) #define SPI_SMEM_CS_SETUP_V 0x00000001U #define SPI_SMEM_CS_SETUP_S 0 -/** SPI_SMEM_CS_HOLD : HRO; bitpos: [1]; default: 0; +/** SPI_SMEM_CS_HOLD : R/W; bitpos: [1]; default: 0; * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */ #define SPI_SMEM_CS_HOLD (BIT(1)) #define SPI_SMEM_CS_HOLD_M (SPI_SMEM_CS_HOLD_V << SPI_SMEM_CS_HOLD_S) #define SPI_SMEM_CS_HOLD_V 0x00000001U #define SPI_SMEM_CS_HOLD_S 1 -/** SPI_SMEM_CS_SETUP_TIME : HRO; bitpos: [6:2]; default: 1; +/** SPI_SMEM_CS_SETUP_TIME : R/W; bitpos: [6:2]; default: 1; * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with * spi_mem_cs_setup bit. */ @@ -2855,7 +3014,7 @@ extern "C" { #define SPI_SMEM_CS_SETUP_TIME_M (SPI_SMEM_CS_SETUP_TIME_V << SPI_SMEM_CS_SETUP_TIME_S) #define SPI_SMEM_CS_SETUP_TIME_V 0x0000001FU #define SPI_SMEM_CS_SETUP_TIME_S 2 -/** SPI_SMEM_CS_HOLD_TIME : HRO; bitpos: [11:7]; default: 1; +/** SPI_SMEM_CS_HOLD_TIME : R/W; bitpos: [11:7]; default: 1; * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are * combined with spi_mem_cs_hold bit. */ @@ -2863,7 +3022,7 @@ extern "C" { #define SPI_SMEM_CS_HOLD_TIME_M (SPI_SMEM_CS_HOLD_TIME_V << SPI_SMEM_CS_HOLD_TIME_S) #define SPI_SMEM_CS_HOLD_TIME_V 0x0000001FU #define SPI_SMEM_CS_HOLD_TIME_S 7 -/** SPI_SMEM_ECC_CS_HOLD_TIME : HRO; bitpos: [14:12]; default: 3; +/** SPI_SMEM_ECC_CS_HOLD_TIME : R/W; bitpos: [14:12]; default: 3; * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold * cycles in ECC mode when accessed external RAM. */ @@ -2871,7 +3030,7 @@ extern "C" { #define SPI_SMEM_ECC_CS_HOLD_TIME_M (SPI_SMEM_ECC_CS_HOLD_TIME_V << SPI_SMEM_ECC_CS_HOLD_TIME_S) #define SPI_SMEM_ECC_CS_HOLD_TIME_V 0x00000007U #define SPI_SMEM_ECC_CS_HOLD_TIME_S 12 -/** SPI_SMEM_ECC_SKIP_PAGE_CORNER : HRO; bitpos: [15]; default: 1; +/** SPI_SMEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [15]; default: 1; * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when * accesses external RAM. */ @@ -2879,7 +3038,7 @@ extern "C" { #define SPI_SMEM_ECC_SKIP_PAGE_CORNER_M (SPI_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_SMEM_ECC_SKIP_PAGE_CORNER_S) #define SPI_SMEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U #define SPI_SMEM_ECC_SKIP_PAGE_CORNER_S 15 -/** SPI_SMEM_ECC_16TO18_BYTE_EN : HRO; bitpos: [16]; default: 0; +/** SPI_SMEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [16]; default: 0; * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when * accesses external RAM. */ @@ -2887,7 +3046,7 @@ extern "C" { #define SPI_SMEM_ECC_16TO18_BYTE_EN_M (SPI_SMEM_ECC_16TO18_BYTE_EN_V << SPI_SMEM_ECC_16TO18_BYTE_EN_S) #define SPI_SMEM_ECC_16TO18_BYTE_EN_V 0x00000001U #define SPI_SMEM_ECC_16TO18_BYTE_EN_S 16 -/** SPI_SMEM_CS_HOLD_DELAY : HRO; bitpos: [30:25]; default: 0; +/** SPI_SMEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) * MSPI core clock cycles. @@ -2896,7 +3055,7 @@ extern "C" { #define SPI_SMEM_CS_HOLD_DELAY_M (SPI_SMEM_CS_HOLD_DELAY_V << SPI_SMEM_CS_HOLD_DELAY_S) #define SPI_SMEM_CS_HOLD_DELAY_V 0x0000003FU #define SPI_SMEM_CS_HOLD_DELAY_S 25 -/** SPI_SMEM_SPLIT_TRANS_EN : HRO; bitpos: [31]; default: 0; +/** SPI_SMEM_SPLIT_TRANS_EN : R/W; bitpos: [31]; default: 0; * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter * whether there is an ECC region or not. @@ -3098,14 +3257,14 @@ extern "C" { #define SPI_MMU_PAGE_SIZE_M (SPI_MMU_PAGE_SIZE_V << SPI_MMU_PAGE_SIZE_S) #define SPI_MMU_PAGE_SIZE_V 0x00000003U #define SPI_MMU_PAGE_SIZE_S 3 -/** SPI_MEM_AUX_CTRL : HRO; bitpos: [29:16]; default: 4896; +/** SPI_MEM_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896; * MMU PSRAM aux control register */ #define SPI_MEM_AUX_CTRL 0x00003FFFU #define SPI_MEM_AUX_CTRL_M (SPI_MEM_AUX_CTRL_V << SPI_MEM_AUX_CTRL_S) #define SPI_MEM_AUX_CTRL_V 0x00003FFFU #define SPI_MEM_AUX_CTRL_S 16 -/** SPI_MEM_RDN_ENA : HRO; bitpos: [30]; default: 0; +/** SPI_MEM_RDN_ENA : R/W; bitpos: [30]; default: 0; * ECO register enable bit * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -3166,21 +3325,28 @@ extern "C" { #define SPI_MEM_MODE_PSEUDO_M (SPI_MEM_MODE_PSEUDO_V << SPI_MEM_MODE_PSEUDO_S) #define SPI_MEM_MODE_PSEUDO_V 0x00000003U #define SPI_MEM_MODE_PSEUDO_S 0 -/** SPI_MEM_PSEUDO_BASE : R/W; bitpos: [5:2]; default: 2; +/** SPI_MEM_PSEUDO_RNG_CNT : R/W; bitpos: [4:2]; default: 7; + * xts aes peseudo function base round that must be performed. + */ +#define SPI_MEM_PSEUDO_RNG_CNT 0x00000007U +#define SPI_MEM_PSEUDO_RNG_CNT_M (SPI_MEM_PSEUDO_RNG_CNT_V << SPI_MEM_PSEUDO_RNG_CNT_S) +#define SPI_MEM_PSEUDO_RNG_CNT_V 0x00000007U +#define SPI_MEM_PSEUDO_RNG_CNT_S 2 +/** SPI_MEM_PSEUDO_BASE : R/W; bitpos: [8:5]; default: 2; * xts aes peseudo function base round that must be performed. */ #define SPI_MEM_PSEUDO_BASE 0x0000000FU #define SPI_MEM_PSEUDO_BASE_M (SPI_MEM_PSEUDO_BASE_V << SPI_MEM_PSEUDO_BASE_S) #define SPI_MEM_PSEUDO_BASE_V 0x0000000FU -#define SPI_MEM_PSEUDO_BASE_S 2 -/** SPI_MEM_PSEUDO_INC : R/W; bitpos: [7:6]; default: 2; +#define SPI_MEM_PSEUDO_BASE_S 5 +/** SPI_MEM_PSEUDO_INC : R/W; bitpos: [10:9]; default: 2; * xts aes peseudo function increment round that will be performed randomly between 0 & * 2**(inc+1). */ #define SPI_MEM_PSEUDO_INC 0x00000003U #define SPI_MEM_PSEUDO_INC_M (SPI_MEM_PSEUDO_INC_V << SPI_MEM_PSEUDO_INC_S) #define SPI_MEM_PSEUDO_INC_V 0x00000003U -#define SPI_MEM_PSEUDO_INC_S 6 +#define SPI_MEM_PSEUDO_INC_S 9 /** SPI_MEM_REGISTERRND_ECO_HIGH_REG register * MSPI ECO high register @@ -3188,7 +3354,7 @@ extern "C" { * applications. */ #define SPI_MEM_REGISTERRND_ECO_HIGH_REG(i) (REG_SPI_MEM_BASE(i) + 0x3f0) -/** SPI_MEM_REGISTERRND_ECO_HIGH : RO; bitpos: [31:0]; default: 892; +/** SPI_MEM_REGISTERRND_ECO_HIGH : R/W; bitpos: [31:0]; default: 892; * ECO high register * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -3203,7 +3369,7 @@ extern "C" { * applications. */ #define SPI_MEM_REGISTERRND_ECO_LOW_REG(i) (REG_SPI_MEM_BASE(i) + 0x3f4) -/** SPI_MEM_REGISTERRND_ECO_LOW : RO; bitpos: [31:0]; default: 892; +/** SPI_MEM_REGISTERRND_ECO_LOW : R/W; bitpos: [31:0]; default: 892; * ECO low register * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -3216,7 +3382,7 @@ extern "C" { * SPI0 version control register */ #define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3fc) -/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 36770128; +/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37823232; * SPI0 register version. */ #define SPI_MEM_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c61/register/soc/spi_mem_c_struct.h b/components/soc/esp32c61/register/soc/spi_mem_c_struct.h index 8fef2bcb1c..7231833aef 100644 --- a/components/soc/esp32c61/register/soc/spi_mem_c_struct.h +++ b/components/soc/esp32c61/register/soc/spi_mem_c_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,7 +30,7 @@ typedef union { uint32_t mem_slv_st:4; uint32_t reserved_8:10; /** mem_usr : HRO; bitpos: [18]; default: 0; - * SPI0 USR_CMD start bit, only used when spi_mem_c_AXI_REQ_EN is cleared. An operation + * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation * will be triggered when the bit is set. The bit will be cleared once the operation * done.1: enable 0: disable. */ @@ -45,13 +45,13 @@ typedef union { */ typedef union { struct { - /** mem_axi_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0; + /** mem_axi_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0; * This bits show the first AXI write/read invalid error or AXI write flash error - * address. It is cleared by when spi_mem_c_AXI_WADDR_ERR_INT_CLR, - * spi_mem_c_AXI_WR_FLASH_ERR_IN_CLR or spi_mem_c_AXI_RADDR_ERR_IN_CLR bit is set. + * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, + * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */ - uint32_t mem_axi_err_addr:27; - uint32_t reserved_27:5; + uint32_t mem_axi_err_addr:29; + uint32_t reserved_29:3; }; uint32_t val; } spi_mem_c_axi_err_addr_reg_t; @@ -63,7 +63,7 @@ typedef union { */ typedef union { struct { - /** mem_wdummy_dqs_always_out : HRO; bitpos: [0]; default: 0; + /** mem_wdummy_dqs_always_out : R/W; bitpos: [0]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to flash, the level * of SPI_DQS is output by the MSPI controller. */ @@ -85,15 +85,15 @@ typedef union { * pre-drive flash. */ uint32_t mem_fdummy_wout:1; - /** mem_fdout_oct : HRO; bitpos: [4]; default: 0; + /** mem_fdout_oct : R/W; bitpos: [4]; default: 0; * Apply 8 signals during write-data phase 1:enable 0: disable */ uint32_t mem_fdout_oct:1; - /** mem_fdin_oct : HRO; bitpos: [5]; default: 0; + /** mem_fdin_oct : R/W; bitpos: [5]; default: 0; * Apply 8 signals during read-data phase 1:enable 0: disable */ uint32_t mem_fdin_oct:1; - /** mem_faddr_oct : HRO; bitpos: [6]; default: 0; + /** mem_faddr_oct : R/W; bitpos: [6]; default: 0; * Apply 8 signals during address phase 1:enable 0: disable */ uint32_t mem_faddr_oct:1; @@ -102,14 +102,14 @@ typedef union { * Apply 4 signals during command phase 1:enable 0: disable */ uint32_t mem_fcmd_quad:1; - /** mem_fcmd_oct : HRO; bitpos: [9]; default: 0; + /** mem_fcmd_oct : R/W; bitpos: [9]; default: 0; * Apply 8 signals during command phase 1:enable 0: disable */ uint32_t mem_fcmd_oct:1; uint32_t reserved_10:3; /** mem_fastrd_mode : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: spi_mem_c_FREAD_QIO, spi_mem_c_FREAD_DIO, spi_mem_c_FREAD_QOUT - * and spi_mem_c_FREAD_DOUT. 1: enable 0: disable. + * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT + * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */ uint32_t mem_fastrd_mode:1; /** mem_fread_dual : R/W; bitpos: [14]; default: 0; @@ -145,7 +145,7 @@ typedef union { */ uint32_t mem_fread_qio:1; uint32_t reserved_25:5; - /** mem_dqs_ie_always_on : HRO; bitpos: [30]; default: 0; + /** mem_dqs_ie_always_on : R/W; bitpos: [30]; default: 0; * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always * 1. 0: Others. */ @@ -170,39 +170,34 @@ typedef union { * SPI clock is always on. */ uint32_t mem_clk_mode:2; - uint32_t reserved_2:19; - /** ar_size0_1_support_en : R/W; bitpos: [21]; default: 1; + uint32_t reserved_2:20; + /** ar_size0_1_support_en : R/W; bitpos: [22]; default: 1; * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. */ uint32_t ar_size0_1_support_en:1; - /** aw_size0_1_support_en : R/W; bitpos: [22]; default: 1; + /** aw_size0_1_support_en : R/W; bitpos: [23]; default: 1; * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. */ uint32_t aw_size0_1_support_en:1; - /** axi_rdata_back_fast : HRO; bitpos: [23]; default: 1; - * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: - * Reply AXI read data to AXI bus when all the read data is available. - */ - uint32_t axi_rdata_back_fast:1; /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * when there is a ECC error in AXI read data. The ECC error information is recorded - * in spi_mem_c_ECC_ERR_ADDR_REG. + * in SPI_MEM_ECC_ERR_ADDR_REG. */ uint32_t mem_rresp_ecc_err_en:1; - /** mem_ar_splice_en : HRO; bitpos: [25]; default: 0; + /** mem_ar_splice_en : R/W; bitpos: [25]; default: 0; * Set this bit to enable AXI Read Splice-transfer. */ uint32_t mem_ar_splice_en:1; - /** mem_aw_splice_en : HRO; bitpos: [26]; default: 0; + /** mem_aw_splice_en : R/W; bitpos: [26]; default: 0; * Set this bit to enable AXI Write Splice-transfer. */ uint32_t mem_aw_splice_en:1; /** mem_ram0_en : HRO; bitpos: [27]; default: 1; - * When spi_mem_c_DUAL_RAM_EN is 0 and spi_mem_c_RAM0_EN is 1, only EXT_RAM0 will be - * accessed. When spi_mem_c_DUAL_RAM_EN is 0 and spi_mem_c_RAM0_EN is 0, only EXT_RAM1 - * will be accessed. When spi_mem_c_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be * accessed at the same time. */ uint32_t mem_ram0_en:1; @@ -238,25 +233,25 @@ typedef union { struct { /** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1; * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with - * spi_mem_c_CS_SETUP bit. + * SPI_MEM_CS_SETUP bit. */ uint32_t mem_cs_setup_time:5; /** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1; * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with - * spi_mem_c_CS_HOLD bit. + * SPI_MEM_CS_HOLD bit. */ uint32_t mem_cs_hold_time:5; - /** mem_ecc_cs_hold_time : HRO; bitpos: [12:10]; default: 3; - * spi_mem_c_CS_HOLD_TIME + spi_mem_c_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + /** mem_ecc_cs_hold_time : R/W; bitpos: [12:10]; default: 3; + * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC * mode when accessed flash. */ uint32_t mem_ecc_cs_hold_time:3; - /** mem_ecc_skip_page_corner : HRO; bitpos: [13]; default: 1; + /** mem_ecc_skip_page_corner : R/W; bitpos: [13]; default: 1; * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when * accesses flash. */ uint32_t mem_ecc_skip_page_corner:1; - /** mem_ecc_16to18_byte_en : HRO; bitpos: [14]; default: 0; + /** mem_ecc_16to18_byte_en : R/W; bitpos: [14]; default: 0; * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when * accesses flash. */ @@ -270,7 +265,7 @@ typedef union { uint32_t mem_split_trans_en:1; /** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to flash. tSHSL is (spi_mem_c_CS_HOLD_DELAY[5:0] + 1) MSPI + * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI * core clock cycles. */ uint32_t mem_cs_hold_delay:6; @@ -331,42 +326,42 @@ typedef union { uint32_t mem_cache_flash_usr_cmd:1; /** mem_fdin_dual : R/W; bitpos: [3]; default: 0; * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_c_fread_dio. + * same with spi_mem_fread_dio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_fdin_dual:1; /** mem_fdout_dual : R/W; bitpos: [4]; default: 0; * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_c_fread_dio. + * same with spi_mem_fread_dio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_fdout_dual:1; /** mem_faddr_dual : R/W; bitpos: [5]; default: 0; * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_c_fread_dio. + * the same with spi_mem_fread_dio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_faddr_dual:1; /** mem_fdin_quad : R/W; bitpos: [6]; default: 0; * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_c_fread_qio. + * same with spi_mem_fread_qio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_fdin_quad:1; /** mem_fdout_quad : R/W; bitpos: [7]; default: 0; * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_c_fread_qio. + * same with spi_mem_fread_qio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_fdout_quad:1; /** mem_faddr_quad : R/W; bitpos: [8]; default: 0; * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_c_fread_qio. + * the same with spi_mem_fread_qio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_faddr_quad:1; uint32_t reserved_9:21; - /** same_aw_ar_addr_chk_en : HRO; bitpos: [30]; default: 1; + /** same_aw_ar_addr_chk_en : R/W; bitpos: [30]; default: 1; * Set this bit to check AXI read/write the same address region. */ uint32_t same_aw_ar_addr_chk_en:1; @@ -384,76 +379,76 @@ typedef union { */ typedef union { struct { - /** fmem_ddr_en : HRO; bitpos: [0]; default: 0; + /** fmem_ddr_en : R/W; bitpos: [0]; default: 0; * 1: in DDR mode, 0 in SDR mode */ uint32_t fmem_ddr_en:1; - /** fmem_var_dummy : HRO; bitpos: [1]; default: 0; + /** fmem_var_dummy : R/W; bitpos: [1]; default: 0; * Set the bit to enable variable dummy cycle in spi DDR mode. */ uint32_t fmem_var_dummy:1; - /** fmem_ddr_rdat_swp : HRO; bitpos: [2]; default: 0; + /** fmem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0; * Set the bit to reorder rx data of the word in spi DDR mode. */ uint32_t fmem_ddr_rdat_swp:1; - /** fmem_ddr_wdat_swp : HRO; bitpos: [3]; default: 0; + /** fmem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0; * Set the bit to reorder tx data of the word in spi DDR mode. */ uint32_t fmem_ddr_wdat_swp:1; - /** fmem_ddr_cmd_dis : HRO; bitpos: [4]; default: 0; + /** fmem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0; * the bit is used to disable dual edge in command phase when DDR mode. */ uint32_t fmem_ddr_cmd_dis:1; - /** fmem_outminbytelen : HRO; bitpos: [11:5]; default: 1; + /** fmem_outminbytelen : R/W; bitpos: [11:5]; default: 1; * It is the minimum output data length in the panda device. */ uint32_t fmem_outminbytelen:7; - /** fmem_tx_ddr_msk_en : HRO; bitpos: [12]; default: 1; + /** fmem_tx_ddr_msk_en : R/W; bitpos: [12]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when * accesses to flash. */ uint32_t fmem_tx_ddr_msk_en:1; - /** fmem_rx_ddr_msk_en : HRO; bitpos: [13]; default: 1; + /** fmem_rx_ddr_msk_en : R/W; bitpos: [13]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when * accesses to flash. */ uint32_t fmem_rx_ddr_msk_en:1; - /** fmem_usr_ddr_dqs_thd : HRO; bitpos: [20:14]; default: 0; + /** fmem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0; * The delay number of data strobe which from memory based on SPI clock. */ uint32_t fmem_usr_ddr_dqs_thd:7; - /** fmem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; + /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in spi_mem_c_DIN state. It is used when there is no SPI_DQS signal or + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ uint32_t fmem_ddr_dqs_loop:1; uint32_t reserved_22:2; - /** fmem_clk_diff_en : HRO; bitpos: [24]; default: 0; + /** fmem_clk_diff_en : R/W; bitpos: [24]; default: 0; * Set this bit to enable the differential SPI_CLK#. */ uint32_t fmem_clk_diff_en:1; uint32_t reserved_25:1; - /** fmem_dqs_ca_in : HRO; bitpos: [26]; default: 0; + /** fmem_dqs_ca_in : R/W; bitpos: [26]; default: 0; * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. */ uint32_t fmem_dqs_ca_in:1; - /** fmem_hyperbus_dummy_2x : HRO; bitpos: [27]; default: 0; + /** fmem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0; * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 * accesses flash or SPI1 accesses flash or sram. */ uint32_t fmem_hyperbus_dummy_2x:1; - /** fmem_clk_diff_inv : HRO; bitpos: [28]; default: 0; + /** fmem_clk_diff_inv : R/W; bitpos: [28]; default: 0; * Set this bit to invert SPI_DIFF when accesses to flash. . */ uint32_t fmem_clk_diff_inv:1; - /** fmem_octa_ram_addr : HRO; bitpos: [29]; default: 0; + /** fmem_octa_ram_addr : R/W; bitpos: [29]; default: 0; * Set this bit to enable octa_ram address out when accesses to flash, which means * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. */ uint32_t fmem_octa_ram_addr:1; - /** fmem_hyperbus_ca : HRO; bitpos: [30]; default: 0; + /** fmem_hyperbus_ca : R/W; bitpos: [30]; default: 0; * Set this bit to enable HyperRAM address out when accesses to flash, which means * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. */ @@ -471,16 +466,16 @@ typedef union { typedef union { struct { /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_c_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_CLKCNT_N. */ uint32_t mem_clkcnt_l:8; /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_c_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). */ uint32_t mem_clkcnt_h:8; /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi_mem_c_clk. So spi_mem_c_clk frequency is - * system/(spi_mem_c_clkcnt_N+1) + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(SPI_MEM_CLKCNT_N+1) */ uint32_t mem_clkcnt_n:8; uint32_t reserved_24:7; @@ -498,25 +493,25 @@ typedef union { */ typedef union { struct { - /** mem_sclkcnt_l : HRO; bitpos: [7:0]; default: 3; - * For SPI0 external RAM interface, it must be equal to spi_mem_c_clkcnt_N. + /** mem_sclkcnt_l : R/W; bitpos: [7:0]; default: 3; + * For SPI0 external RAM interface, it must be equal to SPI_MEM_SCLKCNT_N. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclkcnt_l:8; - /** mem_sclkcnt_h : HRO; bitpos: [15:8]; default: 1; - * For SPI0 external RAM interface, it must be floor((spi_mem_c_clkcnt_N+1)/2-1). + /** mem_sclkcnt_h : R/W; bitpos: [15:8]; default: 1; + * For SPI0 external RAM interface, it must be floor((SPI_MEM_SCLKCNT_N+1)/2-1). * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclkcnt_h:8; - /** mem_sclkcnt_n : HRO; bitpos: [23:16]; default: 3; - * For SPI0 external RAM interface, it is the divider of spi_mem_c_clk. So spi_mem_c_clk - * frequency is system/(spi_mem_c_clkcnt_N+1) + /** mem_sclkcnt_n : R/W; bitpos: [23:16]; default: 3; + * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk + * frequency is system/(SPI_MEM_SCLKCNT_N+1) * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclkcnt_n:8; uint32_t reserved_24:7; - /** mem_sclk_equ_sysclk : HRO; bitpos: [31]; default: 0; - * For SPI0 external RAM interface, 1: spi_mem_c_clk is equal to system 0: spi_mem_c_clk + /** mem_sclk_equ_sysclk : R/W; bitpos: [31]; default: 0; + * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk * is divided from system clock. * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -557,7 +552,7 @@ typedef union { uint32_t mem_cs_setup:1; uint32_t reserved_8:1; /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0; - * The bit combined with spi_mem_c_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. */ uint32_t mem_ck_out_edge:1; uint32_t reserved_10:16; @@ -581,15 +576,15 @@ typedef union { typedef union { struct { /** mem_usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; - * The length in spi_mem_c_clk cycles of dummy phase. The register value shall be + * The length in spi_mem_clk cycles of dummy phase. The register value shall be * (cycle_num-1). */ uint32_t mem_usr_dummy_cyclelen:6; - /** mem_usr_dbytelen : HRO; bitpos: [8:6]; default: 1; + /** mem_usr_dbytelen : HRO; bitpos: [11:6]; default: 1; * SPI0 USR_CMD read or write data byte length -1 */ - uint32_t mem_usr_dbytelen:3; - uint32_t reserved_9:17; + uint32_t mem_usr_dbytelen:6; + uint32_t reserved_12:14; /** mem_usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23; * The length in bits of address phase. The register value shall be (bit_num-1). */ @@ -623,11 +618,21 @@ typedef union { struct { uint32_t reserved_0:16; /** mem_wb_mode : R/W; bitpos: [23:16]; default: 0; - * Mode bits in the flash fast read mode it is combined with spi_mem_c_fastrd_mode bit. + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_wb_mode:8; - uint32_t reserved_24:8; + /** mem_wb_mode_bitlen : R/W; bitpos: [26:24]; default: 0; + * Mode bits length for flash fast read mode. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_wb_mode_bitlen:3; + /** mem_wb_mode_en : R/W; bitpos: [27]; default: 0; + * Mode bits is valid while this bit is enable. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_wb_mode_en:1; + uint32_t reserved_28:4; }; uint32_t val; } spi_mem_c_rd_status_reg_t; @@ -639,63 +644,63 @@ typedef union { */ typedef union { struct { - /** mem_cache_usr_saddr_4byte : HRO; bitpos: [0]; default: 0; + /** mem_cache_usr_saddr_4byte : R/W; bitpos: [0]; default: 0; * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: * enable, 0:disable. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_usr_saddr_4byte:1; - /** mem_usr_sram_dio : HRO; bitpos: [1]; default: 0; + /** mem_usr_sram_dio : R/W; bitpos: [1]; default: 0; * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_usr_sram_dio:1; - /** mem_usr_sram_qio : HRO; bitpos: [2]; default: 0; + /** mem_usr_sram_qio : R/W; bitpos: [2]; default: 0; * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_usr_sram_qio:1; - /** mem_usr_wr_sram_dummy : HRO; bitpos: [3]; default: 0; + /** mem_usr_wr_sram_dummy : R/W; bitpos: [3]; default: 0; * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write * operations. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_usr_wr_sram_dummy:1; - /** mem_usr_rd_sram_dummy : HRO; bitpos: [4]; default: 1; + /** mem_usr_rd_sram_dummy : R/W; bitpos: [4]; default: 1; * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read * operations. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_usr_rd_sram_dummy:1; - /** mem_cache_sram_usr_rcmd : HRO; bitpos: [5]; default: 1; + /** mem_cache_sram_usr_rcmd : R/W; bitpos: [5]; default: 1; * For SPI0, In the external RAM mode cache read external RAM for user define command. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_rcmd:1; - /** mem_sram_rdummy_cyclelen : HRO; bitpos: [11:6]; default: 1; + /** mem_sram_rdummy_cyclelen : R/W; bitpos: [11:6]; default: 1; * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. * The register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sram_rdummy_cyclelen:6; uint32_t reserved_12:2; - /** mem_sram_addr_bitlen : HRO; bitpos: [19:14]; default: 23; + /** mem_sram_addr_bitlen : R/W; bitpos: [19:14]; default: 23; * For SPI0, In the external RAM mode, it is the length in bits of address phase. The * register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sram_addr_bitlen:6; - /** mem_cache_sram_usr_wcmd : HRO; bitpos: [20]; default: 1; + /** mem_cache_sram_usr_wcmd : R/W; bitpos: [20]; default: 1; * For SPI0, In the external RAM mode cache write sram for user define command * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_wcmd:1; - /** mem_sram_oct : HRO; bitpos: [21]; default: 0; + /** mem_sram_oct : R/W; bitpos: [21]; default: 0; * reserved * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sram_oct:1; - /** mem_sram_wdummy_cyclelen : HRO; bitpos: [27:22]; default: 1; + /** mem_sram_wdummy_cyclelen : R/W; bitpos: [27:22]; default: 1; * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. * The register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. @@ -711,78 +716,78 @@ typedef union { */ typedef union { struct { - /** mem_sclk_mode : HRO; bitpos: [1:0]; default: 0; + /** mem_sclk_mode : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: * SPI clock is always on. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclk_mode:2; - /** mem_swb_mode : HRO; bitpos: [9:2]; default: 0; + /** mem_swb_mode : R/W; bitpos: [9:2]; default: 0; * Mode bits in the external RAM fast read mode it is combined with - * spi_mem_c_fastrd_mode bit. + * spi_mem_fastrd_mode bit. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_swb_mode:8; - /** mem_sdin_dual : HRO; bitpos: [10]; default: 0; + /** mem_sdin_dual : R/W; bitpos: [10]; default: 0; * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_c_usr_sram_dio. + * the same with spi_mem_usr_sram_dio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdin_dual:1; - /** mem_sdout_dual : HRO; bitpos: [11]; default: 0; + /** mem_sdout_dual : R/W; bitpos: [11]; default: 0; * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit - * is the same with spi_mem_c_usr_sram_dio. + * is the same with spi_mem_usr_sram_dio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdout_dual:1; - /** mem_saddr_dual : HRO; bitpos: [12]; default: 0; + /** mem_saddr_dual : R/W; bitpos: [12]; default: 0; * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The - * bit is the same with spi_mem_c_usr_sram_dio. + * bit is the same with spi_mem_usr_sram_dio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_saddr_dual:1; uint32_t reserved_13:1; - /** mem_sdin_quad : HRO; bitpos: [14]; default: 0; + /** mem_sdin_quad : R/W; bitpos: [14]; default: 0; * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_c_usr_sram_qio. + * the same with spi_mem_usr_sram_qio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdin_quad:1; - /** mem_sdout_quad : HRO; bitpos: [15]; default: 0; + /** mem_sdout_quad : R/W; bitpos: [15]; default: 0; * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit - * is the same with spi_mem_c_usr_sram_qio. + * is the same with spi_mem_usr_sram_qio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdout_quad:1; - /** mem_saddr_quad : HRO; bitpos: [16]; default: 0; + /** mem_saddr_quad : R/W; bitpos: [16]; default: 0; * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The - * bit is the same with spi_mem_c_usr_sram_qio. + * bit is the same with spi_mem_usr_sram_qio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_saddr_quad:1; - /** mem_scmd_quad : HRO; bitpos: [17]; default: 0; + /** mem_scmd_quad : R/W; bitpos: [17]; default: 0; * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_c_usr_sram_qio. + * the same with spi_mem_usr_sram_qio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_scmd_quad:1; - /** mem_sdin_oct : HRO; bitpos: [18]; default: 0; + /** mem_sdin_oct : R/W; bitpos: [18]; default: 0; * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdin_oct:1; - /** mem_sdout_oct : HRO; bitpos: [19]; default: 0; + /** mem_sdout_oct : R/W; bitpos: [19]; default: 0; * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdout_oct:1; - /** mem_saddr_oct : HRO; bitpos: [20]; default: 0; + /** mem_saddr_oct : R/W; bitpos: [20]; default: 0; * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_saddr_oct:1; - /** mem_scmd_oct : HRO; bitpos: [21]; default: 0; + /** mem_scmd_oct : R/W; bitpos: [21]; default: 0; * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -793,29 +798,39 @@ typedef union { * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdummy_rin:1; - /** mem_sdummy_wout : HRO; bitpos: [23]; default: 0; + /** mem_sdummy_wout : R/W; bitpos: [23]; default: 1; * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the * signal level of SPI bus is output by the MSPI controller. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdummy_wout:1; - /** smem_wdummy_dqs_always_out : HRO; bitpos: [24]; default: 0; + /** smem_wdummy_dqs_always_out : R/W; bitpos: [24]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, * the level of SPI_DQS is output by the MSPI controller. */ uint32_t smem_wdummy_dqs_always_out:1; - /** smem_wdummy_always_out : HRO; bitpos: [25]; default: 0; + /** smem_wdummy_always_out : R/W; bitpos: [25]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, * the level of SPI_IO[7:0] is output by the MSPI controller. */ uint32_t smem_wdummy_always_out:1; - uint32_t reserved_26:4; - /** smem_dqs_ie_always_on : HRO; bitpos: [30]; default: 1; + /** mem_sdin_hex : HRO; bitpos: [26]; default: 0; + * For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sdin_hex:1; + /** mem_sdout_hex : HRO; bitpos: [27]; default: 0; + * For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sdout_hex:1; + uint32_t reserved_28:2; + /** smem_dqs_ie_always_on : R/W; bitpos: [30]; default: 0; * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are * always 1. 0: Others. */ uint32_t smem_dqs_ie_always_on:1; - /** smem_data_ie_always_on : HRO; bitpos: [31]; default: 1; + /** smem_data_ie_always_on : R/W; bitpos: [31]; default: 1; * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] * are always 1. 0: Others. */ @@ -829,14 +844,14 @@ typedef union { */ typedef union { struct { - /** mem_cache_sram_usr_rd_cmd_value : HRO; bitpos: [15:0]; default: 0; + /** mem_cache_sram_usr_rd_cmd_value : R/W; bitpos: [15:0]; default: 0; * For SPI0,When cache mode is enable it is the read command value of command phase * for sram. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_rd_cmd_value:16; uint32_t reserved_16:12; - /** mem_cache_sram_usr_rd_cmd_bitlen : HRO; bitpos: [31:28]; default: 0; + /** mem_cache_sram_usr_rd_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; * For SPI0,When cache mode is enable it is the length in bits of command phase for * sram. The register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. @@ -851,14 +866,14 @@ typedef union { */ typedef union { struct { - /** mem_cache_sram_usr_wr_cmd_value : HRO; bitpos: [15:0]; default: 0; + /** mem_cache_sram_usr_wr_cmd_value : R/W; bitpos: [15:0]; default: 0; * For SPI0,When cache mode is enable it is the write command value of command phase * for sram. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_wr_cmd_value:16; uint32_t reserved_16:12; - /** mem_cache_sram_usr_wr_cmd_bitlen : HRO; bitpos: [31:28]; default: 0; + /** mem_cache_sram_usr_wr_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; * For SPI0,When cache mode is enable it is the in bits of command phase for sram. * The register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. @@ -873,77 +888,77 @@ typedef union { */ typedef union { struct { - /** smem_ddr_en : HRO; bitpos: [0]; default: 0; + /** smem_ddr_en : R/W; bitpos: [0]; default: 0; * 1: in DDR mode, 0 in SDR mode */ uint32_t smem_ddr_en:1; - /** smem_var_dummy : HRO; bitpos: [1]; default: 0; + /** smem_var_dummy : R/W; bitpos: [1]; default: 0; * Set the bit to enable variable dummy cycle in spi DDR mode. */ uint32_t smem_var_dummy:1; - /** smem_ddr_rdat_swp : HRO; bitpos: [2]; default: 0; + /** smem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0; * Set the bit to reorder rx data of the word in spi DDR mode. */ uint32_t smem_ddr_rdat_swp:1; - /** smem_ddr_wdat_swp : HRO; bitpos: [3]; default: 0; + /** smem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0; * Set the bit to reorder tx data of the word in spi DDR mode. */ uint32_t smem_ddr_wdat_swp:1; - /** smem_ddr_cmd_dis : HRO; bitpos: [4]; default: 0; + /** smem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0; * the bit is used to disable dual edge in command phase when DDR mode. */ uint32_t smem_ddr_cmd_dis:1; - /** smem_outminbytelen : HRO; bitpos: [11:5]; default: 1; + /** smem_outminbytelen : R/W; bitpos: [11:5]; default: 1; * It is the minimum output data length in the DDR psram. */ uint32_t smem_outminbytelen:7; - /** smem_tx_ddr_msk_en : HRO; bitpos: [12]; default: 1; + /** smem_tx_ddr_msk_en : R/W; bitpos: [12]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when * accesses to external RAM. */ uint32_t smem_tx_ddr_msk_en:1; - /** smem_rx_ddr_msk_en : HRO; bitpos: [13]; default: 1; + /** smem_rx_ddr_msk_en : R/W; bitpos: [13]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when * accesses to external RAM. */ uint32_t smem_rx_ddr_msk_en:1; - /** smem_usr_ddr_dqs_thd : HRO; bitpos: [20:14]; default: 0; + /** smem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0; * The delay number of data strobe which from memory based on SPI clock. */ uint32_t smem_usr_ddr_dqs_thd:7; - /** smem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; + /** smem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in spi_mem_c_DIN state. It is used when there is no SPI_DQS signal or + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ uint32_t smem_ddr_dqs_loop:1; uint32_t reserved_22:2; - /** smem_clk_diff_en : HRO; bitpos: [24]; default: 0; + /** smem_clk_diff_en : R/W; bitpos: [24]; default: 0; * Set this bit to enable the differential SPI_CLK#. */ uint32_t smem_clk_diff_en:1; uint32_t reserved_25:1; - /** smem_dqs_ca_in : HRO; bitpos: [26]; default: 0; + /** smem_dqs_ca_in : R/W; bitpos: [26]; default: 0; * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. */ uint32_t smem_dqs_ca_in:1; - /** smem_hyperbus_dummy_2x : HRO; bitpos: [27]; default: 0; + /** smem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0; * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 * accesses flash or SPI1 accesses flash or sram. */ uint32_t smem_hyperbus_dummy_2x:1; - /** smem_clk_diff_inv : HRO; bitpos: [28]; default: 0; + /** smem_clk_diff_inv : R/W; bitpos: [28]; default: 0; * Set this bit to invert SPI_DIFF when accesses to external RAM. . */ uint32_t smem_clk_diff_inv:1; - /** smem_octa_ram_addr : HRO; bitpos: [29]; default: 0; + /** smem_octa_ram_addr : R/W; bitpos: [29]; default: 0; * Set this bit to enable octa_ram address out when accesses to external RAM, which * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], * 1'b0}. */ uint32_t smem_octa_ram_addr:1; - /** smem_hyperbus_ca : HRO; bitpos: [30]; default: 0; + /** smem_hyperbus_ca : R/W; bitpos: [30]; default: 0; * Set this bit to enable HyperRAM address out when accesses to external RAM, which * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. */ @@ -951,55 +966,55 @@ typedef union { uint32_t reserved_31:1; }; uint32_t val; -} spi_smem_c_ddr_reg_t; +} spi_smem_ddr_reg_t; /** Type of smem_ac register * MSPI external RAM ECC and SPI CS timing control register */ typedef union { struct { - /** smem_cs_setup : HRO; bitpos: [0]; default: 0; + /** smem_cs_setup : R/W; bitpos: [0]; default: 0; * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: * disable. */ uint32_t smem_cs_setup:1; - /** smem_cs_hold : HRO; bitpos: [1]; default: 0; + /** smem_cs_hold : R/W; bitpos: [1]; default: 0; * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */ uint32_t smem_cs_hold:1; - /** smem_cs_setup_time : HRO; bitpos: [6:2]; default: 1; + /** smem_cs_setup_time : R/W; bitpos: [6:2]; default: 1; * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with - * spi_mem_c_cs_setup bit. + * spi_mem_cs_setup bit. */ uint32_t smem_cs_setup_time:5; - /** smem_cs_hold_time : HRO; bitpos: [11:7]; default: 1; + /** smem_cs_hold_time : R/W; bitpos: [11:7]; default: 1; * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are - * combined with spi_mem_c_cs_hold bit. + * combined with spi_mem_cs_hold bit. */ uint32_t smem_cs_hold_time:5; - /** smem_ecc_cs_hold_time : HRO; bitpos: [14:12]; default: 3; - * spi_smem_c_CS_HOLD_TIME + spi_smem_c_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold + /** smem_ecc_cs_hold_time : R/W; bitpos: [14:12]; default: 3; + * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold * cycles in ECC mode when accessed external RAM. */ uint32_t smem_ecc_cs_hold_time:3; - /** smem_ecc_skip_page_corner : HRO; bitpos: [15]; default: 1; + /** smem_ecc_skip_page_corner : R/W; bitpos: [15]; default: 1; * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when * accesses external RAM. */ uint32_t smem_ecc_skip_page_corner:1; - /** smem_ecc_16to18_byte_en : HRO; bitpos: [16]; default: 0; + /** smem_ecc_16to18_byte_en : R/W; bitpos: [16]; default: 0; * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when * accesses external RAM. */ uint32_t smem_ecc_16to18_byte_en:1; uint32_t reserved_17:8; - /** smem_cs_hold_delay : HRO; bitpos: [30:25]; default: 0; + /** smem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (spi_smem_c_CS_HOLD_DELAY[5:0] + 1) + * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) * MSPI core clock cycles. */ uint32_t smem_cs_hold_delay:6; - /** smem_split_trans_en : HRO; bitpos: [31]; default: 0; + /** smem_split_trans_en : R/W; bitpos: [31]; default: 0; * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter * whether there is an ECC region or not. @@ -1007,7 +1022,7 @@ typedef union { uint32_t smem_split_trans_en:1; }; uint32_t val; -} spi_smem_c_ac_reg_t; +} spi_smem_ac_reg_t; /** Group: State control register */ @@ -1017,11 +1032,19 @@ typedef union { typedef union { struct { uint32_t reserved_0:7; - /** mem_lock_delay_time : R/W; bitpos: [11:7]; default: 4; + /** mem_lock_delay_time : R/W; bitpos: [18:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ - uint32_t mem_lock_delay_time:5; - uint32_t reserved_12:20; + uint32_t mem_lock_delay_time:12; + /** mem_flash_lock_en : R/W; bitpos: [19]; default: 0; + * The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable. + */ + uint32_t mem_flash_lock_en:1; + /** mem_sram_lock_en : R/W; bitpos: [20]; default: 0; + * The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable. + */ + uint32_t mem_sram_lock_en:1; + uint32_t reserved_21:11; }; uint32_t val; } spi_mem_c_fsm_reg_t; @@ -1035,34 +1058,50 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; - * The enable bit for spi_mem_c_SLV_ST_END_INT interrupt. + * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. */ uint32_t mem_slv_st_end_int_ena:1; /** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; - * The enable bit for spi_mem_c_MST_ST_END_INT interrupt. + * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. */ uint32_t mem_mst_st_end_int_ena:1; - /** mem_ecc_err_int_ena : HRO; bitpos: [5]; default: 0; - * The enable bit for spi_mem_c_ECC_ERR_INT interrupt. + /** mem_ecc_err_int_ena : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. */ uint32_t mem_ecc_err_int_ena:1; /** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0; - * The enable bit for spi_mem_c_PMS_REJECT_INT interrupt. + * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. */ uint32_t mem_pms_reject_int_ena:1; /** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0; - * The enable bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. */ uint32_t mem_axi_raddr_err_int_ena:1; - /** mem_axi_wr_flash_err_int_ena : HRO; bitpos: [8]; default: 0; - * The enable bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt. + /** mem_axi_wr_flash_err_int_ena : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t mem_axi_wr_flash_err_int_ena:1; - /** mem_axi_waddr_err_int__ena : HRO; bitpos: [9]; default: 0; - * The enable bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt. + /** mem_axi_waddr_err_int__ena : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int__ena:1; - uint32_t reserved_10:22; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_ena : R/W; bitpos: [28]; default: 0; + * The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs0_afifo_ovf_int_ena:1; + /** mem_dqs1_afifo_ovf_int_ena : R/W; bitpos: [29]; default: 0; + * The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs1_afifo_ovf_int_ena:1; + /** mem_bus_fifo1_udf_int_ena : R/W; bitpos: [30]; default: 0; + * The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo1_udf_int_ena:1; + /** mem_bus_fifo0_udf_int_ena : R/W; bitpos: [31]; default: 0; + * The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo0_udf_int_ena:1; }; uint32_t val; } spi_mem_c_int_ena_reg_t; @@ -1074,34 +1113,50 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0; - * The clear bit for spi_mem_c_SLV_ST_END_INT interrupt. + * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. */ uint32_t mem_slv_st_end_int_clr:1; /** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0; - * The clear bit for spi_mem_c_MST_ST_END_INT interrupt. + * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. */ uint32_t mem_mst_st_end_int_clr:1; - /** mem_ecc_err_int_clr : HRO; bitpos: [5]; default: 0; - * The clear bit for spi_mem_c_ECC_ERR_INT interrupt. + /** mem_ecc_err_int_clr : WT; bitpos: [5]; default: 0; + * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. */ uint32_t mem_ecc_err_int_clr:1; /** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0; - * The clear bit for spi_mem_c_PMS_REJECT_INT interrupt. + * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. */ uint32_t mem_pms_reject_int_clr:1; /** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0; - * The clear bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt. + * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. */ uint32_t mem_axi_raddr_err_int_clr:1; - /** mem_axi_wr_flash_err_int_clr : HRO; bitpos: [8]; default: 0; - * The clear bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt. + /** mem_axi_wr_flash_err_int_clr : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t mem_axi_wr_flash_err_int_clr:1; - /** mem_axi_waddr_err_int_clr : HRO; bitpos: [9]; default: 0; - * The clear bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt. + /** mem_axi_waddr_err_int_clr : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int_clr:1; - uint32_t reserved_10:22; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_clr : WT; bitpos: [28]; default: 0; + * The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs0_afifo_ovf_int_clr:1; + /** mem_dqs1_afifo_ovf_int_clr : WT; bitpos: [29]; default: 0; + * The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs1_afifo_ovf_int_clr:1; + /** mem_bus_fifo1_udf_int_clr : WT; bitpos: [30]; default: 0; + * The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo1_udf_int_clr:1; + /** mem_bus_fifo0_udf_int_clr : WT; bitpos: [31]; default: 0; + * The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo0_udf_int_clr:1; }; uint32_t val; } spi_mem_c_int_clr_reg_t; @@ -1113,50 +1168,70 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for spi_mem_c_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is + * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is * changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ uint32_t mem_slv_st_end_int_raw:1; /** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for spi_mem_c_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is + * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is * changed from non idle state to idle state. 0: Others. */ uint32_t mem_mst_st_end_int_raw:1; - /** mem_ecc_err_int_raw : HRO; bitpos: [5]; default: 0; - * The raw bit for spi_mem_c_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set - * and spi_smem_c_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times - * of SPI0/1 ECC read flash are equal or bigger than spi_mem_c_ECC_ERR_INT_NUM. When - * SPI_FMEM_ECC_ERR_INT_EN is cleared and spi_smem_c_ECC_ERR_INT_EN is set, this bit is + /** mem_ecc_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set + * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times + * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When + * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger - * than spi_mem_c_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and - * spi_smem_c_ECC_ERR_INT_EN are set, this bit is triggered when the total error times + * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and + * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times * of SPI0/1 ECC read external RAM and flash are equal or bigger than - * spi_mem_c_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and spi_smem_c_ECC_ERR_INT_EN + * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN * are cleared, this bit will not be triggered. */ uint32_t mem_ecc_err_int_raw:1; /** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for spi_mem_c_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is + * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is * rejected. 0: Others. */ uint32_t mem_pms_reject_int_raw:1; /** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read + * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read * address is invalid by compared to MMU configuration. 0: Others. */ uint32_t mem_axi_raddr_err_int_raw:1; - /** mem_axi_wr_flash_err_int_raw : HRO; bitpos: [8]; default: 0; - * The raw bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write + /** mem_axi_wr_flash_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write * flash request is received. 0: Others. */ uint32_t mem_axi_wr_flash_err_int_raw:1; - /** mem_axi_waddr_err_int_raw : HRO; bitpos: [9]; default: 0; - * The raw bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + /** mem_axi_waddr_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write * address is invalid by compared to MMU configuration. 0: Others. */ uint32_t mem_axi_waddr_err_int_raw:1; - uint32_t reserved_10:22; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS1 is overflow. + */ + uint32_t mem_dqs0_afifo_ovf_int_raw:1; + /** mem_dqs1_afifo_ovf_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS is overflow. + */ + uint32_t mem_dqs1_afifo_ovf_int_raw:1; + /** mem_bus_fifo1_udf_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is + * underflow. + */ + uint32_t mem_bus_fifo1_udf_int_raw:1; + /** mem_bus_fifo0_udf_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is + * underflow. + */ + uint32_t mem_bus_fifo0_udf_int_raw:1; }; uint32_t val; } spi_mem_c_int_raw_reg_t; @@ -1168,34 +1243,50 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0; - * The status bit for spi_mem_c_SLV_ST_END_INT interrupt. + * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. */ uint32_t mem_slv_st_end_int_st:1; /** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0; - * The status bit for spi_mem_c_MST_ST_END_INT interrupt. + * The status bit for SPI_MEM_MST_ST_END_INT interrupt. */ uint32_t mem_mst_st_end_int_st:1; - /** mem_ecc_err_int_st : HRO; bitpos: [5]; default: 0; - * The status bit for spi_mem_c_ECC_ERR_INT interrupt. + /** mem_ecc_err_int_st : RO; bitpos: [5]; default: 0; + * The status bit for SPI_MEM_ECC_ERR_INT interrupt. */ uint32_t mem_ecc_err_int_st:1; /** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0; - * The status bit for spi_mem_c_PMS_REJECT_INT interrupt. + * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. */ uint32_t mem_pms_reject_int_st:1; /** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0; - * The enable bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. */ uint32_t mem_axi_raddr_err_int_st:1; - /** mem_axi_wr_flash_err_int_st : HRO; bitpos: [8]; default: 0; - * The enable bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt. + /** mem_axi_wr_flash_err_int_st : RO; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t mem_axi_wr_flash_err_int_st:1; - /** mem_axi_waddr_err_int_st : HRO; bitpos: [9]; default: 0; - * The enable bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt. + /** mem_axi_waddr_err_int_st : RO; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int_st:1; - uint32_t reserved_10:22; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_st : RO; bitpos: [28]; default: 0; + * The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs0_afifo_ovf_int_st:1; + /** mem_dqs1_afifo_ovf_int_st : RO; bitpos: [29]; default: 0; + * The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs1_afifo_ovf_int_st:1; + /** mem_bus_fifo1_udf_int_st : RO; bitpos: [30]; default: 0; + * The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo1_udf_int_st:1; + /** mem_bus_fifo0_udf_int_st : RO; bitpos: [31]; default: 0; + * The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo0_udf_int_st:1; }; uint32_t val; } spi_mem_c_int_st_reg_t; @@ -1231,11 +1322,11 @@ typedef union { */ typedef union { struct { - /** fmem_pmsn_addr_s : R/W; bitpos: [26:0]; default: 0; + /** fmem_pmsn_addr_s : R/W; bitpos: [28:0]; default: 0; * SPI1 flash PMS section n start address value */ - uint32_t fmem_pmsn_addr_s:27; - uint32_t reserved_27:5; + uint32_t fmem_pmsn_addr_s:29; + uint32_t reserved_29:3; }; uint32_t val; } spi_fmem_pmsn_addr_reg_t; @@ -1245,12 +1336,12 @@ typedef union { */ typedef union { struct { - /** fmem_pmsn_size : R/W; bitpos: [14:0]; default: 4096; + /** fmem_pmsn_size : R/W; bitpos: [16:0]; default: 4096; * SPI1 flash PMS section n address region is (SPI_FMEM_PMSn_ADDR_S, * SPI_FMEM_PMSn_ADDR_S + SPI_FMEM_PMSn_SIZE) */ - uint32_t fmem_pmsn_size:15; - uint32_t reserved_15:17; + uint32_t fmem_pmsn_size:17; + uint32_t reserved_17:15; }; uint32_t val; } spi_fmem_pmsn_size_reg_t; @@ -1270,82 +1361,93 @@ typedef union { uint32_t smem_pmsn_wr_attr:1; /** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0; * SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section n is configured by registers spi_smem_c_PMSn_ADDR_REG and - * spi_smem_c_PMSn_SIZE_REG. + * external RAM PMS section n is configured by registers SPI_SMEM_PMSn_ADDR_REG and + * SPI_SMEM_PMSn_SIZE_REG. */ uint32_t smem_pmsn_ecc:1; uint32_t reserved_3:29; }; uint32_t val; -} spi_smem_c_pmsn_attr_reg_t; +} spi_smem_pmsn_attr_reg_t; /** Type of smem_pmsn_addr register * SPI1 external RAM PMS section n start address register */ typedef union { struct { - /** smem_pmsn_addr_s : R/W; bitpos: [26:0]; default: 0; + /** smem_pmsn_addr_s : R/W; bitpos: [28:0]; default: 0; * SPI1 external RAM PMS section n start address value */ - uint32_t smem_pmsn_addr_s:27; - uint32_t reserved_27:5; + uint32_t smem_pmsn_addr_s:29; + uint32_t reserved_29:3; }; uint32_t val; -} spi_smem_c_pmsn_addr_reg_t; +} spi_smem_pmsn_addr_reg_t; /** Type of smem_pmsn_size register * SPI1 external RAM PMS section n start address register */ typedef union { struct { - /** smem_pmsn_size : R/W; bitpos: [14:0]; default: 4096; - * SPI1 external RAM PMS section n address region is (spi_smem_c_PMSn_ADDR_S, - * spi_smem_c_PMSn_ADDR_S + spi_smem_c_PMSn_SIZE) + /** smem_pmsn_size : R/W; bitpos: [16:0]; default: 4096; + * SPI1 external RAM PMS section n address region is (SPI_SMEM_PMSn_ADDR_S, + * SPI_SMEM_PMSn_ADDR_S + SPI_SMEM_PMSn_SIZE) */ - uint32_t smem_pmsn_size:15; - uint32_t reserved_15:17; + uint32_t smem_pmsn_size:17; + uint32_t reserved_17:15; }; uint32_t val; -} spi_smem_c_pmsn_size_reg_t; +} spi_smem_pmsn_size_reg_t; /** Type of mem_pms_reject register * SPI1 access reject register */ typedef union { struct { - /** mem_reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0; - * This bits show the first SPI1 access error address. It is cleared by when - * spi_mem_c_PMS_REJECT_INT_CLR bit is set. - */ - uint32_t mem_reject_addr:27; + uint32_t reserved_0:27; /** mem_pm_en : R/W; bitpos: [27]; default: 0; * Set this bit to enable SPI0/1 transfer permission control function. */ uint32_t mem_pm_en:1; /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0; * 1: SPI1 write access error. 0: No write access error. It is cleared by when - * spi_mem_c_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_ld:1; /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0; * 1: SPI1 read access error. 0: No read access error. It is cleared by when - * spi_mem_c_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_st:1; /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is - * cleared by when spi_mem_c_PMS_REJECT_INT_CLR bit is set. + * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_multi_hit:1; /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit - * error. It is cleared by when spi_mem_c_PMS_REJECT_INT_CLR bit is set. + * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_ivd:1; }; uint32_t val; } spi_mem_c_pms_reject_reg_t; +/** Type of mem_pms_reject_addr register + * SPI1 access reject addr register + */ +typedef union { + struct { + /** mem_reject_addr : R/SS/WTC; bitpos: [28:0]; default: 0; + * This bits show the first SPI1 access error address. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_reject_addr:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} spi_mem_c_pms_reject_addr_reg_t; + /** Group: MSPI ECC registers */ /** Type of mem_ecc_ctrl register @@ -1354,16 +1456,16 @@ typedef union { typedef union { struct { uint32_t reserved_0:5; - /** mem_ecc_err_cnt : HRO; bitpos: [10:5]; default: 0; + /** mem_ecc_err_cnt : R/SS/WTC; bitpos: [10:5]; default: 0; * This bits show the error times of MSPI ECC read. It is cleared by when - * spi_mem_c_ECC_ERR_INT_CLR bit is set. + * SPI_MEM_ECC_ERR_INT_CLR bit is set. */ uint32_t mem_ecc_err_cnt:6; - /** fmem_ecc_err_int_num : HRO; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI spi_mem_c_ECC_ERR_INT interrupt. + /** fmem_ecc_err_int_num : R/W; bitpos: [16:11]; default: 10; + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. */ uint32_t fmem_ecc_err_int_num:6; - /** fmem_ecc_err_int_en : HRO; bitpos: [17]; default: 0; + /** fmem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. */ uint32_t fmem_ecc_err_int_en:1; @@ -1372,24 +1474,25 @@ typedef union { * 1024 bytes. 3: 2048 bytes. */ uint32_t fmem_page_size:2; - /** fmem_ecc_addr_en : HRO; bitpos: [20]; default: 0; + uint32_t reserved_20:1; + /** fmem_ecc_addr_en : R/W; bitpos: [21]; default: 0; * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit * should be 0. Otherwise, this bit should be 1. */ uint32_t fmem_ecc_addr_en:1; - /** mem_usr_ecc_addr_en : HRO; bitpos: [21]; default: 0; + /** mem_usr_ecc_addr_en : R/W; bitpos: [22]; default: 0; * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. */ uint32_t mem_usr_ecc_addr_en:1; - uint32_t reserved_22:2; - /** mem_ecc_continue_record_err_en : HRO; bitpos: [24]; default: 1; - * 1: The error information in spi_mem_c_ECC_ERR_BITS and spi_mem_c_ECC_ERR_ADDR is - * updated when there is an ECC error. 0: spi_mem_c_ECC_ERR_BITS and - * spi_mem_c_ECC_ERR_ADDR record the first ECC error information. + uint32_t reserved_23:1; + /** mem_ecc_continue_record_err_en : R/W; bitpos: [24]; default: 1; + * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and + * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. */ uint32_t mem_ecc_continue_record_err_en:1; - /** mem_ecc_err_bits : HRO; bitpos: [31:25]; default: 0; + /** mem_ecc_err_bits : R/SS/WTC; bitpos: [31:25]; default: 0; * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to * byte 0 bit 0 to byte 15 bit 7) */ @@ -1403,12 +1506,12 @@ typedef union { */ typedef union { struct { - /** mem_ecc_err_addr : HRO; bitpos: [26:0]; default: 0; + /** mem_ecc_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0; * This bits show the first MSPI ECC error address. It is cleared by when - * spi_mem_c_ECC_ERR_INT_CLR bit is set. + * SPI_MEM_ECC_ERR_INT_CLR bit is set. */ - uint32_t mem_ecc_err_addr:27; - uint32_t reserved_27:5; + uint32_t mem_ecc_err_addr:29; + uint32_t reserved_29:3; }; uint32_t val; } spi_mem_c_ecc_err_addr_reg_t; @@ -1419,17 +1522,17 @@ typedef union { typedef union { struct { uint32_t reserved_0:17; - /** smem_ecc_err_int_en : HRO; bitpos: [17]; default: 0; + /** smem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; * Set this bit to calculate the error times of MSPI ECC read when accesses to * external RAM. */ uint32_t smem_ecc_err_int_en:1; - /** smem_page_size : HRO; bitpos: [19:18]; default: 2; + /** smem_page_size : R/W; bitpos: [19:18]; default: 2; * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. * 2: 1024 bytes. 3: 2048 bytes. */ uint32_t smem_page_size:2; - /** smem_ecc_addr_en : HRO; bitpos: [20]; default: 0; + /** smem_ecc_addr_en : R/W; bitpos: [20]; default: 0; * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the * ECC region or non-ECC region of external RAM. If there is no ECC region in external * RAM, this bit should be 0. Otherwise, this bit should be 1. @@ -1438,7 +1541,7 @@ typedef union { uint32_t reserved_21:11; }; uint32_t val; -} spi_smem_c_ecc_ctrl_reg_t; +} spi_smem_ecc_ctrl_reg_t; /** Group: Status and state control registers */ @@ -1476,38 +1579,38 @@ typedef union { uint32_t all_axi_trans_afifo_empty:1; }; uint32_t val; -} spi_smem_c_axi_addr_ctrl_reg_t; +} spi_smem_axi_addr_ctrl_reg_t; /** Type of mem_axi_err_resp_en register * SPI0 AXI error response enable register */ typedef union { struct { - /** mem_aw_resp_en_mmu_vld : HRO; bitpos: [0]; default: 0; + /** mem_aw_resp_en_mmu_vld : R/W; bitpos: [0]; default: 0; * Set this bit to enable AXI response function for mmu valid err in axi write trans. */ uint32_t mem_aw_resp_en_mmu_vld:1; - /** mem_aw_resp_en_mmu_gid : HRO; bitpos: [1]; default: 0; + /** mem_aw_resp_en_mmu_gid : R/W; bitpos: [1]; default: 0; * Set this bit to enable AXI response function for mmu gid err in axi write trans. */ uint32_t mem_aw_resp_en_mmu_gid:1; - /** mem_aw_resp_en_axi_size : HRO; bitpos: [2]; default: 0; + /** mem_aw_resp_en_axi_size : R/W; bitpos: [2]; default: 0; * Set this bit to enable AXI response function for axi size err in axi write trans. */ uint32_t mem_aw_resp_en_axi_size:1; - /** mem_aw_resp_en_axi_flash : HRO; bitpos: [3]; default: 0; + /** mem_aw_resp_en_axi_flash : R/W; bitpos: [3]; default: 0; * Set this bit to enable AXI response function for axi flash err in axi write trans. */ uint32_t mem_aw_resp_en_axi_flash:1; - /** mem_aw_resp_en_mmu_ecc : HRO; bitpos: [4]; default: 0; + /** mem_aw_resp_en_mmu_ecc : R/W; bitpos: [4]; default: 0; * Set this bit to enable AXI response function for mmu ecc err in axi write trans. */ uint32_t mem_aw_resp_en_mmu_ecc:1; - /** mem_aw_resp_en_mmu_sens : HRO; bitpos: [5]; default: 0; + /** mem_aw_resp_en_mmu_sens : R/W; bitpos: [5]; default: 0; * Set this bit to enable AXI response function for mmu sens in err axi write trans. */ uint32_t mem_aw_resp_en_mmu_sens:1; - /** mem_aw_resp_en_axi_wstrb : HRO; bitpos: [6]; default: 0; + /** mem_aw_resp_en_axi_wstrb : R/W; bitpos: [6]; default: 0; * Set this bit to enable AXI response function for axi wstrb err in axi write trans. */ uint32_t mem_aw_resp_en_axi_wstrb:1; @@ -1556,7 +1659,7 @@ typedef union { * add extra dummy spi clock cycle length for spi clock calibration. */ uint32_t mem_extra_dummy_cyclelen:3; - /** mem_dll_timing_cali : HRO; bitpos: [5]; default: 0; + /** mem_dll_timing_cali : R/W; bitpos: [5]; default: 0; * Set this bit to enable DLL for timing calibration in DDR mode when accessed to * flash. */ @@ -1768,91 +1871,102 @@ typedef union { */ typedef union { struct { - /** smem_timing_clk_ena : HRO; bitpos: [0]; default: 1; + /** smem_timing_clk_ena : R/W; bitpos: [0]; default: 1; * For sram, the bit is used to enable timing adjust clock for all reading operations. */ uint32_t smem_timing_clk_ena:1; - /** smem_timing_cali : HRO; bitpos: [1]; default: 0; + /** smem_timing_cali : R/W; bitpos: [1]; default: 0; * For sram, the bit is used to enable timing auto-calibration for all reading * operations. */ uint32_t smem_timing_cali:1; - /** smem_extra_dummy_cyclelen : HRO; bitpos: [4:2]; default: 0; + /** smem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; * For sram, add extra dummy spi clock cycle length for spi clock calibration. */ uint32_t smem_extra_dummy_cyclelen:3; - /** smem_dll_timing_cali : HRO; bitpos: [5]; default: 0; + /** smem_dll_timing_cali : R/W; bitpos: [5]; default: 0; * Set this bit to enable DLL for timing calibration in DDR mode when accessed to * EXT_RAM. */ uint32_t smem_dll_timing_cali:1; - uint32_t reserved_6:26; + uint32_t reserved_6:1; + /** smem_dqs0_270_sel : R/W; bitpos: [8:7]; default: 1; + * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. + * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. + */ + uint32_t smem_dqs0_270_sel:2; + /** smem_dqs0_90_sel : R/W; bitpos: [10:9]; default: 1; + * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, + * 2'd2: 1.5ns 2'd3: 2.0ns. + */ + uint32_t smem_dqs0_90_sel:2; + uint32_t reserved_11:21; }; uint32_t val; -} spi_smem_c_timing_cali_reg_t; +} spi_smem_timing_cali_reg_t; /** Type of smem_din_mode register * MSPI external RAM input timing delay mode control register */ typedef union { struct { - /** smem_din0_mode : HRO; bitpos: [2:0]; default: 0; + /** smem_din0_mode : R/W; bitpos: [2:0]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ uint32_t smem_din0_mode:3; - /** smem_din1_mode : HRO; bitpos: [5:3]; default: 0; + /** smem_din1_mode : R/W; bitpos: [5:3]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ uint32_t smem_din1_mode:3; - /** smem_din2_mode : HRO; bitpos: [8:6]; default: 0; + /** smem_din2_mode : R/W; bitpos: [8:6]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ uint32_t smem_din2_mode:3; - /** smem_din3_mode : HRO; bitpos: [11:9]; default: 0; + /** smem_din3_mode : R/W; bitpos: [11:9]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ uint32_t smem_din3_mode:3; - /** smem_din4_mode : HRO; bitpos: [14:12]; default: 0; + /** smem_din4_mode : R/W; bitpos: [14:12]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ uint32_t smem_din4_mode:3; - /** smem_din5_mode : HRO; bitpos: [17:15]; default: 0; + /** smem_din5_mode : R/W; bitpos: [17:15]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ uint32_t smem_din5_mode:3; - /** smem_din6_mode : HRO; bitpos: [20:18]; default: 0; + /** smem_din6_mode : R/W; bitpos: [20:18]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ uint32_t smem_din6_mode:3; - /** smem_din7_mode : HRO; bitpos: [23:21]; default: 0; + /** smem_din7_mode : R/W; bitpos: [23:21]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ uint32_t smem_din7_mode:3; - /** smem_dins_mode : HRO; bitpos: [26:24]; default: 0; + /** smem_dins_mode : R/W; bitpos: [26:24]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -1862,54 +1976,54 @@ typedef union { uint32_t reserved_27:5; }; uint32_t val; -} spi_smem_c_din_mode_reg_t; +} spi_smem_din_mode_reg_t; /** Type of smem_din_num register * MSPI external RAM input timing delay number control register */ typedef union { struct { - /** smem_din0_num : HRO; bitpos: [1:0]; default: 0; + /** smem_din0_num : R/W; bitpos: [1:0]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ uint32_t smem_din0_num:2; - /** smem_din1_num : HRO; bitpos: [3:2]; default: 0; + /** smem_din1_num : R/W; bitpos: [3:2]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ uint32_t smem_din1_num:2; - /** smem_din2_num : HRO; bitpos: [5:4]; default: 0; + /** smem_din2_num : R/W; bitpos: [5:4]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ uint32_t smem_din2_num:2; - /** smem_din3_num : HRO; bitpos: [7:6]; default: 0; + /** smem_din3_num : R/W; bitpos: [7:6]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ uint32_t smem_din3_num:2; - /** smem_din4_num : HRO; bitpos: [9:8]; default: 0; + /** smem_din4_num : R/W; bitpos: [9:8]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ uint32_t smem_din4_num:2; - /** smem_din5_num : HRO; bitpos: [11:10]; default: 0; + /** smem_din5_num : R/W; bitpos: [11:10]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ uint32_t smem_din5_num:2; - /** smem_din6_num : HRO; bitpos: [13:12]; default: 0; + /** smem_din6_num : R/W; bitpos: [13:12]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ uint32_t smem_din6_num:2; - /** smem_din7_num : HRO; bitpos: [15:14]; default: 0; + /** smem_din7_num : R/W; bitpos: [15:14]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ uint32_t smem_din7_num:2; - /** smem_dins_num : HRO; bitpos: [17:16]; default: 0; + /** smem_dins_num : R/W; bitpos: [17:16]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -1917,70 +2031,70 @@ typedef union { uint32_t reserved_18:14; }; uint32_t val; -} spi_smem_c_din_num_reg_t; +} spi_smem_din_num_reg_t; /** Type of smem_dout_mode register * MSPI external RAM output timing adjustment control register */ typedef union { struct { - /** smem_dout0_mode : HRO; bitpos: [0]; default: 0; + /** smem_dout0_mode : R/W; bitpos: [0]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ uint32_t smem_dout0_mode:1; - /** smem_dout1_mode : HRO; bitpos: [1]; default: 0; + /** smem_dout1_mode : R/W; bitpos: [1]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ uint32_t smem_dout1_mode:1; - /** smem_dout2_mode : HRO; bitpos: [2]; default: 0; + /** smem_dout2_mode : R/W; bitpos: [2]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ uint32_t smem_dout2_mode:1; - /** smem_dout3_mode : HRO; bitpos: [3]; default: 0; + /** smem_dout3_mode : R/W; bitpos: [3]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ uint32_t smem_dout3_mode:1; - /** smem_dout4_mode : HRO; bitpos: [4]; default: 0; + /** smem_dout4_mode : R/W; bitpos: [4]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ uint32_t smem_dout4_mode:1; - /** smem_dout5_mode : HRO; bitpos: [5]; default: 0; + /** smem_dout5_mode : R/W; bitpos: [5]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ uint32_t smem_dout5_mode:1; - /** smem_dout6_mode : HRO; bitpos: [6]; default: 0; + /** smem_dout6_mode : R/W; bitpos: [6]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ uint32_t smem_dout6_mode:1; - /** smem_dout7_mode : HRO; bitpos: [7]; default: 0; + /** smem_dout7_mode : R/W; bitpos: [7]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ uint32_t smem_dout7_mode:1; - /** smem_douts_mode : HRO; bitpos: [8]; default: 0; + /** smem_douts_mode : R/W; bitpos: [8]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -1990,8 +2104,7 @@ typedef union { uint32_t reserved_9:23; }; uint32_t val; -} spi_smem_c_dout_mode_reg_t; - +} spi_smem_dout_mode_reg_t; /** Group: Manual Encryption plaintext Memory */ /** Type of mem_xts_plain_base register @@ -2193,11 +2306,11 @@ typedef union { */ uint32_t mmu_page_size:2; uint32_t reserved_5:11; - /** mem_aux_ctrl : HRO; bitpos: [29:16]; default: 4896; + /** mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; * MMU PSRAM aux control register */ uint32_t mem_aux_ctrl:14; - /** mem_rdn_ena : HRO; bitpos: [30]; default: 0; + /** mem_rdn_ena : R/W; bitpos: [30]; default: 0; * ECO register enable bit * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -2253,16 +2366,20 @@ typedef union { * 2'b11: crypto with pseudo. */ uint32_t mem_mode_pseudo:2; - /** mem_pseudo_base : R/W; bitpos: [5:2]; default: 2; + /** mem_pseudo_rng_cnt : R/W; bitpos: [4:2]; default: 7; + * xts aes peseudo function base round that must be performed. + */ + uint32_t mem_pseudo_rng_cnt:3; + /** mem_pseudo_base : R/W; bitpos: [8:5]; default: 2; * xts aes peseudo function base round that must be performed. */ uint32_t mem_pseudo_base:4; - /** mem_pseudo_inc : R/W; bitpos: [7:6]; default: 2; + /** mem_pseudo_inc : R/W; bitpos: [10:9]; default: 2; * xts aes peseudo function increment round that will be performed randomly between 0 & * 2**(inc+1). */ uint32_t mem_pseudo_inc:2; - uint32_t reserved_8:24; + uint32_t reserved_11:21; }; uint32_t val; } spi_mem_c_xts_pseudo_round_conf_reg_t; @@ -2274,7 +2391,7 @@ typedef union { */ typedef union { struct { - /** mem_registerrnd_eco_high : RO; bitpos: [31:0]; default: 892; + /** mem_registerrnd_eco_high : R/W; bitpos: [31:0]; default: 892; * ECO high register * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -2288,7 +2405,7 @@ typedef union { */ typedef union { struct { - /** mem_registerrnd_eco_low : RO; bitpos: [31:0]; default: 892; + /** mem_registerrnd_eco_low : R/W; bitpos: [31:0]; default: 892; * ECO low register * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -2304,7 +2421,7 @@ typedef union { */ typedef union { struct { - /** mem_date : R/W; bitpos: [27:0]; default: 36770128; + /** mem_date : R/W; bitpos: [27:0]; default: 37823232; * SPI0 register version. */ uint32_t mem_date:28; @@ -2343,31 +2460,31 @@ typedef struct { volatile spi_mem_c_int_st_reg_t mem_int_st; uint32_t reserved_0d0; volatile spi_mem_c_ddr_reg_t mem_ddr; - volatile spi_smem_c_ddr_reg_t smem_ddr; + volatile spi_smem_ddr_reg_t smem_ddr; uint32_t reserved_0dc[9]; volatile spi_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4]; volatile spi_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4]; volatile spi_fmem_pmsn_size_reg_t fmem_pmsn_size[4]; - volatile spi_smem_c_pmsn_attr_reg_t smem_pmsn_attr[4]; - volatile spi_smem_c_pmsn_addr_reg_t smem_pmsn_addr[4]; - volatile spi_smem_c_pmsn_size_reg_t smem_pmsn_size[4]; - uint32_t reserved_160; + volatile spi_smem_pmsn_attr_reg_t smem_pmsn_attr[4]; + volatile spi_smem_pmsn_addr_reg_t smem_pmsn_addr[4]; + volatile spi_smem_pmsn_size_reg_t smem_pmsn_size[4]; volatile spi_mem_c_pms_reject_reg_t mem_pms_reject; + volatile spi_mem_c_pms_reject_addr_reg_t mem_pms_reject_addr; volatile spi_mem_c_ecc_ctrl_reg_t mem_ecc_ctrl; volatile spi_mem_c_ecc_err_addr_reg_t mem_ecc_err_addr; volatile spi_mem_c_axi_err_addr_reg_t mem_axi_err_addr; - volatile spi_smem_c_ecc_ctrl_reg_t smem_ecc_ctrl; - volatile spi_smem_c_axi_addr_ctrl_reg_t smem_axi_addr_ctrl; + volatile spi_smem_ecc_ctrl_reg_t smem_ecc_ctrl; + volatile spi_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl; volatile spi_mem_c_axi_err_resp_en_reg_t mem_axi_err_resp_en; volatile spi_mem_c_timing_cali_reg_t mem_timing_cali; volatile spi_mem_c_din_mode_reg_t mem_din_mode; volatile spi_mem_c_din_num_reg_t mem_din_num; volatile spi_mem_c_dout_mode_reg_t mem_dout_mode; - volatile spi_smem_c_timing_cali_reg_t smem_timing_cali; - volatile spi_smem_c_din_mode_reg_t smem_din_mode; - volatile spi_smem_c_din_num_reg_t smem_din_num; - volatile spi_smem_c_dout_mode_reg_t smem_dout_mode; - volatile spi_smem_c_ac_reg_t smem_ac; + volatile spi_smem_timing_cali_reg_t smem_timing_cali; + volatile spi_smem_din_mode_reg_t smem_din_mode; + volatile spi_smem_din_num_reg_t smem_din_num; + volatile spi_smem_dout_mode_reg_t smem_dout_mode; + volatile spi_smem_ac_reg_t smem_ac; uint32_t reserved_1a4[23]; volatile spi_mem_c_clock_gate_reg_t mem_clock_gate; uint32_t reserved_204[63]; diff --git a/components/soc/esp32c61/register/soc/spi_reg.h b/components/soc/esp32c61/register/soc/spi_reg.h index cce0834349..4ae39b0d7b 100644 --- a/components/soc/esp32c61/register/soc/spi_reg.h +++ b/components/soc/esp32c61/register/soc/spi_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,13 +11,15 @@ extern "C" { #endif +#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C61 + /** SPI_CMD_REG register * Command control register */ #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) /** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0; * Configures the SPI_CLK cycles of SPI CONF state. - * Measurement unit: SPI_CLK clock cycle.\\ + * Measurement unit: SPI_CLK clock cycle. * Can be configured in CONF state. */ #define SPI_CONF_BITLEN 0x0003FFFFU @@ -26,9 +28,9 @@ extern "C" { #define SPI_CONF_BITLEN_S 0 /** SPI_UPDATE : WT; bitpos: [23]; default: 0; * Configures whether or not to synchronize SPI registers from APB clock domain into - * SPI module clock domain. \\ - * 0: Not synchronize \\ - * 1: Synchronize \\ + * SPI module clock domain. + * 0: Not synchronize + * 1: Synchronize * This bit is only used in SPI master transfer. */ #define SPI_UPDATE (BIT(23)) @@ -36,9 +38,9 @@ extern "C" { #define SPI_UPDATE_V 0x00000001U #define SPI_UPDATE_S 23 /** SPI_USR : R/W/SC; bitpos: [24]; default: 0; - * Configures whether or not to enable user-defined command. \\ - * 0: Not enable \\ - * 1: Enable \\ + * Configures whether or not to enable user-defined command. + * 0: Not enable + * 1: Enable * An SPI operation will be triggered when the bit is set. This bit will be cleared * once the operation is done. Can not be changed by CONF_buf. */ @@ -65,9 +67,9 @@ extern "C" { */ #define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) /** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0; - * Configures whether or not to output the FSPI bus signals in DUMMY state. \\ - * 0: Not output \\ - * 1: Output \\ + * Configures whether or not to output the FSPI bus signals in DUMMY state. + * 0: Not output + * 1: Output * Can be configured in CONF state. */ #define SPI_DUMMY_OUT (BIT(3)) @@ -75,9 +77,9 @@ extern "C" { #define SPI_DUMMY_OUT_V 0x00000001U #define SPI_DUMMY_OUT_S 3 /** SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable 2-bit mode during address (ADDR) state.\\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 2-bit mode during address (ADDR) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FADDR_DUAL (BIT(5)) @@ -85,9 +87,9 @@ extern "C" { #define SPI_FADDR_DUAL_V 0x00000001U #define SPI_FADDR_DUAL_S 5 /** SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable 4-bit mode during address (ADDR) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 4-bit mode during address (ADDR) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FADDR_QUAD (BIT(6)) @@ -95,9 +97,9 @@ extern "C" { #define SPI_FADDR_QUAD_V 0x00000001U #define SPI_FADDR_QUAD_S 6 /** SPI_FADDR_OCT : HRO; bitpos: [7]; default: 0; - * Configures whether or not to enable 8-bit mode during address (ADDR) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 8-bit mode during address (ADDR) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FADDR_OCT (BIT(7)) @@ -105,9 +107,9 @@ extern "C" { #define SPI_FADDR_OCT_V 0x00000001U #define SPI_FADDR_OCT_S 7 /** SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable 2-bit mode during command (CMD) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 2-bit mode during command (CMD) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FCMD_DUAL (BIT(8)) @@ -115,9 +117,9 @@ extern "C" { #define SPI_FCMD_DUAL_V 0x00000001U #define SPI_FCMD_DUAL_S 8 /** SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable 4-bit mode during command (CMD) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 4-bit mode during command (CMD) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FCMD_QUAD (BIT(9)) @@ -125,9 +127,9 @@ extern "C" { #define SPI_FCMD_QUAD_V 0x00000001U #define SPI_FCMD_QUAD_S 9 /** SPI_FCMD_OCT : HRO; bitpos: [10]; default: 0; - * Configures whether or not to enable 8-bit mode during command (CMD) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 8-bit mode during command (CMD) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FCMD_OCT (BIT(10)) @@ -136,9 +138,9 @@ extern "C" { #define SPI_FCMD_OCT_S 10 /** SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0; * Configures whether or not to enable the 2-bit mode of read-data (DIN) state in read - * operations. \\ - * 0: Disable \\ - * 1: Enable \\ + * operations. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FREAD_DUAL (BIT(14)) @@ -147,9 +149,9 @@ extern "C" { #define SPI_FREAD_DUAL_S 14 /** SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the 4-bit mode of read-data (DIN) state in read - * operations. \\ - * 0: Disable \\ - * 1: Enable \\ + * operations. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FREAD_QUAD (BIT(15)) @@ -158,9 +160,9 @@ extern "C" { #define SPI_FREAD_QUAD_S 15 /** SPI_FREAD_OCT : HRO; bitpos: [16]; default: 0; * Configures whether or not to enable the 8-bit mode of read-data (DIN) state in read - * operations. \\ - * 0: Disable \\ - * 1: Enable \\ + * operations. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FREAD_OCT (BIT(16)) @@ -168,9 +170,9 @@ extern "C" { #define SPI_FREAD_OCT_V 0x00000001U #define SPI_FREAD_OCT_S 16 /** SPI_Q_POL : R/W; bitpos: [18]; default: 1; - * Configures MISO line polarity. \\ - * 0: Low \\ - * 1: High \\ + * Configures MISO line polarity. + * 0: Low + * 1: High * Can be configured in CONF state. */ #define SPI_Q_POL (BIT(18)) @@ -178,9 +180,9 @@ extern "C" { #define SPI_Q_POL_V 0x00000001U #define SPI_Q_POL_S 18 /** SPI_D_POL : R/W; bitpos: [19]; default: 1; - * Configures MOSI line polarity. \\ - * 0: Low \\ - * 1: High \\ + * Configures MOSI line polarity. + * 0: Low + * 1: High * Can be configured in CONF state. */ #define SPI_D_POL (BIT(19)) @@ -188,9 +190,9 @@ extern "C" { #define SPI_D_POL_V 0x00000001U #define SPI_D_POL_S 19 /** SPI_HOLD_POL : R/W; bitpos: [20]; default: 1; - * Configures SPI_HOLD output value when SPI is in idle. \\ - * 0: Output low \\ - * 1: Output high \\ + * Configures SPI_HOLD output value when SPI is in idle. + * 0: Output low + * 1: Output high * Can be configured in CONF state. */ #define SPI_HOLD_POL (BIT(20)) @@ -198,9 +200,9 @@ extern "C" { #define SPI_HOLD_POL_V 0x00000001U #define SPI_HOLD_POL_S 20 /** SPI_WP_POL : R/W; bitpos: [21]; default: 1; - * Configures the output value of write-protect signal when SPI is in idle. \\ - * 0: Output low \\ - * 1: Output high \\ + * Configures the output value of write-protect signal when SPI is in idle. + * 0: Output low + * 1: Output high * Can be configured in CONF state. */ #define SPI_WP_POL (BIT(21)) @@ -208,9 +210,9 @@ extern "C" { #define SPI_WP_POL_V 0x00000001U #define SPI_WP_POL_S 21 /** SPI_RD_BIT_ORDER : R/W; bitpos: [24:23]; default: 0; - * Configures the bit order in read-data (MISO) state. \\ - * 0: MSB first \\ - * 1: LSB first \\ + * Configures the bit order in read-data (MISO) state. + * 0: MSB first + * 1: LSB first * Can be configured in CONF state. */ #define SPI_RD_BIT_ORDER 0x00000003U @@ -219,9 +221,9 @@ extern "C" { #define SPI_RD_BIT_ORDER_S 23 /** SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0; * Configures the bit order in command (CMD), address (ADDR), and write-data (MOSI) - * states. \\ - * 0: MSB first \\ - * 1: LSB first \\ + * states. + * 0: MSB first + * 1: LSB first * Can be configured in CONF state. */ #define SPI_WR_BIT_ORDER 0x00000003U @@ -245,7 +247,7 @@ extern "C" { * Configures the duty cycle of SPI_CLK (high level) in master transfer. * It's recommended to configure this value to floor((SPI_CLKCNT_N + 1)/2 - 1). * floor() here is to round a number down, e.g., floor(2.2) = 2. In slave mode, it - * must be 0. \\ + * must be 0. * Can be configured in CONF state. */ #define SPI_CLKCNT_H 0x0000003FU @@ -255,7 +257,7 @@ extern "C" { /** SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3; * Configures the divider of SPI_CLK in master transfer. * SPI_CLK frequency is $f_{\textrm{apb_clk}}$/(SPI_CLKDIV_PRE + 1)/(SPI_CLKCNT_N + - * 1). \\ + * 1). * Can be configured in CONF state. */ #define SPI_CLKCNT_N 0x0000003FU @@ -270,10 +272,21 @@ extern "C" { #define SPI_CLKDIV_PRE_M (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S) #define SPI_CLKDIV_PRE_V 0x0000000FU #define SPI_CLKDIV_PRE_S 18 +/** SPI_CLK_EDGE_SEL : R/W; bitpos: [30]; default: 0; + * Configures use standard clock sampling edge or delay the sampling edge by half a + * cycle in master transfer. + * 0: clock sampling edge is delayed by half a cycle. + * 1: clock sampling edge is standard. + * Can be configured in CONF state. + */ +#define SPI_CLK_EDGE_SEL (BIT(30)) +#define SPI_CLK_EDGE_SEL_M (SPI_CLK_EDGE_SEL_V << SPI_CLK_EDGE_SEL_S) +#define SPI_CLK_EDGE_SEL_V 0x00000001U +#define SPI_CLK_EDGE_SEL_S 30 /** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; - * Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer.\\ - * 0: SPI_CLK is divided from APB_CLK.\\ - * 1: SPI_CLK is equal to APB_CLK.\\ + * Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer. + * 0: SPI_CLK is divided from APB_CLK. + * 1: SPI_CLK is equal to APB_CLK. * Can be configured in CONF state. */ #define SPI_CLK_EQU_SYSCLK (BIT(31)) @@ -286,9 +299,9 @@ extern "C" { */ #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10) /** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable full-duplex communication. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable full-duplex communication. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_DOUTDIN (BIT(0)) @@ -296,9 +309,9 @@ extern "C" { #define SPI_DOUTDIN_V 0x00000001U #define SPI_DOUTDIN_S 0 /** SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0; - * Configures whether or not to enable QPI mode. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable QPI mode. + * 0: Disable + * 1: Enable * This configuration is applicable when the SPI controller works as master or slave. * Can be configured in CONF state. */ @@ -315,18 +328,18 @@ extern "C" { #define SPI_OPI_MODE_V 0x00000001U #define SPI_OPI_MODE_S 4 /** SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0; - * Configures whether or not to change the polarity of TSCK in slave transfer. \\ - * 0: TSCK = SPI_CK_I \\ - * 1: TSCK = !SPI_CK_I \\ + * Configures whether or not to change the polarity of TSCK in slave transfer. + * 0: TSCK = SPI_CK_I + * 1: TSCK = !SPI_CK_I */ #define SPI_TSCK_I_EDGE (BIT(5)) #define SPI_TSCK_I_EDGE_M (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S) #define SPI_TSCK_I_EDGE_V 0x00000001U #define SPI_TSCK_I_EDGE_S 5 /** SPI_CS_HOLD : R/W; bitpos: [6]; default: 1; - * Configures whether or not to keep SPI CS low when SPI is in DONE state. \\ - * 0: Not keep low \\ - * 1: Keep low \\ + * Configures whether or not to keep SPI CS low when SPI is in DONE state. + * 0: Not keep low + * 1: Keep low * Can be configured in CONF state. */ #define SPI_CS_HOLD (BIT(6)) @@ -334,9 +347,9 @@ extern "C" { #define SPI_CS_HOLD_V 0x00000001U #define SPI_CS_HOLD_S 6 /** SPI_CS_SETUP : R/W; bitpos: [7]; default: 1; - * Configures whether or not to enable SPI CS when SPI is in prepare (PREP) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable SPI CS when SPI is in prepare (PREP) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_CS_SETUP (BIT(7)) @@ -344,9 +357,9 @@ extern "C" { #define SPI_CS_SETUP_V 0x00000001U #define SPI_CS_SETUP_S 7 /** SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0; - * Configures whether or not to change the polarity of RSCK in slave transfer. \\ - * 0: RSCK = !SPI_CK_I \\ - * 1: RSCK = SPI_CK_I \\ + * Configures whether or not to change the polarity of RSCK in slave transfer. + * 0: RSCK = !SPI_CK_I + * 1: RSCK = SPI_CK_I */ #define SPI_RSCK_I_EDGE (BIT(8)) #define SPI_RSCK_I_EDGE_M (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S) @@ -354,8 +367,7 @@ extern "C" { #define SPI_RSCK_I_EDGE_S 8 /** SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; * Configures SPI clock mode together with SPI_CK_IDLE_EDGE. - * Can be configured in CONF state. For more information, see Section link. + * Can be configured in CONF state. For more information, see Section . */ #define SPI_CK_OUT_EDGE (BIT(9)) #define SPI_CK_OUT_EDGE_M (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S) @@ -363,9 +375,9 @@ extern "C" { #define SPI_CK_OUT_EDGE_S 9 /** SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0; * Configures whether or not to enable the 2-bit mode of read-data phase in write - * operations.\\ - * 0: Not enable \\ - * 1: Enable \\ + * operations. + * 0: Not enable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FWRITE_DUAL (BIT(12)) @@ -374,9 +386,9 @@ extern "C" { #define SPI_FWRITE_DUAL_S 12 /** SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0; * Configures whether or not to enable the 4-bit mode of read-data phase in write - * operations. \\ - * 0: Not enable \\ - * 1: Enable \\ + * operations. + * 0: Not enable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FWRITE_QUAD (BIT(13)) @@ -393,11 +405,11 @@ extern "C" { #define SPI_FWRITE_OCT_S 14 /** SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the CONF state for the next transaction - * (segment) in a configurable segmented transfer. \\ + * (segment) in a configurable segmented transfer. * 0: this transfer will end after the current transaction (segment) is finished. Or - * this is not a configurable segmented transfer. \\ + * this is not a configurable segmented transfer. * 1: this configurable segmented transfer will continue its next transaction - * (segment). \\ + * (segment). * Can be configured in CONF state. */ #define SPI_USR_CONF_NXT (BIT(15)) @@ -406,9 +418,9 @@ extern "C" { #define SPI_USR_CONF_NXT_S 15 /** SPI_SIO : R/W; bitpos: [17]; default: 0; * Configures whether or not to enable 3-line half-duplex communication, where MOSI - * and MISO signals share the same pin.\\ - * 0: Disable \\ - * 1: Enable \\ + * and MISO signals share the same pin. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_SIO (BIT(17)) @@ -417,9 +429,9 @@ extern "C" { #define SPI_SIO_S 17 /** SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0; * Configures whether or not to enable high part mode, i.e., only access to high part - * of the buffers: SPI_W8_REG ~ SPI_W15_REG in read-data phase. \\ - * 0: Disable \\ - * 1: Enable \\ + * of the buffers: SPI_W8_REG ~ SPI_W15_REG in read-data phase. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_MISO_HIGHPART (BIT(24)) @@ -428,9 +440,9 @@ extern "C" { #define SPI_USR_MISO_HIGHPART_S 24 /** SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0; * Configures whether or not to enable high part mode, i.e., only access to high part - * of the buffers: SPI_W8_REG ~ SPI_W15_REG in write-data phase. \\ - * 0: Disable \\ - * 1: Enable \\ + * of the buffers: SPI_W8_REG ~ SPI_W15_REG in write-data phase. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_MOSI_HIGHPART (BIT(25)) @@ -438,9 +450,9 @@ extern "C" { #define SPI_USR_MOSI_HIGHPART_V 0x00000001U #define SPI_USR_MOSI_HIGHPART_S 25 /** SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; - * Configures whether or not to disable SPI clock in DUMMY state. \\ - * 0: Not disable \\ - * 1: Disable \\ + * Configures whether or not to disable SPI clock in DUMMY state. + * 0: Not disable + * 1: Disable * Can be configured in CONF state. */ #define SPI_USR_DUMMY_IDLE (BIT(26)) @@ -448,9 +460,9 @@ extern "C" { #define SPI_USR_DUMMY_IDLE_V 0x00000001U #define SPI_USR_DUMMY_IDLE_S 26 /** SPI_USR_MOSI : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable the write-data (DOUT) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the write-data (DOUT) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_MOSI (BIT(27)) @@ -458,9 +470,9 @@ extern "C" { #define SPI_USR_MOSI_V 0x00000001U #define SPI_USR_MOSI_S 27 /** SPI_USR_MISO : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable the read-data (DIN) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the read-data (DIN) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_MISO (BIT(28)) @@ -468,9 +480,9 @@ extern "C" { #define SPI_USR_MISO_V 0x00000001U #define SPI_USR_MISO_S 28 /** SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable the DUMMY state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the DUMMY state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_DUMMY (BIT(29)) @@ -478,9 +490,9 @@ extern "C" { #define SPI_USR_DUMMY_V 0x00000001U #define SPI_USR_DUMMY_S 29 /** SPI_USR_ADDR : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable the address (ADDR) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the address (ADDR) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_ADDR (BIT(30)) @@ -488,9 +500,9 @@ extern "C" { #define SPI_USR_ADDR_V 0x00000001U #define SPI_USR_ADDR_S 30 /** SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1; - * Configures whether or not to enable the command (CMD) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the command (CMD) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_COMMAND (BIT(31)) @@ -504,7 +516,7 @@ extern "C" { #define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14) /** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7; * Configures the length of DUMMY state. - * Measurement unit: SPI_CLK clock cycles.\\ + * Measurement unit: SPI_CLK clock cycles. * This value is (the expected cycle number - 1). Can be configured in CONF state. */ #define SPI_USR_DUMMY_CYCLELEN 0x000000FFU @@ -513,9 +525,9 @@ extern "C" { #define SPI_USR_DUMMY_CYCLELEN_S 0 /** SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1; * Configures whether or not to end the SPI transfer when SPI RX AFIFO wfull error - * occurs in master full-/half-duplex transfers. \\ - * 0: Not end \\ - * 1: End \\ + * occurs in master full-/half-duplex transfers. + * 0: Not end + * 1: End */ #define SPI_MST_WFULL_ERR_END_EN (BIT(16)) #define SPI_MST_WFULL_ERR_END_EN_M (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S) @@ -523,7 +535,7 @@ extern "C" { #define SPI_MST_WFULL_ERR_END_EN_S 16 /** SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0; * Configures the length of prepare (PREP) state. - * Measurement unit: SPI_CLK clock cycles.\\ + * Measurement unit: SPI_CLK clock cycles. * This value is equal to the expected cycles - 1. This field is used together with * SPI_CS_SETUP. Can be configured in CONF state. */ @@ -533,7 +545,7 @@ extern "C" { #define SPI_CS_SETUP_TIME_S 17 /** SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1; * Configures the delay cycles of CS pin. - * Measurement unit: SPI_CLK clock cycles. \\ + * Measurement unit: SPI_CLK clock cycles. * This field is used together with SPI_CS_HOLD. Can be configured in CONF state. */ #define SPI_CS_HOLD_TIME 0x0000001FU @@ -563,9 +575,9 @@ extern "C" { #define SPI_USR_COMMAND_VALUE_S 0 /** SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1; * Configures whether or not to end the SPI transfer when SPI TX AFIFO read empty - * error occurs in master full-/half-duplex transfers. \\ - * 0: Not end \\ - * 1: End \\ + * error occurs in master full-/half-duplex transfers. + * 0: Not end + * 1: End */ #define SPI_MST_REMPTY_ERR_END_EN (BIT(27)) #define SPI_MST_REMPTY_ERR_END_EN_M (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S) @@ -600,9 +612,9 @@ extern "C" { */ #define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20) /** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ #define SPI_CS0_DIS (BIT(0)) @@ -610,9 +622,9 @@ extern "C" { #define SPI_CS0_DIS_V 0x00000001U #define SPI_CS0_DIS_S 0 /** SPI_CS1_DIS : R/W; bitpos: [1]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ #define SPI_CS1_DIS (BIT(1)) @@ -620,9 +632,9 @@ extern "C" { #define SPI_CS1_DIS_V 0x00000001U #define SPI_CS1_DIS_S 1 /** SPI_CS2_DIS : R/W; bitpos: [2]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ #define SPI_CS2_DIS (BIT(2)) @@ -630,9 +642,9 @@ extern "C" { #define SPI_CS2_DIS_V 0x00000001U #define SPI_CS2_DIS_S 2 /** SPI_CS3_DIS : R/W; bitpos: [3]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ #define SPI_CS3_DIS (BIT(3)) @@ -640,9 +652,9 @@ extern "C" { #define SPI_CS3_DIS_V 0x00000001U #define SPI_CS3_DIS_S 3 /** SPI_CS4_DIS : R/W; bitpos: [4]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ #define SPI_CS4_DIS (BIT(4)) @@ -650,9 +662,9 @@ extern "C" { #define SPI_CS4_DIS_V 0x00000001U #define SPI_CS4_DIS_S 4 /** SPI_CS5_DIS : R/W; bitpos: [5]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ #define SPI_CS5_DIS (BIT(5)) @@ -660,9 +672,9 @@ extern "C" { #define SPI_CS5_DIS_V 0x00000001U #define SPI_CS5_DIS_S 5 /** SPI_CK_DIS : R/W; bitpos: [6]; default: 0; - * Configures whether or not to disable SPI_CLK output.\\ - * 0: Enable\\ - * 1: Disable\\ + * Configures whether or not to disable SPI_CLK output. + * 0: Enable + * 1: Disable * Can be configured in CONF state. */ #define SPI_CK_DIS (BIT(6)) @@ -670,9 +682,9 @@ extern "C" { #define SPI_CK_DIS_V 0x00000001U #define SPI_CK_DIS_S 6 /** SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0; - * Configures the polarity of SPI_CS$n ($n = 0-5) line in master transfer.\\ - * 0: SPI_CS$n is low active.\\ - * 1: SPI_CS$n is high active.\\ + * Configures the polarity of SPI_CS$n ($n = 0-5) line in master transfer. + * 0: SPI_CS$n is low active. + * 1: SPI_CS$n is high active. * Can be configured in CONF state. */ #define SPI_MASTER_CS_POL 0x0000003FU @@ -715,9 +727,9 @@ extern "C" { #define SPI_CMD_DTR_EN_V 0x00000001U #define SPI_CMD_DTR_EN_S 19 /** SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0; - * Configures whether or not invert SPI slave input CS polarity.\\ - * 0: Not change\\ - * 1: Invert\\ + * Configures whether or not invert SPI slave input CS polarity. + * 0: Not change + * 1: Invert * Can be configured in CONF state. */ #define SPI_SLAVE_CS_POL (BIT(23)) @@ -732,9 +744,9 @@ extern "C" { #define SPI_DQS_IDLE_EDGE_V 0x00000001U #define SPI_DQS_IDLE_EDGE_S 24 /** SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0; - * Configures the level of SPI_CLK line when GP-SPI2 is in idle.\\ - * 0: Low\\ - * 1: High\\ + * Configures the level of SPI_CLK line when GP-SPI2 is in idle. + * 0: Low + * 1: High * Can be configured in CONF state. */ #define SPI_CK_IDLE_EDGE (BIT(29)) @@ -742,9 +754,9 @@ extern "C" { #define SPI_CK_IDLE_EDGE_V 0x00000001U #define SPI_CK_IDLE_EDGE_S 29 /** SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0; - * Configures whether or not to keep the SPI_CS line low.\\ - * 0: Not keep low\\ - * 1: Keep low\\ + * Configures whether or not to keep the SPI_CS line low. + * 0: Not keep low + * 1: Keep low * Can be configured in CONF state. */ #define SPI_CS_KEEP_ACTIVE (BIT(30)) @@ -765,13 +777,13 @@ extern "C" { */ #define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24) /** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures the input mode for FSPID signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN0_NUM + 1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPID signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN0_NUM + 1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. */ #define SPI_DIN0_MODE 0x00000003U @@ -779,13 +791,13 @@ extern "C" { #define SPI_DIN0_MODE_V 0x00000003U #define SPI_DIN0_MODE_S 0 /** SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0; - * Configures the input mode for FSPIQ signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN1_NUM+1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPIQ signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN1_NUM+1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. */ #define SPI_DIN1_MODE 0x00000003U @@ -793,13 +805,13 @@ extern "C" { #define SPI_DIN1_MODE_V 0x00000003U #define SPI_DIN1_MODE_S 2 /** SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0; - * Configures the input mode for FSPIWP signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN2_NUM + 1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPIWP signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN2_NUM + 1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. */ #define SPI_DIN2_MODE 0x00000003U @@ -807,13 +819,13 @@ extern "C" { #define SPI_DIN2_MODE_V 0x00000003U #define SPI_DIN2_MODE_S 4 /** SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0; - * Configures the input mode for FSPIHD signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN3_NUM + 1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPIHD signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN3_NUM + 1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. * */ @@ -859,9 +871,9 @@ extern "C" { #define SPI_DIN7_MODE_S 14 /** SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0; * Configures whether or not to enable HCLK (high-frequency clock) in SPI input timing - * module.\\ - * 0: Disable\\ - * 1: Enable\\ + * module. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_TIMING_HCLK_ACTIVE (BIT(16)) @@ -874,11 +886,11 @@ extern "C" { */ #define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x28) /** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; - * Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ #define SPI_DIN0_NUM 0x00000003U @@ -886,11 +898,11 @@ extern "C" { #define SPI_DIN0_NUM_V 0x00000003U #define SPI_DIN0_NUM_S 0 /** SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; - * Configures the delays to input signal FSPIQ based on the setting of SPI_DIN1_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPIQ based on the setting of SPI_DIN1_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ #define SPI_DIN1_NUM 0x00000003U @@ -898,12 +910,11 @@ extern "C" { #define SPI_DIN1_NUM_V 0x00000003U #define SPI_DIN1_NUM_S 2 /** SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; - * Configures the delays to input signal FSPIWP based on the setting of - * SPI_DIN2_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPIWP based on the setting of SPI_DIN2_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ #define SPI_DIN2_NUM 0x00000003U @@ -911,12 +922,11 @@ extern "C" { #define SPI_DIN2_NUM_V 0x00000003U #define SPI_DIN2_NUM_S 4 /** SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; - * Configures the delays to input signal FSPIHD based on the setting of - * SPI_DIN3_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPIHD based on the setting of SPI_DIN3_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ #define SPI_DIN3_NUM 0x00000003U @@ -961,9 +971,9 @@ extern "C" { */ #define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x2c) /** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0; - * Configures the output mode for FSPID signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPID signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ #define SPI_DOUT0_MODE (BIT(0)) @@ -971,9 +981,9 @@ extern "C" { #define SPI_DOUT0_MODE_V 0x00000001U #define SPI_DOUT0_MODE_S 0 /** SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0; - * Configures the output mode for FSPIQ signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPIQ signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ #define SPI_DOUT1_MODE (BIT(1)) @@ -981,9 +991,9 @@ extern "C" { #define SPI_DOUT1_MODE_V 0x00000001U #define SPI_DOUT1_MODE_S 1 /** SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0; - * Configures the output mode for FSPIWP signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPIWP signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ #define SPI_DOUT2_MODE (BIT(2)) @@ -991,9 +1001,9 @@ extern "C" { #define SPI_DOUT2_MODE_V 0x00000001U #define SPI_DOUT2_MODE_S 2 /** SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0; - * Configures the output mode for FSPIHD signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPIHD signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ #define SPI_DOUT3_MODE (BIT(3)) @@ -1051,18 +1061,18 @@ extern "C" { */ #define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x30) /** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1; - * Represents whether or not the DMA TX FIFO is ready for sending data.\\ - * 0: Ready\\ - * 1: Not ready\\ + * Represents whether or not the DMA TX FIFO is ready for sending data. + * 0: Ready + * 1: Not ready */ #define SPI_DMA_OUTFIFO_EMPTY (BIT(0)) #define SPI_DMA_OUTFIFO_EMPTY_M (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S) #define SPI_DMA_OUTFIFO_EMPTY_V 0x00000001U #define SPI_DMA_OUTFIFO_EMPTY_S 0 /** SPI_DMA_INFIFO_FULL : RO; bitpos: [1]; default: 1; - * Represents whether or not the DMA RX FIFO is ready for receiving data.\\ - * 0: Ready\\ - * 1: Not ready\\ + * Represents whether or not the DMA RX FIFO is ready for receiving data. + * 0: Ready + * 1: Not ready */ #define SPI_DMA_INFIFO_FULL (BIT(1)) #define SPI_DMA_INFIFO_FULL_M (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S) @@ -1070,9 +1080,9 @@ extern "C" { #define SPI_DMA_INFIFO_FULL_S 1 /** SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0; * Configures whether or not to enable DMA-controlled segmented transfer in slave - * half-duplex communication.\\ - * 0: Disable\\ - * 1: Enable\\ + * half-duplex communication. + * 0: Disable + * 1: Enable */ #define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18)) #define SPI_DMA_SLV_SEG_TRANS_EN_M (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S) @@ -1080,10 +1090,10 @@ extern "C" { #define SPI_DMA_SLV_SEG_TRANS_EN_S 18 /** SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0; * In slave segmented transfer, if the size of the DMA RX buffer is smaller than the - * size of the received data, \\1: the data in all the following Wr_DMA transactions - * will not be received\\ 0: the data in this Wr_DMA transaction will not be received, - * but in the following transactions,\\ - * + * size of the received data, + * 1: the data in all the following Wr_DMA transactions will not be received + * 0: the data in this Wr_DMA transaction will not be received, but in the following + * transactions, * - if the size of DMA RX buffer is not 0, the data in following Wr_DMA transactions * will be received. * - if the size of DMA RX buffer is 0, the data in following Wr_DMA transactions will @@ -1095,12 +1105,11 @@ extern "C" { #define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19 /** SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0; * In slave segmented transfer, if the size of the DMA TX buffer is smaller than the - * size of the transmitted data,\\ + * size of the transmitted data, * 1: the data in the following transactions will not be updated, i.e. the old data is - * transmitted repeatedly.\\ + * transmitted repeatedly. * 0: the data in this transaction will not be updated. But in the following - * transactions,\\ - * + * transactions, * - if new data is filled in DMA TX FIFO, new data will be transmitted. * - if no new data is filled in DMA TX FIFO, no new data will be transmitted. */ @@ -1120,29 +1129,27 @@ extern "C" { #define SPI_RX_EOF_EN_V 0x00000001U #define SPI_RX_EOF_EN_S 21 /** SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable DMA-controlled receive data transfer.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable DMA-controlled receive data transfer. + * 0: Disable + * 1: Enable */ #define SPI_DMA_RX_ENA (BIT(27)) #define SPI_DMA_RX_ENA_M (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S) #define SPI_DMA_RX_ENA_V 0x00000001U #define SPI_DMA_RX_ENA_S 27 /** SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable DMA-controlled send data transfer.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable DMA-controlled send data transfer. + * 0: Disable + * 1: Enable */ #define SPI_DMA_TX_ENA (BIT(28)) #define SPI_DMA_TX_ENA_M (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S) #define SPI_DMA_TX_ENA_V 0x00000001U #define SPI_DMA_TX_ENA_S 28 /** SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0; - * Configures whether or not to reset spi_rx_afifo as shown in Figure link and in Figure link.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset spi_rx_afifo as shown in Figure . + * 0: Not reset + * 1: Reset * spi_rx_afifo is used to receive data in SPI master and slave transfer. */ #define SPI_RX_AFIFO_RST (BIT(29)) @@ -1150,11 +1157,9 @@ extern "C" { #define SPI_RX_AFIFO_RST_V 0x00000001U #define SPI_RX_AFIFO_RST_S 29 /** SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0; - * Configures whether or not to reset buf_tx_afifo as shown in Figure link and in Figure link.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset buf_tx_afifo as shown in Figure . + * 0: Not reset + * 1: Reset * buf_tx_afifo is used to send data out in CPU-controlled master and slave transfer. */ #define SPI_BUF_AFIFO_RST (BIT(30)) @@ -1162,11 +1167,9 @@ extern "C" { #define SPI_BUF_AFIFO_RST_V 0x00000001U #define SPI_BUF_AFIFO_RST_S 30 /** SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0; - * Configures whether or not to reset dma_tx_afifo as shown in Figure link and in Figure link.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset dma_tx_afifo as shown in Figure . + * 0: Not reset + * 1: Reset * dma_tx_afifo is used to send data out in DMA-controlled slave transfer. */ #define SPI_DMA_AFIFO_RST (BIT(31)) @@ -2135,11 +2138,11 @@ extern "C" { */ #define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xe0) /** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures SPI clock mode.\\ - * 0: SPI clock is off when CS becomes inactive.\\ - * 1: SPI clock is delayed one cycle after CS becomes inactive.\\ - * 2: SPI clock is delayed two cycles after CS becomes inactive.\\ - * 3: SPI clock is always on.\\ + * Configures SPI clock mode. + * 0: SPI clock is off when CS becomes inactive. + * 1: SPI clock is delayed one cycle after CS becomes inactive. + * 2: SPI clock is delayed two cycles after CS becomes inactive. + * 3: SPI clock is always on. * Can be configured in CONF state. */ #define SPI_CLK_MODE 0x00000003U @@ -2147,20 +2150,18 @@ extern "C" { #define SPI_CLK_MODE_V 0x00000003U #define SPI_CLK_MODE_S 0 /** SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0; - * Configure clock mode.\\ - * 0: Support SPI clock mode 0 or 2. See Table link.\\ - * 1: Support SPI clock mode 1 or 3. See Table link.\\ + * Configure clock mode. + * 0: Support SPI clock mode 0 or 2. See Table . + * 1: Support SPI clock mode 1 or 3. See Table . */ #define SPI_CLK_MODE_13 (BIT(2)) #define SPI_CLK_MODE_13_M (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S) #define SPI_CLK_MODE_13_V 0x00000001U #define SPI_CLK_MODE_13_S 2 /** SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0; - * Configures the edge of output data.\\ - * 0: Output data at TSCK rising edge.\\ - * 1: Output data at RSCK rising edge.\\ + * Configures the edge of output data. + * 0: Output data at TSCK rising edge. + * 1: Output data at RSCK rising edge. */ #define SPI_RSCK_DATA_OUT (BIT(3)) #define SPI_RSCK_DATA_OUT_M (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S) @@ -2168,9 +2169,9 @@ extern "C" { #define SPI_RSCK_DATA_OUT_S 3 /** SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Rd_DMA transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Rd_DMA transfer. + * 0: Not use + * 1: Use */ #define SPI_SLV_RDDMA_BITLEN_EN (BIT(8)) #define SPI_SLV_RDDMA_BITLEN_EN_M (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S) @@ -2178,9 +2179,9 @@ extern "C" { #define SPI_SLV_RDDMA_BITLEN_EN_S 8 /** SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Wr_DMA transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Wr_DMA transfer. + * 0: Not use + * 1: Use */ #define SPI_SLV_WRDMA_BITLEN_EN (BIT(9)) #define SPI_SLV_WRDMA_BITLEN_EN_M (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S) @@ -2188,9 +2189,9 @@ extern "C" { #define SPI_SLV_WRDMA_BITLEN_EN_S 9 /** SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Rd_BUF transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Rd_BUF transfer. + * 0: Not use + * 1: Use */ #define SPI_SLV_RDBUF_BITLEN_EN (BIT(10)) #define SPI_SLV_RDBUF_BITLEN_EN_M (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S) @@ -2198,9 +2199,9 @@ extern "C" { #define SPI_SLV_RDBUF_BITLEN_EN_S 10 /** SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Wr_BUF transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Wr_BUF transfer. + * 0: Not use + * 1: Use */ #define SPI_SLV_WRBUF_BITLEN_EN (BIT(11)) #define SPI_SLV_WRBUF_BITLEN_EN_M (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S) @@ -2223,19 +2224,18 @@ extern "C" { #define SPI_DMA_SEG_MAGIC_VALUE_V 0x0000000FU #define SPI_DMA_SEG_MAGIC_VALUE_S 22 /** SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0; - * Configures SPI work mode.\\ - * 0: Master\\ - * 1: Slave\\ + * Configures SPI work mode. + * 0: Master + * 1: Slave */ #define SPI_SLAVE_MODE (BIT(26)) #define SPI_SLAVE_MODE_M (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S) #define SPI_SLAVE_MODE_V 0x00000001U #define SPI_SLAVE_MODE_S 26 /** SPI_SOFT_RESET : WT; bitpos: [27]; default: 0; - * Configures whether to reset the SPI clock line, CS line, and data line via - * software.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether to reset the SPI clock line, CS line, and data line via software. + * 0: Not reset + * 1: Reset * Can be configured in CONF state. */ #define SPI_SOFT_RESET (BIT(27)) @@ -2244,10 +2244,10 @@ extern "C" { #define SPI_SOFT_RESET_S 27 /** SPI_USR_CONF : R/W; bitpos: [28]; default: 0; * Configures whether or not to enable the CONF state of current DMA-controlled - * configurable segmented transfer.\\ + * configurable segmented transfer. * 0: No effect, which means the current transfer is not a configurable segmented - * transfer.\\ - * 1: Enable, which means a configurable segmented transfer is started.\\ + * transfer. + * 1: Enable, which means a configurable segmented transfer is started. */ #define SPI_USR_CONF (BIT(28)) #define SPI_USR_CONF_M (SPI_USR_CONF_V << SPI_USR_CONF_S) @@ -2255,9 +2255,9 @@ extern "C" { #define SPI_USR_CONF_S 28 /** SPI_MST_FD_WAIT_DMA_TX_DATA : R/W; bitpos: [29]; default: 0; * Configures whether or not to wait DMA TX data gets ready before starting SPI - * transfer in master full-duplex transfer.\\ - * 0: Not wait\\ - * 1: Wait\\ + * transfer in master full-duplex transfer. + * 0: Not wait + * 1: Wait */ #define SPI_MST_FD_WAIT_DMA_TX_DATA (BIT(29)) #define SPI_MST_FD_WAIT_DMA_TX_DATA_M (SPI_MST_FD_WAIT_DMA_TX_DATA_V << SPI_MST_FD_WAIT_DMA_TX_DATA_S) @@ -2295,9 +2295,9 @@ extern "C" { */ #define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xe8) /** SPI_CLK_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable clock gate.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable clock gate. + * 0: Disable + * 1: Enable */ #define SPI_CLK_EN (BIT(0)) #define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) @@ -2323,7 +2323,7 @@ extern "C" { * Version control */ #define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xf0) -/** SPI_DATE : R/W; bitpos: [27:0]; default: 36716931; +/** SPI_DATE : R/W; bitpos: [27:0]; default: 37761424; * Version control register. */ #define SPI_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c61/register/soc/spi_struct.h b/components/soc/esp32c61/register/soc/spi_struct.h index 88690647ed..5ea6f2956f 100644 --- a/components/soc/esp32c61/register/soc/spi_struct.h +++ b/components/soc/esp32c61/register/soc/spi_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -18,23 +18,23 @@ typedef union { struct { /** conf_bitlen : R/W; bitpos: [17:0]; default: 0; * Configures the SPI_CLK cycles of SPI CONF state. - * Measurement unit: SPI_CLK clock cycle.\\ + * Measurement unit: SPI_CLK clock cycle. * Can be configured in CONF state. */ uint32_t conf_bitlen:18; uint32_t reserved_18:5; /** update : WT; bitpos: [23]; default: 0; * Configures whether or not to synchronize SPI registers from APB clock domain into - * SPI module clock domain. \\ - * 0: Not synchronize \\ - * 1: Synchronize \\ + * SPI module clock domain. + * 0: Not synchronize + * 1: Synchronize * This bit is only used in SPI master transfer. */ uint32_t update:1; /** usr : R/W/SC; bitpos: [24]; default: 0; - * Configures whether or not to enable user-defined command. \\ - * 0: Not enable \\ - * 1: Enable \\ + * Configures whether or not to enable user-defined command. + * 0: Not enable + * 1: Enable * An SPI operation will be triggered when the bit is set. This bit will be cleared * once the operation is done. Can not be changed by CONF_buf. */ @@ -64,17 +64,17 @@ typedef union { typedef union { struct { /** doutdin : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable full-duplex communication. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable full-duplex communication. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t doutdin:1; uint32_t reserved_1:2; /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0; - * Configures whether or not to enable QPI mode. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable QPI mode. + * 0: Disable + * 1: Enable * This configuration is applicable when the SPI controller works as master or slave. * Can be configured in CONF state. */ @@ -85,51 +85,50 @@ typedef union { */ uint32_t opi_mode:1; /** tsck_i_edge : R/W; bitpos: [5]; default: 0; - * Configures whether or not to change the polarity of TSCK in slave transfer. \\ - * 0: TSCK = SPI_CK_I \\ - * 1: TSCK = !SPI_CK_I \\ + * Configures whether or not to change the polarity of TSCK in slave transfer. + * 0: TSCK = SPI_CK_I + * 1: TSCK = !SPI_CK_I */ uint32_t tsck_i_edge:1; /** cs_hold : R/W; bitpos: [6]; default: 1; - * Configures whether or not to keep SPI CS low when SPI is in DONE state. \\ - * 0: Not keep low \\ - * 1: Keep low \\ + * Configures whether or not to keep SPI CS low when SPI is in DONE state. + * 0: Not keep low + * 1: Keep low * Can be configured in CONF state. */ uint32_t cs_hold:1; /** cs_setup : R/W; bitpos: [7]; default: 1; - * Configures whether or not to enable SPI CS when SPI is in prepare (PREP) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable SPI CS when SPI is in prepare (PREP) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t cs_setup:1; /** rsck_i_edge : R/W; bitpos: [8]; default: 0; - * Configures whether or not to change the polarity of RSCK in slave transfer. \\ - * 0: RSCK = !SPI_CK_I \\ - * 1: RSCK = SPI_CK_I \\ + * Configures whether or not to change the polarity of RSCK in slave transfer. + * 0: RSCK = !SPI_CK_I + * 1: RSCK = SPI_CK_I */ uint32_t rsck_i_edge:1; /** ck_out_edge : R/W; bitpos: [9]; default: 0; * Configures SPI clock mode together with SPI_CK_IDLE_EDGE. - * Can be configured in CONF state. For more information, see Section link. + * Can be configured in CONF state. For more information, see Section . */ uint32_t ck_out_edge:1; uint32_t reserved_10:2; /** fwrite_dual : R/W; bitpos: [12]; default: 0; * Configures whether or not to enable the 2-bit mode of read-data phase in write - * operations.\\ - * 0: Not enable \\ - * 1: Enable \\ + * operations. + * 0: Not enable + * 1: Enable * Can be configured in CONF state. */ uint32_t fwrite_dual:1; /** fwrite_quad : R/W; bitpos: [13]; default: 0; * Configures whether or not to enable the 4-bit mode of read-data phase in write - * operations. \\ - * 0: Not enable \\ - * 1: Enable \\ + * operations. + * 0: Not enable + * 1: Enable * Can be configured in CONF state. */ uint32_t fwrite_quad:1; @@ -140,79 +139,79 @@ typedef union { uint32_t fwrite_oct:1; /** usr_conf_nxt : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the CONF state for the next transaction - * (segment) in a configurable segmented transfer. \\ + * (segment) in a configurable segmented transfer. * 0: this transfer will end after the current transaction (segment) is finished. Or - * this is not a configurable segmented transfer. \\ + * this is not a configurable segmented transfer. * 1: this configurable segmented transfer will continue its next transaction - * (segment). \\ + * (segment). * Can be configured in CONF state. */ uint32_t usr_conf_nxt:1; uint32_t reserved_16:1; /** sio : R/W; bitpos: [17]; default: 0; * Configures whether or not to enable 3-line half-duplex communication, where MOSI - * and MISO signals share the same pin.\\ - * 0: Disable \\ - * 1: Enable \\ + * and MISO signals share the same pin. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t sio:1; uint32_t reserved_18:6; /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; * Configures whether or not to enable high part mode, i.e., only access to high part - * of the buffers: SPI_W8_REG ~ SPI_W15_REG in read-data phase. \\ - * 0: Disable \\ - * 1: Enable \\ + * of the buffers: SPI_W8_REG ~ SPI_W15_REG in read-data phase. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_miso_highpart:1; /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; * Configures whether or not to enable high part mode, i.e., only access to high part - * of the buffers: SPI_W8_REG ~ SPI_W15_REG in write-data phase. \\ - * 0: Disable \\ - * 1: Enable \\ + * of the buffers: SPI_W8_REG ~ SPI_W15_REG in write-data phase. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_mosi_highpart:1; /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; - * Configures whether or not to disable SPI clock in DUMMY state. \\ - * 0: Not disable \\ - * 1: Disable \\ + * Configures whether or not to disable SPI clock in DUMMY state. + * 0: Not disable + * 1: Disable * Can be configured in CONF state. */ uint32_t usr_dummy_idle:1; /** usr_mosi : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable the write-data (DOUT) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the write-data (DOUT) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_mosi:1; /** usr_miso : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable the read-data (DIN) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the read-data (DIN) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_miso:1; /** usr_dummy : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable the DUMMY state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the DUMMY state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_dummy:1; /** usr_addr : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable the address (ADDR) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the address (ADDR) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_addr:1; /** usr_command : R/W; bitpos: [31]; default: 1; - * Configures whether or not to enable the command (CMD) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the command (CMD) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_command:1; @@ -227,28 +226,28 @@ typedef union { struct { /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7; * Configures the length of DUMMY state. - * Measurement unit: SPI_CLK clock cycles.\\ + * Measurement unit: SPI_CLK clock cycles. * This value is (the expected cycle number - 1). Can be configured in CONF state. */ uint32_t usr_dummy_cyclelen:8; uint32_t reserved_8:8; /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1; * Configures whether or not to end the SPI transfer when SPI RX AFIFO wfull error - * occurs in master full-/half-duplex transfers. \\ - * 0: Not end \\ - * 1: End \\ + * occurs in master full-/half-duplex transfers. + * 0: Not end + * 1: End */ uint32_t mst_wfull_err_end_en:1; /** cs_setup_time : R/W; bitpos: [21:17]; default: 0; * Configures the length of prepare (PREP) state. - * Measurement unit: SPI_CLK clock cycles.\\ + * Measurement unit: SPI_CLK clock cycles. * This value is equal to the expected cycles - 1. This field is used together with * SPI_CS_SETUP. Can be configured in CONF state. */ uint32_t cs_setup_time:5; /** cs_hold_time : R/W; bitpos: [26:22]; default: 1; * Configures the delay cycles of CS pin. - * Measurement unit: SPI_CLK clock cycles. \\ + * Measurement unit: SPI_CLK clock cycles. * This field is used together with SPI_CS_HOLD. Can be configured in CONF state. */ uint32_t cs_hold_time:5; @@ -274,9 +273,9 @@ typedef union { uint32_t reserved_16:11; /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1; * Configures whether or not to end the SPI transfer when SPI TX AFIFO read empty - * error occurs in master full-/half-duplex transfers. \\ - * 0: Not end \\ - * 1: End \\ + * error occurs in master full-/half-duplex transfers. + * 0: Not end + * 1: End */ uint32_t mst_rempty_err_end_en:1; /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; @@ -297,122 +296,122 @@ typedef union { struct { uint32_t reserved_0:3; /** dummy_out : R/W; bitpos: [3]; default: 0; - * Configures whether or not to output the FSPI bus signals in DUMMY state. \\ - * 0: Not output \\ - * 1: Output \\ + * Configures whether or not to output the FSPI bus signals in DUMMY state. + * 0: Not output + * 1: Output * Can be configured in CONF state. */ uint32_t dummy_out:1; uint32_t reserved_4:1; /** faddr_dual : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable 2-bit mode during address (ADDR) state.\\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 2-bit mode during address (ADDR) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t faddr_dual:1; /** faddr_quad : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable 4-bit mode during address (ADDR) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 4-bit mode during address (ADDR) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t faddr_quad:1; /** faddr_oct : HRO; bitpos: [7]; default: 0; - * Configures whether or not to enable 8-bit mode during address (ADDR) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 8-bit mode during address (ADDR) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t faddr_oct:1; /** fcmd_dual : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable 2-bit mode during command (CMD) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 2-bit mode during command (CMD) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t fcmd_dual:1; /** fcmd_quad : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable 4-bit mode during command (CMD) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 4-bit mode during command (CMD) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t fcmd_quad:1; /** fcmd_oct : HRO; bitpos: [10]; default: 0; - * Configures whether or not to enable 8-bit mode during command (CMD) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 8-bit mode during command (CMD) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t fcmd_oct:1; uint32_t reserved_11:3; /** fread_dual : R/W; bitpos: [14]; default: 0; * Configures whether or not to enable the 2-bit mode of read-data (DIN) state in read - * operations. \\ - * 0: Disable \\ - * 1: Enable \\ + * operations. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t fread_dual:1; /** fread_quad : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the 4-bit mode of read-data (DIN) state in read - * operations. \\ - * 0: Disable \\ - * 1: Enable \\ + * operations. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t fread_quad:1; /** fread_oct : HRO; bitpos: [16]; default: 0; * Configures whether or not to enable the 8-bit mode of read-data (DIN) state in read - * operations. \\ - * 0: Disable \\ - * 1: Enable \\ + * operations. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t fread_oct:1; uint32_t reserved_17:1; /** q_pol : R/W; bitpos: [18]; default: 1; - * Configures MISO line polarity. \\ - * 0: Low \\ - * 1: High \\ + * Configures MISO line polarity. + * 0: Low + * 1: High * Can be configured in CONF state. */ uint32_t q_pol:1; /** d_pol : R/W; bitpos: [19]; default: 1; - * Configures MOSI line polarity. \\ - * 0: Low \\ - * 1: High \\ + * Configures MOSI line polarity. + * 0: Low + * 1: High * Can be configured in CONF state. */ uint32_t d_pol:1; /** hold_pol : R/W; bitpos: [20]; default: 1; - * Configures SPI_HOLD output value when SPI is in idle. \\ - * 0: Output low \\ - * 1: Output high \\ + * Configures SPI_HOLD output value when SPI is in idle. + * 0: Output low + * 1: Output high * Can be configured in CONF state. */ uint32_t hold_pol:1; /** wp_pol : R/W; bitpos: [21]; default: 1; - * Configures the output value of write-protect signal when SPI is in idle. \\ - * 0: Output low \\ - * 1: Output high \\ + * Configures the output value of write-protect signal when SPI is in idle. + * 0: Output low + * 1: Output high * Can be configured in CONF state. */ uint32_t wp_pol:1; uint32_t reserved_22:1; /** rd_bit_order : R/W; bitpos: [24:23]; default: 0; - * Configures the bit order in read-data (MISO) state. \\ - * 0: MSB first \\ - * 1: LSB first \\ + * Configures the bit order in read-data (MISO) state. + * 0: MSB first + * 1: LSB first * Can be configured in CONF state. */ uint32_t rd_bit_order:2; /** wr_bit_order : R/W; bitpos: [26:25]; default: 0; * Configures the bit order in command (CMD), address (ADDR), and write-data (MOSI) - * states. \\ - * 0: MSB first \\ - * 1: LSB first \\ + * states. + * 0: MSB first + * 1: LSB first * Can be configured in CONF state. */ uint32_t wr_bit_order:2; @@ -444,58 +443,58 @@ typedef union { typedef union { struct { /** cs0_dis : R/W; bitpos: [0]; default: 0; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ uint32_t cs0_dis:1; /** cs1_dis : R/W; bitpos: [1]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ uint32_t cs1_dis:1; /** cs2_dis : R/W; bitpos: [2]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ uint32_t cs2_dis:1; /** cs3_dis : R/W; bitpos: [3]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ uint32_t cs3_dis:1; /** cs4_dis : R/W; bitpos: [4]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ uint32_t cs4_dis:1; /** cs5_dis : R/W; bitpos: [5]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ uint32_t cs5_dis:1; /** ck_dis : R/W; bitpos: [6]; default: 0; - * Configures whether or not to disable SPI_CLK output.\\ - * 0: Enable\\ - * 1: Disable\\ + * Configures whether or not to disable SPI_CLK output. + * 0: Enable + * 1: Disable * Can be configured in CONF state. */ uint32_t ck_dis:1; /** master_cs_pol : R/W; bitpos: [12:7]; default: 0; - * Configures the polarity of SPI_CS$n ($n = 0-5) line in master transfer.\\ - * 0: SPI_CS$n is low active.\\ - * 1: SPI_CS$n is high active.\\ + * Configures the polarity of SPI_CS$n ($n = 0-5) line in master transfer. + * 0: SPI_CS$n is low active. + * 1: SPI_CS$n is high active. * Can be configured in CONF state. */ uint32_t master_cs_pol:6; @@ -525,9 +524,9 @@ typedef union { uint32_t cmd_dtr_en:1; uint32_t reserved_20:3; /** slave_cs_pol : R/W; bitpos: [23]; default: 0; - * Configures whether or not invert SPI slave input CS polarity.\\ - * 0: Not change\\ - * 1: Invert\\ + * Configures whether or not invert SPI slave input CS polarity. + * 0: Not change + * 1: Invert * Can be configured in CONF state. */ uint32_t slave_cs_pol:1; @@ -537,16 +536,16 @@ typedef union { uint32_t dqs_idle_edge:1; uint32_t reserved_25:4; /** ck_idle_edge : R/W; bitpos: [29]; default: 0; - * Configures the level of SPI_CLK line when GP-SPI2 is in idle.\\ - * 0: Low\\ - * 1: High\\ + * Configures the level of SPI_CLK line when GP-SPI2 is in idle. + * 0: Low + * 1: High * Can be configured in CONF state. */ uint32_t ck_idle_edge:1; /** cs_keep_active : R/W; bitpos: [30]; default: 0; - * Configures whether or not to keep the SPI_CS line low.\\ - * 0: Not keep low\\ - * 1: Keep low\\ + * Configures whether or not to keep the SPI_CS line low. + * 0: Not keep low + * 1: Keep low * Can be configured in CONF state. */ uint32_t cs_keep_active:1; @@ -565,31 +564,31 @@ typedef union { typedef union { struct { /** dma_outfifo_empty : RO; bitpos: [0]; default: 1; - * Represents whether or not the DMA TX FIFO is ready for sending data.\\ - * 0: Ready\\ - * 1: Not ready\\ + * Represents whether or not the DMA TX FIFO is ready for sending data. + * 0: Ready + * 1: Not ready */ uint32_t dma_outfifo_empty:1; /** dma_infifo_full : RO; bitpos: [1]; default: 1; - * Represents whether or not the DMA RX FIFO is ready for receiving data.\\ - * 0: Ready\\ - * 1: Not ready\\ + * Represents whether or not the DMA RX FIFO is ready for receiving data. + * 0: Ready + * 1: Not ready */ uint32_t dma_infifo_full:1; uint32_t reserved_2:16; /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0; * Configures whether or not to enable DMA-controlled segmented transfer in slave - * half-duplex communication.\\ - * 0: Disable\\ - * 1: Enable\\ + * half-duplex communication. + * 0: Disable + * 1: Enable */ uint32_t dma_slv_seg_trans_en:1; /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0; * In slave segmented transfer, if the size of the DMA RX buffer is smaller than the - * size of the received data, \\1: the data in all the following Wr_DMA transactions - * will not be received\\ 0: the data in this Wr_DMA transaction will not be received, - * but in the following transactions,\\ - * + * size of the received data, + * 1: the data in all the following Wr_DMA transactions will not be received + * 0: the data in this Wr_DMA transaction will not be received, but in the following + * transactions, * - if the size of DMA RX buffer is not 0, the data in following Wr_DMA transactions * will be received. * - if the size of DMA RX buffer is 0, the data in following Wr_DMA transactions will @@ -598,12 +597,11 @@ typedef union { uint32_t slv_rx_seg_trans_clr_en:1; /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0; * In slave segmented transfer, if the size of the DMA TX buffer is smaller than the - * size of the transmitted data,\\ + * size of the transmitted data, * 1: the data in the following transactions will not be updated, i.e. the old data is - * transmitted repeatedly.\\ + * transmitted repeatedly. * 0: the data in this transaction will not be updated. But in the following - * transactions,\\ - * + * transactions, * - if new data is filled in DMA TX FIFO, new data will be transmitted. * - if no new data is filled in DMA TX FIFO, no new data will be transmitted. */ @@ -618,41 +616,35 @@ typedef union { uint32_t rx_eof_en:1; uint32_t reserved_22:5; /** dma_rx_ena : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable DMA-controlled receive data transfer.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable DMA-controlled receive data transfer. + * 0: Disable + * 1: Enable */ uint32_t dma_rx_ena:1; /** dma_tx_ena : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable DMA-controlled send data transfer.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable DMA-controlled send data transfer. + * 0: Disable + * 1: Enable */ uint32_t dma_tx_ena:1; /** rx_afifo_rst : WT; bitpos: [29]; default: 0; - * Configures whether or not to reset spi_rx_afifo as shown in Figure link and in Figure link.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset spi_rx_afifo as shown in Figure . + * 0: Not reset + * 1: Reset * spi_rx_afifo is used to receive data in SPI master and slave transfer. */ uint32_t rx_afifo_rst:1; /** buf_afifo_rst : WT; bitpos: [30]; default: 0; - * Configures whether or not to reset buf_tx_afifo as shown in Figure link and in Figure link.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset buf_tx_afifo as shown in Figure . + * 0: Not reset + * 1: Reset * buf_tx_afifo is used to send data out in CPU-controlled master and slave transfer. */ uint32_t buf_afifo_rst:1; /** dma_afifo_rst : WT; bitpos: [31]; default: 0; - * Configures whether or not to reset dma_tx_afifo as shown in Figure link and in Figure link.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset dma_tx_afifo as shown in Figure . + * 0: Not reset + * 1: Reset * dma_tx_afifo is used to send data out in DMA-controlled slave transfer. */ uint32_t dma_afifo_rst:1; @@ -666,55 +658,53 @@ typedef union { typedef union { struct { /** clk_mode : R/W; bitpos: [1:0]; default: 0; - * Configures SPI clock mode.\\ - * 0: SPI clock is off when CS becomes inactive.\\ - * 1: SPI clock is delayed one cycle after CS becomes inactive.\\ - * 2: SPI clock is delayed two cycles after CS becomes inactive.\\ - * 3: SPI clock is always on.\\ + * Configures SPI clock mode. + * 0: SPI clock is off when CS becomes inactive. + * 1: SPI clock is delayed one cycle after CS becomes inactive. + * 2: SPI clock is delayed two cycles after CS becomes inactive. + * 3: SPI clock is always on. * Can be configured in CONF state. */ uint32_t clk_mode:2; /** clk_mode_13 : R/W; bitpos: [2]; default: 0; - * Configure clock mode.\\ - * 0: Support SPI clock mode 0 or 2. See Table link.\\ - * 1: Support SPI clock mode 1 or 3. See Table link.\\ + * Configure clock mode. + * 0: Support SPI clock mode 0 or 2. See Table . + * 1: Support SPI clock mode 1 or 3. See Table . */ uint32_t clk_mode_13:1; /** rsck_data_out : R/W; bitpos: [3]; default: 0; - * Configures the edge of output data.\\ - * 0: Output data at TSCK rising edge.\\ - * 1: Output data at RSCK rising edge.\\ + * Configures the edge of output data. + * 0: Output data at TSCK rising edge. + * 1: Output data at RSCK rising edge. */ uint32_t rsck_data_out:1; uint32_t reserved_4:4; /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Rd_DMA transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Rd_DMA transfer. + * 0: Not use + * 1: Use */ uint32_t slv_rddma_bitlen_en:1; /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Wr_DMA transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Wr_DMA transfer. + * 0: Not use + * 1: Use */ uint32_t slv_wrdma_bitlen_en:1; /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Rd_BUF transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Rd_BUF transfer. + * 0: Not use + * 1: Use */ uint32_t slv_rdbuf_bitlen_en:1; /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Wr_BUF transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Wr_BUF transfer. + * 0: Not use + * 1: Use */ uint32_t slv_wrbuf_bitlen_en:1; /** slv_last_byte_strb : R/SS; bitpos: [19:12]; default: 0; @@ -729,32 +719,31 @@ typedef union { */ uint32_t dma_seg_magic_value:4; /** slave_mode : R/W; bitpos: [26]; default: 0; - * Configures SPI work mode.\\ - * 0: Master\\ - * 1: Slave\\ + * Configures SPI work mode. + * 0: Master + * 1: Slave */ uint32_t slave_mode:1; /** soft_reset : WT; bitpos: [27]; default: 0; - * Configures whether to reset the SPI clock line, CS line, and data line via - * software.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether to reset the SPI clock line, CS line, and data line via software. + * 0: Not reset + * 1: Reset * Can be configured in CONF state. */ uint32_t soft_reset:1; /** usr_conf : R/W; bitpos: [28]; default: 0; * Configures whether or not to enable the CONF state of current DMA-controlled - * configurable segmented transfer.\\ + * configurable segmented transfer. * 0: No effect, which means the current transfer is not a configurable segmented - * transfer.\\ - * 1: Enable, which means a configurable segmented transfer is started.\\ + * transfer. + * 1: Enable, which means a configurable segmented transfer is started. */ uint32_t usr_conf:1; /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0; * Configures whether or not to wait DMA TX data gets ready before starting SPI - * transfer in master full-duplex transfer.\\ - * 0: Not wait\\ - * 1: Wait\\ + * transfer in master full-duplex transfer. + * 0: Not wait + * 1: Wait */ uint32_t mst_fd_wait_dma_tx_data:1; uint32_t reserved_30:2; @@ -799,14 +788,14 @@ typedef union { * Configures the duty cycle of SPI_CLK (high level) in master transfer. * It's recommended to configure this value to floor((SPI_CLKCNT_N + 1)/2 - 1). * floor() here is to round a number down, e.g., floor(2.2) = 2. In slave mode, it - * must be 0. \\ + * must be 0. * Can be configured in CONF state. */ uint32_t clkcnt_h:6; /** clkcnt_n : R/W; bitpos: [17:12]; default: 3; * Configures the divider of SPI_CLK in master transfer. * SPI_CLK frequency is $f_{\textrm{apb_clk}}$/(SPI_CLKDIV_PRE + 1)/(SPI_CLKCNT_N + - * 1). \\ + * 1). * Can be configured in CONF state. */ uint32_t clkcnt_n:6; @@ -815,11 +804,19 @@ typedef union { * Can be configured in CONF state. */ uint32_t clkdiv_pre:4; - uint32_t reserved_22:9; + uint32_t reserved_22:8; + /** clk_edge_sel : R/W; bitpos: [30]; default: 0; + * Configures use standard clock sampling edge or delay the sampling edge by half a + * cycle in master transfer. + * 0: clock sampling edge is delayed by half a cycle. + * 1: clock sampling edge is standard. + * Can be configured in CONF state. + */ + uint32_t clk_edge_sel:1; /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; - * Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer.\\ - * 0: SPI_CLK is divided from APB_CLK.\\ - * 1: SPI_CLK is equal to APB_CLK.\\ + * Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer. + * 0: SPI_CLK is divided from APB_CLK. + * 1: SPI_CLK is equal to APB_CLK. * Can be configured in CONF state. */ uint32_t clk_equ_sysclk:1; @@ -833,9 +830,9 @@ typedef union { typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable clock gate.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable clock gate. + * 0: Disable + * 1: Enable */ uint32_t clk_en:1; /** mst_clk_active : R/W; bitpos: [1]; default: 0; @@ -860,46 +857,46 @@ typedef union { typedef union { struct { /** din0_mode : R/W; bitpos: [1:0]; default: 0; - * Configures the input mode for FSPID signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN0_NUM + 1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPID signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN0_NUM + 1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. */ uint32_t din0_mode:2; /** din1_mode : R/W; bitpos: [3:2]; default: 0; - * Configures the input mode for FSPIQ signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN1_NUM+1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPIQ signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN1_NUM+1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. */ uint32_t din1_mode:2; /** din2_mode : R/W; bitpos: [5:4]; default: 0; - * Configures the input mode for FSPIWP signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN2_NUM + 1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPIWP signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN2_NUM + 1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. */ uint32_t din2_mode:2; /** din3_mode : R/W; bitpos: [7:6]; default: 0; - * Configures the input mode for FSPIHD signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN3_NUM + 1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPIHD signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN3_NUM + 1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. * */ @@ -930,9 +927,9 @@ typedef union { uint32_t din7_mode:2; /** timing_hclk_active : R/W; bitpos: [16]; default: 0; * Configures whether or not to enable HCLK (high-frequency clock) in SPI input timing - * module.\\ - * 0: Disable\\ - * 1: Enable\\ + * module. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t timing_hclk_active:1; @@ -947,40 +944,38 @@ typedef union { typedef union { struct { /** din0_num : R/W; bitpos: [1:0]; default: 0; - * Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ uint32_t din0_num:2; /** din1_num : R/W; bitpos: [3:2]; default: 0; - * Configures the delays to input signal FSPIQ based on the setting of SPI_DIN1_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPIQ based on the setting of SPI_DIN1_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ uint32_t din1_num:2; /** din2_num : R/W; bitpos: [5:4]; default: 0; - * Configures the delays to input signal FSPIWP based on the setting of - * SPI_DIN2_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPIWP based on the setting of SPI_DIN2_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ uint32_t din2_num:2; /** din3_num : R/W; bitpos: [7:6]; default: 0; - * Configures the delays to input signal FSPIHD based on the setting of - * SPI_DIN3_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPIHD based on the setting of SPI_DIN3_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ uint32_t din3_num:2; @@ -1015,30 +1010,30 @@ typedef union { typedef union { struct { /** dout0_mode : R/W; bitpos: [0]; default: 0; - * Configures the output mode for FSPID signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPID signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ uint32_t dout0_mode:1; /** dout1_mode : R/W; bitpos: [1]; default: 0; - * Configures the output mode for FSPIQ signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPIQ signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ uint32_t dout1_mode:1; /** dout2_mode : R/W; bitpos: [2]; default: 0; - * Configures the output mode for FSPIWP signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPIWP signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ uint32_t dout2_mode:1; /** dout3_mode : R/W; bitpos: [3]; default: 0; - * Configures the output mode for FSPIHD signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPIHD signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ uint32_t dout3_mode:1; @@ -1556,12 +1551,12 @@ typedef union { /** Group: CPU-controlled data buffer */ /** Type of wn register - * SPI CPU-controlled buffer n + * SPI CPU-controlled buffer0 */ typedef union { struct { /** buf : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer + * 32-bit data buffer $n. */ uint32_t buf:32; }; @@ -1575,7 +1570,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36716931; + /** date : R/W; bitpos: [27:0]; default: 37761424; * Version control register. */ uint32_t date:28; diff --git a/components/soc/esp32c61/register/soc/usb_serial_jtag_reg.h b/components/soc/esp32c61/register/soc/usb_serial_jtag_reg.h index 255d08ed4b..0bbfd5c36e 100644 --- a/components/soc/esp32c61/register/soc/usb_serial_jtag_reg.h +++ b/components/soc/esp32c61/register/soc/usb_serial_jtag_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -540,13 +540,6 @@ extern "C" { * PHY hardware configuration. */ #define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) -/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; - * Select internal/external PHY - */ -#define USB_SERIAL_JTAG_PHY_SEL (BIT(0)) -#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S) -#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001U -#define USB_SERIAL_JTAG_PHY_SEL_S 0 /** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; * Enable software control USB D+ D- exchange */ @@ -640,6 +633,14 @@ extern "C" { #define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S) #define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U #define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15 +/** USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL : R/W; bitpos: [16]; default: 0; + * Control at which clock edge the dp and dm are sent to USB PHY, 0: tx output at + * clock negative edge. 1: tx output at clock positive edge. + */ +#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL (BIT(16)) +#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_M (USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_V << USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_S) +#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_V 0x00000001U +#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_S 16 /** USB_SERIAL_JTAG_TEST_REG register * Registers used for debugging the PHY. @@ -1215,7 +1216,7 @@ extern "C" { * Date register */ #define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) -/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 36770368; +/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 37822848; * register version. */ #define USB_SERIAL_JTAG_DATE 0xFFFFFFFFU diff --git a/components/soc/esp32c61/register/soc/usb_serial_jtag_struct.h b/components/soc/esp32c61/register/soc/usb_serial_jtag_struct.h index f53954885d..328eb1375a 100644 --- a/components/soc/esp32c61/register/soc/usb_serial_jtag_struct.h +++ b/components/soc/esp32c61/register/soc/usb_serial_jtag_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,7 +23,8 @@ typedef union { * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know * how many data is received, then read data from UART Rx FIFO. */ - uint32_t rdwr_byte:32; + uint32_t rdwr_byte:8; + uint32_t reserved_8:24; }; uint32_t val; } usb_serial_jtag_ep1_reg_t; @@ -59,6 +60,7 @@ typedef union { struct { /** phy_sel : R/W; bitpos: [0]; default: 0; * Select internal/external PHY + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t phy_sel:1; /** exchg_pins_override : R/W; bitpos: [1]; default: 0; @@ -115,7 +117,12 @@ typedef union { * through GPIO Matrix. */ uint32_t usb_jtag_bridge_en:1; - uint32_t reserved_16:16; + /** usb_phy_tx_edge_sel : R/W; bitpos: [16]; default: 0; + * Control at which clock edge the dp and dm are sent to USB PHY, 0: tx output at + * clock negative edge. 1: tx output at clock positive edge. + */ + uint32_t usb_phy_tx_edge_sel:1; + uint32_t reserved_17:15; }; uint32_t val; } usb_serial_jtag_conf0_reg_t; @@ -130,7 +137,7 @@ typedef union { */ uint32_t test_enable:1; /** test_usb_oe : R/W; bitpos: [1]; default: 0; - * USB pad output enable in test + * USB pad oen in test */ uint32_t test_usb_oe:1; /** test_tx_dp : R/W; bitpos: [2]; default: 0; @@ -925,7 +932,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [31:0]; default: 36770368; + /** date : R/W; bitpos: [31:0]; default: 37822848; * register version. */ uint32_t date:32; diff --git a/components/wpa_supplicant/test_apps/README.md b/components/wpa_supplicant/test_apps/README.md index e5c31559f2..57661ca258 100644 --- a/components/wpa_supplicant/test_apps/README.md +++ b/components/wpa_supplicant/test_apps/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # wpa_supplicant unit test diff --git a/docs/conf_common.py b/docs/conf_common.py index fffec165d3..03e40e8b8d 100644 --- a/docs/conf_common.py +++ b/docs/conf_common.py @@ -287,7 +287,7 @@ ESP32C2_DOCS = ['api-guides/RF_calibration.rst', 'api-guides/phy.rst'] ESP32C5_DOCS = ['api-guides/phy.rst', 'api-reference/peripherals/sd_pullup_requirements.rst'] -ESP32C61_DOCS = ['api-guides/phy.rst'] +ESP32C61_DOCS = [] # TODO: IDF-13141, re-open for c61 eco3 ESP32C6_DOCS = [ 'api-guides/RF_calibration.rst', diff --git a/docs/doxygen/Doxyfile_esp32c61 b/docs/doxygen/Doxyfile_esp32c61 index f332f112e2..aaf712269c 100644 --- a/docs/doxygen/Doxyfile_esp32c61 +++ b/docs/doxygen/Doxyfile_esp32c61 @@ -1,5 +1,6 @@ INPUT += \ $(PROJECT_PATH)/components/esp_wifi/include/esp_wifi_he_types.h \ $(PROJECT_PATH)/components/esp_wifi/include/esp_wifi_he.h \ - $(PROJECT_PATH)/components/bt/include/esp32c6/include/esp_bt.h \ - $(PROJECT_PATH)/components/bt/include/esp32c6/include/esp_bt_vs.h \ + # //TODO: IDF-13141, re-open for c61 eco3 + # $(PROJECT_PATH)/components/bt/include/esp32c6/include/esp_bt.h \ + # $(PROJECT_PATH)/components/bt/include/esp32c6/include/esp_bt_vs.h \ diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/README.md b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/README.md index f86c4c7302..b19e36e185 100644 --- a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/README.md +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Beacon/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Bluedroid Beacon Example diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/README.md b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/README.md index ced37511d4..57fbabd059 100644 --- a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/README.md +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_Connection/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Bluedroid Connection Example diff --git a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/README.md b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/README.md index 96b33a5a9b..3fe18aa7ac 100644 --- a/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/README.md +++ b/examples/bluetooth/ble_get_started/bluedroid/Bluedroid_GATT_Server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Bluedroid GATT Server Example diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/README.md b/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/README.md index 4f4b0aed13..d24ea60108 100644 --- a/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/README.md +++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # NimBLE Beacon Example diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/README.md b/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/README.md index 03bd0ae83c..10d5c491db 100644 --- a/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/README.md +++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # NimBLE Connection Example diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/README.md b/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/README.md index 9be317a527..8cf3166053 100644 --- a/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/README.md +++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # NimBLE GATT Server Example diff --git a/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/README.md b/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/README.md index d652ffb4b3..16e35c9f7d 100644 --- a/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/README.md +++ b/examples/bluetooth/ble_get_started/nimble/NimBLE_Security/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # NimBLE Security Example diff --git a/examples/bluetooth/bluedroid/ble/ble_ancs/README.md b/examples/bluetooth/bluedroid/ble/ble_ancs/README.md index a839e400f8..51dfe46c38 100644 --- a/examples/bluetooth/bluedroid/ble/ble_ancs/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_ancs/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE ANCS Example diff --git a/examples/bluetooth/bluedroid/ble/ble_compatibility_test/README.md b/examples/bluetooth/bluedroid/ble/ble_compatibility_test/README.md index acbae4e97e..433e4374eb 100644 --- a/examples/bluetooth/bluedroid/ble/ble_compatibility_test/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_compatibility_test/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE Compatibility Test Example diff --git a/examples/bluetooth/bluedroid/ble/ble_eddystone_receiver/README.md b/examples/bluetooth/bluedroid/ble/ble_eddystone_receiver/README.md index 3ec829bee2..ddd68fec61 100644 --- a/examples/bluetooth/bluedroid/ble/ble_eddystone_receiver/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_eddystone_receiver/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Eddystone Example diff --git a/examples/bluetooth/bluedroid/ble/ble_eddystone_sender/README.md b/examples/bluetooth/bluedroid/ble/ble_eddystone_sender/README.md index 7cb1a69290..c1bd7352d1 100644 --- a/examples/bluetooth/bluedroid/ble/ble_eddystone_sender/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_eddystone_sender/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Eddystone Example diff --git a/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/README.md b/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/README.md index 95fcaf166a..7e76c67aa3 100644 --- a/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_hid_device_demo/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE HID Example diff --git a/examples/bluetooth/bluedroid/ble/ble_ibeacon/README.md b/examples/bluetooth/bluedroid/ble/ble_ibeacon/README.md index b375876e87..ac45b46798 100644 --- a/examples/bluetooth/bluedroid/ble/ble_ibeacon/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_ibeacon/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF iBeacon demo diff --git a/examples/bluetooth/bluedroid/ble/ble_spp_client/README.md b/examples/bluetooth/bluedroid/ble/ble_spp_client/README.md index e0ca60fd04..851f505a00 100644 --- a/examples/bluetooth/bluedroid/ble/ble_spp_client/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_spp_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF SPP GATT CLIENT demo diff --git a/examples/bluetooth/bluedroid/ble/ble_spp_server/README.md b/examples/bluetooth/bluedroid/ble/ble_spp_server/README.md index 9f570d67c9..39f153b065 100644 --- a/examples/bluetooth/bluedroid/ble/ble_spp_server/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_spp_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | ## ESP-IDF GATT SERVER SPP Example diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/README.md b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/README.md index 6b90e7a23e..b1eaf26e65 100644 --- a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE throughput GATT CLIENT Test diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/README.md b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/README.md index 18851f22ea..82e1b95301 100644 --- a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/README.md +++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE throughput GATT SERVER Test diff --git a/examples/bluetooth/bluedroid/ble/gatt_client/README.md b/examples/bluetooth/bluedroid/ble/gatt_client/README.md index df97a162c5..d5da135b3c 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_client/README.md +++ b/examples/bluetooth/bluedroid/ble/gatt_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Client Example diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_client/README.md b/examples/bluetooth/bluedroid/ble/gatt_security_client/README.md index 2fe96fc901..34b0b516aa 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_security_client/README.md +++ b/examples/bluetooth/bluedroid/ble/gatt_security_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Security Client Example diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_server/README.md b/examples/bluetooth/bluedroid/ble/gatt_security_server/README.md index 36b1d60d27..82c7349470 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_security_server/README.md +++ b/examples/bluetooth/bluedroid/ble/gatt_security_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Security Server Example diff --git a/examples/bluetooth/bluedroid/ble/gatt_server/README.md b/examples/bluetooth/bluedroid/ble/gatt_server/README.md index fe79948f1c..a1f7efe0a6 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_server/README.md +++ b/examples/bluetooth/bluedroid/ble/gatt_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Server Example diff --git a/examples/bluetooth/bluedroid/ble/gatt_server_service_table/README.md b/examples/bluetooth/bluedroid/ble/gatt_server_service_table/README.md index 4edb06cf0c..ff6179f470 100644 --- a/examples/bluetooth/bluedroid/ble/gatt_server_service_table/README.md +++ b/examples/bluetooth/bluedroid/ble/gatt_server_service_table/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Server Service Table Example diff --git a/examples/bluetooth/bluedroid/ble/gattc_multi_connect/README.md b/examples/bluetooth/bluedroid/ble/gattc_multi_connect/README.md index 889efc13fe..af18cba2db 100644 --- a/examples/bluetooth/bluedroid/ble/gattc_multi_connect/README.md +++ b/examples/bluetooth/bluedroid/ble/gattc_multi_connect/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Client Multi Connection Example diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_security_client/README.md b/examples/bluetooth/bluedroid/ble_50/ble50_security_client/README.md index c94cd0d3ff..e1d0db6adc 100644 --- a/examples/bluetooth/bluedroid/ble_50/ble50_security_client/README.md +++ b/examples/bluetooth/bluedroid/ble_50/ble50_security_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Gatt Security Client Example diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_security_server/README.md b/examples/bluetooth/bluedroid/ble_50/ble50_security_server/README.md index ae64baa5a6..9f7f9fd75e 100644 --- a/examples/bluetooth/bluedroid/ble_50/ble50_security_server/README.md +++ b/examples/bluetooth/bluedroid/ble_50/ble50_security_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE50 Security Server Example diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_throughput/throughput_client/README.md b/examples/bluetooth/bluedroid/ble_50/ble50_throughput/throughput_client/README.md index b94fd36a80..026ff9d881 100644 --- a/examples/bluetooth/bluedroid/ble_50/ble50_throughput/throughput_client/README.md +++ b/examples/bluetooth/bluedroid/ble_50/ble50_throughput/throughput_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE 50 throughput GATT CLIENT Test diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_throughput/throughput_server/README.md b/examples/bluetooth/bluedroid/ble_50/ble50_throughput/throughput_server/README.md index 70e7f2f6ae..988f28fe74 100644 --- a/examples/bluetooth/bluedroid/ble_50/ble50_throughput/throughput_server/README.md +++ b/examples/bluetooth/bluedroid/ble_50/ble50_throughput/throughput_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BLE 50 throughput GATT SERVER Test diff --git a/examples/bluetooth/bluedroid/ble_50/multi-adv/README.md b/examples/bluetooth/bluedroid/ble_50/multi-adv/README.md index 3f7a212d7d..ba0dfd8180 100644 --- a/examples/bluetooth/bluedroid/ble_50/multi-adv/README.md +++ b/examples/bluetooth/bluedroid/ble_50/multi-adv/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | #ESP-IDF Multi Adv Example diff --git a/examples/bluetooth/bluedroid/ble_50/periodic_adv/README.md b/examples/bluetooth/bluedroid/ble_50/periodic_adv/README.md index cc9a06c40e..98dcffba06 100644 --- a/examples/bluetooth/bluedroid/ble_50/periodic_adv/README.md +++ b/examples/bluetooth/bluedroid/ble_50/periodic_adv/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP_IDF Periodic Adv Example diff --git a/examples/bluetooth/bluedroid/ble_50/periodic_sync/README.md b/examples/bluetooth/bluedroid/ble_50/periodic_sync/README.md index 6cf9dceebb..59254cb20b 100644 --- a/examples/bluetooth/bluedroid/ble_50/periodic_sync/README.md +++ b/examples/bluetooth/bluedroid/ble_50/periodic_sync/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Periodic Sync Example diff --git a/examples/bluetooth/bluedroid/bluedroid_host_only/bluedroid_host_only_uart/README.md b/examples/bluetooth/bluedroid/bluedroid_host_only/bluedroid_host_only_uart/README.md index 97adc5a665..22090b32b7 100644 --- a/examples/bluetooth/bluedroid/bluedroid_host_only/bluedroid_host_only_uart/README.md +++ b/examples/bluetooth/bluedroid/bluedroid_host_only/bluedroid_host_only_uart/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | ESP-IDF UART HCI Host ===================== diff --git a/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/README.md b/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/README.md index 1aba998ec0..a37256a40f 100644 --- a/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/README.md +++ b/examples/bluetooth/bluedroid/coex/gattc_gatts_coex/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | ESP-IDF Gattc and Gatts Coexistence example ============================================== diff --git a/examples/bluetooth/blufi/README.md b/examples/bluetooth/blufi/README.md index 6a07013c72..589638c202 100644 --- a/examples/bluetooth/blufi/README.md +++ b/examples/bluetooth/blufi/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF Blufi Example diff --git a/examples/bluetooth/esp_ble_mesh/aligenie_demo/README.md b/examples/bluetooth/esp_ble_mesh/aligenie_demo/README.md index f89104c4cb..6d3570be59 100644 --- a/examples/bluetooth/esp_ble_mesh/aligenie_demo/README.md +++ b/examples/bluetooth/esp_ble_mesh/aligenie_demo/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh AliGenie Example ============================= diff --git a/examples/bluetooth/esp_ble_mesh/directed_forwarding/README.md b/examples/bluetooth/esp_ble_mesh/directed_forwarding/README.md index 52ec6f3fa5..7cdc334e5f 100644 --- a/examples/bluetooth/esp_ble_mesh/directed_forwarding/README.md +++ b/examples/bluetooth/esp_ble_mesh/directed_forwarding/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | # Directed Forwarding diff --git a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/README.md b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/README.md index d498835b81..58ca4371fd 100644 --- a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/README.md +++ b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh Fast Provisioning Client example ======================== diff --git a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/README.md b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/README.md index 4cbcfb1820..bd9ed0a7bc 100644 --- a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/README.md +++ b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh Fast Provisioning Server example ======================== diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/README.md b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/README.md index f1f7ea462b..267c62c596 100644 --- a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/README.md +++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh Client Model Demo ======================== diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/README.md b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/README.md index e412f506aa..3a0fdc8612 100644 --- a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/README.md +++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh Node demo ========================== diff --git a/examples/bluetooth/esp_ble_mesh/provisioner/README.md b/examples/bluetooth/esp_ble_mesh/provisioner/README.md index 40d4540b11..c5fa5c6572 100644 --- a/examples/bluetooth/esp_ble_mesh/provisioner/README.md +++ b/examples/bluetooth/esp_ble_mesh/provisioner/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh Provisioner demo ================================ diff --git a/examples/bluetooth/esp_ble_mesh/remote_provisioning/README.md b/examples/bluetooth/esp_ble_mesh/remote_provisioning/README.md index 46fcbf9681..53842d0f25 100644 --- a/examples/bluetooth/esp_ble_mesh/remote_provisioning/README.md +++ b/examples/bluetooth/esp_ble_mesh/remote_provisioning/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | # Remote Provisioning (See the README.md file in the upper level 'examples' directory for more information about examples.) diff --git a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/README.md b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/README.md index f76b47d8e2..d711ea9f7e 100644 --- a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/README.md +++ b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh Sensor Client Example ================================== diff --git a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/README.md b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/README.md index 3ea258109f..ef25333faf 100644 --- a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/README.md +++ b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh Sensor Server Example ================================== diff --git a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/README.md b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/README.md index a236ac08bf..085aef23cd 100644 --- a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/README.md +++ b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh Vendor Client Example ================================== diff --git a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/README.md b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/README.md index 4aa875a23d..b9db144804 100644 --- a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/README.md +++ b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh Vendor Server Example ================================== diff --git a/examples/bluetooth/esp_ble_mesh/wifi_coexist/README.md b/examples/bluetooth/esp_ble_mesh/wifi_coexist/README.md index 567f4901c4..2d672fa0be 100644 --- a/examples/bluetooth/esp_ble_mesh/wifi_coexist/README.md +++ b/examples/bluetooth/esp_ble_mesh/wifi_coexist/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | ESP-BLE-MESH and Wi-Fi Coexistence Example ============================================= diff --git a/examples/bluetooth/esp_hid_device/README.md b/examples/bluetooth/esp_hid_device/README.md index 7a80a5d443..8b32d406bf 100644 --- a/examples/bluetooth/esp_hid_device/README.md +++ b/examples/bluetooth/esp_hid_device/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BT/BLE HID Device Demo diff --git a/examples/bluetooth/esp_hid_host/README.md b/examples/bluetooth/esp_hid_host/README.md index 0f4c02f76b..9d29a93e14 100644 --- a/examples/bluetooth/esp_hid_host/README.md +++ b/examples/bluetooth/esp_hid_host/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # ESP-IDF BT/BLE HID Host Demo diff --git a/examples/bluetooth/hci/ble_adv_scan_combined/README.md b/examples/bluetooth/hci/ble_adv_scan_combined/README.md index 20ea4ac560..5fa19f8816 100644 --- a/examples/bluetooth/hci/ble_adv_scan_combined/README.md +++ b/examples/bluetooth/hci/ble_adv_scan_combined/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | ESP-IDF Combined Bluetooth advertising and scanning =================================================== diff --git a/examples/bluetooth/hci/controller_vhci_ble_adv/README.md b/examples/bluetooth/hci/controller_vhci_ble_adv/README.md index 7feb7000d1..e54bfb8ba1 100644 --- a/examples/bluetooth/hci/controller_vhci_ble_adv/README.md +++ b/examples/bluetooth/hci/controller_vhci_ble_adv/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | ESP-IDF VHCI ble_advertising app ================================ diff --git a/examples/bluetooth/nimble/ble_cts/cts_cent/README.md b/examples/bluetooth/nimble/ble_cts/cts_cent/README.md index 571c49f32a..b171a80b05 100644 --- a/examples/bluetooth/nimble/ble_cts/cts_cent/README.md +++ b/examples/bluetooth/nimble/ble_cts/cts_cent/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE CTS Cent Example diff --git a/examples/bluetooth/nimble/ble_cts/cts_prph/README.md b/examples/bluetooth/nimble/ble_cts/cts_prph/README.md index e84491233e..719cced902 100644 --- a/examples/bluetooth/nimble/ble_cts/cts_prph/README.md +++ b/examples/bluetooth/nimble/ble_cts/cts_prph/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE Current Time Service Example diff --git a/examples/bluetooth/nimble/ble_dynamic_service/README.md b/examples/bluetooth/nimble/ble_dynamic_service/README.md index 81158bfcfd..a0297b23b3 100644 --- a/examples/bluetooth/nimble/ble_dynamic_service/README.md +++ b/examples/bluetooth/nimble/ble_dynamic_service/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE Dynamic Service Example diff --git a/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_cent/README.md b/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_cent/README.md index 38e4a0c5ea..65947640d5 100644 --- a/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_cent/README.md +++ b/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_cent/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE Encrypted Advertising Data Central Example diff --git a/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_prph/README.md b/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_prph/README.md index 8c75a5645d..74d151b396 100644 --- a/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_prph/README.md +++ b/examples/bluetooth/nimble/ble_enc_adv_data/enc_adv_data_prph/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE Encrypted Advertising Data Peripheral Example diff --git a/examples/bluetooth/nimble/ble_gattc_gatts_coex/README.md b/examples/bluetooth/nimble/ble_gattc_gatts_coex/README.md index 3d91b02206..684ac49dea 100644 --- a/examples/bluetooth/nimble/ble_gattc_gatts_coex/README.md +++ b/examples/bluetooth/nimble/ble_gattc_gatts_coex/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE GATTC GATTS Coex Example diff --git a/examples/bluetooth/nimble/ble_htp/htp_cent/README.md b/examples/bluetooth/nimble/ble_htp/htp_cent/README.md index b7546d3547..90cbe19c99 100644 --- a/examples/bluetooth/nimble/ble_htp/htp_cent/README.md +++ b/examples/bluetooth/nimble/ble_htp/htp_cent/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE HTP Cent Example diff --git a/examples/bluetooth/nimble/ble_htp/htp_prph/README.md b/examples/bluetooth/nimble/ble_htp/htp_prph/README.md index 365f877e6a..0298750360 100644 --- a/examples/bluetooth/nimble/ble_htp/htp_prph/README.md +++ b/examples/bluetooth/nimble/ble_htp/htp_prph/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE Heart Rate Measurement Example diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/README.md b/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/README.md index e428b899c4..3c2359c39a 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/README.md +++ b/examples/bluetooth/nimble/ble_l2cap_coc/coc_blecent/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE Central L2CAP COC Example diff --git a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/README.md b/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/README.md index 91ba54dac7..bc89496edd 100644 --- a/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/README.md +++ b/examples/bluetooth/nimble/ble_l2cap_coc/coc_bleprph/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE Peripheral L2CAP COC Example diff --git a/examples/bluetooth/nimble/ble_multi_adv/README.md b/examples/bluetooth/nimble/ble_multi_adv/README.md index b485d51198..f274722908 100644 --- a/examples/bluetooth/nimble/ble_multi_adv/README.md +++ b/examples/bluetooth/nimble/ble_multi_adv/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE Multi Adv Example diff --git a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/README.md b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/README.md index 8f3339a66e..dc3bf6cc3c 100644 --- a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/README.md +++ b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | -| ----------------- | -------- | -------- | --------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | -------- | # BLE Multiple Connection Central Example diff --git a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/README.md b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/README.md index 95d7358bbd..8038e1aa55 100644 --- a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/README.md +++ b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | -| ----------------- | -------- | -------- | --------- | -------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | -------- | # BLE Multiple Connection Peripheral Example diff --git a/examples/bluetooth/nimble/ble_periodic_adv/README.md b/examples/bluetooth/nimble/ble_periodic_adv/README.md index 2841fb0569..3f1132a107 100644 --- a/examples/bluetooth/nimble/ble_periodic_adv/README.md +++ b/examples/bluetooth/nimble/ble_periodic_adv/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE Periodic Advertiser Example diff --git a/examples/bluetooth/nimble/ble_periodic_sync/README.md b/examples/bluetooth/nimble/ble_periodic_sync/README.md index f42796b1e0..1bdaf4427d 100644 --- a/examples/bluetooth/nimble/ble_periodic_sync/README.md +++ b/examples/bluetooth/nimble/ble_periodic_sync/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE Periodic Sync Example diff --git a/examples/bluetooth/nimble/ble_phy/phy_cent/README.md b/examples/bluetooth/nimble/ble_phy/phy_cent/README.md index 577e115f53..9a985ed607 100644 --- a/examples/bluetooth/nimble/ble_phy/phy_cent/README.md +++ b/examples/bluetooth/nimble/ble_phy/phy_cent/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE Central PHY Example diff --git a/examples/bluetooth/nimble/ble_phy/phy_prph/README.md b/examples/bluetooth/nimble/ble_phy/phy_prph/README.md index e1e08e7271..ba3069abc8 100644 --- a/examples/bluetooth/nimble/ble_phy/phy_prph/README.md +++ b/examples/bluetooth/nimble/ble_phy/phy_prph/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE Peripheral PHY Example diff --git a/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_cent/README.md b/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_cent/README.md index bed629eaf9..47cbd72465 100644 --- a/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_cent/README.md +++ b/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_cent/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE Central Proximity Sensor Example diff --git a/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_prph/README.md b/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_prph/README.md index a3323cf122..0ab040898f 100644 --- a/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_prph/README.md +++ b/examples/bluetooth/nimble/ble_proximity_sensor/proximity_sensor_prph/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE Peripheral Proximity Sensor Example diff --git a/examples/bluetooth/nimble/ble_spp/spp_client/README.md b/examples/bluetooth/nimble/ble_spp/spp_client/README.md index 25cb257aff..5be87b530e 100644 --- a/examples/bluetooth/nimble/ble_spp/spp_client/README.md +++ b/examples/bluetooth/nimble/ble_spp/spp_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE SPP central example diff --git a/examples/bluetooth/nimble/ble_spp/spp_server/README.md b/examples/bluetooth/nimble/ble_spp/spp_server/README.md index 8b2adb4d14..a9d13fc8fe 100644 --- a/examples/bluetooth/nimble/ble_spp/spp_server/README.md +++ b/examples/bluetooth/nimble/ble_spp/spp_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE SPP peripheral example diff --git a/examples/bluetooth/nimble/blecent/README.md b/examples/bluetooth/nimble/blecent/README.md index 4aff911fe3..cdf60286d1 100644 --- a/examples/bluetooth/nimble/blecent/README.md +++ b/examples/bluetooth/nimble/blecent/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE Central Example diff --git a/examples/bluetooth/nimble/blecsc/README.md b/examples/bluetooth/nimble/blecsc/README.md index aab033e044..e934a01d82 100644 --- a/examples/bluetooth/nimble/blecsc/README.md +++ b/examples/bluetooth/nimble/blecsc/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/examples/bluetooth/nimble/blehr/README.md b/examples/bluetooth/nimble/blehr/README.md index c4c1f62a69..93f73518e0 100644 --- a/examples/bluetooth/nimble/blehr/README.md +++ b/examples/bluetooth/nimble/blehr/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE Heart Rate Measurement Example diff --git a/examples/bluetooth/nimble/bleprph/README.md b/examples/bluetooth/nimble/bleprph/README.md index 27540364e8..e5b45d1690 100644 --- a/examples/bluetooth/nimble/bleprph/README.md +++ b/examples/bluetooth/nimble/bleprph/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE Peripheral Example diff --git a/examples/bluetooth/nimble/bleprph_host_only/README.md b/examples/bluetooth/nimble/bleprph_host_only/README.md index d60b04e5ba..443d506d0c 100644 --- a/examples/bluetooth/nimble/bleprph_host_only/README.md +++ b/examples/bluetooth/nimble/bleprph_host_only/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # BLE Peripheral Example diff --git a/examples/bluetooth/nimble/bleprph_wifi_coex/README.md b/examples/bluetooth/nimble/bleprph_wifi_coex/README.md index 1ae1277e48..dc6e3d215d 100644 --- a/examples/bluetooth/nimble/bleprph_wifi_coex/README.md +++ b/examples/bluetooth/nimble/bleprph_wifi_coex/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # BLE Peripheral with ICMP Echo-Reply diff --git a/examples/bluetooth/nimble/hci/README.md b/examples/bluetooth/nimble/hci/README.md index 23c81f3c25..5d77232644 100644 --- a/examples/bluetooth/nimble/hci/README.md +++ b/examples/bluetooth/nimble/hci/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C2 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | -| ----------------- | -------- | -------- | -------- | --------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C5 | ESP32-C6 | ESP32-H2 | +| ----------------- | -------- | -------- | -------- | -------- | ESP-IDF UART HCI Controller =========================== diff --git a/examples/bluetooth/nimble/power_save/README.md b/examples/bluetooth/nimble/power_save/README.md index 2cbea64861..f71ee71458 100644 --- a/examples/bluetooth/nimble/power_save/README.md +++ b/examples/bluetooth/nimble/power_save/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | Bluetooth Power Save Example ================================= diff --git a/examples/bluetooth/nimble/throughput_app/blecent_throughput/README.md b/examples/bluetooth/nimble/throughput_app/blecent_throughput/README.md index 51cd8f3733..2da8757038 100644 --- a/examples/bluetooth/nimble/throughput_app/blecent_throughput/README.md +++ b/examples/bluetooth/nimble/throughput_app/blecent_throughput/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Throughput blecent Example diff --git a/examples/bluetooth/nimble/throughput_app/bleprph_throughput/README.md b/examples/bluetooth/nimble/throughput_app/bleprph_throughput/README.md index f22f9effc5..924c5d5c37 100644 --- a/examples/bluetooth/nimble/throughput_app/bleprph_throughput/README.md +++ b/examples/bluetooth/nimble/throughput_app/bleprph_throughput/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Throughput bleprph Example diff --git a/examples/mesh/internal_communication/README.md b/examples/mesh/internal_communication/README.md index c2a5b5f488..a86b04351c 100644 --- a/examples/mesh/internal_communication/README.md +++ b/examples/mesh/internal_communication/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # Mesh Internal Communication Example diff --git a/examples/mesh/ip_internal_network/README.md b/examples/mesh/ip_internal_network/README.md index 394e9622b8..2cbf75ed58 100644 --- a/examples/mesh/ip_internal_network/README.md +++ b/examples/mesh/ip_internal_network/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # Mesh IP Internal Networking example diff --git a/examples/mesh/manual_networking/README.md b/examples/mesh/manual_networking/README.md index 5fc60d9bf9..276ea16130 100644 --- a/examples/mesh/manual_networking/README.md +++ b/examples/mesh/manual_networking/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | # Mesh Manual Networking Example diff --git a/examples/network/eth2ap/README.md b/examples/network/eth2ap/README.md index f6437c1728..20306fa973 100644 --- a/examples/network/eth2ap/README.md +++ b/examples/network/eth2ap/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # eth2ap Example (See the README.md file in the upper level 'examples' directory for more information about examples. To try a more complex application about Ethernet to WiFi data forwarding, please go to [iot-solution](https://github.com/espressif/esp-iot-solution/tree/release/v1.0/examples/eth2wifi).) diff --git a/examples/network/simple_sniffer/README.md b/examples/network/simple_sniffer/README.md index 2af07bb096..9503435084 100644 --- a/examples/network/simple_sniffer/README.md +++ b/examples/network/simple_sniffer/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Simple Sniffer Example diff --git a/examples/network/sta2eth/README.md b/examples/network/sta2eth/README.md index 2665071dca..ac29de800a 100644 --- a/examples/network/sta2eth/README.md +++ b/examples/network/sta2eth/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # WiFi station to "Wired" interface L2 forwarder diff --git a/examples/openthread/ot_br/README.md b/examples/openthread/ot_br/README.md index 718fbd86d4..29f4f7b060 100644 --- a/examples/openthread/ot_br/README.md +++ b/examples/openthread/ot_br/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | # OpenThread Border Router Example diff --git a/examples/openthread/ot_trel/README.md b/examples/openthread/ot_trel/README.md index 5cc60dfa2f..2ce050140b 100644 --- a/examples/openthread/ot_trel/README.md +++ b/examples/openthread/ot_trel/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Thread Radio Encapsulation Link Example diff --git a/examples/peripherals/i2c/i2c_slave_network_sensor/README.md b/examples/peripherals/i2c/i2c_slave_network_sensor/README.md index 91c3ef9314..4f1ad29e2c 100644 --- a/examples/peripherals/i2c/i2c_slave_network_sensor/README.md +++ b/examples/peripherals/i2c/i2c_slave_network_sensor/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | +| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | # I2C slave example diff --git a/examples/protocols/http_server/captive_portal/README.md b/examples/protocols/http_server/captive_portal/README.md index 7b13b555fb..41f1840b05 100644 --- a/examples/protocols/http_server/captive_portal/README.md +++ b/examples/protocols/http_server/captive_portal/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Captive Portal Example diff --git a/examples/provisioning/wifi_prov_mgr/README.md b/examples/provisioning/wifi_prov_mgr/README.md index 50a458f5c5..7648e58670 100644 --- a/examples/provisioning/wifi_prov_mgr/README.md +++ b/examples/provisioning/wifi_prov_mgr/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Wi-Fi Provisioning Manager Example diff --git a/examples/wifi/espnow/README.md b/examples/wifi/espnow/README.md index c9880f6fbe..198522d838 100644 --- a/examples/wifi/espnow/README.md +++ b/examples/wifi/espnow/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # ESPNOW Example diff --git a/examples/wifi/fast_scan/README.md b/examples/wifi/fast_scan/README.md index 003351dba6..2be7009b42 100644 --- a/examples/wifi/fast_scan/README.md +++ b/examples/wifi/fast_scan/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Wi-Fi Fast Scan Example diff --git a/examples/wifi/getting_started/softAP/README.md b/examples/wifi/getting_started/softAP/README.md index 4c9713eadb..7a7277cfa5 100644 --- a/examples/wifi/getting_started/softAP/README.md +++ b/examples/wifi/getting_started/softAP/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Wi-Fi SoftAP Example diff --git a/examples/wifi/getting_started/station/README.md b/examples/wifi/getting_started/station/README.md index 07ca4f962a..6a35555d95 100644 --- a/examples/wifi/getting_started/station/README.md +++ b/examples/wifi/getting_started/station/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Wi-Fi Station Example diff --git a/examples/wifi/iperf/README.md b/examples/wifi/iperf/README.md index 1b86f94ccd..99b17378b4 100644 --- a/examples/wifi/iperf/README.md +++ b/examples/wifi/iperf/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Iperf Example diff --git a/examples/wifi/itwt/README.md b/examples/wifi/itwt/README.md index 74079c36be..49ba38a5c2 100644 --- a/examples/wifi/itwt/README.md +++ b/examples/wifi/itwt/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | -| ----------------- | -------- | -------- | --------- | +| Supported Targets | ESP32-C5 | ESP32-C6 | +| ----------------- | -------- | -------- | # Wifi itwt Example diff --git a/examples/wifi/power_save/README.md b/examples/wifi/power_save/README.md index 473379d265..50df4b8e6e 100644 --- a/examples/wifi/power_save/README.md +++ b/examples/wifi/power_save/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Wifi Power Save Example diff --git a/examples/wifi/roaming/roaming_11kvr/README.md b/examples/wifi/roaming/roaming_11kvr/README.md index de083f2f4c..5e069f0a10 100644 --- a/examples/wifi/roaming/roaming_11kvr/README.md +++ b/examples/wifi/roaming/roaming_11kvr/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Roaming Example diff --git a/examples/wifi/roaming/roaming_app/README.md b/examples/wifi/roaming/roaming_app/README.md index 6a26485be5..5484547e09 100644 --- a/examples/wifi/roaming/roaming_app/README.md +++ b/examples/wifi/roaming/roaming_app/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Wi-Fi Station Example diff --git a/examples/wifi/scan/README.md b/examples/wifi/scan/README.md index f69e8a56b6..44fe4c7fe7 100644 --- a/examples/wifi/scan/README.md +++ b/examples/wifi/scan/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Wi-Fi Scan Example diff --git a/examples/wifi/smart_config/README.md b/examples/wifi/smart_config/README.md index 191d3d085e..822c52226b 100644 --- a/examples/wifi/smart_config/README.md +++ b/examples/wifi/smart_config/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # smartconfig Example diff --git a/examples/wifi/softap_sta/README.md b/examples/wifi/softap_sta/README.md index 1c7e046959..21a5098a2a 100644 --- a/examples/wifi/softap_sta/README.md +++ b/examples/wifi/softap_sta/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Wi-Fi SoftAP & Station Example diff --git a/examples/wifi/wifi_aware/nan_console/README.md b/examples/wifi/wifi_aware/nan_console/README.md index 2601c22a5c..f203f2effe 100644 --- a/examples/wifi/wifi_aware/nan_console/README.md +++ b/examples/wifi/wifi_aware/nan_console/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C5 | ESP32-C61 | ESP32-S2 | -| ----------------- | ----- | -------- | --------- | -------- | +| Supported Targets | ESP32 | ESP32-C5 | ESP32-S2 | +| ----------------- | ----- | -------- | -------- | # NAN Console Example diff --git a/examples/wifi/wifi_aware/nan_publisher/README.md b/examples/wifi/wifi_aware/nan_publisher/README.md index a50dd05847..a5013be5db 100644 --- a/examples/wifi/wifi_aware/nan_publisher/README.md +++ b/examples/wifi/wifi_aware/nan_publisher/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C5 | ESP32-C61 | ESP32-S2 | -| ----------------- | ----- | -------- | --------- | -------- | +| Supported Targets | ESP32 | ESP32-C5 | ESP32-S2 | +| ----------------- | ----- | -------- | -------- | # NAN Publisher Example diff --git a/examples/wifi/wifi_aware/nan_subscriber/README.md b/examples/wifi/wifi_aware/nan_subscriber/README.md index c648c75ab7..02fe1a1feb 100644 --- a/examples/wifi/wifi_aware/nan_subscriber/README.md +++ b/examples/wifi/wifi_aware/nan_subscriber/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C5 | ESP32-C61 | ESP32-S2 | -| ----------------- | ----- | -------- | --------- | -------- | +| Supported Targets | ESP32 | ESP32-C5 | ESP32-S2 | +| ----------------- | ----- | -------- | -------- | # NAN Subscriber Example diff --git a/examples/wifi/wifi_eap_fast/README.md b/examples/wifi/wifi_eap_fast/README.md index ea048f9146..670c852fcf 100644 --- a/examples/wifi/wifi_eap_fast/README.md +++ b/examples/wifi/wifi_eap_fast/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # WPA2 Enterprise Example diff --git a/examples/wifi/wifi_easy_connect/dpp-enrollee/README.md b/examples/wifi/wifi_easy_connect/dpp-enrollee/README.md index 859ccb2f77..5e6740aa28 100644 --- a/examples/wifi/wifi_easy_connect/dpp-enrollee/README.md +++ b/examples/wifi/wifi_easy_connect/dpp-enrollee/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Device Provisioning Protocol (Enrollee) Example diff --git a/examples/wifi/wifi_enterprise/README.md b/examples/wifi/wifi_enterprise/README.md index c9b821f295..06404b82c5 100644 --- a/examples/wifi/wifi_enterprise/README.md +++ b/examples/wifi/wifi_enterprise/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Understanding different WiFi enterprise modes: diff --git a/examples/wifi/wifi_nvs_config/README.md b/examples/wifi/wifi_nvs_config/README.md index ccab6ce2cd..c0043ba5a8 100644 --- a/examples/wifi/wifi_nvs_config/README.md +++ b/examples/wifi/wifi_nvs_config/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # WiFi NVS Config Example diff --git a/examples/wifi/wps/README.md b/examples/wifi/wps/README.md index 4260e86dfa..089f1fd0f1 100644 --- a/examples/wifi/wps/README.md +++ b/examples/wifi/wps/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Wi-Fi WPS Example diff --git a/examples/wifi/wps_softap_registrar/README.md b/examples/wifi/wps_softap_registrar/README.md index e6dcd9da91..1af61b74d8 100644 --- a/examples/wifi/wps_softap_registrar/README.md +++ b/examples/wifi/wps_softap_registrar/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # Wi-Fi WPS Registrar Example diff --git a/tools/test_apps/peripherals/i2c_wifi/README.md b/tools/test_apps/peripherals/i2c_wifi/README.md index fd5ce5dc51..e2fe908965 100644 --- a/tools/test_apps/peripherals/i2c_wifi/README.md +++ b/tools/test_apps/peripherals/i2c_wifi/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | # I2C-WIFI Test diff --git a/tools/test_apps/phy/phy_multi_init_data_test/README.md b/tools/test_apps/phy/phy_multi_init_data_test/README.md index 1c35092948..0c839f750c 100644 --- a/tools/test_apps/phy/phy_multi_init_data_test/README.md +++ b/tools/test_apps/phy/phy_multi_init_data_test/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/tools/test_apps/phy/phy_tsens/README.md b/tools/test_apps/phy/phy_tsens/README.md index c9e6beeb01..30a51ab995 100644 --- a/tools/test_apps/phy/phy_tsens/README.md +++ b/tools/test_apps/phy/phy_tsens/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | -| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 | +| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- |