diff --git a/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld b/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld
index 5a20fa92a0..be2ef967a1 100644
--- a/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld
+++ b/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld
@@ -39,7 +39,7 @@ SECTIONS
     *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
     *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
     *libsoc.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
-    *libsoc.a:i2c_rtc_clk.*(.literal .text .literal.* .text.*)
+    *libsoc.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
     *libefuse.a:*.*(.literal .text .literal.* .text.*)
     *(.fini.literal)
     *(.fini)
diff --git a/components/driver/esp32s2/rtc_tempsensor.c b/components/driver/esp32s2/rtc_tempsensor.c
index cb92253d9d..ca7ef7ecd9 100644
--- a/components/driver/esp32s2/rtc_tempsensor.c
+++ b/components/driver/esp32s2/rtc_tempsensor.c
@@ -25,6 +25,7 @@
 #include "soc/sens_struct.h"
 #include "driver/temp_sensor.h"
 #include "esp32s2/rom/ets_sys.h"
+#include "regi2c_ctrl.h"
 
 static const char *TAG = "tsens";
 
@@ -39,18 +40,6 @@ static const char *TAG = "tsens";
 #define TSENS_DAC_FACTOR  (27.88)
 #define TSENS_SYS_OFFSET  (20.52)
 
-#include "i2c_rtc_clk.h"
-
-#define ANA_CONFIG2_REG  0x6000E048
-#define ANA_CONFIG2_M   (BIT(18))
-
-#define I2C_ADC            0X69
-#define I2C_ADC_HOSTID     1
-
-#define I2C_SARADC_TSENS_DAC        6
-#define I2C_SARADC_TSENS_DAC_MSB    3
-#define I2C_SARADC_TSENS_DAC_LSB    0
-
 typedef struct {
     int index;
     int offset;
@@ -75,9 +64,9 @@ esp_err_t temp_sensor_set_config(temp_sensor_config_t tsens)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M);
     SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
-    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
-    SET_PERI_REG_MASK(ANA_CONFIG2_REG, BIT(16));
-    I2C_WRITEREG_MASK_RTC(I2C_ADC, I2C_SARADC_TSENS_DAC, dac_offset[tsens.dac_offset].set_val);
+    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M);
+    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC, dac_offset[tsens.dac_offset].set_val);
     SENS.sar_tctrl.tsens_clk_div = tsens.clk_div;
     SENS.sar_tctrl.tsens_power_up_force = 1;
     SENS.sar_tctrl2.tsens_xpd_wait = TSENS_XPD_WAIT_DEFAULT;
@@ -96,9 +85,9 @@ esp_err_t temp_sensor_get_config(temp_sensor_config_t *tsens)
     TSENS_CHECK(tsens != NULL, ESP_ERR_INVALID_ARG);
     CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M);
     SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
-    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
-    SET_PERI_REG_MASK(ANA_CONFIG2_REG, BIT(16));
-    tsens->dac_offset = I2C_READREG_MASK_RTC(I2C_ADC, I2C_SARADC_TSENS_DAC);
+    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M);
+    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
+    tsens->dac_offset = REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC);
     for (int i = TSENS_DAC_L0; i < TSENS_DAC_MAX; i++) {
         if (tsens->dac_offset == dac_offset[i].set_val) {
             tsens->dac_offset = dac_offset[i].index;
diff --git a/components/soc/soc/component.mk b/components/soc/soc/component.mk
index 0bbeee0844..8deea5253f 100644
--- a/components/soc/soc/component.mk
+++ b/components/soc/soc/component.mk
@@ -1,2 +1,2 @@
-COMPONENT_ADD_INCLUDEDIRS += soc/include soc/$(SOC_NAME) soc/$(SOC_NAME)/include
+COMPONENT_ADD_INCLUDEDIRS += soc/include soc/$(SOC_NAME)/private_include soc/$(SOC_NAME)/include
 COMPONENT_SRCDIRS += soc/$(SOC_NAME)
diff --git a/components/soc/soc/esp32/CMakeLists.txt b/components/soc/soc/esp32/CMakeLists.txt
index d078dd52d5..334f189b5e 100644
--- a/components/soc/soc/esp32/CMakeLists.txt
+++ b/components/soc/soc/esp32/CMakeLists.txt
@@ -14,4 +14,4 @@ add_library(soc_esp32 STATIC
     "uart_periph.c"
     "touch_sensor_periph.c")
 
-target_include_directories(soc_esp32 PUBLIC . include ../include)
\ No newline at end of file
+target_include_directories(soc_esp32 PUBLIC include ../include private_include)
\ No newline at end of file
diff --git a/components/soc/soc/esp32/i2c_apll.h b/components/soc/soc/esp32/private_include/regi2c_apll.h
similarity index 97%
rename from components/soc/soc/esp32/i2c_apll.h
rename to components/soc/soc/esp32/private_include/regi2c_apll.h
index 935810afab..05f274b28b 100644
--- a/components/soc/soc/esp32/i2c_apll.h
+++ b/components/soc/soc/esp32/private_include/regi2c_apll.h
@@ -15,11 +15,11 @@
 #pragma once
 
 /**
- * @file i2c_apll.h
+ * @file regi2c_apll.h
  * @brief Register definitions for audio PLL (APLL)
  *
  * This file lists register fields of APLL, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
  * rtc_clk_apll_enable function in rtc_clk.c.
  */
 
diff --git a/components/soc/soc/esp32/i2c_bbpll.h b/components/soc/soc/esp32/private_include/regi2c_bbpll.h
similarity index 98%
rename from components/soc/soc/esp32/i2c_bbpll.h
rename to components/soc/soc/esp32/private_include/regi2c_bbpll.h
index 6889bc7321..68c87fb6c9 100644
--- a/components/soc/soc/esp32/i2c_bbpll.h
+++ b/components/soc/soc/esp32/private_include/regi2c_bbpll.h
@@ -15,11 +15,11 @@
 #pragma once
 
 /**
- * @file i2c_apll.h
+ * @file regi2c_apll.h
  * @brief Register definitions for digital PLL (BBPLL)
  *
  * This file lists register fields of BBPLL, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
  * rtc_clk_cpu_freq_set function in rtc_clk.c.
  */
 
diff --git a/components/soc/soc/esp32s2/CMakeLists.txt b/components/soc/soc/esp32s2/CMakeLists.txt
index 808e76f7e0..f981736f66 100644
--- a/components/soc/soc/esp32s2/CMakeLists.txt
+++ b/components/soc/soc/esp32s2/CMakeLists.txt
@@ -13,4 +13,4 @@ add_library(soc_esp32s2 STATIC
     "usb_periph.c"
     "touch_sensor_periph.c")
 
-target_include_directories(soc_esp32s2 PUBLIC . include ../include)
+target_include_directories(soc_esp32s2 PUBLIC include ../include private_include)
diff --git a/components/soc/soc/esp32s2/i2c_apll.h b/components/soc/soc/esp32s2/private_include/regi2c_apll.h
similarity index 97%
rename from components/soc/soc/esp32s2/i2c_apll.h
rename to components/soc/soc/esp32s2/private_include/regi2c_apll.h
index 909326f64e..a6630d92cb 100644
--- a/components/soc/soc/esp32s2/i2c_apll.h
+++ b/components/soc/soc/esp32s2/private_include/regi2c_apll.h
@@ -15,11 +15,11 @@
 #pragma once
 
 /**
- * @file i2c_apll.h
+ * @file regi2c_apll.h
  * @brief Register definitions for audio PLL (APLL)
  *
  * This file lists register fields of APLL, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
  * rtc_clk_apll_enable function in rtc_clk.c.
  */
 
diff --git a/components/soc/soc/esp32s2/i2c_bbpll.h b/components/soc/soc/esp32s2/private_include/regi2c_bbpll.h
similarity index 98%
rename from components/soc/soc/esp32s2/i2c_bbpll.h
rename to components/soc/soc/esp32s2/private_include/regi2c_bbpll.h
index 1f56a5f40d..494f1d7225 100644
--- a/components/soc/soc/esp32s2/i2c_bbpll.h
+++ b/components/soc/soc/esp32s2/private_include/regi2c_bbpll.h
@@ -15,11 +15,11 @@
 #pragma once
 
 /**
- * @file i2c_apll.h
+ * @file regi2c_apll.h
  * @brief Register definitions for digital PLL (BBPLL)
  *
  * This file lists register fields of BBPLL, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
  * rtc_clk_cpu_freq_set function in rtc_clk.c.
  */
 
diff --git a/components/soc/src/esp32s2/i2c_brownout.h b/components/soc/soc/esp32s2/private_include/regi2c_brownout.h
similarity index 90%
rename from components/soc/src/esp32s2/i2c_brownout.h
rename to components/soc/soc/esp32s2/private_include/regi2c_brownout.h
index 5fac2c91b3..0b8b618bba 100644
--- a/components/soc/src/esp32s2/i2c_brownout.h
+++ b/components/soc/soc/esp32s2/private_include/regi2c_brownout.h
@@ -15,11 +15,11 @@
 #pragma once
 
 /**
- * @file i2c_brownout.h
+ * @file regi2c_brownout.h
  * @brief Register definitions for brownout detector
  *
  * This file lists register fields of the brownout detector, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h.
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h.
  */
 
 #define I2C_BOD            0x61
diff --git a/components/soc/soc/esp32s2/i2c_saradc.h b/components/soc/soc/esp32s2/private_include/regi2c_saradc.h
similarity index 90%
rename from components/soc/soc/esp32s2/i2c_saradc.h
rename to components/soc/soc/esp32s2/private_include/regi2c_saradc.h
index 5aa6451743..0c223812bb 100644
--- a/components/soc/soc/esp32s2/i2c_saradc.h
+++ b/components/soc/soc/esp32s2/private_include/regi2c_saradc.h
@@ -15,18 +15,16 @@
 #pragma once
 
 /**
- * @file i2c_sar.h
+ * @file regi2c_saradc.h
  * @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC.
  *
  * This file lists register fields of SAR, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
  * function in adc_ll.h.
  */
 
 #define I2C_SAR_ADC            0X69
-#define I2C_SAR_ADC_HOSTID     0
-
-#define ADC_ANA_CONFIG2_REG  0x6000E048
+#define I2C_SAR_ADC_HOSTID     1
 
 #define ADC_SAR1_ENCAL_GND_ADDR 0x7
 #define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
@@ -75,3 +73,7 @@
 #define ADC_SARADC_ENT_RTC_ADDR 0x7
 #define ADC_SARADC_ENT_RTC_ADDR_MSB 3
 #define ADC_SARADC_ENT_RTC_ADDR_LSB 3
+
+#define I2C_SARADC_TSENS_DAC 0x6
+#define I2C_SARADC_TSENS_DAC_MSB 3
+#define I2C_SARADC_TSENS_DAC_LSB 0
diff --git a/components/soc/soc/esp32s2/i2c_ulp.h b/components/soc/soc/esp32s2/private_include/regi2c_ulp.h
similarity index 92%
rename from components/soc/soc/esp32s2/i2c_ulp.h
rename to components/soc/soc/esp32s2/private_include/regi2c_ulp.h
index e7f4afa08f..1bd427836d 100644
--- a/components/soc/soc/esp32s2/i2c_ulp.h
+++ b/components/soc/soc/esp32s2/private_include/regi2c_ulp.h
@@ -15,11 +15,11 @@
 #pragma once
 
 /**
- * @file i2c_ulp.h
+ * @file regi2c_ulp.h
  * @brief Register definitions for analog to calibrate o_code for getting a more precise voltage.
  *
  * This file lists register fields of ULP, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
  * rtc_init function in rtc_init.c.
  */
 
diff --git a/components/soc/src/esp32/i2c_rtc_clk.h b/components/soc/src/esp32/regi2c_ctrl.h
similarity index 85%
rename from components/soc/src/esp32/i2c_rtc_clk.h
rename to components/soc/src/esp32/regi2c_ctrl.h
index 5ca44d3089..1a8c2b3b21 100644
--- a/components/soc/src/esp32/i2c_rtc_clk.h
+++ b/components/soc/src/esp32/regi2c_ctrl.h
@@ -14,8 +14,9 @@
 
 #pragma once
 
-#include "i2c_apll.h"
-#include "i2c_bbpll.h"
+#include <stdint.h>
+#include "regi2c_apll.h"
+#include "regi2c_bbpll.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -37,18 +38,18 @@ void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t d
 void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
 
 /* Convenience macros for the above functions, these use register definitions
- * from i2c_apll.h/i2c_bbpll.h header files.
+ * from regi2c_apll.h/regi2c_bbpll.h header files.
  */
-#define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \
+#define REGI2C_WRITE_MASK(block, reg_add, indata) \
       rom_i2c_writeReg_Mask(block, block##_HOSTID,  reg_add,  reg_add##_MSB,  reg_add##_LSB,  indata)
 
-#define I2C_READREG_MASK_RTC(block, reg_add) \
+#define REGI2C_READ_MASK(block, reg_add) \
       rom_i2c_readReg_Mask(block, block##_HOSTID,  reg_add,  reg_add##_MSB,  reg_add##_LSB)
 
-#define I2C_WRITEREG_RTC(block, reg_add, indata) \
+#define REGI2C_WRITE(block, reg_add, indata) \
       rom_i2c_writeReg(block, block##_HOSTID,  reg_add, indata)
 
-#define I2C_READREG_RTC(block, reg_add) \
+#define REGI2C_READ(block, reg_add) \
       rom_i2c_readReg(block, block##_HOSTID,  reg_add)
 
 
diff --git a/components/soc/src/esp32/rtc_clk.c b/components/soc/src/esp32/rtc_clk.c
index e0c74ec722..574cf6d0f7 100644
--- a/components/soc/src/esp32/rtc_clk.c
+++ b/components/soc/src/esp32/rtc_clk.c
@@ -26,7 +26,7 @@
 #include "soc/dport_reg.h"
 #include "soc/efuse_periph.h"
 #include "soc/apb_ctrl_reg.h"
-#include "i2c_rtc_clk.h"
+#include "regi2c_ctrl.h"
 #include "soc_log.h"
 #include "sdkconfig.h"
 #include "xtensa/core-macros.h"
@@ -253,21 +253,21 @@ void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm
             sdm1 = 0;
             sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV0;
         }
-        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM2, sdm2);
-        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM0, sdm0);
-        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM1, sdm1);
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1);
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, sdm_stop_val_2);
-        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div);
+        REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM2, sdm2);
+        REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM0, sdm0);
+        REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM1, sdm1);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_SDM_STOP, sdm_stop_val_2);
+        REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div);
 
         /* calibration */
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_1);
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_2);
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_3);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_1);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_2);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_3);
 
         /* wait for calibration end */
-        while (!(I2C_READREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_CAL_END))) {
-            /* use ets_delay_us so the RTC bus doesn't get flooded */
+        while (!(REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_CAL_END))) {
+            /* use esp_rom_delay_us so the RTC bus doesn't get flooded */
             ets_delay_us(1);
         }
     }
@@ -356,8 +356,8 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
                 bw = 0;
                 break;
         }
-        I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_320M);
-        I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_320M);
+        REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_320M);
+        REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_320M);
     } else {
         /* Raise the voltage */
         REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M);
@@ -397,16 +397,16 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
                 bw = 0;
                 break;
         }
-        I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_480M);
-        I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_480M);
+        REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_480M);
+        REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_480M);
     }
 
     uint8_t i2c_bbpll_lref  = (lref << 7) | (div10_8 << 4) | (div_ref);
     uint8_t i2c_bbpll_div_7_0 = div7_0;
     uint8_t i2c_bbpll_dcur = (bw << 6) | dcur;
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_LREF, i2c_bbpll_lref);
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_LREF, i2c_bbpll_lref);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
     uint32_t delay_pll_en = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) ?
             DELAY_PLL_ENABLE_WITH_150K : DELAY_PLL_ENABLE_WITH_32K;
     ets_delay_us(delay_pll_en);
@@ -465,11 +465,11 @@ static void rtc_clk_bbpll_enable(void)
              RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
 
     /* reset BBPLL configuration */
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, BBPLL_IR_CAL_DELAY_VAL);
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL);
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL);
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL);
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, BBPLL_BBADC_CAL_7_0_VAL);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, BBPLL_IR_CAL_DELAY_VAL);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, BBPLL_BBADC_CAL_7_0_VAL);
 }
 
 /**
diff --git a/components/soc/src/esp32/rtc_clk_init.c b/components/soc/src/esp32/rtc_clk_init.c
index d1f128ffa3..6416f48cff 100644
--- a/components/soc/src/esp32/rtc_clk_init.c
+++ b/components/soc/src/esp32/rtc_clk_init.c
@@ -25,7 +25,7 @@
 #include "soc/sens_periph.h"
 #include "soc/efuse_periph.h"
 #include "soc/apb_ctrl_reg.h"
-#include "i2c_rtc_clk.h"
+#include "regi2c_ctrl.h"
 #include "soc_log.h"
 #include "sdkconfig.h"
 #include "xtensa/core-macros.h"
diff --git a/components/soc/src/esp32s2/CMakeLists.txt b/components/soc/src/esp32s2/CMakeLists.txt
index ddc9b90745..d87dd10bed 100644
--- a/components/soc/src/esp32s2/CMakeLists.txt
+++ b/components/soc/src/esp32s2/CMakeLists.txt
@@ -2,7 +2,7 @@ set(srcs "adc_hal.c"
         "dac_hal.c"
         "brownout_hal.c"
         "rtc_clk.c"
-        "i2c_rtc_clk.c"
+        "regi2c_ctrl.c"
         "rtc_clk_init.c"
         "rtc_init.c"
         "rtc_pm.c"
diff --git a/components/soc/src/esp32s2/brownout_hal.c b/components/soc/src/esp32s2/brownout_hal.c
index 74e60e9ede..0658304d65 100644
--- a/components/soc/src/esp32s2/brownout_hal.c
+++ b/components/soc/src/esp32s2/brownout_hal.c
@@ -16,13 +16,13 @@
 #include "hal/brownout_hal.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/rtc_cntl_reg.h"
-#include "i2c_rtc_clk.h"
-#include "i2c_brownout.h"
+#include "regi2c_ctrl.h"
+#include "regi2c_brownout.h"
 
 
 void brownout_hal_config(const brownout_hal_config_t *cfg)
 {
-    I2C_WRITEREG_MASK_RTC(I2C_BOD, I2C_BOD_THRESHOLD, cfg->threshold);
+    REGI2C_WRITE_MASK(I2C_BOD, I2C_BOD_THRESHOLD, cfg->threshold);
     typeof(RTCCNTL.brown_out) brown_out_reg = {
         .out2_ena = 1,
         .int_wait = 0x002,
diff --git a/components/soc/src/esp32s2/include/hal/adc_ll.h b/components/soc/src/esp32s2/include/hal/adc_ll.h
index 415f105064..95daff46f2 100644
--- a/components/soc/src/esp32s2/include/hal/adc_ll.h
+++ b/components/soc/src/esp32s2/include/hal/adc_ll.h
@@ -7,7 +7,7 @@
 #include "soc/apb_saradc_reg.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/rtc_cntl_reg.h"
-#include "i2c_rtc_clk.h"
+#include "regi2c_ctrl.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -100,10 +100,10 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
 {
     /* Should be called before writing I2C registers. */
     SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
-    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
-    SET_PERI_REG_MASK(ADC_ANA_CONFIG2_REG, BIT(16));
+    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M);
+    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
 
-    I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
 }
 
 /**
@@ -1138,23 +1138,23 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t
     /* Should be called before writing I2C registers. */
     CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M);
     SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
-    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
-    SET_PERI_REG_MASK(ADC_ANA_CONFIG2_REG, BIT(16));
+    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M);
+    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
 
     /* Enable/disable internal connect GND (for calibration). */
     if (adc_n == ADC_NUM_1) {
-        I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 4);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 4);
         if (internal_gnd) {
-            I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1);
         } else {
-            I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
         }
     } else {
-        I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 4);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 4);
         if (internal_gnd) {
-            I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 1);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 1);
         } else {
-            I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0);
         }
     }
 }
@@ -1167,9 +1167,9 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t
 static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n)
 {
     if (adc_n == ADC_NUM_1) {
-        I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
     } else {
-        I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0);
     }
 }
 
@@ -1186,15 +1186,15 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
     uint8_t lsb = param & 0xFF;
     /* Should be called before writing I2C registers. */
     SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
-    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
-    SET_PERI_REG_MASK(ADC_ANA_CONFIG2_REG, BIT(16));
+    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M);
+    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
 
     if (adc_n == ADC_NUM_1) {
-        I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
-        I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
     } else {
-        I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, msb);
-        I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, lsb);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, msb);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, lsb);
     }
 }
 /* Temp code end. */
@@ -1214,20 +1214,20 @@ static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, b
 {
     /* Should be called before writing I2C registers. */
     SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
-    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
-    SET_PERI_REG_MASK(ADC_ANA_CONFIG2_REG, BIT(16));
+    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M);
+    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
 
     if (en) {
         if (adc == ADC_NUM_1) {
             /* Config test mux to route v_ref to ADC1 Channels */
-            I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1);
-            I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0);
-            I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 1);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 1);
         } else {
             /* Config test mux to route v_ref to ADC2 Channels */
-            I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
-            I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 1);
-            I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 1);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
         }
         //in sleep force to use rtc to control ADC
         SENS.sar_meas2_mux.sar2_rtc_force = 1;
@@ -1238,8 +1238,8 @@ static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, b
         //set en_pad for ADC2 channels (bits 0x380)
         SENS.sar_meas2_ctrl2.sar2_en_pad = 1 << channel;
     } else {
-        I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0);
-        I2C_WRITEREG_MASK_RTC(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
         SENS.sar_meas2_mux.sar2_rtc_force = 0;
         //set sar2_en_test
         SENS.sar_meas2_ctrl1.sar2_en_test = 0;
diff --git a/components/soc/src/esp32s2/i2c_rtc_clk.c b/components/soc/src/esp32s2/regi2c_ctrl.c
similarity index 99%
rename from components/soc/src/esp32s2/i2c_rtc_clk.c
rename to components/soc/src/esp32s2/regi2c_ctrl.c
index e6af0b2bcb..88ec4fa0f9 100644
--- a/components/soc/src/esp32s2/i2c_rtc_clk.c
+++ b/components/soc/src/esp32s2/regi2c_ctrl.c
@@ -15,8 +15,8 @@
 #include "esp_err.h"
 #include "soc/soc.h"
 #include "soc/apb_ctrl_reg.h"
-#include "i2c_rtc_clk.h"
-#include "i2c_brownout.h"
+#include "regi2c_ctrl.h"
+#include "regi2c_brownout.h"
 #include "esp_log.h"
 
 #define I2C_RTC_WIFI_CLK_EN (APB_CTRL_WIFI_CLK_EN_REG)
diff --git a/components/soc/src/esp32s2/i2c_rtc_clk.h b/components/soc/src/esp32s2/regi2c_ctrl.h
similarity index 78%
rename from components/soc/src/esp32s2/i2c_rtc_clk.h
rename to components/soc/src/esp32s2/regi2c_ctrl.h
index 11d6af18d9..68d05f7bda 100644
--- a/components/soc/src/esp32s2/i2c_rtc_clk.h
+++ b/components/soc/src/esp32s2/regi2c_ctrl.h
@@ -14,10 +14,11 @@
 
 #pragma once
 
-#include "i2c_apll.h"
-#include "i2c_bbpll.h"
-#include "i2c_ulp.h"
-#include "i2c_saradc.h"
+#include <stdint.h>
+#include "regi2c_apll.h"
+#include "regi2c_bbpll.h"
+#include "regi2c_ulp.h"
+#include "regi2c_saradc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -31,6 +32,11 @@ extern "C" {
 #define I2C_APLL_M      (BIT(14))
 /* Clear to enable BBPLL */
 #define I2C_BBPLL_M     (BIT(17))
+/* Clear to enable SAR */
+#define I2C_SAR_M       (BIT(18))
+
+#define ANA_CONFIG2_REG 0x6000E048
+#define ANA_SAR_CFG2_M  (BIT(16))
 
 /* Read/Write internal control bus */
 uint8_t i2c_rtc_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add);
@@ -40,18 +46,18 @@ void i2c_rtc_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uin
 void i2c_rtc_init(void);
 
 /* Convenience macros for the above functions, these use register definitions
- * from i2c_apll.h/i2c_bbpll.h header files.
+ * from regi2c_apll.h/regi2c_bbpll.h header files.
  */
-#define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \
+#define REGI2C_WRITE_MASK(block, reg_add, indata) \
       i2c_rtc_write_reg_mask(block, block##_HOSTID,  reg_add,  reg_add##_MSB,  reg_add##_LSB,  indata)
 
-#define I2C_READREG_MASK_RTC(block, reg_add) \
+#define REGI2C_READ_MASK(block, reg_add) \
       i2c_rtc_read_reg_mask(block, block##_HOSTID,  reg_add,  reg_add##_MSB,  reg_add##_LSB)
 
-#define I2C_WRITEREG_RTC(block, reg_add, indata) \
+#define REGI2C_WRITE(block, reg_add, indata) \
       i2c_rtc_write_reg(block, block##_HOSTID,  reg_add, indata)
 
-#define I2C_READREG_RTC(block, reg_add) \
+#define REGI2C_READ(block, reg_add) \
       i2c_rtc_read_reg(block, block##_HOSTID,  reg_add)
 
 #ifdef __cplusplus
diff --git a/components/soc/src/esp32s2/rtc_clk.c b/components/soc/src/esp32s2/rtc_clk.c
index 4d59adf5c0..d558bb97d4 100644
--- a/components/soc/src/esp32s2/rtc_clk.c
+++ b/components/soc/src/esp32s2/rtc_clk.c
@@ -29,7 +29,7 @@
 #include "soc/dport_reg.h"
 #include "soc/efuse_reg.h"
 #include "soc/syscon_reg.h"
-#include "i2c_rtc_clk.h"
+#include "regi2c_ctrl.h"
 #include "soc_log.h"
 #include "rtc_clk_common.h"
 #include "sdkconfig.h"
@@ -133,21 +133,21 @@ void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm
     REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU, enable ? 1 : 0);
 
     if (enable) {
-        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM2, sdm2);
-        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM0, sdm0);
-        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM1, sdm1);
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1);
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_2_REV1);
-        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div);
+        REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM2, sdm2);
+        REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM0, sdm0);
+        REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM1, sdm1);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_2_REV1);
+        REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div);
 
         /* calibration */
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_1);
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_2);
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_3);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_1);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_2);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_3);
 
         /* wait for calibration end */
-        while (!(I2C_READREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_CAL_END))) {
-            /* use ets_delay_us so the RTC bus doesn't get flooded */
+        while (!(REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_CAL_END))) {
+            /* use esp_rom_delay_us so the RTC bus doesn't get flooded */
             ets_delay_us(1);
         }
     }
@@ -254,7 +254,7 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
         dr3 = 0;
         dchgp = 5;
         dcur = 4;
-        I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6B);
+        REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6B);
     } else {
         /* Clear this register to let the digital part know 320M PLL is used */
         CLEAR_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL);
@@ -265,23 +265,23 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
         dr3 = 0;
         dchgp = 5;
         dcur = 5;
-        I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69);
+        REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69);
     }
     uint8_t i2c_bbpll_lref  = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref);
     uint8_t i2c_bbpll_div_7_0 = div7_0;
     uint8_t i2c_bbpll_dcur = (2 << I2C_BBPLL_OC_DLREF_SEL_LSB ) | (1 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
-    I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
-    I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
+    REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
+    REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
 
     // Enable calibration by software
-    I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_ENX_CAP, 1);
+    REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_IR_CAL_ENX_CAP, 1);
     for (int ext_cap = 0; ext_cap < 16; ext_cap++) {
         uint8_t cal_result;
-        I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, ext_cap);
-        cal_result = I2C_READREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OR_CAL_CAP);
+        REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, ext_cap);
+        cal_result = REGI2C_READ_MASK(I2C_BBPLL, I2C_BBPLL_OR_CAL_CAP);
         if (cal_result == 0) {
             break;
         }
diff --git a/components/soc/src/esp32s2/rtc_clk_init.c b/components/soc/src/esp32s2/rtc_clk_init.c
index 6480e593b1..decbe67dab 100644
--- a/components/soc/src/esp32s2/rtc_clk_init.c
+++ b/components/soc/src/esp32s2/rtc_clk_init.c
@@ -24,7 +24,7 @@
 #include "soc/sens_periph.h"
 #include "soc/efuse_periph.h"
 #include "soc/apb_ctrl_reg.h"
-#include "i2c_rtc_clk.h"
+#include "regi2c_ctrl.h"
 #include "soc_log.h"
 #include "sdkconfig.h"
 #include "xtensa/core-macros.h"
diff --git a/components/soc/src/esp32s2/rtc_init.c b/components/soc/src/esp32s2/rtc_init.c
index fa7a7aa67f..0753f63ac4 100644
--- a/components/soc/src/esp32s2/rtc_init.c
+++ b/components/soc/src/esp32s2/rtc_init.c
@@ -21,7 +21,7 @@
 #include "soc/gpio_reg.h"
 #include "soc/spi_mem_reg.h"
 #include "soc/extmem_reg.h"
-#include "i2c_rtc_clk.h"
+#include "regi2c_ctrl.h"
 #include "soc_log.h"
 
 static const char *TAG = "rtc_init";
@@ -179,13 +179,13 @@ void rtc_init(rtc_config_t cfg)
         rtc_clk_cpu_freq_set_xtal();
 
 
-        I2C_WRITEREG_MASK_RTC(I2C_ULP, I2C_ULP_IR_RESETB, 0);
-        I2C_WRITEREG_MASK_RTC(I2C_ULP, I2C_ULP_IR_RESETB, 1);
+        REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0);
+        REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1);
         bool odone_flag = 0;
         bool bg_odone_flag = 0;
         while(1) {
-            odone_flag = I2C_READREG_MASK_RTC(I2C_ULP, I2C_ULP_O_DONE_FLAG);
-            bg_odone_flag = I2C_READREG_MASK_RTC(I2C_ULP, I2C_ULP_BG_O_DONE_FLAG);
+            odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_O_DONE_FLAG);
+            bg_odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_BG_O_DONE_FLAG);
             cycle1 = rtc_time_get();
             if (odone_flag && bg_odone_flag)
                 break;