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resolve comments, to squash

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This commit is contained in:
armando
2025-07-09 14:51:08 +08:00
committed by Armando (Dou Yiwen)
parent dfb0662de2
commit bcf04e356b
16 changed files with 82 additions and 83 deletions
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2
components/bootloader/subproject/CMakeLists.txt
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@@ -70,7 +70,7 @@ set(LD_DEFAULT_PATH "${CMAKE_CURRENT_SOURCE_DIR}/main/ld/${IDF_TARGET}")
idf_build_set_property(BOOTLOADER_LINKER_SCRIPT "${LD_DEFAULT_PATH}/bootloader.rom.ld" APPEND)
project(bootloader)
if(CONFIG_ESP32P4_REV_MIN_200)
target_linker_script("__idf_main" INTERFACE "${LD_DEFAULT_PATH}/bootloader.eco5.ld")
target_linker_script("__idf_main" INTERFACE "${LD_DEFAULT_PATH}/bootloader.rev2.ld")
else()
target_linker_script("__idf_main" INTERFACE "${LD_DEFAULT_PATH}/bootloader.ld")
endif()

68
components/bootloader/subproject/main/ld/esp32p4/bootloader.eco5.ld → components/bootloader/subproject/main/ld/esp32p4/bootloader.rev2.ld
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@@ -287,38 +287,38 @@ SECTIONS
/**
* Appendix: Memory Usage of ROM bootloader
*
* 0x4ff296b8 ------------------> _dram0_0_start
* | |
* | |
* | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h
* | |
* | |
* 0x4ff3afc0 ------------------> __stack_sentry
* | |
* | | 2. Startup pro cpu stack (freed when IDF app is running)
* | |
* 0x4ff3cfc0 ------------------> __stack (pro cpu)
* | |
* | | Startup app cpu stack
* | |
* 0x4ff3efc0 ------------------> __stack_app (app cpu)
* | |
* | |
* | | 3. Shared memory only used in startup code or nonos/early boot*
* | | (can be freed when IDF runs)
* | |
* | |
* 0x4ff3fba4 ------------------> _dram0_rtos_reserved_start
* | |
* | |
* | | 4. Shared memory used in startup code and when IDF runs
* | |
* | |
* 0x4ff3ff94 ------------------> _dram0_rtos_reserved_end
* | |
* 0x4ff3ffc8 ------------------> _data_start_interface
* | |
* | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
* | |
* 0x4ff40000 ------------------> _data_end_interface
* 0x4ffa96b8 ------------------> _dram0_0_start
* | |
* | |
* | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h
* | |
* | |
* 0x4ffbafc0 ------------------> __stack_sentry
* | |
* | | 2. Startup pro cpu stack (freed when IDF app is running)
* | |
* 0x4ffbcfc0 ------------------> __stack (pro cpu)
* | |
* | | Startup app cpu stack
* | |
* 0x4ffbefc0 ------------------> __stack_app (app cpu)
* | |
* | |
* | | 3. Shared memory only used in startup code or nonos/early boot*
* | | (can be freed when IDF runs)
* | |
* | |
* 0x4ffbfbb0 ------------------> _dram0_rtos_reserved_start
* | |
* | |
* | | 4. Shared memory used in startup code and when IDF runs
* | |
* | |
* 0x4ffbffa4 ------------------> _dram0_rtos_reserved_end
* | |
* 0x4ffbffc8 ------------------> _data_start_interface
* | |
* | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
* | |
* 0x4ffc0000 ------------------> _data_end_interface
*/

4
components/bootloader_support/src/esp_image_format.c
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@@ -387,8 +387,8 @@ err:
}
#ifdef BOOTLOADER_BUILD
#if CONFIG_ESP32P4_REV_MIN_200 // TODO: IDF-13410
#define ROM_STACK_START (SOC_ROM_STACK_START_ECO5)
#if CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V2
#define ROM_STACK_START (SOC_ROM_STACK_START_REV2)
#else
#define ROM_STACK_START (SOC_ROM_STACK_START)
#endif

4
components/esp_hw_support/Kconfig
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@@ -264,7 +264,7 @@ menu "Hardware Settings"
config ESP_BRINGUP_BYPASS_CPU_CLK_SETTING
bool
default y if !SOC_CLK_TREE_SUPPORTED
default y if ESP32P4_REV_MIN_200
default y if ESP32P4_REV_MIN_200 # TODO: IDF-13574
default n
help
This option is only used for new chip bringup, when
@@ -274,7 +274,7 @@ menu "Hardware Settings"
config ESP_BRINGUP_BYPASS_RANDOM_SETTING
bool
default y if !SOC_RNG_SUPPORTED
default y if ESP32P4_REV_MIN_200
default y if ESP32P4_REV_MIN_200 # TODO: IDF-13574
default n
help
This option is only used for new chip bringup, when

22
components/esp_hw_support/port/esp32p4/Kconfig.hw_support
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@@ -1,12 +1,13 @@
config ESP32P4_REV_LESS_V2_SUPPORT
bool "Support ESP32-P4 revisions <2.0"
comment "NOTE! Support of ESP32-P4 rev. <2.0 and >=2.0 is mutually exclusive"
comment "Read the help text of the option below for explanation"
config ESP32P4_SELECTS_REV_LESS_V2
bool "Select ESP32-P4 revisions <2.0 (No >=2.x Support)"
default y
help
Enable this option to support ESP32-P4 revisions 0.x and 1.x.
Select this option to support ESP32-P4 revisions 0.x and 1.x.
Revision 2.0 and revisions less than 2.0 have huge hardware difference.
comment "NOTE! Support of ESP32-P4 rev. <2.0 and >=2.0 is mutually exclusive"
comment "Read the help text of the option below for explanation"
Revisions higher than 2.0 (included) is not compatible with 0.x and 1.x.
choice ESP32P4_REV_MIN
prompt "Minimum Supported ESP32-P4 Revision"
@@ -20,14 +21,17 @@ choice ESP32P4_REV_MIN
this will also help to reduce binary size.
config ESP32P4_REV_MIN_0
depends on ESP32P4_SELECTS_REV_LESS_V2
bool "Rev v0.0"
config ESP32P4_REV_MIN_1
depends on ESP32P4_SELECTS_REV_LESS_V2
bool "Rev v0.1"
config ESP32P4_REV_MIN_100
depends on ESP32P4_SELECTS_REV_LESS_V2
bool "Rev v1.0"
config ESP32P4_REV_MIN_200
bool "Rev v2.0"
depends on !ESP32P4_REV_LESS_V2_SUPPORT
depends on !ESP32P4_SELECTS_REV_LESS_V2
select ESPTOOLPY_NO_STUB if (IDF_ENV_FPGA || IDF_ENV_BRINGUP)
endchoice
@@ -36,7 +40,7 @@ config ESP32P4_REV_MIN_FULL
default 0 if ESP32P4_REV_MIN_0
default 1 if ESP32P4_REV_MIN_1
default 100 if ESP32P4_REV_MIN_100
default 0 if ESP32P4_REV_MIN_200 # To be updated to 200 when chip efuse is burnt
default 0 if ESP32P4_REV_MIN_200 # TODO: IDF-13410. To be updated to 200 when chip efuse is burnt
config ESP_REV_MIN_FULL
int
@@ -54,7 +58,7 @@ config ESP_REV_MIN_FULL
config ESP32P4_REV_MAX_FULL
int
default 299
default 199 #TODO: IDF-13574
# keep in sync the "Maximum Supported Revision" description with this value
config ESP_REV_MAX_FULL

5
components/esp_system/CMakeLists.txt
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@@ -151,9 +151,8 @@ if(NOT BOOTLOADER_BUILD)
endif()
endif()
# Since P4 ECO5, the SRAM is contiguous
# TODO: IDF-13410. Update to (CONFIG_ESP32P4_REV_MIN_FULL GREATER_EQUAL 200) when chip efuse is correct.
if(CONFIG_SOC_MEM_NON_CONTIGUOUS_SRAM OR (CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_REV_MIN_200))
# For P4, since P4 REV2, the SRAM is contiguous
if(CONFIG_ESP32P4_SELECTS_REV_LESS_V2)
target_link_options(${COMPONENT_LIB} INTERFACE "-Wl,--enable-non-contiguous-regions")
endif()

1
components/esp_system/fpga_overrides_clk.c
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@@ -56,6 +56,7 @@ void esp_rtc_init(void)
{
#if SOC_PMU_SUPPORTED
#if CONFIG_ESP32P4_REV_MIN_200
//TODO: IDF-13453
ESP_EARLY_LOGW(TAG, "pmu_init not supported\n");
#else
pmu_init();

6
components/esp_system/ld/esp32p4/memory.ld.in
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@@ -71,11 +71,11 @@ MEMORY
* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
* Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
*/
#if CONFIG_ESP32P4_REV_MIN_200 // TODO: IDF-13410
sram_seg (RWX) : org = SRAM_START, len = SRAM_SIZE
#else
#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
sram_low (RWX) : org = SRAM_LOW_START, len = SRAM_LOW_SIZE
sram_high (RW) : org = SRAM_HIGH_START, len = SRAM_HIGH_SIZE
#else
sram_seg (RWX) : org = SRAM_START, len = SRAM_SIZE
#endif
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS

0
components/esp_system/ld/esp32p4/sections.eco5.ld.in → components/esp_system/ld/esp32p4/sections.rev2.ld.in
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2
components/esp_system/ld/ld.cmake
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@@ -49,7 +49,7 @@ target_linker_script(${COMPONENT_LIB} INTERFACE "${ld_out_path}")
# Generate sections.ld.in and pass it through linker script generator
if(CONFIG_ESP32P4_REV_MIN_200) # TODO: IDF-13410
preprocess_linker_file("sections.eco5.ld.in" "sections.ld.in" ld_out_path)
preprocess_linker_file("sections.rev2.ld.in" "sections.ld.in" ld_out_path)
else()
preprocess_linker_file("sections.ld.in" "sections.ld.in" ld_out_path)
endif()

13
components/esp_system/port/cpu_start.c
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@@ -122,18 +122,13 @@
#include "esp_private/startup_internal.h"
#include "esp_private/system_internal.h"
// TODO: IDF-13410. Update to (CONFIG_ESP32P4_REV_MIN_FULL GREATER_EQUAL 200) when chip efuse is correct.
#if SOC_MEM_NON_CONTIGUOUS_SRAM || (CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_ESP32P4_REV_MIN_200)
#define MEM_NON_CONTIGUOUS_SRAM 1
#endif
#if MEM_NON_CONTIGUOUS_SRAM
#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
extern int _bss_start_low, _bss_start_high;
extern int _bss_end_low, _bss_end_high;
#else
extern int _bss_start;
extern int _bss_end;
#endif // MEM_NON_CONTIGUOUS_SRAM
#endif // CONFIG_ESP32P4_SELECTS_REV_LESS_V2
extern int _rtc_bss_start;
extern int _rtc_bss_end;
#if CONFIG_BT_LE_RELEASE_IRAM_SUPPORTED
@@ -421,12 +416,12 @@ FORCE_INLINE_ATTR IRAM_ATTR void get_reset_reason(soc_reset_reason_t *rst_reas)
FORCE_INLINE_ATTR IRAM_ATTR void init_bss(const soc_reset_reason_t *rst_reas)
{
#if MEM_NON_CONTIGUOUS_SRAM
#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
memset(&_bss_start_low, 0, (uintptr_t)&_bss_end_low - (uintptr_t)&_bss_start_low);
memset(&_bss_start_high, 0, (uintptr_t)&_bss_end_high - (uintptr_t)&_bss_start_high);
#else
memset(&_bss_start, 0, (uintptr_t)&_bss_end - (uintptr_t)&_bss_start);
#endif // MEM_NON_CONTIGUOUS_SRAM
#endif // CONFIG_ESP32P4_SELECTS_REV_LESS_V2
#if CONFIG_BT_LE_RELEASE_IRAM_SUPPORTED
// Clear Bluetooth bss

26
components/heap/port/esp32p4/memory_layout.c
View File

@@ -74,18 +74,18 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
/**
* Register the shared buffer area of the last memory block into the heap during heap initialization
*/
#if CONFIG_ESP32P4_REV_MIN_200 // TODO: IDF-13410
#define ROM_STACK_START (SOC_ROM_STACK_START_ECO5)
#define APP_USABLE_DIRAM_END (ROM_STACK_START - SOC_ROM_STACK_SIZE) // 0x4ffbcfc0 - 0x2000 = 0x4ffbafc0
#define STARTUP_DATA_SIZE (SOC_DRAM_HIGH - APP_USABLE_DIRAM_END) // 0x4ffc0000 - 0x4ffbafc0 = 0x65040 / 0x45040 / 0x5040
#define SOC_DRAM_USABLE_LOW (SOC_DRAM_LOW + CONFIG_CACHE_L2_CACHE_SIZE)
#define SOC_IRAM_USABLE_LOW (SOC_IRAM_LOW + CONFIG_CACHE_L2_CACHE_SIZE)
#else
#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
#define ROM_STACK_START (SOC_ROM_STACK_START)
#define APP_USABLE_DIRAM_END (ROM_STACK_START - SOC_ROM_STACK_SIZE) // 0x4ff3cfc0 - 0x2000 = 0x4ff3afc0
#define STARTUP_DATA_SIZE (SOC_DRAM_HIGH - CONFIG_CACHE_L2_CACHE_SIZE - APP_USABLE_DIRAM_END) // 0x4ffc0000 - 0x20000/0x40000/0x80000 - 0x4ff3afc0 = 0x65040 / 0x45040 / 0x5040
#define SOC_DRAM_USABLE_LOW (SOC_DRAM_LOW)
#define SOC_IRAM_USABLE_LOW (SOC_IRAM_LOW)
#else
#define ROM_STACK_START (SOC_ROM_STACK_START_REV2)
#define APP_USABLE_DIRAM_END (ROM_STACK_START - SOC_ROM_STACK_SIZE) // 0x4ffbcfc0 - 0x2000 = 0x4ffbafc0
#define STARTUP_DATA_SIZE (SOC_DRAM_HIGH - APP_USABLE_DIRAM_END) // 0x4ffc0000 - 0x4ffbafc0 = 0x65040 / 0x45040 / 0x5040
#define SOC_DRAM_USABLE_LOW (SOC_DRAM_LOW + CONFIG_CACHE_L2_CACHE_SIZE)
#define SOC_IRAM_USABLE_LOW (SOC_IRAM_LOW + CONFIG_CACHE_L2_CACHE_SIZE)
#endif
#if CONFIG_ULP_COPROC_ENABLED
@@ -108,10 +108,10 @@ const soc_memory_region_t soc_memory_regions[] = {
const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
#if CONFIG_ESP32P4_REV_MIN_200 // TODO: IDF-13410
extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end;
#else
#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
extern int _data_start_low, _data_start_high, _heap_start_low, _heap_start_high, _iram_start, _iram_end, _rtc_force_slow_end;
#else
extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end;
#endif
extern int _tcm_text_start, _tcm_data_end;
extern int _rtc_reserved_start, _rtc_reserved_end;
@@ -124,11 +124,11 @@ extern int _rtc_ulp_memory_start;
*/
// Static data region. DRAM used by data+bss and possibly rodata
#if CONFIG_ESP32P4_REV_MIN_200 // TODO: IDF-13410
SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data_high);
#else
#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start_low, (intptr_t)&_heap_start_low, dram_data_low);
SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start_high, (intptr_t)&_heap_start_high, dram_data_high);
#else
SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data_high)
#endif
// Target has a shared D/IRAM virtual address, no need to calculate I_D_OFFSET like previous chips

2
components/heap/port/memory_layout_utils.c
View File

@@ -60,7 +60,7 @@ static void s_prepare_reserved_regions(soc_reserved_region_t *reserved, size_t c
/* Get the ROM layout to find which part of DRAM is reserved */
const ets_rom_layout_t *layout = ets_rom_layout_p;
reserved[0].start = (intptr_t)layout->dram0_rtos_reserved_start;
#if SOC_DIRAM_ROM_RESERVE_HIGH && !CONFIG_ESP32P4_REV_MIN_200 // TODO: IDF-13410
#if SOC_DIRAM_ROM_RESERVE_HIGH && CONFIG_ESP32P4_SELECTS_REV_LESS_V2
reserved[0].end = SOC_DIRAM_ROM_RESERVE_HIGH;
#else
reserved[0].end = SOC_DIRAM_DRAM_HIGH;

6
components/riscv/include/esp_private/interrupt_clic.h
View File

@@ -46,7 +46,7 @@ extern "C" {
#define MTVT_CSR 0x307
#if CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_ESP32P4_REV_MIN_200 // TODO: IDF-13410
#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V2
/**
* The ESP32-P4 and the beta version of the ESP32-C5 implement a non-standard version of the CLIC:
@@ -56,9 +56,9 @@ extern "C" {
#define INTTHRESH_STANDARD 0
#define MINTSTATUS_CSR 0x346
#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_ESP32P4_REV_MIN_200 // TODO: IDF-13410
#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H4 || !CONFIG_ESP32P4_SELECTS_REV_LESS_V2
/* The ESP32-C5 (MP), C61, H4 and P4 (since ECO5) use the standard CLIC specification, for example, it defines the mintthresh CSR */
/* The ESP32-C5 (MP), C61, H4 and P4 (since REV2) use the standard CLIC specification, for example, it defines the mintthresh CSR */
#define INTTHRESH_STANDARD 1
#define MINTSTATUS_CSR 0xFB1
#define MINTTHRESH_CSR 0x347

2
components/soc/esp32p4/include/soc/soc.h
View File

@@ -224,7 +224,7 @@
#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
// Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START_ECO5 0x4ffbcfc0
#define SOC_ROM_STACK_START_REV2 0x4ffbcfc0
#define SOC_ROM_STACK_START 0x4ff3cfc0
#define SOC_ROM_STACK_SIZE 0x2000

2
tools/test_apps/build_system/.build-test-rules.yml
View File

@@ -18,4 +18,4 @@ tools/test_apps/build_system/embed_test:
tools/test_apps/build_system/ld_non_contiguous_memory:
disable:
- if: SOC_MEM_NON_CONTIGUOUS_SRAM != 1 # TODO: IDF-13411, since P4 ECO5, the SRAM is contiguous
- if: SOC_MEM_NON_CONTIGUOUS_SRAM != 1 # TODO: IDF-13411, since P4 REV2, the SRAM is contiguous