From 326d76ebdff7d188c276b338b47076a1134d297b Mon Sep 17 00:00:00 2001 From: Armando Date: Tue, 26 Jan 2021 20:18:52 +0800 Subject: [PATCH 1/6] spi: add dma channel auto-alloc feature on esp32 --- components/driver/include/driver/spi_common.h | 12 +- .../include/driver/spi_common_internal.h | 22 +--- components/driver/include/driver/spi_slave.h | 10 +- .../driver/include/driver/spi_slave_hd.h | 2 +- components/driver/spi_common.c | 104 +++++++++++++----- components/driver/spi_slave.c | 28 ++--- components/driver/spi_slave_hd.c | 26 +++-- 7 files changed, 120 insertions(+), 84 deletions(-) diff --git a/components/driver/include/driver/spi_common.h b/components/driver/include/driver/spi_common.h index da12bb36ae..cbb09ca7f8 100644 --- a/components/driver/include/driver/spi_common.h +++ b/components/driver/include/driver/spi_common.h @@ -105,11 +105,11 @@ typedef struct { * * @param host_id SPI peripheral that controls this bus * @param bus_config Pointer to a spi_bus_config_t struct specifying how the host should be initialized - * @param dma_chan Either channel 1 or 2, or 0 in the case when no DMA is required. Selecting a DMA channel - * for a SPI bus allows transfers on the bus to have sizes only limited by the amount of - * internal memory. Selecting no DMA channel (by passing the value 0) limits the amount of - * bytes transfered to a maximum of 64. Set to 0 if only the SPI flash uses - * this bus. + * @param dma_chan -1: auto dma allocate mode; 0: non-dma mode; 1 or 2: assign a specific DMA channel; + * Selecting a DMA channel for an SPI bus allows transfers on the bus to have sizes only + * limited by the amount of internal memory. Selecting no DMA channel (by passing the + * value 0) limits the amount of bytes transfered to a maximum of 64. Set to 0 if only + * the SPI flash uses this bus. Set -1 to let the driver to allocate the DMA channel. * * @warning If a DMA channel is selected, any transmit and receive buffer used should be allocated in * DMA-capable memory. @@ -120,7 +120,7 @@ typedef struct { * * @return * - ESP_ERR_INVALID_ARG if configuration is invalid - * - ESP_ERR_INVALID_STATE if host already is in use + * - ESP_ERR_INVALID_STATE if host already is in use or DMA channel is not available * - ESP_ERR_NO_MEM if out of memory * - ESP_OK on success */ diff --git a/components/driver/include/driver/spi_common_internal.h b/components/driver/include/driver/spi_common_internal.h index 23a2b90050..82d5b73c9d 100644 --- a/components/driver/include/driver/spi_common_internal.h +++ b/components/driver/include/driver/spi_common_internal.h @@ -115,19 +115,6 @@ bool spicommon_periph_in_use(spi_host_device_t host); */ bool spicommon_periph_free(spi_host_device_t host); -/** - * @brief Try to claim a SPI DMA channel - * - * Call this if your driver wants to use SPI with a DMA channnel. - * - * @param dma_chan channel to claim - * - * @note This public API is deprecated. - * - * @return True if success; false otherwise. - */ -bool spicommon_dma_chan_claim(int dma_chan); - /** * @brief Check whether the spi DMA channel is in use. * @@ -151,12 +138,13 @@ bool spicommon_dma_chan_in_use(int dma_chan); bool spicommon_dma_chan_free(int dma_chan); /** - * @brief Connect SPI and DMA peripherals + * @brief Try to claim a SPI DMA channel and connect it with SPI peripherals * - * @param host SPI peripheral - * @param dma_chan DMA channel + * @param host_id SPI host ID + * @param dma_chan -1: auto dma allocate mode; 0: non-dma mode; 1 or 2: assign a specific DMA channel; + * @param[out] out_actual_dma_chan Actual DMA channel (if you choose to assign a specific DMA channel, this will be the channel you assigned before) */ -void spicommon_connect_spi_and_dma(spi_host_device_t host, int dma_chan); +esp_err_t spicommon_alloc_dma(spi_host_device_t host_id, int dma_chan, uint32_t *out_actual_dma_chan); /** * @brief Connect a SPI peripheral to GPIO pins diff --git a/components/driver/include/driver/spi_slave.h b/components/driver/include/driver/spi_slave.h index 4263735a42..3bee13c264 100644 --- a/components/driver/include/driver/spi_slave.h +++ b/components/driver/include/driver/spi_slave.h @@ -93,9 +93,11 @@ struct spi_slave_transaction_t { * @param host SPI peripheral to use as a SPI slave interface * @param bus_config Pointer to a spi_bus_config_t struct specifying how the host should be initialized * @param slave_config Pointer to a spi_slave_interface_config_t struct specifying the details for the slave interface - * @param dma_chan Either 1 or 2. A SPI bus used by this driver must have a DMA channel associated with - * it. The SPI hardware has two DMA channels to share. This parameter indicates which - * one to use. + * @param dma_chan -1: auto dma allocate mode; 0: non-dma mode; 1 or 2: assign a specific DMA channel; + * Selecting a DMA channel for an SPI bus allows transfers on the bus to have sizes only + * limited by the amount of internal memory. Selecting no DMA channel (by passing the + * value 0) limits the amount of bytes transfered to a maximum of 64. Set to 0 if only + * the SPI flash uses this bus. Set -1 to let the driver to allocate the DMA channel. * * @warning If a DMA channel is selected, any transmit and receive buffer used should be allocated in * DMA-capable memory. @@ -106,7 +108,7 @@ struct spi_slave_transaction_t { * * @return * - ESP_ERR_INVALID_ARG if configuration is invalid - * - ESP_ERR_INVALID_STATE if host already is in use + * - ESP_ERR_INVALID_STATE if host already is in use or DMA channel is not available * - ESP_ERR_NO_MEM if out of memory * - ESP_OK on success */ diff --git a/components/driver/include/driver/spi_slave_hd.h b/components/driver/include/driver/spi_slave_hd.h index e847287362..639f7b3287 100644 --- a/components/driver/include/driver/spi_slave_hd.h +++ b/components/driver/include/driver/spi_slave_hd.h @@ -86,7 +86,7 @@ typedef struct { uint32_t address_bits; ///< address field bits, multiples of 8 and at least 8. uint32_t dummy_bits; ///< dummy field bits, multiples of 8 and at least 8. uint32_t queue_size; ///< Transaction queue size. This sets how many transactions can be 'in the air' (queued using spi_slave_hd_queue_trans but not yet finished using spi_slave_hd_get_trans_result) at the same time - uint32_t dma_chan; ///< DMA channel used + uint32_t dma_chan; ///< DMA channel used. -1: auto dma allocate mode; 0: non-dma mode; 1 or 2: assign a specific DMA channel; spi_slave_hd_callback_config_t cb_config; ///< Callback configuration } spi_slave_hd_slot_config_t; diff --git a/components/driver/spi_common.c b/components/driver/spi_common.c index 108a2625bb..2f64299b2c 100644 --- a/components/driver/spi_common.c +++ b/components/driver/spi_common.c @@ -100,6 +100,12 @@ static portMUX_TYPE spi_dma_spinlock = portMUX_INITIALIZER_UNLOCKED; static spicommon_bus_context_t s_mainbus = MAIN_BUS_DEFAULT(); static spicommon_bus_context_t* bus_ctx[SOC_SPI_PERIPH_NUM] = {&s_mainbus}; +#if CONFIG_IDF_TARGET_ESP32 || SOC_GDMA_SUPPORTED +//ESP32S2 does not support DMA channel auto-allocation +//Each bit stands for 1 dma channel, used for auto-alloc dma channel +static uint32_t spi_dma_channel_code; +#endif + //Returns true if this peripheral is successfully claimed, false if otherwise. bool spicommon_periph_claim(spi_host_device_t host, const char* source) @@ -159,7 +165,7 @@ static inline periph_module_t get_dma_periph(int dma_chan) #endif } -bool spicommon_dma_chan_claim(int dma_chan) +static bool spicommon_dma_chan_claim(int dma_chan) { bool ret = false; assert(dma_chan >= 1 && dma_chan <= SOC_SPI_DMA_CHAN_NUM); @@ -196,7 +202,7 @@ bool spicommon_dma_chan_free(int dma_chan) return true; } -void spicommon_connect_spi_and_dma(spi_host_device_t host, int dma_chan) +static void spicommon_connect_spi_and_dma(spi_host_device_t host, int dma_chan) { #if CONFIG_IDF_TARGET_ESP32 DPORT_SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, dma_chan, (host * 2)); @@ -223,6 +229,50 @@ void spicommon_connect_spi_and_dma(spi_host_device_t host, int dma_chan) #endif //#elif SOC_GDMA_SUPPORTED } +esp_err_t spicommon_alloc_dma(spi_host_device_t host_id, int dma_chan, uint32_t *out_actual_dma_chan) +{ + uint32_t actual_dma_chan = 0; + +#if !SOC_GDMA_SUPPORTED + if (dma_chan < 0) { +#if CONFIG_IDF_TARGET_ESP32 + for (int i = 0; i < SOC_SPI_DMA_CHAN_NUM; i++) { + bool is_used = BIT(i) & spi_dma_channel_code; + if (!is_used) { + spi_dma_channel_code |= BIT(i); + actual_dma_chan = i+1; + break; + } + } + if (!actual_dma_chan) { + SPI_CHECK(false, "no available dma channel", ESP_ERR_INVALID_STATE); + } +#elif CONFIG_IDF_TARGET_ESP32S2 + //On ESP32S2, each SPI controller has its own DMA channel. So DMA channel auto-allocation is not supported + SPI_CHECK(false, "ESP32S2 does not support auto-alloc dma channel", ESP_ERR_INVALID_STATE); +#endif //#if CONFIG_IDF_TARGET_XXX + } else if (dma_chan > 0) { + actual_dma_chan = dma_chan; + } else { //dma_chan == 0 + // Program won't reach here + } + + bool dma_chan_claimed = spicommon_dma_chan_claim(actual_dma_chan); + if (!dma_chan_claimed) { + spicommon_periph_free(host_id); + SPI_CHECK(false, "dma channel already in use", ESP_ERR_INVALID_STATE); + } + + spicommon_connect_spi_and_dma(host_id, actual_dma_chan); + +#elif SOC_GDMA_SUPPORTED + +#endif + + *out_actual_dma_chan = actual_dma_chan; + return ESP_OK; +} + static bool bus_uses_iomux_pins(spi_host_device_t host, const spi_bus_config_t* bus_config) { if (bus_config->sclk_io_num>=0 && @@ -490,12 +540,16 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t * esp_err_t err = ESP_OK; spicommon_bus_context_t *ctx = NULL; spi_bus_attr_t *bus_attr = NULL; + uint32_t actual_dma_chan = 0; + SPI_CHECK(is_valid_host(host_id), "invalid host_id", ESP_ERR_INVALID_ARG); SPI_CHECK(bus_ctx[host_id] == NULL, "SPI bus already initialized.", ESP_ERR_INVALID_STATE); #ifdef CONFIG_IDF_TARGET_ESP32 - SPI_CHECK( dma_chan >= 0 && dma_chan <= 2, "invalid dma channel", ESP_ERR_INVALID_ARG ); + SPI_CHECK( (dma_chan >= 0 && dma_chan <= 2) || dma_chan == -1, "invalid dma channel", ESP_ERR_INVALID_ARG ); #elif CONFIG_IDF_TARGET_ESP32S2 SPI_CHECK( dma_chan == 0 || dma_chan == host_id, "invalid dma channel", ESP_ERR_INVALID_ARG ); +#elif SOC_GDMA_SUPPORTED + SPI_CHECK( dma_chan == -1, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG ); #endif SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH|ESP_INTR_FLAG_EDGE|ESP_INTR_FLAG_INTRDISABLED))==0, "intr flag not allowed", ESP_ERR_INVALID_ARG); #ifndef CONFIG_SPI_MASTER_ISR_IN_IRAM @@ -505,36 +559,23 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t * bool spi_chan_claimed = spicommon_periph_claim(host_id, "spi master"); SPI_CHECK(spi_chan_claimed, "host_id already in use", ESP_ERR_INVALID_STATE); - if (dma_chan != 0) { - bool dma_chan_claimed = spicommon_dma_chan_claim(dma_chan); - if (!dma_chan_claimed) { - spicommon_periph_free(host_id); - SPI_CHECK(false, "dma channel already in use", ESP_ERR_INVALID_STATE); - } - - spicommon_connect_spi_and_dma(host_id, dma_chan); - } - //clean and initialize the context - ctx = (spicommon_bus_context_t*)malloc(sizeof(spicommon_bus_context_t)); + ctx = (spicommon_bus_context_t *)calloc(1, sizeof(spicommon_bus_context_t)); if (!ctx) { err = ESP_ERR_NO_MEM; goto cleanup; } - *ctx = (spicommon_bus_context_t) { - .host_id = host_id, - .bus_attr = { - .bus_cfg = *bus_config, - .dma_chan = dma_chan, - }, - }; - + ctx->host_id = host_id; bus_attr = &ctx->bus_attr; - if (dma_chan == 0) { - bus_attr->max_transfer_sz = SOC_SPI_MAXIMUM_BUFFER_SIZE; - bus_attr->dma_desc_num = 0; - } else { - //See how many dma descriptors we need and allocate them + bus_attr->bus_cfg = *bus_config; + + if (dma_chan != 0) { + err = spicommon_alloc_dma(host_id, dma_chan, &actual_dma_chan); + if (err != ESP_OK) { + return err; + } + bus_attr->dma_chan = actual_dma_chan; + int dma_desc_ct = lldesc_get_required_num(bus_config->max_transfer_sz); if (dma_desc_ct == 0) dma_desc_ct = 1; //default to 4k when max is not given @@ -546,6 +587,9 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t * goto cleanup; } bus_attr->dma_desc_num = dma_desc_ct; + } else { + bus_attr->max_transfer_sz = SOC_SPI_MAXIMUM_BUFFER_SIZE; + bus_attr->dma_desc_num = 0; } spi_bus_lock_config_t lock_config = { @@ -565,7 +609,7 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t * } #endif //CONFIG_PM_ENABLE - err = spicommon_bus_initialize_io(host_id, bus_config, dma_chan, SPICOMMON_BUSFLAG_MASTER | bus_config->flags, &bus_attr->flags); + err = spicommon_bus_initialize_io(host_id, bus_config, actual_dma_chan, SPICOMMON_BUSFLAG_MASTER | bus_config->flags, &bus_attr->flags); if (err != ESP_OK) { goto cleanup; } @@ -585,8 +629,8 @@ cleanup: free(bus_attr->dmadesc_rx); } free(ctx); - if (dma_chan) { - spicommon_dma_chan_free(dma_chan); + if (actual_dma_chan) { + spicommon_dma_chan_free(actual_dma_chan); } spicommon_periph_free(host_id); return err; diff --git a/components/driver/spi_slave.c b/components/driver/spi_slave.c index 91f512be2f..d91b3b3137 100644 --- a/components/driver/spi_slave.c +++ b/components/driver/spi_slave.c @@ -110,15 +110,18 @@ static inline void restore_cs(spi_slave_t *host) esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *bus_config, const spi_slave_interface_config_t *slave_config, int dma_chan) { - bool spi_chan_claimed, dma_chan_claimed; + bool spi_chan_claimed; + uint32_t actual_dma_chan = 0; esp_err_t ret = ESP_OK; esp_err_t err; //We only support HSPI/VSPI, period. SPI_CHECK(is_valid_host(host), "invalid host", ESP_ERR_INVALID_ARG); -#if defined(CONFIG_IDF_TARGET_ESP32) - SPI_CHECK( dma_chan >= 0 && dma_chan <= 2, "invalid dma channel", ESP_ERR_INVALID_ARG ); -#elif defined(CONFIG_IDF_TARGET_ESP32S2) +#ifdef CONFIG_IDF_TARGET_ESP32 + SPI_CHECK( (dma_chan >= 0 && dma_chan <= 2) || dma_chan == -1, "invalid dma channel", ESP_ERR_INVALID_ARG ); +#elif CONFIG_IDF_TARGET_ESP32S2 SPI_CHECK( dma_chan == 0 || dma_chan == host, "invalid dma channel", ESP_ERR_INVALID_ARG ); +#elif SOC_GDMA_SUPPORTED + SPI_CHECK( dma_chan == -1, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG ); #endif SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH|ESP_INTR_FLAG_EDGE|ESP_INTR_FLAG_INTRDISABLED))==0, "intr flag not allowed", ESP_ERR_INVALID_ARG); #ifndef CONFIG_SPI_SLAVE_ISR_IN_IRAM @@ -129,15 +132,12 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b spi_chan_claimed=spicommon_periph_claim(host, "spi slave"); SPI_CHECK(spi_chan_claimed, "host already in use", ESP_ERR_INVALID_STATE); - bool use_dma = dma_chan != 0; + bool use_dma = (dma_chan != 0); if (use_dma) { - dma_chan_claimed=spicommon_dma_chan_claim(dma_chan); - if ( !dma_chan_claimed ) { - spicommon_periph_free( host ); - SPI_CHECK(dma_chan_claimed, "dma channel already in use", ESP_ERR_INVALID_STATE); + err = spicommon_alloc_dma(host, dma_chan, &actual_dma_chan); + if (err != ESP_OK) { + return err; } - - spicommon_connect_spi_and_dma(host, dma_chan); } spihost[host] = malloc(sizeof(spi_slave_t)); @@ -149,7 +149,7 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b memcpy(&spihost[host]->cfg, slave_config, sizeof(spi_slave_interface_config_t)); spihost[host]->id = host; - err = spicommon_bus_initialize_io(host, bus_config, dma_chan, SPICOMMON_BUSFLAG_SLAVE|bus_config->flags, &spihost[host]->flags); + err = spicommon_bus_initialize_io(host, bus_config, actual_dma_chan, SPICOMMON_BUSFLAG_SLAVE|bus_config->flags, &spihost[host]->flags); if (err!=ESP_OK) { ret = err; goto cleanup; @@ -162,7 +162,7 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b if (use_dma) freeze_cs(spihost[host]); int dma_desc_ct = 0; - spihost[host]->dma_chan = dma_chan; + spihost[host]->dma_chan = actual_dma_chan; if (use_dma) { //See how many dma descriptors we need and allocate them dma_desc_ct = (bus_config->max_transfer_sz + SPI_MAX_DMA_LEN - 1) / SPI_MAX_DMA_LEN; @@ -242,7 +242,7 @@ cleanup: free(spihost[host]); spihost[host] = NULL; spicommon_periph_free(host); - if (dma_chan != 0) spicommon_dma_chan_free(dma_chan); + if (actual_dma_chan != 0) spicommon_dma_chan_free(actual_dma_chan); return ret; } diff --git a/components/driver/spi_slave_hd.c b/components/driver/spi_slave_hd.c index 1b3cd6b104..86a872320f 100644 --- a/components/driver/spi_slave_hd.c +++ b/components/driver/spi_slave_hd.c @@ -64,12 +64,17 @@ static void spi_slave_hd_intr_append(void *arg); esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *bus_config, const spi_slave_hd_slot_config_t *config) { - bool spi_chan_claimed, dma_chan_claimed; + bool spi_chan_claimed; bool append_mode = (config->flags & SPI_SLAVE_HD_APPEND_MODE); + uint32_t actual_dma_chan = 0; esp_err_t ret = ESP_OK; SPIHD_CHECK(VALID_HOST(host_id), "invalid host", ESP_ERR_INVALID_ARG); +#if CONFIG_IDF_TARGET_ESP32S2 SPIHD_CHECK(config->dma_chan == 0 || config->dma_chan == host_id, "invalid dma channel", ESP_ERR_INVALID_ARG); +#elif SOC_GDMA_SUPPORTED + SPI_CHECK(dma_chan == -1, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG); +#endif #if !CONFIG_IDF_TARGET_ESP32S2 //Append mode is only supported on ESP32S2 now SPIHD_CHECK(append_mode == 0, "Append mode is only supported on ESP32S2 now", ESP_ERR_INVALID_ARG); @@ -78,14 +83,11 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b spi_chan_claimed = spicommon_periph_claim(host_id, "slave_hd"); SPIHD_CHECK(spi_chan_claimed, "host already in use", ESP_ERR_INVALID_STATE); - if ( config->dma_chan != 0 ) { - dma_chan_claimed = spicommon_dma_chan_claim(config->dma_chan); - if (!dma_chan_claimed) { - spicommon_periph_free(host_id); - SPIHD_CHECK(dma_chan_claimed, "dma channel already in use", ESP_ERR_INVALID_STATE); + if (config->dma_chan != 0) { + ret = spicommon_alloc_dma(host_id, config->dma_chan, &actual_dma_chan); + if (ret != ESP_OK) { + return ret; } - - spicommon_connect_spi_and_dma(host_id, config->dma_chan); } spi_slave_hd_slot_t* host = malloc(sizeof(spi_slave_hd_slot_t)); @@ -96,10 +98,10 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b spihost[host_id] = host; memset(host, 0, sizeof(spi_slave_hd_slot_t)); - host->dma_chan = config->dma_chan; + host->dma_chan = actual_dma_chan; host->int_spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; - ret = spicommon_bus_initialize_io(host_id, bus_config, config->dma_chan, + ret = spicommon_bus_initialize_io(host_id, bus_config, actual_dma_chan, SPICOMMON_BUSFLAG_SLAVE | bus_config->flags, &host->flags); if (ret != ESP_OK) { goto cleanup; @@ -113,14 +115,14 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b .host_id = host_id, .dma_in = SPI_LL_GET_HW(host_id), .dma_out = SPI_LL_GET_HW(host_id), - .dma_chan = config->dma_chan, + .dma_chan = actual_dma_chan, .append_mode = append_mode, .mode = config->mode, .tx_lsbfirst = (config->flags & SPI_SLAVE_HD_RXBIT_LSBFIRST), .rx_lsbfirst = (config->flags & SPI_SLAVE_HD_TXBIT_LSBFIRST), }; - if (config->dma_chan != 0) { + if (actual_dma_chan != 0) { //Malloc for all the DMA descriptors uint32_t total_desc_size = spi_slave_hd_hal_get_total_desc_size(&host->hal, bus_config->max_transfer_sz); host->hal.dmadesc_tx = heap_caps_malloc(total_desc_size, MALLOC_CAP_DMA); From ffc4ff5a8c7adca8bf8e1973b51d508dbd9ea822 Mon Sep 17 00:00:00 2001 From: Armando Date: Wed, 27 Jan 2021 21:56:16 +0800 Subject: [PATCH 2/6] spi: apply gdma allocator to SPI --- .../include/driver/spi_common_internal.h | 35 +- .../driver/include/driver/spi_slave_hd.h | 2 +- components/driver/spi_common.c | 299 ++++++++++++------ components/driver/spi_master.c | 37 ++- components/driver/spi_slave.c | 60 ++-- components/driver/spi_slave_hd.c | 43 +-- components/hal/esp32/include/hal/spi_ll.h | 36 ++- components/hal/esp32s2/include/hal/spi_ll.h | 46 +-- components/hal/include/hal/spi_hal.h | 26 +- components/hal/include/hal/spi_slave_hal.h | 4 +- components/hal/include/hal/spi_slave_hd_hal.h | 8 +- components/hal/spi_hal.c | 35 +- components/hal/spi_hal_iram.c | 30 +- components/hal/spi_slave_hal.c | 20 +- components/hal/spi_slave_hal_iram.c | 24 +- components/hal/spi_slave_hd_hal.c | 63 ++-- components/soc/esp32c3/include/soc/spi_caps.h | 2 +- 17 files changed, 480 insertions(+), 290 deletions(-) diff --git a/components/driver/include/driver/spi_common_internal.h b/components/driver/include/driver/spi_common_internal.h index 82d5b73c9d..f5015bfbf4 100644 --- a/components/driver/include/driver/spi_common_internal.h +++ b/components/driver/include/driver/spi_common_internal.h @@ -65,7 +65,9 @@ typedef struct { spi_bus_config_t bus_cfg; ///< Config used to initialize the bus uint32_t flags; ///< Flags (attributes) of the bus int max_transfer_sz; ///< Maximum length of bytes available to send - int dma_chan; ///< DMA channel used + bool dma_enabled; ///< To enable DMA or not + int tx_dma_chan; ///< TX DMA channel, on ESP32 and ESP32S2, tx_dma_chan and rx_dma_chan are same + int rx_dma_chan; ///< RX DMA channel, on ESP32 and ESP32S2, tx_dma_chan and rx_dma_chan are same int dma_desc_num; ///< DMA descriptor number of dmadesc_tx or dmadesc_rx. lldesc_t *dmadesc_tx; ///< DMA descriptor array for TX lldesc_t *dmadesc_rx; ///< DMA descriptor array for RX @@ -127,24 +129,30 @@ bool spicommon_periph_free(spi_host_device_t host); bool spicommon_dma_chan_in_use(int dma_chan); /** - * @brief Return the SPI DMA channel so other driver can claim it, or just to power down DMA. + * @brief Configure DMA for SPI Slave * - * @param dma_chan channel to return + * @param host_id SPI host ID + * @param dma_chan -1: auto dma allocate mode; 0: non-dma mode; 1 or 2: assign a specific DMA channel; + * @param[out] out_actual_tx_dma_chan Actual TX DMA channel (if you choose to assign a specific DMA channel, this will be the channel you assigned before) + * @param[out] out_actual_rx_dma_chan Actual RX DMA channel (if you choose to assign a specific DMA channel, this will be the channel you assigned before) * - * @note This public API is deprecated. - * - * @return True if success; false otherwise. + * @return + * - ESP_OK: On success + * - ESP_ERR_NO_MEM: No enough memory + * - ESP_ERR_INVALID_STATE: Driver invalid state, check the log message for details */ -bool spicommon_dma_chan_free(int dma_chan); +esp_err_t spicommon_slave_alloc_dma(spi_host_device_t host_id, int dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan); /** - * @brief Try to claim a SPI DMA channel and connect it with SPI peripherals + * @brief Free DMA for SPI Slave * - * @param host_id SPI host ID - * @param dma_chan -1: auto dma allocate mode; 0: non-dma mode; 1 or 2: assign a specific DMA channel; - * @param[out] out_actual_dma_chan Actual DMA channel (if you choose to assign a specific DMA channel, this will be the channel you assigned before) + * @param host_id SPI host ID + * @param dma_chan Actual used DMA channel + * + * @return + * - ESP_OK: On success */ -esp_err_t spicommon_alloc_dma(spi_host_device_t host_id, int dma_chan, uint32_t *out_actual_dma_chan); +esp_err_t spicommon_slave_free_dma(spi_host_device_t host_id, int dma_chan); /** * @brief Connect a SPI peripheral to GPIO pins @@ -158,7 +166,6 @@ esp_err_t spicommon_alloc_dma(spi_host_device_t host_id, int dma_chan, uint32_t * * @param host SPI peripheral to be routed * @param bus_config Pointer to a spi_bus_config struct detailing the GPIO pins - * @param dma_chan DMA-channel (1 or 2) to use, or 0 for no DMA. * @param flags Combination of SPICOMMON_BUSFLAG_* flags, set to ensure the pins set are capable with some functions: * - ``SPICOMMON_BUSFLAG_MASTER``: Initialize I/O in master mode * - ``SPICOMMON_BUSFLAG_SLAVE``: Initialize I/O in slave mode @@ -180,7 +187,7 @@ esp_err_t spicommon_alloc_dma(spi_host_device_t host_id, int dma_chan, uint32_t * - ESP_ERR_INVALID_ARG if parameter is invalid * - ESP_OK on success */ -esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_config_t *bus_config, int dma_chan, uint32_t flags, uint32_t *flags_o); +esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_config_t *bus_config, uint32_t flags, uint32_t *flags_o); /** * @brief Free the IO used by a SPI peripheral diff --git a/components/driver/include/driver/spi_slave_hd.h b/components/driver/include/driver/spi_slave_hd.h index 639f7b3287..55990f88ed 100644 --- a/components/driver/include/driver/spi_slave_hd.h +++ b/components/driver/include/driver/spi_slave_hd.h @@ -86,7 +86,7 @@ typedef struct { uint32_t address_bits; ///< address field bits, multiples of 8 and at least 8. uint32_t dummy_bits; ///< dummy field bits, multiples of 8 and at least 8. uint32_t queue_size; ///< Transaction queue size. This sets how many transactions can be 'in the air' (queued using spi_slave_hd_queue_trans but not yet finished using spi_slave_hd_get_trans_result) at the same time - uint32_t dma_chan; ///< DMA channel used. -1: auto dma allocate mode; 0: non-dma mode; 1 or 2: assign a specific DMA channel; + int dma_chan; ///< DMA channel used. -1: auto dma allocate mode; 0: non-dma mode; 1 or 2: assign a specific DMA channel; spi_slave_hd_callback_config_t cb_config; ///< Callback configuration } spi_slave_hd_slot_config_t; diff --git a/components/driver/spi_common.c b/components/driver/spi_common.c index 2f64299b2c..a1ae2f02db 100644 --- a/components/driver/spi_common.c +++ b/components/driver/spi_common.c @@ -38,6 +38,7 @@ //This GDMA related part will be introduced by GDMA dedicated APIs in the future. Here we temporarily use macros. #if SOC_GDMA_SUPPORTED +#include "esp_private/gdma.h" #include "hal/gdma_ll.h" #include "soc/gdma_channel.h" #include "soc/spi_caps.h" @@ -70,43 +71,52 @@ typedef struct spi_device_t spi_device_t; #define DMA_CHANNEL_ENABLED(dma_chan) (BIT(dma_chan-1)) - typedef struct { int host_id; spi_destroy_func_t destroy_func; void* destroy_arg; spi_bus_attr_t bus_attr; +#if SOC_GDMA_SUPPORTED + gdma_channel_handle_t tx_channel; + gdma_channel_handle_t rx_channel; +#endif } spicommon_bus_context_t; #define MAIN_BUS_DEFAULT() { \ .host_id = 0, \ .bus_attr = { \ - .dma_chan = 0, \ + .tx_dma_chan = 0, \ + .rx_dma_chan = 0, \ .max_transfer_sz = SOC_SPI_MAXIMUM_BUFFER_SIZE, \ .dma_desc_num= 0, \ }, \ } //Periph 1 is 'claimed' by SPI flash code. -static atomic_bool spi_periph_claimed[SOC_SPI_PERIPH_NUM] = { ATOMIC_VAR_INIT(true), ATOMIC_VAR_INIT(false), ATOMIC_VAR_INIT(false), -#if SOC_SPI_PERIPH_NUM >= 4 +static atomic_bool spi_periph_claimed[SOC_SPI_PERIPH_NUM] = { ATOMIC_VAR_INIT(true), ATOMIC_VAR_INIT(false), +#if (SOC_SPI_PERIPH_NUM >= 3) +ATOMIC_VAR_INIT(false), +#endif +#if (SOC_SPI_PERIPH_NUM >= 4) ATOMIC_VAR_INIT(false), #endif }; static const char* spi_claiming_func[3] = {NULL, NULL, NULL}; +#if !SOC_GDMA_SUPPORTED static uint8_t spi_dma_chan_enabled = 0; static portMUX_TYPE spi_dma_spinlock = portMUX_INITIALIZER_UNLOCKED; +#endif static spicommon_bus_context_t s_mainbus = MAIN_BUS_DEFAULT(); static spicommon_bus_context_t* bus_ctx[SOC_SPI_PERIPH_NUM] = {&s_mainbus}; -#if CONFIG_IDF_TARGET_ESP32 || SOC_GDMA_SUPPORTED +#if CONFIG_IDF_TARGET_ESP32 //ESP32S2 does not support DMA channel auto-allocation //Each bit stands for 1 dma channel, used for auto-alloc dma channel static uint32_t spi_dma_channel_code; #endif - +//----------------------------------------------------------alloc spi periph-------------------------------------------------------// //Returns true if this peripheral is successfully claimed, false if otherwise. bool spicommon_periph_claim(spi_host_device_t host, const char* source) { @@ -145,6 +155,8 @@ int spicommon_irqdma_source_for_host(spi_host_device_t host) return spi_periph_signal[host].irq_dma; } +//----------------------------------------------------------esp32/s2 dma periph-------------------------------------------------------// +#if !SOC_GDMA_SUPPORTED static inline periph_module_t get_dma_periph(int dma_chan) { #if CONFIG_IDF_TARGET_ESP32S2 @@ -158,10 +170,6 @@ static inline periph_module_t get_dma_periph(int dma_chan) } #elif CONFIG_IDF_TARGET_ESP32 return PERIPH_SPI_DMA_MODULE; -#elif SOC_GDMA_SUPPORTED - return PERIPH_GDMA_MODULE; -#else - return 0; #endif } @@ -183,14 +191,152 @@ static bool spicommon_dma_chan_claim(int dma_chan) return ret; } -bool spicommon_dma_chan_in_use(int dma_chan) +static void spicommon_connect_spi_and_dma(spi_host_device_t host, int dma_chan) { - assert(dma_chan ==1 || dma_chan == 2); - return spi_dma_chan_enabled & DMA_CHANNEL_ENABLED(dma_chan); +#if CONFIG_IDF_TARGET_ESP32 + DPORT_SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, dma_chan, (host * 2)); +#elif CONFIG_IDF_TARGET_ESP32S2 + //On ESP32S2, each SPI controller has its own DMA channel. So there is no need to connect them. +#endif } -bool spicommon_dma_chan_free(int dma_chan) +#endif //#if !SOC_GDMA_SUPPORTED + +bool spicommon_dma_chan_in_use(int dma_chan) { +#if !SOC_GDMA_SUPPORTED + assert(dma_chan ==1 || dma_chan == 2); + return spi_dma_chan_enabled & DMA_CHANNEL_ENABLED(dma_chan); +#endif + return true; +} + +//----------------------------------------------------------alloc dma periph-------------------------------------------------------// +static esp_err_t spicommon_alloc_dma(spi_host_device_t host_id, int dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan) +{ + uint32_t actual_tx_dma_chan = 0; + uint32_t actual_rx_dma_chan = 0; + esp_err_t ret = ESP_OK; + +#if !SOC_GDMA_SUPPORTED +//On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same + if (dma_chan < 0) { +#if CONFIG_IDF_TARGET_ESP32 + for (int i = 0; i < SOC_SPI_DMA_CHAN_NUM; i++) { + bool is_used = BIT(i) & spi_dma_channel_code; + if (!is_used) { + spi_dma_channel_code |= BIT(i); + actual_tx_dma_chan = i+1; + actual_rx_dma_chan = i+1; + break; + } + } + if (!actual_tx_dma_chan) { + SPI_CHECK(false, "no available dma channel", ESP_ERR_INVALID_STATE); + } +#elif CONFIG_IDF_TARGET_ESP32S2 + //On ESP32S2, each SPI controller has its own DMA channel. So DMA channel auto-allocation is not supported + SPI_CHECK(false, "ESP32S2 does not support auto-alloc dma channel", ESP_ERR_INVALID_STATE); +#endif //#if CONFIG_IDF_TARGET_XXX + } else if (dma_chan > 0) { + actual_tx_dma_chan = dma_chan; + actual_rx_dma_chan = dma_chan; + } else { //dma_chan == 0 + // Program won't reach here + abort(); + } + + bool dma_chan_claimed = spicommon_dma_chan_claim(actual_tx_dma_chan); + if (!dma_chan_claimed) { + spicommon_periph_free(host_id); + SPI_CHECK(false, "dma channel already in use", ESP_ERR_INVALID_STATE); + } + + spicommon_connect_spi_and_dma(host_id, actual_tx_dma_chan); + +#else //SOC_GDMA_SUPPORTED + + spicommon_bus_context_t *ctx = bus_ctx[host_id]; + + if (dma_chan < 0) { + gdma_channel_alloc_config_t tx_alloc_config = { + .flags.reserve_sibling = 1, + .direction = GDMA_CHANNEL_DIRECTION_TX, + }; + ret = gdma_new_channel(&tx_alloc_config, &ctx->tx_channel); + if (ret != ESP_OK) { + return ret; + } + + gdma_channel_alloc_config_t rx_alloc_config = { + .direction = GDMA_CHANNEL_DIRECTION_RX, + .sibling_chan = ctx->tx_channel, + }; + ret = gdma_new_channel(&rx_alloc_config, &ctx->rx_channel); + if (ret != ESP_OK) { + return ret; + } + + if (host_id == SPI1_HOST) { + SPI_CHECK(false, "SPI1 does not support DMA mode", ESP_ERR_INVALID_STATE); + } +#if (SOC_SPI_PERIPH_NUM >= 2) + else if (host_id == SPI2_HOST) { + gdma_connect(ctx->rx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2)); + gdma_connect(ctx->tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2)); + } +#endif +#if (SOC_SPI_PERIPH_NUM >= 3) + else { + //host_id == SPI3_HOST + gdma_connect(ctx->rx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 3)); + gdma_connect(ctx->tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 3)); + } +#endif + + gdma_get_channel_id(ctx->tx_channel, (int *)&actual_tx_dma_chan); + gdma_get_channel_id(ctx->rx_channel, (int *)&actual_rx_dma_chan); + + } else if (dma_chan > 0) { + SPI_CHECK(false, "specifying a DMA channel is not supported, please use dma auto-alloc mode", ESP_ERR_INVALID_STATE); + } else { //dma_chan == 0 + // Program won't reach here + } +#endif + + *out_actual_tx_dma_chan = actual_tx_dma_chan; + *out_actual_rx_dma_chan = actual_rx_dma_chan; + return ret; +} + +esp_err_t spicommon_slave_alloc_dma(spi_host_device_t host_id, int dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan) +{ + esp_err_t ret = ESP_OK; + spicommon_bus_context_t *ctx = (spicommon_bus_context_t *)calloc(1, sizeof(spicommon_bus_context_t)); + if (!ctx) { + ret = ESP_ERR_NO_MEM; + goto cleanup; + } + bus_ctx[host_id] = ctx; + ctx->host_id = host_id; + + + ret = spicommon_alloc_dma(host_id, dma_chan, out_actual_tx_dma_chan, out_actual_rx_dma_chan); + if (ret != ESP_OK) { + goto cleanup; + } + return ret; + +cleanup: + free(ctx); + ctx = NULL; + return ret; +} + +//----------------------------------------------------------free dma periph-------------------------------------------------------// +static esp_err_t spicommon_dma_chan_free(spi_host_device_t host_id, int dma_chan) +{ +#if !SOC_GDMA_SUPPORTED assert( dma_chan == 1 || dma_chan == 2 ); assert( spi_dma_chan_enabled & DMA_CHANNEL_ENABLED(dma_chan) ); @@ -199,80 +345,32 @@ bool spicommon_dma_chan_free(int dma_chan) periph_module_disable(get_dma_periph(dma_chan)); portEXIT_CRITICAL(&spi_dma_spinlock); - return true; -} - -static void spicommon_connect_spi_and_dma(spi_host_device_t host, int dma_chan) -{ -#if CONFIG_IDF_TARGET_ESP32 - DPORT_SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, dma_chan, (host * 2)); -#elif CONFIG_IDF_TARGET_ESP32S2 - //On ESP32S2, each SPI controller has its own DMA channel. So there is no need to connect them. -#elif SOC_GDMA_SUPPORTED - int gdma_chan, periph_id; - if (dma_chan == 1) { - gdma_chan = SOC_GDMA_SPI2_DMA_CHANNEL; - periph_id = SOC_GDMA_TRIG_PERIPH_SPI2; -#ifdef SOC_GDMA_TRIG_PERIPH_SPI3 - } else if (dma_chan == 2) { - gdma_chan = SOC_GDMA_SPI3_DMA_CHANNEL; - periph_id = SOC_GDMA_TRIG_PERIPH_SPI3; -#endif - } else { - abort(); +#else //SOC_GDMA_SUPPORTED + spicommon_bus_context_t *ctx = bus_ctx[host_id]; + if (ctx->rx_channel) { + gdma_disconnect(ctx->rx_channel); + gdma_del_channel(ctx->rx_channel); } - - spi_dma_connect_rx_channel_to_periph(gdma_chan, periph_id); - spi_dma_connect_tx_channel_to_periph(gdma_chan, periph_id); - spi_dma_set_rx_channel_priority(gdma_chan, 1); - spi_dma_set_tx_channel_priority(gdma_chan, 1); -#endif //#elif SOC_GDMA_SUPPORTED -} - -esp_err_t spicommon_alloc_dma(spi_host_device_t host_id, int dma_chan, uint32_t *out_actual_dma_chan) -{ - uint32_t actual_dma_chan = 0; - -#if !SOC_GDMA_SUPPORTED - if (dma_chan < 0) { -#if CONFIG_IDF_TARGET_ESP32 - for (int i = 0; i < SOC_SPI_DMA_CHAN_NUM; i++) { - bool is_used = BIT(i) & spi_dma_channel_code; - if (!is_used) { - spi_dma_channel_code |= BIT(i); - actual_dma_chan = i+1; - break; - } - } - if (!actual_dma_chan) { - SPI_CHECK(false, "no available dma channel", ESP_ERR_INVALID_STATE); - } -#elif CONFIG_IDF_TARGET_ESP32S2 - //On ESP32S2, each SPI controller has its own DMA channel. So DMA channel auto-allocation is not supported - SPI_CHECK(false, "ESP32S2 does not support auto-alloc dma channel", ESP_ERR_INVALID_STATE); -#endif //#if CONFIG_IDF_TARGET_XXX - } else if (dma_chan > 0) { - actual_dma_chan = dma_chan; - } else { //dma_chan == 0 - // Program won't reach here + if (ctx->tx_channel) { + gdma_disconnect(ctx->tx_channel); + gdma_del_channel(ctx->tx_channel); } - - bool dma_chan_claimed = spicommon_dma_chan_claim(actual_dma_chan); - if (!dma_chan_claimed) { - spicommon_periph_free(host_id); - SPI_CHECK(false, "dma channel already in use", ESP_ERR_INVALID_STATE); - } - - spicommon_connect_spi_and_dma(host_id, actual_dma_chan); - -#elif SOC_GDMA_SUPPORTED - #endif - *out_actual_dma_chan = actual_dma_chan; return ESP_OK; } +esp_err_t spicommon_slave_free_dma(spi_host_device_t host_id, int dma_chan) +{ + esp_err_t ret = spicommon_dma_chan_free(host_id, dma_chan); + + free(bus_ctx[host_id]); + bus_ctx[host_id] = NULL; + + return ret; +} + +//----------------------------------------------------------IO general-------------------------------------------------------// static bool bus_uses_iomux_pins(spi_host_device_t host, const spi_bus_config_t* bus_config) { if (bus_config->sclk_io_num>=0 && @@ -304,7 +402,7 @@ Do the common stuff to hook up a SPI host to a bus defined by a bunch of GPIO pi bus config struct and it'll set up the GPIO matrix and enable the device. If a pin is set to non-negative value, it should be able to be initialized. */ -esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_config_t *bus_config, int dma_chan, uint32_t flags, uint32_t* flags_o) +esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_config_t *bus_config, uint32_t flags, uint32_t* flags_o) { uint32_t temp_flag = 0; @@ -535,12 +633,14 @@ static inline bool is_valid_host(spi_host_device_t host) return host >= SPI1_HOST && host <= SPI3_HOST; } +//----------------------------------------------------------master bus init-------------------------------------------------------// esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t *bus_config, int dma_chan) { esp_err_t err = ESP_OK; spicommon_bus_context_t *ctx = NULL; spi_bus_attr_t *bus_attr = NULL; - uint32_t actual_dma_chan = 0; + uint32_t actual_tx_dma_chan = 0; + uint32_t actual_rx_dma_chan = 0; SPI_CHECK(is_valid_host(host_id), "invalid host_id", ESP_ERR_INVALID_ARG); SPI_CHECK(bus_ctx[host_id] == NULL, "SPI bus already initialized.", ESP_ERR_INVALID_STATE); @@ -549,7 +649,7 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t * #elif CONFIG_IDF_TARGET_ESP32S2 SPI_CHECK( dma_chan == 0 || dma_chan == host_id, "invalid dma channel", ESP_ERR_INVALID_ARG ); #elif SOC_GDMA_SUPPORTED - SPI_CHECK( dma_chan == -1, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG ); + SPI_CHECK( dma_chan == 0 || dma_chan == -1, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG ); #endif SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH|ESP_INTR_FLAG_EDGE|ESP_INTR_FLAG_INTRDISABLED))==0, "intr flag not allowed", ESP_ERR_INVALID_ARG); #ifndef CONFIG_SPI_MASTER_ISR_IN_IRAM @@ -565,16 +665,20 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t * err = ESP_ERR_NO_MEM; goto cleanup; } + bus_ctx[host_id] = ctx; ctx->host_id = host_id; bus_attr = &ctx->bus_attr; bus_attr->bus_cfg = *bus_config; if (dma_chan != 0) { - err = spicommon_alloc_dma(host_id, dma_chan, &actual_dma_chan); + bus_attr->dma_enabled = 1; + + err = spicommon_alloc_dma(host_id, dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan); if (err != ESP_OK) { - return err; + goto cleanup; } - bus_attr->dma_chan = actual_dma_chan; + bus_attr->tx_dma_chan = actual_tx_dma_chan; + bus_attr->rx_dma_chan = actual_rx_dma_chan; int dma_desc_ct = lldesc_get_required_num(bus_config->max_transfer_sz); if (dma_desc_ct == 0) dma_desc_ct = 1; //default to 4k when max is not given @@ -588,6 +692,7 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t * } bus_attr->dma_desc_num = dma_desc_ct; } else { + bus_attr->dma_enabled = 0; bus_attr->max_transfer_sz = SOC_SPI_MAXIMUM_BUFFER_SIZE; bus_attr->dma_desc_num = 0; } @@ -609,12 +714,11 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t * } #endif //CONFIG_PM_ENABLE - err = spicommon_bus_initialize_io(host_id, bus_config, actual_dma_chan, SPICOMMON_BUSFLAG_MASTER | bus_config->flags, &bus_attr->flags); + err = spicommon_bus_initialize_io(host_id, bus_config, SPICOMMON_BUSFLAG_MASTER | bus_config->flags, &bus_attr->flags); if (err != ESP_OK) { goto cleanup; } - bus_ctx[host_id] = ctx; return ESP_OK; cleanup: @@ -627,12 +731,15 @@ cleanup: } free(bus_attr->dmadesc_tx); free(bus_attr->dmadesc_rx); - } - free(ctx); - if (actual_dma_chan) { - spicommon_dma_chan_free(actual_dma_chan); + + //On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same + if (bus_attr->dma_enabled) { + spicommon_dma_chan_free(host_id, actual_tx_dma_chan); + } } spicommon_periph_free(host_id); + free(bus_ctx[host_id]); + bus_ctx[host_id] = NULL; return err; } @@ -663,8 +770,10 @@ esp_err_t spi_bus_free(spi_host_device_t host_id) free(bus_attr->dmadesc_rx); free(bus_attr->dmadesc_tx); - if (bus_attr->dma_chan > 0) { - spicommon_dma_chan_free (bus_attr->dma_chan); + + //On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same + if (bus_attr->dma_enabled > 0) { + spicommon_dma_chan_free (host_id, bus_attr->tx_dma_chan); } spicommon_periph_free(host_id); diff --git a/components/driver/spi_master.c b/components/driver/spi_master.c index 00325c24d9..e1d9eb3243 100644 --- a/components/driver/spi_master.c +++ b/components/driver/spi_master.c @@ -231,17 +231,18 @@ static esp_err_t spi_master_init_driver(spi_host_device_t host_id) } //assign the SPI, RX DMA and TX DMA peripheral registers beginning address - spi_hal_dma_config_t hal_dma_config = { + spi_hal_config_t hal_config = { //On ESP32-S2 and earlier chips, DMA registers are part of SPI registers. Pass the registers of SPI peripheral to control it. .dma_in = SPI_LL_GET_HW(host_id), .dma_out = SPI_LL_GET_HW(host_id), + .dma_enabled = bus_attr->dma_enabled, .dmadesc_tx = bus_attr->dmadesc_tx, .dmadesc_rx = bus_attr->dmadesc_rx, - .dmadesc_n = bus_attr->dma_desc_num + .tx_dma_chan = bus_attr->tx_dma_chan, + .rx_dma_chan = bus_attr->rx_dma_chan, + .dmadesc_n = bus_attr->dma_desc_num, }; - - spi_hal_init(&host->hal, host_id, &hal_dma_config); - host->hal.dma_enabled = (bus_attr->dma_chan != 0); + spi_hal_init(&host->hal, host_id, &hal_config); if (host_id != SPI1_HOST) { //SPI1 attributes are already initialized at start up. @@ -606,8 +607,9 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg) //Okay, transaction is done. const int cs = host->cur_cs; //Tell common code DMA workaround that our DMA channel is idle. If needed, the code will do a DMA reset. - if (bus_attr->dma_chan) { - spicommon_dmaworkaround_idle(bus_attr->dma_chan); + if (bus_attr->dma_enabled) { + //This workaround is only for esp32, where tx_dma_chan and rx_dma_chan are always same + spicommon_dmaworkaround_idle(bus_attr->tx_dma_chan); } //cur_cs is changed to DEV_NUM_MAX here @@ -658,9 +660,10 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg) if (trans_found) { spi_trans_priv_t *const cur_trans_buf = &host->cur_trans_buf; - if (bus_attr->dma_chan != 0 && (cur_trans_buf->buffer_to_rcv || cur_trans_buf->buffer_to_send)) { + if (bus_attr->dma_enabled && (cur_trans_buf->buffer_to_rcv || cur_trans_buf->buffer_to_send)) { //mark channel as active, so that the DMA will not be reset by the slave - spicommon_dmaworkaround_transfer_active(bus_attr->dma_chan); + //This workaround is only for esp32, where tx_dma_chan and rx_dma_chan are always same + spicommon_dmaworkaround_transfer_active(bus_attr->tx_dma_chan); } spi_new_trans(device_to_send, cur_trans_buf); } @@ -693,7 +696,7 @@ static SPI_MASTER_ISR_ATTR esp_err_t check_trans_valid(spi_device_handle_t handl SPI_CHECK(!((trans_desc->flags & (SPI_TRANS_MODE_DIO|SPI_TRANS_MODE_QIO)) && (handle->cfg.flags & SPI_DEVICE_3WIRE)), "incompatible iface params", ESP_ERR_INVALID_ARG); SPI_CHECK(!((trans_desc->flags & (SPI_TRANS_MODE_DIO|SPI_TRANS_MODE_QIO)) && !is_half_duplex), "incompatible iface params", ESP_ERR_INVALID_ARG); #ifdef CONFIG_IDF_TARGET_ESP32 - SPI_CHECK(!is_half_duplex || bus_attr->dma_chan == 0 || !rx_enabled || !tx_enabled, "SPI half duplex mode does not support using DMA with both MOSI and MISO phases.", ESP_ERR_INVALID_ARG ); + SPI_CHECK(!is_half_duplex || !bus_attr->dma_enabled || !rx_enabled || !tx_enabled, "SPI half duplex mode does not support using DMA with both MOSI and MISO phases.", ESP_ERR_INVALID_ARG ); #elif CONFIG_IDF_TARGET_ESP32S3 SPI_CHECK(!is_half_duplex || !tx_enabled || !rx_enabled, "SPI half duplex mode is not supported when both MOSI and MISO phases are enabled.", ESP_ERR_INVALID_ARG); #endif @@ -788,7 +791,7 @@ esp_err_t SPI_MASTER_ATTR spi_device_queue_trans(spi_device_handle_t handle, spi SPI_CHECK(!spi_bus_device_is_polling(handle), "Cannot queue new transaction while previous polling transaction is not terminated.", ESP_ERR_INVALID_STATE ); spi_trans_priv_t trans_buf; - ret = setup_priv_desc(trans_desc, &trans_buf, (host->bus_attr->dma_chan!=0)); + ret = setup_priv_desc(trans_desc, &trans_buf, (host->bus_attr->dma_enabled)); if (ret != ESP_OK) return ret; #ifdef CONFIG_PM_ENABLE @@ -877,8 +880,9 @@ esp_err_t SPI_MASTER_ISR_ATTR spi_device_acquire_bus(spi_device_t *device, TickT //configure the device ahead so that we don't need to do it again in the following transactions spi_setup_device(host->device[device->id]); //the DMA is also occupied by the device, all the slave devices that using DMA should wait until bus released. - if (host->bus_attr->dma_chan != 0) { - spicommon_dmaworkaround_transfer_active(host->bus_attr->dma_chan); + if (host->bus_attr->dma_enabled) { + //This workaround is only for esp32, where tx_dma_chan and rx_dma_chan are always same + spicommon_dmaworkaround_transfer_active(host->bus_attr->tx_dma_chan); } return ESP_OK; } @@ -893,8 +897,9 @@ void SPI_MASTER_ISR_ATTR spi_device_release_bus(spi_device_t *dev) assert(0); } - if (host->bus_attr->dma_chan != 0) { - spicommon_dmaworkaround_idle(host->bus_attr->dma_chan); + if (host->bus_attr->dma_enabled) { + //This workaround is only for esp32, where tx_dma_chan and rx_dma_chan are always same + spicommon_dmaworkaround_idle(host->bus_attr->tx_dma_chan); } //Tell common code DMA workaround that our DMA channel is idle. If needed, the code will do a DMA reset. @@ -928,7 +933,7 @@ esp_err_t SPI_MASTER_ISR_ATTR spi_device_polling_start(spi_device_handle_t handl } if (ret != ESP_OK) return ret; - ret = setup_priv_desc(trans_desc, &host->cur_trans_buf, (host->bus_attr->dma_chan!=0)); + ret = setup_priv_desc(trans_desc, &host->cur_trans_buf, (host->bus_attr->dma_enabled)); if (ret!=ESP_OK) return ret; //Polling, no interrupt is used. diff --git a/components/driver/spi_slave.c b/components/driver/spi_slave.c index d91b3b3137..e7765e2920 100644 --- a/components/driver/spi_slave.c +++ b/components/driver/spi_slave.c @@ -67,7 +67,9 @@ typedef struct { int max_transfer_sz; QueueHandle_t trans_queue; QueueHandle_t ret_queue; - int dma_chan; + bool dma_enabled; + uint32_t tx_dma_chan; + uint32_t rx_dma_chan; #ifdef CONFIG_PM_ENABLE esp_pm_lock_handle_t pm_lock; #endif @@ -111,7 +113,8 @@ static inline void restore_cs(spi_slave_t *host) esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *bus_config, const spi_slave_interface_config_t *slave_config, int dma_chan) { bool spi_chan_claimed; - uint32_t actual_dma_chan = 0; + uint32_t actual_tx_dma_chan = 0; + uint32_t actual_rx_dma_chan = 0; esp_err_t ret = ESP_OK; esp_err_t err; //We only support HSPI/VSPI, period. @@ -121,7 +124,7 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b #elif CONFIG_IDF_TARGET_ESP32S2 SPI_CHECK( dma_chan == 0 || dma_chan == host, "invalid dma channel", ESP_ERR_INVALID_ARG ); #elif SOC_GDMA_SUPPORTED - SPI_CHECK( dma_chan == -1, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG ); + SPI_CHECK( dma_chan == 0 || dma_chan == -1, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG ); #endif SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH|ESP_INTR_FLAG_EDGE|ESP_INTR_FLAG_INTRDISABLED))==0, "intr flag not allowed", ESP_ERR_INVALID_ARG); #ifndef CONFIG_SPI_SLAVE_ISR_IN_IRAM @@ -132,14 +135,6 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b spi_chan_claimed=spicommon_periph_claim(host, "spi slave"); SPI_CHECK(spi_chan_claimed, "host already in use", ESP_ERR_INVALID_STATE); - bool use_dma = (dma_chan != 0); - if (use_dma) { - err = spicommon_alloc_dma(host, dma_chan, &actual_dma_chan); - if (err != ESP_OK) { - return err; - } - } - spihost[host] = malloc(sizeof(spi_slave_t)); if (spihost[host] == NULL) { ret = ESP_ERR_NO_MEM; @@ -149,7 +144,16 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b memcpy(&spihost[host]->cfg, slave_config, sizeof(spi_slave_interface_config_t)); spihost[host]->id = host; - err = spicommon_bus_initialize_io(host, bus_config, actual_dma_chan, SPICOMMON_BUSFLAG_SLAVE|bus_config->flags, &spihost[host]->flags); + bool use_dma = (dma_chan != 0); + spihost[host]->dma_enabled = use_dma; + if (use_dma) { + ret = spicommon_slave_alloc_dma(host, dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan); + if (ret != ESP_OK) { + goto cleanup; + } + } + + err = spicommon_bus_initialize_io(host, bus_config, SPICOMMON_BUSFLAG_SLAVE|bus_config->flags, &spihost[host]->flags); if (err!=ESP_OK) { ret = err; goto cleanup; @@ -162,7 +166,8 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b if (use_dma) freeze_cs(spihost[host]); int dma_desc_ct = 0; - spihost[host]->dma_chan = actual_dma_chan; + spihost[host]->tx_dma_chan = actual_tx_dma_chan; + spihost[host]->rx_dma_chan = actual_rx_dma_chan; if (use_dma) { //See how many dma descriptors we need and allocate them dma_desc_ct = (bus_config->max_transfer_sz + SPI_MAX_DMA_LEN - 1) / SPI_MAX_DMA_LEN; @@ -220,6 +225,8 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b hal->tx_lsbfirst = (slave_config->flags & SPI_SLAVE_TXBIT_LSBFIRST) ? 1 : 0; hal->mode = slave_config->mode; hal->use_dma = use_dma; + hal->tx_dma_chan = actual_tx_dma_chan; + hal->rx_dma_chan = actual_rx_dma_chan; spi_slave_hal_setup_device(hal); @@ -239,10 +246,15 @@ cleanup: #endif } spi_slave_hal_deinit(&spihost[host]->hal); + //On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same + if (spihost[host]->dma_enabled) { + spicommon_slave_free_dma(host, actual_tx_dma_chan); + } + free(spihost[host]); spihost[host] = NULL; spicommon_periph_free(host); - if (actual_dma_chan != 0) spicommon_dma_chan_free(actual_dma_chan); + return ret; } @@ -252,8 +264,9 @@ esp_err_t spi_slave_free(spi_host_device_t host) SPI_CHECK(spihost[host], "host not slave", ESP_ERR_INVALID_ARG); if (spihost[host]->trans_queue) vQueueDelete(spihost[host]->trans_queue); if (spihost[host]->ret_queue) vQueueDelete(spihost[host]->ret_queue); - if ( spihost[host]->dma_chan > 0 ) { - spicommon_dma_chan_free ( spihost[host]->dma_chan ); + if (spihost[host]->dma_enabled) { + //On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same + spicommon_slave_free_dma(host, spihost[host]->tx_dma_chan); } free(spihost[host]->hal.dmadesc_tx); free(spihost[host]->hal.dmadesc_rx); @@ -274,9 +287,9 @@ esp_err_t SPI_SLAVE_ATTR spi_slave_queue_trans(spi_host_device_t host, const spi BaseType_t r; SPI_CHECK(is_valid_host(host), "invalid host", ESP_ERR_INVALID_ARG); SPI_CHECK(spihost[host], "host not slave", ESP_ERR_INVALID_ARG); - SPI_CHECK(spihost[host]->dma_chan == 0 || trans_desc->tx_buffer==NULL || esp_ptr_dma_capable(trans_desc->tx_buffer), + SPI_CHECK(spihost[host]->dma_enabled == 0 || trans_desc->tx_buffer==NULL || esp_ptr_dma_capable(trans_desc->tx_buffer), "txdata not in DMA-capable memory", ESP_ERR_INVALID_ARG); - SPI_CHECK(spihost[host]->dma_chan == 0 || trans_desc->rx_buffer==NULL || + SPI_CHECK(spihost[host]->dma_enabled == 0 || trans_desc->rx_buffer==NULL || (esp_ptr_dma_capable(trans_desc->rx_buffer) && esp_ptr_word_aligned(trans_desc->rx_buffer) && (trans_desc->length%4==0)), "rxdata not in DMA-capable memory or not WORD aligned", ESP_ERR_INVALID_ARG); @@ -332,7 +345,7 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg) assert(spi_slave_hal_usr_is_done(hal)); - bool use_dma = host->dma_chan != 0; + bool use_dma = host->dma_enabled; if (host->cur_trans) { // When DMA is enabled, the slave rx dma suffers from unexpected transactions. Forbid reading until transaction ready. if (use_dma) freeze_cs(host); @@ -341,7 +354,8 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg) host->cur_trans->trans_len = spi_slave_hal_get_rcv_bitlen(hal); if (spi_slave_hal_dma_need_reset(hal)) { - spicommon_dmaworkaround_req_reset(host->dma_chan, spi_slave_restart_after_dmareset, host); + //On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same + spicommon_dmaworkaround_req_reset(host->tx_dma_chan, spi_slave_restart_after_dmareset, host); } if (host->cfg.post_trans_cb) host->cfg.post_trans_cb(host->cur_trans); //Okay, transaction is done. @@ -350,7 +364,8 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg) host->cur_trans = NULL; } if (use_dma) { - spicommon_dmaworkaround_idle(host->dma_chan); + //On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same + spicommon_dmaworkaround_idle(host->tx_dma_chan); if (spicommon_dmaworkaround_reset_in_progress()) { //We need to wait for the reset to complete. Disable int (will be re-enabled on reset callback) and exit isr. esp_intr_disable(host->intr); @@ -375,7 +390,8 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg) hal->tx_buffer = trans->tx_buffer; if (use_dma) { - spicommon_dmaworkaround_transfer_active(host->dma_chan); + //On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same + spicommon_dmaworkaround_transfer_active(host->tx_dma_chan); } spi_slave_hal_prepare_data(hal); diff --git a/components/driver/spi_slave_hd.c b/components/driver/spi_slave_hd.c index 86a872320f..fbb521c199 100644 --- a/components/driver/spi_slave_hd.c +++ b/components/driver/spi_slave_hd.c @@ -28,7 +28,9 @@ #define SPIHD_CHECK(cond,warn,ret) do{if(!(cond)){ESP_LOGE(TAG, warn); return ret;}} while(0) typedef struct { - int dma_chan; + bool dma_enabled; + uint32_t tx_dma_chan; + uint32_t rx_dma_chan; int max_transfer_sz; uint32_t flags; portMUX_TYPE int_spinlock; @@ -66,14 +68,15 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b { bool spi_chan_claimed; bool append_mode = (config->flags & SPI_SLAVE_HD_APPEND_MODE); - uint32_t actual_dma_chan = 0; + uint32_t actual_tx_dma_chan = 0; + uint32_t actual_rx_dma_chan = 0; esp_err_t ret = ESP_OK; SPIHD_CHECK(VALID_HOST(host_id), "invalid host", ESP_ERR_INVALID_ARG); #if CONFIG_IDF_TARGET_ESP32S2 SPIHD_CHECK(config->dma_chan == 0 || config->dma_chan == host_id, "invalid dma channel", ESP_ERR_INVALID_ARG); #elif SOC_GDMA_SUPPORTED - SPI_CHECK(dma_chan == -1, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG); + SPIHD_CHECK(config->dma_chan == 0 || config->dma_chan == -1, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG); #endif #if !CONFIG_IDF_TARGET_ESP32S2 //Append mode is only supported on ESP32S2 now @@ -83,13 +86,6 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b spi_chan_claimed = spicommon_periph_claim(host_id, "slave_hd"); SPIHD_CHECK(spi_chan_claimed, "host already in use", ESP_ERR_INVALID_STATE); - if (config->dma_chan != 0) { - ret = spicommon_alloc_dma(host_id, config->dma_chan, &actual_dma_chan); - if (ret != ESP_OK) { - return ret; - } - } - spi_slave_hd_slot_t* host = malloc(sizeof(spi_slave_hd_slot_t)); if (host == NULL) { ret = ESP_ERR_NO_MEM; @@ -97,12 +93,20 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b } spihost[host_id] = host; memset(host, 0, sizeof(spi_slave_hd_slot_t)); - - host->dma_chan = actual_dma_chan; host->int_spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; + host->dma_enabled = (config->dma_chan != 0); - ret = spicommon_bus_initialize_io(host_id, bus_config, actual_dma_chan, - SPICOMMON_BUSFLAG_SLAVE | bus_config->flags, &host->flags); + if (host->dma_enabled) { + ret = spicommon_slave_alloc_dma(host_id, config->dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan); + if (ret != ESP_OK) { + goto cleanup; + } + } + + host->tx_dma_chan = actual_tx_dma_chan; + host->rx_dma_chan = actual_rx_dma_chan; + + ret = spicommon_bus_initialize_io(host_id, bus_config, SPICOMMON_BUSFLAG_SLAVE | bus_config->flags, &host->flags); if (ret != ESP_OK) { goto cleanup; } @@ -115,14 +119,16 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b .host_id = host_id, .dma_in = SPI_LL_GET_HW(host_id), .dma_out = SPI_LL_GET_HW(host_id), - .dma_chan = actual_dma_chan, + .dma_enabled = host->dma_enabled, + .tx_dma_chan = host->tx_dma_chan, + .rx_dma_chan = host->rx_dma_chan, .append_mode = append_mode, .mode = config->mode, .tx_lsbfirst = (config->flags & SPI_SLAVE_HD_RXBIT_LSBFIRST), .rx_lsbfirst = (config->flags & SPI_SLAVE_HD_TXBIT_LSBFIRST), }; - if (actual_dma_chan != 0) { + if (host->dma_enabled) { //Malloc for all the DMA descriptors uint32_t total_desc_size = spi_slave_hd_hal_get_total_desc_size(&host->hal, bus_config->max_transfer_sz); host->hal.dmadesc_tx = heap_caps_malloc(total_desc_size, MALLOC_CAP_DMA); @@ -245,8 +251,9 @@ esp_err_t spi_slave_hd_deinit(spi_host_device_t host_id) } spicommon_periph_free(host_id); - if (host->dma_chan) { - spicommon_dma_chan_free(host->dma_chan); + if (host->dma_enabled) { + //On ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same + spicommon_slave_free_dma(host_id, host->tx_dma_chan); } free(host); spihost[host_id] = NULL; diff --git a/components/hal/esp32/include/hal/spi_ll.h b/components/hal/esp32/include/hal/spi_ll.h index d8081ef667..99a0967625 100644 --- a/components/hal/esp32/include/hal/spi_ll.h +++ b/components/hal/esp32/include/hal/spi_ll.h @@ -946,9 +946,10 @@ static inline void spi_ll_enable_int(spi_dev_t *hw) /** * Reset RX DMA which stores the data received from a peripheral into RAM. * - * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + * @param channel DMA channel */ -static inline void spi_dma_ll_rx_reset(spi_dma_dev_t *dma_in) +static inline void spi_dma_ll_rx_reset(spi_dma_dev_t *dma_in, uint32_t channel) { //Reset RX DMA peripheral dma_in->dma_conf.in_rst = 1; @@ -958,10 +959,11 @@ static inline void spi_dma_ll_rx_reset(spi_dma_dev_t *dma_in) /** * Start RX DMA. * - * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. - * @param addr Address of the beginning DMA descriptor. + * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + * @param channel DMA channel + * @param addr Address of the beginning DMA descriptor. */ -static inline void spi_dma_ll_rx_start(spi_dma_dev_t *dma_in, lldesc_t *addr) +static inline void spi_dma_ll_rx_start(spi_dma_dev_t *dma_in, uint32_t channel, lldesc_t *addr) { dma_in->dma_in_link.addr = (int) addr & 0xFFFFF; dma_in->dma_in_link.start = 1; @@ -971,9 +973,10 @@ static inline void spi_dma_ll_rx_start(spi_dma_dev_t *dma_in, lldesc_t *addr) * Enable DMA RX channel burst for data * * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + * @param channel DMA channel * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_rx_enable_burst_data(spi_dma_dev_t *dma_in, bool enable) +static inline void spi_dma_ll_rx_enable_burst_data(spi_dma_dev_t *dma_in, uint32_t channel, bool enable) { //This is not supported in esp32 } @@ -982,9 +985,10 @@ static inline void spi_dma_ll_rx_enable_burst_data(spi_dma_dev_t *dma_in, bool e * Enable DMA RX channel burst for descriptor * * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + * @param channel DMA channel * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_rx_enable_burst_desc(spi_dma_dev_t *dma_in, bool enable) +static inline void spi_dma_ll_rx_enable_burst_desc(spi_dma_dev_t *dma_in, uint32_t channel, bool enable) { dma_in->dma_conf.indscr_burst_en = enable; } @@ -993,8 +997,9 @@ static inline void spi_dma_ll_rx_enable_burst_desc(spi_dma_dev_t *dma_in, bool e * Reset TX DMA which transmits the data from RAM to a peripheral. * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param channel DMA channel */ -static inline void spi_dma_ll_tx_reset(spi_dma_dev_t *dma_out) +static inline void spi_dma_ll_tx_reset(spi_dma_dev_t *dma_out, uint32_t channel) { //Reset TX DMA peripheral dma_out->dma_conf.out_rst = 1; @@ -1005,9 +1010,10 @@ static inline void spi_dma_ll_tx_reset(spi_dma_dev_t *dma_out) * Start TX DMA. * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param channel DMA channel * @param addr Address of the beginning DMA descriptor. */ -static inline void spi_dma_ll_tx_start(spi_dma_dev_t *dma_out, lldesc_t *addr) +static inline void spi_dma_ll_tx_start(spi_dma_dev_t *dma_out, uint32_t channel, lldesc_t *addr) { dma_out->dma_out_link.addr = (int) addr & 0xFFFFF; dma_out->dma_out_link.start = 1; @@ -1017,9 +1023,10 @@ static inline void spi_dma_ll_tx_start(spi_dma_dev_t *dma_out, lldesc_t *addr) * Enable DMA TX channel burst for data * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param channel DMA channel * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_tx_enable_burst_data(spi_dma_dev_t *dma_out, bool enable) +static inline void spi_dma_ll_tx_enable_burst_data(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) { dma_out->dma_conf.out_data_burst_en = enable; } @@ -1028,9 +1035,10 @@ static inline void spi_dma_ll_tx_enable_burst_data(spi_dma_dev_t *dma_out, bool * Enable DMA TX channel burst for descriptor * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param channel DMA channel * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_tx_enable_burst_desc(spi_dma_dev_t *dma_out, bool enable) +static inline void spi_dma_ll_tx_enable_burst_desc(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) { dma_out->dma_conf.outdscr_burst_en = enable; } @@ -1039,9 +1047,10 @@ static inline void spi_dma_ll_tx_enable_burst_desc(spi_dma_dev_t *dma_out, bool * Configuration of OUT EOF flag generation way * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param channel DMA channel * @param enable 1: when dma pop all data from fifo 0:when ahb push all data to fifo. */ -static inline void spi_dma_ll_set_out_eof_generation(spi_dma_dev_t *dma_out, bool enable) +static inline void spi_dma_ll_set_out_eof_generation(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) { dma_out->dma_conf.out_eof_mode = enable; } @@ -1050,9 +1059,10 @@ static inline void spi_dma_ll_set_out_eof_generation(spi_dma_dev_t *dma_out, boo * Enable automatic outlink-writeback * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param channel DMA channel * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_enable_out_auto_wrback(spi_dma_dev_t *dma_out, bool enable) +static inline void spi_dma_ll_enable_out_auto_wrback(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) { //does not configure it in ESP32 } diff --git a/components/hal/esp32s2/include/hal/spi_ll.h b/components/hal/esp32s2/include/hal/spi_ll.h index 022cc3f316..6a1090a34c 100644 --- a/components/hal/esp32s2/include/hal/spi_ll.h +++ b/components/hal/esp32s2/include/hal/spi_ll.h @@ -1080,10 +1080,10 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t* hw) /** * Reset RX DMA which stores the data received from a peripheral into RAM. * - * @param hw Beginning address of the peripheral registers. - * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + * @param channel DMA channel */ -static inline void spi_dma_ll_rx_reset(spi_dma_dev_t *dma_in) +static inline void spi_dma_ll_rx_reset(spi_dma_dev_t *dma_in, uint32_t channel) { //Reset RX DMA peripheral dma_in->dma_in_link.dma_rx_ena = 0; @@ -1096,10 +1096,11 @@ static inline void spi_dma_ll_rx_reset(spi_dma_dev_t *dma_in) /** * Start RX DMA. * - * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. - * @param addr Address of the beginning DMA descriptor. + * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + * @param channel DMA channel + * @param addr Address of the beginning DMA descriptor. */ -static inline void spi_dma_ll_rx_start(spi_dma_dev_t *dma_in, lldesc_t *addr) +static inline void spi_dma_ll_rx_start(spi_dma_dev_t *dma_in, uint32_t channel, lldesc_t *addr) { dma_in->dma_in_link.addr = (int) addr & 0xFFFFF; dma_in->dma_in_link.start = 1; @@ -1109,9 +1110,10 @@ static inline void spi_dma_ll_rx_start(spi_dma_dev_t *dma_in, lldesc_t *addr) * Enable DMA RX channel burst for data * * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + * @param channel DMA channel * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_rx_enable_burst_data(spi_dma_dev_t *dma_in, bool enable) +static inline void spi_dma_ll_rx_enable_burst_data(spi_dma_dev_t *dma_in, uint32_t channel, bool enable) { //This is not supported in esp32s2 } @@ -1119,10 +1121,11 @@ static inline void spi_dma_ll_rx_enable_burst_data(spi_dma_dev_t *dma_in, bool e /** * Enable DMA TX channel burst for descriptor * - * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. + * @param channel DMA channel * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_rx_enable_burst_desc(spi_dma_dev_t *dma_in, bool enable) +static inline void spi_dma_ll_rx_enable_burst_desc(spi_dma_dev_t *dma_in, uint32_t channel, bool enable) { dma_in->dma_conf.indscr_burst_en = enable; } @@ -1130,10 +1133,10 @@ static inline void spi_dma_ll_rx_enable_burst_desc(spi_dma_dev_t *dma_in, bool e /** * Reset TX DMA which transmits the data from RAM to a peripheral. * - * @param hw Beginning address of the peripheral registers. * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param channel DMA channel */ -static inline void spi_dma_ll_tx_reset(spi_dma_dev_t *dma_out) +static inline void spi_dma_ll_tx_reset(spi_dma_dev_t *dma_out, uint32_t channel) { //Reset TX DMA peripheral dma_out->dma_conf.out_rst = 1; @@ -1144,9 +1147,10 @@ static inline void spi_dma_ll_tx_reset(spi_dma_dev_t *dma_out) * Start TX DMA. * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. - * @param addr Address of the beginning DMA descriptor. + * @param channel DMA channel + * @param addr Address of the beginning DMA descriptor. */ -static inline void spi_dma_ll_tx_start(spi_dma_dev_t *dma_out, lldesc_t *addr) +static inline void spi_dma_ll_tx_start(spi_dma_dev_t *dma_out, uint32_t channel, lldesc_t *addr) { dma_out->dma_out_link.addr = (int) addr & 0xFFFFF; dma_out->dma_out_link.start = 1; @@ -1156,9 +1160,10 @@ static inline void spi_dma_ll_tx_start(spi_dma_dev_t *dma_out, lldesc_t *addr) * Enable DMA TX channel burst for data * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param channel DMA channel * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_tx_enable_burst_data(spi_dma_dev_t *dma_out, bool enable) +static inline void spi_dma_ll_tx_enable_burst_data(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) { dma_out->dma_conf.out_data_burst_en = enable; } @@ -1167,9 +1172,10 @@ static inline void spi_dma_ll_tx_enable_burst_data(spi_dma_dev_t *dma_out, bool * Enable DMA TX channel burst for descriptor * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param channel DMA channel * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_tx_enable_burst_desc(spi_dma_dev_t *dma_out, bool enable) +static inline void spi_dma_ll_tx_enable_burst_desc(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) { dma_out->dma_conf.outdscr_burst_en = enable; } @@ -1178,9 +1184,10 @@ static inline void spi_dma_ll_tx_enable_burst_desc(spi_dma_dev_t *dma_out, bool * Configuration of OUT EOF flag generation way * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param channel DMA channel * @param enable 1: when dma pop all data from fifo 0:when ahb push all data to fifo. */ -static inline void spi_dma_ll_set_out_eof_generation(spi_dma_dev_t *dma_out, bool enable) +static inline void spi_dma_ll_set_out_eof_generation(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) { dma_out->dma_conf.out_eof_mode = enable; } @@ -1189,19 +1196,20 @@ static inline void spi_dma_ll_set_out_eof_generation(spi_dma_dev_t *dma_out, boo * Enable automatic outlink-writeback * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. + * @param channel DMA channel * @param enable True to enable, false to disable */ -static inline void spi_dma_ll_enable_out_auto_wrback(spi_dma_dev_t *dma_out, bool enable) +static inline void spi_dma_ll_enable_out_auto_wrback(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) { dma_out->dma_conf.out_auto_wrback = enable; } -static inline void spi_dma_ll_rx_restart(spi_dma_dev_t *dma_in) +static inline void spi_dma_ll_rx_restart(spi_dma_dev_t *dma_in, uint32_t channel) { dma_in->dma_in_link.restart = 1; } -static inline void spi_dma_ll_tx_restart(spi_dma_dev_t *dma_out) +static inline void spi_dma_ll_tx_restart(spi_dma_dev_t *dma_out, uint32_t channel) { dma_out->dma_out_link.restart = 1; } diff --git a/components/hal/include/hal/spi_hal.h b/components/hal/include/hal/spi_hal.h index bba02465ef..ec23ee0d1a 100644 --- a/components/hal/include/hal/spi_hal.h +++ b/components/hal/include/hal/spi_hal.h @@ -72,6 +72,7 @@ typedef struct { typedef struct { spi_dma_dev_t *dma_in; ///< Input DMA(DMA -> RAM) peripheral register address spi_dma_dev_t *dma_out; ///< Output DMA(RAM -> DMA) peripheral register address + bool dma_enabled; ///< Whether the DMA is enabled, do not update after initialization lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the TX DMA. * The amount should be larger than dmadesc_n. The driver should ensure that * the data to be sent is shorter than the descriptors can hold. @@ -80,8 +81,10 @@ typedef struct { * The amount should be larger than dmadesc_n. The driver should ensure that * the data to be sent is shorter than the descriptors can hold. */ + uint32_t tx_dma_chan; ///< TX DMA channel + uint32_t rx_dma_chan; ///< RX DMA channel int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use. -} spi_hal_dma_config_t; +} spi_hal_config_t; /** * Transaction configuration structure, this should be assigned by driver each time. @@ -104,12 +107,24 @@ typedef struct { * Context that should be maintained by both the driver and the HAL. */ typedef struct { + /* These two need to be malloced by the driver first */ + lldesc_t *dmadesc_tx; /**< Array of DMA descriptor used by the TX DMA. + * The amount should be larger than dmadesc_n. The driver should ensure that + * the data to be sent is shorter than the descriptors can hold. + */ + lldesc_t *dmadesc_rx; /**< Array of DMA descriptor used by the RX DMA. + * The amount should be larger than dmadesc_n. The driver should ensure that + * the data to be sent is shorter than the descriptors can hold. + */ + /* Configured by driver at initialization, don't touch */ spi_dev_t *hw; ///< Beginning address of the peripheral registers. spi_dma_dev_t *dma_in; ///< Address of the DMA peripheral registers which stores the data received from a peripheral into RAM (DMA -> RAM). spi_dma_dev_t *dma_out; ///< Address of the DMA peripheral registers which transmits the data from RAM to a peripheral (RAM -> DMA). bool dma_enabled; ///< Whether the DMA is enabled, do not update after initialization - spi_hal_dma_config_t dma_config; ///< DMA configuration + uint32_t tx_dma_chan; ///< TX DMA channel + uint32_t rx_dma_chan; ///< RX DMA channel + int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use. /* Internal parameters, don't touch */ spi_hal_trans_config_t trans_config; ///< Transaction configuration @@ -144,10 +159,11 @@ typedef struct { /** * Init the peripheral and the context. * - * @param hal Context of the HAL layer. - * @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for HSPI (SPI2) and 2 for VSPI (SPI3). + * @param hal Context of the HAL layer. + * @param host_id Index of the SPI peripheral. 0 for SPI1, 1 for HSPI (SPI2) and 2 for VSPI (SPI3). + * @param hal_config Configuration of the hal defined by the upper layer. */ -void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id, const spi_hal_dma_config_t *hal_dma_config); +void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id, const spi_hal_config_t *hal_config); /** * Deinit the peripheral (and the context if needed). diff --git a/components/hal/include/hal/spi_slave_hal.h b/components/hal/include/hal/spi_slave_hal.h index b6d2ad5b35..ba03c28b7f 100644 --- a/components/hal/include/hal/spi_slave_hal.h +++ b/components/hal/include/hal/spi_slave_hal.h @@ -55,7 +55,9 @@ typedef struct { * The amount should be larger than dmadesc_n. The driver should ensure that * the data to be sent is shorter than the descriptors can hold. */ - int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use. + int dmadesc_n; ///< The amount of descriptors of both ``dmadesc_tx`` and ``dmadesc_rx`` that the HAL can use. + uint32_t tx_dma_chan; ///< TX DMA channel + uint32_t rx_dma_chan; ///< RX DMA channel /* * configurations to be filled after ``spi_slave_hal_init``. Updated to diff --git a/components/hal/include/hal/spi_slave_hd_hal.h b/components/hal/include/hal/spi_slave_hd_hal.h index 5c8458c9e9..de38ee42fa 100644 --- a/components/hal/include/hal/spi_slave_hd_hal.h +++ b/components/hal/include/hal/spi_slave_hd_hal.h @@ -70,7 +70,9 @@ typedef struct { uint32_t host_id; ///< Host ID of the spi peripheral spi_dma_dev_t *dma_in; ///< Input DMA(DMA -> RAM) peripheral register address spi_dma_dev_t *dma_out; ///< Output DMA(RAM -> DMA) peripheral register address - uint32_t dma_chan; ///< The dma channel used. + bool dma_enabled; ///< DMA enabled or not + uint32_t tx_dma_chan; ///< TX DMA channel used. + uint32_t rx_dma_chan; ///< RX DMA channel used. bool append_mode; ///< True for DMA append mode, false for segment mode uint32_t spics_io_num; ///< CS GPIO pin for this device uint8_t mode; ///< SPI mode (0-3) @@ -94,7 +96,9 @@ typedef struct { spi_dev_t *dev; ///< Beginning address of the peripheral registers. spi_dma_dev_t *dma_in; ///< Address of the DMA peripheral registers which stores the data received from a peripheral into RAM. spi_dma_dev_t *dma_out; ///< Address of the DMA peripheral registers which transmits the data from RAM to a peripheral. - + bool dma_enabled; ///< DMA enabled or not + uint32_t tx_dma_chan; ///< TX DMA channel used. + uint32_t rx_dma_chan; ///< RX DMA channel used. bool append_mode; ///< True for DMA append mode, false for segment mode uint32_t dma_desc_num; ///< Number of the available DMA descriptors. Calculated from ``bus_max_transfer_size``. spi_slave_hd_hal_desc_append_t *tx_cur_desc; ///< Current TX DMA descriptor that could be linked (set up). diff --git a/components/hal/spi_hal.c b/components/hal/spi_hal.c index c76529d7cf..b5b6e2168a 100644 --- a/components/hal/spi_hal.c +++ b/components/hal/spi_hal.c @@ -22,12 +22,12 @@ #include "soc/gdma_struct.h" #include "hal/gdma_ll.h" -#define spi_dma_ll_rx_enable_burst_data(dev, enable) gdma_ll_rx_enable_data_burst(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, enable); -#define spi_dma_ll_tx_enable_burst_data(dev, enable) gdma_ll_tx_enable_data_burst(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, enable); -#define spi_dma_ll_rx_enable_burst_desc(dev, enable) gdma_ll_rx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, enable); -#define spi_dma_ll_tx_enable_burst_desc(dev, enable) gdma_ll_tx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, enable); -#define spi_dma_ll_enable_out_auto_wrback(dev, enable) gdma_ll_tx_enable_auto_write_back(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, enable); -#define spi_dma_ll_set_out_eof_generation(dev, enable) gdma_ll_tx_set_eof_mode(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, enable); +#define spi_dma_ll_rx_enable_burst_data(dev, chan, enable) gdma_ll_rx_enable_data_burst(&GDMA, chan, enable); +#define spi_dma_ll_tx_enable_burst_data(dev, chan, enable) gdma_ll_tx_enable_data_burst(&GDMA, chan, enable); +#define spi_dma_ll_rx_enable_burst_desc(dev, chan, enable) gdma_ll_rx_enable_descriptor_burst(&GDMA, chan, enable); +#define spi_dma_ll_tx_enable_burst_desc(dev, chan, enable) gdma_ll_tx_enable_descriptor_burst(&GDMA, chan, enable); +#define spi_dma_ll_enable_out_auto_wrback(dev, chan, enable) gdma_ll_tx_enable_auto_write_back(&GDMA, chan, enable); +#define spi_dma_ll_set_out_eof_generation(dev, chan, enable) gdma_ll_tx_set_eof_mode(&GDMA, chan, enable); #endif static const char SPI_HAL_TAG[] = "spi_hal"; @@ -39,19 +39,25 @@ static const char SPI_HAL_TAG[] = "spi_hal"; static void s_spi_hal_dma_init_config(const spi_hal_context_t *hal) { - spi_dma_ll_rx_enable_burst_data(hal->dma_in, 1); - spi_dma_ll_tx_enable_burst_data(hal->dma_out, 1); - spi_dma_ll_rx_enable_burst_desc(hal->dma_in, 1); - spi_dma_ll_tx_enable_burst_desc(hal->dma_out, 1); + spi_dma_ll_rx_enable_burst_data(hal->dma_in, hal->rx_dma_chan, 1); + spi_dma_ll_tx_enable_burst_data(hal->dma_out, hal->tx_dma_chan, 1); + spi_dma_ll_rx_enable_burst_desc(hal->dma_in, hal->rx_dma_chan, 1); + spi_dma_ll_tx_enable_burst_desc(hal->dma_out, hal->tx_dma_chan ,1); } -void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id, const spi_hal_dma_config_t *dma_config) +void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id, const spi_hal_config_t *config) { memset(hal, 0, sizeof(spi_hal_context_t)); spi_dev_t *hw = SPI_LL_GET_HW(host_id); hal->hw = hw; - hal->dma_in = dma_config->dma_in; - hal->dma_out = dma_config->dma_out; + hal->dma_in = config->dma_in; + hal->dma_out = config->dma_out; + hal->dma_enabled = config->dma_enabled; + hal->dmadesc_tx = config->dmadesc_tx; + hal->dmadesc_rx = config->dmadesc_rx; + hal->tx_dma_chan = config->tx_dma_chan; + hal->rx_dma_chan = config->rx_dma_chan; + hal->dmadesc_n = config->dmadesc_n; spi_ll_master_init(hw); s_spi_hal_dma_init_config(hal); @@ -63,9 +69,6 @@ void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id, const spi_hal_dma_co spi_ll_enable_int(hw); spi_ll_set_int_stat(hw); spi_ll_set_mosi_delay(hw, 0, 0); - - //Save the dma configuration in ``spi_hal_context_t`` - memcpy(&hal->dma_config, dma_config, sizeof(spi_hal_dma_config_t)); } void spi_hal_deinit(spi_hal_context_t *hal) diff --git a/components/hal/spi_hal_iram.c b/components/hal/spi_hal_iram.c index 821c26e543..dcbbe4753c 100644 --- a/components/hal/spi_hal_iram.c +++ b/components/hal/spi_hal_iram.c @@ -23,15 +23,15 @@ #include "soc/gdma_struct.h" #include "hal/gdma_ll.h" -#define spi_dma_ll_rx_reset(dev) gdma_ll_rx_reset_channel(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL) -#define spi_dma_ll_tx_reset(dev) gdma_ll_tx_reset_channel(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL); -#define spi_dma_ll_rx_start(dev, addr) do {\ - gdma_ll_rx_set_desc_addr(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, (uint32_t)addr);\ - gdma_ll_rx_start(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL);\ +#define spi_dma_ll_rx_reset(dev, chan) gdma_ll_rx_reset_channel(&GDMA, chan) +#define spi_dma_ll_tx_reset(dev, chan) gdma_ll_tx_reset_channel(&GDMA, chan); +#define spi_dma_ll_rx_start(dev, chan, addr) do {\ + gdma_ll_rx_set_desc_addr(&GDMA, chan, (uint32_t)addr);\ + gdma_ll_rx_start(&GDMA, chan);\ } while (0) -#define spi_dma_ll_tx_start(dev, addr) do {\ - gdma_ll_tx_set_desc_addr(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL, (uint32_t)addr);\ - gdma_ll_tx_start(&GDMA, SOC_GDMA_SPI2_DMA_CHANNEL);\ +#define spi_dma_ll_tx_start(dev, chan, addr) do {\ + gdma_ll_tx_set_desc_addr(&GDMA, chan, (uint32_t)addr);\ + gdma_ll_tx_start(&GDMA, chan);\ } while (0) #endif @@ -143,12 +143,12 @@ void spi_hal_prepare_data(spi_hal_context_t *hal, const spi_hal_dev_config_t *de if (!hal->dma_enabled) { //No need to setup anything; we'll copy the result out of the work registers directly later. } else { - lldesc_setup_link(hal->dma_config.dmadesc_rx, trans->rcv_buffer, ((trans->rx_bitlen + 7) / 8), true); + lldesc_setup_link(hal->dmadesc_rx, trans->rcv_buffer, ((trans->rx_bitlen + 7) / 8), true); - spi_dma_ll_rx_reset(hal->dma_in); + spi_dma_ll_rx_reset(hal->dma_in, hal->rx_dma_chan); spi_ll_dma_rx_fifo_reset(hal->dma_in); spi_ll_dma_rx_enable(hal->hw, 1); - spi_dma_ll_rx_start(hal->dma_in, hal->dma_config.dmadesc_rx); + spi_dma_ll_rx_start(hal->dma_in, hal->rx_dma_chan, hal->dmadesc_rx); } } @@ -157,7 +157,7 @@ void spi_hal_prepare_data(spi_hal_context_t *hal, const spi_hal_dev_config_t *de //DMA temporary workaround: let RX DMA work somehow to avoid the issue in ESP32 v0/v1 silicon if (hal->dma_enabled && !dev->half_duplex) { spi_ll_dma_rx_enable(hal->hw, 1); - spi_dma_ll_rx_start(hal->dma_in, 0); + spi_dma_ll_rx_start(hal->dma_in, hal->rx_dma_chan, 0); } } #endif @@ -167,12 +167,12 @@ void spi_hal_prepare_data(spi_hal_context_t *hal, const spi_hal_dev_config_t *de //Need to copy data to registers manually spi_ll_write_buffer(hw, trans->send_buffer, trans->tx_bitlen); } else { - lldesc_setup_link(hal->dma_config.dmadesc_tx, trans->send_buffer, (trans->tx_bitlen + 7) / 8, false); + lldesc_setup_link(hal->dmadesc_tx, trans->send_buffer, (trans->tx_bitlen + 7) / 8, false); - spi_dma_ll_tx_reset(hal->dma_out); + spi_dma_ll_tx_reset(hal->dma_out, hal->tx_dma_chan); spi_ll_dma_tx_fifo_reset(hal->dma_in); spi_ll_dma_tx_enable(hal->hw, 1); - spi_dma_ll_tx_start(hal->dma_out, hal->dma_config.dmadesc_tx); + spi_dma_ll_tx_start(hal->dma_out, hal->tx_dma_chan, hal->dmadesc_tx); } } diff --git a/components/hal/spi_slave_hal.c b/components/hal/spi_slave_hal.c index 1b4beddf36..04982f1a7e 100644 --- a/components/hal/spi_slave_hal.c +++ b/components/hal/spi_slave_hal.c @@ -7,20 +7,20 @@ #include "soc/gdma_struct.h" #include "hal/gdma_ll.h" -#define spi_dma_ll_rx_enable_burst_data(dev, enable) gdma_ll_rx_enable_data_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); -#define spi_dma_ll_tx_enable_burst_data(dev, enable) gdma_ll_tx_enable_data_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); -#define spi_dma_ll_rx_enable_burst_desc(dev, enable) gdma_ll_rx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); -#define spi_dma_ll_tx_enable_burst_desc(dev, enable) gdma_ll_tx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); -#define spi_dma_ll_enable_out_auto_wrback(dev, enable) gdma_ll_tx_enable_auto_write_back(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); -#define spi_dma_ll_set_out_eof_generation(dev, enable) gdma_ll_tx_set_eof_mode(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); +#define spi_dma_ll_rx_enable_burst_data(dev, chan, enable) gdma_ll_rx_enable_data_burst(&GDMA, chan, enable); +#define spi_dma_ll_tx_enable_burst_data(dev, chan, enable) gdma_ll_tx_enable_data_burst(&GDMA, chan, enable); +#define spi_dma_ll_rx_enable_burst_desc(dev, chan, enable) gdma_ll_rx_enable_descriptor_burst(&GDMA, chan, enable); +#define spi_dma_ll_tx_enable_burst_desc(dev, chan, enable) gdma_ll_tx_enable_descriptor_burst(&GDMA, chan, enable); +#define spi_dma_ll_enable_out_auto_wrback(dev, chan, enable) gdma_ll_tx_enable_auto_write_back(&GDMA, chan, enable); +#define spi_dma_ll_set_out_eof_generation(dev, chan, enable) gdma_ll_tx_set_eof_mode(&GDMA, chan, enable); #endif static void s_spi_slave_hal_dma_init_config(const spi_slave_hal_context_t *hal) { - spi_dma_ll_rx_enable_burst_data(hal->dma_in, 1); - spi_dma_ll_tx_enable_burst_data(hal->dma_out, 1); - spi_dma_ll_rx_enable_burst_desc(hal->dma_in, 1); - spi_dma_ll_tx_enable_burst_desc(hal->dma_out, 1); + spi_dma_ll_rx_enable_burst_data(hal->dma_in, hal->rx_dma_chan, 1); + spi_dma_ll_tx_enable_burst_data(hal->dma_out, hal->tx_dma_chan, 1); + spi_dma_ll_rx_enable_burst_desc(hal->dma_in, hal->rx_dma_chan, 1); + spi_dma_ll_tx_enable_burst_desc(hal->dma_out, hal->tx_dma_chan, 1); } void spi_slave_hal_init(spi_slave_hal_context_t *hal, const spi_slave_hal_config_t *hal_config) diff --git a/components/hal/spi_slave_hal_iram.c b/components/hal/spi_slave_hal_iram.c index dbfe9f070e..5fb3f4dd1a 100644 --- a/components/hal/spi_slave_hal_iram.c +++ b/components/hal/spi_slave_hal_iram.c @@ -7,15 +7,15 @@ #include "soc/gdma_struct.h" #include "hal/gdma_ll.h" -#define spi_dma_ll_rx_reset(dev) gdma_ll_rx_reset_channel(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL) -#define spi_dma_ll_tx_reset(dev) gdma_ll_tx_reset_channel(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL); -#define spi_dma_ll_rx_start(dev, addr) do {\ - gdma_ll_rx_set_desc_addr(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, (uint32_t)addr);\ - gdma_ll_rx_start(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);\ +#define spi_dma_ll_rx_reset(dev, chan) gdma_ll_rx_reset_channel(&GDMA, chan) +#define spi_dma_ll_tx_reset(dev, chan) gdma_ll_tx_reset_channel(&GDMA, chan); +#define spi_dma_ll_rx_start(dev, chan, addr) do {\ + gdma_ll_rx_set_desc_addr(&GDMA, chan, (uint32_t)addr);\ + gdma_ll_rx_start(&GDMA, chan);\ } while (0) -#define spi_dma_ll_tx_start(dev, addr) do {\ - gdma_ll_tx_set_desc_addr(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, (uint32_t)addr);\ - gdma_ll_tx_start(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);\ +#define spi_dma_ll_tx_start(dev, chan, addr) do {\ + gdma_ll_tx_set_desc_addr(&GDMA, chan, (uint32_t)addr);\ + gdma_ll_tx_start(&GDMA, chan);\ } while (0) #endif @@ -39,24 +39,24 @@ void spi_slave_hal_prepare_data(const spi_slave_hal_context_t *hal) lldesc_setup_link(hal->dmadesc_rx, hal->rx_buffer, ((hal->bitlen + 7) / 8), true); //reset dma inlink, this should be reset before spi related reset - spi_dma_ll_rx_reset(hal->dma_in); + spi_dma_ll_rx_reset(hal->dma_in, hal->rx_dma_chan); spi_ll_dma_rx_fifo_reset(hal->dma_in); spi_ll_slave_reset(hal->hw); spi_ll_infifo_full_clr(hal->hw); spi_ll_dma_rx_enable(hal->hw, 1); - spi_dma_ll_rx_start(hal->dma_in, &hal->dmadesc_rx[0]); + spi_dma_ll_rx_start(hal->dma_in, hal->rx_dma_chan, &hal->dmadesc_rx[0]); } if (hal->tx_buffer) { lldesc_setup_link(hal->dmadesc_tx, hal->tx_buffer, (hal->bitlen + 7) / 8, false); //reset dma outlink, this should be reset before spi related reset - spi_dma_ll_tx_reset(hal->dma_out); + spi_dma_ll_tx_reset(hal->dma_out, hal->tx_dma_chan); spi_ll_dma_tx_fifo_reset(hal->dma_out); spi_ll_slave_reset(hal->hw); spi_ll_outfifo_empty_clr(hal->hw); spi_ll_dma_tx_enable(hal->hw, 1); - spi_dma_ll_tx_start(hal->dma_out, (&hal->dmadesc_tx[0])); + spi_dma_ll_tx_start(hal->dma_out, hal->tx_dma_chan, (&hal->dmadesc_tx[0])); } } else { //No DMA. Turn off SPI and copy data to transmit buffers. diff --git a/components/hal/spi_slave_hd_hal.c b/components/hal/spi_slave_hd_hal.c index 3727bb15eb..fe1054441c 100644 --- a/components/hal/spi_slave_hd_hal.c +++ b/components/hal/spi_slave_hd_hal.c @@ -29,31 +29,31 @@ #include "soc/gdma_struct.h" #include "hal/gdma_ll.h" -#define spi_dma_ll_rx_reset(dev) gdma_ll_rx_reset_channel(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL) -#define spi_dma_ll_tx_reset(dev) gdma_ll_tx_reset_channel(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL); -#define spi_dma_ll_rx_enable_burst_data(dev, enable) gdma_ll_rx_enable_data_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); -#define spi_dma_ll_tx_enable_burst_data(dev, enable) gdma_ll_tx_enable_data_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); -#define spi_dma_ll_rx_enable_burst_desc(dev, enable) gdma_ll_rx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); -#define spi_dma_ll_tx_enable_burst_desc(dev, enable) gdma_ll_tx_enable_descriptor_burst(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); -#define spi_dma_ll_enable_out_auto_wrback(dev, enable) gdma_ll_tx_enable_auto_write_back(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); -#define spi_dma_ll_set_out_eof_generation(dev, enable) gdma_ll_tx_set_eof_mode(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, enable); -#define spi_dma_ll_rx_start(dev, addr) do {\ - gdma_ll_rx_set_desc_addr(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, (uint32_t)addr);\ - gdma_ll_rx_start(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);\ +#define spi_dma_ll_rx_reset(dev, chan) gdma_ll_rx_reset_channel(&GDMA, chan) +#define spi_dma_ll_tx_reset(dev, chan) gdma_ll_tx_reset_channel(&GDMA, chan); +#define spi_dma_ll_rx_enable_burst_data(dev, chan, enable) gdma_ll_rx_enable_data_burst(&GDMA, chan, enable); +#define spi_dma_ll_tx_enable_burst_data(dev, chan, enable) gdma_ll_tx_enable_data_burst(&GDMA, chan, enable); +#define spi_dma_ll_rx_enable_burst_desc(dev, chan, enable) gdma_ll_rx_enable_descriptor_burst(&GDMA, chan, enable); +#define spi_dma_ll_tx_enable_burst_desc(dev, chan, enable) gdma_ll_tx_enable_descriptor_burst(&GDMA, chan, enable); +#define spi_dma_ll_enable_out_auto_wrback(dev, chan, enable) gdma_ll_tx_enable_auto_write_back(&GDMA, chan, enable); +#define spi_dma_ll_set_out_eof_generation(dev, chan, enable) gdma_ll_tx_set_eof_mode(&GDMA, chan, enable); +#define spi_dma_ll_rx_start(dev, chan, addr) do {\ + gdma_ll_rx_set_desc_addr(&GDMA, chan, (uint32_t)addr);\ + gdma_ll_rx_start(&GDMA, chan);\ } while (0) -#define spi_dma_ll_tx_start(dev, addr) do {\ - gdma_ll_tx_set_desc_addr(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL, (uint32_t)addr);\ - gdma_ll_tx_start(&GDMA, SOC_GDMA_SPI3_DMA_CHANNEL);\ +#define spi_dma_ll_tx_start(dev, chan, addr) do {\ + gdma_ll_tx_set_desc_addr(&GDMA, chan, (uint32_t)addr);\ + gdma_ll_tx_start(&GDMA, chan);\ } while (0) #endif static void s_spi_slave_hd_hal_dma_init_config(const spi_slave_hd_hal_context_t *hal) { - spi_dma_ll_rx_enable_burst_data(hal->dma_in, 1); - spi_dma_ll_tx_enable_burst_data(hal->dma_out, 1); - spi_dma_ll_rx_enable_burst_desc(hal->dma_in, 1); - spi_dma_ll_tx_enable_burst_desc(hal->dma_out, 1); - spi_dma_ll_enable_out_auto_wrback(hal->dma_out, 1); + spi_dma_ll_rx_enable_burst_data(hal->dma_in, hal->rx_dma_chan, 1); + spi_dma_ll_tx_enable_burst_data(hal->dma_out, hal->tx_dma_chan, 1); + spi_dma_ll_rx_enable_burst_desc(hal->dma_in, hal->rx_dma_chan, 1); + spi_dma_ll_tx_enable_burst_desc(hal->dma_out, hal->tx_dma_chan, 1); + spi_dma_ll_enable_out_auto_wrback(hal->dma_out, hal->tx_dma_chan, 1); } void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_hal_config_t *hal_config) @@ -62,6 +62,9 @@ void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_h hal->dev = hw; hal->dma_in = hal_config->dma_in; hal->dma_out = hal_config->dma_out; + hal->dma_enabled = hal_config->dma_enabled; + hal->tx_dma_chan = hal_config->tx_dma_chan; + hal->rx_dma_chan = hal_config->rx_dma_chan; hal->append_mode = hal_config->append_mode; hal->rx_cur_desc = hal->dmadesc_rx; hal->tx_cur_desc = hal->dmadesc_tx; @@ -75,7 +78,7 @@ void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_h spi_ll_set_dummy(hw, hal_config->dummy_bits); spi_ll_set_rx_lsbfirst(hw, hal_config->rx_lsbfirst); spi_ll_set_tx_lsbfirst(hw, hal_config->tx_lsbfirst); - spi_ll_slave_set_mode(hw, hal_config->mode, (hal_config->dma_chan != 0)); + spi_ll_slave_set_mode(hw, hal_config->mode, (hal_config->dma_enabled)); spi_ll_disable_intr(hw, UINT32_MAX); spi_ll_clear_intr(hw, UINT32_MAX); @@ -134,14 +137,14 @@ void spi_slave_hd_hal_rxdma(spi_slave_hd_hal_context_t *hal, uint8_t *out_buf, s lldesc_setup_link(&hal->dmadesc_rx->desc, out_buf, len, true); spi_ll_dma_rx_fifo_reset(hal->dev); - spi_dma_ll_rx_reset(hal->dma_in); + spi_dma_ll_rx_reset(hal->dma_in, hal->rx_dma_chan); spi_ll_slave_reset(hal->dev); spi_ll_infifo_full_clr(hal->dev); spi_ll_clear_intr(hal->dev, SPI_LL_INTR_CMD7); spi_ll_slave_set_rx_bitlen(hal->dev, len * 8); spi_ll_dma_rx_enable(hal->dev, 1); - spi_dma_ll_rx_start(hal->dma_in, &hal->dmadesc_rx->desc); + spi_dma_ll_rx_start(hal->dma_in, hal->rx_dma_chan, &hal->dmadesc_rx->desc); } void spi_slave_hd_hal_txdma(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len) @@ -149,13 +152,13 @@ void spi_slave_hd_hal_txdma(spi_slave_hd_hal_context_t *hal, uint8_t *data, size lldesc_setup_link(&hal->dmadesc_tx->desc, data, len, false); spi_ll_dma_tx_fifo_reset(hal->dev); - spi_dma_ll_tx_reset(hal->dma_out); + spi_dma_ll_tx_reset(hal->dma_out, hal->tx_dma_chan); spi_ll_slave_reset(hal->dev); spi_ll_outfifo_empty_clr(hal->dev); spi_ll_clear_intr(hal->dev, SPI_LL_INTR_CMD8); spi_ll_dma_tx_enable(hal->dev, 1); - spi_dma_ll_tx_start(hal->dma_out, &hal->dmadesc_tx->desc); + spi_dma_ll_tx_start(hal->dma_out, hal->tx_dma_chan, &hal->dmadesc_tx->desc); } static spi_ll_intr_t get_event_intr(spi_slave_hd_hal_context_t *hal, spi_event_t ev) @@ -333,18 +336,18 @@ esp_err_t spi_slave_hd_hal_txdma_append(spi_slave_hd_hal_context_t *hal, uint8_t hal->tx_dma_head = hal->tx_cur_desc; hal->tx_dma_tail = hal->tx_cur_desc; - spi_dma_ll_tx_reset(hal->dma_out); + spi_dma_ll_tx_reset(hal->dma_out, hal->tx_dma_chan); spi_ll_outfifo_empty_clr(hal->dev); spi_ll_clear_intr(hal->dev, SPI_LL_INTR_OUT_EOF); spi_ll_dma_tx_enable(hal->dev, 1); - spi_dma_ll_tx_start(hal->dma_out, &hal->tx_dma_head->desc); + spi_dma_ll_tx_start(hal->dma_out, hal->tx_dma_chan, &hal->tx_dma_head->desc); } else { //there is already a link STAILQ_NEXT(&hal->tx_dma_tail->desc, qe) = &hal->tx_cur_desc->desc; hal->tx_dma_tail = hal->tx_cur_desc; - spi_dma_ll_tx_restart(hal->dma_out); + spi_dma_ll_tx_restart(hal->dma_out, hal->tx_dma_chan); } //Move the current descriptor pointer according to the number of the linked descriptors @@ -376,18 +379,18 @@ esp_err_t spi_slave_hd_hal_rxdma_append(spi_slave_hd_hal_context_t *hal, uint8_t hal->rx_dma_head = hal->rx_cur_desc; hal->rx_dma_tail = hal->rx_cur_desc; - spi_dma_ll_rx_reset(hal->dma_in); + spi_dma_ll_rx_reset(hal->dma_in, hal->rx_dma_chan); spi_ll_infifo_full_clr(hal->dev); spi_ll_clear_intr(hal->dev, SPI_LL_INTR_CMD7); spi_ll_dma_rx_enable(hal->dev, 1); - spi_dma_ll_rx_start(hal->dma_in, &hal->rx_dma_head->desc); + spi_dma_ll_rx_start(hal->dma_in, hal->rx_dma_chan, &hal->rx_dma_head->desc); } else { //there is already a link STAILQ_NEXT(&hal->rx_dma_tail->desc, qe) = &hal->rx_cur_desc->desc; hal->rx_dma_tail = hal->rx_cur_desc; - spi_dma_ll_rx_restart(hal->dma_in); + spi_dma_ll_rx_restart(hal->dma_in, hal->rx_dma_chan); } //Move the current descriptor pointer according to the number of the linked descriptors diff --git a/components/soc/esp32c3/include/soc/spi_caps.h b/components/soc/esp32c3/include/soc/spi_caps.h index c3578456d8..fefb464f6f 100644 --- a/components/soc/esp32c3/include/soc/spi_caps.h +++ b/components/soc/esp32c3/include/soc/spi_caps.h @@ -14,7 +14,7 @@ #pragma once -#define SOC_SPI_PERIPH_NUM 4 +#define SOC_SPI_PERIPH_NUM 2 #define SOC_SPI_DMA_CHAN_NUM 3 #define SOC_SPI_PERIPH_CS_NUM(i) 3 From 97f248d22cb4bcf6e44203a356312a0051ff2926 Mon Sep 17 00:00:00 2001 From: Armando Date: Wed, 27 Jan 2021 21:56:52 +0800 Subject: [PATCH 3/6] spi: update unit tests to spi gdma allocator --- components/driver/test/test_spi_master.c | 166 ++++++++++++--------- components/driver/test/test_spi_param.c | 31 +++- components/driver/test/test_spi_slave.c | 4 + components/driver/test/test_spi_slave_hd.c | 8 + 4 files changed, 138 insertions(+), 71 deletions(-) diff --git a/components/driver/test/test_spi_master.c b/components/driver/test/test_spi_master.c index 434775a4e0..7a2681f475 100644 --- a/components/driver/test/test_spi_master.c +++ b/components/driver/test/test_spi_master.c @@ -74,7 +74,11 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]") .quadhd_io_num=-1 }; esp_err_t ret; - ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1); +#if !SOC_GDMA_SUPPORTED + ret = spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1); +#else + ret = spi_bus_initialize(TEST_SPI_HOST, &buscfg, -1); +#endif TEST_ASSERT(ret==ESP_OK); check_spi_pre_n_for(26000000, 1, 3); @@ -110,13 +114,14 @@ static spi_device_handle_t setup_spi_bus_loopback(int clkspeed, bool dma) { .spics_io_num=PIN_NUM_CS, .queue_size=3, }; - esp_err_t ret; spi_device_handle_t handle; - ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, dma?1:0); - TEST_ASSERT(ret==ESP_OK); - ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &handle); - TEST_ASSERT(ret==ESP_OK); +#if !SOC_GDMA_SUPPORTED + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, dma ? 1 : 0)); +#else + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, dma ? -1 : 0)); +#endif + TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &handle)); //connect MOSI to two devices breaks the output, fix it. spitest_gpio_output_sel(PIN_NUM_MOSI, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out); printf("Bus/dev inited.\n"); @@ -276,8 +281,14 @@ static esp_err_t test_master_pins(int mosi, int miso, int sclk, int cs) spi_device_interface_config_t master_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG(); master_cfg.spics_io_num = cs; +#if !SOC_GDMA_SUPPORTED ret = spi_bus_initialize(TEST_SPI_HOST, &cfg, 1); - if (ret != ESP_OK) return ret; +#else + ret = spi_bus_initialize(TEST_SPI_HOST, &cfg, -1); +#endif + if (ret != ESP_OK) { + return ret; + } spi_device_handle_t spi; ret = spi_bus_add_device(TEST_SPI_HOST, &master_cfg, &spi); @@ -301,8 +312,14 @@ static esp_err_t test_slave_pins(int mosi, int miso, int sclk, int cs) spi_slave_interface_config_t slave_cfg = SPI_SLAVE_TEST_DEFAULT_CONFIG(); slave_cfg.spics_io_num = cs; +#if !SOC_GDMA_SUPPORTED ret = spi_slave_initialize(TEST_SLAVE_HOST, &cfg, &slave_cfg, TEST_DMA_CHAN_SLAVE); - if (ret != ESP_OK) return ret; +#else + ret = spi_slave_initialize(TEST_SLAVE_HOST, &cfg, &slave_cfg, -1); +#endif + if (ret != ESP_OK) { + return ret; + } spi_slave_free(TEST_SLAVE_HOST); return ESP_OK; @@ -315,7 +332,6 @@ TEST_CASE("spi placed on input-only pins", "[spi]") TEST_ESP_OK(test_master_pins(PIN_NUM_MOSI, INPUT_ONLY_PIN, PIN_NUM_CLK, PIN_NUM_CS)); TEST_ASSERT(test_master_pins(PIN_NUM_MOSI, PIN_NUM_MISO, INPUT_ONLY_PIN, PIN_NUM_CS) != ESP_OK); TEST_ASSERT(test_master_pins(PIN_NUM_MOSI, PIN_NUM_MISO, PIN_NUM_CLK, INPUT_ONLY_PIN) != ESP_OK); - TEST_ESP_OK(test_slave_pins(PIN_NUM_MOSI, PIN_NUM_MISO, PIN_NUM_CLK, PIN_NUM_CS)); TEST_ESP_OK(test_slave_pins(INPUT_ONLY_PIN, PIN_NUM_MISO, PIN_NUM_CLK, PIN_NUM_CS)); TEST_ASSERT(test_slave_pins(PIN_NUM_MOSI, INPUT_ONLY_PIN, PIN_NUM_CLK, PIN_NUM_CS) != ESP_OK); @@ -336,18 +352,18 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_IOMUX_PINS | SPICOMMON_BUSFLAG_QUAD; cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); - TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); ESP_LOGI(TAG, "test 4 iomux output pins..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_IOMUX_PINS | SPICOMMON_BUSFLAG_DUAL; cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); - TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); ESP_LOGI(TAG, "test 6 output pins..."); @@ -355,9 +371,9 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") //swap MOSI and MISO cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); - TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); ESP_LOGI(TAG, "test 4 output pins..."); @@ -365,9 +381,9 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") //swap MOSI and MISO cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); - TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); #if !DISABLED_FOR_TARGETS(ESP32C3) //There is no input-only pin on esp32c3, so this test could be ignored. @@ -375,14 +391,14 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD | SPICOMMON_BUSFLAG_GPIO_PINS; cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); ESP_LOGI(TAG, "test slave 5 output pins and MISO on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD | SPICOMMON_BUSFLAG_GPIO_PINS; cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); ESP_LOGI(TAG, "test master 3 output pins and MOSI on input-only pin..."); @@ -390,14 +406,14 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); ESP_LOGI(TAG, "test slave 3 output pins and MISO on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_GPIO_PINS; cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); #endif @@ -406,72 +422,72 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") //swap MOSI and MISO cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check native flag for 4 output pins..."); flags_expected = SPICOMMON_BUSFLAG_IOMUX_PINS; //swap MOSI and MISO cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); #if !DISABLED_FOR_TARGETS(ESP32C3) //There is no input-only pin on esp32c3, so this test could be ignored. ESP_LOGI(TAG, "check dual flag for master 5 output pins and MISO/MOSI on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_DUAL | SPICOMMON_BUSFLAG_GPIO_PINS; cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check dual flag for master 3 output pins and MISO/MOSI on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_DUAL | SPICOMMON_BUSFLAG_GPIO_PINS; cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); #endif ESP_LOGI(TAG, "check sclk flag..."); flags_expected = SPICOMMON_BUSFLAG_SCLK; cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = -1, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check mosi flag..."); flags_expected = SPICOMMON_BUSFLAG_MOSI; cfg = (spi_bus_config_t){.mosi_io_num = -1, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check miso flag..."); flags_expected = SPICOMMON_BUSFLAG_MISO; cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = -1, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check quad flag..."); flags_expected = SPICOMMON_BUSFLAG_QUAD; cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); } TEST_CASE("SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)", "[spi]") @@ -507,30 +523,38 @@ TEST_CASE("SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)" //initialize for first host host = TEST_SPI_HOST; - TEST_ASSERT(spi_bus_initialize(host, &bus_config, GET_DMA_CHAN(host)) == ESP_OK); - TEST_ASSERT(spi_bus_add_device(host, &device_config, &spi) == ESP_OK); +#if !SOC_GDMA_SUPPORTED + TEST_ESP_OK(spi_bus_initialize(host, &bus_config, host)); +#else + TEST_ESP_OK(spi_bus_initialize(host, &bus_config, -1)); +#endif + TEST_ESP_OK(spi_bus_add_device(host, &device_config, &spi)); printf("before first xmit\n"); - TEST_ASSERT(spi_device_transmit(spi, &transaction) == ESP_OK); + TEST_ESP_OK(spi_device_transmit(spi, &transaction)); printf("after first xmit\n"); - TEST_ASSERT(spi_bus_remove_device(spi) == ESP_OK); - TEST_ASSERT(spi_bus_free(host) == ESP_OK); + TEST_ESP_OK(spi_bus_remove_device(spi)); + TEST_ESP_OK(spi_bus_free(host)); //for second host and failed before host = TEST_SLAVE_HOST; - TEST_ASSERT(spi_bus_initialize(host, &bus_config, GET_DMA_CHAN(host)) == ESP_OK); - TEST_ASSERT(spi_bus_add_device(host, &device_config, &spi) == ESP_OK); +#if !SOC_GDMA_SUPPORTED + TEST_ESP_OK(spi_bus_initialize(host, &bus_config, host)); +#else + TEST_ESP_OK(spi_bus_initialize(host, &bus_config, -1)); +#endif + TEST_ESP_OK(spi_bus_add_device(host, &device_config, &spi)); printf("before second xmit\n"); // the original version (bit mis-written) stucks here. - TEST_ASSERT(spi_device_transmit(spi, &transaction) == ESP_OK); + TEST_ESP_OK(spi_device_transmit(spi, &transaction)); // test case success when see this. printf("after second xmit\n"); - TEST_ASSERT(spi_bus_remove_device(spi) == ESP_OK); - TEST_ASSERT(spi_bus_free(host) == ESP_OK); + TEST_ESP_OK(spi_bus_remove_device(spi)); + TEST_ESP_OK(spi_bus_free(host)); } DRAM_ATTR static uint32_t data_dram[80]={0}; @@ -588,11 +612,13 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]") spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG(); //Initialize the SPI bus - ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1); - TEST_ASSERT(ret==ESP_OK); +#if !SOC_GDMA_SUPPORTED + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1)); +#else + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, -1)); +#endif //Attach the LCD to the SPI bus - ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &spi); - TEST_ASSERT(ret==ESP_OK); + TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &spi)); //connect MOSI to two devices breaks the output, fix it. spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out); @@ -658,7 +684,6 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]") uint8_t tx_buf[320]={0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0, 0xaa, 0xcc, 0xff, 0xee, 0x55, 0x77, 0x88, 0x43}; uint8_t rx_buf[320]; - esp_err_t ret; spi_device_handle_t spi; spi_bus_config_t buscfg={ .miso_io_num=PIN_NUM_MOSI, @@ -675,11 +700,13 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]") .pre_cb=NULL, }; //Initialize the SPI bus - ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1); - TEST_ASSERT(ret==ESP_OK); +#if !SOC_GDMA_SUPPORTED + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1)); +#else + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, -1)); +#endif //Attach the LCD to the SPI bus - ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &spi); - TEST_ASSERT(ret==ESP_OK); + TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &spi)); //connect MOSI to two devices breaks the output, fix it. spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out); @@ -746,7 +773,11 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first) //initial master, mode 0, 1MHz spi_bus_config_t buscfg=SPI_BUS_TEST_DEFAULT_CONFIG(); buscfg.quadhd_io_num = UNCONNECTED_PIN; +#if !SOC_GDMA_SUPPORTED TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1)); +#else + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, -1)); +#endif spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG(); devcfg.clock_speed_hz = 1*1000*1000; if (lsb_first) devcfg.flags |= SPI_DEVICE_BIT_LSBFIRST; @@ -1076,16 +1107,17 @@ TEST_CASE("SPI master hd dma TX without RX test", "[spi]") static void speed_setup(spi_device_handle_t* spi, bool use_dma) { - esp_err_t ret; spi_bus_config_t buscfg=SPI_BUS_TEST_DEFAULT_CONFIG(); spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG(); devcfg.queue_size=8; //We want to be able to queue 7 transactions at a time //Initialize the SPI bus and the device to test - ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, (use_dma? GET_DMA_CHAN(TEST_SPI_HOST): 0)); - TEST_ASSERT(ret==ESP_OK); - ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, spi); - TEST_ASSERT(ret==ESP_OK); +#if !SOC_GDMA_SUPPORTED + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, (use_dma? GET_DMA_CHAN(TEST_SPI_HOST): 0))); +#else + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, (use_dma? -1 : 0))); +#endif + TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, spi)); } static void sorted_array_insert(uint32_t* array, int* size, uint32_t item) diff --git a/components/driver/test/test_spi_param.c b/components/driver/test/test_spi_param.c index da3f37453e..90f9ab1859 100644 --- a/components/driver/test/test_spi_param.c +++ b/components/driver/test/test_spi_param.c @@ -100,12 +100,22 @@ static void local_test_start(spi_device_handle_t *spi, int freq, const spitest_p slave_pull_up(&buscfg, slvcfg.spics_io_num); - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, pset->master_dma_chan)); +#if !SOC_GDMA_SUPPORTED + int dma_chan = pset->master_dma_chan; +#else + int dma_chan = (pset->master_dma_chan == 0) ? 0 : -1; +#endif + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, dma_chan)); TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, spi)); //slave automatically use iomux pins if pins are on VSPI_* pins buscfg.quadhd_io_num = -1; - TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, pset->slave_dma_chan)); +#if !SOC_GDMA_SUPPORTED + int slave_dma_chan = pset->slave_dma_chan; +#else + int slave_dma_chan = (pset->slave_dma_chan == 0) ? 0 : -1; +#endif + TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, slave_dma_chan)); //initialize master and slave on the same pins break some of the output configs, fix them if (pset->master_iomux) { @@ -702,7 +712,15 @@ static void test_master_start(spi_device_handle_t *spi, int freq, const spitest_ devpset.input_delay_ns = pset->slave_tv_ns; devpset.clock_speed_hz = freq; if (pset->master_limit != 0 && freq > pset->master_limit) devpset.flags |= SPI_DEVICE_NO_DUMMY; - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buspset, pset->master_dma_chan)); + + + +#if !SOC_GDMA_SUPPORTED + int dma_chan = pset->master_dma_chan; +#else + int dma_chan = (pset->master_dma_chan == 0) ? 0 : -1; +#endif + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buspset, dma_chan)); TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devpset, spi)); //prepare data for the slave @@ -822,7 +840,12 @@ static void timing_slave_start(int speed, const spitest_param_set_t* pset, spite //Enable pull-ups on SPI lines so we don't detect rogue pulses when no master is connected. slave_pull_up(&slv_buscfg, slvcfg.spics_io_num); - TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &slv_buscfg, &slvcfg, pset->slave_dma_chan)); +#if !SOC_GDMA_SUPPORTED + int slave_dma_chan = pset->slave_dma_chan; +#else + int slave_dma_chan = (pset->slave_dma_chan == 0) ? 0 : -1; +#endif + TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &slv_buscfg, &slvcfg, slave_dma_chan)); //prepare data for the master for (int i = 0; i < pset->test_size; i++) { diff --git a/components/driver/test/test_spi_slave.c b/components/driver/test/test_spi_slave.c index 71ed6c449f..a37ce50d89 100644 --- a/components/driver/test/test_spi_slave.c +++ b/components/driver/test/test_spi_slave.c @@ -74,8 +74,12 @@ static void slave_init(void) gpio_set_pull_mode(PIN_NUM_MOSI, GPIO_PULLUP_ONLY); gpio_set_pull_mode(PIN_NUM_CLK, GPIO_PULLUP_ONLY); gpio_set_pull_mode(PIN_NUM_CS, GPIO_PULLUP_ONLY); +#if !SOC_GDMA_SUPPORTED //Initialize SPI slave interface TEST_ESP_OK( spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, 2) ); +#else + TEST_ESP_OK( spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, -1) ); +#endif } TEST_CASE("test slave send unaligned","[spi]") diff --git a/components/driver/test/test_spi_slave_hd.c b/components/driver/test/test_spi_slave_hd.c index 24f01a4942..d5d50638e4 100644 --- a/components/driver/test/test_spi_slave_hd.c +++ b/components/driver/test/test_spi_slave_hd.c @@ -99,7 +99,11 @@ static void init_master_hd(spi_device_handle_t* spi, const spitest_param_set_t* bus_cfg.flags |= SPICOMMON_BUSFLAG_GPIO_PINS; #endif +#if !SOC_GDMA_SUPPORTED TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, TEST_SPI_HOST)); +#else + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, -1)); +#endif spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG(); dev_cfg.flags = SPI_DEVICE_HALFDUPLEX; dev_cfg.command_bits = 8; @@ -122,7 +126,11 @@ static void init_slave_hd(int mode, bool append_mode, const spi_slave_hd_callbac #endif spi_slave_hd_slot_config_t slave_hd_cfg = SPI_SLOT_TEST_DEFAULT_CONFIG(); slave_hd_cfg.mode = mode; +#if !SOC_GDMA_SUPPORTED slave_hd_cfg.dma_chan = TEST_SLAVE_HOST; +#else + slave_hd_cfg.dma_chan = -1; +#endif if (append_mode) { slave_hd_cfg.flags |= SPI_SLAVE_HD_APPEND_MODE; } From 66d10f0eec18e708ad182b36b153fe3c840f1538 Mon Sep 17 00:00:00 2001 From: Armando Date: Wed, 3 Feb 2021 15:14:17 +0800 Subject: [PATCH 4/6] spi: refactor spi_common dma allocator --- components/driver/include/driver/spi_common.h | 21 +- .../include/driver/spi_common_internal.h | 22 +- components/driver/include/driver/spi_slave.h | 21 +- .../driver/include/driver/spi_slave_hd.h | 13 +- components/driver/spi_common.c | 237 ++++++++---------- components/driver/spi_master.c | 6 +- components/driver/spi_slave.c | 20 +- components/driver/spi_slave_hd.c | 25 +- components/driver/test/test_spi_master.c | 61 +---- components/driver/test/test_spi_param.c | 77 +++--- components/driver/test/test_spi_slave.c | 10 +- components/driver/test/test_spi_slave_hd.c | 12 +- components/hal/esp32/include/hal/spi_ll.h | 20 +- components/hal/esp32s2/include/hal/spi_ll.h | 20 +- components/hal/include/hal/spi_types.h | 2 +- 15 files changed, 233 insertions(+), 334 deletions(-) diff --git a/components/driver/include/driver/spi_common.h b/components/driver/include/driver/spi_common.h index cbb09ca7f8..3c5b599e63 100644 --- a/components/driver/include/driver/spi_common.h +++ b/components/driver/include/driver/spi_common.h @@ -29,6 +29,8 @@ extern "C" //Maximum amount of bytes that can be put in one DMA descriptor #define SPI_MAX_DMA_LEN (4096-4) +//Set the ``dma_chan`` to this, then driver will auto-alloc a DMA channel +#define DMA_AUTO_CHAN (-2) /** * Transform unsigned integer of length <= 32 bits to the format which can be @@ -103,13 +105,15 @@ typedef struct { * * @warning For now, only supports HSPI and VSPI. * - * @param host_id SPI peripheral that controls this bus - * @param bus_config Pointer to a spi_bus_config_t struct specifying how the host should be initialized - * @param dma_chan -1: auto dma allocate mode; 0: non-dma mode; 1 or 2: assign a specific DMA channel; - * Selecting a DMA channel for an SPI bus allows transfers on the bus to have sizes only - * limited by the amount of internal memory. Selecting no DMA channel (by passing the - * value 0) limits the amount of bytes transfered to a maximum of 64. Set to 0 if only - * the SPI flash uses this bus. Set -1 to let the driver to allocate the DMA channel. + * @param host_id SPI peripheral that controls this bus + * @param bus_config Pointer to a spi_bus_config_t struct specifying how the host should be initialized + * @param dma_chan - DMA_AUTO_CHAN: allocate a free channel automatically; + * - 1 or 2: assign a specific DMA channel; + * - 0: non-dma mode; + * Selecting a DMA channel for an SPI bus allows transfers on the bus to have sizes only + * limited by the amount of internal memory. Selecting no DMA channel (by passing the + * value 0) limits the amount of bytes transfered to a maximum of 64. Set to 0 if only + * the SPI flash uses this bus. Set to DMA_AUTO_CHAN to let the driver to allocate the DMA channel. * * @warning If a DMA channel is selected, any transmit and receive buffer used should be allocated in * DMA-capable memory. @@ -120,7 +124,8 @@ typedef struct { * * @return * - ESP_ERR_INVALID_ARG if configuration is invalid - * - ESP_ERR_INVALID_STATE if host already is in use or DMA channel is not available + * - ESP_ERR_INVALID_STATE if host already is in use + * - ESP_ERR_NOT_FOUND if there is no available DMA channel * - ESP_ERR_NO_MEM if out of memory * - ESP_OK on success */ diff --git a/components/driver/include/driver/spi_common_internal.h b/components/driver/include/driver/spi_common_internal.h index f5015bfbf4..ab0ed69dd9 100644 --- a/components/driver/include/driver/spi_common_internal.h +++ b/components/driver/include/driver/spi_common_internal.h @@ -118,41 +118,29 @@ bool spicommon_periph_in_use(spi_host_device_t host); bool spicommon_periph_free(spi_host_device_t host); /** - * @brief Check whether the spi DMA channel is in use. - * - * @param dma_chan DMA channel to check. - * - * @note This public API is deprecated. - * - * @return True if in use, otherwise false. - */ -bool spicommon_dma_chan_in_use(int dma_chan); - -/** - * @brief Configure DMA for SPI Slave + * @brief Alloc DMA for SPI Slave * * @param host_id SPI host ID - * @param dma_chan -1: auto dma allocate mode; 0: non-dma mode; 1 or 2: assign a specific DMA channel; + * @param dma_chan DMA_AUTO_CHAN: auto dma allocate mode; 0: non-dma mode; 1 or 2: assign a specific DMA channel; * @param[out] out_actual_tx_dma_chan Actual TX DMA channel (if you choose to assign a specific DMA channel, this will be the channel you assigned before) * @param[out] out_actual_rx_dma_chan Actual RX DMA channel (if you choose to assign a specific DMA channel, this will be the channel you assigned before) * * @return * - ESP_OK: On success * - ESP_ERR_NO_MEM: No enough memory - * - ESP_ERR_INVALID_STATE: Driver invalid state, check the log message for details + * - ESP_ERR_NOT_FOUND: There is no available DMA channel */ -esp_err_t spicommon_slave_alloc_dma(spi_host_device_t host_id, int dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan); +esp_err_t spicommon_slave_dma_chan_alloc(spi_host_device_t host_id, int dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan); /** * @brief Free DMA for SPI Slave * * @param host_id SPI host ID - * @param dma_chan Actual used DMA channel * * @return * - ESP_OK: On success */ -esp_err_t spicommon_slave_free_dma(spi_host_device_t host_id, int dma_chan); +esp_err_t spicommon_slave_free_dma(spi_host_device_t host_id); /** * @brief Connect a SPI peripheral to GPIO pins diff --git a/components/driver/include/driver/spi_slave.h b/components/driver/include/driver/spi_slave.h index 3bee13c264..ebb1268289 100644 --- a/components/driver/include/driver/spi_slave.h +++ b/components/driver/include/driver/spi_slave.h @@ -90,14 +90,16 @@ struct spi_slave_transaction_t { * * @warning For now, only supports HSPI and VSPI. * - * @param host SPI peripheral to use as a SPI slave interface - * @param bus_config Pointer to a spi_bus_config_t struct specifying how the host should be initialized - * @param slave_config Pointer to a spi_slave_interface_config_t struct specifying the details for the slave interface - * @param dma_chan -1: auto dma allocate mode; 0: non-dma mode; 1 or 2: assign a specific DMA channel; - * Selecting a DMA channel for an SPI bus allows transfers on the bus to have sizes only - * limited by the amount of internal memory. Selecting no DMA channel (by passing the - * value 0) limits the amount of bytes transfered to a maximum of 64. Set to 0 if only - * the SPI flash uses this bus. Set -1 to let the driver to allocate the DMA channel. + * @param host SPI peripheral to use as a SPI slave interface + * @param bus_config Pointer to a spi_bus_config_t struct specifying how the host should be initialized + * @param slave_config Pointer to a spi_slave_interface_config_t struct specifying the details for the slave interface + * @param dma_chan - DMA_AUTO_CHAN: allocate a free channel automatically; + * - 1 or 2: assign a specific DMA channel; + * - 0: non-dma mode; + * Selecting a DMA channel for an SPI bus allows transfers on the bus to have sizes only + * limited by the amount of internal memory. Selecting no DMA channel (by passing the + * value 0) limits the amount of bytes transfered to a maximum of 64. Set to 0 if only + * the SPI flash uses this bus. Set to DMA_AUTO_CHAN to let the driver to allocate the DMA channel. * * @warning If a DMA channel is selected, any transmit and receive buffer used should be allocated in * DMA-capable memory. @@ -108,7 +110,8 @@ struct spi_slave_transaction_t { * * @return * - ESP_ERR_INVALID_ARG if configuration is invalid - * - ESP_ERR_INVALID_STATE if host already is in use or DMA channel is not available + * - ESP_ERR_INVALID_STATE if host already is in use + * - ESP_ERR_NOT_FOUND if there is no available DMA channel * - ESP_ERR_NO_MEM if out of memory * - ESP_OK on success */ diff --git a/components/driver/include/driver/spi_slave_hd.h b/components/driver/include/driver/spi_slave_hd.h index 55990f88ed..80174dde9e 100644 --- a/components/driver/include/driver/spi_slave_hd.h +++ b/components/driver/include/driver/spi_slave_hd.h @@ -86,7 +86,11 @@ typedef struct { uint32_t address_bits; ///< address field bits, multiples of 8 and at least 8. uint32_t dummy_bits; ///< dummy field bits, multiples of 8 and at least 8. uint32_t queue_size; ///< Transaction queue size. This sets how many transactions can be 'in the air' (queued using spi_slave_hd_queue_trans but not yet finished using spi_slave_hd_get_trans_result) at the same time - int dma_chan; ///< DMA channel used. -1: auto dma allocate mode; 0: non-dma mode; 1 or 2: assign a specific DMA channel; + int dma_chan; /**< DMA channel to used. + * - DMA_AUTO_CHAN: allocate a free channel automatically; + * - 1 or 2: assign a specific DMA channel; + * - 0: non-dma mode; + */ spi_slave_hd_callback_config_t cb_config; ///< Callback configuration } spi_slave_hd_slot_config_t; @@ -97,10 +101,11 @@ typedef struct { * @param bus_config Bus configuration for the bus used * @param config Configuration for the SPI Slave HD driver * @return - * - ESP_OK: on success - * - ESP_ERR_INVALID_ARG: invalid argument given + * - ESP_OK: on success + * - ESP_ERR_INVALID_ARG: invalid argument given * - ESP_ERR_INVALID_STATE: function called in invalid state, may be some resources are already in use - * - ESP_ERR_NO_MEM: memory allocation failed + * - ESP_ERR_NOT_FOUND if there is no available DMA channel + * - ESP_ERR_NO_MEM: memory allocation failed * - or other return value from `esp_intr_alloc` */ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *bus_config, diff --git a/components/driver/spi_common.c b/components/driver/spi_common.c index a1ae2f02db..c8f547b30b 100644 --- a/components/driver/spi_common.c +++ b/components/driver/spi_common.c @@ -31,22 +31,11 @@ #include "stdatomic.h" #include "hal/spi_hal.h" #include "esp_rom_gpio.h" - #if CONFIG_IDF_TARGET_ESP32 #include "soc/dport_reg.h" #endif - -//This GDMA related part will be introduced by GDMA dedicated APIs in the future. Here we temporarily use macros. #if SOC_GDMA_SUPPORTED #include "esp_private/gdma.h" -#include "hal/gdma_ll.h" -#include "soc/gdma_channel.h" -#include "soc/spi_caps.h" - -#define spi_dma_set_rx_channel_priority(gdma_chan, priority) gdma_ll_rx_set_priority(&GDMA, gdma_chan, priority); -#define spi_dma_set_tx_channel_priority(gdma_chan, priority) gdma_ll_tx_set_priority(&GDMA, gdma_chan, priority); -#define spi_dma_connect_rx_channel_to_periph(gdma_chan, periph_id) gdma_ll_rx_connect_to_periph(&GDMA, gdma_chan, periph_id); -#define spi_dma_connect_tx_channel_to_periph(gdma_chan, periph_id) gdma_ll_tx_connect_to_periph(&GDMA, gdma_chan, periph_id); #endif static const char *SPI_TAG = "spi"; @@ -64,12 +53,18 @@ static const char *SPI_TAG = "spi"; SPI_CHECK(GPIO_IS_VALID_GPIO(pin_num), pin_name" not valid", ESP_ERR_INVALID_ARG); \ } - -typedef struct spi_device_t spi_device_t; +#define MAIN_BUS_DEFAULT() { \ + .host_id = 0, \ + .bus_attr = { \ + .tx_dma_chan = 0, \ + .rx_dma_chan = 0, \ + .max_transfer_sz = SOC_SPI_MAXIMUM_BUFFER_SIZE, \ + .dma_desc_num= 0, \ + }, \ + } #define FUNC_GPIO PIN_FUNC_GPIO -#define DMA_CHANNEL_ENABLED(dma_chan) (BIT(dma_chan-1)) typedef struct { int host_id; @@ -82,39 +77,35 @@ typedef struct { #endif } spicommon_bus_context_t; -#define MAIN_BUS_DEFAULT() { \ - .host_id = 0, \ - .bus_attr = { \ - .tx_dma_chan = 0, \ - .rx_dma_chan = 0, \ - .max_transfer_sz = SOC_SPI_MAXIMUM_BUFFER_SIZE, \ - .dma_desc_num= 0, \ - }, \ - } - //Periph 1 is 'claimed' by SPI flash code. static atomic_bool spi_periph_claimed[SOC_SPI_PERIPH_NUM] = { ATOMIC_VAR_INIT(true), ATOMIC_VAR_INIT(false), #if (SOC_SPI_PERIPH_NUM >= 3) ATOMIC_VAR_INIT(false), #endif #if (SOC_SPI_PERIPH_NUM >= 4) - ATOMIC_VAR_INIT(false), +ATOMIC_VAR_INIT(false), #endif }; -static const char* spi_claiming_func[3] = {NULL, NULL, NULL}; -#if !SOC_GDMA_SUPPORTED -static uint8_t spi_dma_chan_enabled = 0; -static portMUX_TYPE spi_dma_spinlock = portMUX_INITIALIZER_UNLOCKED; -#endif +static const char* spi_claiming_func[3] = {NULL, NULL, NULL}; static spicommon_bus_context_t s_mainbus = MAIN_BUS_DEFAULT(); static spicommon_bus_context_t* bus_ctx[SOC_SPI_PERIPH_NUM] = {&s_mainbus}; -#if CONFIG_IDF_TARGET_ESP32 -//ESP32S2 does not support DMA channel auto-allocation -//Each bit stands for 1 dma channel, used for auto-alloc dma channel -static uint32_t spi_dma_channel_code; +#if !SOC_GDMA_SUPPORTED +//Each bit stands for 1 dma channel, BIT(0) should be used for SPI1 +static uint8_t spi_dma_chan_enabled = 0; +static portMUX_TYPE spi_dma_spinlock = portMUX_INITIALIZER_UNLOCKED; +#endif //#if !SOC_GDMA_SUPPORTED + + +static inline bool is_valid_host(spi_host_device_t host) +{ +#if (SOC_SPI_PERIPH_NUM == 2) + return host >= SPI1_HOST && host <= SPI2_HOST; +#elif (SOC_SPI_PERIPH_NUM == 3) + return host >= SPI1_HOST && host <= SPI3_HOST; #endif +} //----------------------------------------------------------alloc spi periph-------------------------------------------------------// //Returns true if this peripheral is successfully claimed, false if otherwise. @@ -155,37 +146,38 @@ int spicommon_irqdma_source_for_host(spi_host_device_t host) return spi_periph_signal[host].irq_dma; } -//----------------------------------------------------------esp32/s2 dma periph-------------------------------------------------------// +//----------------------------------------------------------alloc dma periph-------------------------------------------------------// #if !SOC_GDMA_SUPPORTED static inline periph_module_t get_dma_periph(int dma_chan) { + assert(dma_chan >= 1 && dma_chan <= SOC_SPI_DMA_CHAN_NUM); #if CONFIG_IDF_TARGET_ESP32S2 if (dma_chan == 1) { return PERIPH_SPI2_DMA_MODULE; - } else if (dma_chan==2) { + } else if (dma_chan == 2) { return PERIPH_SPI3_DMA_MODULE; } else { abort(); - return -1; } #elif CONFIG_IDF_TARGET_ESP32 return PERIPH_SPI_DMA_MODULE; #endif } -static bool spicommon_dma_chan_claim(int dma_chan) +//On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same +static bool spicommon_dma_chan_claim(int dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan) { bool ret = false; - assert(dma_chan >= 1 && dma_chan <= SOC_SPI_DMA_CHAN_NUM); portENTER_CRITICAL(&spi_dma_spinlock); - if ( !(spi_dma_chan_enabled & DMA_CHANNEL_ENABLED(dma_chan)) ) { - // get the channel only when it's not claimed yet. - spi_dma_chan_enabled |= DMA_CHANNEL_ENABLED(dma_chan); + bool is_used = (BIT(dma_chan) & spi_dma_chan_enabled); + if (!is_used) { + spi_dma_chan_enabled |= BIT(dma_chan); + periph_module_enable(get_dma_periph(dma_chan)); + *out_actual_tx_dma_chan = dma_chan; + *out_actual_rx_dma_chan = dma_chan; ret = true; } - - periph_module_enable(get_dma_periph(dma_chan)); portEXIT_CRITICAL(&spi_dma_spinlock); return ret; @@ -200,65 +192,53 @@ static void spicommon_connect_spi_and_dma(spi_host_device_t host, int dma_chan) #endif } -#endif //#if !SOC_GDMA_SUPPORTED - -bool spicommon_dma_chan_in_use(int dma_chan) +static esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, int dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan) { -#if !SOC_GDMA_SUPPORTED - assert(dma_chan ==1 || dma_chan == 2); - return spi_dma_chan_enabled & DMA_CHANNEL_ENABLED(dma_chan); -#endif - return true; -} - -//----------------------------------------------------------alloc dma periph-------------------------------------------------------// -static esp_err_t spicommon_alloc_dma(spi_host_device_t host_id, int dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan) -{ - uint32_t actual_tx_dma_chan = 0; - uint32_t actual_rx_dma_chan = 0; - esp_err_t ret = ESP_OK; - -#if !SOC_GDMA_SUPPORTED -//On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same - if (dma_chan < 0) { + assert(is_valid_host(host_id)); #if CONFIG_IDF_TARGET_ESP32 - for (int i = 0; i < SOC_SPI_DMA_CHAN_NUM; i++) { - bool is_used = BIT(i) & spi_dma_channel_code; - if (!is_used) { - spi_dma_channel_code |= BIT(i); - actual_tx_dma_chan = i+1; - actual_rx_dma_chan = i+1; + assert((dma_chan > 0 && dma_chan <= 2) || dma_chan == DMA_AUTO_CHAN); +#elif CONFIG_IDF_TARGET_ESP32S2 + assert(dma_chan == host_id || dma_chan == DMA_AUTO_CHAN); +#endif + + esp_err_t ret = ESP_OK; + bool success = false; + + if (dma_chan == DMA_AUTO_CHAN) { +#if CONFIG_IDF_TARGET_ESP32 + for (int i = 1; i < SOC_SPI_DMA_CHAN_NUM+1; i++) { + success = spicommon_dma_chan_claim(i, out_actual_tx_dma_chan, out_actual_rx_dma_chan); + if (success) { break; } } - if (!actual_tx_dma_chan) { - SPI_CHECK(false, "no available dma channel", ESP_ERR_INVALID_STATE); - } #elif CONFIG_IDF_TARGET_ESP32S2 - //On ESP32S2, each SPI controller has its own DMA channel. So DMA channel auto-allocation is not supported - SPI_CHECK(false, "ESP32S2 does not support auto-alloc dma channel", ESP_ERR_INVALID_STATE); + //On ESP32S2, each SPI controller has its own DMA channel + success = spicommon_dma_chan_claim(host_id, out_actual_tx_dma_chan, out_actual_rx_dma_chan); #endif //#if CONFIG_IDF_TARGET_XXX } else if (dma_chan > 0) { - actual_tx_dma_chan = dma_chan; - actual_rx_dma_chan = dma_chan; - } else { //dma_chan == 0 - // Program won't reach here - abort(); + success = spicommon_dma_chan_claim(dma_chan, out_actual_tx_dma_chan, out_actual_rx_dma_chan); } - bool dma_chan_claimed = spicommon_dma_chan_claim(actual_tx_dma_chan); - if (!dma_chan_claimed) { - spicommon_periph_free(host_id); - SPI_CHECK(false, "dma channel already in use", ESP_ERR_INVALID_STATE); + if (!success) { + SPI_CHECK(false, "no available dma channel", ESP_ERR_NOT_FOUND); } - spicommon_connect_spi_and_dma(host_id, actual_tx_dma_chan); + spicommon_connect_spi_and_dma(host_id, *out_actual_tx_dma_chan); + + return ret; +} #else //SOC_GDMA_SUPPORTED +static esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, int dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan) +{ + assert(is_valid_host(host_id)); + assert(dma_chan == DMA_AUTO_CHAN); + esp_err_t ret = ESP_OK; spicommon_bus_context_t *ctx = bus_ctx[host_id]; - if (dma_chan < 0) { + if (dma_chan == DMA_AUTO_CHAN) { gdma_channel_alloc_config_t tx_alloc_config = { .flags.reserve_sibling = 1, .direction = GDMA_CHANNEL_DIRECTION_TX, @@ -277,41 +257,32 @@ static esp_err_t spicommon_alloc_dma(spi_host_device_t host_id, int dma_chan, ui return ret; } - if (host_id == SPI1_HOST) { - SPI_CHECK(false, "SPI1 does not support DMA mode", ESP_ERR_INVALID_STATE); - } -#if (SOC_SPI_PERIPH_NUM >= 2) - else if (host_id == SPI2_HOST) { + if (host_id == SPI2_HOST) { gdma_connect(ctx->rx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2)); gdma_connect(ctx->tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2)); } -#endif #if (SOC_SPI_PERIPH_NUM >= 3) - else { - //host_id == SPI3_HOST + else if (host_id == SPI3_HOST) { gdma_connect(ctx->rx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 3)); gdma_connect(ctx->tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 3)); } #endif - - gdma_get_channel_id(ctx->tx_channel, (int *)&actual_tx_dma_chan); - gdma_get_channel_id(ctx->rx_channel, (int *)&actual_rx_dma_chan); - - } else if (dma_chan > 0) { - SPI_CHECK(false, "specifying a DMA channel is not supported, please use dma auto-alloc mode", ESP_ERR_INVALID_STATE); - } else { //dma_chan == 0 - // Program won't reach here + gdma_get_channel_id(ctx->tx_channel, (int *)out_actual_tx_dma_chan); + gdma_get_channel_id(ctx->rx_channel, (int *)out_actual_rx_dma_chan); } -#endif - *out_actual_tx_dma_chan = actual_tx_dma_chan; - *out_actual_rx_dma_chan = actual_rx_dma_chan; return ret; } +#endif //#if !SOC_GDMA_SUPPORTED -esp_err_t spicommon_slave_alloc_dma(spi_host_device_t host_id, int dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan) +esp_err_t spicommon_slave_dma_chan_alloc(spi_host_device_t host_id, int dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan) { + assert(is_valid_host(host_id)); + assert((dma_chan == 1 || dma_chan == 2 || dma_chan == DMA_AUTO_CHAN)); + esp_err_t ret = ESP_OK; + uint32_t actual_tx_dma_chan = 0; + uint32_t actual_rx_dma_chan = 0; spicommon_bus_context_t *ctx = (spicommon_bus_context_t *)calloc(1, sizeof(spicommon_bus_context_t)); if (!ctx) { ret = ESP_ERR_NO_MEM; @@ -320,11 +291,15 @@ esp_err_t spicommon_slave_alloc_dma(spi_host_device_t host_id, int dma_chan, uin bus_ctx[host_id] = ctx; ctx->host_id = host_id; - - ret = spicommon_alloc_dma(host_id, dma_chan, out_actual_tx_dma_chan, out_actual_rx_dma_chan); + ret = spicommon_dma_chan_alloc(host_id, dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan); if (ret != ESP_OK) { goto cleanup; } + ctx->bus_attr.tx_dma_chan = actual_tx_dma_chan; + ctx->bus_attr.rx_dma_chan = actual_rx_dma_chan; + *out_actual_tx_dma_chan = actual_tx_dma_chan; + *out_actual_rx_dma_chan = actual_rx_dma_chan; + return ret; cleanup: @@ -334,19 +309,22 @@ cleanup: } //----------------------------------------------------------free dma periph-------------------------------------------------------// -static esp_err_t spicommon_dma_chan_free(spi_host_device_t host_id, int dma_chan) +static esp_err_t spicommon_dma_chan_free(spi_host_device_t host_id) { + assert(is_valid_host(host_id)); + + spicommon_bus_context_t *ctx = bus_ctx[host_id]; #if !SOC_GDMA_SUPPORTED - assert( dma_chan == 1 || dma_chan == 2 ); - assert( spi_dma_chan_enabled & DMA_CHANNEL_ENABLED(dma_chan) ); + //On ESP32S2, each SPI controller has its own DMA channel + int dma_chan = ctx->bus_attr.tx_dma_chan; + assert(spi_dma_chan_enabled & BIT(dma_chan)); portENTER_CRITICAL(&spi_dma_spinlock); - spi_dma_chan_enabled &= ~DMA_CHANNEL_ENABLED(dma_chan); + spi_dma_chan_enabled &= ~BIT(dma_chan); periph_module_disable(get_dma_periph(dma_chan)); portEXIT_CRITICAL(&spi_dma_spinlock); #else //SOC_GDMA_SUPPORTED - spicommon_bus_context_t *ctx = bus_ctx[host_id]; if (ctx->rx_channel) { gdma_disconnect(ctx->rx_channel); gdma_del_channel(ctx->rx_channel); @@ -360,10 +338,11 @@ static esp_err_t spicommon_dma_chan_free(spi_host_device_t host_id, int dma_chan return ESP_OK; } -esp_err_t spicommon_slave_free_dma(spi_host_device_t host_id, int dma_chan) +esp_err_t spicommon_slave_free_dma(spi_host_device_t host_id) { - esp_err_t ret = spicommon_dma_chan_free(host_id, dma_chan); + assert(is_valid_host(host_id)); + esp_err_t ret = spicommon_dma_chan_free(host_id); free(bus_ctx[host_id]); bus_ctx[host_id] = NULL; @@ -628,11 +607,6 @@ spi_bus_lock_handle_t spi_bus_lock_get_by_id(spi_host_device_t host_id) return bus_ctx[host_id]->bus_attr.lock; } -static inline bool is_valid_host(spi_host_device_t host) -{ - return host >= SPI1_HOST && host <= SPI3_HOST; -} - //----------------------------------------------------------master bus init-------------------------------------------------------// esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t *bus_config, int dma_chan) { @@ -645,11 +619,11 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t * SPI_CHECK(is_valid_host(host_id), "invalid host_id", ESP_ERR_INVALID_ARG); SPI_CHECK(bus_ctx[host_id] == NULL, "SPI bus already initialized.", ESP_ERR_INVALID_STATE); #ifdef CONFIG_IDF_TARGET_ESP32 - SPI_CHECK( (dma_chan >= 0 && dma_chan <= 2) || dma_chan == -1, "invalid dma channel", ESP_ERR_INVALID_ARG ); + SPI_CHECK( (dma_chan >= 0 && dma_chan <= 2) || dma_chan == DMA_AUTO_CHAN, "invalid dma channel", ESP_ERR_INVALID_ARG ); #elif CONFIG_IDF_TARGET_ESP32S2 - SPI_CHECK( dma_chan == 0 || dma_chan == host_id, "invalid dma channel", ESP_ERR_INVALID_ARG ); + SPI_CHECK( dma_chan == 0 || dma_chan == host_id || dma_chan == DMA_AUTO_CHAN, "invalid dma channel", ESP_ERR_INVALID_ARG ); #elif SOC_GDMA_SUPPORTED - SPI_CHECK( dma_chan == 0 || dma_chan == -1, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG ); + SPI_CHECK( dma_chan == 0 || dma_chan == DMA_AUTO_CHAN, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG ); #endif SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH|ESP_INTR_FLAG_EDGE|ESP_INTR_FLAG_INTRDISABLED))==0, "intr flag not allowed", ESP_ERR_INVALID_ARG); #ifndef CONFIG_SPI_MASTER_ISR_IN_IRAM @@ -673,7 +647,7 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t * if (dma_chan != 0) { bus_attr->dma_enabled = 1; - err = spicommon_alloc_dma(host_id, dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan); + err = spicommon_dma_chan_alloc(host_id, dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan); if (err != ESP_OK) { goto cleanup; } @@ -731,10 +705,10 @@ cleanup: } free(bus_attr->dmadesc_tx); free(bus_attr->dmadesc_rx); - - //On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same + bus_attr->dmadesc_tx = NULL; + bus_attr->dmadesc_rx = NULL; if (bus_attr->dma_enabled) { - spicommon_dma_chan_free(host_id, actual_tx_dma_chan); + spicommon_dma_chan_free(host_id); } } spicommon_periph_free(host_id); @@ -766,17 +740,14 @@ esp_err_t spi_bus_free(spi_host_device_t host_id) esp_pm_lock_delete(bus_attr->pm_lock); #endif spi_bus_deinit_lock(bus_attr->lock); - free(bus_attr->dmadesc_rx); free(bus_attr->dmadesc_tx); - - - //On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same + bus_attr->dmadesc_tx = NULL; + bus_attr->dmadesc_rx = NULL; if (bus_attr->dma_enabled > 0) { - spicommon_dma_chan_free (host_id, bus_attr->tx_dma_chan); + spicommon_dma_chan_free(host_id); } spicommon_periph_free(host_id); - free(ctx); bus_ctx[host_id] = NULL; return err; diff --git a/components/driver/spi_master.c b/components/driver/spi_master.c index e1d9eb3243..7eb160cb99 100644 --- a/components/driver/spi_master.c +++ b/components/driver/spi_master.c @@ -188,10 +188,12 @@ static esp_err_t spi_master_deinit_driver(void* arg); static inline bool is_valid_host(spi_host_device_t host) { +//SPI1 can be used as GPSPI only on ESP32 #if CONFIG_IDF_TARGET_ESP32 return host >= SPI1_HOST && host <= SPI3_HOST; -#else -// SPI_HOST (SPI1_HOST) is not supported by the SPI Master driver on ESP32-S2 and later +#elif (SOC_SPI_PERIPH_NUM == 2) + return host == SPI2_HOST; +#elif (SOC_SPI_PERIPH_NUM == 3) return host >= SPI2_HOST && host <= SPI3_HOST; #endif } diff --git a/components/driver/spi_slave.c b/components/driver/spi_slave.c index e7765e2920..3e42e03f43 100644 --- a/components/driver/spi_slave.c +++ b/components/driver/spi_slave.c @@ -81,10 +81,12 @@ static void IRAM_ATTR spi_intr(void *arg); static inline bool is_valid_host(spi_host_device_t host) { +//SPI1 can be used as GPSPI only on ESP32 #if CONFIG_IDF_TARGET_ESP32 return host >= SPI1_HOST && host <= SPI3_HOST; -#else -// SPI_HOST (SPI1_HOST) is not supported by the SPI Slave driver on ESP32-S2 & later +#elif (SOC_SPI_PERIPH_NUM == 2) + return host == SPI2_HOST; +#elif (SOC_SPI_PERIPH_NUM == 3) return host >= SPI2_HOST && host <= SPI3_HOST; #endif } @@ -120,11 +122,11 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b //We only support HSPI/VSPI, period. SPI_CHECK(is_valid_host(host), "invalid host", ESP_ERR_INVALID_ARG); #ifdef CONFIG_IDF_TARGET_ESP32 - SPI_CHECK( (dma_chan >= 0 && dma_chan <= 2) || dma_chan == -1, "invalid dma channel", ESP_ERR_INVALID_ARG ); + SPI_CHECK( (dma_chan >= 0 && dma_chan <= 2) || dma_chan == DMA_AUTO_CHAN, "invalid dma channel", ESP_ERR_INVALID_ARG ); #elif CONFIG_IDF_TARGET_ESP32S2 - SPI_CHECK( dma_chan == 0 || dma_chan == host, "invalid dma channel", ESP_ERR_INVALID_ARG ); + SPI_CHECK( dma_chan == 0 || dma_chan == host || dma_chan == DMA_AUTO_CHAN, "invalid dma channel", ESP_ERR_INVALID_ARG ); #elif SOC_GDMA_SUPPORTED - SPI_CHECK( dma_chan == 0 || dma_chan == -1, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG ); + SPI_CHECK( dma_chan == 0 || dma_chan == DMA_AUTO_CHAN, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG ); #endif SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH|ESP_INTR_FLAG_EDGE|ESP_INTR_FLAG_INTRDISABLED))==0, "intr flag not allowed", ESP_ERR_INVALID_ARG); #ifndef CONFIG_SPI_SLAVE_ISR_IN_IRAM @@ -147,7 +149,7 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b bool use_dma = (dma_chan != 0); spihost[host]->dma_enabled = use_dma; if (use_dma) { - ret = spicommon_slave_alloc_dma(host, dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan); + ret = spicommon_slave_dma_chan_alloc(host, dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan); if (ret != ESP_OK) { goto cleanup; } @@ -246,9 +248,8 @@ cleanup: #endif } spi_slave_hal_deinit(&spihost[host]->hal); - //On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same if (spihost[host]->dma_enabled) { - spicommon_slave_free_dma(host, actual_tx_dma_chan); + spicommon_slave_free_dma(host); } free(spihost[host]); @@ -265,8 +266,7 @@ esp_err_t spi_slave_free(spi_host_device_t host) if (spihost[host]->trans_queue) vQueueDelete(spihost[host]->trans_queue); if (spihost[host]->ret_queue) vQueueDelete(spihost[host]->ret_queue); if (spihost[host]->dma_enabled) { - //On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same - spicommon_slave_free_dma(host, spihost[host]->tx_dma_chan); + spicommon_slave_free_dma(host); } free(spihost[host]->hal.dmadesc_tx); free(spihost[host]->hal.dmadesc_rx); diff --git a/components/driver/spi_slave_hd.c b/components/driver/spi_slave_hd.c index fbb521c199..44298e3049 100644 --- a/components/driver/spi_slave_hd.c +++ b/components/driver/spi_slave_hd.c @@ -23,14 +23,15 @@ #include "hal/spi_slave_hd_hal.h" -//SPI1 can never be used as the slave -#define VALID_HOST(x) (x>SPI_HOST && x<=HSPI_HOST) +#if (SOC_SPI_PERIPH_NUM == 2) +#define VALID_HOST(x) ((x) == SPI2_HOST) +#elif (SOC_SPI_PERIPH_NUM == 3) +#define VALID_HOST(x) ((x) >= SPI2_HOST && (x) <= SPI3_HOST) +#endif #define SPIHD_CHECK(cond,warn,ret) do{if(!(cond)){ESP_LOGE(TAG, warn); return ret;}} while(0) typedef struct { bool dma_enabled; - uint32_t tx_dma_chan; - uint32_t rx_dma_chan; int max_transfer_sz; uint32_t flags; portMUX_TYPE int_spinlock; @@ -74,9 +75,9 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b SPIHD_CHECK(VALID_HOST(host_id), "invalid host", ESP_ERR_INVALID_ARG); #if CONFIG_IDF_TARGET_ESP32S2 - SPIHD_CHECK(config->dma_chan == 0 || config->dma_chan == host_id, "invalid dma channel", ESP_ERR_INVALID_ARG); + SPIHD_CHECK(config->dma_chan == 0 || config->dma_chan == host_id || config->dma_chan == DMA_AUTO_CHAN, "invalid dma channel", ESP_ERR_INVALID_ARG); #elif SOC_GDMA_SUPPORTED - SPIHD_CHECK(config->dma_chan == 0 || config->dma_chan == -1, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG); + SPIHD_CHECK(config->dma_chan == 0 || config->dma_chan == DMA_AUTO_CHAN, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG); #endif #if !CONFIG_IDF_TARGET_ESP32S2 //Append mode is only supported on ESP32S2 now @@ -97,15 +98,12 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b host->dma_enabled = (config->dma_chan != 0); if (host->dma_enabled) { - ret = spicommon_slave_alloc_dma(host_id, config->dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan); + ret = spicommon_slave_dma_chan_alloc(host_id, config->dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan); if (ret != ESP_OK) { goto cleanup; } } - host->tx_dma_chan = actual_tx_dma_chan; - host->rx_dma_chan = actual_rx_dma_chan; - ret = spicommon_bus_initialize_io(host_id, bus_config, SPICOMMON_BUSFLAG_SLAVE | bus_config->flags, &host->flags); if (ret != ESP_OK) { goto cleanup; @@ -120,8 +118,8 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b .dma_in = SPI_LL_GET_HW(host_id), .dma_out = SPI_LL_GET_HW(host_id), .dma_enabled = host->dma_enabled, - .tx_dma_chan = host->tx_dma_chan, - .rx_dma_chan = host->rx_dma_chan, + .tx_dma_chan = actual_tx_dma_chan, + .rx_dma_chan = actual_rx_dma_chan, .append_mode = append_mode, .mode = config->mode, .tx_lsbfirst = (config->flags & SPI_SLAVE_HD_RXBIT_LSBFIRST), @@ -252,8 +250,7 @@ esp_err_t spi_slave_hd_deinit(spi_host_device_t host_id) spicommon_periph_free(host_id); if (host->dma_enabled) { - //On ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same - spicommon_slave_free_dma(host_id, host->tx_dma_chan); + spicommon_slave_free_dma(host_id); } free(host); spihost[host_id] = NULL; diff --git a/components/driver/test/test_spi_master.c b/components/driver/test/test_spi_master.c index 7a2681f475..47355a462a 100644 --- a/components/driver/test/test_spi_master.c +++ b/components/driver/test/test_spi_master.c @@ -74,11 +74,7 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]") .quadhd_io_num=-1 }; esp_err_t ret; -#if !SOC_GDMA_SUPPORTED - ret = spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1); -#else - ret = spi_bus_initialize(TEST_SPI_HOST, &buscfg, -1); -#endif + ret = spi_bus_initialize(TEST_SPI_HOST, &buscfg, DMA_AUTO_CHAN); TEST_ASSERT(ret==ESP_OK); check_spi_pre_n_for(26000000, 1, 3); @@ -116,11 +112,7 @@ static spi_device_handle_t setup_spi_bus_loopback(int clkspeed, bool dma) { }; spi_device_handle_t handle; -#if !SOC_GDMA_SUPPORTED - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, dma ? 1 : 0)); -#else - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, dma ? -1 : 0)); -#endif + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, dma ? DMA_AUTO_CHAN : 0)); TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &handle)); //connect MOSI to two devices breaks the output, fix it. spitest_gpio_output_sel(PIN_NUM_MOSI, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out); @@ -281,11 +273,7 @@ static esp_err_t test_master_pins(int mosi, int miso, int sclk, int cs) spi_device_interface_config_t master_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG(); master_cfg.spics_io_num = cs; -#if !SOC_GDMA_SUPPORTED - ret = spi_bus_initialize(TEST_SPI_HOST, &cfg, 1); -#else - ret = spi_bus_initialize(TEST_SPI_HOST, &cfg, -1); -#endif + ret = spi_bus_initialize(TEST_SPI_HOST, &cfg, DMA_AUTO_CHAN); if (ret != ESP_OK) { return ret; } @@ -312,11 +300,7 @@ static esp_err_t test_slave_pins(int mosi, int miso, int sclk, int cs) spi_slave_interface_config_t slave_cfg = SPI_SLAVE_TEST_DEFAULT_CONFIG(); slave_cfg.spics_io_num = cs; -#if !SOC_GDMA_SUPPORTED - ret = spi_slave_initialize(TEST_SLAVE_HOST, &cfg, &slave_cfg, TEST_DMA_CHAN_SLAVE); -#else - ret = spi_slave_initialize(TEST_SLAVE_HOST, &cfg, &slave_cfg, -1); -#endif + ret = spi_slave_initialize(TEST_SLAVE_HOST, &cfg, &slave_cfg, DMA_AUTO_CHAN); if (ret != ESP_OK) { return ret; } @@ -523,11 +507,7 @@ TEST_CASE("SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)" //initialize for first host host = TEST_SPI_HOST; -#if !SOC_GDMA_SUPPORTED - TEST_ESP_OK(spi_bus_initialize(host, &bus_config, host)); -#else - TEST_ESP_OK(spi_bus_initialize(host, &bus_config, -1)); -#endif + TEST_ESP_OK(spi_bus_initialize(host, &bus_config, DMA_AUTO_CHAN)); TEST_ESP_OK(spi_bus_add_device(host, &device_config, &spi)); printf("before first xmit\n"); @@ -539,12 +519,7 @@ TEST_CASE("SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)" //for second host and failed before host = TEST_SLAVE_HOST; - -#if !SOC_GDMA_SUPPORTED - TEST_ESP_OK(spi_bus_initialize(host, &bus_config, host)); -#else - TEST_ESP_OK(spi_bus_initialize(host, &bus_config, -1)); -#endif + TEST_ESP_OK(spi_bus_initialize(host, &bus_config, DMA_AUTO_CHAN)); TEST_ESP_OK(spi_bus_add_device(host, &device_config, &spi)); printf("before second xmit\n"); @@ -612,11 +587,7 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]") spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG(); //Initialize the SPI bus -#if !SOC_GDMA_SUPPORTED - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1)); -#else - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, -1)); -#endif + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, DMA_AUTO_CHAN)); //Attach the LCD to the SPI bus TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &spi)); //connect MOSI to two devices breaks the output, fix it. @@ -700,11 +671,7 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]") .pre_cb=NULL, }; //Initialize the SPI bus -#if !SOC_GDMA_SUPPORTED - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1)); -#else - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, -1)); -#endif + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, DMA_AUTO_CHAN)); //Attach the LCD to the SPI bus TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &spi)); @@ -773,11 +740,7 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first) //initial master, mode 0, 1MHz spi_bus_config_t buscfg=SPI_BUS_TEST_DEFAULT_CONFIG(); buscfg.quadhd_io_num = UNCONNECTED_PIN; -#if !SOC_GDMA_SUPPORTED - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1)); -#else - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, -1)); -#endif + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, DMA_AUTO_CHAN)); spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG(); devcfg.clock_speed_hz = 1*1000*1000; if (lsb_first) devcfg.flags |= SPI_DEVICE_BIT_LSBFIRST; @@ -1112,11 +1075,7 @@ static void speed_setup(spi_device_handle_t* spi, bool use_dma) devcfg.queue_size=8; //We want to be able to queue 7 transactions at a time //Initialize the SPI bus and the device to test -#if !SOC_GDMA_SUPPORTED - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, (use_dma? GET_DMA_CHAN(TEST_SPI_HOST): 0))); -#else - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, (use_dma? -1 : 0))); -#endif + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, (use_dma ? DMA_AUTO_CHAN : 0))); TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, spi)); } diff --git a/components/driver/test/test_spi_param.c b/components/driver/test/test_spi_param.c index 90f9ab1859..741e65b7e8 100644 --- a/components/driver/test/test_spi_param.c +++ b/components/driver/test/test_spi_param.c @@ -97,24 +97,15 @@ static void local_test_start(spi_device_handle_t *spi, int freq, const spitest_p //slave config slvcfg.mode = pset->mode; - slave_pull_up(&buscfg, slvcfg.spics_io_num); -#if !SOC_GDMA_SUPPORTED - int dma_chan = pset->master_dma_chan; -#else - int dma_chan = (pset->master_dma_chan == 0) ? 0 : -1; -#endif + int dma_chan = (pset->master_dma_chan == 0) ? 0 : DMA_AUTO_CHAN; TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, dma_chan)); TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, spi)); //slave automatically use iomux pins if pins are on VSPI_* pins buscfg.quadhd_io_num = -1; -#if !SOC_GDMA_SUPPORTED - int slave_dma_chan = pset->slave_dma_chan; -#else - int slave_dma_chan = (pset->slave_dma_chan == 0) ? 0 : -1; -#endif + int slave_dma_chan = (pset->slave_dma_chan == 0) ? 0 : DMA_AUTO_CHAN; TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, slave_dma_chan)); //initialize master and slave on the same pins break some of the output configs, fix them @@ -402,7 +393,7 @@ static spitest_param_set_t mode_pgroup[] = { .master_limit = SPI_MASTER_FREQ_13M, .dup = FULL_DUPLEX, .mode = 0, - .slave_dma_chan = 2, + .slave_dma_chan = DMA_AUTO_CHAN, .master_iomux = false, .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT, @@ -414,7 +405,7 @@ static spitest_param_set_t mode_pgroup[] = { .master_limit = SPI_MASTER_FREQ_13M, .dup = FULL_DUPLEX, .mode = 1, - .slave_dma_chan = 2, + .slave_dma_chan = DMA_AUTO_CHAN, .master_iomux = false, .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT, @@ -425,7 +416,7 @@ static spitest_param_set_t mode_pgroup[] = { .master_limit = SPI_MASTER_FREQ_13M, .dup = FULL_DUPLEX, .mode = 2, - .slave_dma_chan = 2, + .slave_dma_chan = DMA_AUTO_CHAN, .master_iomux = false, .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT, @@ -437,7 +428,7 @@ static spitest_param_set_t mode_pgroup[] = { .master_limit = SPI_MASTER_FREQ_13M, .dup = FULL_DUPLEX, .mode = 3, - .slave_dma_chan = 2, + .slave_dma_chan = DMA_AUTO_CHAN, .master_iomux = false, .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT, @@ -480,7 +471,7 @@ static spitest_param_set_t mode_pgroup[] = { .freq_list = test_freq_mode_local, .dup = HALF_DUPLEX_MISO, .mode = 0, - .slave_dma_chan = 2, + .slave_dma_chan = DMA_AUTO_CHAN, .master_iomux = false, .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT+SLAVE_EXTRA_DELAY_DMA, @@ -490,7 +481,7 @@ static spitest_param_set_t mode_pgroup[] = { .freq_list = test_freq_mode_local, .dup = HALF_DUPLEX_MISO, .mode = 1, - .slave_dma_chan = 2, + .slave_dma_chan = DMA_AUTO_CHAN, .master_iomux = false, .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT, @@ -500,7 +491,7 @@ static spitest_param_set_t mode_pgroup[] = { .freq_list = test_freq_mode_local, .dup = HALF_DUPLEX_MISO, .mode = 2, - .slave_dma_chan = 2, + .slave_dma_chan = DMA_AUTO_CHAN, .master_iomux = false, .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT+SLAVE_EXTRA_DELAY_DMA, @@ -510,7 +501,7 @@ static spitest_param_set_t mode_pgroup[] = { .freq_list = test_freq_mode_local, .dup = HALF_DUPLEX_MISO, .mode = 3, - .slave_dma_chan = 2, + .slave_dma_chan = DMA_AUTO_CHAN, .master_iomux = false, .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT, @@ -555,7 +546,7 @@ TEST_CASE("Slave receive correct data", "[spi]") .master_iomux = false, .slave_iomux = false, .master_dma_chan = 0, - .slave_dma_chan = (dma_chan? TEST_DMA_CHAN_SLAVE: 0), + .slave_dma_chan = (dma_chan ? DMA_AUTO_CHAN: 0), }; ESP_LOGI(SLAVE_TAG, "Test slave recv @ mode %d, dma enabled=%d", spi_mode, dma_chan); @@ -713,13 +704,7 @@ static void test_master_start(spi_device_handle_t *spi, int freq, const spitest_ devpset.clock_speed_hz = freq; if (pset->master_limit != 0 && freq > pset->master_limit) devpset.flags |= SPI_DEVICE_NO_DUMMY; - - -#if !SOC_GDMA_SUPPORTED - int dma_chan = pset->master_dma_chan; -#else - int dma_chan = (pset->master_dma_chan == 0) ? 0 : -1; -#endif + int dma_chan = (pset->master_dma_chan == 0) ? 0 : DMA_AUTO_CHAN; TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buspset, dma_chan)); TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devpset, spi)); @@ -840,11 +825,7 @@ static void timing_slave_start(int speed, const spitest_param_set_t* pset, spite //Enable pull-ups on SPI lines so we don't detect rogue pulses when no master is connected. slave_pull_up(&slv_buscfg, slvcfg.spics_io_num); -#if !SOC_GDMA_SUPPORTED - int slave_dma_chan = pset->slave_dma_chan; -#else - int slave_dma_chan = (pset->slave_dma_chan == 0) ? 0 : -1; -#endif + int slave_dma_chan = (pset->slave_dma_chan == 0) ? 0 : DMA_AUTO_CHAN; TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &slv_buscfg, &slvcfg, slave_dma_chan)); //prepare data for the master @@ -1105,8 +1086,8 @@ spitest_param_set_t mode_conf[] = { .slave_iomux = true, .slave_tv_ns = DELAY_HCLK_UNTIL_7M, .mode = 0, - .master_dma_chan = 1, - .slave_dma_chan = 1, + .master_dma_chan = DMA_AUTO_CHAN, + .slave_dma_chan = DMA_AUTO_CHAN, .length_aligned = true, }, { .pset_name = "mode 1, DMA", @@ -1117,8 +1098,8 @@ spitest_param_set_t mode_conf[] = { .slave_iomux = true, .slave_tv_ns = TV_WITH_ESP_SLAVE, .mode = 1, - .master_dma_chan = 1, - .slave_dma_chan = 1, + .master_dma_chan = DMA_AUTO_CHAN, + .slave_dma_chan = DMA_AUTO_CHAN, .length_aligned = true, }, { .pset_name = "mode 2, DMA", @@ -1129,8 +1110,8 @@ spitest_param_set_t mode_conf[] = { .slave_iomux = true, .slave_tv_ns = DELAY_HCLK_UNTIL_7M, .mode = 2, - .master_dma_chan = 1, - .slave_dma_chan = 1, + .master_dma_chan = DMA_AUTO_CHAN, + .slave_dma_chan = DMA_AUTO_CHAN, .length_aligned = true, }, { .pset_name = "mode 3, DMA", @@ -1141,8 +1122,8 @@ spitest_param_set_t mode_conf[] = { .slave_iomux = true, .slave_tv_ns = TV_WITH_ESP_SLAVE, .mode = 3, - .master_dma_chan = 1, - .slave_dma_chan = 1, + .master_dma_chan = DMA_AUTO_CHAN, + .slave_dma_chan = DMA_AUTO_CHAN, .length_aligned = true, }, //the master can only read to 16MHz, use half-duplex mode to read at 20. @@ -1153,8 +1134,8 @@ spitest_param_set_t mode_conf[] = { .slave_iomux = true, .slave_tv_ns = TV_WITH_ESP_SLAVE, .mode = 0, - .master_dma_chan = 1, - .slave_dma_chan = 1, + .master_dma_chan = DMA_AUTO_CHAN, + .slave_dma_chan = DMA_AUTO_CHAN, }, { .pset_name = "mode 1, DMA, 20M", .freq_list = test_freq_20M_only, @@ -1163,8 +1144,8 @@ spitest_param_set_t mode_conf[] = { .slave_iomux = true, .slave_tv_ns = TV_WITH_ESP_SLAVE, .mode = 1, - .master_dma_chan = 1, - .slave_dma_chan = 1, + .master_dma_chan = DMA_AUTO_CHAN, + .slave_dma_chan = DMA_AUTO_CHAN, }, { .pset_name = "mode 2, DMA, 20M", .freq_list = test_freq_20M_only, @@ -1173,8 +1154,8 @@ spitest_param_set_t mode_conf[] = { .slave_iomux = true, .slave_tv_ns = TV_WITH_ESP_SLAVE, .mode = 2, - .master_dma_chan = 1, - .slave_dma_chan = 1, + .master_dma_chan = DMA_AUTO_CHAN, + .slave_dma_chan = DMA_AUTO_CHAN, }, { .pset_name = "mode 3, DMA, 20M", .freq_list = test_freq_20M_only, @@ -1183,8 +1164,8 @@ spitest_param_set_t mode_conf[] = { .slave_iomux = true, .slave_tv_ns = TV_WITH_ESP_SLAVE, .mode = 3, - .master_dma_chan = 1, - .slave_dma_chan = 1, + .master_dma_chan = DMA_AUTO_CHAN, + .slave_dma_chan = DMA_AUTO_CHAN, }, }; TEST_SPI_MASTER_SLAVE(MODE, mode_conf, "") diff --git a/components/driver/test/test_spi_slave.c b/components/driver/test/test_spi_slave.c index a37ce50d89..f5bfe20baa 100644 --- a/components/driver/test/test_spi_slave.c +++ b/components/driver/test/test_spi_slave.c @@ -48,7 +48,7 @@ static void master_init_nodma( spi_device_handle_t* spi) .cs_ena_pretrans=1, }; //Initialize the SPI bus - ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, 0); + ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, DMA_AUTO_CHAN); TEST_ASSERT(ret==ESP_OK); //Attach the LCD to the SPI bus ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, spi); @@ -74,12 +74,8 @@ static void slave_init(void) gpio_set_pull_mode(PIN_NUM_MOSI, GPIO_PULLUP_ONLY); gpio_set_pull_mode(PIN_NUM_CLK, GPIO_PULLUP_ONLY); gpio_set_pull_mode(PIN_NUM_CS, GPIO_PULLUP_ONLY); -#if !SOC_GDMA_SUPPORTED //Initialize SPI slave interface - TEST_ESP_OK( spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, 2) ); -#else - TEST_ESP_OK( spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, -1) ); -#endif + TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, DMA_AUTO_CHAN)); } TEST_CASE("test slave send unaligned","[spi]") @@ -224,7 +220,7 @@ static void unaligned_test_slave(void) { spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG(); spi_slave_interface_config_t slvcfg = SPI_SLAVE_TEST_DEFAULT_CONFIG(); - TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, TEST_SLAVE_HOST)); + TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, DMA_AUTO_CHAN)); uint8_t *slave_send_buf = heap_caps_malloc(BUF_SIZE, MALLOC_CAP_DMA); uint8_t *slave_recv_buf = heap_caps_calloc(BUF_SIZE, 1, MALLOC_CAP_DMA); diff --git a/components/driver/test/test_spi_slave_hd.c b/components/driver/test/test_spi_slave_hd.c index d5d50638e4..6cf9eb2a1d 100644 --- a/components/driver/test/test_spi_slave_hd.c +++ b/components/driver/test/test_spi_slave_hd.c @@ -99,11 +99,7 @@ static void init_master_hd(spi_device_handle_t* spi, const spitest_param_set_t* bus_cfg.flags |= SPICOMMON_BUSFLAG_GPIO_PINS; #endif -#if !SOC_GDMA_SUPPORTED - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, TEST_SPI_HOST)); -#else - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, -1)); -#endif + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, DMA_AUTO_CHAN)); spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG(); dev_cfg.flags = SPI_DEVICE_HALFDUPLEX; dev_cfg.command_bits = 8; @@ -126,11 +122,7 @@ static void init_slave_hd(int mode, bool append_mode, const spi_slave_hd_callbac #endif spi_slave_hd_slot_config_t slave_hd_cfg = SPI_SLOT_TEST_DEFAULT_CONFIG(); slave_hd_cfg.mode = mode; -#if !SOC_GDMA_SUPPORTED - slave_hd_cfg.dma_chan = TEST_SLAVE_HOST; -#else - slave_hd_cfg.dma_chan = -1; -#endif + slave_hd_cfg.dma_chan = DMA_AUTO_CHAN; if (append_mode) { slave_hd_cfg.flags |= SPI_SLAVE_HD_APPEND_MODE; } diff --git a/components/hal/esp32/include/hal/spi_ll.h b/components/hal/esp32/include/hal/spi_ll.h index 99a0967625..cacffe0a05 100644 --- a/components/hal/esp32/include/hal/spi_ll.h +++ b/components/hal/esp32/include/hal/spi_ll.h @@ -947,7 +947,7 @@ static inline void spi_ll_enable_int(spi_dev_t *hw) * Reset RX DMA which stores the data received from a peripheral into RAM. * * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. */ static inline void spi_dma_ll_rx_reset(spi_dma_dev_t *dma_in, uint32_t channel) { @@ -960,7 +960,7 @@ static inline void spi_dma_ll_rx_reset(spi_dma_dev_t *dma_in, uint32_t channel) * Start RX DMA. * * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. * @param addr Address of the beginning DMA descriptor. */ static inline void spi_dma_ll_rx_start(spi_dma_dev_t *dma_in, uint32_t channel, lldesc_t *addr) @@ -973,7 +973,7 @@ static inline void spi_dma_ll_rx_start(spi_dma_dev_t *dma_in, uint32_t channel, * Enable DMA RX channel burst for data * * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ static inline void spi_dma_ll_rx_enable_burst_data(spi_dma_dev_t *dma_in, uint32_t channel, bool enable) @@ -985,7 +985,7 @@ static inline void spi_dma_ll_rx_enable_burst_data(spi_dma_dev_t *dma_in, uint32 * Enable DMA RX channel burst for descriptor * * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ static inline void spi_dma_ll_rx_enable_burst_desc(spi_dma_dev_t *dma_in, uint32_t channel, bool enable) @@ -997,7 +997,7 @@ static inline void spi_dma_ll_rx_enable_burst_desc(spi_dma_dev_t *dma_in, uint32 * Reset TX DMA which transmits the data from RAM to a peripheral. * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. */ static inline void spi_dma_ll_tx_reset(spi_dma_dev_t *dma_out, uint32_t channel) { @@ -1010,7 +1010,7 @@ static inline void spi_dma_ll_tx_reset(spi_dma_dev_t *dma_out, uint32_t channel) * Start TX DMA. * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. * @param addr Address of the beginning DMA descriptor. */ static inline void spi_dma_ll_tx_start(spi_dma_dev_t *dma_out, uint32_t channel, lldesc_t *addr) @@ -1023,7 +1023,7 @@ static inline void spi_dma_ll_tx_start(spi_dma_dev_t *dma_out, uint32_t channel, * Enable DMA TX channel burst for data * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ static inline void spi_dma_ll_tx_enable_burst_data(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) @@ -1035,7 +1035,7 @@ static inline void spi_dma_ll_tx_enable_burst_data(spi_dma_dev_t *dma_out, uint3 * Enable DMA TX channel burst for descriptor * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ static inline void spi_dma_ll_tx_enable_burst_desc(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) @@ -1047,7 +1047,7 @@ static inline void spi_dma_ll_tx_enable_burst_desc(spi_dma_dev_t *dma_out, uint3 * Configuration of OUT EOF flag generation way * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. * @param enable 1: when dma pop all data from fifo 0:when ahb push all data to fifo. */ static inline void spi_dma_ll_set_out_eof_generation(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) @@ -1059,7 +1059,7 @@ static inline void spi_dma_ll_set_out_eof_generation(spi_dma_dev_t *dma_out, uin * Enable automatic outlink-writeback * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ static inline void spi_dma_ll_enable_out_auto_wrback(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) diff --git a/components/hal/esp32s2/include/hal/spi_ll.h b/components/hal/esp32s2/include/hal/spi_ll.h index 6a1090a34c..05f3689a15 100644 --- a/components/hal/esp32s2/include/hal/spi_ll.h +++ b/components/hal/esp32s2/include/hal/spi_ll.h @@ -1081,7 +1081,7 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t* hw) * Reset RX DMA which stores the data received from a peripheral into RAM. * * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. */ static inline void spi_dma_ll_rx_reset(spi_dma_dev_t *dma_in, uint32_t channel) { @@ -1097,7 +1097,7 @@ static inline void spi_dma_ll_rx_reset(spi_dma_dev_t *dma_in, uint32_t channel) * Start RX DMA. * * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. * @param addr Address of the beginning DMA descriptor. */ static inline void spi_dma_ll_rx_start(spi_dma_dev_t *dma_in, uint32_t channel, lldesc_t *addr) @@ -1110,7 +1110,7 @@ static inline void spi_dma_ll_rx_start(spi_dma_dev_t *dma_in, uint32_t channel, * Enable DMA RX channel burst for data * * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ static inline void spi_dma_ll_rx_enable_burst_data(spi_dma_dev_t *dma_in, uint32_t channel, bool enable) @@ -1122,7 +1122,7 @@ static inline void spi_dma_ll_rx_enable_burst_data(spi_dma_dev_t *dma_in, uint32 * Enable DMA TX channel burst for descriptor * * @param dma_in Beginning address of the DMA peripheral registers which stores the data received from a peripheral into RAM. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ static inline void spi_dma_ll_rx_enable_burst_desc(spi_dma_dev_t *dma_in, uint32_t channel, bool enable) @@ -1134,7 +1134,7 @@ static inline void spi_dma_ll_rx_enable_burst_desc(spi_dma_dev_t *dma_in, uint32 * Reset TX DMA which transmits the data from RAM to a peripheral. * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. */ static inline void spi_dma_ll_tx_reset(spi_dma_dev_t *dma_out, uint32_t channel) { @@ -1147,7 +1147,7 @@ static inline void spi_dma_ll_tx_reset(spi_dma_dev_t *dma_out, uint32_t channel) * Start TX DMA. * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. * @param addr Address of the beginning DMA descriptor. */ static inline void spi_dma_ll_tx_start(spi_dma_dev_t *dma_out, uint32_t channel, lldesc_t *addr) @@ -1160,7 +1160,7 @@ static inline void spi_dma_ll_tx_start(spi_dma_dev_t *dma_out, uint32_t channel, * Enable DMA TX channel burst for data * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ static inline void spi_dma_ll_tx_enable_burst_data(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) @@ -1172,7 +1172,7 @@ static inline void spi_dma_ll_tx_enable_burst_data(spi_dma_dev_t *dma_out, uint3 * Enable DMA TX channel burst for descriptor * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ static inline void spi_dma_ll_tx_enable_burst_desc(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) @@ -1184,7 +1184,7 @@ static inline void spi_dma_ll_tx_enable_burst_desc(spi_dma_dev_t *dma_out, uint3 * Configuration of OUT EOF flag generation way * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. * @param enable 1: when dma pop all data from fifo 0:when ahb push all data to fifo. */ static inline void spi_dma_ll_set_out_eof_generation(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) @@ -1196,7 +1196,7 @@ static inline void spi_dma_ll_set_out_eof_generation(spi_dma_dev_t *dma_out, uin * Enable automatic outlink-writeback * * @param dma_out Beginning address of the DMA peripheral registers which transmits the data from RAM to a peripheral. - * @param channel DMA channel + * @param channel DMA channel, for chip version compatibility, not used. * @param enable True to enable, false to disable */ static inline void spi_dma_ll_enable_out_auto_wrback(spi_dma_dev_t *dma_out, uint32_t channel, bool enable) diff --git a/components/hal/include/hal/spi_types.h b/components/hal/include/hal/spi_types.h index 4872838e68..ebf4e3b345 100644 --- a/components/hal/include/hal/spi_types.h +++ b/components/hal/include/hal/spi_types.h @@ -23,7 +23,7 @@ * @brief Enum with the three SPI peripherals that are software-accessible in it */ typedef enum { -// SPI_HOST (SPI1_HOST) is not supported by the SPI Master and SPI Slave driver on ESP32-S2 +//SPI1 can be used as GPSPI only on ESP32 SPI1_HOST=0, ///< SPI1 SPI2_HOST=1, ///< SPI2 SPI3_HOST=2, ///< SPI3 From ed6fb33726282f6420b92ada99a4b862a8ee9c1b Mon Sep 17 00:00:00 2001 From: Armando Date: Sun, 7 Feb 2021 14:39:07 +0800 Subject: [PATCH 5/6] spi: remove hard-coded DMA chan in soc_caps.h --- components/driver/spi_common.c | 4 ++-- components/soc/esp32c3/include/soc/soc_caps.h | 9 --------- components/soc/esp32c3/spi_periph.c | 2 +- components/soc/esp32s3/include/soc/soc_caps.h | 2 -- components/soc/esp32s3/spi_periph.c | 4 ++-- 5 files changed, 5 insertions(+), 16 deletions(-) diff --git a/components/driver/spi_common.c b/components/driver/spi_common.c index c8f547b30b..fae1e0694e 100644 --- a/components/driver/spi_common.c +++ b/components/driver/spi_common.c @@ -53,7 +53,7 @@ static const char *SPI_TAG = "spi"; SPI_CHECK(GPIO_IS_VALID_GPIO(pin_num), pin_name" not valid", ESP_ERR_INVALID_ARG); \ } -#define MAIN_BUS_DEFAULT() { \ +#define SPI_MAIN_BUS_DEFAULT() { \ .host_id = 0, \ .bus_attr = { \ .tx_dma_chan = 0, \ @@ -88,7 +88,7 @@ ATOMIC_VAR_INIT(false), }; static const char* spi_claiming_func[3] = {NULL, NULL, NULL}; -static spicommon_bus_context_t s_mainbus = MAIN_BUS_DEFAULT(); +static spicommon_bus_context_t s_mainbus = SPI_MAIN_BUS_DEFAULT(); static spicommon_bus_context_t* bus_ctx[SOC_SPI_PERIPH_NUM] = {&s_mainbus}; #if !SOC_GDMA_SUPPORTED diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index c63a0c3867..55ce507b46 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -13,19 +13,10 @@ // There are 3 DMA channels on ESP32-C3 // Attention: These fixed DMA channels are temporarily workaround before we have a centralized DMA controller API to help alloc the channel dynamically // Remove them when GDMA driver API is ready -#define SOC_GDMA_SPI2_DMA_CHANNEL (2) #define SOC_GDMA_ADC_DMA_CHANNEL (0) - -//NOTE: The CHx number should be consistent with the selected DMA channel above -#define SOC_GDMA_SPI2_INTR_SOURCE ETS_DMA_CH2_INTR_SOURCE -//On C3, there is only 1 GPSPI controller (GPSPI2) -#define SOC_GDMA_SPI3_DMA_CHANNEL SOC_GDMA_SPI2_DMA_CHANNEL - #define SOC_GDMA_ADC_INTR_SOURCE ETS_DMA_CH0_INTR_SOURCE - #include "rmt_caps.h" - /*-------------------------- DAC CAPS ----------------------------------------*/ #define SOC_DAC_PERIPH_NUM 0 diff --git a/components/soc/esp32c3/spi_periph.c b/components/soc/esp32c3/spi_periph.c index 1d1b41df8f..ada81b36c3 100644 --- a/components/soc/esp32c3/spi_periph.c +++ b/components/soc/esp32c3/spi_periph.c @@ -63,7 +63,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .spihd_iomux_pin = FSPI_IOMUX_PIN_NUM_HD, .spics0_iomux_pin = FSPI_IOMUX_PIN_NUM_CS, .irq = ETS_SPI2_INTR_SOURCE, - .irq_dma = SOC_GDMA_SPI2_INTR_SOURCE, + .irq_dma = -1, .module = PERIPH_SPI2_MODULE, .hw = &GPSPI2, .func = FSPI_FUNC_NUM, diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index fe949f659f..b6a03c4a07 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -159,8 +159,6 @@ // Attention: These fixed DMA channels are temporarily workaround before we have a centralized DMA controller API to help alloc the channel dynamically // Remove them when GDMA driver API is ready -#define SOC_GDMA_SPI2_DMA_CHANNEL (1) -#define SOC_GDMA_SPI3_DMA_CHANNEL (2) #define SOC_GDMA_SHA_DMA_CHANNEL (3) #define SOC_GDMA_AES_DMA_CHANNEL (4) diff --git a/components/soc/esp32s3/spi_periph.c b/components/soc/esp32s3/spi_periph.c index de93c48ae6..4554c12f17 100644 --- a/components/soc/esp32s3/spi_periph.c +++ b/components/soc/esp32s3/spi_periph.c @@ -63,7 +63,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .spihd_iomux_pin = FSPI_IOMUX_PIN_NUM_HD, .spics0_iomux_pin = FSPI_IOMUX_PIN_NUM_CS, .irq = ETS_SPI2_INTR_SOURCE, - .irq_dma = ETS_SPI2_DMA_INTR_SOURCE, + .irq_dma = -1, .module = PERIPH_FSPI_MODULE, .hw = &GPSPI2, .func = FSPI_FUNC_NUM, @@ -89,7 +89,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { .spihd_iomux_pin = -1, .spics0_iomux_pin = -1, .irq = ETS_SPI3_INTR_SOURCE, - .irq_dma = ETS_SPI3_DMA_INTR_SOURCE, + .irq_dma = -1, .module = PERIPH_HSPI_MODULE, .hw = &GPSPI3, .func = -1, From 8a2f91b48ab14874627403a7277b86c87eed8a53 Mon Sep 17 00:00:00 2001 From: Armando Date: Sat, 20 Feb 2021 11:03:28 +0800 Subject: [PATCH 6/6] spi: add enum for spi dma channels --- components/driver/include/driver/spi_common.h | 33 +++++++---- .../include/driver/spi_common_internal.h | 4 +- components/driver/include/driver/spi_slave.h | 13 ++--- .../driver/include/driver/spi_slave_hd.h | 6 +- components/driver/spi_common.c | 51 +++++++++------- components/driver/spi_slave.c | 10 ++-- components/driver/spi_slave_hd.c | 6 +- components/driver/test/test_spi_master.c | 22 +++---- components/driver/test/test_spi_param.c | 58 +++++++++---------- components/driver/test/test_spi_slave.c | 6 +- components/driver/test/test_spi_slave_hd.c | 4 +- 11 files changed, 114 insertions(+), 99 deletions(-) diff --git a/components/driver/include/driver/spi_common.h b/components/driver/include/driver/spi_common.h index 3c5b599e63..05d7d2c776 100644 --- a/components/driver/include/driver/spi_common.h +++ b/components/driver/include/driver/spi_common.h @@ -29,8 +29,6 @@ extern "C" //Maximum amount of bytes that can be put in one DMA descriptor #define SPI_MAX_DMA_LEN (4096-4) -//Set the ``dma_chan`` to this, then driver will auto-alloc a DMA channel -#define DMA_AUTO_CHAN (-2) /** * Transform unsigned integer of length <= 32 bits to the format which can be @@ -74,6 +72,24 @@ extern "C" #define SPICOMMON_BUSFLAG_NATIVE_PINS SPICOMMON_BUSFLAG_IOMUX_PINS +/** + * @brief SPI DMA channels + */ +typedef enum { + SPI_DMA_DISABLED = 0, ///< Do not enable DMA for SPI +#if CONFIG_IDF_TARGET_ESP32 + SPI_DMA_CH1 = 1, ///< Enable DMA, select DMA Channel 1 + SPI_DMA_CH2 = 2, ///< Enable DMA, select DMA Channel 2 +#endif + SPI_DMA_CH_AUTO = 3, ///< Enable DMA, channel is automatically selected by driver +} spi_common_dma_t; + +#if __cplusplus +/* Needed for C++ backwards compatibility with earlier ESP-IDF where this argument is a bare 'int'. Can be removed in ESP-IDF 5 */ +typedef int spi_dma_chan_t; +#else +typedef spi_common_dma_t spi_dma_chan_t; +#endif /** * @brief This is a configuration structure for a SPI bus. @@ -107,13 +123,10 @@ typedef struct { * * @param host_id SPI peripheral that controls this bus * @param bus_config Pointer to a spi_bus_config_t struct specifying how the host should be initialized - * @param dma_chan - DMA_AUTO_CHAN: allocate a free channel automatically; - * - 1 or 2: assign a specific DMA channel; - * - 0: non-dma mode; - * Selecting a DMA channel for an SPI bus allows transfers on the bus to have sizes only - * limited by the amount of internal memory. Selecting no DMA channel (by passing the - * value 0) limits the amount of bytes transfered to a maximum of 64. Set to 0 if only - * the SPI flash uses this bus. Set to DMA_AUTO_CHAN to let the driver to allocate the DMA channel. + * @param dma_chan - Selecting a DMA channel for an SPI bus allows transactions on the bus with size only limited by the amount of internal memory. + * - Selecting SPI_DMA_DISABLED limits the size of transactions. + * - Set to SPI_DMA_DISABLED if only the SPI flash uses this bus. + * - Set to SPI_DMA_CH_AUTO to let the driver to allocate the DMA channel. * * @warning If a DMA channel is selected, any transmit and receive buffer used should be allocated in * DMA-capable memory. @@ -129,7 +142,7 @@ typedef struct { * - ESP_ERR_NO_MEM if out of memory * - ESP_OK on success */ -esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t *bus_config, int dma_chan); +esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t *bus_config, spi_dma_chan_t dma_chan); /** * @brief Free a SPI bus diff --git a/components/driver/include/driver/spi_common_internal.h b/components/driver/include/driver/spi_common_internal.h index ab0ed69dd9..b490efeb7e 100644 --- a/components/driver/include/driver/spi_common_internal.h +++ b/components/driver/include/driver/spi_common_internal.h @@ -121,7 +121,7 @@ bool spicommon_periph_free(spi_host_device_t host); * @brief Alloc DMA for SPI Slave * * @param host_id SPI host ID - * @param dma_chan DMA_AUTO_CHAN: auto dma allocate mode; 0: non-dma mode; 1 or 2: assign a specific DMA channel; + * @param dma_chan DMA channel to be used * @param[out] out_actual_tx_dma_chan Actual TX DMA channel (if you choose to assign a specific DMA channel, this will be the channel you assigned before) * @param[out] out_actual_rx_dma_chan Actual RX DMA channel (if you choose to assign a specific DMA channel, this will be the channel you assigned before) * @@ -130,7 +130,7 @@ bool spicommon_periph_free(spi_host_device_t host); * - ESP_ERR_NO_MEM: No enough memory * - ESP_ERR_NOT_FOUND: There is no available DMA channel */ -esp_err_t spicommon_slave_dma_chan_alloc(spi_host_device_t host_id, int dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan); +esp_err_t spicommon_slave_dma_chan_alloc(spi_host_device_t host_id, spi_dma_chan_t dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan); /** * @brief Free DMA for SPI Slave diff --git a/components/driver/include/driver/spi_slave.h b/components/driver/include/driver/spi_slave.h index ebb1268289..a970159f47 100644 --- a/components/driver/include/driver/spi_slave.h +++ b/components/driver/include/driver/spi_slave.h @@ -93,13 +93,10 @@ struct spi_slave_transaction_t { * @param host SPI peripheral to use as a SPI slave interface * @param bus_config Pointer to a spi_bus_config_t struct specifying how the host should be initialized * @param slave_config Pointer to a spi_slave_interface_config_t struct specifying the details for the slave interface - * @param dma_chan - DMA_AUTO_CHAN: allocate a free channel automatically; - * - 1 or 2: assign a specific DMA channel; - * - 0: non-dma mode; - * Selecting a DMA channel for an SPI bus allows transfers on the bus to have sizes only - * limited by the amount of internal memory. Selecting no DMA channel (by passing the - * value 0) limits the amount of bytes transfered to a maximum of 64. Set to 0 if only - * the SPI flash uses this bus. Set to DMA_AUTO_CHAN to let the driver to allocate the DMA channel. + * @param dma_chan - Selecting a DMA channel for an SPI bus allows transactions on the bus with size only limited by the amount of internal memory. + * - Selecting SPI_DMA_DISABLED limits the size of transactions. + * - Set to SPI_DMA_DISABLED if only the SPI flash uses this bus. + * - Set to SPI_DMA_CH_AUTO to let the driver to allocate the DMA channel. * * @warning If a DMA channel is selected, any transmit and receive buffer used should be allocated in * DMA-capable memory. @@ -115,7 +112,7 @@ struct spi_slave_transaction_t { * - ESP_ERR_NO_MEM if out of memory * - ESP_OK on success */ -esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *bus_config, const spi_slave_interface_config_t *slave_config, int dma_chan); +esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *bus_config, const spi_slave_interface_config_t *slave_config, spi_dma_chan_t dma_chan); /** * @brief Free a SPI bus claimed as a SPI slave interface diff --git a/components/driver/include/driver/spi_slave_hd.h b/components/driver/include/driver/spi_slave_hd.h index 80174dde9e..7e9289fb4b 100644 --- a/components/driver/include/driver/spi_slave_hd.h +++ b/components/driver/include/driver/spi_slave_hd.h @@ -86,11 +86,7 @@ typedef struct { uint32_t address_bits; ///< address field bits, multiples of 8 and at least 8. uint32_t dummy_bits; ///< dummy field bits, multiples of 8 and at least 8. uint32_t queue_size; ///< Transaction queue size. This sets how many transactions can be 'in the air' (queued using spi_slave_hd_queue_trans but not yet finished using spi_slave_hd_get_trans_result) at the same time - int dma_chan; /**< DMA channel to used. - * - DMA_AUTO_CHAN: allocate a free channel automatically; - * - 1 or 2: assign a specific DMA channel; - * - 0: non-dma mode; - */ + spi_dma_chan_t dma_chan; ///< DMA channel to used. spi_slave_hd_callback_config_t cb_config; ///< Callback configuration } spi_slave_hd_slot_config_t; diff --git a/components/driver/spi_common.c b/components/driver/spi_common.c index fae1e0694e..f0e6cae24b 100644 --- a/components/driver/spi_common.c +++ b/components/driver/spi_common.c @@ -164,8 +164,7 @@ static inline periph_module_t get_dma_periph(int dma_chan) #endif } -//On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same -static bool spicommon_dma_chan_claim(int dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan) +static bool spicommon_dma_chan_claim(int dma_chan, uint32_t *out_actual_dma_chan) { bool ret = false; @@ -174,8 +173,7 @@ static bool spicommon_dma_chan_claim(int dma_chan, uint32_t *out_actual_tx_dma_c if (!is_used) { spi_dma_chan_enabled |= BIT(dma_chan); periph_module_enable(get_dma_periph(dma_chan)); - *out_actual_tx_dma_chan = dma_chan; - *out_actual_rx_dma_chan = dma_chan; + *out_actual_dma_chan = dma_chan; ret = true; } portEXIT_CRITICAL(&spi_dma_spinlock); @@ -192,34 +190,39 @@ static void spicommon_connect_spi_and_dma(spi_host_device_t host, int dma_chan) #endif } -static esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, int dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan) +static esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, spi_dma_chan_t dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan) { assert(is_valid_host(host_id)); #if CONFIG_IDF_TARGET_ESP32 - assert((dma_chan > 0 && dma_chan <= 2) || dma_chan == DMA_AUTO_CHAN); + assert(dma_chan > SPI_DMA_DISABLED && dma_chan <= SPI_DMA_CH_AUTO); #elif CONFIG_IDF_TARGET_ESP32S2 - assert(dma_chan == host_id || dma_chan == DMA_AUTO_CHAN); + assert(dma_chan == (int)host_id || dma_chan == SPI_DMA_CH_AUTO); #endif esp_err_t ret = ESP_OK; bool success = false; + uint32_t actual_dma_chan = 0; - if (dma_chan == DMA_AUTO_CHAN) { + if (dma_chan == SPI_DMA_CH_AUTO) { #if CONFIG_IDF_TARGET_ESP32 for (int i = 1; i < SOC_SPI_DMA_CHAN_NUM+1; i++) { - success = spicommon_dma_chan_claim(i, out_actual_tx_dma_chan, out_actual_rx_dma_chan); + success = spicommon_dma_chan_claim(i, &actual_dma_chan); if (success) { break; } } #elif CONFIG_IDF_TARGET_ESP32S2 //On ESP32S2, each SPI controller has its own DMA channel - success = spicommon_dma_chan_claim(host_id, out_actual_tx_dma_chan, out_actual_rx_dma_chan); + success = spicommon_dma_chan_claim(host_id, &actual_dma_chan); #endif //#if CONFIG_IDF_TARGET_XXX - } else if (dma_chan > 0) { - success = spicommon_dma_chan_claim(dma_chan, out_actual_tx_dma_chan, out_actual_rx_dma_chan); + } else { + success = spicommon_dma_chan_claim((int)dma_chan, &actual_dma_chan); } + //On ESP32 and ESP32S2, actual_tx_dma_chan and actual_rx_dma_chan are always same + *out_actual_tx_dma_chan = actual_dma_chan; + *out_actual_rx_dma_chan = actual_dma_chan; + if (!success) { SPI_CHECK(false, "no available dma channel", ESP_ERR_NOT_FOUND); } @@ -230,15 +233,15 @@ static esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, int dma_cha } #else //SOC_GDMA_SUPPORTED -static esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, int dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan) +static esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, spi_dma_chan_t dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan) { assert(is_valid_host(host_id)); - assert(dma_chan == DMA_AUTO_CHAN); + assert(dma_chan == SPI_DMA_CH_AUTO); esp_err_t ret = ESP_OK; spicommon_bus_context_t *ctx = bus_ctx[host_id]; - if (dma_chan == DMA_AUTO_CHAN) { + if (dma_chan == SPI_DMA_CH_AUTO) { gdma_channel_alloc_config_t tx_alloc_config = { .flags.reserve_sibling = 1, .direction = GDMA_CHANNEL_DIRECTION_TX, @@ -275,10 +278,14 @@ static esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, int dma_cha } #endif //#if !SOC_GDMA_SUPPORTED -esp_err_t spicommon_slave_dma_chan_alloc(spi_host_device_t host_id, int dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan) +esp_err_t spicommon_slave_dma_chan_alloc(spi_host_device_t host_id, spi_dma_chan_t dma_chan, uint32_t *out_actual_tx_dma_chan, uint32_t *out_actual_rx_dma_chan) { assert(is_valid_host(host_id)); - assert((dma_chan == 1 || dma_chan == 2 || dma_chan == DMA_AUTO_CHAN)); +#if CONFIG_IDF_TARGET_ESP32 + assert(dma_chan > SPI_DMA_DISABLED && dma_chan <= SPI_DMA_CH_AUTO); +#elif CONFIG_IDF_TARGET_ESP32S2 + assert(dma_chan == (int)host_id || dma_chan == SPI_DMA_CH_AUTO); +#endif esp_err_t ret = ESP_OK; uint32_t actual_tx_dma_chan = 0; @@ -608,7 +615,7 @@ spi_bus_lock_handle_t spi_bus_lock_get_by_id(spi_host_device_t host_id) } //----------------------------------------------------------master bus init-------------------------------------------------------// -esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t *bus_config, int dma_chan) +esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t *bus_config, spi_dma_chan_t dma_chan) { esp_err_t err = ESP_OK; spicommon_bus_context_t *ctx = NULL; @@ -619,11 +626,11 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t * SPI_CHECK(is_valid_host(host_id), "invalid host_id", ESP_ERR_INVALID_ARG); SPI_CHECK(bus_ctx[host_id] == NULL, "SPI bus already initialized.", ESP_ERR_INVALID_STATE); #ifdef CONFIG_IDF_TARGET_ESP32 - SPI_CHECK( (dma_chan >= 0 && dma_chan <= 2) || dma_chan == DMA_AUTO_CHAN, "invalid dma channel", ESP_ERR_INVALID_ARG ); + SPI_CHECK(dma_chan >= SPI_DMA_DISABLED && dma_chan <= SPI_DMA_CH_AUTO, "invalid dma channel", ESP_ERR_INVALID_ARG ); #elif CONFIG_IDF_TARGET_ESP32S2 - SPI_CHECK( dma_chan == 0 || dma_chan == host_id || dma_chan == DMA_AUTO_CHAN, "invalid dma channel", ESP_ERR_INVALID_ARG ); + SPI_CHECK( dma_chan == SPI_DMA_DISABLED || dma_chan == (int)host_id || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel", ESP_ERR_INVALID_ARG ); #elif SOC_GDMA_SUPPORTED - SPI_CHECK( dma_chan == 0 || dma_chan == DMA_AUTO_CHAN, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG ); + SPI_CHECK( dma_chan == SPI_DMA_DISABLED || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG ); #endif SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH|ESP_INTR_FLAG_EDGE|ESP_INTR_FLAG_INTRDISABLED))==0, "intr flag not allowed", ESP_ERR_INVALID_ARG); #ifndef CONFIG_SPI_MASTER_ISR_IN_IRAM @@ -644,7 +651,7 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t * bus_attr = &ctx->bus_attr; bus_attr->bus_cfg = *bus_config; - if (dma_chan != 0) { + if (dma_chan != SPI_DMA_DISABLED) { bus_attr->dma_enabled = 1; err = spicommon_dma_chan_alloc(host_id, dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan); diff --git a/components/driver/spi_slave.c b/components/driver/spi_slave.c index 3e42e03f43..09945a988d 100644 --- a/components/driver/spi_slave.c +++ b/components/driver/spi_slave.c @@ -112,7 +112,7 @@ static inline void restore_cs(spi_slave_t *host) } } -esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *bus_config, const spi_slave_interface_config_t *slave_config, int dma_chan) +esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *bus_config, const spi_slave_interface_config_t *slave_config, spi_dma_chan_t dma_chan) { bool spi_chan_claimed; uint32_t actual_tx_dma_chan = 0; @@ -122,11 +122,11 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b //We only support HSPI/VSPI, period. SPI_CHECK(is_valid_host(host), "invalid host", ESP_ERR_INVALID_ARG); #ifdef CONFIG_IDF_TARGET_ESP32 - SPI_CHECK( (dma_chan >= 0 && dma_chan <= 2) || dma_chan == DMA_AUTO_CHAN, "invalid dma channel", ESP_ERR_INVALID_ARG ); + SPI_CHECK(dma_chan >= SPI_DMA_DISABLED && dma_chan <= SPI_DMA_CH_AUTO, "invalid dma channel", ESP_ERR_INVALID_ARG ); #elif CONFIG_IDF_TARGET_ESP32S2 - SPI_CHECK( dma_chan == 0 || dma_chan == host || dma_chan == DMA_AUTO_CHAN, "invalid dma channel", ESP_ERR_INVALID_ARG ); + SPI_CHECK( dma_chan == SPI_DMA_DISABLED || dma_chan == (int)host || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel", ESP_ERR_INVALID_ARG ); #elif SOC_GDMA_SUPPORTED - SPI_CHECK( dma_chan == 0 || dma_chan == DMA_AUTO_CHAN, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG ); + SPI_CHECK( dma_chan == SPI_DMA_DISABLED || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG ); #endif SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH|ESP_INTR_FLAG_EDGE|ESP_INTR_FLAG_INTRDISABLED))==0, "intr flag not allowed", ESP_ERR_INVALID_ARG); #ifndef CONFIG_SPI_SLAVE_ISR_IN_IRAM @@ -146,7 +146,7 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b memcpy(&spihost[host]->cfg, slave_config, sizeof(spi_slave_interface_config_t)); spihost[host]->id = host; - bool use_dma = (dma_chan != 0); + bool use_dma = (dma_chan != SPI_DMA_DISABLED); spihost[host]->dma_enabled = use_dma; if (use_dma) { ret = spicommon_slave_dma_chan_alloc(host, dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan); diff --git a/components/driver/spi_slave_hd.c b/components/driver/spi_slave_hd.c index 44298e3049..90dd626e41 100644 --- a/components/driver/spi_slave_hd.c +++ b/components/driver/spi_slave_hd.c @@ -75,9 +75,9 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b SPIHD_CHECK(VALID_HOST(host_id), "invalid host", ESP_ERR_INVALID_ARG); #if CONFIG_IDF_TARGET_ESP32S2 - SPIHD_CHECK(config->dma_chan == 0 || config->dma_chan == host_id || config->dma_chan == DMA_AUTO_CHAN, "invalid dma channel", ESP_ERR_INVALID_ARG); + SPIHD_CHECK(config->dma_chan == SPI_DMA_DISABLED || config->dma_chan == (int)host_id || config->dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel", ESP_ERR_INVALID_ARG); #elif SOC_GDMA_SUPPORTED - SPIHD_CHECK(config->dma_chan == 0 || config->dma_chan == DMA_AUTO_CHAN, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG); + SPIHD_CHECK(config->dma_chan == SPI_DMA_DISABLED || config->dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG); #endif #if !CONFIG_IDF_TARGET_ESP32S2 //Append mode is only supported on ESP32S2 now @@ -95,7 +95,7 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b spihost[host_id] = host; memset(host, 0, sizeof(spi_slave_hd_slot_t)); host->int_spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; - host->dma_enabled = (config->dma_chan != 0); + host->dma_enabled = (config->dma_chan != SPI_DMA_DISABLED); if (host->dma_enabled) { ret = spicommon_slave_dma_chan_alloc(host_id, config->dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan); diff --git a/components/driver/test/test_spi_master.c b/components/driver/test/test_spi_master.c index 47355a462a..d4c7749e0d 100644 --- a/components/driver/test/test_spi_master.c +++ b/components/driver/test/test_spi_master.c @@ -74,7 +74,7 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]") .quadhd_io_num=-1 }; esp_err_t ret; - ret = spi_bus_initialize(TEST_SPI_HOST, &buscfg, DMA_AUTO_CHAN); + ret = spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO); TEST_ASSERT(ret==ESP_OK); check_spi_pre_n_for(26000000, 1, 3); @@ -112,7 +112,7 @@ static spi_device_handle_t setup_spi_bus_loopback(int clkspeed, bool dma) { }; spi_device_handle_t handle; - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, dma ? DMA_AUTO_CHAN : 0)); + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, dma ? SPI_DMA_CH_AUTO : 0)); TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &handle)); //connect MOSI to two devices breaks the output, fix it. spitest_gpio_output_sel(PIN_NUM_MOSI, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out); @@ -273,7 +273,7 @@ static esp_err_t test_master_pins(int mosi, int miso, int sclk, int cs) spi_device_interface_config_t master_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG(); master_cfg.spics_io_num = cs; - ret = spi_bus_initialize(TEST_SPI_HOST, &cfg, DMA_AUTO_CHAN); + ret = spi_bus_initialize(TEST_SPI_HOST, &cfg, SPI_DMA_CH_AUTO); if (ret != ESP_OK) { return ret; } @@ -300,7 +300,7 @@ static esp_err_t test_slave_pins(int mosi, int miso, int sclk, int cs) spi_slave_interface_config_t slave_cfg = SPI_SLAVE_TEST_DEFAULT_CONFIG(); slave_cfg.spics_io_num = cs; - ret = spi_slave_initialize(TEST_SLAVE_HOST, &cfg, &slave_cfg, DMA_AUTO_CHAN); + ret = spi_slave_initialize(TEST_SLAVE_HOST, &cfg, &slave_cfg, SPI_DMA_CH_AUTO); if (ret != ESP_OK) { return ret; } @@ -507,7 +507,7 @@ TEST_CASE("SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)" //initialize for first host host = TEST_SPI_HOST; - TEST_ESP_OK(spi_bus_initialize(host, &bus_config, DMA_AUTO_CHAN)); + TEST_ESP_OK(spi_bus_initialize(host, &bus_config, SPI_DMA_CH_AUTO)); TEST_ESP_OK(spi_bus_add_device(host, &device_config, &spi)); printf("before first xmit\n"); @@ -519,7 +519,7 @@ TEST_CASE("SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)" //for second host and failed before host = TEST_SLAVE_HOST; - TEST_ESP_OK(spi_bus_initialize(host, &bus_config, DMA_AUTO_CHAN)); + TEST_ESP_OK(spi_bus_initialize(host, &bus_config, SPI_DMA_CH_AUTO)); TEST_ESP_OK(spi_bus_add_device(host, &device_config, &spi)); printf("before second xmit\n"); @@ -587,7 +587,7 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]") spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG(); //Initialize the SPI bus - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, DMA_AUTO_CHAN)); + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO)); //Attach the LCD to the SPI bus TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &spi)); //connect MOSI to two devices breaks the output, fix it. @@ -671,7 +671,7 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]") .pre_cb=NULL, }; //Initialize the SPI bus - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, DMA_AUTO_CHAN)); + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO)); //Attach the LCD to the SPI bus TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &spi)); @@ -740,7 +740,7 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first) //initial master, mode 0, 1MHz spi_bus_config_t buscfg=SPI_BUS_TEST_DEFAULT_CONFIG(); buscfg.quadhd_io_num = UNCONNECTED_PIN; - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, DMA_AUTO_CHAN)); + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO)); spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG(); devcfg.clock_speed_hz = 1*1000*1000; if (lsb_first) devcfg.flags |= SPI_DEVICE_BIT_LSBFIRST; @@ -978,6 +978,8 @@ TEST_CASE("SPI master hd dma TX without RX test", "[spi]") TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &spi)); spi_slave_interface_config_t slave_cfg = SPI_SLAVE_TEST_DEFAULT_CONFIG(); + + printf("TEST_SLAVE_HOST is %d\n", TEST_SLAVE_HOST); TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &bus_cfg, &slave_cfg, TEST_SLAVE_HOST)); same_pin_func_sel(bus_cfg, dev_cfg, 0); @@ -1075,7 +1077,7 @@ static void speed_setup(spi_device_handle_t* spi, bool use_dma) devcfg.queue_size=8; //We want to be able to queue 7 transactions at a time //Initialize the SPI bus and the device to test - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, (use_dma ? DMA_AUTO_CHAN : 0))); + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, (use_dma ? SPI_DMA_CH_AUTO : 0))); TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, spi)); } diff --git a/components/driver/test/test_spi_param.c b/components/driver/test/test_spi_param.c index 741e65b7e8..66dc3499bc 100644 --- a/components/driver/test/test_spi_param.c +++ b/components/driver/test/test_spi_param.c @@ -99,13 +99,13 @@ static void local_test_start(spi_device_handle_t *spi, int freq, const spitest_p slvcfg.mode = pset->mode; slave_pull_up(&buscfg, slvcfg.spics_io_num); - int dma_chan = (pset->master_dma_chan == 0) ? 0 : DMA_AUTO_CHAN; + int dma_chan = (pset->master_dma_chan == 0) ? 0 : SPI_DMA_CH_AUTO; TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, dma_chan)); TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, spi)); //slave automatically use iomux pins if pins are on VSPI_* pins buscfg.quadhd_io_num = -1; - int slave_dma_chan = (pset->slave_dma_chan == 0) ? 0 : DMA_AUTO_CHAN; + int slave_dma_chan = (pset->slave_dma_chan == 0) ? 0 : SPI_DMA_CH_AUTO; TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, slave_dma_chan)); //initialize master and slave on the same pins break some of the output configs, fix them @@ -393,7 +393,7 @@ static spitest_param_set_t mode_pgroup[] = { .master_limit = SPI_MASTER_FREQ_13M, .dup = FULL_DUPLEX, .mode = 0, - .slave_dma_chan = DMA_AUTO_CHAN, + .slave_dma_chan = SPI_DMA_CH_AUTO, .master_iomux = false, .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT, @@ -405,7 +405,7 @@ static spitest_param_set_t mode_pgroup[] = { .master_limit = SPI_MASTER_FREQ_13M, .dup = FULL_DUPLEX, .mode = 1, - .slave_dma_chan = DMA_AUTO_CHAN, + .slave_dma_chan = SPI_DMA_CH_AUTO, .master_iomux = false, .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT, @@ -416,7 +416,7 @@ static spitest_param_set_t mode_pgroup[] = { .master_limit = SPI_MASTER_FREQ_13M, .dup = FULL_DUPLEX, .mode = 2, - .slave_dma_chan = DMA_AUTO_CHAN, + .slave_dma_chan = SPI_DMA_CH_AUTO, .master_iomux = false, .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT, @@ -428,7 +428,7 @@ static spitest_param_set_t mode_pgroup[] = { .master_limit = SPI_MASTER_FREQ_13M, .dup = FULL_DUPLEX, .mode = 3, - .slave_dma_chan = DMA_AUTO_CHAN, + .slave_dma_chan = SPI_DMA_CH_AUTO, .master_iomux = false, .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT, @@ -471,7 +471,7 @@ static spitest_param_set_t mode_pgroup[] = { .freq_list = test_freq_mode_local, .dup = HALF_DUPLEX_MISO, .mode = 0, - .slave_dma_chan = DMA_AUTO_CHAN, + .slave_dma_chan = SPI_DMA_CH_AUTO, .master_iomux = false, .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT+SLAVE_EXTRA_DELAY_DMA, @@ -481,7 +481,7 @@ static spitest_param_set_t mode_pgroup[] = { .freq_list = test_freq_mode_local, .dup = HALF_DUPLEX_MISO, .mode = 1, - .slave_dma_chan = DMA_AUTO_CHAN, + .slave_dma_chan = SPI_DMA_CH_AUTO, .master_iomux = false, .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT, @@ -491,7 +491,7 @@ static spitest_param_set_t mode_pgroup[] = { .freq_list = test_freq_mode_local, .dup = HALF_DUPLEX_MISO, .mode = 2, - .slave_dma_chan = DMA_AUTO_CHAN, + .slave_dma_chan = SPI_DMA_CH_AUTO, .master_iomux = false, .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT+SLAVE_EXTRA_DELAY_DMA, @@ -501,7 +501,7 @@ static spitest_param_set_t mode_pgroup[] = { .freq_list = test_freq_mode_local, .dup = HALF_DUPLEX_MISO, .mode = 3, - .slave_dma_chan = DMA_AUTO_CHAN, + .slave_dma_chan = SPI_DMA_CH_AUTO, .master_iomux = false, .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, .slave_tv_ns = TV_INT_CONNECT, @@ -546,7 +546,7 @@ TEST_CASE("Slave receive correct data", "[spi]") .master_iomux = false, .slave_iomux = false, .master_dma_chan = 0, - .slave_dma_chan = (dma_chan ? DMA_AUTO_CHAN: 0), + .slave_dma_chan = (dma_chan ? SPI_DMA_CH_AUTO: 0), }; ESP_LOGI(SLAVE_TAG, "Test slave recv @ mode %d, dma enabled=%d", spi_mode, dma_chan); @@ -704,7 +704,7 @@ static void test_master_start(spi_device_handle_t *spi, int freq, const spitest_ devpset.clock_speed_hz = freq; if (pset->master_limit != 0 && freq > pset->master_limit) devpset.flags |= SPI_DEVICE_NO_DUMMY; - int dma_chan = (pset->master_dma_chan == 0) ? 0 : DMA_AUTO_CHAN; + int dma_chan = (pset->master_dma_chan == 0) ? 0 : SPI_DMA_CH_AUTO; TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buspset, dma_chan)); TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devpset, spi)); @@ -825,7 +825,7 @@ static void timing_slave_start(int speed, const spitest_param_set_t* pset, spite //Enable pull-ups on SPI lines so we don't detect rogue pulses when no master is connected. slave_pull_up(&slv_buscfg, slvcfg.spics_io_num); - int slave_dma_chan = (pset->slave_dma_chan == 0) ? 0 : DMA_AUTO_CHAN; + int slave_dma_chan = (pset->slave_dma_chan == 0) ? 0 : SPI_DMA_CH_AUTO; TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &slv_buscfg, &slvcfg, slave_dma_chan)); //prepare data for the master @@ -1086,8 +1086,8 @@ spitest_param_set_t mode_conf[] = { .slave_iomux = true, .slave_tv_ns = DELAY_HCLK_UNTIL_7M, .mode = 0, - .master_dma_chan = DMA_AUTO_CHAN, - .slave_dma_chan = DMA_AUTO_CHAN, + .master_dma_chan = SPI_DMA_CH_AUTO, + .slave_dma_chan = SPI_DMA_CH_AUTO, .length_aligned = true, }, { .pset_name = "mode 1, DMA", @@ -1098,8 +1098,8 @@ spitest_param_set_t mode_conf[] = { .slave_iomux = true, .slave_tv_ns = TV_WITH_ESP_SLAVE, .mode = 1, - .master_dma_chan = DMA_AUTO_CHAN, - .slave_dma_chan = DMA_AUTO_CHAN, + .master_dma_chan = SPI_DMA_CH_AUTO, + .slave_dma_chan = SPI_DMA_CH_AUTO, .length_aligned = true, }, { .pset_name = "mode 2, DMA", @@ -1110,8 +1110,8 @@ spitest_param_set_t mode_conf[] = { .slave_iomux = true, .slave_tv_ns = DELAY_HCLK_UNTIL_7M, .mode = 2, - .master_dma_chan = DMA_AUTO_CHAN, - .slave_dma_chan = DMA_AUTO_CHAN, + .master_dma_chan = SPI_DMA_CH_AUTO, + .slave_dma_chan = SPI_DMA_CH_AUTO, .length_aligned = true, }, { .pset_name = "mode 3, DMA", @@ -1122,8 +1122,8 @@ spitest_param_set_t mode_conf[] = { .slave_iomux = true, .slave_tv_ns = TV_WITH_ESP_SLAVE, .mode = 3, - .master_dma_chan = DMA_AUTO_CHAN, - .slave_dma_chan = DMA_AUTO_CHAN, + .master_dma_chan = SPI_DMA_CH_AUTO, + .slave_dma_chan = SPI_DMA_CH_AUTO, .length_aligned = true, }, //the master can only read to 16MHz, use half-duplex mode to read at 20. @@ -1134,8 +1134,8 @@ spitest_param_set_t mode_conf[] = { .slave_iomux = true, .slave_tv_ns = TV_WITH_ESP_SLAVE, .mode = 0, - .master_dma_chan = DMA_AUTO_CHAN, - .slave_dma_chan = DMA_AUTO_CHAN, + .master_dma_chan = SPI_DMA_CH_AUTO, + .slave_dma_chan = SPI_DMA_CH_AUTO, }, { .pset_name = "mode 1, DMA, 20M", .freq_list = test_freq_20M_only, @@ -1144,8 +1144,8 @@ spitest_param_set_t mode_conf[] = { .slave_iomux = true, .slave_tv_ns = TV_WITH_ESP_SLAVE, .mode = 1, - .master_dma_chan = DMA_AUTO_CHAN, - .slave_dma_chan = DMA_AUTO_CHAN, + .master_dma_chan = SPI_DMA_CH_AUTO, + .slave_dma_chan = SPI_DMA_CH_AUTO, }, { .pset_name = "mode 2, DMA, 20M", .freq_list = test_freq_20M_only, @@ -1154,8 +1154,8 @@ spitest_param_set_t mode_conf[] = { .slave_iomux = true, .slave_tv_ns = TV_WITH_ESP_SLAVE, .mode = 2, - .master_dma_chan = DMA_AUTO_CHAN, - .slave_dma_chan = DMA_AUTO_CHAN, + .master_dma_chan = SPI_DMA_CH_AUTO, + .slave_dma_chan = SPI_DMA_CH_AUTO, }, { .pset_name = "mode 3, DMA, 20M", .freq_list = test_freq_20M_only, @@ -1164,8 +1164,8 @@ spitest_param_set_t mode_conf[] = { .slave_iomux = true, .slave_tv_ns = TV_WITH_ESP_SLAVE, .mode = 3, - .master_dma_chan = DMA_AUTO_CHAN, - .slave_dma_chan = DMA_AUTO_CHAN, + .master_dma_chan = SPI_DMA_CH_AUTO, + .slave_dma_chan = SPI_DMA_CH_AUTO, }, }; TEST_SPI_MASTER_SLAVE(MODE, mode_conf, "") diff --git a/components/driver/test/test_spi_slave.c b/components/driver/test/test_spi_slave.c index f5bfe20baa..ab1f145cf0 100644 --- a/components/driver/test/test_spi_slave.c +++ b/components/driver/test/test_spi_slave.c @@ -48,7 +48,7 @@ static void master_init_nodma( spi_device_handle_t* spi) .cs_ena_pretrans=1, }; //Initialize the SPI bus - ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, DMA_AUTO_CHAN); + ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO); TEST_ASSERT(ret==ESP_OK); //Attach the LCD to the SPI bus ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, spi); @@ -75,7 +75,7 @@ static void slave_init(void) gpio_set_pull_mode(PIN_NUM_CLK, GPIO_PULLUP_ONLY); gpio_set_pull_mode(PIN_NUM_CS, GPIO_PULLUP_ONLY); //Initialize SPI slave interface - TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, DMA_AUTO_CHAN)); + TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, SPI_DMA_CH_AUTO)); } TEST_CASE("test slave send unaligned","[spi]") @@ -220,7 +220,7 @@ static void unaligned_test_slave(void) { spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG(); spi_slave_interface_config_t slvcfg = SPI_SLAVE_TEST_DEFAULT_CONFIG(); - TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, DMA_AUTO_CHAN)); + TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &buscfg, &slvcfg, SPI_DMA_CH_AUTO)); uint8_t *slave_send_buf = heap_caps_malloc(BUF_SIZE, MALLOC_CAP_DMA); uint8_t *slave_recv_buf = heap_caps_calloc(BUF_SIZE, 1, MALLOC_CAP_DMA); diff --git a/components/driver/test/test_spi_slave_hd.c b/components/driver/test/test_spi_slave_hd.c index 6cf9eb2a1d..1babb5fc98 100644 --- a/components/driver/test/test_spi_slave_hd.c +++ b/components/driver/test/test_spi_slave_hd.c @@ -99,7 +99,7 @@ static void init_master_hd(spi_device_handle_t* spi, const spitest_param_set_t* bus_cfg.flags |= SPICOMMON_BUSFLAG_GPIO_PINS; #endif - TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, DMA_AUTO_CHAN)); + TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, SPI_DMA_CH_AUTO)); spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG(); dev_cfg.flags = SPI_DEVICE_HALFDUPLEX; dev_cfg.command_bits = 8; @@ -122,7 +122,7 @@ static void init_slave_hd(int mode, bool append_mode, const spi_slave_hd_callbac #endif spi_slave_hd_slot_config_t slave_hd_cfg = SPI_SLOT_TEST_DEFAULT_CONFIG(); slave_hd_cfg.mode = mode; - slave_hd_cfg.dma_chan = DMA_AUTO_CHAN; + slave_hd_cfg.dma_chan = SPI_DMA_CH_AUTO; if (append_mode) { slave_hd_cfg.flags |= SPI_SLAVE_HD_APPEND_MODE; }