From bd7bcbb03ba01d34734d29819a531518a9b41b06 Mon Sep 17 00:00:00 2001 From: zlq Date: Wed, 27 Jul 2022 18:18:03 +0800 Subject: [PATCH] 1.add ldo parameters in efuse table; 2.set ldo dbias based on pvt-efuse; 3.add pll cali stop function; 4. add efuse_ocode --- components/esp_hw_support/port/esp32c2/rtc_clk.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/esp_hw_support/port/esp32c2/rtc_clk.c b/components/esp_hw_support/port/esp32c2/rtc_clk.c index 73516f5865..a0d88be36f 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c2/rtc_clk.c @@ -28,7 +28,7 @@ static const char *TAG = "rtc_clk"; // Current PLL frequency, in 480MHZ. Zero if PLL is not enabled. static int s_cur_pll_freq; -static void rtc_clk_cpu_freq_to_xtal(int freq, int div); +void rtc_clk_cpu_freq_to_xtal(int freq, int div); static void rtc_clk_cpu_freq_to_8m(void); void rtc_clk_32k_enable_external(void) @@ -279,7 +279,7 @@ void rtc_clk_cpu_freq_set_xtal(void) /** * Switch to XTAL frequency. Does not disable the PLL. */ -static void rtc_clk_cpu_freq_to_xtal(int freq, int div) +void rtc_clk_cpu_freq_to_xtal(int freq, int div) { ets_update_cpu_frequency(freq); /* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */