esp_system: enable "cache disable but cache accessed" interrupt for ESP32-S3

components/esp_system/port/arch/xtensa/panic_arch.c

@@ -422,11 +422,7 @@ void panic_soc_fill_info(void *f, panic_info_t *info)
         "Coprocessor exception",
         "Interrupt wdt timeout on CPU0",
         "Interrupt wdt timeout on CPU1",
-#if CONFIG_IDF_TARGET_ESP32
         "Cache disabled but cached memory region accessed",
-#elif CONFIG_IDF_TARGET_ESP32S2
-        "Cache error",
-#endif
     };
 
     info->reason = pseudo_reason[0];
@@ -441,7 +437,7 @@ void panic_soc_fill_info(void *f, panic_info_t *info)
         info->exception = PANIC_EXCEPTION_DEBUG;
     }
 
-#if CONFIG_IDF_TARGET_ESP32S2
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
     if (frame->exccause == PANIC_RSN_CACHEERR) {
 #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
         if ( esp_memprot_is_intr_ena_any() ) {

components/esp_system/port/soc/esp32s3/cache_err_int.c

@@ -1,16 +1,8 @@
-// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 
 /**
  * @file cache_err_int.c
@@ -65,11 +57,69 @@ void esp_cache_err_int_init(void)
                       EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA |
                       EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA);
 
+    if (core_id == PRO_CPU_NUM) {
+        intr_matrix_set(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
+        /* On the hardware side, stat by clearing all the bits reponsible for
+         * enabling cache access error interrupts.  */
+        SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG,
+                EXTMEM_CORE0_DBUS_REJECT_INT_CLR |
+                EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR |
+                EXTMEM_CORE0_IBUS_REJECT_INT_CLR |
+                EXTMEM_CORE0_IBUS_WR_IC_INT_CLR |
+                EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR);
+
+        /* Enable cache access error interrupts */
+        SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG,
+                EXTMEM_CORE0_DBUS_REJECT_INT_ENA |
+                EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA |
+                EXTMEM_CORE0_IBUS_REJECT_INT_ENA |
+                EXTMEM_CORE0_IBUS_WR_IC_INT_ENA |
+                EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA);
+    } else {
+        intr_matrix_set(core_id, ETS_CACHE_CORE1_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
+
+        /* On the hardware side, stat by clearing all the bits reponsible for
+         * enabling cache access error interrupts.  */
+        SET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_CLR_REG,
+                EXTMEM_CORE1_DBUS_REJECT_INT_CLR |
+                EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR |
+                EXTMEM_CORE1_IBUS_REJECT_INT_CLR |
+                EXTMEM_CORE1_IBUS_WR_IC_INT_CLR |
+                EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR);
+
+        /* Enable cache access error interrupts */
+        SET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_ENA_REG,
+                EXTMEM_CORE1_DBUS_REJECT_INT_ENA |
+                EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA |
+                EXTMEM_CORE1_IBUS_REJECT_INT_ENA |
+                EXTMEM_CORE1_IBUS_WR_IC_INT_ENA |
+                EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA);
+    }
+
     ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
 }
 
 int IRAM_ATTR esp_cache_err_get_cpuid(void)
 {
-    // FIXME
+    const uint32_t pro_mask = EXTMEM_CORE0_DBUS_REJECT_ST |
+                EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST |
+                EXTMEM_CORE0_IBUS_REJECT_ST |
+                EXTMEM_CORE0_IBUS_WR_ICACHE_ST |
+                EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST;
+
+    if (GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, pro_mask)) {
+        return PRO_CPU_NUM;
+    }
+
+    const uint32_t app_mask = EXTMEM_CORE1_DBUS_REJECT_ST |
+                EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST |
+                EXTMEM_CORE1_IBUS_REJECT_ST |
+                EXTMEM_CORE1_IBUS_WR_ICACHE_ST |
+                EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST;
+
+    if (GET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_ST_REG, app_mask)) {
+        return APP_CPU_NUM;
+    }
+
     return -1;
 }

tools/ci/check_copyright_ignore.txt

@@ -1154,7 +1154,6 @@ components/esp_system/port/soc/esp32s2/clk.c
 components/esp_system/port/soc/esp32s2/reset_reason.c
 components/esp_system/port/soc/esp32s2/system_internal.c
 components/esp_system/port/soc/esp32s2/usb_console.c
-components/esp_system/port/soc/esp32s3/cache_err_int.c
 components/esp_system/port/soc/esp32s3/cache_err_int.h
 components/esp_system/port/soc/esp32s3/clk.c
 components/esp_system/port/soc/esp32s3/reset_reason.c