From bc54778b6cdef808971b4d7fda83c45848dee9b6 Mon Sep 17 00:00:00 2001 From: jiangguangming Date: Wed, 12 Oct 2022 20:07:40 +0800 Subject: [PATCH 1/4] esp_rom: update esp_rom_caps.h --- components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld | 1 + components/esp_rom/esp32c3/Kconfig.soc_caps.in | 4 ++++ components/esp_rom/esp32c3/esp_rom_caps.h | 1 + components/esp_rom/esp32h2/Kconfig.soc_caps.in | 4 ++++ components/esp_rom/esp32h2/esp_rom_caps.h | 1 + components/esp_rom/patches/esp_rom_sys.c | 6 ++++-- 6 files changed, 15 insertions(+), 2 deletions(-) diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld index 4c39a51332..565d2a6a40 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld @@ -35,6 +35,7 @@ PROVIDE ( esp_rom_mbedtls_md5_update_ret = mbedtls_md5_update_ret ); PROVIDE ( esp_rom_mbedtls_md5_finish_ret = mbedtls_md5_finish_ret ); PROVIDE ( esp_rom_printf = ets_printf ); +PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf ); PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set ); diff --git a/components/esp_rom/esp32c3/Kconfig.soc_caps.in b/components/esp_rom/esp32c3/Kconfig.soc_caps.in index 5d8515d9f0..ddab1c823b 100644 --- a/components/esp_rom/esp32c3/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c3/Kconfig.soc_caps.in @@ -38,3 +38,7 @@ config ESP_ROM_GET_CLK_FREQ config ESP_ROM_NEEDS_SWSETUP_WORKAROUND bool default y + +config ESP_ROM_HAS_ETS_PRINTF_BUG + bool + default y diff --git a/components/esp_rom/esp32c3/esp_rom_caps.h b/components/esp_rom/esp32c3/esp_rom_caps.h index d95eae7478..4fc1ef4cad 100644 --- a/components/esp_rom/esp32c3/esp_rom_caps.h +++ b/components/esp_rom/esp32c3/esp_rom_caps.h @@ -15,3 +15,4 @@ #define ESP_ROM_HAS_ERASE_0_REGION_BUG (1) // ROM has esp_flash_erase_region(size=0) bug #define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing +#define ESP_ROM_HAS_ETS_PRINTF_BUG (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register diff --git a/components/esp_rom/esp32h2/Kconfig.soc_caps.in b/components/esp_rom/esp32h2/Kconfig.soc_caps.in index c6beb32f11..6a98982390 100644 --- a/components/esp_rom/esp32h2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32h2/Kconfig.soc_caps.in @@ -34,3 +34,7 @@ config ESP_ROM_HAS_ERASE_0_REGION_BUG config ESP_ROM_GET_CLK_FREQ bool default y + +config ESP_ROM_HAS_ETS_PRINTF_BUG + bool + default y diff --git a/components/esp_rom/esp32h2/esp_rom_caps.h b/components/esp_rom/esp32h2/esp_rom_caps.h index 151fb44e08..d07ecfab7d 100644 --- a/components/esp_rom/esp32h2/esp_rom_caps.h +++ b/components/esp_rom/esp32h2/esp_rom_caps.h @@ -14,3 +14,4 @@ #define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking #define ESP_ROM_HAS_ERASE_0_REGION_BUG (1) // ROM has esp_flash_erase_region(size=0) bug #define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` +#define ESP_ROM_HAS_ETS_PRINTF_BUG (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register diff --git a/components/esp_rom/patches/esp_rom_sys.c b/components/esp_rom/patches/esp_rom_sys.c index 5500f3b712..dde99a1210 100644 --- a/components/esp_rom/patches/esp_rom_sys.c +++ b/components/esp_rom/patches/esp_rom_sys.c @@ -8,7 +8,7 @@ #include #include "esp_attr.h" -#include "sdkconfig.h" +#include "esp_rom_caps.h" IRAM_ATTR void esp_rom_install_channel_putc(int channel, void (*putc)(char c)) { @@ -26,14 +26,16 @@ IRAM_ATTR void esp_rom_install_channel_putc(int channel, void (*putc)(char c)) } } -#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 +#if ESP_ROM_HAS_ETS_PRINTF_BUG IRAM_ATTR void esp_rom_install_uart_printf(void) { extern void ets_install_uart_printf(void); extern bool g_uart_print; + extern bool g_usb_print; // If ROM log is disabled permanently via eFuse or temporarily via RTC storage register, // this ROM symbol will be set to false, and cause ``esp_rom_printf`` can't work on esp-idf side. g_uart_print = true; + g_usb_print = true; ets_install_uart_printf(); } #endif From 7472018f061db6c78e1bd54c4159f30e79c06e84 Mon Sep 17 00:00:00 2001 From: jiangguangming Date: Wed, 26 Oct 2022 14:55:07 +0800 Subject: [PATCH 2/4] esp_rom: fix esp32s3 rom ets_printf bug --- components/bootloader_support/src/bootloader_console.c | 5 ----- components/esp_rom/esp32s3/Kconfig.soc_caps.in | 4 ++++ components/esp_rom/esp32s3/esp_rom_caps.h | 1 + 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c index 85e4aa8027..0609dc8cbb 100644 --- a/components/bootloader_support/src/bootloader_console.c +++ b/components/bootloader_support/src/bootloader_console.c @@ -47,12 +47,7 @@ void bootloader_console_init(void) { const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM; -#if !ESP_ROM_SUPPORT_MULTIPLE_UART - /* esp_rom_install_channel_put is not available unless multiple UARTs are supported */ esp_rom_install_uart_printf(); -#else - esp_rom_install_channel_putc(1, esp_rom_uart_putc); -#endif // Wait for UART FIFO to be empty. esp_rom_uart_tx_wait_idle(0); diff --git a/components/esp_rom/esp32s3/Kconfig.soc_caps.in b/components/esp_rom/esp32s3/Kconfig.soc_caps.in index 9788a68b77..bec937f88f 100644 --- a/components/esp_rom/esp32s3/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s3/Kconfig.soc_caps.in @@ -46,3 +46,7 @@ config ESP_ROM_HAS_HAL_WDT config ESP_ROM_NEEDS_SWSETUP_WORKAROUND bool default y + +config ESP_ROM_HAS_ETS_PRINTF_BUG + bool + default y diff --git a/components/esp_rom/esp32s3/esp_rom_caps.h b/components/esp_rom/esp32s3/esp_rom_caps.h index a5362a68e4..7399ce6633 100644 --- a/components/esp_rom/esp32s3/esp_rom_caps.h +++ b/components/esp_rom/esp32s3/esp_rom_caps.h @@ -17,3 +17,4 @@ #define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency` #define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing +#define ESP_ROM_HAS_ETS_PRINTF_BUG (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register From 8b0d0cbf5df89d4a441ff1f8b373d195b9f68712 Mon Sep 17 00:00:00 2001 From: jiangguangming Date: Wed, 26 Oct 2022 14:57:47 +0800 Subject: [PATCH 3/4] esp_rom: remove ESP_ROM_SUPPORT_MULTIPLE_UART --- components/bootloader_support/src/bootloader_console.c | 4 ++-- components/esp_rom/esp32/Kconfig.soc_caps.in | 4 ---- components/esp_rom/esp32/esp_rom_caps.h | 1 - components/esp_rom/esp32s2/Kconfig.soc_caps.in | 4 ---- components/esp_rom/esp32s2/esp_rom_caps.h | 1 - components/esp_rom/esp32s3/Kconfig.soc_caps.in | 4 ---- components/esp_rom/esp32s3/esp_rom_caps.h | 1 - 7 files changed, 2 insertions(+), 17 deletions(-) diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c index 0609dc8cbb..ffa52379d7 100644 --- a/components/bootloader_support/src/bootloader_console.c +++ b/components/bootloader_support/src/bootloader_console.c @@ -56,10 +56,10 @@ void bootloader_console_init(void) // Some constants to make the following code less upper-case const int uart_tx_gpio = CONFIG_ESP_CONSOLE_UART_TX_GPIO; const int uart_rx_gpio = CONFIG_ESP_CONSOLE_UART_RX_GPIO; + // Switch to the new UART (this just changes UART number used for esp_rom_printf in ROM code). -#if ESP_ROM_SUPPORT_MULTIPLE_UART esp_rom_uart_set_as_console(uart_num); -#endif + // If console is attached to UART1 or if non-default pins are used, // need to reconfigure pins using GPIO matrix if (uart_num != 0 || diff --git a/components/esp_rom/esp32/Kconfig.soc_caps.in b/components/esp_rom/esp32/Kconfig.soc_caps.in index 4707ff484e..ed129cb84e 100644 --- a/components/esp_rom/esp32/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32/Kconfig.soc_caps.in @@ -15,10 +15,6 @@ config ESP_ROM_HAS_JPEG_DECODE bool default y -config ESP_ROM_SUPPORT_MULTIPLE_UART - bool - default y - config ESP_ROM_NEEDS_SWSETUP_WORKAROUND bool default y diff --git a/components/esp_rom/esp32/esp_rom_caps.h b/components/esp_rom/esp32/esp_rom_caps.h index 1d19be8571..959075b29c 100644 --- a/components/esp_rom/esp32/esp_rom_caps.h +++ b/components/esp_rom/esp32/esp_rom_caps.h @@ -9,5 +9,4 @@ #define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian #define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian #define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library -#define ESP_ROM_SUPPORT_MULTIPLE_UART (1) // ROM has multiple UARTs available for logging #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing diff --git a/components/esp_rom/esp32s2/Kconfig.soc_caps.in b/components/esp_rom/esp32s2/Kconfig.soc_caps.in index 2b753e7e0d..870795370c 100644 --- a/components/esp_rom/esp32s2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s2/Kconfig.soc_caps.in @@ -7,10 +7,6 @@ config ESP_ROM_HAS_CRC_LE bool default y -config ESP_ROM_SUPPORT_MULTIPLE_UART - bool - default y - config ESP_ROM_NEEDS_SWSETUP_WORKAROUND bool default y diff --git a/components/esp_rom/esp32s2/esp_rom_caps.h b/components/esp_rom/esp32s2/esp_rom_caps.h index 1078ff8997..1032eef93a 100644 --- a/components/esp_rom/esp32s2/esp_rom_caps.h +++ b/components/esp_rom/esp32s2/esp_rom_caps.h @@ -7,5 +7,4 @@ #pragma once #define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian -#define ESP_ROM_SUPPORT_MULTIPLE_UART (1) // ROM has multiple UARTs available for logging #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing diff --git a/components/esp_rom/esp32s3/Kconfig.soc_caps.in b/components/esp_rom/esp32s3/Kconfig.soc_caps.in index bec937f88f..1d474656fc 100644 --- a/components/esp_rom/esp32s3/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s3/Kconfig.soc_caps.in @@ -15,10 +15,6 @@ config ESP_ROM_HAS_JPEG_DECODE bool default y -config ESP_ROM_SUPPORT_MULTIPLE_UART - bool - default y - config ESP_ROM_UART_CLK_IS_XTAL bool default y diff --git a/components/esp_rom/esp32s3/esp_rom_caps.h b/components/esp_rom/esp32s3/esp_rom_caps.h index 7399ce6633..566f38b0b5 100644 --- a/components/esp_rom/esp32s3/esp_rom_caps.h +++ b/components/esp_rom/esp32s3/esp_rom_caps.h @@ -9,7 +9,6 @@ #define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian #define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian #define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library -#define ESP_ROM_SUPPORT_MULTIPLE_UART (1) // ROM has multiple UARTs available for logging #define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM #define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking #define ESP_ROM_USB_SERIAL_DEVICE_NUM (4) // The serial port ID (UART, USB, ...) of USB_SERIAL_JTAG in the ROM. From eedc5bbdb7ec1b92e65394012d491549dbc7a17f Mon Sep 17 00:00:00 2001 From: jiangguangming Date: Fri, 4 Nov 2022 11:45:39 +0800 Subject: [PATCH 4/4] esp_rom: add rom api esp_rom_uart_set_as_console for riscv chips --- .../esp_rom/esp32c2/ld/esp32c2.rom.api.ld | 1 + .../esp32h2/ld/rev1/esp32h2.rom.api.ld | 1 + .../esp32h2/ld/rev2/esp32h2.rom.api.ld | 1 + components/esp_rom/patches/esp_rom_uart.c | 23 +++++++++++++++++++ 4 files changed, 26 insertions(+) diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld index 565d2a6a40..3e7c7ab600 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld @@ -28,6 +28,7 @@ PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char ); PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle ); PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char ); PROVIDE ( esp_rom_uart_rx_string = UartRxString ); +PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch ); PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); PROVIDE ( esp_rom_mbedtls_md5_starts_ret = mbedtls_md5_starts_ret ); diff --git a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld index 7945722adc..437ebe7daf 100644 --- a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld +++ b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld @@ -30,6 +30,7 @@ PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char ); PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle ); PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char ); PROVIDE ( esp_rom_uart_rx_string = UartRxString ); +PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch ); PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld index 7945722adc..437ebe7daf 100644 --- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld +++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld @@ -30,6 +30,7 @@ PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char ); PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle ); PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char ); PROVIDE ( esp_rom_uart_rx_string = UartRxString ); +PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch ); PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); diff --git a/components/esp_rom/patches/esp_rom_uart.c b/components/esp_rom/patches/esp_rom_uart.c index 7f71a542e2..470b6f5205 100644 --- a/components/esp_rom/patches/esp_rom_uart.c +++ b/components/esp_rom/patches/esp_rom_uart.c @@ -9,6 +9,7 @@ #include "esp_attr.h" #include "sdkconfig.h" #include "hal/uart_ll.h" +#include "hal/efuse_hal.h" #if CONFIG_IDF_TARGET_ESP32 /** @@ -24,3 +25,25 @@ IRAM_ATTR void esp_rom_uart_set_clock_baudrate(uint8_t uart_no, uint32_t clock_h { uart_ll_set_baudrate(UART_LL_GET_HW(uart_no), baud_rate, clock_hz); } + +#if CONFIG_IDF_TARGET_ESP32C3 +/** + * The ESP32-C3 ROM has released two versions, one is the ECO3 version, + * and the other is the version before ECO3 (include ECO0 ECO1 ECO2). + * These two versions of the ROM code do not list uart_tx_switch wrap + * function in the ROM interface, so here use the uart_tx_switch direct + * address instead. + */ +IRAM_ATTR void esp_rom_uart_set_as_console(uint8_t uart_no) +{ + typedef void (*rom_func_t)(uint8_t); + rom_func_t uart_tx_switch = NULL; + + if (efuse_hal_chip_revision() < 3) { + uart_tx_switch = (rom_func_t)0x4004b8ca; + } else { + uart_tx_switch = (rom_func_t)0x4004c166; + } + uart_tx_switch(uart_no); +} +#endif