diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index a2ca2effea..ba75fa1706 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -16,7 +16,7 @@ if(${target} STREQUAL "esp32c6") list(APPEND priv_requires hal) endif() -set(srcs "cpu.c" "esp_memory_utils.c" "port/${IDF_TARGET}/cpu_region_protect.c") +set(srcs "cpu.c" "port/${IDF_TARGET}/esp_cpu_intr.c" "esp_memory_utils.c" "port/${IDF_TARGET}/cpu_region_protect.c") if(NOT BOOTLOADER_BUILD) list(APPEND srcs "esp_clk.c" "clk_ctrl_os.c" diff --git a/components/esp_hw_support/cpu.c b/components/esp_hw_support/cpu.c index 7fefa9d432..a2a01b2395 100644 --- a/components/esp_hw_support/cpu.c +++ b/components/esp_hw_support/cpu.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -144,184 +144,6 @@ void esp_cpu_wait_for_intr(void) #endif // __XTENSA__ } -/* -------------------------------------------------- CPU Registers ---------------------------------------------------- - * - * ------------------------------------------------------------------------------------------------------------------ */ - -/* ------------------------------------------------- CPU Interrupts ---------------------------------------------------- - * - * ------------------------------------------------------------------------------------------------------------------ */ - -// ---------------- Interrupt Descriptors ------------------ - -#if SOC_CPU_HAS_FLEXIBLE_INTC - - -#if SOC_INT_CLIC_SUPPORTED - -static bool is_intr_num_resv(int ext_intr_num) { - /* On targets that uses CLIC as the interrupt controller, the first 16 lines (0..15) are reserved for software - * interrupts, all the other lines starting from 16 and above can be used by external peripheral. - * in the case of this function, the parameter only refers to the external peripheral index, so if - * `ext_intr_num` is 0, it refers to interrupt index 16. - * - * Only interrupt line 6 is reserved at the moment since it is used for disabling interrupts */ - return ext_intr_num == 6; -} - -#else // !SOC_INT_CLIC_SUPPORTED - -static bool is_intr_num_resv(int intr_num) -{ - // Workaround to reserve interrupt number 1 for Wi-Fi, 5,8 for Bluetooth, 6 for "permanently disabled interrupt" - // [TODO: IDF-2465] - uint32_t reserved = BIT(1) | BIT(5) | BIT(6) | BIT(8); - - // int_num 0,3,4,7 are unavailable for PULP cpu -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2// TODO: IDF-5728 replace with a better macro name - reserved |= BIT(0) | BIT(3) | BIT(4) | BIT(7); -#endif - - if (reserved & BIT(intr_num)) { - return true; - } - - extern int _vector_table; - extern int _interrupt_handler; - const intptr_t pc = (intptr_t)(&_vector_table + intr_num); - - /* JAL instructions are relative to the PC there are executed from. */ - const intptr_t destination = pc + riscv_decode_offset_from_jal_instruction(pc); - - return destination != (intptr_t)&_interrupt_handler; -} - -#endif // SOC_INT_CLIC_SUPPORTED - -void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) -{ - intr_desc_ret->priority = 1; //Todo: We should make this -1 - intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA; -#if __riscv - intr_desc_ret->flags = is_intr_num_resv(intr_num) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0; -#else - intr_desc_ret->flags = 0; -#endif -} - -#else // SOC_CPU_HAS_FLEXIBLE_INTC - -typedef struct { - int priority; - esp_cpu_intr_type_t type; - uint32_t flags[SOC_CPU_CORES_NUM]; -} intr_desc_t; - -#if SOC_CPU_CORES_NUM > 1 -// Note: We currently only have dual core targets, so the table initializer is hard coded -const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = { - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //0 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //1 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //2 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //3 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, //4 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //5 -#if CONFIG_FREERTOS_CORETIMER_0 - { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //6 -#else - { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //6 -#endif - { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //7 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //8 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //9 - { 1, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } }, //10 - { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //11 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0} }, //12 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0} }, //13 - { 7, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //14, NMI -#if CONFIG_FREERTOS_CORETIMER_1 - { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //15 -#else - { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //15 -#endif - { 5, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //16 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //17 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //18 - { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //19 - { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //20 - { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //21 - { 3, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, //22 - { 3, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //23 - { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, //24 - { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //25 - { 5, ESP_CPU_INTR_TYPE_LEVEL, { 0, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //26 - { 3, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //27 - { 4, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } }, //28 - { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //29 - { 4, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //30 - { 5, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //31 -}; - -#else // SOC_CPU_CORES_NUM > 1 - -const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = { - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //0 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //1 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //2 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //3 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //4 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //5 -#if CONFIG_FREERTOS_CORETIMER_0 - { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //6 -#else - { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //6 -#endif - { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //7 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //8 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //9 - { 1, ESP_CPU_INTR_TYPE_EDGE, { 0 } }, //10 - { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //11 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //12 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //13 - { 7, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //14, NMI -#if CONFIG_FREERTOS_CORETIMER_1 - { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //15 -#else - { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //15 -#endif - { 5, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //16 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //17 - { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //18 - { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //19 - { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //20 - { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //21 - { 3, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //22 - { 3, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //23 - { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //24 - { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //25 - { 5, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //26 - { 3, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //27 - { 4, ESP_CPU_INTR_TYPE_EDGE, { 0 } }, //28 - { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //29 - { 4, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //30 - { 5, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //31 -}; - -#endif // SOC_CPU_CORES_NUM > 1 - -void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) -{ - assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM); -#if SOC_CPU_CORES_NUM == 1 - core_id = 0; //If this is a single core target, hard code CPU ID to 0 -#endif - intr_desc_ret->priority = intr_desc_table[intr_num].priority; - intr_desc_ret->type = intr_desc_table[intr_num].type; - intr_desc_ret->flags = intr_desc_table[intr_num].flags[core_id]; -} - -#endif // SOC_CPU_HAS_FLEXIBLE_INTC - /* ---------------------------------------------------- Debugging ------------------------------------------------------ * * ------------------------------------------------------------------------------------------------------------------ */ diff --git a/components/esp_hw_support/include/esp_private/esp_riscv_intr.h b/components/esp_hw_support/include/esp_private/esp_riscv_intr.h new file mode 100644 index 0000000000..e53f8a2151 --- /dev/null +++ b/components/esp_hw_support/include/esp_private/esp_riscv_intr.h @@ -0,0 +1,74 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include + +#if CONFIG_IDF_TARGET_ARCH_RISCV + +#if SOC_INT_CLIC_SUPPORTED + +/** + * @brief Checks whether the given interrupt number is reserved either in the given mask or in the + * _mtvt_table, which contains the routines the CPU will jump to when an interrupt or an exception + * occurs, on RISC-V targets. + * + * @param intr_num External interrupt number to check, in range 0~32 + * @param rsvd_mask Reserved interrupt mask, where bit i is 1 if interrupt i is reserved. + * + * @returns ESP_CPU_INTR_DESC_FLAG_RESVD if the interrupt is reserved, 0 else + */ +static inline uint32_t esp_riscv_intr_num_flags(int intr_num, uint32_t rsvd_mask) +{ + if (rsvd_mask & BIT(intr_num)) { + return ESP_CPU_INTR_DESC_FLAG_RESVD; + } + + extern intptr_t _mtvt_table[48]; + extern intptr_t _interrupt_handler; + + /* The first 16 entries of the array are internal interrupt, ignore them */ + const intptr_t destination = _mtvt_table[16 + intr_num]; + + return (destination != (intptr_t)&_interrupt_handler) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0; +} + + + +#else // !SOC_INT_CLIC_SUPPORTED + +#include "esp_cpu.h" +#include "riscv/instruction_decode.h" + +/** + * @brief Checks whether the given interrupt number is reserved either in the given mask or in the + * _vector_table, which contains the routines the CPU will jump to when an interrupt or an exception + * occurs, on RISC-V targets. + * + * @param intr_num Interrupt number to check, in range 0~32 + * @param rsvd_mask Reserved interrupt mask, where bit i is 1 if interrupt i is reserved. + * + * @returns ESP_CPU_INTR_DESC_FLAG_RESVD if the interrupt is reserved, 0 else + */ +static inline uint32_t esp_riscv_intr_num_flags(int intr_num, uint32_t rsvd_mask) +{ + if (rsvd_mask & BIT(intr_num)) { + return ESP_CPU_INTR_DESC_FLAG_RESVD; + } + + extern intptr_t _vector_table[32]; + extern int _interrupt_handler; + const intptr_t pc = (intptr_t) &_vector_table[intr_num]; + + /* JAL instructions are relative to the PC they are executed from. */ + const intptr_t destination = pc + riscv_decode_offset_from_jal_instruction(pc); + + return (destination != (intptr_t)&_interrupt_handler) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0; +} + +#endif // SOC_INT_CLIC_SUPPORTED + +#endif // CONFIG_IDF_TARGET_ARCH_RISCV diff --git a/components/esp_hw_support/intr_alloc.c b/components/esp_hw_support/intr_alloc.c index da61b3a1f2..f316ed971b 100644 --- a/components/esp_hw_support/intr_alloc.c +++ b/components/esp_hw_support/intr_alloc.c @@ -630,7 +630,7 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre esp_intr_disable(ret); } -#ifdef SOC_CPU_HAS_FLEXIBLE_INTC +#if SOC_CPU_HAS_FLEXIBLE_INTC //Extract the level from the interrupt passed flags int level = esp_intr_flags_to_level(flags); esp_cpu_intr_set_priority(intr, level); @@ -642,6 +642,11 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre } #endif +#if SOC_INT_PLIC_SUPPORTED + /* Make sure the interrupt is not delegated to user mode (IDF uses machine mode only) */ + RV_CLEAR_CSR(mideleg, BIT(intr)); +#endif + portEXIT_CRITICAL(&spinlock); //Fill return handle if needed, otherwise free handle. diff --git a/components/esp_hw_support/port/esp32/esp_cpu_intr.c b/components/esp_hw_support/port/esp32/esp_cpu_intr.c new file mode 100644 index 0000000000..5ac8c8f704 --- /dev/null +++ b/components/esp_hw_support/port/esp32/esp_cpu_intr.c @@ -0,0 +1,207 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include +#include "soc/soc_caps.h" +#include "esp_cpu.h" + +/* Xtensa core has 3 interrupts dedicated to timers, we can use either timer0 or timer1 depending on the Kconfig, + * timer2 is always set to SPECIAL in our configuration array */ + +/** + * @brief Type defined for the table below + */ +typedef struct { + int priority; + esp_cpu_intr_type_t type; + uint32_t flags[SOC_CPU_CORES_NUM]; +} intr_desc_t; + + +/** + * @brief Reserve interrupt 5 or 25 for Bluetooth BR/EDR and BLE controller. + */ +#if CONFIG_BTDM_CTRL_HLI + #define STATE_INTERRUPT_5 0 + #define STATE_INTERRUPT_25 ESP_CPU_INTR_DESC_FLAG_RESVD +#else // !CONFIG_BTDM_CTRL_HLI + #define STATE_INTERRUPT_5 ESP_CPU_INTR_DESC_FLAG_RESVD + #define STATE_INTERRUPT_25 0 +#endif // CONFIG_BTDM_CTRL_HLI + + +/** + * @brief Interrupt 1 is used by UART HCI, regardless of High-Level Interrupt (HLI) configuration + */ +#if CONFIG_BTDM_CTRL_HCI_MODE_UART_H4 + #define STATE_INTERRUPT_1 ESP_CPU_INTR_DESC_FLAG_RESVD + /* Interrupt 7 being a software interrupt, it is marked as "special" if not used */ + #define STATE_INTERRUPT_7 ESP_CPU_INTR_DESC_FLAG_SPECIAL +#else // !BTDM_CTRL_HCI_MODE_UART_H4 + #define STATE_INTERRUPT_1 0 + #define STATE_INTERRUPT_7 ESP_CPU_INTR_DESC_FLAG_RESVD +#endif // BTDM_CTRL_HCI_MODE_UART_H4 + + +/** + * @brief Reserve the interrupts on the core where Bluetooth will run. + * The macro CONFIG_BTDM_CTRL_PINNED_TO_CORE is only defined if Bluetooth controller is enabled. + * It is set to the core where it will run. + */ +#ifdef CONFIG_BTDM_CTRL_PINNED_TO_CORE + #if CONFIG_BTDM_CTRL_PINNED_TO_CORE == 0 + /* Interrupt 1 is used by Bluetooth UART HCI, check code above */ + #define CORE_0_INTERRUPT_1 STATE_INTERRUPT_1 + #define CORE_1_INTERRUPT_1 0 + /* Interrupt 5 may be used by Bluetooth BR/EDR and BLE controller */ + #define CORE_0_INTERRUPT_5 STATE_INTERRUPT_5 + #define CORE_1_INTERRUPT_5 0 + /* Interrupt 7 is used by Bluetooth VHCI software interrupt */ + #define CORE_0_INTERRUPT_7 STATE_INTERRUPT_7 + #define CORE_1_INTERRUPT_7 ESP_CPU_INTR_DESC_FLAG_SPECIAL + /* Interrupt 8 is used by Bluetooth BB */ + #define CORE_0_INTERRUPT_8 ESP_CPU_INTR_DESC_FLAG_RESVD + #define CORE_1_INTERRUPT_8 0 + /* Interrupt 25 may be used by Bluetooth BR/EDR and BLE controller */ + #define CORE_0_INTERRUPT_25 STATE_INTERRUPT_25 + #define CORE_1_INTERRUPT_25 0 + #elif CONFIG_BTDM_CTRL_PINNED_TO_CORE == 1 + /* Interrupt 1 is used by Bluetooth UART HCI, check code above */ + #define CORE_0_INTERRUPT_1 0 + #define CORE_1_INTERRUPT_1 STATE_INTERRUPT_1 + /* Interrupt 5 may be used by Bluetooth BR/EDR and BLE controller */ + #define CORE_0_INTERRUPT_5 0 + #define CORE_1_INTERRUPT_5 STATE_INTERRUPT_5 + /* Interrupt 7 is used by Bluetooth VHCI software interrupt */ + #define CORE_0_INTERRUPT_7 ESP_CPU_INTR_DESC_FLAG_SPECIAL + #define CORE_1_INTERRUPT_7 STATE_INTERRUPT_7 + /* Interrupt 8 is used by Bluetooth BB */ + #define CORE_0_INTERRUPT_8 0 + #define CORE_1_INTERRUPT_8 ESP_CPU_INTR_DESC_FLAG_RESVD + /* Interrupt 25 may be used by Bluetooth BR/EDR and BLE controller */ + #define CORE_0_INTERRUPT_25 0 + #define CORE_1_INTERRUPT_25 STATE_INTERRUPT_25 + #endif +#else // Bluetooth not enabled + #define CORE_0_INTERRUPT_1 0 + #define CORE_1_INTERRUPT_1 0 + #define CORE_0_INTERRUPT_5 0 + #define CORE_1_INTERRUPT_5 0 + #define CORE_0_INTERRUPT_7 ESP_CPU_INTR_DESC_FLAG_SPECIAL + #define CORE_1_INTERRUPT_7 ESP_CPU_INTR_DESC_FLAG_SPECIAL + #define CORE_0_INTERRUPT_8 0 + #define CORE_1_INTERRUPT_8 0 + #define CORE_0_INTERRUPT_25 0 + #define CORE_1_INTERRUPT_25 0 +#endif + + +/** + * @brief The system interrupts (memory access, cache, watchdog, ...) can be allocated on either level 4 or level 5 interrupts. + * Check the configuration. + */ +#if CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 + #define CORE_0_INTERRUPT_24 0 + #define CORE_1_INTERRUPT_24 0 + /* If CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 is enabled, Bluetooth macros above take care of interrupt 25 */ + /* Interrupt 26 reserved for T1 Watchdog, cache and memory access errors */ + #define CORE_0_INTERRUPT_26 ESP_CPU_INTR_DESC_FLAG_RESVD + #define CORE_1_INTERRUPT_26 ESP_CPU_INTR_DESC_FLAG_RESVD + #define CORE_0_INTERRUPT_28 0 + #define CORE_1_INTERRUPT_28 0 + /* Interrupt 31 reserved for IPC ISRs */ + #define CORE_0_INTERRUPT_31 ESP_CPU_INTR_DESC_FLAG_RESVD + #define CORE_1_INTERRUPT_31 ESP_CPU_INTR_DESC_FLAG_RESVD +#elif CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 + /* Interrupt reserved for T1 Watchdog, make sure it is enabled */ + #if CONFIG_ESP_INT_WDT + #define CORE_0_INTERRUPT_24 ESP_CPU_INTR_DESC_FLAG_RESVD + #define CORE_1_INTERRUPT_24 ESP_CPU_INTR_DESC_FLAG_RESVD + #else // !CONFIG_ESP_INT_WDT + #define CORE_0_INTERRUPT_24 0 + #define CORE_1_INTERRUPT_24 0 + #endif + /* If CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 is enabled, Bluetooth HLI is not enabled for sure (guaranteed by Kconfig), + * so we can discard the macro previously defined for interrupt 25 */ + #undef CORE_0_INTERRUPT_25 + #undef CORE_1_INTERRUPT_25 + /* Interrupt reserved for memory access and cache errors */ + #define CORE_0_INTERRUPT_25 ESP_CPU_INTR_DESC_FLAG_RESVD + #define CORE_1_INTERRUPT_25 ESP_CPU_INTR_DESC_FLAG_RESVD + #define CORE_0_INTERRUPT_26 0 + #define CORE_1_INTERRUPT_26 0 + /* Interrupt reserved for IPC ISRs */ + #define CORE_0_INTERRUPT_28 ESP_CPU_INTR_DESC_FLAG_RESVD + #define CORE_1_INTERRUPT_28 ESP_CPU_INTR_DESC_FLAG_RESVD + #define CORE_0_INTERRUPT_31 0 + #define CORE_1_INTERRUPT_31 0 +#endif // CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 + + +const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = { + /* Interrupt 0 reserved for WMAC (Wifi) */ + [0] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, + /* Interrupt 1 reserved for BT/BLE Host HCI DMA when CONFIG_BTDM_CTRL_HCI_MODE_UART_H4 is enabled */ + [1] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_1, CORE_1_INTERRUPT_1 } }, + [2] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [3] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + /* Interrupt 4 reserved for WBB */ + [4] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, + /* Interrupt 5 reserved for BT/BLE Controller when Bluetooth HLI is enabled */ + [5] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_5, CORE_1_INTERRUPT_5 } }, +#if CONFIG_FREERTOS_CORETIMER_0 + [6] = { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, +#else + [6] = { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, +#endif + /* Interrupt 7 reserved for Bluetooth VHCI (software interrupt) */ + [7] = { 1, ESP_CPU_INTR_TYPE_NA, { CORE_0_INTERRUPT_7, CORE_1_INTERRUPT_7 } }, + /* Interrupt 8 reserved for BT/BLE BB(RX/TX) */ + [8] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_8, CORE_1_INTERRUPT_8 } }, + [9] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [10] = { 1, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } }, + [11] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, + [12] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [13] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [14] = { 7, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, // NMI +#if CONFIG_FREERTOS_CORETIMER_1 + [15] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, +#else + [15] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, +#endif + [16] = { 5, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, + [17] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [18] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [19] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [20] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [21] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [22] = { 3, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } }, + [23] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + /* Interrupt 24 reserved for T1 WDT when CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 is enabled */ + [24] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_24, CORE_1_INTERRUPT_24 } }, + /* Interrupt 25 reserved for Memory access and cache errors when CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 is enabled + * Reserved for BT/BLE Controller when CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 is enabled */ + [25] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_25, CORE_1_INTERRUPT_25 } }, + /* Interrupt 26 reserved for T1 WDT, Memory access and cache errors when CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 is enabled */ + [26] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_26, CORE_1_INTERRUPT_26 } }, + [27] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + /* Interrupt 28 reserved for IPC when CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 is enabled */ + [28] = { 4, ESP_CPU_INTR_TYPE_EDGE, { CORE_0_INTERRUPT_28, CORE_1_INTERRUPT_28 } }, + [29] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, + [30] = { 4, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } }, + /* Interrupt 31 reserved for IPC when CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 is enabled */ + [31] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_31, CORE_1_INTERRUPT_31 } }, +}; + + +void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) +{ + assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM && intr_desc_ret != NULL); + intr_desc_ret->priority = intr_desc_table[intr_num].priority; + intr_desc_ret->type = intr_desc_table[intr_num].type; + intr_desc_ret->flags = intr_desc_table[intr_num].flags[core_id]; +} diff --git a/components/esp_hw_support/port/esp32c2/esp_cpu_intr.c b/components/esp_hw_support/port/esp32c2/esp_cpu_intr.c new file mode 100644 index 0000000000..6a901a2fdb --- /dev/null +++ b/components/esp_hw_support/port/esp32c2/esp_cpu_intr.c @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_cpu.h" +#include "esp_riscv_intr.h" + +void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) +{ + /* On the ESP32-C2, interrupt: + * - 1 is for Wi-Fi + * - 6 for "permanently disabled interrupt", named INT_MUX_DISABLED_INTNO in the interrupt allocator + */ + // [TODO: IDF-2465] + const uint32_t rsvd_mask = BIT(1) | BIT(6); + + intr_desc_ret->priority = 1; + intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA; + intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask); +} diff --git a/components/esp_hw_support/port/esp32c3/esp_cpu_intr.c b/components/esp_hw_support/port/esp32c3/esp_cpu_intr.c new file mode 100644 index 0000000000..1c95ca8e70 --- /dev/null +++ b/components/esp_hw_support/port/esp32c3/esp_cpu_intr.c @@ -0,0 +1,23 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_cpu.h" +#include "esp_riscv_intr.h" + +void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) +{ + /* On the ESP32-C3, interrupt: + * - 1 is for Wi-Fi + * - 5 and 8 for Bluetooth + * - 6 for "permanently disabled interrupt", named INT_MUX_DISABLED_INTNO in the interrupt allocator + */ + // [TODO: IDF-2465] + const uint32_t rsvd_mask = BIT(1) | BIT(5) | BIT(6) | BIT(8); + + intr_desc_ret->priority = 1; + intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA; + intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask); +} diff --git a/components/esp_hw_support/port/esp32c6/esp_cpu_intr.c b/components/esp_hw_support/port/esp32c6/esp_cpu_intr.c new file mode 100644 index 0000000000..38fdf890d8 --- /dev/null +++ b/components/esp_hw_support/port/esp32c6/esp_cpu_intr.c @@ -0,0 +1,24 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_cpu.h" +#include "esp_riscv_intr.h" + +void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) +{ + /* On the ESP32-C6, interrupt: + * - 1 is for Wi-Fi + * - 6 for "permanently disabled interrupt" + * + * Interrupts 3, 4 and 7 are unavailable for PULP CPU as they are bound to Core-Local Interrupts (CLINT) + */ + // [TODO: IDF-2465] + const uint32_t rsvd_mask = BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(7); + + intr_desc_ret->priority = 1; + intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA; + intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask); +} diff --git a/components/esp_hw_support/port/esp32h2/esp_cpu_intr.c b/components/esp_hw_support/port/esp32h2/esp_cpu_intr.c new file mode 100644 index 0000000000..9ce7dfa69c --- /dev/null +++ b/components/esp_hw_support/port/esp32h2/esp_cpu_intr.c @@ -0,0 +1,24 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_cpu.h" +#include "esp_riscv_intr.h" + +void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) +{ + /* On the ESP32-H2, interrupt: + * - 1 is for Wi-Fi + * - 6 for "permanently disabled interrupt" + * + * Interrupts 3, 4 and 7 are unavailable for PULP CPU as they are bound to Core-Local Interrupts (CLINT) + */ + // [TODO: IDF-2465] + const uint32_t rsvd_mask = BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(7); + + intr_desc_ret->priority = 1; + intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA; + intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask); +} diff --git a/components/esp_hw_support/port/esp32p4/esp_cpu_intr.c b/components/esp_hw_support/port/esp32p4/esp_cpu_intr.c new file mode 100644 index 0000000000..da246c75de --- /dev/null +++ b/components/esp_hw_support/port/esp32p4/esp_cpu_intr.c @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_cpu.h" +#include "esp_riscv_intr.h" + +void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) +{ + /* On targets that uses CLIC as the interrupt controller, the first 16 lines (0..15) are reserved for software + * interrupts, all the other lines starting from 16 and above can be used by external peripheral. + * + * Only interrupt line 6 is reserved at the moment since it is used for disabling interrupts in the + * interrupt allocator (INT_MUX_DISABLED_INTNO) */ + const uint32_t rsvd_mask = BIT(6); + + intr_desc_ret->priority = 1; + intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA; + intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask); +} diff --git a/components/esp_hw_support/port/esp32s2/esp_cpu_intr.c b/components/esp_hw_support/port/esp32s2/esp_cpu_intr.c new file mode 100644 index 0000000000..34979086e6 --- /dev/null +++ b/components/esp_hw_support/port/esp32s2/esp_cpu_intr.c @@ -0,0 +1,80 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include +#include "soc/soc_caps.h" +#include "esp_cpu.h" + +/* Xtensa core has 3 interrupts dedicated to timers, we can use either timer0 or timer1 depending on the Kconfig, + * timer2 is always set to SPECIAL in our configuration array */ + +/** + * @brief Type defined for the table below + */ +typedef struct { + int priority; + esp_cpu_intr_type_t type; + uint32_t flags; +} intr_desc_t; + + +const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = { + /* Interrupt 0 reserved for WMAC (Wifi) */ + [0] = { 1, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD }, + [1] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [2] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [3] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + /* Interrupt 4 reserved for WBB */ + [4] = { 1, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD }, + [5] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 }, +#if CONFIG_FREERTOS_CORETIMER_0 + [6] = { 1, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_RESVD }, +#else + [6] = { 1, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL }, +#endif + [7] = { 1, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL }, + [8] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [9] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [10] = { 1, ESP_CPU_INTR_TYPE_EDGE, 0 }, + [11] = { 3, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL }, + [12] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [13] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + /* Interrupt 14 reserved for NMI (Non-Maskable Interrupts) */ + [14] = { 7, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD }, +#if CONFIG_FREERTOS_CORETIMER_1 + [15] = { 3, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_RESVD }, +#else + [15] = { 3, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL }, +#endif + [16] = { 5, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL }, + [17] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [18] = { 1, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [19] = { 2, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [20] = { 2, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [21] = { 2, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [22] = { 3, ESP_CPU_INTR_TYPE_EDGE, 0 }, + [23] = { 3, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + /* Interrupt 24 reserved for T1 WDT */ + [24] = { 4, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD }, + /* Interrupt 25 reserved for memory access errors */ + [25] = { 4, ESP_CPU_INTR_TYPE_LEVEL, ESP_CPU_INTR_DESC_FLAG_RESVD }, + [26] = { 5, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [27] = { 3, ESP_CPU_INTR_TYPE_LEVEL, 0 }, + [28] = { 4, ESP_CPU_INTR_TYPE_EDGE, 0 }, + [29] = { 3, ESP_CPU_INTR_TYPE_NA, ESP_CPU_INTR_DESC_FLAG_SPECIAL }, + [30] = { 4, ESP_CPU_INTR_TYPE_EDGE, 0 }, + [31] = { 5, ESP_CPU_INTR_TYPE_LEVEL, 0 }, +}; + + +void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) +{ + assert(core_id == 0 && intr_num < SOC_CPU_INTR_NUM && intr_desc_ret != NULL); + intr_desc_ret->priority = intr_desc_table[intr_num].priority; + intr_desc_ret->type = intr_desc_table[intr_num].type; + intr_desc_ret->flags = intr_desc_table[intr_num].flags; +} diff --git a/components/esp_hw_support/port/esp32s3/esp_cpu_intr.c b/components/esp_hw_support/port/esp32s3/esp_cpu_intr.c new file mode 100644 index 0000000000..acd0cbe83d --- /dev/null +++ b/components/esp_hw_support/port/esp32s3/esp_cpu_intr.c @@ -0,0 +1,102 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include "esp_cpu.h" + +/* The ESP32-S3 uses the SysTimer for the FreeRTOS system tick, there is no need to use Xtensa core timer interrupts, + * marked as ESP_CPU_INTR_DESC_FLAG_SPECIAL in the table below */ + +/** + * @brief Type defined for the table below + */ +typedef struct { + int priority; + esp_cpu_intr_type_t type; + uint32_t flags[SOC_CPU_CORES_NUM]; +} intr_desc_t; + + +/** + * @brief Reserve the interrupts on the core where Bluetooth will run. + * The macro CONFIG_BT_CTRL_PINNED_TO_CORE is only defined if Bluetooth controller is enabled. + * It is set to the core where it will run. + */ +#ifdef CONFIG_BT_CTRL_PINNED_TO_CORE + #if CONFIG_BT_CTRL_PINNED_TO_CORE == 0 + #define CORE_0_INTERRUPT_5 ESP_CPU_INTR_DESC_FLAG_RESVD + #define CORE_1_INTERRUPT_5 0 + #define CORE_0_INTERRUPT_8 ESP_CPU_INTR_DESC_FLAG_RESVD + #define CORE_1_INTERRUPT_8 0 + #elif CONFIG_BT_CTRL_PINNED_TO_CORE == 1 + #define CORE_0_INTERRUPT_5 0 + #define CORE_1_INTERRUPT_5 ESP_CPU_INTR_DESC_FLAG_RESVD + #define CORE_0_INTERRUPT_8 0 + #define CORE_1_INTERRUPT_8 ESP_CPU_INTR_DESC_FLAG_RESVD + #endif +#else // Bluetooth not enabled + #define CORE_0_INTERRUPT_5 0 + #define CORE_1_INTERRUPT_5 0 + #define CORE_0_INTERRUPT_8 0 + #define CORE_1_INTERRUPT_8 0 +#endif + + +const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = { + /* Interrupt 0 reserved for WMAC (Wifi) */ +#if CONFIG_ESP_WIFI_TASK_PINNED_TO_CORE_0 + [0] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, +#else + [0] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, ESP_CPU_INTR_DESC_FLAG_RESVD } }, +#endif + [1] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [2] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [3] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + /* Interrupt 4 reserved for WBB */ + [4] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, + /* Interrupt 5 reserved for BT/BLE Controller */ + [5] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_5, CORE_1_INTERRUPT_5 } }, + [6] = { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, + [7] = { 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, + /* Interrupt 8 reserved for BT/BLE Controller */ + [8] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { CORE_0_INTERRUPT_8, CORE_1_INTERRUPT_8 } }, + [9] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [10] = { 1, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } }, + [11] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, + [12] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [13] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + /* Interrupt 14 reserved for NMI (Non-Maskable Interrupts) */ + [14] = { 7, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, // NMI + [15] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, + [16] = { 5, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, + [17] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [18] = { 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [19] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [20] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [21] = { 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [22] = { 3, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } }, + [23] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + /* Interrupt 24 reserved for T1 WDT */ + [24] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, + /* Interrupt 25 reserved for memory access and cache errors */ + [25] = { 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, + [26] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + [27] = { 3, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, + /* Interrupt 28 reserved for IPC */ + [28] = { 4, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, + [29] = { 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, + [30] = { 4, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } }, + [31] = { 5, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, +}; + + +void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) +{ + assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM && intr_desc_ret != NULL); + intr_desc_ret->priority = intr_desc_table[intr_num].priority; + intr_desc_ret->type = intr_desc_table[intr_num].type; + intr_desc_ret->flags = intr_desc_table[intr_num].flags[core_id]; +} diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h index 05e2a3fb7e..941513d6e2 100644 --- a/components/soc/esp32/include/soc/soc.h +++ b/components/soc/esp32/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -220,51 +220,12 @@ // Start (highest address) of ROM boot stack, only relevant during early boot #define SOC_ROM_STACK_START 0x3ffe3f20 -#if CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 -//interrupt cpu using table, Please see the core-isa.h -/************************************************************************************************************* - * Intr num Level Type PRO CPU usage APP CPU uasge - * 0 1 extern level WMAC Reserved - * 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA - * 2 1 extern level - * 3 1 extern level - * 4 1 extern level WBB - * 5 1 extern level - * 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1) - * 7 1 software BT/BLE VHCI BT/BLE VHCI - * 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX) - * 9 1 extern level - * 10 1 extern edge - * 11 3 profiling - * 12 1 extern level - * 13 1 extern level - * 14 7 nmi Reserved Reserved - * 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3) - * 16 5 timer Reserved Reserved - * 17 1 extern level - * 18 1 extern level - * 19 2 extern level - * 20 2 extern level - * 21 2 extern level - * 22 3 extern edge - * 23 3 extern level - * 24 4 extern level - * 25 4 extern level BT/BLE Controller BT/BLE Controller - * 26 5 extern level TG1_WDT & CACHEERR - * 27 3 extern level Reserved Reserved - * 28 4 extern edge - * 29 3 software BT/BLE hli BT/BLE hli - * 30 4 extern edge Reserved Reserved - * 31 5 extern level IPC_ISR IPC_ISR - ************************************************************************************************************* - */ - -//CPU0 Interrupt number reserved, not touch this. #define ETS_WMAC_INUM 0 #define ETS_BT_HOST_INUM 1 #define ETS_WBB_INUM 4 -#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/ -#define ETS_FRC1_INUM 22 + +#if CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 + #define ETS_T1_WDT_CACHEERR_INUM 26 #define ETS_T1_WDT_INUM ETS_T1_WDT_CACHEERR_INUM #define ETS_MEMACCESS_ERR_INUM ETS_T1_WDT_CACHEERR_INUM @@ -274,50 +235,6 @@ #elif CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 -//interrupt cpu using table, Please see the core-isa.h -/************************************************************************************************************* - * Intr num Level Type PRO CPU usage APP CPU uasge - * 0 1 extern level WMAC Reserved - * 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA - * 2 1 extern level - * 3 1 extern level - * 4 1 extern level WBB - * 5 1 extern level BT/BLE Controller BT/BLE Controller - * 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1) - * 7 1 software BT/BLE VHCI BT/BLE VHCI - * 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX) - * 9 1 extern level - * 10 1 extern edge - * 11 3 profiling - * 12 1 extern level - * 13 1 extern level - * 14 7 nmi Reserved Reserved - * 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3) - * 16 5 timer - * 17 1 extern level - * 18 1 extern level - * 19 2 extern level - * 20 2 extern level - * 21 2 extern level - * 22 3 extern edge - * 23 3 extern level - * 24 4 extern level TG1_WDT - * 25 4 extern level CACHEERR - * 26 5 extern level - * 27 3 extern level Reserved Reserved - * 28 4 extern edge IPC_ISR IPC_ISR - * 29 3 software Reserved Reserved - * 30 4 extern edge Reserved Reserved - * 31 5 extern level - ************************************************************************************************************* - */ - -//CPU0 Interrupt number reserved, not touch this. -#define ETS_WMAC_INUM 0 -#define ETS_BT_HOST_INUM 1 -#define ETS_WBB_INUM 4 -#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/ -#define ETS_FRC1_INUM 22 #define ETS_T1_WDT_INUM 24 #define ETS_MEMACCESS_ERR_INUM 25 /* backwards compatibility only, use ETS_MEMACCESS_ERR_INUM instead*/ diff --git a/components/soc/esp32c6/esp_cpu_intr.c b/components/soc/esp32c6/esp_cpu_intr.c new file mode 100644 index 0000000000..ded3030aeb --- /dev/null +++ b/components/soc/esp32c6/esp_cpu_intr.c @@ -0,0 +1,22 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_cpu.h" +#include "esp_riscv_intr.h" + +void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret) +{ + /* On targets that uses CLIC as the interrupt controller, the first 16 lines (0..15) are reserved for software + * interrupts, all the other lines starting from 16 and above can be used by external peripheral. + * + * Reserve interrupt line 1 for the Wifi controller. + * Reserve interrupt line 6 since it is used for disabling interrupts in the interrupt allocator (INT_MUX_DISABLED_INTNO) + */ + const uint32_t rsvd_mask = BIT(1) | BIT(6); + intr_desc_ret->priority = 1; + intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA; + intr_desc_ret->flags = esp_riscv_intr_num_flags(intr_num, rsvd_mask); +} diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h index 6d59f41632..2439e12560 100644 --- a/components/soc/esp32s2/include/soc/soc.h +++ b/components/soc/esp32s2/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -208,50 +208,8 @@ // Start (highest address) of ROM boot stack, only relevant during early boot #define SOC_ROM_STACK_START 0x3fffe70c -//interrupt cpu using table, Please see the core-isa.h -/************************************************************************************************************* - * Intr num Level Type PRO CPU usage - * 0 1 extern level WMAC - * 1 1 extern level BT/BLE Host HCI DMA - * 2 1 extern level - * 3 1 extern level - * 4 1 extern level WBB - * 5 1 extern level BT/BLE Controller - * 6 1 timer FreeRTOS Tick(L1) - * 7 1 software BT/BLE VHCI - * 8 1 extern level BT/BLE BB(RX/TX) - * 9 1 extern level - * 10 1 extern edge - * 11 3 profiling - * 12 1 extern level - * 13 1 extern level - * 14 7 nmi Reserved - * 15 3 timer FreeRTOS Tick(L3) - * 16 5 timer - * 17 1 extern level - * 18 1 extern level - * 19 2 extern level - * 20 2 extern level - * 21 2 extern level - * 22 3 extern edge - * 23 3 extern level - * 24 4 extern level TG1_WDT - * 25 4 extern level CACHEERR - * 26 5 extern level - * 27 3 extern level Reserved - * 28 4 extern edge Reserved - * 29 3 software Reserved - * 30 4 extern edge Reserved - * 31 5 extern level - ************************************************************************************************************* - */ - -//CPU0 Interrupt number reserved, not touch this. #define ETS_WMAC_INUM 0 -#define ETS_BT_HOST_INUM 1 #define ETS_WBB_INUM 4 -#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/ -#define ETS_FRC1_INUM 22 #define ETS_T1_WDT_INUM 24 #define ETS_MEMACCESS_ERR_INUM 25 diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index d465da64d4..d91136a812 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -226,50 +226,8 @@ #define SOC_ROM_STACK_START 0x3fceb710 #define SOC_ROM_STACK_SIZE 0x2000 -//interrupt cpu using table, Please see the core-isa.h -/************************************************************************************************************* - * Intr num Level Type PRO CPU usage APP CPU uasge - * 0 1 extern level WMAC Reserved - * 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA - * 2 1 extern level - * 3 1 extern level - * 4 1 extern level WBB - * 5 1 extern level BT/BLE Controller BT/BLE Controller - * 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1) - * 7 1 software BT/BLE VHCI BT/BLE VHCI - * 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX) - * 9 1 extern level - * 10 1 extern edge - * 11 3 profiling - * 12 1 extern level - * 13 1 extern level - * 14 7 nmi Reserved Reserved - * 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3) - * 16 5 timer - * 17 1 extern level - * 18 1 extern level - * 19 2 extern level - * 20 2 extern level - * 21 2 extern level - * 22 3 extern edge - * 23 3 extern level - * 24 4 extern level TG1_WDT - * 25 4 extern level CACHEERR - * 26 5 extern level - * 27 3 extern level Reserved Reserved - * 28 4 extern edge IPC_ISR IPC_ISR - * 29 3 software Reserved Reserved - * 30 4 extern edge Reserved Reserved - * 31 5 extern level - ************************************************************************************************************* - */ - -//CPU0 Interrupt number reserved, not touch this. #define ETS_WMAC_INUM 0 -#define ETS_BT_HOST_INUM 1 #define ETS_WBB_INUM 4 -#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/ -#define ETS_FRC1_INUM 22 #define ETS_T1_WDT_INUM 24 #define ETS_MEMACCESS_ERR_INUM 25 #define ETS_CACHEERR_INUM ETS_MEMACCESS_ERR_INUM diff --git a/tools/test_apps/system/esp_intr_dump/expected_output/esp32.txt b/tools/test_apps/system/esp_intr_dump/expected_output/esp32.txt index 1533cf38ad..ca6df6e5ec 100644 --- a/tools/test_apps/system/esp_intr_dump/expected_output/esp32.txt +++ b/tools/test_apps/system/esp_intr_dump/expected_output/esp32.txt @@ -1,48 +1,14 @@ CPU 0 interrupt status: Int Level Type Status 0 1 Level Reserved - 1 1 Level Reserved - 2 1 Level Used: RTC_CORE - 3 1 Level Used: TG0_LACT_LEVEL + 1 1 Level Used: RTC_CORE + 2 1 Level Used: TG0_LACT_LEVEL + 3 1 Level Used: FROM_CPU0 4 1 Level Reserved - 5 1 Level Reserved + 5 1 Level Used: TG0_WDT_LEVEL 6 1 Level Reserved 7 1 Level CPU-internal - 8 1 Level Reserved - 9 1 Level Used: FROM_CPU0 - 10 1 Edge Free (not general-use) - 11 3 Level CPU-internal - 12 1 Level Used: TG0_WDT_LEVEL - 13 1 Level Used: UART0 - 14 7 Level Reserved - 15 3 Level CPU-internal - 16 5 Level CPU-internal - 17 1 Level Free - 18 1 Level Free - 19 2 Level Free - 20 2 Level Free - 21 2 Level Free - 22 3 Edge Reserved - 23 3 Level Free - 24 4 Level Reserved - 25 4 Level Reserved - 26 5 Level Free (not general-use) - 27 3 Level Reserved - 28 4 Edge Free (not general-use) - 29 3 Level CPU-internal - 30 4 Edge Reserved - 31 5 Level Reserved -CPU 1 interrupt status: - Int Level Type Status - 0 1 Level Reserved - 1 1 Level Reserved - 2 1 Level Used: FROM_CPU1 - 3 1 Level Free - 4 1 Level Free - 5 1 Level Reserved - 6 1 Level Reserved - 7 1 Level CPU-internal - 8 1 Level Reserved + 8 1 Level Used: UART0 9 1 Level Free 10 1 Edge Free (not general-use) 11 3 Level CPU-internal @@ -58,13 +24,47 @@ CPU 1 interrupt status: 21 2 Level Free 22 3 Edge Free (not general-use) 23 3 Level Free - 24 4 Level Free (not general-use) + 24 4 Level Reserved 25 4 Level Reserved - 26 5 Level Reserved - 27 3 Level Reserved - 28 4 Edge Free (not general-use) + 26 5 Level Free (not general-use) + 27 3 Level Free + 28 4 Edge Reserved 29 3 Level CPU-internal - 30 4 Edge Reserved - 31 5 Level Reserved -Interrupts available for general use: 17 + 30 4 Edge Free (not general-use) + 31 5 Level Free (not general-use) +CPU 1 interrupt status: + Int Level Type Status + 0 1 Level Reserved + 1 1 Level Used: FROM_CPU1 + 2 1 Level Free + 3 1 Level Free + 4 1 Level Free + 5 1 Level Free + 6 1 Level Reserved + 7 1 Level CPU-internal + 8 1 Level Free + 9 1 Level Free + 10 1 Edge Free (not general-use) + 11 3 Level CPU-internal + 12 1 Level Free + 13 1 Level Free + 14 7 Level Reserved + 15 3 Level CPU-internal + 16 5 Level CPU-internal + 17 1 Level Free + 18 1 Level Free + 19 2 Level Free + 20 2 Level Free + 21 2 Level Free + 22 3 Edge Free (not general-use) + 23 3 Level Free + 24 4 Level Reserved + 25 4 Level Reserved + 26 5 Level Free (not general-use) + 27 3 Level Free + 28 4 Edge Reserved + 29 3 Level CPU-internal + 30 4 Edge Free (not general-use) + 31 5 Level Free (not general-use) +Interrupts available for general use: 25 Shared interrupts: 0 diff --git a/tools/test_apps/system/esp_intr_dump/expected_output/esp32c2.txt b/tools/test_apps/system/esp_intr_dump/expected_output/esp32c2.txt index 27b2ce6586..06d6c783f9 100644 --- a/tools/test_apps/system/esp_intr_dump/expected_output/esp32c2.txt +++ b/tools/test_apps/system/esp_intr_dump/expected_output/esp32c2.txt @@ -5,11 +5,11 @@ CPU 0 interrupt status: 2 1 Level Used: RTC_CORE 3 1 Level Used: SYSTIMER_TARGET2_EDGE 4 1 Level Used: ETS_FROM_CPU_INTR0 - 5 * * Reserved + 5 1 Level Used: SYSTIMER_TARGET0_EDGE 6 * * Reserved - 7 1 Level Used: SYSTIMER_TARGET0_EDGE - 8 * * Reserved - 9 1 Level Used: UART + 7 1 Level Used: UART + 8 * * Free + 9 * * Free 10 * * Free 11 * * Free 12 * * Free @@ -32,5 +32,5 @@ CPU 0 interrupt status: 29 * * Free 30 * * Free 31 * * Free -Interrupts available for general use: 19 +Interrupts available for general use: 21 Shared interrupts: 0 diff --git a/tools/test_apps/system/esp_intr_dump/expected_output/esp32c3.txt b/tools/test_apps/system/esp_intr_dump/expected_output/esp32c3.txt index e555060c88..a193835854 100644 --- a/tools/test_apps/system/esp_intr_dump/expected_output/esp32c3.txt +++ b/tools/test_apps/system/esp_intr_dump/expected_output/esp32c3.txt @@ -33,4 +33,4 @@ CPU 0 interrupt status: 30 * * Free 31 * * Free Interrupts available for general use: 17 -Shared interrupts: 0 \ No newline at end of file +Shared interrupts: 0 diff --git a/tools/test_apps/system/esp_intr_dump/expected_output/esp32c6.txt b/tools/test_apps/system/esp_intr_dump/expected_output/esp32c6.txt index efccf74798..b1e90c3472 100644 --- a/tools/test_apps/system/esp_intr_dump/expected_output/esp32c6.txt +++ b/tools/test_apps/system/esp_intr_dump/expected_output/esp32c6.txt @@ -5,15 +5,15 @@ CPU 0 interrupt status: 2 1 Level Used: LP_RTC_TIMER 3 * * Reserved 4 * * Reserved - 5 * * Reserved + 5 1 Level Used: SYSTIMER_TARGET2 6 * * Reserved 7 * * Reserved - 8 * * Reserved - 9 1 Level Used: SYSTIMER_TARGET2 - 10 1 Level Used: CPU_FROM_CPU_0 - 11 1 Level Used: SYSTIMER_TARGET0 - 12 1 Level Used: TG0_WDT - 13 1 Level Used: UART0 + 8 1 Level Used: CPU_FROM_CPU_0 + 9 1 Level Used: SYSTIMER_TARGET0 + 10 1 Level Used: TG0_WDT + 11 1 Level Used: UART0 + 12 * * Free + 13 * * Free 14 * * Free 15 * * Free 16 * * Free @@ -32,5 +32,5 @@ CPU 0 interrupt status: 29 * * Free 30 * * Free 31 * * Free -Interrupts available for general use: 15 +Interrupts available for general use: 17 Shared interrupts: 0 diff --git a/tools/test_apps/system/esp_intr_dump/expected_output/esp32h2.txt b/tools/test_apps/system/esp_intr_dump/expected_output/esp32h2.txt index 3b0b62f558..6d5b16217a 100644 --- a/tools/test_apps/system/esp_intr_dump/expected_output/esp32h2.txt +++ b/tools/test_apps/system/esp_intr_dump/expected_output/esp32h2.txt @@ -5,15 +5,15 @@ CPU 0 interrupt status: 2 1 Level Used: LP_RTC_TIMER 3 * * Reserved 4 * * Reserved - 5 * * Reserved + 5 1 Level Used: SYSTIMER_TARGET2 6 * * Reserved 7 * * Reserved - 8 * * Reserved - 9 1 Level Used: SYSTIMER_TARGET2 - 10 1 Level Used: CPUFROM_CPU_0 - 11 1 Level Used: SYSTIMER_TARGET0 - 12 1 Level Used: TG0_WDT - 13 1 Level Used: UART0 + 8 1 Level Used: CPUFROM_CPU_0 + 9 1 Level Used: SYSTIMER_TARGET0 + 10 1 Level Used: TG0_WDT + 11 1 Level Used: UART0 + 12 * * Free + 13 * * Free 14 * * Free 15 * * Free 16 * * Free @@ -32,5 +32,5 @@ CPU 0 interrupt status: 29 * * Free 30 * * Free 31 * * Free -Interrupts available for general use: 15 +Interrupts available for general use: 17 Shared interrupts: 0 diff --git a/tools/test_apps/system/esp_intr_dump/expected_output/esp32s2.txt b/tools/test_apps/system/esp_intr_dump/expected_output/esp32s2.txt index 50b75a349c..0f833b44cd 100644 --- a/tools/test_apps/system/esp_intr_dump/expected_output/esp32s2.txt +++ b/tools/test_apps/system/esp_intr_dump/expected_output/esp32s2.txt @@ -1,18 +1,18 @@ CPU 0 interrupt status: Int Level Type Status 0 1 Level Reserved - 1 1 Level Reserved - 2 1 Level Used: RTC_CORE - 3 1 Level Used: FROM_CPU_INTR0 + 1 1 Level Used: RTC_CORE + 2 1 Level Used: FROM_CPU_INTR0 + 3 1 Level Used: TG0_WDT_LEVEL 4 1 Level Reserved - 5 1 Level Reserved + 5 1 Level Used: UART0 6 1 Level Reserved 7 1 Level CPU-internal - 8 1 Level Reserved - 9 1 Level Used: TG0_WDT_LEVEL + 8 1 Level Free + 9 1 Level Free 10 1 Edge Used: SYSTIMER_TARGET2 11 3 Level CPU-internal - 12 1 Level Used: UART0 + 12 1 Level Free 13 1 Level Free 14 7 Level Reserved 15 3 Level CPU-internal @@ -22,15 +22,15 @@ CPU 0 interrupt status: 19 2 Level Free 20 2 Level Free 21 2 Level Free - 22 3 Edge Reserved + 22 3 Edge Free (not general-use) 23 3 Level Free 24 4 Level Reserved 25 4 Level Reserved 26 5 Level Free (not general-use) - 27 3 Level Reserved + 27 3 Level Free 28 4 Edge Free (not general-use) 29 3 Level CPU-internal - 30 4 Edge Reserved - 31 5 Level Reserved -Interrupts available for general use: 7 + 30 4 Edge Free (not general-use) + 31 5 Level Free (not general-use) +Interrupts available for general use: 11 Shared interrupts: 0 diff --git a/tools/test_apps/system/esp_intr_dump/expected_output/esp32s3.txt b/tools/test_apps/system/esp_intr_dump/expected_output/esp32s3.txt index fb3ee32402..da17c66944 100644 --- a/tools/test_apps/system/esp_intr_dump/expected_output/esp32s3.txt +++ b/tools/test_apps/system/esp_intr_dump/expected_output/esp32s3.txt @@ -1,48 +1,14 @@ CPU 0 interrupt status: Int Level Type Status - 0 1 Level Reserved - 1 1 Level Reserved - 2 1 Level Used: RTC_CORE - 3 1 Level Used: SYSTIMER_TARGET2 + 0 1 Level Used: RTC_CORE + 1 1 Level Used: SYSTIMER_TARGET2 + 2 1 Level Used: FROM_CPU_INTR0 + 3 1 Level Used: SYSTIMER_TARGET0 4 1 Level Reserved - 5 1 Level Reserved + 5 1 Level Used: TG0_WDT_LEVEL 6 1 Level CPU-internal 7 1 Level CPU-internal - 8 1 Level Reserved - 9 1 Level Used: FROM_CPU_INTR0 - 10 1 Edge Free (not general-use) - 11 3 Level CPU-internal - 12 1 Level Used: SYSTIMER_TARGET0 - 13 1 Level Used: TG0_WDT_LEVEL - 14 7 Level Reserved - 15 3 Level CPU-internal - 16 5 Level CPU-internal - 17 1 Level Used: UART0 - 18 1 Level Free - 19 2 Level Free - 20 2 Level Free - 21 2 Level Free - 22 3 Edge Reserved - 23 3 Level Free - 24 4 Level Reserved - 25 4 Level Reserved - 26 5 Level Free (not general-use) - 27 3 Level Reserved - 28 4 Edge Free (not general-use) - 29 3 Level CPU-internal - 30 4 Edge Reserved - 31 5 Level Reserved -CPU 1 interrupt status: - Int Level Type Status - 0 1 Level Reserved - 1 1 Level Reserved - 2 1 Level Used: FROM_CPU_INTR1 - 3 1 Level Used: SYSTIMER_TARGET1 - 4 1 Level Free - 5 1 Level Reserved - 6 1 Level CPU-internal - 7 1 Level CPU-internal - 8 1 Level Reserved + 8 1 Level Used: UART0 9 1 Level Free 10 1 Edge Free (not general-use) 11 3 Level CPU-internal @@ -58,13 +24,47 @@ CPU 1 interrupt status: 21 2 Level Free 22 3 Edge Free (not general-use) 23 3 Level Free - 24 4 Level Free (not general-use) + 24 4 Level Reserved 25 4 Level Reserved - 26 5 Level Reserved - 27 3 Level Reserved - 28 4 Edge Free (not general-use) + 26 5 Level Free (not general-use) + 27 3 Level Free + 28 4 Edge Reserved 29 3 Level CPU-internal - 30 4 Edge Reserved - 31 5 Level Reserved -Interrupts available for general use: 15 + 30 4 Edge Free (not general-use) + 31 5 Level Free (not general-use) +CPU 1 interrupt status: + Int Level Type Status + 0 1 Level Reserved + 1 1 Level Used: FROM_CPU_INTR1 + 2 1 Level Used: SYSTIMER_TARGET1 + 3 1 Level Free + 4 1 Level Free + 5 1 Level Free + 6 1 Level CPU-internal + 7 1 Level CPU-internal + 8 1 Level Free + 9 1 Level Free + 10 1 Edge Free (not general-use) + 11 3 Level CPU-internal + 12 1 Level Free + 13 1 Level Free + 14 7 Level Reserved + 15 3 Level CPU-internal + 16 5 Level CPU-internal + 17 1 Level Free + 18 1 Level Free + 19 2 Level Free + 20 2 Level Free + 21 2 Level Free + 22 3 Edge Free (not general-use) + 23 3 Level Free + 24 4 Level Reserved + 25 4 Level Reserved + 26 5 Level Free (not general-use) + 27 3 Level Free + 28 4 Edge Reserved + 29 3 Level CPU-internal + 30 4 Edge Free (not general-use) + 31 5 Level Free (not general-use) +Interrupts available for general use: 24 Shared interrupts: 0