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Merge branch 'bugfix/xtal_freq_40_2.0' into 'release/v2.0'
esp32: by default, set 40MHz crystal frequency See merge request !1144
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@@ -337,6 +337,7 @@ check_doc_links:
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# clone test bench
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# clone test bench
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- git clone $GITLAB_SSH_SERVER/yinling/auto_test_script.git
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- git clone $GITLAB_SSH_SERVER/yinling/auto_test_script.git
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- cd auto_test_script
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- cd auto_test_script
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- git checkout ${CI_COMMIT_REF_NAME} || echo "Using default branch..."
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# run test
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# run test
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- python CIRunner.py -l $LOG_PATH -c $CONFIG_FILE -e $LOCAL_ENV_CONFIG_PATH -t $TEST_CASE_FILE_PATH -m $MODULE_UPDATE_FILE bin_path $APP_NAME $BIN_PATH
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- python CIRunner.py -l $LOG_PATH -c $CONFIG_FILE -e $LOCAL_ENV_CONFIG_PATH -t $TEST_CASE_FILE_PATH -m $MODULE_UPDATE_FILE bin_path $APP_NAME $BIN_PATH
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@@ -364,6 +365,7 @@ check_doc_links:
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# clone test bench
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# clone test bench
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- git clone $GITLAB_SSH_SERVER/yinling/auto_test_script.git
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- git clone $GITLAB_SSH_SERVER/yinling/auto_test_script.git
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- cd auto_test_script
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- cd auto_test_script
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- git checkout ${CI_COMMIT_REF_NAME} || echo "Using default branch..."
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# run test
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# run test
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- python CIRunner.py -l $LOG_PATH -c $CONFIG_FILE -e $LOCAL_ENV_CONFIG_PATH -t $TEST_CASE_FILE_PATH -m $MODULE_UPDATE_FILE bin_path $APP_NAME $BIN_PATH
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- python CIRunner.py -l $LOG_PATH -c $CONFIG_FILE -e $LOCAL_ENV_CONFIG_PATH -t $TEST_CASE_FILE_PATH -m $MODULE_UPDATE_FILE bin_path $APP_NAME $BIN_PATH
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@@ -36,7 +36,7 @@ void esp_set_cpu_freq(void)
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// wait uart tx finish, otherwise some uart output will be lost
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// wait uart tx finish, otherwise some uart output will be lost
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uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
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uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
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rtc_init_lite(XTAL_AUTO);
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rtc_init_lite(XTAL_40M);
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// work around a bug that RTC fast memory may be isolated
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// work around a bug that RTC fast memory may be isolated
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// from the system after rtc_init_lite
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// from the system after rtc_init_lite
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SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO_M);
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SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO_M);
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