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aes/sha: change gdma transfer ability for sram to be 1 byte aligned

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Previously GDMA transfer ability was set to 4 bytes, but buffers might
be not fulfill these requirements
This commit is contained in:
Marius Vikhammer
2021-08-05 11:02:17 +08:00
parent 1fd56e0b87
commit bf21cf0c99
2 changed files with 25 additions and 26 deletions
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26
components/mbedtls/port/crypto_shared_gdma/esp_crypto_shared_gdma.c
View File

@@ -53,20 +53,6 @@ static inline esp_err_t crypto_shared_gdma_new_channel(gdma_channel_alloc_config
return ret; return ret;
} }
#if SOC_GDMA_SUPPORT_PSRAM
/* Initialize external memory specific DMA configs */
static void esp_crypto_shared_dma_init_extmem(void)
{
gdma_transfer_ability_t transfer_ability = {
.sram_trans_align = 4,
.psram_trans_align = 16,
};
gdma_set_transfer_ability(tx_channel, &transfer_ability);
gdma_set_transfer_ability(rx_channel, &transfer_ability);
}
#endif //SOC_GDMA_SUPPORT_PSRAM
/* Initialize GDMA module and channels */ /* Initialize GDMA module and channels */
static esp_err_t crypto_shared_gdma_init(void) static esp_err_t crypto_shared_gdma_init(void)
{ {
@@ -80,6 +66,12 @@ static esp_err_t crypto_shared_gdma_init(void)
.direction = GDMA_CHANNEL_DIRECTION_RX, .direction = GDMA_CHANNEL_DIRECTION_RX,
}; };
gdma_transfer_ability_t transfer_ability = {
.sram_trans_align = 1,
.psram_trans_align = 16,
};
ret = crypto_shared_gdma_new_channel(&channel_config_tx, &tx_channel); ret = crypto_shared_gdma_new_channel(&channel_config_tx, &tx_channel);
if (ret != ESP_OK) { if (ret != ESP_OK) {
goto err; goto err;
@@ -91,9 +83,9 @@ static esp_err_t crypto_shared_gdma_init(void)
goto err; goto err;
} }
#if SOC_GDMA_SUPPORT_PSRAM
esp_crypto_shared_dma_init_extmem(); gdma_set_transfer_ability(tx_channel, &transfer_ability);
#endif //SOC_GDMA_SUPPORT_PSRAM gdma_set_transfer_ability(rx_channel, &transfer_ability);
gdma_connect(rx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_AES, 0)); gdma_connect(rx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_AES, 0));
gdma_connect(tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_AES, 0)); gdma_connect(tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_AES, 0));

25
components/mbedtls/test/test_aes.c
View File

@@ -773,9 +773,7 @@ TEST_CASE("mbedtls OFB, chained DMA descriptors", "[aes]")
#ifdef CONFIG_SPIRAM_USE_MALLOC const uint8_t expected_cipher_ctr_end[] = {
const uint8_t expected_cipher_psram_end[] = {
0x7e, 0xdf, 0x13, 0xf3, 0x56, 0xef, 0x67, 0x01, 0x7e, 0xdf, 0x13, 0xf3, 0x56, 0xef, 0x67, 0x01,
0xfc, 0x08, 0x49, 0x62, 0xfa, 0xfe, 0x0c, 0x8b, 0xfc, 0x08, 0x49, 0x62, 0xfa, 0xfe, 0x0c, 0x8b,
0x99, 0x39, 0x09, 0x51, 0x2c, 0x9a, 0xd5, 0x48, 0x99, 0x39, 0x09, 0x51, 0x2c, 0x9a, 0xd5, 0x48,
@@ -783,7 +781,7 @@ const uint8_t expected_cipher_psram_end[] = {
}; };
void aes_psram_ctr_test(uint32_t input_buf_caps, uint32_t output_buf_caps) void aes_ctr_alignment_test(uint32_t input_buf_caps, uint32_t output_buf_caps)
{ {
mbedtls_aes_context ctx; mbedtls_aes_context ctx;
uint8_t nonce[16]; uint8_t nonce[16];
@@ -815,7 +813,7 @@ void aes_psram_ctr_test(uint32_t input_buf_caps, uint32_t output_buf_caps)
offset = 0; offset = 0;
memset(nonce, 0x2F, 16); memset(nonce, 0x2F, 16);
mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, plaintext + i, chipertext + i); mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, plaintext + i, chipertext + i);
TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_psram_end, chipertext + i + SZ - 32, 32); TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_ctr_end, chipertext + i + SZ - 32, 32);
// Decrypt // Decrypt
offset = 0; offset = 0;
@@ -833,6 +831,15 @@ void aes_psram_ctr_test(uint32_t input_buf_caps, uint32_t output_buf_caps)
free(decryptedtext); free(decryptedtext);
} }
TEST_CASE("mbedtls AES internal mem alignment tests", "[aes]")
{
uint32_t internal_dma_caps = MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL;
aes_ctr_alignment_test(internal_dma_caps, internal_dma_caps);
}
#ifdef CONFIG_SPIRAM_USE_MALLOC
void aes_psram_one_buf_ctr_test(void) void aes_psram_one_buf_ctr_test(void)
{ {
mbedtls_aes_context ctx; mbedtls_aes_context ctx;
@@ -862,7 +869,7 @@ void aes_psram_one_buf_ctr_test(void)
memset(buf, 0x26, SZ + ALIGNMENT_SIZE_BYTES); memset(buf, 0x26, SZ + ALIGNMENT_SIZE_BYTES);
memset(nonce, 0x2F, 16); memset(nonce, 0x2F, 16);
mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, buf + i, buf + i); mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, buf + i, buf + i);
TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_psram_end, buf + i + SZ - 32, 32); TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_ctr_end, buf + i + SZ - 32, 32);
// Decrypt // Decrypt
offset = 0; offset = 0;
@@ -1444,9 +1451,9 @@ void aes_ext_flash_ctr_test(uint32_t output_buf_caps)
/* Tests how crypto DMA handles data in external memory */ /* Tests how crypto DMA handles data in external memory */
TEST_CASE("mbedtls AES PSRAM tests", "[aes]") TEST_CASE("mbedtls AES PSRAM tests", "[aes]")
{ {
aes_psram_ctr_test(MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM); aes_ctr_alignment_test(MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM);
aes_psram_ctr_test(MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL); aes_ctr_alignment_test(MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
aes_psram_ctr_test(MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM, MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM); aes_ctr_alignment_test(MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM, MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM);
aes_psram_one_buf_ctr_test(); aes_psram_one_buf_ctr_test();
} }