From 8fcca0138402e85ab1902423243997c9c3c0dc74 Mon Sep 17 00:00:00 2001 From: houwenxiang Date: Thu, 30 Apr 2020 13:45:45 +0800 Subject: [PATCH] driver(uart): fix uart module reset issue (release V3.3) On ESP32, due to fifo reset issue, UART2 will work incorrectly if reset the fifo of UART1(TX fifo and RX fifo). The software can workaround the RX fifo reset issue, while the TX fifo reset issue can not. When UART2 is used and UART1 is used as the log output port, a software reset can reproduce this issue. So we should reset the UART memory before the software reset to solve this problem. --- components/esp32/system_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp32/system_api.c b/components/esp32/system_api.c index 4de32887e2..ec941dcac0 100644 --- a/components/esp32/system_api.c +++ b/components/esp32/system_api.c @@ -305,7 +305,7 @@ void IRAM_ATTR esp_restart_noos() // Reset timer/spi/uart DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, - DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | DPORT_SPI_DMA_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST); + DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | DPORT_SPI_DMA_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST); DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); // Set CPU back to XTAL source, no PLL, same as hard reset