diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index 574cb8d3b1..dca148feca 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -75,6 +75,7 @@ #define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1E000) #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) +#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) //Registers Operation {{ diff --git a/components/soc/esp32c3/include/soc/spi_reg.h b/components/soc/esp32c3/include/soc/spi_reg.h index a08cb24f3c..361f58ba5c 100644 --- a/components/soc/esp32c3/include/soc/spi_reg.h +++ b/components/soc/esp32c3/include/soc/spi_reg.h @@ -1,24 +1,16 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SPI_REG_H_ #define _SOC_SPI_REG_H_ +#include "soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) /* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */ diff --git a/components/soc/esp32c3/ld/esp32c3.peripherals.ld b/components/soc/esp32c3/ld/esp32c3.peripherals.ld index 0ae0e5522a..f7c495fb5e 100644 --- a/components/soc/esp32c3/ld/esp32c3.peripherals.ld +++ b/components/soc/esp32c3/ld/esp32c3.peripherals.ld @@ -21,10 +21,8 @@ PROVIDE ( TIMERG0 = 0x6001F000 ); PROVIDE ( TIMERG1 = 0x60020000 ); PROVIDE ( SYSTIMER = 0x60023000 ); PROVIDE ( GPSPI2 = 0x60024000 ); -PROVIDE ( GPSPI3 = 0x60025000 ); PROVIDE ( SYSCON = 0x60026000 ); PROVIDE ( TWAI = 0x6002B000 ); -PROVIDE ( GPSPI4 = 0x60037000 ); PROVIDE ( APB_SARADC = 0x60040000 ); PROVIDE ( USB_SERIAL_JTAG = 0x60043000 ); PROVIDE ( GDMA = 0x6003F000 ); diff --git a/components/soc/esp32c3/spi_periph.c b/components/soc/esp32c3/spi_periph.c index ce1c5c9af9..b2f7e416b2 100644 --- a/components/soc/esp32c3/spi_periph.c +++ b/components/soc/esp32c3/spi_periph.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,29 +12,30 @@ */ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { { - .spiclk_out = SPICLK_OUT_MUX_IDX, - .spiclk_in = 0,/* SPI clock is not an input signal*/ - .spid_out = SPID_OUT_IDX, - .spiq_out = SPIQ_OUT_IDX, - .spiwp_out = SPIWP_OUT_IDX, - .spihd_out = SPIHD_OUT_IDX, - .spid_in = SPID_IN_IDX, - .spiq_in = SPIQ_IN_IDX, - .spiwp_in = SPIWP_IN_IDX, - .spihd_in = SPIHD_IN_IDX, - .spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */ - .spics_in = 0,/* SPI cs is not an input signal*/ - .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK, - .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI, - .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO, - .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP, - .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD, - .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS, - .irq = ETS_SPI1_INTR_SOURCE, + // MSPI has dedicated iomux pins + .spiclk_out = -1, + .spiclk_in = -1, + .spid_out = -1, + .spiq_out = -1, + .spiwp_out = -1, + .spihd_out = -1, + .spid_in = -1, + .spiq_in = -1, + .spiwp_in = -1, + .spihd_in = -1, + .spics_out = {-1}, + .spics_in = -1, + .spiclk_iomux_pin = -1, + .spid_iomux_pin = -1, + .spiq_iomux_pin = -1, + .spiwp_iomux_pin = -1, + .spihd_iomux_pin = -1, + .spics0_iomux_pin = -1, + .irq = -1, .irq_dma = -1, - .module = PERIPH_SPI_MODULE, - .hw = (spi_dev_t *) &SPIMEM1, - .func = SPI_FUNC_NUM, + .module = -1, + .hw = NULL, + .func = -1, }, { .spiclk_out = FSPICLK_OUT_IDX, .spiclk_in = FSPICLK_IN_IDX, diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h index 2f62a827a0..5a2bad6f8f 100644 --- a/components/soc/esp32s2/include/soc/soc.h +++ b/components/soc/esp32s2/include/soc/soc.h @@ -83,14 +83,15 @@ #define DR_REG_APB_SARADC_BASE 0x3f440000 #define DR_REG_USB_BASE 0x60080000 -#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) -#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 ) -#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 ) -#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE) -#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) +#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) +#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 ) +#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 ) +#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE) +#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) -#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) +#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3 +#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) //Convenient way to replace the register ops when ulp riscv projects //consume this file diff --git a/components/soc/esp32s2/include/soc/spi_mem_reg.h b/components/soc/esp32s2/include/soc/spi_mem_reg.h index fd3bf04a41..b08abdc1fb 100644 --- a/components/soc/esp32s2/include/soc/spi_mem_reg.h +++ b/components/soc/esp32s2/include/soc/spi_mem_reg.h @@ -1,25 +1,16 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SPI_MEM_REG_H_ #define _SOC_SPI_MEM_REG_H_ +#include "soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) #define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x000) /* SPI_MEM_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */ diff --git a/components/soc/esp32s2/include/soc/spi_reg.h b/components/soc/esp32s2/include/soc/spi_reg.h index 0f0f732baa..1097f31a15 100644 --- a/components/soc/esp32s2/include/soc/spi_reg.h +++ b/components/soc/esp32s2/include/soc/spi_reg.h @@ -1,25 +1,16 @@ -// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_SPI_REG_H_ #define _SOC_SPI_REG_H_ +#include "soc.h" #ifdef __cplusplus extern "C" { #endif -#include "soc.h" -#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (((i)>3) ? (((i-2)* 0x1000) + 0x10000) : ((i - 2)* 0x1000 ))) #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x000) /* SPI_USR : R/W ;bitpos:[24] ;default: 1'b0 ; */ diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index d25e852cac..4a4c62d811 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -112,14 +112,15 @@ #define DR_REG_DPORT_END 0x600D3FFC -#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) -#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) -#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) -#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) -#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) +#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) +#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) +#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) +#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) +#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) -#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) +#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3 +#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) //Convenient way to replace the register ops when ulp riscv projects //consume this file diff --git a/components/soc/esp32s3/ld/esp32s3.peripherals.ld b/components/soc/esp32s3/ld/esp32s3.peripherals.ld index 8e59dd5354..51f98e7e92 100644 --- a/components/soc/esp32s3/ld/esp32s3.peripherals.ld +++ b/components/soc/esp32s3/ld/esp32s3.peripherals.ld @@ -37,7 +37,6 @@ PROVIDE ( SYSCON = 0x60026000 ); PROVIDE ( I2C1 = 0x60027000 ); PROVIDE ( SDMMC = 0x60028000 ); PROVIDE ( TWAI = 0x6002B000 ); -PROVIDE ( GPSPI4 = 0x60037000 ); PROVIDE ( GDMA = 0x6003F000 ); PROVIDE ( UART2 = 0x6002E000 ); PROVIDE ( DMA = 0x6003F000 ); diff --git a/components/soc/esp32s3/spi_periph.c b/components/soc/esp32s3/spi_periph.c index fb7417ba6d..a1098d035f 100644 --- a/components/soc/esp32s3/spi_periph.c +++ b/components/soc/esp32s3/spi_periph.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,29 +12,30 @@ */ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { { - .spiclk_out = SPICLK_OUT_IDX, - .spiclk_in = 0,/* SPI clock is not an input signal*/ - .spid_out = SPID_OUT_IDX, - .spiq_out = SPIQ_OUT_IDX, - .spiwp_out = SPIWP_OUT_IDX, - .spihd_out = SPIHD_OUT_IDX, - .spid_in = SPID_IN_IDX, - .spiq_in = SPIQ_IN_IDX, - .spiwp_in = SPIWP_IN_IDX, - .spihd_in = SPIHD_IN_IDX, - .spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */ - .spics_in = 0,/* SPI cs is not an input signal*/ - .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK, - .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI, - .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO, - .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP, - .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD, - .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS, - .irq = ETS_SPI1_INTR_SOURCE, + // MSPI has dedicated iomux pins + .spiclk_out = -1, + .spiclk_in = -1, + .spid_out = -1, + .spiq_out = -1, + .spiwp_out = -1, + .spihd_out = -1, + .spid_in = -1, + .spiq_in = -1, + .spiwp_in = -1, + .spihd_in = -1, + .spics_out = {-1}, + .spics_in = -1, + .spiclk_iomux_pin = -1, + .spid_iomux_pin = -1, + .spiq_iomux_pin = -1, + .spiwp_iomux_pin = -1, + .spihd_iomux_pin = -1, + .spics0_iomux_pin = -1, + .irq = -1, .irq_dma = -1, - .module = PERIPH_SPI_MODULE, - .hw = (spi_dev_t *) &SPIMEM1, - .func = SPI_FUNC_NUM, + .module = -1, + .hw = NULL, + .func = -1, }, { .spiclk_out = FSPICLK_OUT_IDX, .spiclk_in = FSPICLK_IN_IDX, diff --git a/docs/en/api-reference/protocols/esp_spi_slave_protocol.rst b/docs/en/api-reference/protocols/esp_spi_slave_protocol.rst index fd41922fc8..d284326cce 100644 --- a/docs/en/api-reference/protocols/esp_spi_slave_protocol.rst +++ b/docs/en/api-reference/protocols/esp_spi_slave_protocol.rst @@ -44,10 +44,17 @@ should exist): to/read from. For other commands with this phase, they are meaningless, but still have to exist in the transaction. -- Dummy: 8-bit, floating, optional +.. only:: esp32s2 - This phase is the turn around time between the master and the slave on the bus, and also - provides enough time for the slave to prepare the data to send to master. + - Dummy: 8-bit (for 1-bit mode) or 4-bit (for 2/4-bit mode), floating, optional + + This phase is the turnaround time between the master and the slave on the bus, and also provides enough time for the slave to prepare the data to send to the master. + +.. only:: not esp32s2 + + - Dummy: 8-bit, floating, optional + + This phase is the turnaround time between the master and the slave on the bus, and also provides enough time for the slave to prepare the data to send to the master. - Data: variable length, the direction is also determined by the command. diff --git a/docs/zh_CN/api-reference/protocols/esp_spi_slave_protocol.rst b/docs/zh_CN/api-reference/protocols/esp_spi_slave_protocol.rst index 9aac000d85..13fe11f707 100644 --- a/docs/zh_CN/api-reference/protocols/esp_spi_slave_protocol.rst +++ b/docs/zh_CN/api-reference/protocols/esp_spi_slave_protocol.rst @@ -1 +1 @@ -.. include:: ../../../en/api-reference/protocols/esp_spi_slave_protocol.rst \ No newline at end of file +.. include:: ../../../en/api-reference/protocols/esp_spi_slave_protocol.rst