From c29d93986dbdccffc45b5b2027fbf1f559b0db90 Mon Sep 17 00:00:00 2001
From: Angus Gratton <angus@espressif.com>
Date: Thu, 26 Nov 2020 15:39:49 +1100
Subject: [PATCH] soc: Add initial ESP32-C3 support

From internal commit 7761d6e8
---
 components/soc/esp32/include/soc/soc_caps.h   |   10 +-
 components/soc/esp32c3/CMakeLists.txt         |   18 +
 components/soc/esp32c3/adc_periph.c           |   29 +
 components/soc/esp32c3/gpio_periph.c          |   65 +
 components/soc/esp32c3/i2c_apll.h             |  135 +
 components/soc/esp32c3/i2c_bbpll.h            |  183 +
 components/soc/esp32c3/i2c_periph.c           |   30 +
 components/soc/esp32c3/i2s_periph.c           |   38 +
 components/soc/esp32c3/include/soc/adc_caps.h |   44 +
 .../soc/esp32c3/include/soc/adc_channel.h     |   78 +
 .../soc/esp32c3/include/soc/apb_ctrl_reg.h    |  576 +++
 .../soc/esp32c3/include/soc/apb_ctrl_struct.h |  482 ++
 .../soc/esp32c3/include/soc/apb_saradc_reg.h  |  631 +++
 .../esp32c3/include/soc/apb_saradc_struct.h   |  490 ++
 .../esp32c3/include/soc/assist_debug_reg.h    |  691 +++
 .../soc/esp32c3/include/soc/boot_mode.h       |  101 +
 .../soc/esp32c3/include/soc/brownout_caps.h   |   25 +
 .../soc/esp32c3/include/soc/cache_memory.h    |  100 +
 components/soc/esp32c3/include/soc/cpu_caps.h |   20 +
 components/soc/esp32c3/include/soc/dac_caps.h |   20 +
 .../soc/esp32c3/include/soc/dport_access.h    |  111 +
 .../soc/esp32c3/include/soc/efuse_reg.h       | 2049 ++++++++
 .../soc/esp32c3/include/soc/efuse_struct.h    |  514 ++
 .../soc/esp32c3/include/soc/extmem_reg.h      |  992 ++++
 .../soc/esp32c3/include/soc/gdma_caps.h       |   17 +
 components/soc/esp32c3/include/soc/gdma_reg.h | 2419 +++++++++
 .../soc/esp32c3/include/soc/gdma_struct.h     |  331 ++
 .../soc/esp32c3/include/soc/gpio_caps.h       |   43 +
 .../soc/esp32c3/include/soc/gpio_pins.h       |   27 +
 components/soc/esp32c3/include/soc/gpio_reg.h | 4588 +++++++++++++++++
 .../soc/esp32c3/include/soc/gpio_sd_reg.h     |  114 +
 .../soc/esp32c3/include/soc/gpio_sd_struct.h  |   61 +
 .../soc/esp32c3/include/soc/gpio_sig_map.h    |  184 +
 .../soc/esp32c3/include/soc/gpio_struct.h     |  436 ++
 .../soc/esp32c3/include/soc/hwcrypto_reg.h    |  182 +
 components/soc/esp32c3/include/soc/i2c_caps.h |   37 +
 components/soc/esp32c3/include/soc/i2c_reg.h  | 1062 ++++
 .../soc/esp32c3/include/soc/i2c_struct.h      |  407 ++
 components/soc/esp32c3/include/soc/i2s_caps.h |   25 +
 components/soc/esp32c3/include/soc/i2s_reg.h  | 1051 ++++
 .../soc/esp32c3/include/soc/i2s_struct.h      |  336 ++
 .../esp32c3/include/soc/interrupt_core0_reg.h |  856 +++
 .../soc/esp32c3/include/soc/interrupt_reg.h   |    1 +
 .../soc/esp32c3/include/soc/io_mux_reg.h      |  262 +
 .../soc/esp32c3/include/soc/ledc_caps.h       |   26 +
 components/soc/esp32c3/include/soc/ledc_reg.h | 1226 +++++
 .../soc/esp32c3/include/soc/ledc_struct.h     |  220 +
 components/soc/esp32c3/include/soc/mpu_caps.h |   21 +
 .../soc/esp32c3/include/soc/periph_defs.h     |  119 +
 components/soc/esp32c3/include/soc/rmt_caps.h |   33 +
 components/soc/esp32c3/include/soc/rmt_reg.h  | 1144 ++++
 .../soc/esp32c3/include/soc/rmt_struct.h      |  308 ++
 components/soc/esp32c3/include/soc/rsa_caps.h |   26 +
 components/soc/esp32c3/include/soc/rtc.h      |  785 +++
 .../soc/esp32c3/include/soc/rtc_cntl_reg.h    | 2662 ++++++++++
 .../soc/esp32c3/include/soc/rtc_cntl_struct.h |  843 +++
 .../soc/esp32c3/include/soc/rtc_i2c_reg.h     |  684 +++
 .../soc/esp32c3/include/soc/rtc_i2c_struct.h  |  227 +
 .../soc/esp32c3/include/soc/rtc_io_caps.h     |   24 +
 components/soc/esp32c3/include/soc/sens_reg.h | 1733 +++++++
 .../soc/esp32c3/include/soc/sens_struct.h     |  504 ++
 .../soc/esp32c3/include/soc/sensitive_reg.h   | 2304 +++++++++
 .../esp32c3/include/soc/sensitive_struct.h    | 1912 +++++++
 components/soc/esp32c3/include/soc/sha_caps.h |   54 +
 .../soc/esp32c3/include/soc/sigmadelta_caps.h |   25 +
 components/soc/esp32c3/include/soc/soc.h      |  340 ++
 components/soc/esp32c3/include/soc/soc_caps.h |   45 +
 components/soc/esp32c3/include/soc/soc_pins.h |   24 +
 components/soc/esp32c3/include/soc/spi_caps.h |   38 +
 .../soc/esp32c3/include/soc/spi_mem_reg.h     | 1220 +++++
 .../soc/esp32c3/include/soc/spi_mem_struct.h  |  569 ++
 components/soc/esp32c3/include/soc/spi_pins.h |   39 +
 components/soc/esp32c3/include/soc/spi_reg.h  | 1443 ++++++
 .../soc/esp32c3/include/soc/spi_struct.h      |  382 ++
 .../soc/esp32c3/include/soc/syscon_reg.h      |  625 +++
 .../soc/esp32c3/include/soc/syscon_struct.h   |  482 ++
 .../soc/esp32c3/include/soc/system_reg.h      | 1050 ++++
 .../soc/esp32c3/include/soc/system_struct.h   | 1412 +++++
 .../soc/esp32c3/include/soc/systimer_caps.h   |   24 +
 .../soc/esp32c3/include/soc/systimer_reg.h    |  424 ++
 .../soc/esp32c3/include/soc/systimer_struct.h |  251 +
 .../esp32c3/include/soc/timer_group_caps.h    |   24 +
 .../soc/esp32c3/include/soc/timer_group_reg.h |  441 ++
 .../esp32c3/include/soc/timer_group_struct.h  |  222 +
 .../soc/esp32c3/include/soc/uart_caps.h       |   30 +
 .../soc/esp32c3/include/soc/uart_channel.h    |   61 +
 components/soc/esp32c3/include/soc/uart_reg.h | 1258 +++++
 .../soc/esp32c3/include/soc/uart_struct.h     |  406 ++
 components/soc/esp32c3/include/soc/uhci_reg.h |  748 +++
 .../soc/esp32c3/include/soc/uhci_struct.h     |  230 +
 components/soc/esp32c3/include/soc/wdev_reg.h |   20 +
 components/soc/esp32c3/interrupts.c           |   80 +
 components/soc/esp32c3/ledc_periph.c          |   25 +
 components/soc/esp32c3/rmt_periph.c           |   39 +
 components/soc/esp32c3/sigmadelta_periph.c    |   33 +
 components/soc/esp32c3/spi_periph.c           |   71 +
 components/soc/esp32c3/timer_periph.c         |   28 +
 components/soc/esp32c3/uart_periph.c          |   37 +
 components/soc/esp32s2/include/soc/soc_caps.h |   28 +-
 .../soc/esp32s3/include/soc/gdma_caps.h       |    1 +
 .../soc/esp32s3/include/soc/ledc_caps.h       |    2 +
 .../soc/esp32s3/include/soc/rtc_cntl_reg.h    |    2 +
 .../soc/esp32s3/include/soc/rtc_io_caps.h     |    3 +
 components/soc/esp32s3/include/soc/soc_caps.h |    8 +-
 components/soc/esp32s3/include/soc/spi_caps.h |    2 +
 components/soc/include/soc/adc_periph.h       |    3 +
 components/soc/include/soc/hwcrypto_periph.h  |    8 +
 components/soc/include/soc/lldesc.h           |    2 +
 components/soc/include/soc/rtc_io_periph.h    |   12 +-
 components/soc/include/soc/rtc_periph.h       |    1 +
 .../soc/include/soc/soc_memory_layout.h       |    5 +
 .../soc/include/soc/touch_sensor_periph.h     |    2 +
 112 files changed, 46939 insertions(+), 12 deletions(-)
 create mode 100644 components/soc/esp32c3/CMakeLists.txt
 create mode 100644 components/soc/esp32c3/adc_periph.c
 create mode 100644 components/soc/esp32c3/gpio_periph.c
 create mode 100644 components/soc/esp32c3/i2c_apll.h
 create mode 100644 components/soc/esp32c3/i2c_bbpll.h
 create mode 100644 components/soc/esp32c3/i2c_periph.c
 create mode 100644 components/soc/esp32c3/i2s_periph.c
 create mode 100644 components/soc/esp32c3/include/soc/adc_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/adc_channel.h
 create mode 100644 components/soc/esp32c3/include/soc/apb_ctrl_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/apb_ctrl_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/apb_saradc_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/apb_saradc_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/assist_debug_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/boot_mode.h
 create mode 100644 components/soc/esp32c3/include/soc/brownout_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/cache_memory.h
 create mode 100644 components/soc/esp32c3/include/soc/cpu_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/dac_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/dport_access.h
 create mode 100644 components/soc/esp32c3/include/soc/efuse_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/efuse_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/extmem_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/gdma_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/gdma_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/gdma_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/gpio_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/gpio_pins.h
 create mode 100644 components/soc/esp32c3/include/soc/gpio_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/gpio_sd_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/gpio_sd_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/gpio_sig_map.h
 create mode 100644 components/soc/esp32c3/include/soc/gpio_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/hwcrypto_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/i2c_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/i2c_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/i2c_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/i2s_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/i2s_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/i2s_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/interrupt_core0_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/interrupt_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/io_mux_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/ledc_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/ledc_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/ledc_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/mpu_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/periph_defs.h
 create mode 100644 components/soc/esp32c3/include/soc/rmt_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/rmt_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/rmt_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/rsa_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/rtc.h
 create mode 100644 components/soc/esp32c3/include/soc/rtc_cntl_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/rtc_cntl_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/rtc_i2c_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/rtc_i2c_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/rtc_io_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/sens_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/sens_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/sensitive_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/sensitive_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/sha_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/sigmadelta_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/soc.h
 create mode 100644 components/soc/esp32c3/include/soc/soc_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/soc_pins.h
 create mode 100644 components/soc/esp32c3/include/soc/spi_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/spi_mem_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/spi_mem_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/spi_pins.h
 create mode 100644 components/soc/esp32c3/include/soc/spi_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/spi_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/syscon_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/syscon_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/system_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/system_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/systimer_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/systimer_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/systimer_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/timer_group_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/timer_group_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/timer_group_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/uart_caps.h
 create mode 100644 components/soc/esp32c3/include/soc/uart_channel.h
 create mode 100644 components/soc/esp32c3/include/soc/uart_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/uart_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/uhci_reg.h
 create mode 100644 components/soc/esp32c3/include/soc/uhci_struct.h
 create mode 100644 components/soc/esp32c3/include/soc/wdev_reg.h
 create mode 100644 components/soc/esp32c3/interrupts.c
 create mode 100644 components/soc/esp32c3/ledc_periph.c
 create mode 100644 components/soc/esp32c3/rmt_periph.c
 create mode 100644 components/soc/esp32c3/sigmadelta_periph.c
 create mode 100644 components/soc/esp32c3/spi_periph.c
 create mode 100644 components/soc/esp32c3/timer_periph.c
 create mode 100644 components/soc/esp32c3/uart_periph.c

diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h
index 45889d3f42..d83ce33999 100644
--- a/components/soc/esp32/include/soc/soc_caps.h
+++ b/components/soc/esp32/include/soc/soc_caps.h
@@ -69,7 +69,8 @@
 #define SOC_EMAC_SUPPORTED          1
 #define SOC_RISCV_COPROC_SUPPORTED  0   //TODO: correct the caller and remove this line
 #define SOC_CPU_CORES_NUM           2
-
+#define SOC_ULP_SUPPORTED           1
+#define SOC_RTC_SLOW_MEM_SUPPORTED  1
 
 /*-------------------------- ADC CAPS ----------------------------------------*/
 #define SOC_ADC_PERIPH_NUM              (2)
@@ -173,6 +174,9 @@
 
 /*-------------------------- RTCIO CAPS --------------------------------------*/
 #define SOC_RTCIO_PIN_COUNT 18
+#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
+#define SOC_RTCIO_HOLD_SUPPORTED 1
+#define SOC_RTCIO_WAKE_SUPPORTED 1
 
 /*-------------------------- SIGMA DELTA CAPS --------------------------------*/
 #define SOC_SIGMADELTA_NUM            1
@@ -185,6 +189,7 @@
 #define SOC_SPI_PERIPH_CS_NUM(i)    3
 
 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
+#define SOC_SPI_MAX_PRE_DIVIDER     8192
 
 #define SOC_SPI_SUPPORT_AS_CS       1 //Support to toggle the CS while the clock toggles
 
@@ -235,6 +240,9 @@
 #define SOC_UART_BITRATE_MAX        (5000000)   /*!< Max bit rate supported by UART */
 
 
+/*-------------------------- SPIRAM CAPS -------------------------------------*/
+#define SOC_SPIRAM_SUPPORTED    1
+
 /*--------------------------- SHA CAPS ---------------------------------------*/
 /* ESP32 style SHA engine, where multiple states can be stored in parallel */
 #define SOC_SHA_SUPPORT_PARALLEL_ENG    (1)
diff --git a/components/soc/esp32c3/CMakeLists.txt b/components/soc/esp32c3/CMakeLists.txt
new file mode 100644
index 0000000000..318edc1dc9
--- /dev/null
+++ b/components/soc/esp32c3/CMakeLists.txt
@@ -0,0 +1,18 @@
+set(srcs
+    "adc_periph.c"
+    "gpio_periph.c"
+    "rtc_periph.c"
+    "interrupts.c"
+    "spi_periph.c"
+    "ledc_periph.c"
+    "rmt_periph.c"
+    "sigmadelta_periph.c"
+    "i2s_periph.c"
+    "i2c_periph.c"
+    "uart_periph.c"
+    "timer_periph.c")
+
+add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
+
+target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
+target_include_directories(${COMPONENT_LIB} PUBLIC . include)
diff --git a/components/soc/esp32c3/adc_periph.c b/components/soc/esp32c3/adc_periph.c
new file mode 100644
index 0000000000..68a6bfa4dd
--- /dev/null
+++ b/components/soc/esp32c3/adc_periph.c
@@ -0,0 +1,29 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "soc/adc_periph.h"
+
+/* Store IO number corresponding to the ADC channel number. */
+const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
+    /* ADC1 */
+    {
+        ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM,
+        ADC1_CHANNEL_5_GPIO_NUM, ADC1_CHANNEL_6_GPIO_NUM, ADC1_CHANNEL_7_GPIO_NUM, -1,                      -1
+    },
+    /* ADC2 */
+    {
+        ADC2_CHANNEL_0_GPIO_NUM, ADC2_CHANNEL_1_GPIO_NUM, ADC2_CHANNEL_2_GPIO_NUM, ADC2_CHANNEL_3_GPIO_NUM, ADC2_CHANNEL_4_GPIO_NUM,
+        ADC2_CHANNEL_5_GPIO_NUM, ADC2_CHANNEL_6_GPIO_NUM, ADC2_CHANNEL_7_GPIO_NUM, ADC2_CHANNEL_8_GPIO_NUM, ADC2_CHANNEL_9_GPIO_NUM
+    }
+};
diff --git a/components/soc/esp32c3/gpio_periph.c b/components/soc/esp32c3/gpio_periph.c
new file mode 100644
index 0000000000..88ef3a7418
--- /dev/null
+++ b/components/soc/esp32c3/gpio_periph.c
@@ -0,0 +1,65 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "soc/gpio_periph.h"
+
+const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
+    IO_MUX_GPIO0_REG,
+    IO_MUX_GPIO1_REG,
+    IO_MUX_GPIO2_REG,
+    IO_MUX_GPIO3_REG,
+    IO_MUX_GPIO4_REG,
+    IO_MUX_GPIO5_REG,
+    IO_MUX_GPIO6_REG,
+    IO_MUX_GPIO7_REG,
+    IO_MUX_GPIO8_REG,
+    IO_MUX_GPIO9_REG,
+    IO_MUX_GPIO10_REG,
+    IO_MUX_GPIO11_REG,
+    IO_MUX_GPIO12_REG,
+    IO_MUX_GPIO13_REG,
+    IO_MUX_GPIO14_REG,
+    IO_MUX_GPIO15_REG,
+    IO_MUX_GPIO16_REG,
+    IO_MUX_GPIO17_REG,
+    IO_MUX_GPIO18_REG,
+    IO_MUX_GPIO19_REG,
+    IO_MUX_GPIO20_REG,
+    IO_MUX_GPIO21_REG,
+};
+
+const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
+    0,  //GPIO0
+    0,  //GPIO1
+    0,  //GPIO2
+    0,  //GPIO3
+    0,  //GPIO4
+    0,  //GPIO5
+    BIT(5),     //GPIO6
+    BIT(6),     //GPIO7
+    BIT(3),     //GPIO8
+    BIT(4),     //GPIO9
+    BIT(0),     //GPIO10
+    BIT(15),    //GPIO11
+    BIT(10),    //GPIO12
+    BIT(12),    //GPIO13
+    BIT(8),     //GPIO14
+    BIT(7),     //GPIO15
+    BIT(9),     //GPIO16
+    BIT(11),    //GPIO17
+    BIT(1),     //GPIO18
+    BIT(2),     //GPIO19
+    BIT(13),    //GPIO20
+    BIT(14),    //GPIO21
+};
diff --git a/components/soc/esp32c3/i2c_apll.h b/components/soc/esp32c3/i2c_apll.h
new file mode 100644
index 0000000000..f25f0a7146
--- /dev/null
+++ b/components/soc/esp32c3/i2c_apll.h
@@ -0,0 +1,135 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+/**
+ * @file i2c_apll.h
+ * @brief Register definitions for audio PLL (APLL)
+ *
+ * This file lists register fields of APLL, located on an internal configuration
+ * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
+ * rtc_clk_apll_enable function in rtc_clk.c.
+ */
+
+#define I2C_APLL            0X6D
+#define I2C_APLL_HOSTID     3
+
+#define I2C_APLL_IR_CAL_DELAY        0
+#define I2C_APLL_IR_CAL_DELAY_MSB    3
+#define I2C_APLL_IR_CAL_DELAY_LSB    0
+
+#define I2C_APLL_IR_CAL_RSTB        0
+#define I2C_APLL_IR_CAL_RSTB_MSB    4
+#define I2C_APLL_IR_CAL_RSTB_LSB    4
+
+#define I2C_APLL_IR_CAL_START        0
+#define I2C_APLL_IR_CAL_START_MSB    5
+#define I2C_APLL_IR_CAL_START_LSB    5
+
+#define I2C_APLL_IR_CAL_UNSTOP        0
+#define I2C_APLL_IR_CAL_UNSTOP_MSB    6
+#define I2C_APLL_IR_CAL_UNSTOP_LSB    6
+
+#define I2C_APLL_OC_ENB_FCAL        0
+#define I2C_APLL_OC_ENB_FCAL_MSB    7
+#define I2C_APLL_OC_ENB_FCAL_LSB    7
+
+#define I2C_APLL_IR_CAL_EXT_CAP        1
+#define I2C_APLL_IR_CAL_EXT_CAP_MSB    4
+#define I2C_APLL_IR_CAL_EXT_CAP_LSB    0
+
+#define I2C_APLL_IR_CAL_ENX_CAP        1
+#define I2C_APLL_IR_CAL_ENX_CAP_MSB    5
+#define I2C_APLL_IR_CAL_ENX_CAP_LSB    5
+
+#define I2C_APLL_OC_LBW        1
+#define I2C_APLL_OC_LBW_MSB    6
+#define I2C_APLL_OC_LBW_LSB    6
+
+#define I2C_APLL_IR_CAL_CK_DIV        2
+#define I2C_APLL_IR_CAL_CK_DIV_MSB    3
+#define I2C_APLL_IR_CAL_CK_DIV_LSB    0
+
+#define I2C_APLL_OC_DCHGP        2
+#define I2C_APLL_OC_DCHGP_MSB    6
+#define I2C_APLL_OC_DCHGP_LSB    4
+
+#define I2C_APLL_OC_ENB_VCON        2
+#define I2C_APLL_OC_ENB_VCON_MSB    7
+#define I2C_APLL_OC_ENB_VCON_LSB    7
+
+#define I2C_APLL_OR_CAL_CAP        3
+#define I2C_APLL_OR_CAL_CAP_MSB    4
+#define I2C_APLL_OR_CAL_CAP_LSB    0
+
+#define I2C_APLL_OR_CAL_UDF        3
+#define I2C_APLL_OR_CAL_UDF_MSB    5
+#define I2C_APLL_OR_CAL_UDF_LSB    5
+
+#define I2C_APLL_OR_CAL_OVF        3
+#define I2C_APLL_OR_CAL_OVF_MSB    6
+#define I2C_APLL_OR_CAL_OVF_LSB    6
+
+#define I2C_APLL_OR_CAL_END        3
+#define I2C_APLL_OR_CAL_END_MSB    7
+#define I2C_APLL_OR_CAL_END_LSB    7
+
+#define I2C_APLL_OR_OUTPUT_DIV        4
+#define I2C_APLL_OR_OUTPUT_DIV_MSB    4
+#define I2C_APLL_OR_OUTPUT_DIV_LSB    0
+
+#define I2C_APLL_OC_TSCHGP        4
+#define I2C_APLL_OC_TSCHGP_MSB    6
+#define I2C_APLL_OC_TSCHGP_LSB    6
+
+#define I2C_APLL_EN_FAST_CAL        4
+#define I2C_APLL_EN_FAST_CAL_MSB    7
+#define I2C_APLL_EN_FAST_CAL_LSB    7
+
+#define I2C_APLL_OC_DHREF_SEL        5
+#define I2C_APLL_OC_DHREF_SEL_MSB    1
+#define I2C_APLL_OC_DHREF_SEL_LSB    0
+
+#define I2C_APLL_OC_DLREF_SEL        5
+#define I2C_APLL_OC_DLREF_SEL_MSB    3
+#define I2C_APLL_OC_DLREF_SEL_LSB    2
+
+#define I2C_APLL_SDM_DITHER        5
+#define I2C_APLL_SDM_DITHER_MSB    4
+#define I2C_APLL_SDM_DITHER_LSB    4
+
+#define I2C_APLL_SDM_STOP        5
+#define I2C_APLL_SDM_STOP_MSB    5
+#define I2C_APLL_SDM_STOP_LSB    5
+
+#define I2C_APLL_SDM_RSTB        5
+#define I2C_APLL_SDM_RSTB_MSB    6
+#define I2C_APLL_SDM_RSTB_LSB    6
+
+#define I2C_APLL_OC_DVDD        6
+#define I2C_APLL_OC_DVDD_MSB    4
+#define I2C_APLL_OC_DVDD_LSB    0
+
+#define I2C_APLL_DSDM2        7
+#define I2C_APLL_DSDM2_MSB    5
+#define I2C_APLL_DSDM2_LSB    0
+
+#define I2C_APLL_DSDM1        8
+#define I2C_APLL_DSDM1_MSB    7
+#define I2C_APLL_DSDM1_LSB    0
+
+#define I2C_APLL_DSDM0        9
+#define I2C_APLL_DSDM0_MSB    7
+#define I2C_APLL_DSDM0_LSB    0
diff --git a/components/soc/esp32c3/i2c_bbpll.h b/components/soc/esp32c3/i2c_bbpll.h
new file mode 100644
index 0000000000..c9d4753f49
--- /dev/null
+++ b/components/soc/esp32c3/i2c_bbpll.h
@@ -0,0 +1,183 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+/**
+ * @file i2c_apll.h
+ * @brief Register definitions for digital PLL (BBPLL)
+ *
+ * This file lists register fields of BBPLL, located on an internal configuration
+ * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
+ * rtc_clk_cpu_freq_set function in rtc_clk.c.
+ */
+
+#define I2C_BBPLL           0x66
+#define I2C_BBPLL_HOSTID    1
+
+#define I2C_BBPLL_IR_CAL_DELAY        0
+#define I2C_BBPLL_IR_CAL_DELAY_MSB    3
+#define I2C_BBPLL_IR_CAL_DELAY_LSB    0
+
+#define I2C_BBPLL_IR_CAL_CK_DIV        0
+#define I2C_BBPLL_IR_CAL_CK_DIV_MSB    7
+#define I2C_BBPLL_IR_CAL_CK_DIV_LSB    4
+
+#define I2C_BBPLL_IR_CAL_EXT_CAP        1
+#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB    3
+#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB    0
+
+#define I2C_BBPLL_IR_CAL_ENX_CAP        1
+#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB    4
+#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB    4
+
+#define I2C_BBPLL_IR_CAL_RSTB        1
+#define I2C_BBPLL_IR_CAL_RSTB_MSB    5
+#define I2C_BBPLL_IR_CAL_RSTB_LSB    5
+
+#define I2C_BBPLL_IR_CAL_START        1
+#define I2C_BBPLL_IR_CAL_START_MSB    6
+#define I2C_BBPLL_IR_CAL_START_LSB    6
+
+#define I2C_BBPLL_IR_CAL_UNSTOP        1
+#define I2C_BBPLL_IR_CAL_UNSTOP_MSB    7
+#define I2C_BBPLL_IR_CAL_UNSTOP_LSB    7
+
+#define I2C_BBPLL_OC_REF_DIV        2
+#define I2C_BBPLL_OC_REF_DIV_MSB    3
+#define I2C_BBPLL_OC_REF_DIV_LSB    0
+
+#define I2C_BBPLL_OC_DCHGP        2
+#define I2C_BBPLL_OC_DCHGP_MSB    6
+#define I2C_BBPLL_OC_DCHGP_LSB    4
+
+#define I2C_BBPLL_OC_ENB_FCAL        2
+#define I2C_BBPLL_OC_ENB_FCAL_MSB    7
+#define I2C_BBPLL_OC_ENB_FCAL_LSB    7
+
+#define I2C_BBPLL_OC_DIV_7_0        3
+#define I2C_BBPLL_OC_DIV_7_0_MSB    7
+#define I2C_BBPLL_OC_DIV_7_0_LSB    0
+
+#define I2C_BBPLL_RSTB_DIV_ADC        4
+#define I2C_BBPLL_RSTB_DIV_ADC_MSB    0
+#define I2C_BBPLL_RSTB_DIV_ADC_LSB    0
+
+#define I2C_BBPLL_MODE_HF        4
+#define I2C_BBPLL_MODE_HF_MSB    1
+#define I2C_BBPLL_MODE_HF_LSB    1
+
+#define I2C_BBPLL_DIV_ADC        4
+#define I2C_BBPLL_DIV_ADC_MSB    3
+#define I2C_BBPLL_DIV_ADC_LSB    2
+
+#define I2C_BBPLL_DIV_DAC        4
+#define I2C_BBPLL_DIV_DAC_MSB    4
+#define I2C_BBPLL_DIV_DAC_LSB    4
+
+#define I2C_BBPLL_DIV_CPU        4
+#define I2C_BBPLL_DIV_CPU_MSB    5
+#define I2C_BBPLL_DIV_CPU_LSB    5
+
+#define I2C_BBPLL_OC_ENB_VCON        4
+#define I2C_BBPLL_OC_ENB_VCON_MSB    6
+#define I2C_BBPLL_OC_ENB_VCON_LSB    6
+
+#define I2C_BBPLL_OC_TSCHGP        4
+#define I2C_BBPLL_OC_TSCHGP_MSB    7
+#define I2C_BBPLL_OC_TSCHGP_LSB    7
+
+#define I2C_BBPLL_OC_DR1        5
+#define I2C_BBPLL_OC_DR1_MSB    2
+#define I2C_BBPLL_OC_DR1_LSB    0
+
+#define I2C_BBPLL_OC_DR3        5
+#define I2C_BBPLL_OC_DR3_MSB    6
+#define I2C_BBPLL_OC_DR3_LSB    4
+
+#define I2C_BBPLL_EN_USB        5
+#define I2C_BBPLL_EN_USB_MSB    7
+#define I2C_BBPLL_EN_USB_LSB    7
+
+#define I2C_BBPLL_OC_DCUR        6
+#define I2C_BBPLL_OC_DCUR_MSB    2
+#define I2C_BBPLL_OC_DCUR_LSB    0
+
+#define I2C_BBPLL_INC_CUR        6
+#define I2C_BBPLL_INC_CUR_MSB    3
+#define I2C_BBPLL_INC_CUR_LSB    3
+
+#define I2C_BBPLL_OC_DHREF_SEL        6
+#define I2C_BBPLL_OC_DHREF_SEL_MSB    5
+#define I2C_BBPLL_OC_DHREF_SEL_LSB    4
+
+#define I2C_BBPLL_OC_DLREF_SEL        6
+#define I2C_BBPLL_OC_DLREF_SEL_MSB    7
+#define I2C_BBPLL_OC_DLREF_SEL_LSB    6
+
+#define I2C_BBPLL_OR_CAL_CAP        8
+#define I2C_BBPLL_OR_CAL_CAP_MSB    3
+#define I2C_BBPLL_OR_CAL_CAP_LSB    0
+
+#define I2C_BBPLL_OR_CAL_UDF        8
+#define I2C_BBPLL_OR_CAL_UDF_MSB    4
+#define I2C_BBPLL_OR_CAL_UDF_LSB    4
+
+#define I2C_BBPLL_OR_CAL_OVF        8
+#define I2C_BBPLL_OR_CAL_OVF_MSB    5
+#define I2C_BBPLL_OR_CAL_OVF_LSB    5
+
+#define I2C_BBPLL_OR_CAL_END        8
+#define I2C_BBPLL_OR_CAL_END_MSB    6
+#define I2C_BBPLL_OR_CAL_END_LSB    6
+
+#define I2C_BBPLL_OR_LOCK        8
+#define I2C_BBPLL_OR_LOCK_MSB    7
+#define I2C_BBPLL_OR_LOCK_LSB    7
+
+#define I2C_BBPLL_BBADC_DELAY1        9
+#define I2C_BBPLL_BBADC_DELAY1_MSB    1
+#define I2C_BBPLL_BBADC_DELAY1_LSB    0
+
+#define I2C_BBPLL_BBADC_DELAY2        9
+#define I2C_BBPLL_BBADC_DELAY2_MSB    3
+#define I2C_BBPLL_BBADC_DELAY2_LSB    2
+
+#define I2C_BBPLL_BBADC_DVDD        9
+#define I2C_BBPLL_BBADC_DVDD_MSB    5
+#define I2C_BBPLL_BBADC_DVDD_LSB    4
+
+#define I2C_BBPLL_BBADC_DREF        9
+#define I2C_BBPLL_BBADC_DREF_MSB    7
+#define I2C_BBPLL_BBADC_DREF_LSB    6
+
+#define I2C_BBPLL_BBADC_DCUR        10
+#define I2C_BBPLL_BBADC_DCUR_MSB    1
+#define I2C_BBPLL_BBADC_DCUR_LSB    0
+
+#define I2C_BBPLL_BBADC_INPUT_SHORT        10
+#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB    2
+#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB    2
+
+#define I2C_BBPLL_ENT_PLL        10
+#define I2C_BBPLL_ENT_PLL_MSB    3
+#define I2C_BBPLL_ENT_PLL_LSB    3
+
+#define I2C_BBPLL_DTEST        10
+#define I2C_BBPLL_DTEST_MSB    5
+#define I2C_BBPLL_DTEST_LSB    4
+
+#define I2C_BBPLL_ENT_ADC        10
+#define I2C_BBPLL_ENT_ADC_MSB    7
+#define I2C_BBPLL_ENT_ADC_LSB    6
diff --git a/components/soc/esp32c3/i2c_periph.c b/components/soc/esp32c3/i2c_periph.c
new file mode 100644
index 0000000000..67dfbc56e0
--- /dev/null
+++ b/components/soc/esp32c3/i2c_periph.c
@@ -0,0 +1,30 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "soc/i2c_periph.h"
+#include "soc/gpio_sig_map.h"
+
+/*
+ Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
+    {
+        .sda_out_sig = I2CEXT0_SDA_OUT_IDX,
+        .sda_in_sig = I2CEXT0_SDA_IN_IDX,
+        .scl_out_sig = I2CEXT0_SCL_OUT_IDX,
+        .scl_in_sig = I2CEXT0_SCL_IN_IDX,
+        .irq = ETS_I2C_EXT0_INTR_SOURCE,
+        .module = PERIPH_I2C0_MODULE,
+    },
+};
diff --git a/components/soc/esp32c3/i2s_periph.c b/components/soc/esp32c3/i2s_periph.c
new file mode 100644
index 0000000000..b20ff7fbf8
--- /dev/null
+++ b/components/soc/esp32c3/i2s_periph.c
@@ -0,0 +1,38 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "soc/i2s_periph.h"
+#include "soc/gpio_sig_map.h"
+
+/*
+ Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
+    {
+        // TODO ESP32-C3 IDF-2098
+
+        // .o_bck_in_sig = I2S0O_BCK_IN_IDX,
+        // .o_ws_in_sig = I2S0O_WS_IN_IDX,
+        // .o_bck_out_sig = I2S0O_BCK_OUT_IDX,
+        // .o_ws_out_sig = I2S0O_WS_OUT_IDX,
+        // .o_data_out_sig = I2S0O_SD_OUT_IDX,
+        // .i_bck_in_sig = I2S0I_BCK_OUT_IDX,
+        // .i_ws_in_sig = I2S0I_WS_OUT_IDX,
+        // .i_bck_out_sig = I2S0I_BCK_IN_IDX,
+        // .i_ws_out_sig = I2S0I_WS_IN_IDX,
+        // .i_data_in_sig = I2S0I_SD_IN_IDX,
+        .irq = ETS_I2S1_INTR_SOURCE,
+        .module = PERIPH_I2S1_MODULE,
+    }
+};
diff --git a/components/soc/esp32c3/include/soc/adc_caps.h b/components/soc/esp32c3/include/soc/adc_caps.h
new file mode 100644
index 0000000000..6572961ade
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/adc_caps.h
@@ -0,0 +1,44 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+
+#define SOC_ADC_PERIPH_NUM              (2)
+#define SOC_ADC_PATT_LEN_MAX            (16)
+
+#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10)
+#define SOC_ADC_MAX_CHANNEL_NUM         (10)
+
+#define SOC_ADC1_DATA_INVERT_DEFAULT    (0)
+#define SOC_ADC2_DATA_INVERT_DEFAULT    (0)
+
+#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
+
+#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT       (8)
+#define SOC_ADC_FSM_START_WAIT_DEFAULT      (5)
+#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT    (100)
+#define ADC_FSM_SAMPLE_CYCLE_DEFAULT        (2)
+
+/**
+ * Check if adc support digital controller (DMA) mode.
+ * @value
+ *      - 1 : support;
+ *      - 0 : not support;
+ */
+#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 1)
+
+#define SOC_ADC_PWDET_CCT_DEFAULT           (4)
+
+#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
+
+#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT     (1)
diff --git a/components/soc/esp32c3/include/soc/adc_channel.h b/components/soc/esp32c3/include/soc/adc_channel.h
new file mode 100644
index 0000000000..59cfeb6039
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/adc_channel.h
@@ -0,0 +1,78 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_ADC_CHANNEL_H
+#define _SOC_ADC_CHANNEL_H
+
+#define ADC1_GPIO1_CHANNEL     ADC1_CHANNEL_0
+#define ADC1_CHANNEL_0_GPIO_NUM 0
+
+#define ADC1_GPIO2_CHANNEL     ADC1_CHANNEL_1
+#define ADC1_CHANNEL_1_GPIO_NUM 1
+
+#define ADC1_GPIO3_CHANNEL     ADC1_CHANNEL_2
+#define ADC1_CHANNEL_2_GPIO_NUM 2
+
+#define ADC1_GPIO4_CHANNEL     ADC1_CHANNEL_3
+#define ADC1_CHANNEL_3_GPIO_NUM 3
+
+#define ADC1_GPIO5_CHANNEL     ADC1_CHANNEL_4
+#define ADC1_CHANNEL_4_GPIO_NUM 4
+
+#define ADC1_GPIO6_CHANNEL     ADC1_CHANNEL_5
+#define ADC1_CHANNEL_5_GPIO_NUM 5
+
+#define ADC1_GPIO7_CHANNEL     ADC1_CHANNEL_6
+#define ADC1_CHANNEL_6_GPIO_NUM 7
+
+#define ADC1_GPIO8_CHANNEL     ADC1_CHANNEL_7
+#define ADC1_CHANNEL_7_GPIO_NUM 8
+
+#define ADC1_GPIO9_CHANNEL     ADC1_CHANNEL_8
+#define ADC1_CHANNEL_8_GPIO_NUM 9
+
+#define ADC1_GPIO10_CHANNEL     ADC1_CHANNEL_9
+#define ADC1_CHANNEL_9_GPIO_NUM 10
+
+#define ADC2_GPIO11_CHANNEL      ADC2_CHANNEL_0
+#define ADC2_CHANNEL_0_GPIO_NUM 5
+
+#define ADC2_GPIO12_CHANNEL      ADC2_CHANNEL_1
+#define ADC2_CHANNEL_1_GPIO_NUM 6
+
+#define ADC2_GPIO13_CHANNEL      ADC2_CHANNEL_2
+#define ADC2_CHANNEL_2_GPIO_NUM 13
+
+#define ADC2_GPIO14_CHANNEL     ADC2_CHANNEL_3
+#define ADC2_CHANNEL_3_GPIO_NUM 14
+
+#define ADC2_GPIO15_CHANNEL     ADC2_CHANNEL_4
+#define ADC2_CHANNEL_4_GPIO_NUM 15
+
+#define ADC2_GPIO16_CHANNEL     ADC2_CHANNEL_5
+#define ADC2_CHANNEL_5_GPIO_NUM 16
+
+#define ADC2_GPIO17_CHANNEL     ADC2_CHANNEL_6
+#define ADC2_CHANNEL_6_GPIO_NUM 17
+
+#define ADC2_GPIO18_CHANNEL     ADC2_CHANNEL_7
+#define ADC2_CHANNEL_7_GPIO_NUM 18
+
+#define ADC2_GPIO19_CHANNEL     ADC2_CHANNEL_8
+#define ADC2_CHANNEL_8_GPIO_NUM 19
+
+#define ADC2_GPIO20_CHANNEL     ADC2_CHANNEL_9
+#define ADC2_CHANNEL_9_GPIO_NUM 20
+
+#endif
diff --git a/components/soc/esp32c3/include/soc/apb_ctrl_reg.h b/components/soc/esp32c3/include/soc/apb_ctrl_reg.h
new file mode 100644
index 0000000000..055b919b08
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/apb_ctrl_reg.h
@@ -0,0 +1,576 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_APB_CTRL_REG_H_
+#define _SOC_APB_CTRL_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define APB_CTRL_SYSCLK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x000)
+/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_RST_TICK_CNT  (BIT(12))
+#define APB_CTRL_RST_TICK_CNT_M  (BIT(12))
+#define APB_CTRL_RST_TICK_CNT_V  0x1
+#define APB_CTRL_RST_TICK_CNT_S  12
+/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_CLK_EN  (BIT(11))
+#define APB_CTRL_CLK_EN_M  (BIT(11))
+#define APB_CTRL_CLK_EN_V  0x1
+#define APB_CTRL_CLK_EN_S  11
+/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_CLK_320M_EN  (BIT(10))
+#define APB_CTRL_CLK_320M_EN_M  (BIT(10))
+#define APB_CTRL_CLK_320M_EN_V  0x1
+#define APB_CTRL_CLK_320M_EN_S  10
+/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
+/*description: */
+#define APB_CTRL_PRE_DIV_CNT  0x000003FF
+#define APB_CTRL_PRE_DIV_CNT_M  ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
+#define APB_CTRL_PRE_DIV_CNT_V  0x3FF
+#define APB_CTRL_PRE_DIV_CNT_S  0
+
+#define APB_CTRL_TICK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x004)
+/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: */
+#define APB_CTRL_TICK_ENABLE  (BIT(16))
+#define APB_CTRL_TICK_ENABLE_M  (BIT(16))
+#define APB_CTRL_TICK_ENABLE_V  0x1
+#define APB_CTRL_TICK_ENABLE_S  16
+/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
+/*description: */
+#define APB_CTRL_CK8M_TICK_NUM  0x000000FF
+#define APB_CTRL_CK8M_TICK_NUM_M  ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S))
+#define APB_CTRL_CK8M_TICK_NUM_V  0xFF
+#define APB_CTRL_CK8M_TICK_NUM_S  8
+/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
+/*description: */
+#define APB_CTRL_XTAL_TICK_NUM  0x000000FF
+#define APB_CTRL_XTAL_TICK_NUM_M  ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S))
+#define APB_CTRL_XTAL_TICK_NUM_V  0xFF
+#define APB_CTRL_XTAL_TICK_NUM_S  0
+
+#define APB_CTRL_CLK_OUT_EN_REG          (DR_REG_APB_CTRL_BASE + 0x008)
+/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK_XTAL_OEN  (BIT(10))
+#define APB_CTRL_CLK_XTAL_OEN_M  (BIT(10))
+#define APB_CTRL_CLK_XTAL_OEN_V  0x1
+#define APB_CTRL_CLK_XTAL_OEN_S  10
+/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK40X_BB_OEN  (BIT(9))
+#define APB_CTRL_CLK40X_BB_OEN_M  (BIT(9))
+#define APB_CTRL_CLK40X_BB_OEN_V  0x1
+#define APB_CTRL_CLK40X_BB_OEN_S  9
+/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK_DAC_CPU_OEN  (BIT(8))
+#define APB_CTRL_CLK_DAC_CPU_OEN_M  (BIT(8))
+#define APB_CTRL_CLK_DAC_CPU_OEN_V  0x1
+#define APB_CTRL_CLK_DAC_CPU_OEN_S  8
+/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK_ADC_INF_OEN  (BIT(7))
+#define APB_CTRL_CLK_ADC_INF_OEN_M  (BIT(7))
+#define APB_CTRL_CLK_ADC_INF_OEN_V  0x1
+#define APB_CTRL_CLK_ADC_INF_OEN_S  7
+/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK_320M_OEN  (BIT(6))
+#define APB_CTRL_CLK_320M_OEN_M  (BIT(6))
+#define APB_CTRL_CLK_320M_OEN_V  0x1
+#define APB_CTRL_CLK_320M_OEN_S  6
+/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK160_OEN  (BIT(5))
+#define APB_CTRL_CLK160_OEN_M  (BIT(5))
+#define APB_CTRL_CLK160_OEN_V  0x1
+#define APB_CTRL_CLK160_OEN_S  5
+/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK80_OEN  (BIT(4))
+#define APB_CTRL_CLK80_OEN_M  (BIT(4))
+#define APB_CTRL_CLK80_OEN_V  0x1
+#define APB_CTRL_CLK80_OEN_S  4
+/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK_BB_OEN  (BIT(3))
+#define APB_CTRL_CLK_BB_OEN_M  (BIT(3))
+#define APB_CTRL_CLK_BB_OEN_V  0x1
+#define APB_CTRL_CLK_BB_OEN_S  3
+/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK44_OEN  (BIT(2))
+#define APB_CTRL_CLK44_OEN_M  (BIT(2))
+#define APB_CTRL_CLK44_OEN_V  0x1
+#define APB_CTRL_CLK44_OEN_S  2
+/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK22_OEN  (BIT(1))
+#define APB_CTRL_CLK22_OEN_M  (BIT(1))
+#define APB_CTRL_CLK22_OEN_V  0x1
+#define APB_CTRL_CLK22_OEN_S  1
+/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK20_OEN  (BIT(0))
+#define APB_CTRL_CLK20_OEN_M  (BIT(0))
+#define APB_CTRL_CLK20_OEN_V  0x1
+#define APB_CTRL_CLK20_OEN_S  0
+
+#define APB_CTRL_WIFI_BB_CFG_REG          (DR_REG_APB_CTRL_BASE + 0x00C)
+/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define APB_CTRL_WIFI_BB_CFG  0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_M  ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S))
+#define APB_CTRL_WIFI_BB_CFG_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_S  0
+
+#define APB_CTRL_WIFI_BB_CFG_2_REG          (DR_REG_APB_CTRL_BASE + 0x010)
+/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define APB_CTRL_WIFI_BB_CFG_2  0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_2_M  ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S))
+#define APB_CTRL_WIFI_BB_CFG_2_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_2_S  0
+
+#define APB_CTRL_WIFI_CLK_EN_REG          (DR_REG_APB_CTRL_BASE + 0x014)
+/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
+/*description: */
+#define APB_CTRL_WIFI_CLK_EN  0xFFFFFFFF
+#define APB_CTRL_WIFI_CLK_EN_M  ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S))
+#define APB_CTRL_WIFI_CLK_EN_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_CLK_EN_S  0
+
+#define APB_CTRL_WIFI_RST_EN_REG          (DR_REG_APB_CTRL_BASE + 0x018)
+/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define APB_CTRL_WIFI_RST  0xFFFFFFFF
+#define APB_CTRL_WIFI_RST_M  ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S))
+#define APB_CTRL_WIFI_RST_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_RST_S  0
+
+#define APB_CTRL_HOST_INF_SEL_REG          (DR_REG_APB_CTRL_BASE + 0x01C)
+/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define APB_CTRL_PERI_IO_SWAP  0x000000FF
+#define APB_CTRL_PERI_IO_SWAP_M  ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S))
+#define APB_CTRL_PERI_IO_SWAP_V  0xFF
+#define APB_CTRL_PERI_IO_SWAP_S  0
+
+#define APB_CTRL_EXT_MEM_PMS_LOCK_REG          (DR_REG_APB_CTRL_BASE + 0x020)
+/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_EXT_MEM_PMS_LOCK  (BIT(0))
+#define APB_CTRL_EXT_MEM_PMS_LOCK_M  (BIT(0))
+#define APB_CTRL_EXT_MEM_PMS_LOCK_V  0x1
+#define APB_CTRL_EXT_MEM_PMS_LOCK_S  0
+
+#define APB_CTRL_FLASH_ACE0_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x028)
+/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE0_ATTR  0x00000003
+#define APB_CTRL_FLASH_ACE0_ATTR_M  ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S))
+#define APB_CTRL_FLASH_ACE0_ATTR_V  0x3
+#define APB_CTRL_FLASH_ACE0_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE1_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x02C)
+/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE1_ATTR  0x00000003
+#define APB_CTRL_FLASH_ACE1_ATTR_M  ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S))
+#define APB_CTRL_FLASH_ACE1_ATTR_V  0x3
+#define APB_CTRL_FLASH_ACE1_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE2_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x030)
+/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE2_ATTR  0x00000003
+#define APB_CTRL_FLASH_ACE2_ATTR_M  ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S))
+#define APB_CTRL_FLASH_ACE2_ATTR_V  0x3
+#define APB_CTRL_FLASH_ACE2_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE3_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x034)
+/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE3_ATTR  0x00000003
+#define APB_CTRL_FLASH_ACE3_ATTR_M  ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S))
+#define APB_CTRL_FLASH_ACE3_ATTR_V  0x3
+#define APB_CTRL_FLASH_ACE3_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE0_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x038)
+/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE0_ADDR_S  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE0_ADDR_S_M  ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE0_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE0_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE1_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x03C)
+/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE1_ADDR_S  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE1_ADDR_S_M  ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE1_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE1_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE2_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x040)
+/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE2_ADDR_S  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE2_ADDR_S_M  ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE2_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE2_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE3_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x044)
+/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hC00000 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE3_ADDR_S  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE3_ADDR_S_M  ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE3_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE3_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE0_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x048)
+/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE0_SIZE  0x00001FFF
+#define APB_CTRL_FLASH_ACE0_SIZE_M  ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S))
+#define APB_CTRL_FLASH_ACE0_SIZE_V  0x1FFF
+#define APB_CTRL_FLASH_ACE0_SIZE_S  0
+
+#define APB_CTRL_FLASH_ACE1_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x04C)
+/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE1_SIZE  0x00001FFF
+#define APB_CTRL_FLASH_ACE1_SIZE_M  ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S))
+#define APB_CTRL_FLASH_ACE1_SIZE_V  0x1FFF
+#define APB_CTRL_FLASH_ACE1_SIZE_S  0
+
+#define APB_CTRL_FLASH_ACE2_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x050)
+/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE2_SIZE  0x00001FFF
+#define APB_CTRL_FLASH_ACE2_SIZE_M  ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S))
+#define APB_CTRL_FLASH_ACE2_SIZE_V  0x1FFF
+#define APB_CTRL_FLASH_ACE2_SIZE_S  0
+
+#define APB_CTRL_FLASH_ACE3_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x054)
+/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE3_SIZE  0x00001FFF
+#define APB_CTRL_FLASH_ACE3_SIZE_M  ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S))
+#define APB_CTRL_FLASH_ACE3_SIZE_V  0x1FFF
+#define APB_CTRL_FLASH_ACE3_SIZE_S  0
+
+#define APB_CTRL_SPI_MEM_PMS_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x088)
+/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
+/*description: */
+#define APB_CTRL_SPI_MEM_REJECT_CDE  0x0000001F
+#define APB_CTRL_SPI_MEM_REJECT_CDE_M  ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S))
+#define APB_CTRL_SPI_MEM_REJECT_CDE_V  0x1F
+#define APB_CTRL_SPI_MEM_REJECT_CDE_S  2
+/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_SPI_MEM_REJECT_CLR  (BIT(1))
+#define APB_CTRL_SPI_MEM_REJECT_CLR_M  (BIT(1))
+#define APB_CTRL_SPI_MEM_REJECT_CLR_V  0x1
+#define APB_CTRL_SPI_MEM_REJECT_CLR_S  1
+/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_SPI_MEM_REJECT_INT  (BIT(0))
+#define APB_CTRL_SPI_MEM_REJECT_INT_M  (BIT(0))
+#define APB_CTRL_SPI_MEM_REJECT_INT_V  0x1
+#define APB_CTRL_SPI_MEM_REJECT_INT_S  0
+
+#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x08C)
+/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define APB_CTRL_SPI_MEM_REJECT_ADDR  0xFFFFFFFF
+#define APB_CTRL_SPI_MEM_REJECT_ADDR_M  ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S))
+#define APB_CTRL_SPI_MEM_REJECT_ADDR_V  0xFFFFFFFF
+#define APB_CTRL_SPI_MEM_REJECT_ADDR_S  0
+
+#define APB_CTRL_SDIO_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x090)
+/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define APB_CTRL_SDIO_WIN_ACCESS_EN  (BIT(0))
+#define APB_CTRL_SDIO_WIN_ACCESS_EN_M  (BIT(0))
+#define APB_CTRL_SDIO_WIN_ACCESS_EN_V  0x1
+#define APB_CTRL_SDIO_WIN_ACCESS_EN_S  0
+
+#define APB_CTRL_REDCY_SIG0_REG          (DR_REG_APB_CTRL_BASE + 0x094)
+/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define APB_CTRL_REDCY_ANDOR  (BIT(31))
+#define APB_CTRL_REDCY_ANDOR_M  (BIT(31))
+#define APB_CTRL_REDCY_ANDOR_V  0x1
+#define APB_CTRL_REDCY_ANDOR_S  31
+/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: */
+#define APB_CTRL_REDCY_SIG0  0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG0_M  ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S))
+#define APB_CTRL_REDCY_SIG0_V  0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG0_S  0
+
+#define APB_CTRL_REDCY_SIG1_REG          (DR_REG_APB_CTRL_BASE + 0x098)
+/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define APB_CTRL_REDCY_NANDOR  (BIT(31))
+#define APB_CTRL_REDCY_NANDOR_M  (BIT(31))
+#define APB_CTRL_REDCY_NANDOR_V  0x1
+#define APB_CTRL_REDCY_NANDOR_S  31
+/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: */
+#define APB_CTRL_REDCY_SIG1  0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG1_M  ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S))
+#define APB_CTRL_REDCY_SIG1_V  0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG1_S  0
+
+#define APB_CTRL_FRONT_END_MEM_PD_REG          (DR_REG_APB_CTRL_BASE + 0x09C)
+/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_DC_MEM_FORCE_PD  (BIT(5))
+#define APB_CTRL_DC_MEM_FORCE_PD_M  (BIT(5))
+#define APB_CTRL_DC_MEM_FORCE_PD_V  0x1
+#define APB_CTRL_DC_MEM_FORCE_PD_S  5
+/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_DC_MEM_FORCE_PU  (BIT(4))
+#define APB_CTRL_DC_MEM_FORCE_PU_M  (BIT(4))
+#define APB_CTRL_DC_MEM_FORCE_PU_V  0x1
+#define APB_CTRL_DC_MEM_FORCE_PU_S  4
+/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_PBUS_MEM_FORCE_PD  (BIT(3))
+#define APB_CTRL_PBUS_MEM_FORCE_PD_M  (BIT(3))
+#define APB_CTRL_PBUS_MEM_FORCE_PD_V  0x1
+#define APB_CTRL_PBUS_MEM_FORCE_PD_S  3
+/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_PBUS_MEM_FORCE_PU  (BIT(2))
+#define APB_CTRL_PBUS_MEM_FORCE_PU_M  (BIT(2))
+#define APB_CTRL_PBUS_MEM_FORCE_PU_V  0x1
+#define APB_CTRL_PBUS_MEM_FORCE_PU_S  2
+/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_AGC_MEM_FORCE_PD  (BIT(1))
+#define APB_CTRL_AGC_MEM_FORCE_PD_M  (BIT(1))
+#define APB_CTRL_AGC_MEM_FORCE_PD_V  0x1
+#define APB_CTRL_AGC_MEM_FORCE_PD_S  1
+/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_AGC_MEM_FORCE_PU  (BIT(0))
+#define APB_CTRL_AGC_MEM_FORCE_PU_M  (BIT(0))
+#define APB_CTRL_AGC_MEM_FORCE_PU_V  0x1
+#define APB_CTRL_AGC_MEM_FORCE_PU_S  0
+
+#define APB_CTRL_RETENTION_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x0A0)
+/* APB_CTRL_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_NOBYPASS_CPU_ISO_RST  (BIT(27))
+#define APB_CTRL_NOBYPASS_CPU_ISO_RST_M  (BIT(27))
+#define APB_CTRL_NOBYPASS_CPU_ISO_RST_V  0x1
+#define APB_CTRL_NOBYPASS_CPU_ISO_RST_S  27
+/* APB_CTRL_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
+/*description: */
+#define APB_CTRL_RETENTION_LINK_ADDR  0x07FFFFFF
+#define APB_CTRL_RETENTION_LINK_ADDR_M  ((APB_CTRL_RETENTION_LINK_ADDR_V)<<(APB_CTRL_RETENTION_LINK_ADDR_S))
+#define APB_CTRL_RETENTION_LINK_ADDR_V  0x7FFFFFF
+#define APB_CTRL_RETENTION_LINK_ADDR_S  0
+
+#define APB_CTRL_CLKGATE_FORCE_ON_REG          (DR_REG_APB_CTRL_BASE + 0x0A4)
+/* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
+/*description: */
+#define APB_CTRL_SRAM_CLKGATE_FORCE_ON  0x0000000F
+#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_M  ((APB_CTRL_SRAM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_SRAM_CLKGATE_FORCE_ON_S))
+#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_V  0xF
+#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_S  2
+/* APB_CTRL_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define APB_CTRL_ROM_CLKGATE_FORCE_ON  0x00000003
+#define APB_CTRL_ROM_CLKGATE_FORCE_ON_M  ((APB_CTRL_ROM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_ROM_CLKGATE_FORCE_ON_S))
+#define APB_CTRL_ROM_CLKGATE_FORCE_ON_V  0x3
+#define APB_CTRL_ROM_CLKGATE_FORCE_ON_S  0
+
+#define APB_CTRL_MEM_POWER_DOWN_REG          (DR_REG_APB_CTRL_BASE + 0x0A8)
+/* APB_CTRL_SRAM_POWER_DOWN : R/W ;bitpos:[5:2] ;default: 4'b0 ; */
+/*description: */
+#define APB_CTRL_SRAM_POWER_DOWN  0x0000000F
+#define APB_CTRL_SRAM_POWER_DOWN_M  ((APB_CTRL_SRAM_POWER_DOWN_V)<<(APB_CTRL_SRAM_POWER_DOWN_S))
+#define APB_CTRL_SRAM_POWER_DOWN_V  0xF
+#define APB_CTRL_SRAM_POWER_DOWN_S  2
+/* APB_CTRL_ROM_POWER_DOWN : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define APB_CTRL_ROM_POWER_DOWN  0x00000003
+#define APB_CTRL_ROM_POWER_DOWN_M  ((APB_CTRL_ROM_POWER_DOWN_V)<<(APB_CTRL_ROM_POWER_DOWN_S))
+#define APB_CTRL_ROM_POWER_DOWN_V  0x3
+#define APB_CTRL_ROM_POWER_DOWN_S  0
+
+#define APB_CTRL_MEM_POWER_UP_REG          (DR_REG_APB_CTRL_BASE + 0x0AC)
+/* APB_CTRL_SRAM_POWER_UP : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
+/*description: */
+#define APB_CTRL_SRAM_POWER_UP  0x0000000F
+#define APB_CTRL_SRAM_POWER_UP_M  ((APB_CTRL_SRAM_POWER_UP_V)<<(APB_CTRL_SRAM_POWER_UP_S))
+#define APB_CTRL_SRAM_POWER_UP_V  0xF
+#define APB_CTRL_SRAM_POWER_UP_S  2
+/* APB_CTRL_ROM_POWER_UP : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define APB_CTRL_ROM_POWER_UP  0x00000003
+#define APB_CTRL_ROM_POWER_UP_M  ((APB_CTRL_ROM_POWER_UP_V)<<(APB_CTRL_ROM_POWER_UP_S))
+#define APB_CTRL_ROM_POWER_UP_V  0x3
+#define APB_CTRL_ROM_POWER_UP_S  0
+
+#define APB_CTRL_RND_DATA_REG          (DR_REG_APB_CTRL_BASE + 0x0B0)
+/* APB_CTRL_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define APB_CTRL_RND_DATA  0xFFFFFFFF
+#define APB_CTRL_RND_DATA_M  ((APB_CTRL_RND_DATA_V)<<(APB_CTRL_RND_DATA_S))
+#define APB_CTRL_RND_DATA_V  0xFFFFFFFF
+#define APB_CTRL_RND_DATA_S  0
+
+#define APB_CTRL_PERI_BACKUP_CONFIG_REG          (DR_REG_APB_CTRL_BASE + 0x0B4)
+/* APB_CTRL_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_ENA  (BIT(31))
+#define APB_CTRL_PERI_BACKUP_ENA_M  (BIT(31))
+#define APB_CTRL_PERI_BACKUP_ENA_V  0x1
+#define APB_CTRL_PERI_BACKUP_ENA_S  31
+/* APB_CTRL_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_TO_MEM  (BIT(30))
+#define APB_CTRL_PERI_BACKUP_TO_MEM_M  (BIT(30))
+#define APB_CTRL_PERI_BACKUP_TO_MEM_V  0x1
+#define APB_CTRL_PERI_BACKUP_TO_MEM_S  30
+/* APB_CTRL_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_START  (BIT(29))
+#define APB_CTRL_PERI_BACKUP_START_M  (BIT(29))
+#define APB_CTRL_PERI_BACKUP_START_V  0x1
+#define APB_CTRL_PERI_BACKUP_START_S  29
+/* APB_CTRL_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_SIZE  0x000003FF
+#define APB_CTRL_PERI_BACKUP_SIZE_M  ((APB_CTRL_PERI_BACKUP_SIZE_V)<<(APB_CTRL_PERI_BACKUP_SIZE_S))
+#define APB_CTRL_PERI_BACKUP_SIZE_V  0x3FF
+#define APB_CTRL_PERI_BACKUP_SIZE_S  19
+/* APB_CTRL_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_TOUT_THRES  0x000003FF
+#define APB_CTRL_PERI_BACKUP_TOUT_THRES_M  ((APB_CTRL_PERI_BACKUP_TOUT_THRES_V)<<(APB_CTRL_PERI_BACKUP_TOUT_THRES_S))
+#define APB_CTRL_PERI_BACKUP_TOUT_THRES_V  0x3FF
+#define APB_CTRL_PERI_BACKUP_TOUT_THRES_S  9
+/* APB_CTRL_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_BURST_LIMIT  0x0000001F
+#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_M  ((APB_CTRL_PERI_BACKUP_BURST_LIMIT_V)<<(APB_CTRL_PERI_BACKUP_BURST_LIMIT_S))
+#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_V  0x1F
+#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_S  4
+/* APB_CTRL_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_FLOW_ERR  0x00000003
+#define APB_CTRL_PERI_BACKUP_FLOW_ERR_M  ((APB_CTRL_PERI_BACKUP_FLOW_ERR_V)<<(APB_CTRL_PERI_BACKUP_FLOW_ERR_S))
+#define APB_CTRL_PERI_BACKUP_FLOW_ERR_V  0x3
+#define APB_CTRL_PERI_BACKUP_FLOW_ERR_S  1
+
+#define APB_CTRL_PERI_BACKUP_APB_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x0B8)
+/* APB_CTRL_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: */
+#define APB_CTRL_BACKUP_APB_START_ADDR  0xFFFFFFFF
+#define APB_CTRL_BACKUP_APB_START_ADDR_M  ((APB_CTRL_BACKUP_APB_START_ADDR_V)<<(APB_CTRL_BACKUP_APB_START_ADDR_S))
+#define APB_CTRL_BACKUP_APB_START_ADDR_V  0xFFFFFFFF
+#define APB_CTRL_BACKUP_APB_START_ADDR_S  0
+
+#define APB_CTRL_PERI_BACKUP_MEM_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x0BC)
+/* APB_CTRL_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: */
+#define APB_CTRL_BACKUP_MEM_START_ADDR  0xFFFFFFFF
+#define APB_CTRL_BACKUP_MEM_START_ADDR_M  ((APB_CTRL_BACKUP_MEM_START_ADDR_V)<<(APB_CTRL_BACKUP_MEM_START_ADDR_S))
+#define APB_CTRL_BACKUP_MEM_START_ADDR_V  0xFFFFFFFF
+#define APB_CTRL_BACKUP_MEM_START_ADDR_S  0
+
+#define APB_CTRL_PERI_BACKUP_INT_RAW_REG          (DR_REG_APB_CTRL_BASE + 0x0C0)
+/* APB_CTRL_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_M  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_V  0x1
+#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_S  1
+/* APB_CTRL_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_M  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_V  0x1
+#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_S  0
+
+#define APB_CTRL_PERI_BACKUP_INT_ST_REG          (DR_REG_APB_CTRL_BASE + 0x0C4)
+/* APB_CTRL_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ST  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_M  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_V  0x1
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_S  1
+/* APB_CTRL_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ST  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_M  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_V  0x1
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_S  0
+
+#define APB_CTRL_PERI_BACKUP_INT_ENA_REG          (DR_REG_APB_CTRL_BASE + 0x0C8)
+/* APB_CTRL_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_M  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_V  0x1
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_S  1
+/* APB_CTRL_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_M  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_V  0x1
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_S  0
+
+#define APB_CTRL_PERI_BACKUP_INT_CLR_REG          (DR_REG_APB_CTRL_BASE + 0x0D0)
+/* APB_CTRL_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_M  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_V  0x1
+#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_S  1
+/* APB_CTRL_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_M  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_V  0x1
+#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_S  0
+
+#define APB_CTRL_DATE_REG          (DR_REG_APB_CTRL_BASE + 0x3FC)
+/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007210 ; */
+/*description: Version control*/
+#define APB_CTRL_DATE  0xFFFFFFFF
+#define APB_CTRL_DATE_M  ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))
+#define APB_CTRL_DATE_V  0xFFFFFFFF
+#define APB_CTRL_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_APB_CTRL_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/apb_ctrl_struct.h b/components/soc/esp32c3/include/soc/apb_ctrl_struct.h
new file mode 100644
index 0000000000..9b832df8dd
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/apb_ctrl_struct.h
@@ -0,0 +1,482 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_APB_CTRL_STRUCT_H_
+#define _SOC_APB_CTRL_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t pre_div:     10;
+            uint32_t clk_320m_en:  1;
+            uint32_t clk_en:       1;
+            uint32_t rst_tick:     1;
+            uint32_t reserved13:  19;
+        };
+        uint32_t val;
+    } clk_conf;
+    union {
+        struct {
+            uint32_t xtal_tick:     8;
+            uint32_t ck8m_tick:     8;
+            uint32_t tick_enable:   1;
+            uint32_t reserved17:   15;
+        };
+        uint32_t val;
+    } tick_conf;
+    union {
+        struct {
+            uint32_t clk20_oen:       1;
+            uint32_t clk22_oen:       1;
+            uint32_t clk44_oen:       1;
+            uint32_t clk_bb_oen:      1;
+            uint32_t clk80_oen:       1;
+            uint32_t clk160_oen:      1;
+            uint32_t clk_320m_oen:    1;
+            uint32_t clk_adc_inf_oen: 1;
+            uint32_t clk_dac_cpu_oen: 1;
+            uint32_t clk40x_bb_oen:   1;
+            uint32_t clk_xtal_oen:    1;
+            uint32_t reserved11:     21;
+        };
+        uint32_t val;
+    } clk_out_en;
+    uint32_t wifi_bb_cfg;                               /**/
+    uint32_t wifi_bb_cfg_2;                             /**/
+    uint32_t wifi_clk_en;                               /**/
+    uint32_t wifi_rst_en;                               /**/
+    union {
+        struct {
+            uint32_t peri_io_swap: 8;
+            uint32_t reserved8:   24;
+        };
+        uint32_t val;
+    } host_inf_sel;
+    union {
+        struct {
+            uint32_t ext_mem_pms_lock: 1;
+            uint32_t reserved1:       31;
+        };
+        uint32_t val;
+    } ext_mem_pms_lock;
+    uint32_t reserved_24;
+    union {
+        struct {
+            uint32_t flash_ace0_attr: 2;
+            uint32_t reserved2:      30;
+        };
+        uint32_t val;
+    } flash_ace0_attr;
+    union {
+        struct {
+            uint32_t flash_ace1_attr: 2;
+            uint32_t reserved2:      30;
+        };
+        uint32_t val;
+    } flash_ace1_attr;
+    union {
+        struct {
+            uint32_t flash_ace2_attr: 2;
+            uint32_t reserved2:      30;
+        };
+        uint32_t val;
+    } flash_ace2_attr;
+    union {
+        struct {
+            uint32_t flash_ace3_attr: 2;
+            uint32_t reserved2:      30;
+        };
+        uint32_t val;
+    } flash_ace3_attr;
+    uint32_t flash_ace0_addr;                           /**/
+    uint32_t flash_ace1_addr;                           /**/
+    uint32_t flash_ace2_addr;                           /**/
+    uint32_t flash_ace3_addr;                           /**/
+    union {
+        struct {
+            uint32_t flash_ace0_size:13;
+            uint32_t reserved13:     19;
+        };
+        uint32_t val;
+    } flash_ace0_size;
+    union {
+        struct {
+            uint32_t flash_ace1_size:13;
+            uint32_t reserved13:     19;
+        };
+        uint32_t val;
+    } flash_ace1_size;
+    union {
+        struct {
+            uint32_t flash_ace2_size:13;
+            uint32_t reserved13:     19;
+        };
+        uint32_t val;
+    } flash_ace2_size;
+    union {
+        struct {
+            uint32_t flash_ace3_size:13;
+            uint32_t reserved13:     19;
+        };
+        uint32_t val;
+    } flash_ace3_size;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    union {
+        struct {
+            uint32_t spi_mem_reject_int: 1;
+            uint32_t spi_mem_reject_clr: 1;
+            uint32_t spi_mem_reject_cde: 5;
+            uint32_t reserved7:         25;
+        };
+        uint32_t val;
+    } spi_mem_pms_ctrl;
+    uint32_t spi_mem_reject_addr;                       /**/
+    union {
+        struct {
+            uint32_t sdio_win_access_en: 1;
+            uint32_t reserved1:         31;
+        };
+        uint32_t val;
+    } sdio_ctrl;
+    union {
+        struct {
+            uint32_t redcy_sig0: 31;
+            uint32_t redcy_andor: 1;
+        };
+        uint32_t val;
+    } redcy_sig0;
+    union {
+        struct {
+            uint32_t redcy_sig1:  31;
+            uint32_t redcy_nandor: 1;
+        };
+        uint32_t val;
+    } redcy_sig1;
+    union {
+        struct {
+            uint32_t agc_mem_force_pu:  1;
+            uint32_t agc_mem_force_pd:  1;
+            uint32_t pbus_mem_force_pu: 1;
+            uint32_t pbus_mem_force_pd: 1;
+            uint32_t dc_mem_force_pu:   1;
+            uint32_t dc_mem_force_pd:   1;
+            uint32_t reserved6:        26;
+        };
+        uint32_t val;
+    } front_end_mem_pd;
+    union {
+        struct {
+            uint32_t retention_link_addr: 27;
+            uint32_t nobypass_cpu_iso_rst: 1;
+            uint32_t reserved28:           4;
+        };
+        uint32_t val;
+    } retention_ctrl;
+    union {
+        struct {
+            uint32_t rom_clkgate_force_on:  2;
+            uint32_t sram_clkgate_force_on: 4;
+            uint32_t reserved6:            26;
+        };
+        uint32_t val;
+    } clkgate_force_on;
+    union {
+        struct {
+            uint32_t rom_power_down:  2;
+            uint32_t sram_power_down: 4;
+            uint32_t reserved6:      26;
+        };
+        uint32_t val;
+    } mem_power_down;
+    union {
+        struct {
+            uint32_t rom_power_up:  2;
+            uint32_t sram_power_up: 4;
+            uint32_t reserved6:    26;
+        };
+        uint32_t val;
+    } mem_power_up;
+    uint32_t rnd_data;                                  /**/
+    union {
+        struct {
+            uint32_t reserved0:               1;
+            uint32_t peri_backup_flow_err:    2;
+            uint32_t reserved3:               1;
+            uint32_t peri_backup_burst_limit: 5;
+            uint32_t peri_backup_tout_thres: 10;
+            uint32_t peri_backup_size:       10;
+            uint32_t peri_backup_start:       1;
+            uint32_t peri_backup_to_mem:      1;
+            uint32_t peri_backup_ena:         1;
+        };
+        uint32_t val;
+    } peri_backup_config;
+    uint32_t peri_backup_addr;                      /**/
+    uint32_t peri_backup_mem_addr;                      /**/
+    union {
+        struct {
+            uint32_t peri_backup_done:         1;
+            uint32_t peri_backup_err:          1;
+            uint32_t reserved2:               30;
+        };
+        uint32_t val;
+    } peri_backup_int_raw;
+    union {
+        struct {
+            uint32_t peri_backup_done:        1;
+            uint32_t peri_backup_err:         1;
+            uint32_t reserved2:              30;
+        };
+        uint32_t val;
+    } peri_backup_int_st;
+    union {
+        struct {
+            uint32_t peri_backup_done:         1;
+            uint32_t peri_backup_err:          1;
+            uint32_t reserved2:               30;
+        };
+        uint32_t val;
+    } peri_backup_int_ena;
+    uint32_t reserved_cc;
+    union {
+        struct {
+            uint32_t peri_backup_done:         1;
+            uint32_t peri_backup_err:          1;
+            uint32_t reserved2:               30;
+        };
+        uint32_t val;
+    } peri_backup_int_clr;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    uint32_t date;                                      /*Version control*/
+} apb_ctrl_dev_t;
+extern apb_ctrl_dev_t APB_CTRL;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_APB_CTRL_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/apb_saradc_reg.h b/components/soc/esp32c3/include/soc/apb_saradc_reg.h
new file mode 100644
index 0000000000..69785ca84d
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/apb_saradc_reg.h
@@ -0,0 +1,631 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_APB_SARADC_REG_H_
+#define _SOC_APB_SARADC_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define APB_SARADC_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x000)
+/* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */
+/*description: wait arbit signal stable after sar_done*/
+#define APB_SARADC_WAIT_ARB_CYCLE  0x00000003
+#define APB_SARADC_WAIT_ARB_CYCLE_M  ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S))
+#define APB_SARADC_WAIT_ARB_CYCLE_V  0x3
+#define APB_SARADC_WAIT_ARB_CYCLE_S  30
+/* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
+/*description: force option to xpd sar blocks*/
+#define APB_SARADC_XPD_SAR_FORCE  0x00000003
+#define APB_SARADC_XPD_SAR_FORCE_M  ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S))
+#define APB_SARADC_XPD_SAR_FORCE_V  0x3
+#define APB_SARADC_XPD_SAR_FORCE_S  27
+/* APB_SARADC_SAR_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
+#define APB_SARADC_SAR_PATT_P_CLEAR  (BIT(23))
+#define APB_SARADC_SAR_PATT_P_CLEAR_M  (BIT(23))
+#define APB_SARADC_SAR_PATT_P_CLEAR_V  0x1
+#define APB_SARADC_SAR_PATT_P_CLEAR_S  23
+/* APB_SARADC_SAR_PATT_LEN : R/W ;bitpos:[17:15] ;default: 3'd7 ; */
+/*description: 0 ~ 15 means length 1 ~ 16*/
+#define APB_SARADC_SAR_PATT_LEN  0x00000007
+#define APB_SARADC_SAR_PATT_LEN_M  ((APB_SARADC_SAR_PATT_LEN_V)<<(APB_SARADC_SAR_PATT_LEN_S))
+#define APB_SARADC_SAR_PATT_LEN_V  0x7
+#define APB_SARADC_SAR_PATT_LEN_S  15
+/* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
+/*description: SAR clock divider*/
+#define APB_SARADC_SAR_CLK_DIV  0x000000FF
+#define APB_SARADC_SAR_CLK_DIV_M  ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S))
+#define APB_SARADC_SAR_CLK_DIV_V  0xFF
+#define APB_SARADC_SAR_CLK_DIV_S  7
+/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define APB_SARADC_SAR_CLK_GATED  (BIT(6))
+#define APB_SARADC_SAR_CLK_GATED_M  (BIT(6))
+#define APB_SARADC_SAR_CLK_GATED_V  0x1
+#define APB_SARADC_SAR_CLK_GATED_S  6
+/* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define APB_SARADC_START  (BIT(1))
+#define APB_SARADC_START_M  (BIT(1))
+#define APB_SARADC_START_V  0x1
+#define APB_SARADC_START_S  1
+/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define APB_SARADC_START_FORCE  (BIT(0))
+#define APB_SARADC_START_FORCE_M  (BIT(0))
+#define APB_SARADC_START_FORCE_V  0x1
+#define APB_SARADC_START_FORCE_S  0
+
+#define APB_SARADC_CTRL2_REG          (DR_REG_APB_SARADC_BASE + 0x004)
+/* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: to enable saradc timer trigger*/
+#define APB_SARADC_TIMER_EN  (BIT(24))
+#define APB_SARADC_TIMER_EN_M  (BIT(24))
+#define APB_SARADC_TIMER_EN_V  0x1
+#define APB_SARADC_TIMER_EN_S  24
+/* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */
+/*description: to set saradc timer target*/
+#define APB_SARADC_TIMER_TARGET  0x00000FFF
+#define APB_SARADC_TIMER_TARGET_M  ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S))
+#define APB_SARADC_TIMER_TARGET_V  0xFFF
+#define APB_SARADC_TIMER_TARGET_S  12
+/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: 1: data to DIG ADC2 CTRL is inverted  otherwise not*/
+#define APB_SARADC_SAR2_INV  (BIT(10))
+#define APB_SARADC_SAR2_INV_M  (BIT(10))
+#define APB_SARADC_SAR2_INV_V  0x1
+#define APB_SARADC_SAR2_INV_S  10
+/* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: 1: data to DIG ADC1 CTRL is inverted  otherwise not*/
+#define APB_SARADC_SAR1_INV  (BIT(9))
+#define APB_SARADC_SAR1_INV_M  (BIT(9))
+#define APB_SARADC_SAR1_INV_V  0x1
+#define APB_SARADC_SAR1_INV_S  9
+/* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
+/*description: max conversion number*/
+#define APB_SARADC_MAX_MEAS_NUM  0x000000FF
+#define APB_SARADC_MAX_MEAS_NUM_M  ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S))
+#define APB_SARADC_MAX_MEAS_NUM_V  0xFF
+#define APB_SARADC_MAX_MEAS_NUM_S  1
+/* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define APB_SARADC_MEAS_NUM_LIMIT  (BIT(0))
+#define APB_SARADC_MEAS_NUM_LIMIT_M  (BIT(0))
+#define APB_SARADC_MEAS_NUM_LIMIT_V  0x1
+#define APB_SARADC_MEAS_NUM_LIMIT_S  0
+
+#define APB_SARADC_FILTER_CTRL1_REG          (DR_REG_APB_SARADC_BASE + 0x008)
+/* APB_SARADC_FILTER_FACTOR0 : R/W ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: */
+#define APB_SARADC_FILTER_FACTOR0  0x00000007
+#define APB_SARADC_FILTER_FACTOR0_M  ((APB_SARADC_FILTER_FACTOR0_V)<<(APB_SARADC_FILTER_FACTOR0_S))
+#define APB_SARADC_FILTER_FACTOR0_V  0x7
+#define APB_SARADC_FILTER_FACTOR0_S  29
+/* APB_SARADC_FILTER_FACTOR1 : R/W ;bitpos:[28:26] ;default: 3'd0 ; */
+/*description: */
+#define APB_SARADC_FILTER_FACTOR1  0x00000007
+#define APB_SARADC_FILTER_FACTOR1_M  ((APB_SARADC_FILTER_FACTOR1_V)<<(APB_SARADC_FILTER_FACTOR1_S))
+#define APB_SARADC_FILTER_FACTOR1_V  0x7
+#define APB_SARADC_FILTER_FACTOR1_S  26
+
+#define APB_SARADC_FSM_WAIT_REG          (DR_REG_APB_SARADC_BASE + 0x00C)
+/* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
+/*description: */
+#define APB_SARADC_STANDBY_WAIT  0x000000FF
+#define APB_SARADC_STANDBY_WAIT_M  ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S))
+#define APB_SARADC_STANDBY_WAIT_V  0xFF
+#define APB_SARADC_STANDBY_WAIT_S  16
+/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
+/*description: */
+#define APB_SARADC_RSTB_WAIT  0x000000FF
+#define APB_SARADC_RSTB_WAIT_M  ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S))
+#define APB_SARADC_RSTB_WAIT_V  0xFF
+#define APB_SARADC_RSTB_WAIT_S  8
+/* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
+/*description: */
+#define APB_SARADC_XPD_WAIT  0x000000FF
+#define APB_SARADC_XPD_WAIT_M  ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S))
+#define APB_SARADC_XPD_WAIT_V  0xFF
+#define APB_SARADC_XPD_WAIT_S  0
+
+#define APB_SARADC_SAR1_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x010)
+/* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: */
+#define APB_SARADC_SAR1_STATUS  0xFFFFFFFF
+#define APB_SARADC_SAR1_STATUS_M  ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S))
+#define APB_SARADC_SAR1_STATUS_V  0xFFFFFFFF
+#define APB_SARADC_SAR1_STATUS_S  0
+
+#define APB_SARADC_SAR2_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x014)
+/* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: */
+#define APB_SARADC_SAR2_STATUS  0xFFFFFFFF
+#define APB_SARADC_SAR2_STATUS_M  ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S))
+#define APB_SARADC_SAR2_STATUS_V  0xFFFFFFFF
+#define APB_SARADC_SAR2_STATUS_S  0
+
+#define APB_SARADC_SAR_PATT_TAB1_REG          (DR_REG_APB_SARADC_BASE + 0x018)
+/* APB_SARADC_SAR_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
+#define APB_SARADC_SAR_PATT_TAB1  0x00FFFFFF
+#define APB_SARADC_SAR_PATT_TAB1_M  ((APB_SARADC_SAR_PATT_TAB1_V)<<(APB_SARADC_SAR_PATT_TAB1_S))
+#define APB_SARADC_SAR_PATT_TAB1_V  0xFFFFFF
+#define APB_SARADC_SAR_PATT_TAB1_S  0
+
+#define APB_SARADC_SAR_PATT_TAB2_REG          (DR_REG_APB_SARADC_BASE + 0x01C)
+/* APB_SARADC_SAR_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
+#define APB_SARADC_SAR_PATT_TAB2  0x00FFFFFF
+#define APB_SARADC_SAR_PATT_TAB2_M  ((APB_SARADC_SAR_PATT_TAB2_V)<<(APB_SARADC_SAR_PATT_TAB2_S))
+#define APB_SARADC_SAR_PATT_TAB2_V  0xFFFFFF
+#define APB_SARADC_SAR_PATT_TAB2_S  0
+
+#define APB_SARADC_ONETIME_SAMPLE_REG          (DR_REG_APB_SARADC_BASE + 0x020)
+/* APB_SARADC1_ONETIME_SAMPLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC1_ONETIME_SAMPLE  (BIT(31))
+#define APB_SARADC1_ONETIME_SAMPLE_M  (BIT(31))
+#define APB_SARADC1_ONETIME_SAMPLE_V  0x1
+#define APB_SARADC1_ONETIME_SAMPLE_S  31
+/* APB_SARADC2_ONETIME_SAMPLE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC2_ONETIME_SAMPLE  (BIT(30))
+#define APB_SARADC2_ONETIME_SAMPLE_M  (BIT(30))
+#define APB_SARADC2_ONETIME_SAMPLE_V  0x1
+#define APB_SARADC2_ONETIME_SAMPLE_S  30
+/* APB_SARADC_ONETIME_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_ONETIME_START  (BIT(29))
+#define APB_SARADC_ONETIME_START_M  (BIT(29))
+#define APB_SARADC_ONETIME_START_V  0x1
+#define APB_SARADC_ONETIME_START_S  29
+/* APB_SARADC_ONETIME_CHANNEL : R/W ;bitpos:[28:25] ;default: 4'd13 ; */
+/*description: */
+#define APB_SARADC_ONETIME_CHANNEL  0x0000000F
+#define APB_SARADC_ONETIME_CHANNEL_M  ((APB_SARADC_ONETIME_CHANNEL_V)<<(APB_SARADC_ONETIME_CHANNEL_S))
+#define APB_SARADC_ONETIME_CHANNEL_V  0xF
+#define APB_SARADC_ONETIME_CHANNEL_S  25
+/* APB_SARADC_ONETIME_ATTEN : R/W ;bitpos:[24:23] ;default: 2'd0 ; */
+/*description: */
+#define APB_SARADC_ONETIME_ATTEN  0x00000003
+#define APB_SARADC_ONETIME_ATTEN_M  ((APB_SARADC_ONETIME_ATTEN_V)<<(APB_SARADC_ONETIME_ATTEN_S))
+#define APB_SARADC_ONETIME_ATTEN_V  0x3
+#define APB_SARADC_ONETIME_ATTEN_S  23
+
+#define APB_SARADC_APB_ADC_ARB_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x024)
+/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: adc2 arbiter uses fixed priority*/
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY  (BIT(12))
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M  (BIT(12))
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V  0x1
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S  12
+/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
+/*description: Set adc2 arbiter wifi priority*/
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY  0x00000003
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M  ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S))
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V  0x3
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S  10
+/* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */
+/*description: Set adc2 arbiter rtc priority*/
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY  0x00000003
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M  ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S))
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V  0x3
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S  8
+/* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Set adc2 arbiterapb priority*/
+#define APB_SARADC_ADC_ARB_APB_PRIORITY  0x00000003
+#define APB_SARADC_ADC_ARB_APB_PRIORITY_M  ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S))
+#define APB_SARADC_ADC_ARB_APB_PRIORITY_V  0x3
+#define APB_SARADC_ADC_ARB_APB_PRIORITY_S  6
+/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: adc2 arbiter force grant*/
+#define APB_SARADC_ADC_ARB_GRANT_FORCE  (BIT(5))
+#define APB_SARADC_ADC_ARB_GRANT_FORCE_M  (BIT(5))
+#define APB_SARADC_ADC_ARB_GRANT_FORCE_V  0x1
+#define APB_SARADC_ADC_ARB_GRANT_FORCE_S  5
+/* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: adc2 arbiter force to enable wifi controller*/
+#define APB_SARADC_ADC_ARB_WIFI_FORCE  (BIT(4))
+#define APB_SARADC_ADC_ARB_WIFI_FORCE_M  (BIT(4))
+#define APB_SARADC_ADC_ARB_WIFI_FORCE_V  0x1
+#define APB_SARADC_ADC_ARB_WIFI_FORCE_S  4
+/* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: adc2 arbiter force to enable rtc controller*/
+#define APB_SARADC_ADC_ARB_RTC_FORCE  (BIT(3))
+#define APB_SARADC_ADC_ARB_RTC_FORCE_M  (BIT(3))
+#define APB_SARADC_ADC_ARB_RTC_FORCE_V  0x1
+#define APB_SARADC_ADC_ARB_RTC_FORCE_S  3
+/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: adc2 arbiter force to enableapb controller*/
+#define APB_SARADC_ADC_ARB_APB_FORCE  (BIT(2))
+#define APB_SARADC_ADC_ARB_APB_FORCE_M  (BIT(2))
+#define APB_SARADC_ADC_ARB_APB_FORCE_V  0x1
+#define APB_SARADC_ADC_ARB_APB_FORCE_S  2
+
+#define APB_SARADC_FILTER_CTRL0_REG          (DR_REG_APB_SARADC_BASE + 0x028)
+/* APB_SARADC_FILTER_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: enable apb_adc1_filter*/
+#define APB_SARADC_FILTER_RESET  (BIT(31))
+#define APB_SARADC_FILTER_RESET_M  (BIT(31))
+#define APB_SARADC_FILTER_RESET_V  0x1
+#define APB_SARADC_FILTER_RESET_S  31
+/* APB_SARADC_FILTER_CHANNEL0 : R/W ;bitpos:[25:22] ;default: 4'd13 ; */
+/*description: apb_adc1_filter_factor*/
+#define APB_SARADC_FILTER_CHANNEL0  0x0000000F
+#define APB_SARADC_FILTER_CHANNEL0_M  ((APB_SARADC_FILTER_CHANNEL0_V)<<(APB_SARADC_FILTER_CHANNEL0_S))
+#define APB_SARADC_FILTER_CHANNEL0_V  0xF
+#define APB_SARADC_FILTER_CHANNEL0_S  22
+/* APB_SARADC_FILTER_CHANNEL1 : R/W ;bitpos:[21:18] ;default: 4'd13 ; */
+/*description: */
+#define APB_SARADC_FILTER_CHANNEL1  0x0000000F
+#define APB_SARADC_FILTER_CHANNEL1_M  ((APB_SARADC_FILTER_CHANNEL1_V)<<(APB_SARADC_FILTER_CHANNEL1_S))
+#define APB_SARADC_FILTER_CHANNEL1_V  0xF
+#define APB_SARADC_FILTER_CHANNEL1_S  18
+
+#define APB_SARADC_1_DATA_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x02C)
+/* APB_SARADC_ADC1_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
+/*description: */
+#define APB_SARADC_ADC1_DATA  0x0001FFFF
+#define APB_SARADC_ADC1_DATA_M  ((APB_SARADC_ADC1_DATA_V)<<(APB_SARADC_ADC1_DATA_S))
+#define APB_SARADC_ADC1_DATA_V  0x1FFFF
+#define APB_SARADC_ADC1_DATA_S  0
+
+#define APB_SARADC_2_DATA_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x030)
+/* APB_SARADC_ADC2_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
+/*description: */
+#define APB_SARADC_ADC2_DATA  0x0001FFFF
+#define APB_SARADC_ADC2_DATA_M  ((APB_SARADC_ADC2_DATA_V)<<(APB_SARADC_ADC2_DATA_S))
+#define APB_SARADC_ADC2_DATA_V  0x1FFFF
+#define APB_SARADC_ADC2_DATA_S  0
+
+#define APB_SARADC_THRES0_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x034)
+/* APB_SARADC_THRES0_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
+/*description: saradc1's thres0 monitor thres*/
+#define APB_SARADC_THRES0_LOW  0x00001FFF
+#define APB_SARADC_THRES0_LOW_M  ((APB_SARADC_THRES0_LOW_V)<<(APB_SARADC_THRES0_LOW_S))
+#define APB_SARADC_THRES0_LOW_V  0x1FFF
+#define APB_SARADC_THRES0_LOW_S  18
+/* APB_SARADC_THRES0_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
+/*description: saradc1's thres0 monitor thres*/
+#define APB_SARADC_THRES0_HIGH  0x00001FFF
+#define APB_SARADC_THRES0_HIGH_M  ((APB_SARADC_THRES0_HIGH_V)<<(APB_SARADC_THRES0_HIGH_S))
+#define APB_SARADC_THRES0_HIGH_V  0x1FFF
+#define APB_SARADC_THRES0_HIGH_S  5
+/* APB_SARADC_THRES0_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */
+/*description: */
+#define APB_SARADC_THRES0_CHANNEL  0x0000000F
+#define APB_SARADC_THRES0_CHANNEL_M  ((APB_SARADC_THRES0_CHANNEL_V)<<(APB_SARADC_THRES0_CHANNEL_S))
+#define APB_SARADC_THRES0_CHANNEL_V  0xF
+#define APB_SARADC_THRES0_CHANNEL_S  0
+
+#define APB_SARADC_THRES1_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x038)
+/* APB_SARADC_THRES1_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
+/*description: saradc1's thres0 monitor thres*/
+#define APB_SARADC_THRES1_LOW  0x00001FFF
+#define APB_SARADC_THRES1_LOW_M  ((APB_SARADC_THRES1_LOW_V)<<(APB_SARADC_THRES1_LOW_S))
+#define APB_SARADC_THRES1_LOW_V  0x1FFF
+#define APB_SARADC_THRES1_LOW_S  18
+/* APB_SARADC_THRES1_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
+/*description: saradc1's thres0 monitor thres*/
+#define APB_SARADC_THRES1_HIGH  0x00001FFF
+#define APB_SARADC_THRES1_HIGH_M  ((APB_SARADC_THRES1_HIGH_V)<<(APB_SARADC_THRES1_HIGH_S))
+#define APB_SARADC_THRES1_HIGH_V  0x1FFF
+#define APB_SARADC_THRES1_HIGH_S  5
+/* APB_SARADC_THRES1_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */
+/*description: */
+#define APB_SARADC_THRES1_CHANNEL  0x0000000F
+#define APB_SARADC_THRES1_CHANNEL_M  ((APB_SARADC_THRES1_CHANNEL_V)<<(APB_SARADC_THRES1_CHANNEL_S))
+#define APB_SARADC_THRES1_CHANNEL_V  0xF
+#define APB_SARADC_THRES1_CHANNEL_S  0
+
+#define APB_SARADC_THRES_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x03C)
+/* APB_SARADC_THRES0_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES0_EN  (BIT(31))
+#define APB_SARADC_THRES0_EN_M  (BIT(31))
+#define APB_SARADC_THRES0_EN_V  0x1
+#define APB_SARADC_THRES0_EN_S  31
+/* APB_SARADC_THRES1_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES1_EN  (BIT(30))
+#define APB_SARADC_THRES1_EN_M  (BIT(30))
+#define APB_SARADC_THRES1_EN_V  0x1
+#define APB_SARADC_THRES1_EN_S  30
+/*description: */
+#define APB_SARADC_THRES_ALL_EN  (BIT(27))
+#define APB_SARADC_THRES_ALL_EN_M  (BIT(27))
+#define APB_SARADC_THRES_ALL_EN_V  0x1
+#define APB_SARADC_THRES_ALL_EN_S  27
+
+#define APB_SARADC_INT_ENA_REG          (DR_REG_APB_SARADC_BASE + 0x040)
+/* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_ADC1_DONE_INT_ENA  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_ENA_M  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_ENA_V  0x1
+#define APB_SARADC_ADC1_DONE_INT_ENA_S  31
+/* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_ADC2_DONE_INT_ENA  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_ENA_M  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_ENA_V  0x1
+#define APB_SARADC_ADC2_DONE_INT_ENA_S  30
+/* APB_SARADC_THRES0_HIGH_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES0_HIGH_INT_ENA  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_ENA_M  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_ENA_V  0x1
+#define APB_SARADC_THRES0_HIGH_INT_ENA_S  29
+/* APB_SARADC_THRES1_HIGH_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES1_HIGH_INT_ENA  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_ENA_M  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_ENA_V  0x1
+#define APB_SARADC_THRES1_HIGH_INT_ENA_S  28
+/* APB_SARADC_THRES0_LOW_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES0_LOW_INT_ENA  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_ENA_M  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_ENA_V  0x1
+#define APB_SARADC_THRES0_LOW_INT_ENA_S  27
+/* APB_SARADC_THRES1_LOW_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES1_LOW_INT_ENA  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_ENA_M  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_ENA_V  0x1
+#define APB_SARADC_THRES1_LOW_INT_ENA_S  26
+
+#define APB_SARADC_INT_RAW_REG          (DR_REG_APB_SARADC_BASE + 0x044)
+/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_ADC1_DONE_INT_RAW  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_RAW_M  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_RAW_V  0x1
+#define APB_SARADC_ADC1_DONE_INT_RAW_S  31
+/* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_ADC2_DONE_INT_RAW  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_RAW_M  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_RAW_V  0x1
+#define APB_SARADC_ADC2_DONE_INT_RAW_S  30
+/* APB_SARADC_THRES0_HIGH_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES0_HIGH_INT_RAW  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_RAW_M  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_RAW_V  0x1
+#define APB_SARADC_THRES0_HIGH_INT_RAW_S  29
+/* APB_SARADC_THRES1_HIGH_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES1_HIGH_INT_RAW  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_RAW_M  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_RAW_V  0x1
+#define APB_SARADC_THRES1_HIGH_INT_RAW_S  28
+/* APB_SARADC_THRES0_LOW_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES0_LOW_INT_RAW  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_RAW_M  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_RAW_V  0x1
+#define APB_SARADC_THRES0_LOW_INT_RAW_S  27
+/* APB_SARADC_THRES1_LOW_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES1_LOW_INT_RAW  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_RAW_M  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_RAW_V  0x1
+#define APB_SARADC_THRES1_LOW_INT_RAW_S  26
+
+#define APB_SARADC_INT_ST_REG          (DR_REG_APB_SARADC_BASE + 0x048)
+/* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_ADC1_DONE_INT_ST  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_ST_M  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_ST_V  0x1
+#define APB_SARADC_ADC1_DONE_INT_ST_S  31
+/* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_ADC2_DONE_INT_ST  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_ST_M  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_ST_V  0x1
+#define APB_SARADC_ADC2_DONE_INT_ST_S  30
+/* APB_SARADC_THRES0_HIGH_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES0_HIGH_INT_ST  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_ST_M  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_ST_V  0x1
+#define APB_SARADC_THRES0_HIGH_INT_ST_S  29
+/* APB_SARADC_THRES1_HIGH_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES1_HIGH_INT_ST  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_ST_M  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_ST_V  0x1
+#define APB_SARADC_THRES1_HIGH_INT_ST_S  28
+/* APB_SARADC_THRES0_LOW_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES0_LOW_INT_ST  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_ST_M  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_ST_V  0x1
+#define APB_SARADC_THRES0_LOW_INT_ST_S  27
+/* APB_SARADC_THRES1_LOW_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES1_LOW_INT_ST  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_ST_M  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_ST_V  0x1
+#define APB_SARADC_THRES1_LOW_INT_ST_S  26
+
+#define APB_SARADC_INT_CLR_REG          (DR_REG_APB_SARADC_BASE + 0x04C)
+/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_ADC1_DONE_INT_CLR  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_CLR_M  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_CLR_V  0x1
+#define APB_SARADC_ADC1_DONE_INT_CLR_S  31
+/* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_ADC2_DONE_INT_CLR  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_CLR_M  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_CLR_V  0x1
+#define APB_SARADC_ADC2_DONE_INT_CLR_S  30
+/* APB_SARADC_THRES0_HIGH_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES0_HIGH_INT_CLR  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_CLR_M  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_CLR_V  0x1
+#define APB_SARADC_THRES0_HIGH_INT_CLR_S  29
+/* APB_SARADC_THRES1_HIGH_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES1_HIGH_INT_CLR  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_CLR_M  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_CLR_V  0x1
+#define APB_SARADC_THRES1_HIGH_INT_CLR_S  28
+/* APB_SARADC_THRES0_LOW_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES0_LOW_INT_CLR  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_CLR_M  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_CLR_V  0x1
+#define APB_SARADC_THRES0_LOW_INT_CLR_S  27
+/* APB_SARADC_THRES1_LOW_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES1_LOW_INT_CLR  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_CLR_M  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_CLR_V  0x1
+#define APB_SARADC_THRES1_LOW_INT_CLR_S  26
+
+#define APB_SARADC_DMA_CONF_REG          (DR_REG_APB_SARADC_BASE + 0x050)
+/* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: enable apb_adc use spi_dma*/
+#define APB_SARADC_APB_ADC_TRANS  (BIT(31))
+#define APB_SARADC_APB_ADC_TRANS_M  (BIT(31))
+#define APB_SARADC_APB_ADC_TRANS_V  0x1
+#define APB_SARADC_APB_ADC_TRANS_S  31
+/* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: reset_apb_adc_state*/
+#define APB_SARADC_APB_ADC_RESET_FSM  (BIT(30))
+#define APB_SARADC_APB_ADC_RESET_FSM_M  (BIT(30))
+#define APB_SARADC_APB_ADC_RESET_FSM_V  0x1
+#define APB_SARADC_APB_ADC_RESET_FSM_S  30
+/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */
+/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num*/
+#define APB_SARADC_APB_ADC_EOF_NUM  0x0000FFFF
+#define APB_SARADC_APB_ADC_EOF_NUM_M  ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S))
+#define APB_SARADC_APB_ADC_EOF_NUM_V  0xFFFF
+#define APB_SARADC_APB_ADC_EOF_NUM_S  0
+
+#define APB_SARADC_APB_ADC_CLKM_CONF_REG          (DR_REG_APB_SARADC_BASE + 0x054)
+/* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */
+/*description: Set this bit to enable clk_apll*/
+#define APB_SARADC_CLK_SEL  0x00000003
+#define APB_SARADC_CLK_SEL_M  ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S))
+#define APB_SARADC_CLK_SEL_V  0x3
+#define APB_SARADC_CLK_SEL_S  21
+/* APB_SARADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: */
+#define APB_SARADC_CLK_EN  (BIT(20))
+#define APB_SARADC_CLK_EN_M  (BIT(20))
+#define APB_SARADC_CLK_EN_V  0x1
+#define APB_SARADC_CLK_EN_S  20
+/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */
+/*description: Fractional clock divider denominator value*/
+#define APB_SARADC_CLKM_DIV_A  0x0000003F
+#define APB_SARADC_CLKM_DIV_A_M  ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S))
+#define APB_SARADC_CLKM_DIV_A_V  0x3F
+#define APB_SARADC_CLKM_DIV_A_S  14
+/* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */
+/*description: Fractional clock divider numerator value*/
+#define APB_SARADC_CLKM_DIV_B  0x0000003F
+#define APB_SARADC_CLKM_DIV_B_M  ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S))
+#define APB_SARADC_CLKM_DIV_B_V  0x3F
+#define APB_SARADC_CLKM_DIV_B_S  8
+/* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */
+/*description: Integral I2S clock divider value*/
+#define APB_SARADC_CLKM_DIV_NUM  0x000000FF
+#define APB_SARADC_CLKM_DIV_NUM_M  ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S))
+#define APB_SARADC_CLKM_DIV_NUM_V  0xFF
+#define APB_SARADC_CLKM_DIV_NUM_S  0
+
+#define APB_SARADC_APB_TSENS_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x058)
+/* APB_SARADC_TSENS_PU : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_TSENS_PU  (BIT(22))
+#define APB_SARADC_TSENS_PU_M  (BIT(22))
+#define APB_SARADC_TSENS_PU_V  0x1
+#define APB_SARADC_TSENS_PU_S  22
+/* APB_SARADC_TSENS_CLK_DIV : R/W ;bitpos:[21:14] ;default: 8'd6 ; */
+/*description: */
+#define APB_SARADC_TSENS_CLK_DIV  0x000000FF
+#define APB_SARADC_TSENS_CLK_DIV_M  ((APB_SARADC_TSENS_CLK_DIV_V)<<(APB_SARADC_TSENS_CLK_DIV_S))
+#define APB_SARADC_TSENS_CLK_DIV_V  0xFF
+#define APB_SARADC_TSENS_CLK_DIV_S  14
+/* APB_SARADC_TSENS_IN_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_TSENS_IN_INV  (BIT(13))
+#define APB_SARADC_TSENS_IN_INV_M  (BIT(13))
+#define APB_SARADC_TSENS_IN_INV_V  0x1
+#define APB_SARADC_TSENS_IN_INV_S  13
+/* APB_SARADC_TSENS_OUT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define APB_SARADC_TSENS_OUT  0x000000FF
+#define APB_SARADC_TSENS_OUT_M  ((APB_SARADC_TSENS_OUT_V)<<(APB_SARADC_TSENS_OUT_S))
+#define APB_SARADC_TSENS_OUT_V  0xFF
+#define APB_SARADC_TSENS_OUT_S  0
+
+#define APB_SARADC_APB_TSENS_CTRL2_REG          (DR_REG_APB_SARADC_BASE + 0x05C)
+/* APB_SARADC_TSENS_CLK_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_TSENS_CLK_SEL  (BIT(15))
+#define APB_SARADC_TSENS_CLK_SEL_M  (BIT(15))
+#define APB_SARADC_TSENS_CLK_SEL_V  0x1
+#define APB_SARADC_TSENS_CLK_SEL_S  15
+/* APB_SARADC_TSENS_CLK_INV : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: */
+#define APB_SARADC_TSENS_CLK_INV  (BIT(14))
+#define APB_SARADC_TSENS_CLK_INV_M  (BIT(14))
+#define APB_SARADC_TSENS_CLK_INV_V  0x1
+#define APB_SARADC_TSENS_CLK_INV_S  14
+/* APB_SARADC_TSENS_XPD_FORCE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: */
+#define APB_SARADC_TSENS_XPD_FORCE  0x00000003
+#define APB_SARADC_TSENS_XPD_FORCE_M  ((APB_SARADC_TSENS_XPD_FORCE_V)<<(APB_SARADC_TSENS_XPD_FORCE_S))
+#define APB_SARADC_TSENS_XPD_FORCE_V  0x3
+#define APB_SARADC_TSENS_XPD_FORCE_S  12
+/* APB_SARADC_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */
+/*description: */
+#define APB_SARADC_TSENS_XPD_WAIT  0x00000FFF
+#define APB_SARADC_TSENS_XPD_WAIT_M  ((APB_SARADC_TSENS_XPD_WAIT_V)<<(APB_SARADC_TSENS_XPD_WAIT_S))
+#define APB_SARADC_TSENS_XPD_WAIT_V  0xFFF
+#define APB_SARADC_TSENS_XPD_WAIT_S  0
+
+#define APB_SARADC_CALI_REG          (DR_REG_APB_SARADC_BASE + 0x060)
+/* APB_SARADC_CALI_CFG : R/W ;bitpos:[16:0] ;default: 17'h8000 ; */
+/*description: */
+#define APB_SARADC_CALI_CFG  0x0001FFFF
+#define APB_SARADC_CALI_CFG_M  ((APB_SARADC_CALI_CFG_V)<<(APB_SARADC_CALI_CFG_S))
+#define APB_SARADC_CALI_CFG_V  0x1FFFF
+#define APB_SARADC_CALI_CFG_S  0
+
+#define APB_SARADC_APB_CTRL_DATE_REG          (DR_REG_APB_SARADC_BASE + 0x3fc)
+/* APB_SARADC_DATE : R/W ;bitpos:[31:0] ;default: 32'h02007171 ; */
+/*description: */
+#define APB_SARADC_DATE  0xFFFFFFFF
+#define APB_SARADC_DATE_M  ((APB_SARADC_DATE_V)<<(APB_SARADC_DATE_S))
+#define APB_SARADC_DATE_V  0xFFFFFFFF
+#define APB_SARADC_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_APB_SARADC_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/apb_saradc_struct.h b/components/soc/esp32c3/include/soc/apb_saradc_struct.h
new file mode 100644
index 0000000000..c3ea73f150
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/apb_saradc_struct.h
@@ -0,0 +1,490 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_APB_SARADC_STRUCT_H_
+#define _SOC_APB_SARADC_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t start_force:             1;
+            uint32_t start:                   1;
+            uint32_t reserved2:               4;              /*0: single mode  1: double mode  2: alternate mode*/
+            uint32_t sar_clk_gated:           1;
+            uint32_t sar_clk_div:             8;              /*SAR clock divider*/
+            uint32_t sar_patt_len:            3;              /*0 ~ 15 means length 1 ~ 16*/
+            uint32_t reserved18:              5;
+            uint32_t sar_patt_p_clear:        1;              /*clear the pointer of pattern table for DIG ADC1 CTRL*/
+            uint32_t reserved24:              3;
+            uint32_t xpd_sar_force:           2;              /*force option to xpd sar blocks*/
+            uint32_t reserved29:              1;
+            uint32_t wait_arb_cycle:          2;              /*wait arbit signal stable after sar_done*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t meas_num_limit:        1;
+            uint32_t max_meas_num:          8;                /*max conversion number*/
+            uint32_t sar1_inv:              1;                /*1: data to DIG ADC1 CTRL is inverted  otherwise not*/
+            uint32_t sar2_inv:              1;                /*1: data to DIG ADC2 CTRL is inverted  otherwise not*/
+            uint32_t reserved11:            1;                /*1: select saradc timer 0: i2s_ws trigger*/
+            uint32_t timer_target:         12;                /*to set saradc timer target*/
+            uint32_t timer_en:              1;                /*to enable saradc timer trigger*/
+            uint32_t reserved25:            7;
+        };
+        uint32_t val;
+    } ctrl2;
+    union {
+        struct {
+            uint32_t reserved0:     26;
+            uint32_t filter_factor1: 3;
+            uint32_t filter_factor0: 3;
+        };
+        uint32_t val;
+    } filter_ctrl1;
+    union {
+        struct {
+            uint32_t xpd_wait:            8;
+            uint32_t rstb_wait:           8;
+            uint32_t standby_wait:        8;
+            uint32_t reserved24:          8;
+        };
+        uint32_t val;
+    } fsm_wait;
+    uint32_t sar1_status;                                     /**/
+    uint32_t sar2_status;                                     /**/
+    union {
+        struct {
+            uint32_t sar_patt_tab1:       24;                 /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
+            uint32_t reserved24:           8;
+        };
+        uint32_t val;
+    } sar_patt_tab[2];
+    union {
+        struct {
+            uint32_t reserved0:             23;
+            uint32_t onetime_atten:          2;
+            uint32_t onetime_channel:        4;
+            uint32_t onetime_start:          1;
+            uint32_t adc2_onetime_sample:    1;
+            uint32_t adc1_onetime_sample:    1;
+        };
+        uint32_t val;
+    } onetime_sample;
+    union {
+        struct {
+            uint32_t reserved0:             2;
+            uint32_t adc_arb_apb_force:     1;                /*adc2 arbiter force to enableapb controller*/
+            uint32_t adc_arb_rtc_force:     1;                /*adc2 arbiter force to enable rtc controller*/
+            uint32_t adc_arb_wifi_force:    1;                /*adc2 arbiter force to enable wifi controller*/
+            uint32_t adc_arb_grant_force:   1;                /*adc2 arbiter force grant*/
+            uint32_t adc_arb_apb_priority:  2;                /*Set adc2 arbiterapb priority*/
+            uint32_t adc_arb_rtc_priority:  2;                /*Set adc2 arbiter rtc priority*/
+            uint32_t adc_arb_wifi_priority: 2;                /*Set adc2 arbiter wifi priority*/
+            uint32_t adc_arb_fix_priority:  1;                /*adc2 arbiter uses fixed priority*/
+            uint32_t reserved13:           19;
+        };
+        uint32_t val;
+    } apb_adc_arb_ctrl;
+    union {
+        struct {
+            uint32_t reserved0:      18;
+            uint32_t filter_channel1: 4;
+            uint32_t filter_channel0: 4;                      /*apb_adc1_filter_factor*/
+            uint32_t reserved26:      5;
+            uint32_t filter_reset:    1;                      /*enable apb_adc1_filter*/
+        };
+        uint32_t val;
+    } filter_ctrl0;
+    union {
+        struct {
+            uint32_t adc1_data: 17;
+            uint32_t reserved17:15;
+        };
+        uint32_t val;
+    } apb_saradc1_data_status;
+    union {
+        struct {
+            uint32_t adc2_data: 17;
+            uint32_t reserved17:15;
+        };
+        uint32_t val;
+    } apb_saradc2_data_status;
+    union {
+        struct {
+            uint32_t thres0_channel: 4;
+            uint32_t reserved4:      1;
+            uint32_t thres0_high:   13;                       /*saradc1's thres0 monitor thres*/
+            uint32_t thres0_low:    13;                       /*saradc1's thres0 monitor thres*/
+            uint32_t reserved31:     1;
+        };
+        uint32_t val;
+    } thres0_ctrl;
+    union {
+        struct {
+            uint32_t thres1_channel: 4;
+            uint32_t reserved4:      1;
+            uint32_t thres1_high:   13;                       /*saradc1's thres0 monitor thres*/
+            uint32_t thres1_low:    13;                       /*saradc1's thres0 monitor thres*/
+            uint32_t reserved31:     1;
+        };
+        uint32_t val;
+    } thres1_ctrl;
+    union {
+        struct {
+            uint32_t reserved0:   27;
+            uint32_t thres_all_en: 1;
+            uint32_t reserved28:   2;
+            uint32_t thres1_en:    1;
+            uint32_t thres0_en:    1;
+        };
+        uint32_t val;
+    } thres_ctrl;
+    union {
+        struct {
+            uint32_t reserved0:          26;
+            uint32_t thres1_low:          1;
+            uint32_t thres0_low:          1;
+            uint32_t thres1_high:         1;
+            uint32_t thres0_high:         1;
+            uint32_t adc2_done:           1;
+            uint32_t adc1_done:           1;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t reserved0:          26;
+            uint32_t thres1_low:          1;
+            uint32_t thres0_low:          1;
+            uint32_t thres1_high:         1;
+            uint32_t thres0_high:         1;
+            uint32_t adc2_done:           1;
+            uint32_t adc1_done:           1;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t reserved0:         26;
+            uint32_t thres1_low:         1;
+            uint32_t thres0_low:         1;
+            uint32_t thres1_high:        1;
+            uint32_t thres0_high:        1;
+            uint32_t adc2_done:          1;
+            uint32_t adc1_done:          1;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t reserved0:          26;
+            uint32_t thres1_low:          1;
+            uint32_t thres0_low:          1;
+            uint32_t thres1_high:         1;
+            uint32_t thres0_high:         1;
+            uint32_t adc2_done:           1;
+            uint32_t adc1_done:           1;
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t apb_adc_eof_num:  16;                    /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/
+            uint32_t reserved16:       14;
+            uint32_t apb_adc_reset_fsm: 1;                    /*reset_apb_adc_state*/
+            uint32_t apb_adc_trans:     1;                    /*enable apb_adc use spi_dma*/
+        };
+        uint32_t val;
+    } dma_conf;
+    union {
+        struct {
+            uint32_t clkm_div_num: 8;                         /*Integral I2S clock divider value*/
+            uint32_t clkm_div_b:   6;                         /*Fractional clock divider numerator value*/
+            uint32_t clkm_div_a:   6;                         /*Fractional clock divider denominator value*/
+            uint32_t clk_en:       1;
+            uint32_t clk_sel:      2;                         /*Set this bit to enable clk_apll*/
+            uint32_t reserved23:   9;
+        };
+        uint32_t val;
+    } apb_adc_clkm_conf;
+    union {
+        struct {
+            uint32_t tsens_out:     8;
+            uint32_t reserved8:     5;
+            uint32_t tsens_in_inv:  1;
+            uint32_t tsens_clk_div: 8;
+            uint32_t tsens_pu:      1;
+            uint32_t reserved23:    9;
+        };
+        uint32_t val;
+    } apb_tsens_ctrl;
+    union {
+        struct {
+            uint32_t tsens_xpd_wait: 12;
+            uint32_t tsens_xpd_force: 2;
+            uint32_t tsens_clk_inv:   1;
+            uint32_t tsens_clk_sel:   1;
+            uint32_t reserved16:     16;
+        };
+        uint32_t val;
+    } apb_tsens_ctrl2;
+    union {
+        struct {
+            uint32_t cali_cfg:  17;
+            uint32_t reserved17:15;
+        };
+        uint32_t val;
+    } cali;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    uint32_t apb_ctrl_date;                                   /**/
+} apb_saradc_dev_t;
+extern apb_saradc_dev_t APB_SARADC;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_APB_SARADC_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/assist_debug_reg.h b/components/soc/esp32c3/include/soc/assist_debug_reg.h
new file mode 100644
index 0000000000..a0c1e9c9d8
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/assist_debug_reg.h
@@ -0,0 +1,691 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_ASSIST_DEBUG_REG_H_
+#define _SOC_ASSIST_DEBUG_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x000)
+/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S  11
+/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S  10
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  9
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  8
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S  7
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S  6
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S  5
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S  4
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
+
+#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x004)
+/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S  11
+/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S  10
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  9
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  8
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S  7
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S  6
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S  5
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S  4
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
+
+#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x008)
+/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S  11
+/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S  10
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S  9
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S  8
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S  7
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S  6
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S  5
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S  4
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S  3
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S  2
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S  1
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S  0
+
+#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x00C)
+/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S  11
+/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S  10
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  9
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  8
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S  7
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S  6
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S  5
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S  4
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x010)
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x014)
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x018)
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x01C)
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x020)
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x024)
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x028)
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x02C)
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x030)
+/* ASSIST_DEBUG_CORE_0_AREA_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PC  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PC_M  ((ASSIST_DEBUG_CORE_0_AREA_PC_V)<<(ASSIST_DEBUG_CORE_0_AREA_PC_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PC_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_SP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x034)
+/* ASSIST_DEBUG_CORE_0_AREA_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_SP  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_SP_M  ((ASSIST_DEBUG_CORE_0_AREA_SP_V)<<(ASSIST_DEBUG_CORE_0_AREA_SP_S))
+#define ASSIST_DEBUG_CORE_0_AREA_SP_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_SP_S  0
+
+#define ASSIST_DEBUG_CORE_0_SP_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x038)
+/* ASSIST_DEBUG_CORE_0_SP_MIN : RW ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_MIN  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_MIN_M  ((ASSIST_DEBUG_CORE_0_SP_MIN_V)<<(ASSIST_DEBUG_CORE_0_SP_MIN_S))
+#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_0_SP_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x03C)
+/* ASSIST_DEBUG_CORE_0_SP_MAX : RW ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_MAX  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_MAX_M  ((ASSIST_DEBUG_CORE_0_SP_MAX_V)<<(ASSIST_DEBUG_CORE_0_SP_MAX_S))
+#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_0_SP_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x040)
+/* ASSIST_DEBUG_CORE_0_SP_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_PC  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_PC_M  ((ASSIST_DEBUG_CORE_0_SP_PC_V)<<(ASSIST_DEBUG_CORE_0_SP_PC_S))
+#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
+
+#define ASSIST_DEBUG_CORE_0_RCD_EN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x044)
+/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : RW ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable CPU Pdebug function  if enable  CPU will update PdebugPC*/
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V  0x1
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
+/* ASSIST_DEBUG_CORE_0_RCD_RECORDEN : RW ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable recording function  if enable  assist_debug will update
+ PdebugPC  so you can read it*/
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V  0x1
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S  0
+
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x048)
+/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
+
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x04C)
+/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S  0
+
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x050)
+/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0  (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M  (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S  25
+/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S  24
+/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0  0x00FFFFFF
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V  0xFFFFFF
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S  0
+
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x054)
+/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1  (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M  (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S  25
+/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S  24
+/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1  0x00FFFFFF
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V  0xFFFFFF
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S  0
+
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x058)
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO ;bitpos:[28:25] ;default: 4'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0  0x0000000F
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V  0xF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S  25
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S  24
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0  0x00FFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V  0xFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S  0
+
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x05C)
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S  0
+
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x060)
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO ;bitpos:[28:25] ;default: 4'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1  0x0000000F
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V  0xF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S  25
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S  24
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1  0x00FFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V  0xFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S  0
+
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x064)
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S  0
+
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x068)
+/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0  0x000FFFFF
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M  ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S))
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V  0xFFFFF
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S  0
+
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x06C)
+/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1  0x000FFFFF
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M  ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S))
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V  0xFFFFF
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S  0
+
+#define ASSIST_DEBUG_LOG_SETTING_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x070)
+/* ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE  (BIT(7))
+#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M  (BIT(7))
+#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V  0x1
+#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S  7
+/* ASSIST_DEBUG_LOG_MODE : R/W ;bitpos:[6:3] ;default: 4'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_MODE  0x0000000F
+#define ASSIST_DEBUG_LOG_MODE_M  ((ASSIST_DEBUG_LOG_MODE_V)<<(ASSIST_DEBUG_LOG_MODE_S))
+#define ASSIST_DEBUG_LOG_MODE_V  0xF
+#define ASSIST_DEBUG_LOG_MODE_S  3
+/* ASSIST_DEBUG_LOG_ENA : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_ENA  0x00000007
+#define ASSIST_DEBUG_LOG_ENA_M  ((ASSIST_DEBUG_LOG_ENA_V)<<(ASSIST_DEBUG_LOG_ENA_S))
+#define ASSIST_DEBUG_LOG_ENA_V  0x7
+#define ASSIST_DEBUG_LOG_ENA_S  0
+
+#define ASSIST_DEBUG_LOG_DATA_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x074)
+/* ASSIST_DEBUG_LOG_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_DATA_0  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_0_M  ((ASSIST_DEBUG_LOG_DATA_0_V)<<(ASSIST_DEBUG_LOG_DATA_0_S))
+#define ASSIST_DEBUG_LOG_DATA_0_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_0_S  0
+
+#define ASSIST_DEBUG_LOG_DATA_MASK_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x078)
+/* ASSIST_DEBUG_LOG_DATA_SIZE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_DATA_SIZE  0x0000FFFF
+#define ASSIST_DEBUG_LOG_DATA_SIZE_M  ((ASSIST_DEBUG_LOG_DATA_SIZE_V)<<(ASSIST_DEBUG_LOG_DATA_SIZE_S))
+#define ASSIST_DEBUG_LOG_DATA_SIZE_V  0xFFFF
+#define ASSIST_DEBUG_LOG_DATA_SIZE_S  0
+
+#define ASSIST_DEBUG_LOG_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x07C)
+/* ASSIST_DEBUG_LOG_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_MIN  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MIN_M  ((ASSIST_DEBUG_LOG_MIN_V)<<(ASSIST_DEBUG_LOG_MIN_S))
+#define ASSIST_DEBUG_LOG_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MIN_S  0
+
+#define ASSIST_DEBUG_LOG_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x080)
+/* ASSIST_DEBUG_LOG_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_MAX  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MAX_M  ((ASSIST_DEBUG_LOG_MAX_V)<<(ASSIST_DEBUG_LOG_MAX_S))
+#define ASSIST_DEBUG_LOG_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MAX_S  0
+
+#define ASSIST_DEBUG_LOG_MEM_START_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x084)
+/* ASSIST_DEBUG_LOG_MEM_START : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_MEM_START  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_START_M  ((ASSIST_DEBUG_LOG_MEM_START_V)<<(ASSIST_DEBUG_LOG_MEM_START_S))
+#define ASSIST_DEBUG_LOG_MEM_START_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_START_S  0
+
+#define ASSIST_DEBUG_LOG_MEM_END_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x088)
+/* ASSIST_DEBUG_LOG_MEM_END : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_MEM_END  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_END_M  ((ASSIST_DEBUG_LOG_MEM_END_V)<<(ASSIST_DEBUG_LOG_MEM_END_S))
+#define ASSIST_DEBUG_LOG_MEM_END_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_END_S  0
+
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x08C)
+/* ASSIST_DEBUG_LOG_MEM_WRITING_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_M  ((ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V)<<(ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S))
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S  0
+
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x090)
+/* ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG  (BIT(1))
+#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_M  (BIT(1))
+#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_V  0x1
+#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_S  1
+/* ASSIST_DEBUG_LOG_MEM_FULL_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG  (BIT(0))
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M  (BIT(0))
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V  0x1
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S  0
+
+#define ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x094)
+/* ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M  ((ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V)<<(ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S))
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S  0
+
+#define ASSIST_DEBUG_C0RE_0_DEBUG_MODE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x098)
+/* ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V  0x1
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S  1
+/* ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V  0x1
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S  0
+
+#define ASSIST_DEBUG_DATE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x1FC)
+/* ASSIST_DEBUG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2008010 ; */
+/*description: */
+#define ASSIST_DEBUG_DATE  0x0FFFFFFF
+#define ASSIST_DEBUG_DATE_M  ((ASSIST_DEBUG_DATE_V)<<(ASSIST_DEBUG_DATE_S))
+#define ASSIST_DEBUG_DATE_V  0xFFFFFFF
+#define ASSIST_DEBUG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_ASSIST_DEBUG_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/boot_mode.h b/components/soc/esp32c3/include/soc/boot_mode.h
new file mode 100644
index 0000000000..648d0a4386
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/boot_mode.h
@@ -0,0 +1,101 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_BOOT_MODE_H_
+#define _SOC_BOOT_MODE_H_
+
+#include "soc.h"
+
+/*SPI Boot*/
+#define IS_1XXX(v)                              (((v)&0x08)==0x08)
+
+/*Download Boot, SPI(or SDIO_V2)/UART0*/
+#define IS_00XX(v)                              (((v)&0x0c)==0x00)
+
+/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
+#define IS_0000(v)                              (((v)&0x0f)==0x00)
+
+/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/
+#define IS_0001(v)                              (((v)&0x0f)==0x01)
+
+/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
+#define IS_0010(v)                              (((v)&0x0f)==0x02)
+
+/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/
+#define IS_0011(v)                              (((v)&0x0f)==0x03)
+
+/*legacy SPI Boot*/
+#define IS_0100(v)                              (((v)&0x0f)==0x04)
+
+/*ATE/ANALOG Mode*/
+#define IS_0101(v)                              (((v)&0x0f)==0x05)
+
+/*SPI(or SDIO_V1) download Mode*/
+#define IS_0110(v)                              (((v)&0x0f)==0x06)
+
+/*Diagnostic Mode+UART0 download Mode*/
+#define IS_0111(v)                              (((v)&0x0f)==0x07)
+
+
+
+#define BOOT_MODE_GET()                         (GPIO_REG_READ(GPIO_STRAP_REG))
+
+/*do not include download mode*/
+#define ETS_IS_UART_BOOT()                      IS_0111(BOOT_MODE_GET())
+
+/*all spi boot including spi/legacy*/
+#define ETS_IS_FLASH_BOOT()                     (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET()))
+
+/*all faster spi boot including spi*/
+#define ETS_IS_FAST_FLASH_BOOT()                IS_1XXX(BOOT_MODE_GET())
+
+#if SUPPORT_SDIO_DOWNLOAD
+
+/*all sdio V2 of failing edge input, failing edge output*/
+#define ETS_IS_SDIO_FEI_FEO_V2_BOOT()           IS_0000(BOOT_MODE_GET())
+
+/*all sdio V2 of failing edge input, raising edge output*/
+#define ETS_IS_SDIO_FEI_REO_V2_BOOT()           IS_0001(BOOT_MODE_GET())
+
+/*all sdio V2 of raising edge input, failing edge output*/
+#define ETS_IS_SDIO_REI_FEO_V2_BOOT()           IS_0010(BOOT_MODE_GET())
+
+/*all sdio V2 of raising edge input, raising edge output*/
+#define ETS_IS_SDIO_REI_REO_V2_BOOT()           IS_0011(BOOT_MODE_GET())
+
+/*all sdio V1 of raising edge input, failing edge output*/
+#define ETS_IS_SDIO_REI_FEO_V1_BOOT()           IS_0110(BOOT_MODE_GET())
+
+/*do not include joint download mode*/
+#define ETS_IS_SDIO_BOOT()                      IS_0110(BOOT_MODE_GET())
+#else
+
+/*do not include joint download mode*/
+#define ETS_IS_SPI_DOWNLOAD_BOOT()              IS_0110(BOOT_MODE_GET())
+
+#endif
+
+/*joint download boot*/
+#define ETS_IS_JOINT_DOWNLOAD_BOOT()                  IS_00XX(BOOT_MODE_GET())
+
+/*ATE mode*/
+#define ETS_IS_ATE_BOOT()                       IS_0101(BOOT_MODE_GET())
+
+/*used by  ETS_IS_SDIO_UART_BOOT*/
+#define SEL_NO_BOOT                             0
+#define SEL_SDIO_BOOT                           BIT0
+#define SEL_UART_BOOT                           BIT1
+#define SEL_SPI_SLAVE_BOOT                      BIT2
+
+#endif /* _SOC_BOOT_MODE_H_ */
diff --git a/components/soc/esp32c3/include/soc/brownout_caps.h b/components/soc/esp32c3/include/soc/brownout_caps.h
new file mode 100644
index 0000000000..797d33ebb9
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/brownout_caps.h
@@ -0,0 +1,25 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SOC_BROWNOUT_RESET_SUPPORTED 1
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/include/soc/cache_memory.h b/components/soc/esp32c3/include/soc/cache_memory.h
new file mode 100644
index 0000000000..db558c4e50
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/cache_memory.h
@@ -0,0 +1,100 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _CACHE_MEMORY_H_
+#define _CACHE_MEMORY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*IRAM0 is connected with Cache IBUS0*/
+#define IRAM0_ADDRESS_LOW               0x40000000
+#define IRAM0_ADDRESS_HIGH              0x44000000
+#define IRAM0_CACHE_ADDRESS_LOW	        0x42000000
+#define IRAM0_CACHE_ADDRESS_HIGH        0x42800000
+
+/*DRAM0 is connected with Cache DBUS0*/
+#define DRAM0_ADDRESS_LOW               0x3C000000
+#define DRAM0_ADDRESS_HIGH              0x40000000
+#define DRAM0_CACHE_ADDRESS_LOW         0x3C000000
+#define DRAM0_CACHE_ADDRESS_HIGH        0x3C800000
+#define DRAM0_CACHE_OPERATION_HIGH      DRAM0_CACHE_ADDRESS_HIGH
+#define ESP_CACHE_TEMP_ADDR             0x3C000000
+
+#define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
+#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
+
+#define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
+#define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
+#define ADDRESS_IN_DRAM0(vaddr)            ADDRESS_IN_BUS(DRAM0, vaddr)
+#define ADDRESS_IN_DRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
+
+#define BUS_IRAM0_CACHE_SIZE              BUS_SIZE(IRAM0_CACHE)
+#define BUS_DRAM0_CACHE_SIZE              BUS_SIZE(DRAM0_CACHE)
+
+#define CACHE_IBUS                      0
+#define CACHE_IBUS_MMU_START            0
+#define CACHE_IBUS_MMU_END              0x200
+
+#define CACHE_DBUS                      1
+#define CACHE_DBUS_MMU_START            0
+#define CACHE_DBUS_MMU_END              0x200
+
+#define CACHE_IROM_MMU_START            0
+#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
+#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
+
+#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
+#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
+#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
+
+#define CACHE_DROM_MMU_MAX_END          0x200
+
+#define ICACHE_MMU_SIZE                 0x200
+#define DCACHE_MMU_SIZE                 0x200
+
+#define MMU_BUS_START(i)                0
+#define MMU_BUS_SIZE(i)                 0x200
+
+#define MMU_INVALID                     BIT(8)
+#define MMU_TYPE                        0
+#define MMU_ACCESS_FLASH                0
+
+#define CACHE_MAX_SYNC_NUM 0x400000
+#define CACHE_MAX_LOCK_NUM 0x8000
+
+#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
+#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
+
+#define MMU_TABLE_INVALID_VAL 0x100
+#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
+#define MMU_ADDRESS_MASK 0xff
+#define MMU_PAGE_SIZE 0x10000
+#define INVALID_PHY_PAGE 0xffff
+
+#define BUS_ADDR_SIZE 0x800000
+#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
+
+#define CACHE_ICACHE_LOW_SHIFT         0
+#define CACHE_ICACHE_HIGH_SHIFT        2
+#define CACHE_DCACHE_LOW_SHIFT         4
+#define CACHE_DCACHE_HIGH_SHIFT        6
+
+#define CACHE_MEMORY_IBANK0_ADDR        0x4037c000
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_CACHE_MEMORY_H_ */
diff --git a/components/soc/esp32c3/include/soc/cpu_caps.h b/components/soc/esp32c3/include/soc/cpu_caps.h
new file mode 100644
index 0000000000..e8692efc29
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/cpu_caps.h
@@ -0,0 +1,20 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#define SOC_CPU_BREAKPOINTS_NUM         8
+#define SOC_CPU_WATCHPOINTS_NUM         8
+
+#define SOC_CPU_WATCHPOINT_SIZE         0x80000000 // bytes
diff --git a/components/soc/esp32c3/include/soc/dac_caps.h b/components/soc/esp32c3/include/soc/dac_caps.h
new file mode 100644
index 0000000000..cad2a48daf
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/dac_caps.h
@@ -0,0 +1,20 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_RTC_DAC_CAPS_H_
+#define _SOC_RTC_DAC_CAPS_H_
+
+#define SOC_DAC_PERIPH_NUM      0
+
+#endif
diff --git a/components/soc/esp32c3/include/soc/dport_access.h b/components/soc/esp32c3/include/soc/dport_access.h
new file mode 100644
index 0000000000..e6dfa2bec0
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/dport_access.h
@@ -0,0 +1,111 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DPORT_ACCESS_H_
+#define _DPORT_ACCESS_H_
+
+#include <stdint.h>
+#include "esp_attr.h"
+#include "esp_attr.h"
+#include "esp32c3/dport_access.h"
+#include "soc.h"
+#include "uart_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions
+
+// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent.
+#define _DPORT_REG_READ(_r)        (*(volatile uint32_t *)(_r))
+#define _DPORT_REG_WRITE(_r, _v)   (*(volatile uint32_t *)(_r)) = (_v)
+
+// Write value to DPORT register (does not require protecting)
+#define DPORT_REG_WRITE(_r, _v)   _DPORT_REG_WRITE((_r), (_v))
+
+#define DPORT_REG_READ(_r)    _DPORT_REG_READ(_r)
+#define DPORT_SEQUENCE_REG_READ(_r)    _DPORT_REG_READ(_r)
+
+//get bit or get bits from register
+#define DPORT_REG_GET_BIT(_r, _b)  (DPORT_REG_READ(_r) & (_b))
+
+//set bit or set bits to register
+#define DPORT_REG_SET_BIT(_r, _b)  DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
+
+//clear bit or clear bits of register
+#define DPORT_REG_CLR_BIT(_r, _b)  DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
+
+//set bits of register controlled by mask
+#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
+
+//get field from register, uses field _S & _V to determine mask
+#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
+
+//set field to register, used when _f is not left shifted by _f##_S
+#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S))))
+
+//get field value from a variable, used when _f is not left shifted by _f##_S
+#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
+
+//get field value from a variable, used when _f is left shifted by _f##_S
+#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
+
+//set field value to a variable, used when _f is not left shifted by _f##_S
+#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
+
+//set field value to a variable, used when _f is left shifted by _f##_S
+#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
+
+//generate a value from a field value, used when _f is not left shifted by _f##_S
+#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
+
+//generate a value from a field value, used when _f is left shifted by _f##_S
+#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
+
+//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
+#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
+#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
+#define _DPORT_REG_SET_BIT(_r, _b)  _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
+#define _DPORT_REG_CLR_BIT(_r, _b)  _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
+
+#define DPORT_READ_PERI_REG(addr)       _DPORT_READ_PERI_REG(addr)
+
+//write value to register
+#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
+
+//clear bits of register controlled by mask
+#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
+
+//set bits of register controlled by mask
+#define DPORT_SET_PERI_REG_MASK(reg, mask)   DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
+
+//get bits of register controlled by mask
+#define DPORT_GET_PERI_REG_MASK(reg, mask)   (DPORT_READ_PERI_REG(reg) & (mask))
+
+//get bits of register controlled by highest bit and lowest bit
+#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos)     ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
+
+//set bits of register controlled by mask and shift
+#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
+
+//get field of register
+#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift)      ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
+//}}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DPORT_ACCESS_H_ */
diff --git a/components/soc/esp32c3/include/soc/efuse_reg.h b/components/soc/esp32c3/include/soc/efuse_reg.h
new file mode 100644
index 0000000000..cabb2428a4
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/efuse_reg.h
@@ -0,0 +1,2049 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_EFUSE_REG_H_
+#define _SOC_EFUSE_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define EFUSE_PGM_DATA0_REG          (DR_REG_EFUSE_BASE + 0x000)
+/* EFUSE_WR_DIS : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Disable programming of individual eFuses.*/
+#define EFUSE_WR_DIS  0xFFFFFFFF
+#define EFUSE_WR_DIS_M  ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S))
+#define EFUSE_WR_DIS_V  0xFFFFFFFF
+#define EFUSE_WR_DIS_S  0
+
+#define EFUSE_PGM_DATA1_REG          (DR_REG_EFUSE_BASE + 0x004)
+/* EFUSE_POWER_GLITCH_DSENSE : R/W ;bitpos:[31:30] ;default: 2'h0 ; */
+/*description: Sample delay configuration of power glitch.*/
+#define EFUSE_POWER_GLITCH_DSENSE  0x00000003
+#define EFUSE_POWER_GLITCH_DSENSE_M  ((EFUSE_POWER_GLITCH_DSENSE_V)<<(EFUSE_POWER_GLITCH_DSENSE_S))
+#define EFUSE_POWER_GLITCH_DSENSE_V  0x3
+#define EFUSE_POWER_GLITCH_DSENSE_S  30
+/* EFUSE_POWERGLITCH_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to enable power glitch function.*/
+#define EFUSE_POWERGLITCH_EN  (BIT(29))
+#define EFUSE_POWERGLITCH_EN_M  (BIT(29))
+#define EFUSE_POWERGLITCH_EN_V  0x1
+#define EFUSE_POWERGLITCH_EN_S  29
+/* EFUSE_BTLC_GPIO_ENABLE : R/W ;bitpos:[28:27] ;default: 2'h0 ; */
+/*description: Enable btlc gpio.*/
+#define EFUSE_BTLC_GPIO_ENABLE  0x00000003
+#define EFUSE_BTLC_GPIO_ENABLE_M  ((EFUSE_BTLC_GPIO_ENABLE_V)<<(EFUSE_BTLC_GPIO_ENABLE_S))
+#define EFUSE_BTLC_GPIO_ENABLE_V  0x3
+#define EFUSE_BTLC_GPIO_ENABLE_S  27
+/* EFUSE_VDD_SPI_AS_GPIO : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to vdd spi pin function as gpio.*/
+#define EFUSE_VDD_SPI_AS_GPIO  (BIT(26))
+#define EFUSE_VDD_SPI_AS_GPIO_M  (BIT(26))
+#define EFUSE_VDD_SPI_AS_GPIO_V  0x1
+#define EFUSE_VDD_SPI_AS_GPIO_S  26
+/* EFUSE_USB_EXCHG_PINS : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Set this bit to exchange USB D+ and D- pins.*/
+#define EFUSE_USB_EXCHG_PINS  (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_M  (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_V  0x1
+#define EFUSE_USB_EXCHG_PINS_S  25
+/* EFUSE_USB_DREFL : R/W ;bitpos:[24:23] ;default: 2'h0 ; */
+/*description: Controls single-end input threshold vrefl  0.8 V to 1.04 V with
+ step of 80 mV  stored in eFuse.*/
+#define EFUSE_USB_DREFL  0x00000003
+#define EFUSE_USB_DREFL_M  ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S))
+#define EFUSE_USB_DREFL_V  0x3
+#define EFUSE_USB_DREFL_S  23
+/* EFUSE_USB_DREFH : R/W ;bitpos:[22:21] ;default: 2'h0 ; */
+/*description: Controls single-end input threshold vrefh  1.76 V to 2 V with
+ step of 80 mV  stored in eFuse.*/
+#define EFUSE_USB_DREFH  0x00000003
+#define EFUSE_USB_DREFH_M  ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S))
+#define EFUSE_USB_DREFH_V  0x3
+#define EFUSE_USB_DREFH_S  21
+/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Set this bit to disable flash encryption when in download boot modes.*/
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT  (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
+/* EFUSE_DIS_PAD_JTAG : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/
+#define EFUSE_DIS_PAD_JTAG  (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_M  (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_V  0x1
+#define EFUSE_DIS_PAD_JTAG_S  19
+/* EFUSE_SOFT_DIS_JTAG : R/W ;bitpos:[18:16] ;default: 3'h0 ; */
+/*description: Set these bits to disable JTAG in the soft way (odd number 1
+ means disable ). JTAG can be enabled in HMAC module.*/
+#define EFUSE_SOFT_DIS_JTAG  0x00000007
+#define EFUSE_SOFT_DIS_JTAG_M  ((EFUSE_SOFT_DIS_JTAG_V)<<(EFUSE_SOFT_DIS_JTAG_S))
+#define EFUSE_SOFT_DIS_JTAG_V  0x7
+#define EFUSE_SOFT_DIS_JTAG_S  16
+/* EFUSE_JTAG_SEL_ENABLE : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to enable selection between usb_to_jtag and pad_to_jtag
+ through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/
+#define EFUSE_JTAG_SEL_ENABLE  (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_M  (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_V  0x1
+#define EFUSE_JTAG_SEL_ENABLE_S  15
+/* EFUSE_DIS_TWAI : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to disable TWAI function.*/
+#define EFUSE_DIS_TWAI  (BIT(14))
+#define EFUSE_DIS_TWAI_M  (BIT(14))
+#define EFUSE_DIS_TWAI_V  0x1
+#define EFUSE_DIS_TWAI_S  14
+/* EFUSE_RPT4_RESERVED6_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Reserved..*/
+#define EFUSE_RPT4_RESERVED6    (BIT(13))
+#define EFUSE_RPT4_RESERVED6_M  (BIT(13))
+#define EFUSE_RPT4_RESERVED6_V  0x1
+#define EFUSE_RPT4_RESERVED6_S  13
+/* EFUSE_DIS_FORCE_DOWNLOAD : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to disable the function that forces chip into download mode.*/
+#define EFUSE_DIS_FORCE_DOWNLOAD  (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_M  (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x1
+#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
+/* EFUSE_DIS_USB_DEVICE : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to disable usb device.*/
+#define EFUSE_DIS_USB_DEVICE  (BIT(11))
+#define EFUSE_DIS_USB_DEVICE_M  (BIT(11))
+#define EFUSE_DIS_USB_DEVICE_V  0x1
+#define EFUSE_DIS_USB_DEVICE_S  11
+/* EFUSE_DIS_DOWNLOAD_ICACHE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to disable Icache in download mode (boot_mode[3:0]
+ is 0  1  2  3  6  7).*/
+#define EFUSE_DIS_DOWNLOAD_ICACHE  (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_M  (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_ICACHE_S  10
+/* EFUSE_DIS_USB_JTAG : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to disable function of usb switch to jtag in module of usb device.*/
+#define EFUSE_DIS_USB_JTAG  (BIT(9))
+#define EFUSE_DIS_USB_JTAG_M  (BIT(9))
+#define EFUSE_DIS_USB_JTAG_V  0x1
+#define EFUSE_DIS_USB_JTAG_S  9
+/* EFUSE_DIS_ICACHE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to disable Icache.*/
+#define EFUSE_DIS_ICACHE  (BIT(8))
+#define EFUSE_DIS_ICACHE_M  (BIT(8))
+#define EFUSE_DIS_ICACHE_V  0x1
+#define EFUSE_DIS_ICACHE_S  8
+/* EFUSE_DIS_RTC_RAM_BOOT : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to disable boot from RTC RAM.*/
+#define EFUSE_DIS_RTC_RAM_BOOT  (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_M  (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_V  0x1
+#define EFUSE_DIS_RTC_RAM_BOOT_S  7
+/* EFUSE_RD_DIS : R/W ;bitpos:[6:0] ;default: 7'h0 ; */
+/*description: Set this bit to disable reading from BlOCK4-10.*/
+#define EFUSE_RD_DIS  0x0000007F
+#define EFUSE_RD_DIS_M  ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S))
+#define EFUSE_RD_DIS_V  0x7F
+#define EFUSE_RD_DIS_S  0
+
+#define EFUSE_PGM_DATA2_REG          (DR_REG_EFUSE_BASE + 0x008)
+/* EFUSE_KEY_PURPOSE_1 : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: Purpose of Key1.*/
+#define EFUSE_KEY_PURPOSE_1  0x0000000F
+#define EFUSE_KEY_PURPOSE_1_M  ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S))
+#define EFUSE_KEY_PURPOSE_1_V  0xF
+#define EFUSE_KEY_PURPOSE_1_S  28
+/* EFUSE_KEY_PURPOSE_0 : R/W ;bitpos:[27:24] ;default: 4'h0 ; */
+/*description: Purpose of Key0.*/
+#define EFUSE_KEY_PURPOSE_0  0x0000000F
+#define EFUSE_KEY_PURPOSE_0_M  ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S))
+#define EFUSE_KEY_PURPOSE_0_V  0xF
+#define EFUSE_KEY_PURPOSE_0_S  24
+/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Set this bit to enable revoking third secure boot key.*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2  (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
+/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Set this bit to enable revoking second secure boot key.*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1  (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
+/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Set this bit to enable revoking first secure boot key.*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0  (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
+/* EFUSE_SPI_BOOT_CRYPT_CNT : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: Set this bit to enable SPI boot encrypt/decrypt. Odd number of
+ 1: enable. even number of 1: disable.*/
+#define EFUSE_SPI_BOOT_CRYPT_CNT  0x00000007
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S))
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x7
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
+/* EFUSE_WAT_DELAY_SEL : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: Selects RTC watchdog timeout threshold  in unit of slow clock
+ cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/
+#define EFUSE_WAT_DELAY_SEL  0x00000003
+#define EFUSE_WAT_DELAY_SEL_M  ((EFUSE_WAT_DELAY_SEL_V)<<(EFUSE_WAT_DELAY_SEL_S))
+#define EFUSE_WAT_DELAY_SEL_V  0x3
+#define EFUSE_WAT_DELAY_SEL_S  16
+/* EFUSE_RPT4_RESERVED2 : RO ;bitpos:[15:0] ;default: 2'h0 ; */
+/*description: Reserved (used for four backups method).*/
+#define EFUSE_RPT4_RESERVED2  0x0000FFFF
+#define EFUSE_RPT4_RESERVED2_M  ((EFUSE_RPT4_RESERVED2_V)<<(EFUSE_RPT4_RESERVED2_S))
+#define EFUSE_RPT4_RESERVED2_V  0xFFFF
+#define EFUSE_RPT4_RESERVED2_S  0
+
+#define EFUSE_PGM_DATA3_REG          (DR_REG_EFUSE_BASE + 0x00C)
+/* EFUSE_FLASH_TPUW : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: Configures flash waiting time after power-up  in unit of ms.
+ If the value is less than 15  the waiting time is the configurable value*/
+#define EFUSE_FLASH_TPUW  0x0000000F
+#define EFUSE_FLASH_TPUW_M  ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S))
+#define EFUSE_FLASH_TPUW_V  0xF
+#define EFUSE_FLASH_TPUW_S  28
+/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[27:22] ;default: 6'h0 ; */
+/*description: Reserved (used for four backups method).*/
+#define EFUSE_RPT4_RESERVED0  0x0000003F
+#define EFUSE_RPT4_RESERVED0_M  ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S))
+#define EFUSE_RPT4_RESERVED0_V  0x3F
+#define EFUSE_RPT4_RESERVED0_S  22
+/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Set this bit to enable revoking aggressive secure boot.*/
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE  (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x1
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
+/* EFUSE_SECURE_BOOT_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Set this bit to enable secure boot.*/
+#define EFUSE_SECURE_BOOT_EN  (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_M  (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_V  0x1
+#define EFUSE_SECURE_BOOT_EN_S  20
+/* EFUSE_RPT4_RESERVED3 : RO ;bitpos:[19:16] ;default: 4'h0 ; */
+/*description: Reserved (used for four backups method).*/
+#define EFUSE_RPT4_RESERVED3  0x0000000F
+#define EFUSE_RPT4_RESERVED3_M  ((EFUSE_RPT4_RESERVED3_V)<<(EFUSE_RPT4_RESERVED3_S))
+#define EFUSE_RPT4_RESERVED3_V  0xF
+#define EFUSE_RPT4_RESERVED3_S  16
+/* EFUSE_KEY_PURPOSE_5 : R/W ;bitpos:[15:12] ;default: 4'h0 ; */
+/*description: Purpose of Key5.*/
+#define EFUSE_KEY_PURPOSE_5  0x0000000F
+#define EFUSE_KEY_PURPOSE_5_M  ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S))
+#define EFUSE_KEY_PURPOSE_5_V  0xF
+#define EFUSE_KEY_PURPOSE_5_S  12
+/* EFUSE_KEY_PURPOSE_4 : R/W ;bitpos:[11:8] ;default: 4'h0 ; */
+/*description: Purpose of Key4.*/
+#define EFUSE_KEY_PURPOSE_4  0x0000000F
+#define EFUSE_KEY_PURPOSE_4_M  ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S))
+#define EFUSE_KEY_PURPOSE_4_V  0xF
+#define EFUSE_KEY_PURPOSE_4_S  8
+/* EFUSE_KEY_PURPOSE_3 : R/W ;bitpos:[7:4] ;default: 4'h0 ; */
+/*description: Purpose of Key3.*/
+#define EFUSE_KEY_PURPOSE_3  0x0000000F
+#define EFUSE_KEY_PURPOSE_3_M  ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S))
+#define EFUSE_KEY_PURPOSE_3_V  0xF
+#define EFUSE_KEY_PURPOSE_3_S  4
+/* EFUSE_KEY_PURPOSE_2 : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: Purpose of Key2.*/
+#define EFUSE_KEY_PURPOSE_2  0x0000000F
+#define EFUSE_KEY_PURPOSE_2_M  ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S))
+#define EFUSE_KEY_PURPOSE_2_V  0xF
+#define EFUSE_KEY_PURPOSE_2_S  0
+
+#define EFUSE_PGM_DATA4_REG          (DR_REG_EFUSE_BASE + 0x010)
+/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */
+/*description: Reserved (used for four backups method).*/
+#define EFUSE_RPT4_RESERVED1  0x00000003
+#define EFUSE_RPT4_RESERVED1_M  ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S))
+#define EFUSE_RPT4_RESERVED1_V  0x3
+#define EFUSE_RPT4_RESERVED1_S  30
+/* EFUSE_SECURE_VERSION : R/W ;bitpos:[29:14] ;default: 16'h0 ; */
+/*description: Secure version (used by ESP-IDF anti-rollback feature).*/
+#define EFUSE_SECURE_VERSION  0x0000FFFF
+#define EFUSE_SECURE_VERSION_M  ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S))
+#define EFUSE_SECURE_VERSION_V  0xFFFF
+#define EFUSE_SECURE_VERSION_S  14
+/* EFUSE_FORCE_SEND_RESUME : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to force ROM code to send a resume command during SPI boot.*/
+#define EFUSE_FORCE_SEND_RESUME  (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_M  (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_V  0x1
+#define EFUSE_FORCE_SEND_RESUME_S  13
+/* EFUSE_FLASH_ECC_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set 1 to enable ECC for flash boot.*/
+#define EFUSE_FLASH_ECC_EN  (BIT(12))
+#define EFUSE_FLASH_ECC_EN_M  (BIT(12))
+#define EFUSE_FLASH_ECC_EN_V  0x1
+#define EFUSE_FLASH_ECC_EN_S  12
+/* EFUSE_FLASH_PAGE_SIZE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: Set Flash page size.*/
+#define EFUSE_FLASH_PAGE_SIZE  0x00000003
+#define EFUSE_FLASH_PAGE_SIZE_M  ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S))
+#define EFUSE_FLASH_PAGE_SIZE_V  0x3
+#define EFUSE_FLASH_PAGE_SIZE_S  10
+/* EFUSE_FLASH_TYPE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.*/
+#define EFUSE_FLASH_TYPE  (BIT(9))
+#define EFUSE_FLASH_TYPE_M  (BIT(9))
+#define EFUSE_FLASH_TYPE_V  0x1
+#define EFUSE_FLASH_TYPE_S  9
+/* EFUSE_PIN_POWER_SELECTION : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.*/
+#define EFUSE_PIN_POWER_SELECTION  (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_M  (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_V  0x1
+#define EFUSE_PIN_POWER_SELECTION_S  8
+/* EFUSE_UART_PRINT_CONTROL : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: Set the default UARTboot message output mode. 00: Enabled. 01:
+ Enabled when GPIO46 is low at reset. 10: Enabled when GPIO46 is high at reset. 11:disabled.*/
+#define EFUSE_UART_PRINT_CONTROL  0x00000003
+#define EFUSE_UART_PRINT_CONTROL_M  ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S))
+#define EFUSE_UART_PRINT_CONTROL_V  0x3
+#define EFUSE_UART_PRINT_CONTROL_S  6
+/* EFUSE_ENABLE_SECURITY_DOWNLOAD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable secure UART download mode.*/
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD  (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x1
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
+/* EFUSE_DIS_USB_DOWNLOAD_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to disable UART download mode through USB.*/
+#define EFUSE_DIS_USB_DOWNLOAD_MODE  (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_M  (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_V  0x1
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_S  4
+/* EFUSE_FLASH_ECC_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set ECC mode in ROM  0: ROM would Enable Flash ECC 16to18 byte
+ mode. 1:ROM would use 16to17 byte mode.*/
+#define EFUSE_FLASH_ECC_MODE  (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_M  (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_V  0x1
+#define EFUSE_FLASH_ECC_MODE_S  3
+/* EFUSE_UART_PRINT_CHANNEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Selectes the default UART print channel. 0: UART0. 1: UART1.*/
+#define EFUSE_UART_PRINT_CHANNEL  (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_M  (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_V  0x1
+#define EFUSE_UART_PRINT_CHANNEL_S  2
+/* EFUSE_DIS_LEGACY_SPI_BOOT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).*/
+#define EFUSE_DIS_LEGACY_SPI_BOOT  (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_M  (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_V  0x1
+#define EFUSE_DIS_LEGACY_SPI_BOOT_S  1
+/* EFUSE_DIS_DOWNLOAD_MODE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to disable download mode (boot_mode[3:0] = 0  1  2  3  6  7).*/
+#define EFUSE_DIS_DOWNLOAD_MODE  (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MODE_S  0
+
+#define EFUSE_PGM_DATA5_REG          (DR_REG_EFUSE_BASE + 0x014)
+/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Reserved (used for four backups method).*/
+#define EFUSE_RPT4_RESERVED4  0x00FFFFFF
+#define EFUSE_RPT4_RESERVED4_M  ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S))
+#define EFUSE_RPT4_RESERVED4_V  0xFFFFFF
+#define EFUSE_RPT4_RESERVED4_S  0
+
+#define EFUSE_PGM_DATA6_REG          (DR_REG_EFUSE_BASE + 0x018)
+/* EFUSE_PGM_DATA_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the sixth 32-bit data to be programmed.*/
+#define EFUSE_PGM_DATA_6  0xFFFFFFFF
+#define EFUSE_PGM_DATA_6_M  ((EFUSE_PGM_DATA_6_V)<<(EFUSE_PGM_DATA_6_S))
+#define EFUSE_PGM_DATA_6_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_6_S  0
+
+#define EFUSE_PGM_DATA7_REG          (DR_REG_EFUSE_BASE + 0x01C)
+/* EFUSE_PGM_DATA_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the seventh 32-bit data to be programmed.*/
+#define EFUSE_PGM_DATA_7  0xFFFFFFFF
+#define EFUSE_PGM_DATA_7_M  ((EFUSE_PGM_DATA_7_V)<<(EFUSE_PGM_DATA_7_S))
+#define EFUSE_PGM_DATA_7_V  0xFFFFFFFF
+#define EFUSE_PGM_DATA_7_S  0
+
+#define EFUSE_PGM_CHECK_VALUE0_REG          (DR_REG_EFUSE_BASE + 0x020)
+/* EFUSE_PGM_RS_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the 0th 32-bit RS code to be programmed.*/
+#define EFUSE_PGM_RS_DATA_0  0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_0_M  ((EFUSE_PGM_RS_DATA_0_V)<<(EFUSE_PGM_RS_DATA_0_S))
+#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_0_S  0
+
+#define EFUSE_PGM_CHECK_VALUE1_REG          (DR_REG_EFUSE_BASE + 0x024)
+/* EFUSE_PGM_RS_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the first 32-bit RS code to be programmed.*/
+#define EFUSE_PGM_RS_DATA_1  0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_1_M  ((EFUSE_PGM_RS_DATA_1_V)<<(EFUSE_PGM_RS_DATA_1_S))
+#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_1_S  0
+
+#define EFUSE_PGM_CHECK_VALUE2_REG          (DR_REG_EFUSE_BASE + 0x028)
+/* EFUSE_PGM_RS_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The content of the second 32-bit RS code to be programmed.*/
+#define EFUSE_PGM_RS_DATA_2  0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_2_M  ((EFUSE_PGM_RS_DATA_2_V)<<(EFUSE_PGM_RS_DATA_2_S))
+#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFF
+#define EFUSE_PGM_RS_DATA_2_S  0
+
+#define EFUSE_RD_WR_DIS_REG          (DR_REG_EFUSE_BASE + 0x02C)
+/* EFUSE_WR_DIS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The value of WR_DIS.*/
+#define EFUSE_WR_DIS  0xFFFFFFFF
+#define EFUSE_WR_DIS_M  ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S))
+#define EFUSE_WR_DIS_V  0xFFFFFFFF
+#define EFUSE_WR_DIS_S  0
+
+#define EFUSE_RD_REPEAT_DATA0_REG          (DR_REG_EFUSE_BASE + 0x030)
+/* EFUSE_POWER_GLITCH_DSENSE : RO ;bitpos:[31:30] ;default: 2'h0 ; */
+/*description: The value of POWER_GLITCH_DSENSE.*/
+#define EFUSE_POWER_GLITCH_DSENSE  0x00000003
+#define EFUSE_POWER_GLITCH_DSENSE_M  ((EFUSE_POWER_GLITCH_DSENSE_V)<<(EFUSE_POWER_GLITCH_DSENSE_S))
+#define EFUSE_POWER_GLITCH_DSENSE_V  0x3
+#define EFUSE_POWER_GLITCH_DSENSE_S  30
+/* EFUSE_POWERGLITCH_EN : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: The value of POWERGLITCH_EN.*/
+#define EFUSE_POWERGLITCH_EN  (BIT(29))
+#define EFUSE_POWERGLITCH_EN_M  (BIT(29))
+#define EFUSE_POWERGLITCH_EN_V  0x1
+#define EFUSE_POWERGLITCH_EN_S  29
+/* EFUSE_BTLC_GPIO_ENABLE : RO ;bitpos:[28:27] ;default: 2'h0 ; */
+/*description: The value of BTLC_GPIO_ENABLE.*/
+#define EFUSE_BTLC_GPIO_ENABLE  0x00000003
+#define EFUSE_BTLC_GPIO_ENABLE_M  ((EFUSE_BTLC_GPIO_ENABLE_V)<<(EFUSE_BTLC_GPIO_ENABLE_S))
+#define EFUSE_BTLC_GPIO_ENABLE_V  0x3
+#define EFUSE_BTLC_GPIO_ENABLE_S  27
+/* EFUSE_VDD_SPI_AS_GPIO : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: The value of VDD_SPI_AS_GPIO.*/
+#define EFUSE_VDD_SPI_AS_GPIO  (BIT(26))
+#define EFUSE_VDD_SPI_AS_GPIO_M  (BIT(26))
+#define EFUSE_VDD_SPI_AS_GPIO_V  0x1
+#define EFUSE_VDD_SPI_AS_GPIO_S  26
+/* EFUSE_USB_EXCHG_PINS : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: The value of USB_EXCHG_PINS.*/
+#define EFUSE_USB_EXCHG_PINS  (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_M  (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_V  0x1
+#define EFUSE_USB_EXCHG_PINS_S  25
+/* EFUSE_USB_DREFL : RO ;bitpos:[24:23] ;default: 2'h0 ; */
+/*description: The value of USB_DREFL.*/
+#define EFUSE_USB_DREFL  0x00000003
+#define EFUSE_USB_DREFL_M  ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S))
+#define EFUSE_USB_DREFL_V  0x3
+#define EFUSE_USB_DREFL_S  23
+/* EFUSE_USB_DREFH : RO ;bitpos:[22:21] ;default: 2'h0 ; */
+/*description: The value of USB_DREFH.*/
+#define EFUSE_USB_DREFH  0x00000003
+#define EFUSE_USB_DREFH_M  ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S))
+#define EFUSE_USB_DREFH_V  0x3
+#define EFUSE_USB_DREFH_S  21
+/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The value of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT  (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
+/* EFUSE_DIS_PAD_JTAG : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The value of DIS_PAD_JTAG.*/
+#define EFUSE_DIS_PAD_JTAG  (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_M  (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_V  0x1
+#define EFUSE_DIS_PAD_JTAG_S  19
+/* EFUSE_SOFT_DIS_JTAG : RO ;bitpos:[18:16] ;default: 3'h0 ; */
+/*description: The value of SOFT_DIS_JTAG.*/
+#define EFUSE_SOFT_DIS_JTAG  0x00000007
+#define EFUSE_SOFT_DIS_JTAG_M  ((EFUSE_SOFT_DIS_JTAG_V)<<(EFUSE_SOFT_DIS_JTAG_S))
+#define EFUSE_SOFT_DIS_JTAG_V  0x7
+#define EFUSE_SOFT_DIS_JTAG_S  16
+/* EFUSE_JTAG_SEL_ENABLE : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The value of JTAG_SEL_ENABLE.*/
+#define EFUSE_JTAG_SEL_ENABLE  (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_M  (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_V  0x1
+#define EFUSE_JTAG_SEL_ENABLE_S  15
+/* EFUSE_DIS_TWAI : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The value of DIS_TWAI.*/
+#define EFUSE_DIS_TWAI  (BIT(14))
+#define EFUSE_DIS_TWAI_M  (BIT(14))
+#define EFUSE_DIS_TWAI_V  0x1
+#define EFUSE_DIS_TWAI_S  14
+/* EFUSE_RPT4_RESERVED6 : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Reserved (used for four backups method)..*/
+#define EFUSE_RPT4_RESERVED6    (BIT(13))
+#define EFUSE_RPT4_RESERVED6_M  (BIT(13))
+#define EFUSE_RPT4_RESERVED6_V  0x1
+#define EFUSE_RPT4_RESERVED6_S  13
+/* EFUSE_DIS_FORCE_DOWNLOAD : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The value of DIS_FORCE_DOWNLOAD.*/
+#define EFUSE_DIS_FORCE_DOWNLOAD  (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_M  (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x1
+#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
+/* EFUSE_DIS_USB_DEVICE : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The value of DIS_USB_DEVICE.*/
+#define EFUSE_DIS_USB_DEVICE  (BIT(11))
+#define EFUSE_DIS_USB_DEVICE_M  (BIT(11))
+#define EFUSE_DIS_USB_DEVICE_V  0x1
+#define EFUSE_DIS_USB_DEVICE_S  11
+/* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The value of DIS_DOWNLOAD_ICACHE.*/
+#define EFUSE_DIS_DOWNLOAD_ICACHE  (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_M  (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_ICACHE_S  10
+/* EFUSE_DIS_USB_JTAG : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The value of DIS_USB_JTAG.*/
+#define EFUSE_DIS_USB_JTAG  (BIT(9))
+#define EFUSE_DIS_USB_JTAG_M  (BIT(9))
+#define EFUSE_DIS_USB_JTAG_V  0x1
+#define EFUSE_DIS_USB_JTAG_S  9
+/* EFUSE_DIS_ICACHE : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The value of DIS_ICACHE.*/
+#define EFUSE_DIS_ICACHE  (BIT(8))
+#define EFUSE_DIS_ICACHE_M  (BIT(8))
+#define EFUSE_DIS_ICACHE_V  0x1
+#define EFUSE_DIS_ICACHE_S  8
+/* EFUSE_DIS_RTC_RAM_BOOT : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The value of DIS_RTC_RAM_BOOT.*/
+#define EFUSE_DIS_RTC_RAM_BOOT  (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_M  (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_V  0x1
+#define EFUSE_DIS_RTC_RAM_BOOT_S  7
+/* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */
+/*description: The value of RD_DIS.*/
+#define EFUSE_RD_DIS  0x0000007F
+#define EFUSE_RD_DIS_M  ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S))
+#define EFUSE_RD_DIS_V  0x7F
+#define EFUSE_RD_DIS_S  0
+
+#define EFUSE_RD_REPEAT_DATA1_REG          (DR_REG_EFUSE_BASE + 0x034)
+/* EFUSE_KEY_PURPOSE_1 : RO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: The value of KEY_PURPOSE_1.*/
+#define EFUSE_KEY_PURPOSE_1  0x0000000F
+#define EFUSE_KEY_PURPOSE_1_M  ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S))
+#define EFUSE_KEY_PURPOSE_1_V  0xF
+#define EFUSE_KEY_PURPOSE_1_S  28
+/* EFUSE_KEY_PURPOSE_0 : RO ;bitpos:[27:24] ;default: 4'h0 ; */
+/*description: The value of KEY_PURPOSE_0.*/
+#define EFUSE_KEY_PURPOSE_0  0x0000000F
+#define EFUSE_KEY_PURPOSE_0_M  ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S))
+#define EFUSE_KEY_PURPOSE_0_V  0xF
+#define EFUSE_KEY_PURPOSE_0_S  24
+/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: The value of SECURE_BOOT_KEY_REVOKE2.*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2  (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
+/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: The value of SECURE_BOOT_KEY_REVOKE1.*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1  (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
+/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The value of SECURE_BOOT_KEY_REVOKE0.*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0  (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
+/* EFUSE_SPI_BOOT_CRYPT_CNT : RO ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: The value of SPI_BOOT_CRYPT_CNT.*/
+#define EFUSE_SPI_BOOT_CRYPT_CNT  0x00000007
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S))
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x7
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
+/* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: The value of WDT_DELAY_SEL.*/
+#define EFUSE_WDT_DELAY_SEL  0x00000003
+#define EFUSE_WDT_DELAY_SEL_M  ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S))
+#define EFUSE_WDT_DELAY_SEL_V  0x3
+#define EFUSE_WDT_DELAY_SEL_S  16
+/* EFUSE_RPT4_RESERVED2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: Reserved.*/
+#define EFUSE_RPT4_RESERVED2  0x0000FFFF
+#define EFUSE_RPT4_RESERVED2_M  ((EFUSE_RPT4_RESERVED2_V)<<(EFUSE_RPT4_RESERVED2_S))
+#define EFUSE_RPT4_RESERVED2_V  0xFFFF
+#define EFUSE_RPT4_RESERVED2_S  0
+
+#define EFUSE_RD_REPEAT_DATA2_REG          (DR_REG_EFUSE_BASE + 0x038)
+/* EFUSE_FLASH_TPUW : RO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: The value of FLASH_TPUW.*/
+#define EFUSE_FLASH_TPUW  0x0000000F
+#define EFUSE_FLASH_TPUW_M  ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S))
+#define EFUSE_FLASH_TPUW_V  0xF
+#define EFUSE_FLASH_TPUW_S  28
+/* EFUSE_RPT4_RESERVED0 : RO ;bitpos:[27:22] ;default: 6'h0 ; */
+/*description: Reserved.*/
+#define EFUSE_RPT4_RESERVED0  0x0000003F
+#define EFUSE_RPT4_RESERVED0_M  ((EFUSE_RPT4_RESERVED0_V)<<(EFUSE_RPT4_RESERVED0_S))
+#define EFUSE_RPT4_RESERVED0_V  0x3F
+#define EFUSE_RPT4_RESERVED0_S  22
+/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The value of SECURE_BOOT_AGGRESSIVE_REVOKE.*/
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE  (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x1
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
+/* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The value of SECURE_BOOT_EN.*/
+#define EFUSE_SECURE_BOOT_EN  (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_M  (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_V  0x1
+#define EFUSE_SECURE_BOOT_EN_S  20
+/* EFUSE_RPT4_RESERVED3 : RO ;bitpos:[19:16] ;default: 4'h0 ; */
+/*description: Reserved.*/
+#define EFUSE_RPT4_RESERVED3  0x0000000F
+#define EFUSE_RPT4_RESERVED3_M  ((EFUSE_RPT4_RESERVED3_V)<<(EFUSE_RPT4_RESERVED3_S))
+#define EFUSE_RPT4_RESERVED3_V  0xF
+#define EFUSE_RPT4_RESERVED3_S  16
+/* EFUSE_KEY_PURPOSE_5 : RO ;bitpos:[15:12] ;default: 4'h0 ; */
+/*description: The value of KEY_PURPOSE_5.*/
+#define EFUSE_KEY_PURPOSE_5  0x0000000F
+#define EFUSE_KEY_PURPOSE_5_M  ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S))
+#define EFUSE_KEY_PURPOSE_5_V  0xF
+#define EFUSE_KEY_PURPOSE_5_S  12
+/* EFUSE_KEY_PURPOSE_4 : RO ;bitpos:[11:8] ;default: 4'h0 ; */
+/*description: The value of KEY_PURPOSE_4.*/
+#define EFUSE_KEY_PURPOSE_4  0x0000000F
+#define EFUSE_KEY_PURPOSE_4_M  ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S))
+#define EFUSE_KEY_PURPOSE_4_V  0xF
+#define EFUSE_KEY_PURPOSE_4_S  8
+/* EFUSE_KEY_PURPOSE_3 : RO ;bitpos:[7:4] ;default: 4'h0 ; */
+/*description: The value of KEY_PURPOSE_3.*/
+#define EFUSE_KEY_PURPOSE_3  0x0000000F
+#define EFUSE_KEY_PURPOSE_3_M  ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S))
+#define EFUSE_KEY_PURPOSE_3_V  0xF
+#define EFUSE_KEY_PURPOSE_3_S  4
+/* EFUSE_KEY_PURPOSE_2 : RO ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: The value of KEY_PURPOSE_2.*/
+#define EFUSE_KEY_PURPOSE_2  0x0000000F
+#define EFUSE_KEY_PURPOSE_2_M  ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S))
+#define EFUSE_KEY_PURPOSE_2_V  0xF
+#define EFUSE_KEY_PURPOSE_2_S  0
+
+#define EFUSE_RD_REPEAT_DATA3_REG          (DR_REG_EFUSE_BASE + 0x03C)
+/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */
+/*description: Reserved.*/
+#define EFUSE_RPT4_RESERVED1  0x00000003
+#define EFUSE_RPT4_RESERVED1_M  ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S))
+#define EFUSE_RPT4_RESERVED1_V  0x3
+#define EFUSE_RPT4_RESERVED1_S  30
+/* EFUSE_SECURE_VERSION : RO ;bitpos:[29:14] ;default: 16'h0 ; */
+/*description: The value of SECURE_VERSION.*/
+#define EFUSE_SECURE_VERSION  0x0000FFFF
+#define EFUSE_SECURE_VERSION_M  ((EFUSE_SECURE_VERSION_V)<<(EFUSE_SECURE_VERSION_S))
+#define EFUSE_SECURE_VERSION_V  0xFFFF
+#define EFUSE_SECURE_VERSION_S  14
+/* EFUSE_FORCE_SEND_RESUME : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The value of FORCE_SEND_RESUME.*/
+#define EFUSE_FORCE_SEND_RESUME  (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_M  (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_V  0x1
+#define EFUSE_FORCE_SEND_RESUME_S  13
+/* EFUSE_FLASH_ECC_EN : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The value of FLASH_ECC_EN.*/
+#define EFUSE_FLASH_ECC_EN  (BIT(12))
+#define EFUSE_FLASH_ECC_EN_M  (BIT(12))
+#define EFUSE_FLASH_ECC_EN_V  0x1
+#define EFUSE_FLASH_ECC_EN_S  12
+/* EFUSE_FLASH_PAGE_SIZE : RO ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: The value of FLASH_PAGE_SIZE.*/
+#define EFUSE_FLASH_PAGE_SIZE  0x00000003
+#define EFUSE_FLASH_PAGE_SIZE_M  ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S))
+#define EFUSE_FLASH_PAGE_SIZE_V  0x3
+#define EFUSE_FLASH_PAGE_SIZE_S  10
+/* EFUSE_FLASH_TYPE : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The value of FLASH_TYPE.*/
+#define EFUSE_FLASH_TYPE  (BIT(9))
+#define EFUSE_FLASH_TYPE_M  (BIT(9))
+#define EFUSE_FLASH_TYPE_V  0x1
+#define EFUSE_FLASH_TYPE_S  9
+/* EFUSE_PIN_POWER_SELECTION : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The value of PIN_POWER_SELECTION.*/
+#define EFUSE_PIN_POWER_SELECTION  (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_M  (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_V  0x1
+#define EFUSE_PIN_POWER_SELECTION_S  8
+/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: The value of UART_PRINT_CONTROL.*/
+#define EFUSE_UART_PRINT_CONTROL  0x00000003
+#define EFUSE_UART_PRINT_CONTROL_M  ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S))
+#define EFUSE_UART_PRINT_CONTROL_V  0x3
+#define EFUSE_UART_PRINT_CONTROL_S  6
+/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The value of ENABLE_SECURITY_DOWNLOAD.*/
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD  (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x1
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
+/* EFUSE_DIS_USB_DOWNLOAD_MODE : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The value of DIS_USB_DOWNLOAD_MODE.*/
+#define EFUSE_DIS_USB_DOWNLOAD_MODE  (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_M  (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_V  0x1
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_S  4
+/* EFUSE_FLASH_ECC_MODE : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The value of FLASH_ECC_MODE.*/
+#define EFUSE_FLASH_ECC_MODE  (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_M  (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_V  0x1
+#define EFUSE_FLASH_ECC_MODE_S  3
+/* EFUSE_UART_PRINT_CHANNEL : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The value of UART_PRINT_CHANNEL.*/
+#define EFUSE_UART_PRINT_CHANNEL  (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_M  (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_V  0x1
+#define EFUSE_UART_PRINT_CHANNEL_S  2
+/* EFUSE_DIS_LEGACY_SPI_BOOT : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The value of DIS_LEGACY_SPI_BOOT.*/
+#define EFUSE_DIS_LEGACY_SPI_BOOT  (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_M  (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_V  0x1
+#define EFUSE_DIS_LEGACY_SPI_BOOT_S  1
+/* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The value of DIS_DOWNLOAD_MODE.*/
+#define EFUSE_DIS_DOWNLOAD_MODE  (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MODE_S  0
+
+#define EFUSE_RD_REPEAT_DATA4_REG          (DR_REG_EFUSE_BASE + 0x040)
+/* EFUSE_RPT4_RESERVED4 : RO ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Reserved.*/
+#define EFUSE_RPT4_RESERVED4  0x00FFFFFF
+#define EFUSE_RPT4_RESERVED4_M  ((EFUSE_RPT4_RESERVED4_V)<<(EFUSE_RPT4_RESERVED4_S))
+#define EFUSE_RPT4_RESERVED4_V  0xFFFFFF
+#define EFUSE_RPT4_RESERVED4_S  0
+
+#define EFUSE_RD_MAC_SPI_SYS_0_REG          (DR_REG_EFUSE_BASE + 0x044)
+/* EFUSE_MAC_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the low 32 bits of MAC address.*/
+#define EFUSE_MAC_0  0xFFFFFFFF
+#define EFUSE_MAC_0_M  ((EFUSE_MAC_0_V)<<(EFUSE_MAC_0_S))
+#define EFUSE_MAC_0_V  0xFFFFFFFF
+#define EFUSE_MAC_0_S  0
+
+#define EFUSE_RD_MAC_SPI_SYS_1_REG          (DR_REG_EFUSE_BASE + 0x048)
+/* EFUSE_SPI_PAD_CONF_0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: Stores the zeroth part of SPI_PAD_CONF.*/
+#define EFUSE_SPI_PAD_CONF_0  0x0000FFFF
+#define EFUSE_SPI_PAD_CONF_0_M  ((EFUSE_SPI_PAD_CONF_0_V)<<(EFUSE_SPI_PAD_CONF_0_S))
+#define EFUSE_SPI_PAD_CONF_0_V  0xFFFF
+#define EFUSE_SPI_PAD_CONF_0_S  16
+/* EFUSE_MAC_1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: Stores the high 16 bits of MAC address.*/
+#define EFUSE_MAC_1  0x0000FFFF
+#define EFUSE_MAC_1_M  ((EFUSE_MAC_1_V)<<(EFUSE_MAC_1_S))
+#define EFUSE_MAC_1_V  0xFFFF
+#define EFUSE_MAC_1_S  0
+
+#define EFUSE_RD_MAC_SPI_SYS_2_REG          (DR_REG_EFUSE_BASE + 0x04C)
+/* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first part of SPI_PAD_CONF.*/
+#define EFUSE_SPI_PAD_CONF_1  0xFFFFFFFF
+#define EFUSE_SPI_PAD_CONF_1_M  ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S))
+#define EFUSE_SPI_PAD_CONF_1_V  0xFFFFFFFF
+#define EFUSE_SPI_PAD_CONF_1_S  0
+
+#define EFUSE_RD_MAC_SPI_SYS_3_REG          (DR_REG_EFUSE_BASE + 0x050)
+/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:18] ;default: 14'h0 ; */
+/*description: Stores the fist 14 bits of the zeroth part of system data.*/
+#define EFUSE_SYS_DATA_PART0_0  0x00003FFF
+#define EFUSE_SYS_DATA_PART0_0_M  ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S))
+#define EFUSE_SYS_DATA_PART0_0_V  0x3FFF
+#define EFUSE_SYS_DATA_PART0_0_S  18
+/* EFUSE_SPI_PAD_CONF_2 : RO ;bitpos:[17:0] ;default: 18'h0 ; */
+/*description: Stores the second part of SPI_PAD_CONF.*/
+#define EFUSE_SPI_PAD_CONF_2  0x0003FFFF
+#define EFUSE_SPI_PAD_CONF_2_M  ((EFUSE_SPI_PAD_CONF_2_V)<<(EFUSE_SPI_PAD_CONF_2_S))
+#define EFUSE_SPI_PAD_CONF_2_V  0x3FFFF
+#define EFUSE_SPI_PAD_CONF_2_S  0
+
+#define EFUSE_RD_MAC_SPI_SYS_4_REG          (DR_REG_EFUSE_BASE + 0x054)
+/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fist 32 bits of the zeroth part of system data.*/
+#define EFUSE_SYS_DATA_PART0_1  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART0_1_M  ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S))
+#define EFUSE_SYS_DATA_PART0_1_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART0_1_S  0
+
+#define EFUSE_RD_MAC_SPI_SYS_5_REG          (DR_REG_EFUSE_BASE + 0x058)
+/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of the zeroth part of system data.*/
+#define EFUSE_SYS_DATA_PART0_2  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART0_2_M  ((EFUSE_SYS_DATA_PART0_2_V)<<(EFUSE_SYS_DATA_PART0_2_S))
+#define EFUSE_SYS_DATA_PART0_2_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART0_2_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA0_REG          (DR_REG_EFUSE_BASE + 0x05C)
+/* EFUSE_SYS_DATA_PART1_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of the first part of system data.*/
+#define EFUSE_SYS_DATA_PART1_0  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_0_M  ((EFUSE_SYS_DATA_PART1_0_V)<<(EFUSE_SYS_DATA_PART1_0_S))
+#define EFUSE_SYS_DATA_PART1_0_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_0_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA1_REG          (DR_REG_EFUSE_BASE + 0x060)
+/* EFUSE_SYS_DATA_PART1_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of the first part of system data.*/
+#define EFUSE_SYS_DATA_PART1_1  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_1_M  ((EFUSE_SYS_DATA_PART1_1_V)<<(EFUSE_SYS_DATA_PART1_1_S))
+#define EFUSE_SYS_DATA_PART1_1_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_1_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA2_REG          (DR_REG_EFUSE_BASE + 0x064)
+/* EFUSE_SYS_DATA_PART1_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of the first part of system data.*/
+#define EFUSE_SYS_DATA_PART1_2  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_2_M  ((EFUSE_SYS_DATA_PART1_2_V)<<(EFUSE_SYS_DATA_PART1_2_S))
+#define EFUSE_SYS_DATA_PART1_2_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_2_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA3_REG          (DR_REG_EFUSE_BASE + 0x068)
+/* EFUSE_SYS_DATA_PART1_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of the first part of system data.*/
+#define EFUSE_SYS_DATA_PART1_3  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_3_M  ((EFUSE_SYS_DATA_PART1_3_V)<<(EFUSE_SYS_DATA_PART1_3_S))
+#define EFUSE_SYS_DATA_PART1_3_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_3_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA4_REG          (DR_REG_EFUSE_BASE + 0x06C)
+/* EFUSE_SYS_DATA_PART1_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of the first part of system data.*/
+#define EFUSE_SYS_DATA_PART1_4  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_4_M  ((EFUSE_SYS_DATA_PART1_4_V)<<(EFUSE_SYS_DATA_PART1_4_S))
+#define EFUSE_SYS_DATA_PART1_4_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_4_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA5_REG          (DR_REG_EFUSE_BASE + 0x070)
+/* EFUSE_SYS_DATA_PART1_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of the first part of system data.*/
+#define EFUSE_SYS_DATA_PART1_5  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_5_M  ((EFUSE_SYS_DATA_PART1_5_V)<<(EFUSE_SYS_DATA_PART1_5_S))
+#define EFUSE_SYS_DATA_PART1_5_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_5_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA6_REG          (DR_REG_EFUSE_BASE + 0x074)
+/* EFUSE_SYS_DATA_PART1_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of the first part of system data.*/
+#define EFUSE_SYS_DATA_PART1_6  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_6_M  ((EFUSE_SYS_DATA_PART1_6_V)<<(EFUSE_SYS_DATA_PART1_6_S))
+#define EFUSE_SYS_DATA_PART1_6_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_6_S  0
+
+#define EFUSE_RD_SYS_PART1_DATA7_REG          (DR_REG_EFUSE_BASE + 0x078)
+/* EFUSE_SYS_DATA_PART1_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of the first part of system data.*/
+#define EFUSE_SYS_DATA_PART1_7  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_7_M  ((EFUSE_SYS_DATA_PART1_7_V)<<(EFUSE_SYS_DATA_PART1_7_S))
+#define EFUSE_SYS_DATA_PART1_7_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART1_7_S  0
+
+#define EFUSE_RD_USR_DATA0_REG          (DR_REG_EFUSE_BASE + 0x07C)
+/* EFUSE_USR_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of BLOCK3 (user).*/
+#define EFUSE_USR_DATA0  0xFFFFFFFF
+#define EFUSE_USR_DATA0_M  ((EFUSE_USR_DATA0_V)<<(EFUSE_USR_DATA0_S))
+#define EFUSE_USR_DATA0_V  0xFFFFFFFF
+#define EFUSE_USR_DATA0_S  0
+
+#define EFUSE_RD_USR_DATA1_REG          (DR_REG_EFUSE_BASE + 0x080)
+/* EFUSE_USR_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of BLOCK3 (user).*/
+#define EFUSE_USR_DATA1  0xFFFFFFFF
+#define EFUSE_USR_DATA1_M  ((EFUSE_USR_DATA1_V)<<(EFUSE_USR_DATA1_S))
+#define EFUSE_USR_DATA1_V  0xFFFFFFFF
+#define EFUSE_USR_DATA1_S  0
+
+#define EFUSE_RD_USR_DATA2_REG          (DR_REG_EFUSE_BASE + 0x084)
+/* EFUSE_USR_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of BLOCK3 (user).*/
+#define EFUSE_USR_DATA2  0xFFFFFFFF
+#define EFUSE_USR_DATA2_M  ((EFUSE_USR_DATA2_V)<<(EFUSE_USR_DATA2_S))
+#define EFUSE_USR_DATA2_V  0xFFFFFFFF
+#define EFUSE_USR_DATA2_S  0
+
+#define EFUSE_RD_USR_DATA3_REG          (DR_REG_EFUSE_BASE + 0x088)
+/* EFUSE_USR_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of BLOCK3 (user).*/
+#define EFUSE_USR_DATA3  0xFFFFFFFF
+#define EFUSE_USR_DATA3_M  ((EFUSE_USR_DATA3_V)<<(EFUSE_USR_DATA3_S))
+#define EFUSE_USR_DATA3_V  0xFFFFFFFF
+#define EFUSE_USR_DATA3_S  0
+
+#define EFUSE_RD_USR_DATA4_REG          (DR_REG_EFUSE_BASE + 0x08C)
+/* EFUSE_USR_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of BLOCK3 (user).*/
+#define EFUSE_USR_DATA4  0xFFFFFFFF
+#define EFUSE_USR_DATA4_M  ((EFUSE_USR_DATA4_V)<<(EFUSE_USR_DATA4_S))
+#define EFUSE_USR_DATA4_V  0xFFFFFFFF
+#define EFUSE_USR_DATA4_S  0
+
+#define EFUSE_RD_USR_DATA5_REG          (DR_REG_EFUSE_BASE + 0x090)
+/* EFUSE_USR_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of BLOCK3 (user).*/
+#define EFUSE_USR_DATA5  0xFFFFFFFF
+#define EFUSE_USR_DATA5_M  ((EFUSE_USR_DATA5_V)<<(EFUSE_USR_DATA5_S))
+#define EFUSE_USR_DATA5_V  0xFFFFFFFF
+#define EFUSE_USR_DATA5_S  0
+
+#define EFUSE_RD_USR_DATA6_REG          (DR_REG_EFUSE_BASE + 0x094)
+/* EFUSE_USR_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of BLOCK3 (user).*/
+#define EFUSE_USR_DATA6  0xFFFFFFFF
+#define EFUSE_USR_DATA6_M  ((EFUSE_USR_DATA6_V)<<(EFUSE_USR_DATA6_S))
+#define EFUSE_USR_DATA6_V  0xFFFFFFFF
+#define EFUSE_USR_DATA6_S  0
+
+#define EFUSE_RD_USR_DATA7_REG          (DR_REG_EFUSE_BASE + 0x098)
+/* EFUSE_USR_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of BLOCK3 (user).*/
+#define EFUSE_USR_DATA7  0xFFFFFFFF
+#define EFUSE_USR_DATA7_M  ((EFUSE_USR_DATA7_V)<<(EFUSE_USR_DATA7_S))
+#define EFUSE_USR_DATA7_V  0xFFFFFFFF
+#define EFUSE_USR_DATA7_S  0
+
+#define EFUSE_RD_KEY0_DATA0_REG          (DR_REG_EFUSE_BASE + 0x09C)
+/* EFUSE_KEY0_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of KEY0.*/
+#define EFUSE_KEY0_DATA0  0xFFFFFFFF
+#define EFUSE_KEY0_DATA0_M  ((EFUSE_KEY0_DATA0_V)<<(EFUSE_KEY0_DATA0_S))
+#define EFUSE_KEY0_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA0_S  0
+
+#define EFUSE_RD_KEY0_DATA1_REG          (DR_REG_EFUSE_BASE + 0x0A0)
+/* EFUSE_KEY0_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of KEY0.*/
+#define EFUSE_KEY0_DATA1  0xFFFFFFFF
+#define EFUSE_KEY0_DATA1_M  ((EFUSE_KEY0_DATA1_V)<<(EFUSE_KEY0_DATA1_S))
+#define EFUSE_KEY0_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA1_S  0
+
+#define EFUSE_RD_KEY0_DATA2_REG          (DR_REG_EFUSE_BASE + 0x0A4)
+/* EFUSE_KEY0_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of KEY0.*/
+#define EFUSE_KEY0_DATA2  0xFFFFFFFF
+#define EFUSE_KEY0_DATA2_M  ((EFUSE_KEY0_DATA2_V)<<(EFUSE_KEY0_DATA2_S))
+#define EFUSE_KEY0_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA2_S  0
+
+#define EFUSE_RD_KEY0_DATA3_REG          (DR_REG_EFUSE_BASE + 0x0A8)
+/* EFUSE_KEY0_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of KEY0.*/
+#define EFUSE_KEY0_DATA3  0xFFFFFFFF
+#define EFUSE_KEY0_DATA3_M  ((EFUSE_KEY0_DATA3_V)<<(EFUSE_KEY0_DATA3_S))
+#define EFUSE_KEY0_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA3_S  0
+
+#define EFUSE_RD_KEY0_DATA4_REG          (DR_REG_EFUSE_BASE + 0x0AC)
+/* EFUSE_KEY0_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of KEY0.*/
+#define EFUSE_KEY0_DATA4  0xFFFFFFFF
+#define EFUSE_KEY0_DATA4_M  ((EFUSE_KEY0_DATA4_V)<<(EFUSE_KEY0_DATA4_S))
+#define EFUSE_KEY0_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA4_S  0
+
+#define EFUSE_RD_KEY0_DATA5_REG          (DR_REG_EFUSE_BASE + 0x0B0)
+/* EFUSE_KEY0_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of KEY0.*/
+#define EFUSE_KEY0_DATA5  0xFFFFFFFF
+#define EFUSE_KEY0_DATA5_M  ((EFUSE_KEY0_DATA5_V)<<(EFUSE_KEY0_DATA5_S))
+#define EFUSE_KEY0_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA5_S  0
+
+#define EFUSE_RD_KEY0_DATA6_REG          (DR_REG_EFUSE_BASE + 0x0B4)
+/* EFUSE_KEY0_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of KEY0.*/
+#define EFUSE_KEY0_DATA6  0xFFFFFFFF
+#define EFUSE_KEY0_DATA6_M  ((EFUSE_KEY0_DATA6_V)<<(EFUSE_KEY0_DATA6_S))
+#define EFUSE_KEY0_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA6_S  0
+
+#define EFUSE_RD_KEY0_DATA7_REG          (DR_REG_EFUSE_BASE + 0x0B8)
+/* EFUSE_KEY0_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of KEY0.*/
+#define EFUSE_KEY0_DATA7  0xFFFFFFFF
+#define EFUSE_KEY0_DATA7_M  ((EFUSE_KEY0_DATA7_V)<<(EFUSE_KEY0_DATA7_S))
+#define EFUSE_KEY0_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA7_S  0
+
+#define EFUSE_RD_KEY1_DATA0_REG          (DR_REG_EFUSE_BASE + 0x0BC)
+/* EFUSE_KEY1_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of KEY1.*/
+#define EFUSE_KEY1_DATA0  0xFFFFFFFF
+#define EFUSE_KEY1_DATA0_M  ((EFUSE_KEY1_DATA0_V)<<(EFUSE_KEY1_DATA0_S))
+#define EFUSE_KEY1_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA0_S  0
+
+#define EFUSE_RD_KEY1_DATA1_REG          (DR_REG_EFUSE_BASE + 0x0C0)
+/* EFUSE_KEY1_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of KEY1.*/
+#define EFUSE_KEY1_DATA1  0xFFFFFFFF
+#define EFUSE_KEY1_DATA1_M  ((EFUSE_KEY1_DATA1_V)<<(EFUSE_KEY1_DATA1_S))
+#define EFUSE_KEY1_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA1_S  0
+
+#define EFUSE_RD_KEY1_DATA2_REG          (DR_REG_EFUSE_BASE + 0x0C4)
+/* EFUSE_KEY1_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of KEY1.*/
+#define EFUSE_KEY1_DATA2  0xFFFFFFFF
+#define EFUSE_KEY1_DATA2_M  ((EFUSE_KEY1_DATA2_V)<<(EFUSE_KEY1_DATA2_S))
+#define EFUSE_KEY1_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA2_S  0
+
+#define EFUSE_RD_KEY1_DATA3_REG          (DR_REG_EFUSE_BASE + 0x0C8)
+/* EFUSE_KEY1_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of KEY1.*/
+#define EFUSE_KEY1_DATA3  0xFFFFFFFF
+#define EFUSE_KEY1_DATA3_M  ((EFUSE_KEY1_DATA3_V)<<(EFUSE_KEY1_DATA3_S))
+#define EFUSE_KEY1_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA3_S  0
+
+#define EFUSE_RD_KEY1_DATA4_REG          (DR_REG_EFUSE_BASE + 0x0CC)
+/* EFUSE_KEY1_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of KEY1.*/
+#define EFUSE_KEY1_DATA4  0xFFFFFFFF
+#define EFUSE_KEY1_DATA4_M  ((EFUSE_KEY1_DATA4_V)<<(EFUSE_KEY1_DATA4_S))
+#define EFUSE_KEY1_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA4_S  0
+
+#define EFUSE_RD_KEY1_DATA5_REG          (DR_REG_EFUSE_BASE + 0x0D0)
+/* EFUSE_KEY1_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of KEY1.*/
+#define EFUSE_KEY1_DATA5  0xFFFFFFFF
+#define EFUSE_KEY1_DATA5_M  ((EFUSE_KEY1_DATA5_V)<<(EFUSE_KEY1_DATA5_S))
+#define EFUSE_KEY1_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA5_S  0
+
+#define EFUSE_RD_KEY1_DATA6_REG          (DR_REG_EFUSE_BASE + 0x0D4)
+/* EFUSE_KEY1_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of KEY1.*/
+#define EFUSE_KEY1_DATA6  0xFFFFFFFF
+#define EFUSE_KEY1_DATA6_M  ((EFUSE_KEY1_DATA6_V)<<(EFUSE_KEY1_DATA6_S))
+#define EFUSE_KEY1_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA6_S  0
+
+#define EFUSE_RD_KEY1_DATA7_REG          (DR_REG_EFUSE_BASE + 0x0D8)
+/* EFUSE_KEY1_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of KEY1.*/
+#define EFUSE_KEY1_DATA7  0xFFFFFFFF
+#define EFUSE_KEY1_DATA7_M  ((EFUSE_KEY1_DATA7_V)<<(EFUSE_KEY1_DATA7_S))
+#define EFUSE_KEY1_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA7_S  0
+
+#define EFUSE_RD_KEY2_DATA0_REG          (DR_REG_EFUSE_BASE + 0x0DC)
+/* EFUSE_KEY2_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of KEY2.*/
+#define EFUSE_KEY2_DATA0  0xFFFFFFFF
+#define EFUSE_KEY2_DATA0_M  ((EFUSE_KEY2_DATA0_V)<<(EFUSE_KEY2_DATA0_S))
+#define EFUSE_KEY2_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA0_S  0
+
+#define EFUSE_RD_KEY2_DATA1_REG          (DR_REG_EFUSE_BASE + 0x0E0)
+/* EFUSE_KEY2_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of KEY2.*/
+#define EFUSE_KEY2_DATA1  0xFFFFFFFF
+#define EFUSE_KEY2_DATA1_M  ((EFUSE_KEY2_DATA1_V)<<(EFUSE_KEY2_DATA1_S))
+#define EFUSE_KEY2_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA1_S  0
+
+#define EFUSE_RD_KEY2_DATA2_REG          (DR_REG_EFUSE_BASE + 0x0E4)
+/* EFUSE_KEY2_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of KEY2.*/
+#define EFUSE_KEY2_DATA2  0xFFFFFFFF
+#define EFUSE_KEY2_DATA2_M  ((EFUSE_KEY2_DATA2_V)<<(EFUSE_KEY2_DATA2_S))
+#define EFUSE_KEY2_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA2_S  0
+
+#define EFUSE_RD_KEY2_DATA3_REG          (DR_REG_EFUSE_BASE + 0x0E8)
+/* EFUSE_KEY2_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of KEY2.*/
+#define EFUSE_KEY2_DATA3  0xFFFFFFFF
+#define EFUSE_KEY2_DATA3_M  ((EFUSE_KEY2_DATA3_V)<<(EFUSE_KEY2_DATA3_S))
+#define EFUSE_KEY2_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA3_S  0
+
+#define EFUSE_RD_KEY2_DATA4_REG          (DR_REG_EFUSE_BASE + 0x0EC)
+/* EFUSE_KEY2_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of KEY2.*/
+#define EFUSE_KEY2_DATA4  0xFFFFFFFF
+#define EFUSE_KEY2_DATA4_M  ((EFUSE_KEY2_DATA4_V)<<(EFUSE_KEY2_DATA4_S))
+#define EFUSE_KEY2_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA4_S  0
+
+#define EFUSE_RD_KEY2_DATA5_REG          (DR_REG_EFUSE_BASE + 0x0F0)
+/* EFUSE_KEY2_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of KEY2.*/
+#define EFUSE_KEY2_DATA5  0xFFFFFFFF
+#define EFUSE_KEY2_DATA5_M  ((EFUSE_KEY2_DATA5_V)<<(EFUSE_KEY2_DATA5_S))
+#define EFUSE_KEY2_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA5_S  0
+
+#define EFUSE_RD_KEY2_DATA6_REG          (DR_REG_EFUSE_BASE + 0x0F4)
+/* EFUSE_KEY2_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of KEY2.*/
+#define EFUSE_KEY2_DATA6  0xFFFFFFFF
+#define EFUSE_KEY2_DATA6_M  ((EFUSE_KEY2_DATA6_V)<<(EFUSE_KEY2_DATA6_S))
+#define EFUSE_KEY2_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA6_S  0
+
+#define EFUSE_RD_KEY2_DATA7_REG          (DR_REG_EFUSE_BASE + 0x0F8)
+/* EFUSE_KEY2_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of KEY2.*/
+#define EFUSE_KEY2_DATA7  0xFFFFFFFF
+#define EFUSE_KEY2_DATA7_M  ((EFUSE_KEY2_DATA7_V)<<(EFUSE_KEY2_DATA7_S))
+#define EFUSE_KEY2_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA7_S  0
+
+#define EFUSE_RD_KEY3_DATA0_REG          (DR_REG_EFUSE_BASE + 0x0FC)
+/* EFUSE_KEY3_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of KEY3.*/
+#define EFUSE_KEY3_DATA0  0xFFFFFFFF
+#define EFUSE_KEY3_DATA0_M  ((EFUSE_KEY3_DATA0_V)<<(EFUSE_KEY3_DATA0_S))
+#define EFUSE_KEY3_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA0_S  0
+
+#define EFUSE_RD_KEY3_DATA1_REG          (DR_REG_EFUSE_BASE + 0x100)
+/* EFUSE_KEY3_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of KEY3.*/
+#define EFUSE_KEY3_DATA1  0xFFFFFFFF
+#define EFUSE_KEY3_DATA1_M  ((EFUSE_KEY3_DATA1_V)<<(EFUSE_KEY3_DATA1_S))
+#define EFUSE_KEY3_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA1_S  0
+
+#define EFUSE_RD_KEY3_DATA2_REG          (DR_REG_EFUSE_BASE + 0x104)
+/* EFUSE_KEY3_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of KEY3.*/
+#define EFUSE_KEY3_DATA2  0xFFFFFFFF
+#define EFUSE_KEY3_DATA2_M  ((EFUSE_KEY3_DATA2_V)<<(EFUSE_KEY3_DATA2_S))
+#define EFUSE_KEY3_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA2_S  0
+
+#define EFUSE_RD_KEY3_DATA3_REG          (DR_REG_EFUSE_BASE + 0x108)
+/* EFUSE_KEY3_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of KEY3.*/
+#define EFUSE_KEY3_DATA3  0xFFFFFFFF
+#define EFUSE_KEY3_DATA3_M  ((EFUSE_KEY3_DATA3_V)<<(EFUSE_KEY3_DATA3_S))
+#define EFUSE_KEY3_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA3_S  0
+
+#define EFUSE_RD_KEY3_DATA4_REG          (DR_REG_EFUSE_BASE + 0x10C)
+/* EFUSE_KEY3_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of KEY3.*/
+#define EFUSE_KEY3_DATA4  0xFFFFFFFF
+#define EFUSE_KEY3_DATA4_M  ((EFUSE_KEY3_DATA4_V)<<(EFUSE_KEY3_DATA4_S))
+#define EFUSE_KEY3_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA4_S  0
+
+#define EFUSE_RD_KEY3_DATA5_REG          (DR_REG_EFUSE_BASE + 0x110)
+/* EFUSE_KEY3_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of KEY3.*/
+#define EFUSE_KEY3_DATA5  0xFFFFFFFF
+#define EFUSE_KEY3_DATA5_M  ((EFUSE_KEY3_DATA5_V)<<(EFUSE_KEY3_DATA5_S))
+#define EFUSE_KEY3_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA5_S  0
+
+#define EFUSE_RD_KEY3_DATA6_REG          (DR_REG_EFUSE_BASE + 0x114)
+/* EFUSE_KEY3_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of KEY3.*/
+#define EFUSE_KEY3_DATA6  0xFFFFFFFF
+#define EFUSE_KEY3_DATA6_M  ((EFUSE_KEY3_DATA6_V)<<(EFUSE_KEY3_DATA6_S))
+#define EFUSE_KEY3_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA6_S  0
+
+#define EFUSE_RD_KEY3_DATA7_REG          (DR_REG_EFUSE_BASE + 0x118)
+/* EFUSE_KEY3_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of KEY3.*/
+#define EFUSE_KEY3_DATA7  0xFFFFFFFF
+#define EFUSE_KEY3_DATA7_M  ((EFUSE_KEY3_DATA7_V)<<(EFUSE_KEY3_DATA7_S))
+#define EFUSE_KEY3_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA7_S  0
+
+#define EFUSE_RD_KEY4_DATA0_REG          (DR_REG_EFUSE_BASE + 0x11C)
+/* EFUSE_KEY4_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of KEY4.*/
+#define EFUSE_KEY4_DATA0  0xFFFFFFFF
+#define EFUSE_KEY4_DATA0_M  ((EFUSE_KEY4_DATA0_V)<<(EFUSE_KEY4_DATA0_S))
+#define EFUSE_KEY4_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA0_S  0
+
+#define EFUSE_RD_KEY4_DATA1_REG          (DR_REG_EFUSE_BASE + 0x120)
+/* EFUSE_KEY4_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of KEY4.*/
+#define EFUSE_KEY4_DATA1  0xFFFFFFFF
+#define EFUSE_KEY4_DATA1_M  ((EFUSE_KEY4_DATA1_V)<<(EFUSE_KEY4_DATA1_S))
+#define EFUSE_KEY4_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA1_S  0
+
+#define EFUSE_RD_KEY4_DATA2_REG          (DR_REG_EFUSE_BASE + 0x124)
+/* EFUSE_KEY4_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of KEY4.*/
+#define EFUSE_KEY4_DATA2  0xFFFFFFFF
+#define EFUSE_KEY4_DATA2_M  ((EFUSE_KEY4_DATA2_V)<<(EFUSE_KEY4_DATA2_S))
+#define EFUSE_KEY4_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA2_S  0
+
+#define EFUSE_RD_KEY4_DATA3_REG          (DR_REG_EFUSE_BASE + 0x128)
+/* EFUSE_KEY4_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of KEY4.*/
+#define EFUSE_KEY4_DATA3  0xFFFFFFFF
+#define EFUSE_KEY4_DATA3_M  ((EFUSE_KEY4_DATA3_V)<<(EFUSE_KEY4_DATA3_S))
+#define EFUSE_KEY4_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA3_S  0
+
+#define EFUSE_RD_KEY4_DATA4_REG          (DR_REG_EFUSE_BASE + 0x12C)
+/* EFUSE_KEY4_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of KEY4.*/
+#define EFUSE_KEY4_DATA4  0xFFFFFFFF
+#define EFUSE_KEY4_DATA4_M  ((EFUSE_KEY4_DATA4_V)<<(EFUSE_KEY4_DATA4_S))
+#define EFUSE_KEY4_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA4_S  0
+
+#define EFUSE_RD_KEY4_DATA5_REG          (DR_REG_EFUSE_BASE + 0x130)
+/* EFUSE_KEY4_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of KEY4.*/
+#define EFUSE_KEY4_DATA5  0xFFFFFFFF
+#define EFUSE_KEY4_DATA5_M  ((EFUSE_KEY4_DATA5_V)<<(EFUSE_KEY4_DATA5_S))
+#define EFUSE_KEY4_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA5_S  0
+
+#define EFUSE_RD_KEY4_DATA6_REG          (DR_REG_EFUSE_BASE + 0x134)
+/* EFUSE_KEY4_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of KEY4.*/
+#define EFUSE_KEY4_DATA6  0xFFFFFFFF
+#define EFUSE_KEY4_DATA6_M  ((EFUSE_KEY4_DATA6_V)<<(EFUSE_KEY4_DATA6_S))
+#define EFUSE_KEY4_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA6_S  0
+
+#define EFUSE_RD_KEY4_DATA7_REG          (DR_REG_EFUSE_BASE + 0x138)
+/* EFUSE_KEY4_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of KEY4.*/
+#define EFUSE_KEY4_DATA7  0xFFFFFFFF
+#define EFUSE_KEY4_DATA7_M  ((EFUSE_KEY4_DATA7_V)<<(EFUSE_KEY4_DATA7_S))
+#define EFUSE_KEY4_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA7_S  0
+
+#define EFUSE_RD_KEY5_DATA0_REG          (DR_REG_EFUSE_BASE + 0x13C)
+/* EFUSE_KEY5_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the zeroth 32 bits of KEY5.*/
+#define EFUSE_KEY5_DATA0  0xFFFFFFFF
+#define EFUSE_KEY5_DATA0_M  ((EFUSE_KEY5_DATA0_V)<<(EFUSE_KEY5_DATA0_S))
+#define EFUSE_KEY5_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA0_S  0
+
+#define EFUSE_RD_KEY5_DATA1_REG          (DR_REG_EFUSE_BASE + 0x140)
+/* EFUSE_KEY5_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first 32 bits of KEY5.*/
+#define EFUSE_KEY5_DATA1  0xFFFFFFFF
+#define EFUSE_KEY5_DATA1_M  ((EFUSE_KEY5_DATA1_V)<<(EFUSE_KEY5_DATA1_S))
+#define EFUSE_KEY5_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA1_S  0
+
+#define EFUSE_RD_KEY5_DATA2_REG          (DR_REG_EFUSE_BASE + 0x144)
+/* EFUSE_KEY5_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the second 32 bits of KEY5.*/
+#define EFUSE_KEY5_DATA2  0xFFFFFFFF
+#define EFUSE_KEY5_DATA2_M  ((EFUSE_KEY5_DATA2_V)<<(EFUSE_KEY5_DATA2_S))
+#define EFUSE_KEY5_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA2_S  0
+
+#define EFUSE_RD_KEY5_DATA3_REG          (DR_REG_EFUSE_BASE + 0x148)
+/* EFUSE_KEY5_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the third 32 bits of KEY5.*/
+#define EFUSE_KEY5_DATA3  0xFFFFFFFF
+#define EFUSE_KEY5_DATA3_M  ((EFUSE_KEY5_DATA3_V)<<(EFUSE_KEY5_DATA3_S))
+#define EFUSE_KEY5_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA3_S  0
+
+#define EFUSE_RD_KEY5_DATA4_REG          (DR_REG_EFUSE_BASE + 0x14C)
+/* EFUSE_KEY5_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fourth 32 bits of KEY5.*/
+#define EFUSE_KEY5_DATA4  0xFFFFFFFF
+#define EFUSE_KEY5_DATA4_M  ((EFUSE_KEY5_DATA4_V)<<(EFUSE_KEY5_DATA4_S))
+#define EFUSE_KEY5_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA4_S  0
+
+#define EFUSE_RD_KEY5_DATA5_REG          (DR_REG_EFUSE_BASE + 0x150)
+/* EFUSE_KEY5_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the fifth 32 bits of KEY5.*/
+#define EFUSE_KEY5_DATA5  0xFFFFFFFF
+#define EFUSE_KEY5_DATA5_M  ((EFUSE_KEY5_DATA5_V)<<(EFUSE_KEY5_DATA5_S))
+#define EFUSE_KEY5_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA5_S  0
+
+#define EFUSE_RD_KEY5_DATA6_REG          (DR_REG_EFUSE_BASE + 0x154)
+/* EFUSE_KEY5_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the sixth 32 bits of KEY5.*/
+#define EFUSE_KEY5_DATA6  0xFFFFFFFF
+#define EFUSE_KEY5_DATA6_M  ((EFUSE_KEY5_DATA6_V)<<(EFUSE_KEY5_DATA6_S))
+#define EFUSE_KEY5_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA6_S  0
+
+#define EFUSE_RD_KEY5_DATA7_REG          (DR_REG_EFUSE_BASE + 0x158)
+/* EFUSE_KEY5_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the seventh 32 bits of KEY5.*/
+#define EFUSE_KEY5_DATA7  0xFFFFFFFF
+#define EFUSE_KEY5_DATA7_M  ((EFUSE_KEY5_DATA7_V)<<(EFUSE_KEY5_DATA7_S))
+#define EFUSE_KEY5_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA7_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA0_REG          (DR_REG_EFUSE_BASE + 0x15C)
+/* EFUSE_SYS_DATA_PART2_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data.*/
+#define EFUSE_SYS_DATA_PART2_0  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_0_M  ((EFUSE_SYS_DATA_PART2_0_V)<<(EFUSE_SYS_DATA_PART2_0_S))
+#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_0_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA1_REG          (DR_REG_EFUSE_BASE + 0x160)
+/* EFUSE_SYS_DATA_PART2_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data.*/
+#define EFUSE_SYS_DATA_PART2_1  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_1_M  ((EFUSE_SYS_DATA_PART2_1_V)<<(EFUSE_SYS_DATA_PART2_1_S))
+#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_1_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA2_REG          (DR_REG_EFUSE_BASE + 0x164)
+/* EFUSE_SYS_DATA_PART2_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data.*/
+#define EFUSE_SYS_DATA_PART2_2  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_2_M  ((EFUSE_SYS_DATA_PART2_2_V)<<(EFUSE_SYS_DATA_PART2_2_S))
+#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_2_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA3_REG          (DR_REG_EFUSE_BASE + 0x168)
+/* EFUSE_SYS_DATA_PART2_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data.*/
+#define EFUSE_SYS_DATA_PART2_3  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_3_M  ((EFUSE_SYS_DATA_PART2_3_V)<<(EFUSE_SYS_DATA_PART2_3_S))
+#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_3_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA4_REG          (DR_REG_EFUSE_BASE + 0x16C)
+/* EFUSE_SYS_DATA_PART2_4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data.*/
+#define EFUSE_SYS_DATA_PART2_4  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_4_M  ((EFUSE_SYS_DATA_PART2_4_V)<<(EFUSE_SYS_DATA_PART2_4_S))
+#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_4_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA5_REG          (DR_REG_EFUSE_BASE + 0x170)
+/* EFUSE_SYS_DATA_PART2_5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data.*/
+#define EFUSE_SYS_DATA_PART2_5  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_5_M  ((EFUSE_SYS_DATA_PART2_5_V)<<(EFUSE_SYS_DATA_PART2_5_S))
+#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_5_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA6_REG          (DR_REG_EFUSE_BASE + 0x174)
+/* EFUSE_SYS_DATA_PART2_6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data.*/
+#define EFUSE_SYS_DATA_PART2_6  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_6_M  ((EFUSE_SYS_DATA_PART2_6_V)<<(EFUSE_SYS_DATA_PART2_6_S))
+#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_6_S  0
+
+#define EFUSE_RD_SYS_PART2_DATA7_REG          (DR_REG_EFUSE_BASE + 0x178)
+/* EFUSE_SYS_DATA_PART2_7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the $nth 32 bits of the 2nd part of system data.*/
+#define EFUSE_SYS_DATA_PART2_7  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_7_M  ((EFUSE_SYS_DATA_PART2_7_V)<<(EFUSE_SYS_DATA_PART2_7_S))
+#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART2_7_S  0
+
+#define EFUSE_RD_REPEAT_ERR0_REG          (DR_REG_EFUSE_BASE + 0x17C)
+/* EFUSE_POWER_GLITCH_DSENSE_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */
+/*description: If any bit in POWER_GLITCH_DSENSE is 1  then it indicates a programming error.*/
+#define EFUSE_POWER_GLITCH_DSENSE_ERR  0x00000003
+#define EFUSE_POWER_GLITCH_DSENSE_ERR_M  ((EFUSE_POWER_GLITCH_DSENSE_ERR_V)<<(EFUSE_POWER_GLITCH_DSENSE_ERR_S))
+#define EFUSE_POWER_GLITCH_DSENSE_ERR_V  0x3
+#define EFUSE_POWER_GLITCH_DSENSE_ERR_S  30
+/* EFUSE_POWERGLITCH_EN_ERR : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: If POWERGLITCH_EN is 1  then it indicates a programming error.*/
+#define EFUSE_POWERGLITCH_EN_ERR  (BIT(29))
+#define EFUSE_POWERGLITCH_EN_ERR_M  (BIT(29))
+#define EFUSE_POWERGLITCH_EN_ERR_V  0x1
+#define EFUSE_POWERGLITCH_EN_ERR_S  29
+/* EFUSE_BTLC_GPIO_ENABLE_ERR : RO ;bitpos:[28:27] ;default: 2'h0 ; */
+/*description: If any bit in BTLC_GPIO_ENABLE is 1  then it indicates a programming error.*/
+#define EFUSE_BTLC_GPIO_ENABLE_ERR  0x00000003
+#define EFUSE_BTLC_GPIO_ENABLE_ERR_M  ((EFUSE_BTLC_GPIO_ENABLE_ERR_V)<<(EFUSE_BTLC_GPIO_ENABLE_ERR_S))
+#define EFUSE_BTLC_GPIO_ENABLE_ERR_V  0x3
+#define EFUSE_BTLC_GPIO_ENABLE_ERR_S  27
+/* EFUSE_VDD_SPI_AS_GPIO_ERR : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: If VDD_SPI_AS_GPIO is 1  then it indicates a programming error.*/
+#define EFUSE_VDD_SPI_AS_GPIO_ERR  (BIT(26))
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_M  (BIT(26))
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_V  0x1
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_S  26
+/* EFUSE_USB_EXCHG_PINS_ERR : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: If USB_EXCHG_PINS is 1  then it indicates a programming error.*/
+#define EFUSE_USB_EXCHG_PINS_ERR  (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_ERR_M  (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_ERR_V  0x1
+#define EFUSE_USB_EXCHG_PINS_ERR_S  25
+/* EFUSE_USB_DREFL_ERR : RO ;bitpos:[24:23] ;default: 2'h0 ; */
+/*description: If any bit in USB_DREFL is 1  then it indicates a programming error.*/
+#define EFUSE_USB_DREFL_ERR  0x00000003
+#define EFUSE_USB_DREFL_ERR_M  ((EFUSE_USB_DREFL_ERR_V)<<(EFUSE_USB_DREFL_ERR_S))
+#define EFUSE_USB_DREFL_ERR_V  0x3
+#define EFUSE_USB_DREFL_ERR_S  23
+/* EFUSE_USB_DREFH_ERR : RO ;bitpos:[22:21] ;default: 2'h0 ; */
+/*description: If any bit in USB_DREFH is 1  then it indicates a programming error.*/
+#define EFUSE_USB_DREFH_ERR  0x00000003
+#define EFUSE_USB_DREFH_ERR_M  ((EFUSE_USB_DREFH_ERR_V)<<(EFUSE_USB_DREFH_ERR_S))
+#define EFUSE_USB_DREFH_ERR_V  0x3
+#define EFUSE_USB_DREFH_ERR_S  21
+/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR  (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
+/* EFUSE_DIS_PAD_JTAG_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: If DIS_PAD_JTAG is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_PAD_JTAG_ERR  (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_ERR_M  (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_ERR_V  0x1
+#define EFUSE_DIS_PAD_JTAG_ERR_S  19
+/* EFUSE_SOFT_DIS_JTAG_ERR : RO ;bitpos:[18:16] ;default: 3'h0 ; */
+/*description: If SOFT_DIS_JTAG is 1  then it indicates a programming error.*/
+#define EFUSE_SOFT_DIS_JTAG_ERR  0x00000007
+#define EFUSE_SOFT_DIS_JTAG_ERR_M  ((EFUSE_SOFT_DIS_JTAG_ERR_V)<<(EFUSE_SOFT_DIS_JTAG_ERR_S))
+#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x7
+#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
+/* EFUSE_JTAG_SEL_ENABLE_ERR : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: If JTAG_SEL_ENABLE is 1  then it indicates a programming error.*/
+#define EFUSE_JTAG_SEL_ENABLE_ERR  (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x1
+#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
+/* EFUSE_DIS_TWAI_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: If DIS_TWAI is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_TWAI_ERR  (BIT(14))
+#define EFUSE_DIS_TWAI_ERR_M  (BIT(14))
+#define EFUSE_DIS_TWAI_ERR_V  0x1
+#define EFUSE_DIS_TWAI_ERR_S  14
+/* EFUSE_RPT4_RESERVED6_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Reserved..*/
+#define EFUSE_RPT4_RESERVED6_ERR    (BIT(13))
+#define EFUSE_RPT4_RESERVED6_ERR_M  (BIT(13))
+#define EFUSE_RPT4_RESERVED6_ERR_V  0x1
+#define EFUSE_RPT4_RESERVED6_ERR_S  13
+/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: If DIS_FORCE_DOWNLOAD is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR  (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x1
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
+/* EFUSE_DIS_USB_DEVICE_ERR : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: If DIS_USB_DEVICE is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_USB_DEVICE_ERR  (BIT(11))
+#define EFUSE_DIS_USB_DEVICE_ERR_M  (BIT(11))
+#define EFUSE_DIS_USB_DEVICE_ERR_V  0x1
+#define EFUSE_DIS_USB_DEVICE_ERR_S  11
+/* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: If DIS_DOWNLOAD_ICACHE is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_DOWNLOAD_ICACHE  (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_M  (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_ICACHE_S  10
+/* EFUSE_DIS_USB_JTAG_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: If DIS_USB_JTAG is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_USB_JTAG_ERR  (BIT(9))
+#define EFUSE_DIS_USB_JTAG_ERR_M  (BIT(9))
+#define EFUSE_DIS_USB_JTAG_ERR_V  0x1
+#define EFUSE_DIS_USB_JTAG_ERR_S  9
+/* EFUSE_DIS_ICACHE_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: If DIS_ICACHE is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_ICACHE_ERR  (BIT(8))
+#define EFUSE_DIS_ICACHE_ERR_M  (BIT(8))
+#define EFUSE_DIS_ICACHE_ERR_V  0x1
+#define EFUSE_DIS_ICACHE_ERR_S  8
+/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: If DIS_RTC_RAM_BOOT is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR  (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M  (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V  0x1
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S  7
+/* EFUSE_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */
+/*description: If any bit in RD_DIS is 1  then it indicates a programming error.*/
+#define EFUSE_RD_DIS_ERR  0x0000007F
+#define EFUSE_RD_DIS_ERR_M  ((EFUSE_RD_DIS_ERR_V)<<(EFUSE_RD_DIS_ERR_S))
+#define EFUSE_RD_DIS_ERR_V  0x7F
+#define EFUSE_RD_DIS_ERR_S  0
+
+#define EFUSE_RD_REPEAT_ERR1_REG          (DR_REG_EFUSE_BASE + 0x180)
+/* EFUSE_KEY_PURPOSE_1_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: If any bit in KEY_PURPOSE_1 is 1  then it indicates a programming error.*/
+#define EFUSE_KEY_PURPOSE_1_ERR  0x0000000F
+#define EFUSE_KEY_PURPOSE_1_ERR_M  ((EFUSE_KEY_PURPOSE_1_ERR_V)<<(EFUSE_KEY_PURPOSE_1_ERR_S))
+#define EFUSE_KEY_PURPOSE_1_ERR_V  0xF
+#define EFUSE_KEY_PURPOSE_1_ERR_S  28
+/* EFUSE_KEY_PURPOSE_0_ERR : RO ;bitpos:[27:24] ;default: 4'h0 ; */
+/*description: If any bit in KEY_PURPOSE_0 is 1  then it indicates a programming error.*/
+#define EFUSE_KEY_PURPOSE_0_ERR  0x0000000F
+#define EFUSE_KEY_PURPOSE_0_ERR_M  ((EFUSE_KEY_PURPOSE_0_ERR_V)<<(EFUSE_KEY_PURPOSE_0_ERR_S))
+#define EFUSE_KEY_PURPOSE_0_ERR_V  0xF
+#define EFUSE_KEY_PURPOSE_0_ERR_S  24
+/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: If SECURE_BOOT_KEY_REVOKE2 is 1  then it indicates a programming error.*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR  (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
+/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: If SECURE_BOOT_KEY_REVOKE1 is 1  then it indicates a programming error.*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR  (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
+/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: If SECURE_BOOT_KEY_REVOKE0 is 1  then it indicates a programming error.*/
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR  (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
+/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: If any bit in SPI_BOOT_CRYPT_CNT is 1  then it indicates a programming error.*/
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR  0x00000007
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  ((EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S))
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x7
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
+/* EFUSE_WDT_DELAY_SEL_ERR : RO ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: If any bit in WDT_DELAY_SEL is 1  then it indicates a programming error.*/
+#define EFUSE_WDT_DELAY_SEL_ERR  0x00000003
+#define EFUSE_WDT_DELAY_SEL_ERR_M  ((EFUSE_WDT_DELAY_SEL_ERR_V)<<(EFUSE_WDT_DELAY_SEL_ERR_S))
+#define EFUSE_WDT_DELAY_SEL_ERR_V  0x3
+#define EFUSE_WDT_DELAY_SEL_ERR_S  16
+/* EFUSE_RPT4_RESERVED2_ERR : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: Reserved.*/
+#define EFUSE_RPT4_RESERVED2_ERR  0x0000FFFF
+#define EFUSE_RPT4_RESERVED2_ERR_M  ((EFUSE_RPT4_RESERVED2_ERR_V)<<(EFUSE_RPT4_RESERVED2_ERR_S))
+#define EFUSE_RPT4_RESERVED2_ERR_V  0xFFFF
+#define EFUSE_RPT4_RESERVED2_ERR_S  0
+
+#define EFUSE_RD_REPEAT_ERR2_REG          (DR_REG_EFUSE_BASE + 0x184)
+/* EFUSE_FLASH_TPUW_ERR : RO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: If any bit in FLASH_TPUM is 1  then it indicates a programming error.*/
+#define EFUSE_FLASH_TPUW_ERR  0x0000000F
+#define EFUSE_FLASH_TPUW_ERR_M  ((EFUSE_FLASH_TPUW_ERR_V)<<(EFUSE_FLASH_TPUW_ERR_S))
+#define EFUSE_FLASH_TPUW_ERR_V  0xF
+#define EFUSE_FLASH_TPUW_ERR_S  28
+/* EFUSE_RPT4_RESERVED0_ERR : RO ;bitpos:[27:22] ;default: 6'h0 ; */
+/*description: Reserved.*/
+#define EFUSE_RPT4_RESERVED0_ERR  0x0000003F
+#define EFUSE_RPT4_RESERVED0_ERR_M  ((EFUSE_RPT4_RESERVED0_ERR_V)<<(EFUSE_RPT4_RESERVED0_ERR_S))
+#define EFUSE_RPT4_RESERVED0_ERR_V  0x3F
+#define EFUSE_RPT4_RESERVED0_ERR_S  22
+/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: If SECURE_BOOT_AGGRESSIVE_REVOKE is 1  then it indicates a programming error.*/
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR  (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x1
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
+/* EFUSE_SECURE_BOOT_EN_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: If SECURE_BOOT_EN is 1  then it indicates a programming error.*/
+#define EFUSE_SECURE_BOOT_EN_ERR  (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_ERR_M  (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_ERR_V  0x1
+#define EFUSE_SECURE_BOOT_EN_ERR_S  20
+/* EFUSE_RPT4_RESERVED3_ERR : RO ;bitpos:[19:16] ;default: 4'h0 ; */
+/*description: Reserved.*/
+#define EFUSE_RPT4_RESERVED3_ERR  0x0000000F
+#define EFUSE_RPT4_RESERVED3_ERR_M  ((EFUSE_RPT4_RESERVED3_ERR_V)<<(EFUSE_RPT4_RESERVED3_ERR_S))
+#define EFUSE_RPT4_RESERVED3_ERR_V  0xF
+#define EFUSE_RPT4_RESERVED3_ERR_S  16
+/* EFUSE_KEY_PURPOSE_5_ERR : RO ;bitpos:[15:12] ;default: 4'h0 ; */
+/*description: If any bit in KEY_PURPOSE_5 is 1  then it indicates a programming error.*/
+#define EFUSE_KEY_PURPOSE_5_ERR  0x0000000F
+#define EFUSE_KEY_PURPOSE_5_ERR_M  ((EFUSE_KEY_PURPOSE_5_ERR_V)<<(EFUSE_KEY_PURPOSE_5_ERR_S))
+#define EFUSE_KEY_PURPOSE_5_ERR_V  0xF
+#define EFUSE_KEY_PURPOSE_5_ERR_S  12
+/* EFUSE_KEY_PURPOSE_4_ERR : RO ;bitpos:[11:8] ;default: 4'h0 ; */
+/*description: If any bit in KEY_PURPOSE_4 is 1  then it indicates a programming error.*/
+#define EFUSE_KEY_PURPOSE_4_ERR  0x0000000F
+#define EFUSE_KEY_PURPOSE_4_ERR_M  ((EFUSE_KEY_PURPOSE_4_ERR_V)<<(EFUSE_KEY_PURPOSE_4_ERR_S))
+#define EFUSE_KEY_PURPOSE_4_ERR_V  0xF
+#define EFUSE_KEY_PURPOSE_4_ERR_S  8
+/* EFUSE_KEY_PURPOSE_3_ERR : RO ;bitpos:[7:4] ;default: 4'h0 ; */
+/*description: If any bit in KEY_PURPOSE_3 is 1  then it indicates a programming error.*/
+#define EFUSE_KEY_PURPOSE_3_ERR  0x0000000F
+#define EFUSE_KEY_PURPOSE_3_ERR_M  ((EFUSE_KEY_PURPOSE_3_ERR_V)<<(EFUSE_KEY_PURPOSE_3_ERR_S))
+#define EFUSE_KEY_PURPOSE_3_ERR_V  0xF
+#define EFUSE_KEY_PURPOSE_3_ERR_S  4
+/* EFUSE_KEY_PURPOSE_2_ERR : RO ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: If any bit in KEY_PURPOSE_2 is 1  then it indicates a programming error.*/
+#define EFUSE_KEY_PURPOSE_2_ERR  0x0000000F
+#define EFUSE_KEY_PURPOSE_2_ERR_M  ((EFUSE_KEY_PURPOSE_2_ERR_V)<<(EFUSE_KEY_PURPOSE_2_ERR_S))
+#define EFUSE_KEY_PURPOSE_2_ERR_V  0xF
+#define EFUSE_KEY_PURPOSE_2_ERR_S  0
+
+#define EFUSE_RD_REPEAT_ERR3_REG          (DR_REG_EFUSE_BASE + 0x188)
+/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */
+/*description: Reserved.*/
+#define EFUSE_RPT4_RESERVED1_ERR  0x00000003
+#define EFUSE_RPT4_RESERVED1_ERR_M  ((EFUSE_RPT4_RESERVED1_ERR_V)<<(EFUSE_RPT4_RESERVED1_ERR_S))
+#define EFUSE_RPT4_RESERVED1_ERR_V  0x3
+#define EFUSE_RPT4_RESERVED1_ERR_S  30
+/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[29:14] ;default: 16'h0 ; */
+/*description: If any bit in SECURE_VERSION is 1  then it indicates a programming error.*/
+#define EFUSE_SECURE_VERSION_ERR  0x0000FFFF
+#define EFUSE_SECURE_VERSION_ERR_M  ((EFUSE_SECURE_VERSION_ERR_V)<<(EFUSE_SECURE_VERSION_ERR_S))
+#define EFUSE_SECURE_VERSION_ERR_V  0xFFFF
+#define EFUSE_SECURE_VERSION_ERR_S  14
+/* EFUSE_FORCE_SEND_RESUME_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: If FORCE_SEND_RESUME is 1  then it indicates a programming error.*/
+#define EFUSE_FORCE_SEND_RESUME_ERR  (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_ERR_M  (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x1
+#define EFUSE_FORCE_SEND_RESUME_ERR_S  13
+/* EFUSE_FLASH_ECC_EN : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: If FLASH_ECC_EN_ERR is 1  then it indicates a programming error.*/
+#define EFUSE_FLASH_ECC_EN  (BIT(12))
+#define EFUSE_FLASH_ECC_EN_M  (BIT(12))
+#define EFUSE_FLASH_ECC_EN_V  0x1
+#define EFUSE_FLASH_ECC_EN_S  12
+/* EFUSE_FLASH_PAGE_SIZE : RO ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: If any bits in FLASH_PAGE_SIZE is 1  then it indicates a programming error.*/
+#define EFUSE_FLASH_PAGE_SIZE  0x00000003
+#define EFUSE_FLASH_PAGE_SIZE_M  ((EFUSE_FLASH_PAGE_SIZE_V)<<(EFUSE_FLASH_PAGE_SIZE_S))
+#define EFUSE_FLASH_PAGE_SIZE_V  0x3
+#define EFUSE_FLASH_PAGE_SIZE_S  10
+/* EFUSE_FLASH_TYPE_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: If FLASH_TYPE is 1  then it indicates a programming error.*/
+#define EFUSE_FLASH_TYPE_ERR  (BIT(9))
+#define EFUSE_FLASH_TYPE_ERR_M  (BIT(9))
+#define EFUSE_FLASH_TYPE_ERR_V  0x1
+#define EFUSE_FLASH_TYPE_ERR_S  9
+/* EFUSE_PIN_POWER_SELECTION_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: If PIN_POWER_SELECTION is 1  then it indicates a programming error.*/
+#define EFUSE_PIN_POWER_SELECTION_ERR  (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_ERR_M  (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_ERR_V  0x1
+#define EFUSE_PIN_POWER_SELECTION_ERR_S  8
+/* EFUSE_UART_PRINT_CONTROL_ERR : RO ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: If any bit in UART_PRINT_CONTROL is 1  then it indicates a programming error.*/
+#define EFUSE_UART_PRINT_CONTROL_ERR  0x00000003
+#define EFUSE_UART_PRINT_CONTROL_ERR_M  ((EFUSE_UART_PRINT_CONTROL_ERR_V)<<(EFUSE_UART_PRINT_CONTROL_ERR_S))
+#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x3
+#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
+/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: If ENABLE_SECURITY_DOWNLOAD is 1  then it indicates a programming error.*/
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR  (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x1
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
+/* EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: If DIS_USB_DOWNLOAD_MODE is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR  (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M  (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V  0x1
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S  4
+/* EFUSE_FLASH_ECC_MODE_ERR : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: If FLASH_ECC_MODE is 1  then it indicates a programming error.*/
+#define EFUSE_FLASH_ECC_MODE_ERR  (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_ERR_M  (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_ERR_V  0x1
+#define EFUSE_FLASH_ECC_MODE_ERR_S  3
+/* EFUSE_UART_PRINT_CHANNEL_ERR : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: If UART_PRINT_CHANNEL is 1  then it indicates a programming error.*/
+#define EFUSE_UART_PRINT_CHANNEL_ERR  (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_ERR_M  (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_ERR_V  0x1
+#define EFUSE_UART_PRINT_CHANNEL_ERR_S  2
+/* EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: If DIS_LEGACY_SPI_BOOT is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR  (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M  (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V  0x1
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S  1
+/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: If DIS_DOWNLOAD_MODE is 1  then it indicates a programming error.*/
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR  (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
+
+#define EFUSE_RD_REPEAT_ERR4_REG          (DR_REG_EFUSE_BASE + 0x190)
+/* EFUSE_RPT4_RESERVED4_ERR : RO ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Reserved.*/
+#define EFUSE_RPT4_RESERVED4_ERR  0x00FFFFFF
+#define EFUSE_RPT4_RESERVED4_ERR_M  ((EFUSE_RPT4_RESERVED4_ERR_V)<<(EFUSE_RPT4_RESERVED4_ERR_S))
+#define EFUSE_RPT4_RESERVED4_ERR_V  0xFFFFFF
+#define EFUSE_RPT4_RESERVED4_ERR_S  0
+
+#define EFUSE_RD_RS_ERR0_REG          (DR_REG_EFUSE_BASE + 0x1C0)
+/* EFUSE_KEY4_FAIL : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of key$n is reliable 1:
+ Means that programming key$n failed and the number of error bytes is over 6.*/
+#define EFUSE_KEY4_FAIL  (BIT(31))
+#define EFUSE_KEY4_FAIL_M  (BIT(31))
+#define EFUSE_KEY4_FAIL_V  0x1
+#define EFUSE_KEY4_FAIL_S  31
+/* EFUSE_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes.*/
+#define EFUSE_KEY4_ERR_NUM  0x00000007
+#define EFUSE_KEY4_ERR_NUM_M  ((EFUSE_KEY4_ERR_NUM_V)<<(EFUSE_KEY4_ERR_NUM_S))
+#define EFUSE_KEY4_ERR_NUM_V  0x7
+#define EFUSE_KEY4_ERR_NUM_S  28
+/* EFUSE_KEY3_FAIL : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of key$n is reliable 1:
+ Means that programming key$n failed and the number of error bytes is over 6.*/
+#define EFUSE_KEY3_FAIL  (BIT(27))
+#define EFUSE_KEY3_FAIL_M  (BIT(27))
+#define EFUSE_KEY3_FAIL_V  0x1
+#define EFUSE_KEY3_FAIL_S  27
+/* EFUSE_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes.*/
+#define EFUSE_KEY3_ERR_NUM  0x00000007
+#define EFUSE_KEY3_ERR_NUM_M  ((EFUSE_KEY3_ERR_NUM_V)<<(EFUSE_KEY3_ERR_NUM_S))
+#define EFUSE_KEY3_ERR_NUM_V  0x7
+#define EFUSE_KEY3_ERR_NUM_S  24
+/* EFUSE_KEY2_FAIL : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of key$n is reliable 1:
+ Means that programming key$n failed and the number of error bytes is over 6.*/
+#define EFUSE_KEY2_FAIL  (BIT(23))
+#define EFUSE_KEY2_FAIL_M  (BIT(23))
+#define EFUSE_KEY2_FAIL_V  0x1
+#define EFUSE_KEY2_FAIL_S  23
+/* EFUSE_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes.*/
+#define EFUSE_KEY2_ERR_NUM  0x00000007
+#define EFUSE_KEY2_ERR_NUM_M  ((EFUSE_KEY2_ERR_NUM_V)<<(EFUSE_KEY2_ERR_NUM_S))
+#define EFUSE_KEY2_ERR_NUM_V  0x7
+#define EFUSE_KEY2_ERR_NUM_S  20
+/* EFUSE_KEY1_FAIL : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of key$n is reliable 1:
+ Means that programming key$n failed and the number of error bytes is over 6.*/
+#define EFUSE_KEY1_FAIL  (BIT(19))
+#define EFUSE_KEY1_FAIL_M  (BIT(19))
+#define EFUSE_KEY1_FAIL_V  0x1
+#define EFUSE_KEY1_FAIL_S  19
+/* EFUSE_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes.*/
+#define EFUSE_KEY1_ERR_NUM  0x00000007
+#define EFUSE_KEY1_ERR_NUM_M  ((EFUSE_KEY1_ERR_NUM_V)<<(EFUSE_KEY1_ERR_NUM_S))
+#define EFUSE_KEY1_ERR_NUM_V  0x7
+#define EFUSE_KEY1_ERR_NUM_S  16
+/* EFUSE_KEY0_FAIL : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of key$n is reliable 1:
+ Means that programming key$n failed and the number of error bytes is over 6.*/
+#define EFUSE_KEY0_FAIL  (BIT(15))
+#define EFUSE_KEY0_FAIL_M  (BIT(15))
+#define EFUSE_KEY0_FAIL_V  0x1
+#define EFUSE_KEY0_FAIL_S  15
+/* EFUSE_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes.*/
+#define EFUSE_KEY0_ERR_NUM  0x00000007
+#define EFUSE_KEY0_ERR_NUM_M  ((EFUSE_KEY0_ERR_NUM_V)<<(EFUSE_KEY0_ERR_NUM_S))
+#define EFUSE_KEY0_ERR_NUM_V  0x7
+#define EFUSE_KEY0_ERR_NUM_S  12
+/* EFUSE_USR_DATA_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the user data is reliable 1: Means
+ that programming user data failed and the number of error bytes is over 6.*/
+#define EFUSE_USR_DATA_FAIL  (BIT(11))
+#define EFUSE_USR_DATA_FAIL_M  (BIT(11))
+#define EFUSE_USR_DATA_FAIL_V  0x1
+#define EFUSE_USR_DATA_FAIL_S  11
+/* EFUSE_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes.*/
+#define EFUSE_USR_DATA_ERR_NUM  0x00000007
+#define EFUSE_USR_DATA_ERR_NUM_M  ((EFUSE_USR_DATA_ERR_NUM_V)<<(EFUSE_USR_DATA_ERR_NUM_S))
+#define EFUSE_USR_DATA_ERR_NUM_V  0x7
+#define EFUSE_USR_DATA_ERR_NUM_S  8
+/* EFUSE_SYS_PART1_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of system part1 is reliable
+ 1: Means that programming user data failed and the number of error bytes is over 6.*/
+#define EFUSE_SYS_PART1_FAIL  (BIT(7))
+#define EFUSE_SYS_PART1_FAIL_M  (BIT(7))
+#define EFUSE_SYS_PART1_FAIL_V  0x1
+#define EFUSE_SYS_PART1_FAIL_S  7
+/* EFUSE_SYS_PART1_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes.*/
+#define EFUSE_SYS_PART1_NUM  0x00000007
+#define EFUSE_SYS_PART1_NUM_M  ((EFUSE_SYS_PART1_NUM_V)<<(EFUSE_SYS_PART1_NUM_S))
+#define EFUSE_SYS_PART1_NUM_V  0x7
+#define EFUSE_SYS_PART1_NUM_S  4
+/* EFUSE_MAC_SPI_8M_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of MAC_SPI_8M is reliable
+ 1: Means that programming user data failed and the number of error bytes is over 6.*/
+#define EFUSE_MAC_SPI_8M_FAIL  (BIT(3))
+#define EFUSE_MAC_SPI_8M_FAIL_M  (BIT(3))
+#define EFUSE_MAC_SPI_8M_FAIL_V  0x1
+#define EFUSE_MAC_SPI_8M_FAIL_S  3
+/* EFUSE_MAC_SPI_8M_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes.*/
+#define EFUSE_MAC_SPI_8M_ERR_NUM  0x00000007
+#define EFUSE_MAC_SPI_8M_ERR_NUM_M  ((EFUSE_MAC_SPI_8M_ERR_NUM_V)<<(EFUSE_MAC_SPI_8M_ERR_NUM_S))
+#define EFUSE_MAC_SPI_8M_ERR_NUM_V  0x7
+#define EFUSE_MAC_SPI_8M_ERR_NUM_S  0
+
+#define EFUSE_RD_RS_ERR1_REG          (DR_REG_EFUSE_BASE + 0x1C4)
+/* EFUSE_SYS_PART2_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of system part2 is reliable
+ 1: Means that programming user data failed and the number of error bytes is over 6.*/
+#define EFUSE_SYS_PART2_FAIL  (BIT(7))
+#define EFUSE_SYS_PART2_FAIL_M  (BIT(7))
+#define EFUSE_SYS_PART2_FAIL_V  0x1
+#define EFUSE_SYS_PART2_FAIL_S  7
+/* EFUSE_SYS_PART2_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes.*/
+#define EFUSE_SYS_PART2_ERR_NUM  0x00000007
+#define EFUSE_SYS_PART2_ERR_NUM_M  ((EFUSE_SYS_PART2_ERR_NUM_V)<<(EFUSE_SYS_PART2_ERR_NUM_S))
+#define EFUSE_SYS_PART2_ERR_NUM_V  0x7
+#define EFUSE_SYS_PART2_ERR_NUM_S  4
+/* EFUSE_KEY5_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 0: Means no failure and that the data of KEY5 is reliable 1:
+ Means that programming user data failed and the number of error bytes is over 6.*/
+#define EFUSE_KEY5_FAIL  (BIT(3))
+#define EFUSE_KEY5_FAIL_M  (BIT(3))
+#define EFUSE_KEY5_FAIL_V  0x1
+#define EFUSE_KEY5_FAIL_S  3
+/* EFUSE_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: The value of this signal means the number of error bytes.*/
+#define EFUSE_KEY5_ERR_NUM  0x00000007
+#define EFUSE_KEY5_ERR_NUM_M  ((EFUSE_KEY5_ERR_NUM_V)<<(EFUSE_KEY5_ERR_NUM_S))
+#define EFUSE_KEY5_ERR_NUM_V  0x7
+#define EFUSE_KEY5_ERR_NUM_S  0
+
+#define EFUSE_CLK_REG          (DR_REG_EFUSE_BASE + 0x1C8)
+/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit and force to enable clock signal of eFuse memory.*/
+#define EFUSE_CLK_EN  (BIT(16))
+#define EFUSE_CLK_EN_M  (BIT(16))
+#define EFUSE_CLK_EN_V  0x1
+#define EFUSE_CLK_EN_S  16
+/* EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to force eFuse SRAM into working mode.*/
+#define EFUSE_MEM_FORCE_PU  (BIT(2))
+#define EFUSE_MEM_FORCE_PU_M  (BIT(2))
+#define EFUSE_MEM_FORCE_PU_V  0x1
+#define EFUSE_MEM_FORCE_PU_S  2
+/* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: Set this bit and force to activate clock signal of eFuse SRAM.*/
+#define EFUSE_MEM_CLK_FORCE_ON  (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_M  (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_V  0x1
+#define EFUSE_MEM_CLK_FORCE_ON_S  1
+/* EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to force eFuse SRAM into power-saving mode.*/
+#define EFUSE_MEM_FORCE_PD  (BIT(0))
+#define EFUSE_MEM_FORCE_PD_M  (BIT(0))
+#define EFUSE_MEM_FORCE_PD_V  0x1
+#define EFUSE_MEM_FORCE_PD_S  0
+
+#define EFUSE_CONF_REG          (DR_REG_EFUSE_BASE + 0x1CC)
+/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command.*/
+#define EFUSE_OP_CODE  0x0000FFFF
+#define EFUSE_OP_CODE_M  ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S))
+#define EFUSE_OP_CODE_V  0xFFFF
+#define EFUSE_OP_CODE_S  0
+
+#define EFUSE_STATUS_REG          (DR_REG_EFUSE_BASE + 0x1D0)
+/* EFUSE_REPEAT_ERR_CNT : RO ;bitpos:[17:10] ;default: 8'h0 ; */
+/*description: Indicates the number of error bits during programming BLOCK0.*/
+#define EFUSE_REPEAT_ERR_CNT  0x000000FF
+#define EFUSE_REPEAT_ERR_CNT_M  ((EFUSE_REPEAT_ERR_CNT_V)<<(EFUSE_REPEAT_ERR_CNT_S))
+#define EFUSE_REPEAT_ERR_CNT_V  0xFF
+#define EFUSE_REPEAT_ERR_CNT_S  10
+/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The value of OTP_VDDQ_IS_SW.*/
+#define EFUSE_OTP_VDDQ_IS_SW  (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_M  (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_V  0x1
+#define EFUSE_OTP_VDDQ_IS_SW_S  9
+/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The value of OTP_PGENB_SW.*/
+#define EFUSE_OTP_PGENB_SW  (BIT(8))
+#define EFUSE_OTP_PGENB_SW_M  (BIT(8))
+#define EFUSE_OTP_PGENB_SW_V  0x1
+#define EFUSE_OTP_PGENB_SW_S  8
+/* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The value of OTP_CSB_SW.*/
+#define EFUSE_OTP_CSB_SW  (BIT(7))
+#define EFUSE_OTP_CSB_SW_M  (BIT(7))
+#define EFUSE_OTP_CSB_SW_V  0x1
+#define EFUSE_OTP_CSB_SW_S  7
+/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The value of OTP_STROBE_SW.*/
+#define EFUSE_OTP_STROBE_SW  (BIT(6))
+#define EFUSE_OTP_STROBE_SW_M  (BIT(6))
+#define EFUSE_OTP_STROBE_SW_V  0x1
+#define EFUSE_OTP_STROBE_SW_S  6
+/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The value of OTP_VDDQ_C_SYNC2.*/
+#define EFUSE_OTP_VDDQ_C_SYNC2  (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_M  (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x1
+#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
+/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The value of OTP_LOAD_SW.*/
+#define EFUSE_OTP_LOAD_SW  (BIT(4))
+#define EFUSE_OTP_LOAD_SW_M  (BIT(4))
+#define EFUSE_OTP_LOAD_SW_V  0x1
+#define EFUSE_OTP_LOAD_SW_S  4
+/* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: Indicates the state of the eFuse state machine.*/
+#define EFUSE_STATE  0x0000000F
+#define EFUSE_STATE_M  ((EFUSE_STATE_V)<<(EFUSE_STATE_S))
+#define EFUSE_STATE_V  0xF
+#define EFUSE_STATE_S  0
+
+#define EFUSE_CMD_REG          (DR_REG_EFUSE_BASE + 0x1D4)
+/* EFUSE_BLK_NUM : R/W ;bitpos:[5:2] ;default: 4'h0 ; */
+/*description: The serial number of the block to be programmed. Value 0-10 corresponds
+ to block number 0-10  respectively.*/
+#define EFUSE_BLK_NUM  0x0000000F
+#define EFUSE_BLK_NUM_M  ((EFUSE_BLK_NUM_V)<<(EFUSE_BLK_NUM_S))
+#define EFUSE_BLK_NUM_V  0xF
+#define EFUSE_BLK_NUM_S  2
+/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to send programming command.*/
+#define EFUSE_PGM_CMD  (BIT(1))
+#define EFUSE_PGM_CMD_M  (BIT(1))
+#define EFUSE_PGM_CMD_V  0x1
+#define EFUSE_PGM_CMD_S  1
+/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to send read command.*/
+#define EFUSE_READ_CMD  (BIT(0))
+#define EFUSE_READ_CMD_M  (BIT(0))
+#define EFUSE_READ_CMD_V  0x1
+#define EFUSE_READ_CMD_S  0
+
+#define EFUSE_INT_RAW_REG          (DR_REG_EFUSE_BASE + 0x1D8)
+/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw bit signal for pgm_done interrupt.*/
+#define EFUSE_PGM_DONE_INT_RAW  (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_V  0x1
+#define EFUSE_PGM_DONE_INT_RAW_S  1
+/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw bit signal for read_done interrupt.*/
+#define EFUSE_READ_DONE_INT_RAW  (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_V  0x1
+#define EFUSE_READ_DONE_INT_RAW_S  0
+
+#define EFUSE_INT_ST_REG          (DR_REG_EFUSE_BASE + 0x1DC)
+/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status signal for pgm_done interrupt.*/
+#define EFUSE_PGM_DONE_INT_ST  (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_V  0x1
+#define EFUSE_PGM_DONE_INT_ST_S  1
+/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status signal for read_done interrupt.*/
+#define EFUSE_READ_DONE_INT_ST  (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_V  0x1
+#define EFUSE_READ_DONE_INT_ST_S  0
+
+#define EFUSE_INT_ENA_REG          (DR_REG_EFUSE_BASE + 0x1E0)
+/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable signal for pgm_done interrupt.*/
+#define EFUSE_PGM_DONE_INT_ENA  (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_V  0x1
+#define EFUSE_PGM_DONE_INT_ENA_S  1
+/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable signal for read_done interrupt.*/
+#define EFUSE_READ_DONE_INT_ENA  (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_V  0x1
+#define EFUSE_READ_DONE_INT_ENA_S  0
+
+#define EFUSE_INT_CLR_REG          (DR_REG_EFUSE_BASE + 0x1E4)
+/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear signal for pgm_done interrupt.*/
+#define EFUSE_PGM_DONE_INT_CLR  (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_V  0x1
+#define EFUSE_PGM_DONE_INT_CLR_S  1
+/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear signal for read_done interrupt.*/
+#define EFUSE_READ_DONE_INT_CLR  (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_V  0x1
+#define EFUSE_READ_DONE_INT_CLR_S  0
+
+#define EFUSE_DAC_CONF_REG          (DR_REG_EFUSE_BASE + 0x1E8)
+/* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Reduces the power supply of the programming voltage.*/
+#define EFUSE_OE_CLR  (BIT(17))
+#define EFUSE_OE_CLR_M  (BIT(17))
+#define EFUSE_OE_CLR_V  0x1
+#define EFUSE_OE_CLR_S  17
+/* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */
+/*description: Controls the rising period of the programming voltage.*/
+#define EFUSE_DAC_NUM  0x000000FF
+#define EFUSE_DAC_NUM_M  ((EFUSE_DAC_NUM_V)<<(EFUSE_DAC_NUM_S))
+#define EFUSE_DAC_NUM_V  0xFF
+#define EFUSE_DAC_NUM_S  9
+/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Don't care.*/
+#define EFUSE_DAC_CLK_PAD_SEL  (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M  (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_V  0x1
+#define EFUSE_DAC_CLK_PAD_SEL_S  8
+/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd28 ; */
+/*description: Controls the division factor of the rising clock of the programming voltage.*/
+#define EFUSE_DAC_CLK_DIV  0x000000FF
+#define EFUSE_DAC_CLK_DIV_M  ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S))
+#define EFUSE_DAC_CLK_DIV_V  0xFF
+#define EFUSE_DAC_CLK_DIV_S  0
+
+#define EFUSE_RD_TIM_CONF_REG          (DR_REG_EFUSE_BASE + 0x1EC)
+/* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'h12 ; */
+/*description: Configures the initial read time of eFuse.*/
+#define EFUSE_READ_INIT_NUM  0x000000FF
+#define EFUSE_READ_INIT_NUM_M  ((EFUSE_READ_INIT_NUM_V)<<(EFUSE_READ_INIT_NUM_S))
+#define EFUSE_READ_INIT_NUM_V  0xFF
+#define EFUSE_READ_INIT_NUM_S  24
+
+#define EFUSE_WR_TIM_CONF1_REG          (DR_REG_EFUSE_BASE + 0x1F0)
+/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h2880 ; */
+/*description: Configures the power up time for VDDQ.*/
+#define EFUSE_PWR_ON_NUM  0x0000FFFF
+#define EFUSE_PWR_ON_NUM_M  ((EFUSE_PWR_ON_NUM_V)<<(EFUSE_PWR_ON_NUM_S))
+#define EFUSE_PWR_ON_NUM_V  0xFFFF
+#define EFUSE_PWR_ON_NUM_S  8
+
+#define EFUSE_WR_TIM_CONF2_REG          (DR_REG_EFUSE_BASE + 0x1F4)
+/* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h190 ; */
+/*description: Configures the power outage time for VDDQ.*/
+#define EFUSE_PWR_OFF_NUM  0x0000FFFF
+#define EFUSE_PWR_OFF_NUM_M  ((EFUSE_PWR_OFF_NUM_V)<<(EFUSE_PWR_OFF_NUM_S))
+#define EFUSE_PWR_OFF_NUM_V  0xFFFF
+#define EFUSE_PWR_OFF_NUM_S  0
+
+#define EFUSE_DATE_REG          (DR_REG_EFUSE_BASE + 0x1FC)
+/* EFUSE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007200 ; */
+/*description: Stores eFuse version.*/
+#define EFUSE_DATE  0x0FFFFFFF
+#define EFUSE_DATE_M  ((EFUSE_DATE_V)<<(EFUSE_DATE_S))
+#define EFUSE_DATE_V  0xFFFFFFF
+#define EFUSE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_EFUSE_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/efuse_struct.h b/components/soc/esp32c3/include/soc/efuse_struct.h
new file mode 100644
index 0000000000..e6da229105
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/efuse_struct.h
@@ -0,0 +1,514 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_EFUSE_STRUCT_H_
+#define _SOC_EFUSE_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    uint32_t pgm_data0;                                          /*Register 0 that stores data to be programmed.*/
+    union {
+        struct {
+            uint32_t rd_dis:                      7;             /*Set this bit to disable reading from BlOCK4-10.*/
+            uint32_t dis_rtc_ram_boot:            1;             /*Set this bit to disable boot from RTC RAM.*/
+            uint32_t dis_icache:                  1;             /*Set this bit to disable Icache.*/
+            uint32_t dis_usb_jtag:                1;             /*Set this bit to disable function of usb switch to jtag in module of usb device.*/
+            uint32_t dis_download_icache:         1;             /*Set this bit to disable Icache in download mode (boot_mode[3:0] is 0  1  2  3  6  7).*/
+            uint32_t dis_usb_device:              1;             /*Set this bit to disable usb device.*/
+            uint32_t dis_force_download:          1;             /*Set this bit to disable the function that forces chip into download mode.*/
+            uint32_t dis_usb:                     1;             /*Set this bit to disable USB function.*/
+            uint32_t dis_can:                     1;             /*Set this bit to disable CAN function.*/
+            uint32_t jtag_sel_enable:             1;             /*Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/
+            uint32_t soft_dis_jtag:               3;             /*Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.*/
+            uint32_t dis_pad_jtag:                1;             /*Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/
+            uint32_t dis_download_manual_encrypt: 1;             /*Set this bit to disable flash encryption when in download boot modes.*/
+            uint32_t usb_drefh:                   2;             /*Controls single-end input threshold vrefh  1.76 V to 2 V with step of 80 mV  stored in eFuse.*/
+            uint32_t usb_drefl:                   2;             /*Controls single-end input threshold vrefl  0.8 V to 1.04 V with step of 80 mV  stored in eFuse.*/
+            uint32_t usb_exchg_pins:              1;             /*Set this bit to exchange USB D+ and D- pins.*/
+            uint32_t vdd_spi_as_gpio:             1;             /*Set this bit to vdd spi pin function as gpio.*/
+            uint32_t btlc_gpio_enable:            2;             /*Enable btlc gpio.*/
+            uint32_t powerglitch_en:              1;             /*Set this bit to enable power glitch function.*/
+            uint32_t power_glitch_dsense:         2;             /*Sample delay configuration of power glitch.*/
+        };
+        uint32_t val;
+    } pgm_data1;
+    union {
+        struct {
+            uint32_t rpt4_reserved2:         16;                 /*Reserved (used for four backups method).*/
+            uint32_t wat_delay_sel:           2;                 /*Selects RTC watchdog timeout threshold  in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/
+            uint32_t spi_boot_crypt_cnt:      3;                 /*Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.*/
+            uint32_t secure_boot_key_revoke0: 1;                 /*Set this bit to enable revoking first secure boot key.*/
+            uint32_t secure_boot_key_revoke1: 1;                 /*Set this bit to enable revoking second secure boot key.*/
+            uint32_t secure_boot_key_revoke2: 1;                 /*Set this bit to enable revoking third secure boot key.*/
+            uint32_t key_purpose_0:           4;                 /*Purpose of Key0.*/
+            uint32_t key_purpose_1:           4;                 /*Purpose of Key1.*/
+        };
+        uint32_t val;
+    } pgm_data2;
+    union {
+        struct {
+            uint32_t key_purpose_2:                 4;           /*Purpose of Key2.*/
+            uint32_t key_purpose_3:                 4;           /*Purpose of Key3.*/
+            uint32_t key_purpose_4:                 4;           /*Purpose of Key4.*/
+            uint32_t key_purpose_5:                 4;           /*Purpose of Key5.*/
+            uint32_t rpt4_reserved3:                4;           /*Reserved (used for four backups method).*/
+            uint32_t secure_boot_en:                1;           /*Set this bit to enable secure boot.*/
+            uint32_t secure_boot_aggressive_revoke: 1;           /*Set this bit to enable revoking aggressive secure boot.*/
+            uint32_t rpt4_reserved0:                6;           /*Reserved (used for four backups method).*/
+            uint32_t flash_tpuw:                    4;           /*Configures flash waiting time after power-up  in unit of ms. If the value is less than 15  the waiting time is the configurable value*/
+        };
+        uint32_t val;
+    } pgm_data3;
+    union {
+        struct {
+            uint32_t dis_download_mode:        1;                /*Set this bit to disable download mode (boot_mode[3:0] = 0  1  2  3  6  7).*/
+            uint32_t dis_legacy_spi_boot:      1;                /*Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).*/
+            uint32_t uart_print_channel:       1;                /*Selectes the default UART print channel. 0: UART0. 1: UART1.*/
+            uint32_t flash_ecc_mode:           1;                /*Set ECC mode in ROM  0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.*/
+            uint32_t dis_usb_download_mode:    1;                /*Set this bit to disable UART download mode through USB.*/
+            uint32_t enable_security_download: 1;                /*Set this bit to enable secure UART download mode.*/
+            uint32_t uart_print_control:       2;                /*Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO46 is low at reset. 10: Enabled when GPIO46 is high at reset. 11:disabled.*/
+            uint32_t pin_power_selection:      1;                /*GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.*/
+            uint32_t flash_type:               1;                /*Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.*/
+            uint32_t flash_page_size:          2;                /*Set Flash page size.*/
+            uint32_t flash_ecc_en:             1;                /*Set 1 to enable ECC for flash boot.*/
+            uint32_t force_send_resume:        1;                /*Set this bit to force ROM code to send a resume command during SPI boot.*/
+            uint32_t secure_version:          16;                /*Secure version (used by ESP-IDF anti-rollback feature).*/
+            uint32_t rpt4_reserved1:           2;                /*Reserved (used for four backups method).*/
+        };
+        uint32_t val;
+    } pgm_data4;
+    union {
+        struct {
+            uint32_t rpt4_reserved4:24;                          /*Reserved (used for four backups method).*/
+            uint32_t reserved24:     8;                          /*Reserved.*/
+        };
+        uint32_t val;
+    } pgm_data5;
+    uint32_t pgm_data6;                                          /*Register 6 that stores data to be programmed.*/
+    uint32_t pgm_data7;                                          /*Register 7 that stores data to be programmed.*/
+    uint32_t pgm_check_value0;                                   /*Register 0 that stores the RS code to be programmed.*/
+    uint32_t pgm_check_value1;                                   /*Register 1 that stores the RS code to be programmed.*/
+    uint32_t pgm_check_value2;                                   /*Register 2 that stores the RS code to be programmed.*/
+    uint32_t rd_wr_dis;                                          /*BLOCK0 data register $n.*/
+    union {
+        struct {
+            uint32_t rd_dis:                      7;             /*The value of RD_DIS.*/
+            uint32_t dis_rtc_ram_boot:            1;             /*The value of DIS_RTC_RAM_BOOT.*/
+            uint32_t dis_icache:                  1;             /*The value of DIS_ICACHE.*/
+            uint32_t dis_usb_jtag:                1;             /*The value of DIS_USB_JTAG.*/
+            uint32_t dis_download_icache:         1;             /*The value of DIS_DOWNLOAD_ICACHE.*/
+            uint32_t dis_usb_device:              1;             /*The value of DIS_USB_DEVICE.*/
+            uint32_t dis_force_download:          1;             /*The value of DIS_FORCE_DOWNLOAD.*/
+            uint32_t dis_usb:                     1;             /*The value of DIS_USB.*/
+            uint32_t dis_can:                     1;             /*The value of DIS_CAN.*/
+            uint32_t jtag_sel_enable:             1;             /*The value of JTAG_SEL_ENABLE.*/
+            uint32_t soft_dis_jtag:               3;             /*The value of SOFT_DIS_JTAG.*/
+            uint32_t dis_pad_jtag:                1;             /*The value of DIS_PAD_JTAG.*/
+            uint32_t dis_download_manual_encrypt: 1;             /*The value of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/
+            uint32_t usb_drefh:                   2;             /*The value of USB_DREFH.*/
+            uint32_t usb_drefl:                   2;             /*The value of USB_DREFL.*/
+            uint32_t usb_exchg_pins:              1;             /*The value of USB_EXCHG_PINS.*/
+            uint32_t vdd_spi_as_gpio:             1;             /*The value of VDD_SPI_AS_GPIO.*/
+            uint32_t btlc_gpio_enable:            2;             /*The value of BTLC_GPIO_ENABLE.*/
+            uint32_t powerglitch_en:              1;             /*The value of POWERGLITCH_EN.*/
+            uint32_t power_glitch_dsense:         2;             /*The value of POWER_GLITCH_DSENSE.*/
+        };
+        uint32_t val;
+    } rd_repeat_data0;
+    union {
+        struct {
+            uint32_t rpt4_reserved2:         16;                 /*Reserved.*/
+            uint32_t wdt_delay_sel:           2;                 /*The value of WDT_DELAY_SEL.*/
+            uint32_t spi_boot_crypt_cnt:      3;                 /*The value of SPI_BOOT_CRYPT_CNT.*/
+            uint32_t secure_boot_key_revoke0: 1;                 /*The value of SECURE_BOOT_KEY_REVOKE0.*/
+            uint32_t secure_boot_key_revoke1: 1;                 /*The value of SECURE_BOOT_KEY_REVOKE1.*/
+            uint32_t secure_boot_key_revoke2: 1;                 /*The value of SECURE_BOOT_KEY_REVOKE2.*/
+            uint32_t key_purpose_0:           4;                 /*The value of KEY_PURPOSE_0.*/
+            uint32_t key_purpose_1:           4;                 /*The value of KEY_PURPOSE_1.*/
+        };
+        uint32_t val;
+    } rd_repeat_data1;
+    union {
+        struct {
+            uint32_t key_purpose_2:                 4;           /*The value of KEY_PURPOSE_2.*/
+            uint32_t key_purpose_3:                 4;           /*The value of KEY_PURPOSE_3.*/
+            uint32_t key_purpose_4:                 4;           /*The value of KEY_PURPOSE_4.*/
+            uint32_t key_purpose_5:                 4;           /*The value of KEY_PURPOSE_5.*/
+            uint32_t rpt4_reserved3:                4;           /*Reserved.*/
+            uint32_t secure_boot_en:                1;           /*The value of SECURE_BOOT_EN.*/
+            uint32_t secure_boot_aggressive_revoke: 1;           /*The value of SECURE_BOOT_AGGRESSIVE_REVOKE.*/
+            uint32_t rpt4_reserved0:                6;           /*Reserved.*/
+            uint32_t flash_tpuw:                    4;           /*The value of FLASH_TPUW.*/
+        };
+        uint32_t val;
+    } rd_repeat_data2;
+    union {
+        struct {
+            uint32_t dis_download_mode:        1;                /*The value of DIS_DOWNLOAD_MODE.*/
+            uint32_t dis_legacy_spi_boot:      1;                /*The value of DIS_LEGACY_SPI_BOOT.*/
+            uint32_t uart_print_channel:       1;                /*The value of UART_PRINT_CHANNEL.*/
+            uint32_t flash_ecc_mode:           1;                /*The value of FLASH_ECC_MODE.*/
+            uint32_t dis_usb_download_mode:    1;                /*The value of DIS_USB_DOWNLOAD_MODE.*/
+            uint32_t enable_security_download: 1;                /*The value of ENABLE_SECURITY_DOWNLOAD.*/
+            uint32_t uart_print_control:       2;                /*The value of UART_PRINT_CONTROL.*/
+            uint32_t pin_power_selection:      1;                /*The value of PIN_POWER_SELECTION.*/
+            uint32_t flash_type:               1;                /*The value of FLASH_TYPE.*/
+            uint32_t flash_page_size:          2;                /*The value of FLASH_PAGE_SIZE.*/
+            uint32_t flash_ecc_en:             1;                /*The value of FLASH_ECC_EN.*/
+            uint32_t force_send_resume:        1;                /*The value of FORCE_SEND_RESUME.*/
+            uint32_t secure_version:          16;                /*The value of SECURE_VERSION.*/
+            uint32_t rpt4_reserved1:           2;                /*Reserved.*/
+        };
+        uint32_t val;
+    } rd_repeat_data3;
+    union {
+        struct {
+            uint32_t rpt4_reserved4:24;                          /*Reserved.*/
+            uint32_t reserved24:     8;                          /*Reserved.*/
+        };
+        uint32_t val;
+    } rd_repeat_data4;
+    uint32_t rd_mac_spi_sys_0;                                   /*BLOCK1 data register $n.*/
+    union {
+        struct {
+            uint32_t mac_1:         16;                          /*Stores the high 16 bits of MAC address.*/
+            uint32_t spi_pad_conf_0:16;                          /*Stores the zeroth part of SPI_PAD_CONF.*/
+        };
+        uint32_t val;
+    } rd_mac_spi_sys_1;
+    uint32_t rd_mac_spi_sys_2;                                   /*BLOCK1 data register $n.*/
+    union {
+        struct {
+            uint32_t spi_pad_conf_2:  18;                        /*Stores the second part of SPI_PAD_CONF.*/
+            uint32_t sys_data_part0_0:14;                        /*Stores the fist 14 bits of the zeroth part of system data.*/
+        };
+        uint32_t val;
+    } rd_mac_spi_sys_3;
+    uint32_t rd_mac_spi_sys_4;                                   /*BLOCK1 data register $n.*/
+    uint32_t rd_mac_spi_sys_5;                                   /*BLOCK1 data register $n.*/
+    uint32_t rd_sys_part1_data0;                                 /*Register $n of BLOCK2 (system).*/
+    uint32_t rd_sys_part1_data1;                                 /*Register $n of BLOCK2 (system).*/
+    uint32_t rd_sys_part1_data2;                                 /*Register $n of BLOCK2 (system).*/
+    uint32_t rd_sys_part1_data3;                                 /*Register $n of BLOCK2 (system).*/
+    uint32_t rd_sys_part1_data4;                                 /*Register $n of BLOCK2 (system).*/
+    uint32_t rd_sys_part1_data5;                                 /*Register $n of BLOCK2 (system).*/
+    uint32_t rd_sys_part1_data6;                                 /*Register $n of BLOCK2 (system).*/
+    uint32_t rd_sys_part1_data7;                                 /*Register $n of BLOCK2 (system).*/
+    uint32_t rd_usr_data0;                                       /*Register $n of BLOCK3 (user).*/
+    uint32_t rd_usr_data1;                                       /*Register $n of BLOCK3 (user).*/
+    uint32_t rd_usr_data2;                                       /*Register $n of BLOCK3 (user).*/
+    uint32_t rd_usr_data3;                                       /*Register $n of BLOCK3 (user).*/
+    uint32_t rd_usr_data4;                                       /*Register $n of BLOCK3 (user).*/
+    uint32_t rd_usr_data5;                                       /*Register $n of BLOCK3 (user).*/
+    uint32_t rd_usr_data6;                                       /*Register $n of BLOCK3 (user).*/
+    uint32_t rd_usr_data7;                                       /*Register $n of BLOCK3 (user).*/
+    uint32_t rd_key0_data0;                                      /*Register $n of BLOCK4 (KEY0).*/
+    uint32_t rd_key0_data1;                                      /*Register $n of BLOCK4 (KEY0).*/
+    uint32_t rd_key0_data2;                                      /*Register $n of BLOCK4 (KEY0).*/
+    uint32_t rd_key0_data3;                                      /*Register $n of BLOCK4 (KEY0).*/
+    uint32_t rd_key0_data4;                                      /*Register $n of BLOCK4 (KEY0).*/
+    uint32_t rd_key0_data5;                                      /*Register $n of BLOCK4 (KEY0).*/
+    uint32_t rd_key0_data6;                                      /*Register $n of BLOCK4 (KEY0).*/
+    uint32_t rd_key0_data7;                                      /*Register $n of BLOCK4 (KEY0).*/
+    uint32_t rd_key1_data0;                                      /*Register $n of BLOCK5 (KEY1).*/
+    uint32_t rd_key1_data1;                                      /*Register $n of BLOCK5 (KEY1).*/
+    uint32_t rd_key1_data2;                                      /*Register $n of BLOCK5 (KEY1).*/
+    uint32_t rd_key1_data3;                                      /*Register $n of BLOCK5 (KEY1).*/
+    uint32_t rd_key1_data4;                                      /*Register $n of BLOCK5 (KEY1).*/
+    uint32_t rd_key1_data5;                                      /*Register $n of BLOCK5 (KEY1).*/
+    uint32_t rd_key1_data6;                                      /*Register $n of BLOCK5 (KEY1).*/
+    uint32_t rd_key1_data7;                                      /*Register $n of BLOCK5 (KEY1).*/
+    uint32_t rd_key2_data0;                                      /*Register $n of BLOCK6 (KEY2).*/
+    uint32_t rd_key2_data1;                                      /*Register $n of BLOCK6 (KEY2).*/
+    uint32_t rd_key2_data2;                                      /*Register $n of BLOCK6 (KEY2).*/
+    uint32_t rd_key2_data3;                                      /*Register $n of BLOCK6 (KEY2).*/
+    uint32_t rd_key2_data4;                                      /*Register $n of BLOCK6 (KEY2).*/
+    uint32_t rd_key2_data5;                                      /*Register $n of BLOCK6 (KEY2).*/
+    uint32_t rd_key2_data6;                                      /*Register $n of BLOCK6 (KEY2).*/
+    uint32_t rd_key2_data7;                                      /*Register $n of BLOCK6 (KEY2).*/
+    uint32_t rd_key3_data0;                                      /*Register $n of BLOCK7 (KEY3).*/
+    uint32_t rd_key3_data1;                                      /*Register $n of BLOCK7 (KEY3).*/
+    uint32_t rd_key3_data2;                                      /*Register $n of BLOCK7 (KEY3).*/
+    uint32_t rd_key3_data3;                                      /*Register $n of BLOCK7 (KEY3).*/
+    uint32_t rd_key3_data4;                                      /*Register $n of BLOCK7 (KEY3).*/
+    uint32_t rd_key3_data5;                                      /*Register $n of BLOCK7 (KEY3).*/
+    uint32_t rd_key3_data6;                                      /*Register $n of BLOCK7 (KEY3).*/
+    uint32_t rd_key3_data7;                                      /*Register $n of BLOCK7 (KEY3).*/
+    uint32_t rd_key4_data0;                                      /*Register $n of BLOCK8 (KEY4).*/
+    uint32_t rd_key4_data1;                                      /*Register $n of BLOCK8 (KEY4).*/
+    uint32_t rd_key4_data2;                                      /*Register $n of BLOCK8 (KEY4).*/
+    uint32_t rd_key4_data3;                                      /*Register $n of BLOCK8 (KEY4).*/
+    uint32_t rd_key4_data4;                                      /*Register $n of BLOCK8 (KEY4).*/
+    uint32_t rd_key4_data5;                                      /*Register $n of BLOCK8 (KEY4).*/
+    uint32_t rd_key4_data6;                                      /*Register $n of BLOCK8 (KEY4).*/
+    uint32_t rd_key4_data7;                                      /*Register $n of BLOCK8 (KEY4).*/
+    uint32_t rd_key5_data0;                                      /*Register $n of BLOCK9 (KEY5).*/
+    uint32_t rd_key5_data1;                                      /*Register $n of BLOCK9 (KEY5).*/
+    uint32_t rd_key5_data2;                                      /*Register $n of BLOCK9 (KEY5).*/
+    uint32_t rd_key5_data3;                                      /*Register $n of BLOCK9 (KEY5).*/
+    uint32_t rd_key5_data4;                                      /*Register $n of BLOCK9 (KEY5).*/
+    uint32_t rd_key5_data5;                                      /*Register $n of BLOCK9 (KEY5).*/
+    uint32_t rd_key5_data6;                                      /*Register $n of BLOCK9 (KEY5).*/
+    uint32_t rd_key5_data7;                                      /*Register $n of BLOCK9 (KEY5).*/
+    uint32_t rd_sys_part2_data0;                                 /*Register $n of BLOCK10 (system).*/
+    uint32_t rd_sys_part2_data1;                                 /*Register $n of BLOCK9 (KEY5).*/
+    uint32_t rd_sys_part2_data2;                                 /*Register $n of BLOCK10 (system).*/
+    uint32_t rd_sys_part2_data3;                                 /*Register $n of BLOCK10 (system).*/
+    uint32_t rd_sys_part2_data4;                                 /*Register $n of BLOCK10 (system).*/
+    uint32_t rd_sys_part2_data5;                                 /*Register $n of BLOCK10 (system).*/
+    uint32_t rd_sys_part2_data6;                                 /*Register $n of BLOCK10 (system).*/
+    uint32_t rd_sys_part2_data7;                                 /*Register $n of BLOCK10 (system).*/
+    union {
+        struct {
+            uint32_t rd_dis_err:                      7;         /*If any bit in RD_DIS is 1  then it indicates a programming error.*/
+            uint32_t dis_rtc_ram_boot_err:            1;         /*If DIS_RTC_RAM_BOOT is 1  then it indicates a programming error.*/
+            uint32_t dis_icache_err:                  1;         /*If DIS_ICACHE is 1  then it indicates a programming error.*/
+            uint32_t dis_usb_jtag_err:                1;         /*If DIS_USB_JTAG is 1  then it indicates a programming error.*/
+            uint32_t dis_download_icache:             1;         /*If DIS_DOWNLOAD_ICACHE is 1  then it indicates a programming error.*/
+            uint32_t dis_usb_device_err:              1;         /*If DIS_USB_DEVICE is 1  then it indicates a programming error.*/
+            uint32_t dis_force_download_err:          1;         /*If DIS_FORCE_DOWNLOAD is 1  then it indicates a programming error.*/
+            uint32_t dis_usb_err:                     1;         /*If DIS_USB is 1  then it indicates a programming error.*/
+            uint32_t dis_can_err:                     1;         /*If DIS_CAN is 1  then it indicates a programming error.*/
+            uint32_t jtag_sel_enable_err:             1;         /*If JTAG_SEL_ENABLE is 1  then it indicates a programming error.*/
+            uint32_t soft_dis_jtag_err:               3;         /*If SOFT_DIS_JTAG is 1  then it indicates a programming error.*/
+            uint32_t dis_pad_jtag_err:                1;         /*If DIS_PAD_JTAG is 1  then it indicates a programming error.*/
+            uint32_t dis_download_manual_encrypt_err: 1;         /*If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1  then it indicates a programming error.*/
+            uint32_t usb_drefh_err:                   2;         /*If any bit in USB_DREFH is 1  then it indicates a programming error.*/
+            uint32_t usb_drefl_err:                   2;         /*If any bit in USB_DREFL is 1  then it indicates a programming error.*/
+            uint32_t usb_exchg_pins_err:              1;         /*If USB_EXCHG_PINS is 1  then it indicates a programming error.*/
+            uint32_t vdd_spi_as_gpio_err:             1;         /*If VDD_SPI_AS_GPIO is 1  then it indicates a programming error.*/
+            uint32_t btlc_gpio_enable_err:            2;         /*If any bit in BTLC_GPIO_ENABLE is 1  then it indicates a programming error.*/
+            uint32_t powerglitch_en_err:              1;         /*If POWERGLITCH_EN is 1  then it indicates a programming error.*/
+            uint32_t power_glitch_dsense_err:         2;         /*If any bit in POWER_GLITCH_DSENSE is 1  then it indicates a programming error.*/
+        };
+        uint32_t val;
+    } rd_repeat_err0;
+    union {
+        struct {
+            uint32_t rpt4_reserved2_err:         16;             /*Reserved.*/
+            uint32_t wdt_delay_sel_err:           2;             /*If any bit in WDT_DELAY_SEL is 1  then it indicates a programming error.*/
+            uint32_t spi_boot_crypt_cnt_err:      3;             /*If any bit in SPI_BOOT_CRYPT_CNT is 1  then it indicates a programming error.*/
+            uint32_t secure_boot_key_revoke0_err: 1;             /*If SECURE_BOOT_KEY_REVOKE0 is 1  then it indicates a programming error.*/
+            uint32_t secure_boot_key_revoke1_err: 1;             /*If SECURE_BOOT_KEY_REVOKE1 is 1  then it indicates a programming error.*/
+            uint32_t secure_boot_key_revoke2_err: 1;             /*If SECURE_BOOT_KEY_REVOKE2 is 1  then it indicates a programming error.*/
+            uint32_t key_purpose_0_err:           4;             /*If any bit in KEY_PURPOSE_0 is 1  then it indicates a programming error.*/
+            uint32_t key_purpose_1_err:           4;             /*If any bit in KEY_PURPOSE_1 is 1  then it indicates a programming error.*/
+        };
+        uint32_t val;
+    } rd_repeat_err1;
+    union {
+        struct {
+            uint32_t key_purpose_2_err:                 4;       /*If any bit in KEY_PURPOSE_2 is 1  then it indicates a programming error.*/
+            uint32_t key_purpose_3_err:                 4;       /*If any bit in KEY_PURPOSE_3 is 1  then it indicates a programming error.*/
+            uint32_t key_purpose_4_err:                 4;       /*If any bit in KEY_PURPOSE_4 is 1  then it indicates a programming error.*/
+            uint32_t key_purpose_5_err:                 4;       /*If any bit in KEY_PURPOSE_5 is 1  then it indicates a programming error.*/
+            uint32_t rpt4_reserved3_err:                4;       /*Reserved.*/
+            uint32_t secure_boot_en_err:                1;       /*If SECURE_BOOT_EN is 1  then it indicates a programming error.*/
+            uint32_t secure_boot_aggressive_revoke_err: 1;       /*If SECURE_BOOT_AGGRESSIVE_REVOKE is 1  then it indicates a programming error.*/
+            uint32_t rpt4_reserved0_err:                6;       /*Reserved.*/
+            uint32_t flash_tpuw_err:                    4;       /*If any bit in FLASH_TPUM is 1  then it indicates a programming error.*/
+        };
+        uint32_t val;
+    } rd_repeat_err2;
+    union {
+        struct {
+            uint32_t dis_download_mode_err:        1;            /*If DIS_DOWNLOAD_MODE is 1  then it indicates a programming error.*/
+            uint32_t dis_legacy_spi_boot_err:      1;            /*If DIS_LEGACY_SPI_BOOT is 1  then it indicates a programming error.*/
+            uint32_t uart_print_channel_err:       1;            /*If UART_PRINT_CHANNEL is 1  then it indicates a programming error.*/
+            uint32_t flash_ecc_mode_err:           1;            /*If FLASH_ECC_MODE is 1  then it indicates a programming error.*/
+            uint32_t dis_usb_download_mode_err:    1;            /*If DIS_USB_DOWNLOAD_MODE is 1  then it indicates a programming error.*/
+            uint32_t enable_security_download_err: 1;            /*If ENABLE_SECURITY_DOWNLOAD is 1  then it indicates a programming error.*/
+            uint32_t uart_print_control_err:       2;            /*If any bit in UART_PRINT_CONTROL is 1  then it indicates a programming error.*/
+            uint32_t pin_power_selection_err:      1;            /*If PIN_POWER_SELECTION is 1  then it indicates a programming error.*/
+            uint32_t flash_type_err:               1;            /*If FLASH_TYPE is 1  then it indicates a programming error.*/
+            uint32_t flash_page_size:              2;            /*If any bits in FLASH_PAGE_SIZE is 1  then it indicates a programming error.*/
+            uint32_t flash_ecc_en:                 1;            /*If FLASH_ECC_EN_ERR is 1  then it indicates a programming error.*/
+            uint32_t force_send_resume_err:        1;            /*If FORCE_SEND_RESUME is 1  then it indicates a programming error.*/
+            uint32_t secure_version_err:          16;            /*If any bit in SECURE_VERSION is 1  then it indicates a programming error.*/
+            uint32_t rpt4_reserved1_err:           2;            /*Reserved.*/
+        };
+        uint32_t val;
+    } rd_repeat_err3;
+    uint32_t reserved_18c;
+    union {
+        struct {
+            uint32_t rpt4_reserved4_err:24;                      /*Reserved.*/
+            uint32_t reserved24:         8;                      /*Reserved.*/
+        };
+        uint32_t val;
+    } rd_repeat_err4;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    union {
+        struct {
+            uint32_t mac_spi_8m_err_num: 3;                      /*The value of this signal means the number of error bytes.*/
+            uint32_t mac_spi_8m_fail:    1;                      /*0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
+            uint32_t sys_part1_num:      3;                      /*The value of this signal means the number of error bytes.*/
+            uint32_t sys_part1_fail:     1;                      /*0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
+            uint32_t usr_data_err_num:   3;                      /*The value of this signal means the number of error bytes.*/
+            uint32_t usr_data_fail:      1;                      /*0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
+            uint32_t key0_err_num:       3;                      /*The value of this signal means the number of error bytes.*/
+            uint32_t key0_fail:          1;                      /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
+            uint32_t key1_err_num:       3;                      /*The value of this signal means the number of error bytes.*/
+            uint32_t key1_fail:          1;                      /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
+            uint32_t key2_err_num:       3;                      /*The value of this signal means the number of error bytes.*/
+            uint32_t key2_fail:          1;                      /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
+            uint32_t key3_err_num:       3;                      /*The value of this signal means the number of error bytes.*/
+            uint32_t key3_fail:          1;                      /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
+            uint32_t key4_err_num:       3;                      /*The value of this signal means the number of error bytes.*/
+            uint32_t key4_fail:          1;                      /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
+        };
+        uint32_t val;
+    } rd_rs_err0;
+    union {
+        struct {
+            uint32_t key5_err_num:      3;                       /*The value of this signal means the number of error bytes.*/
+            uint32_t key5_fail:         1;                       /*0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
+            uint32_t sys_part2_err_num: 3;                       /*The value of this signal means the number of error bytes.*/
+            uint32_t sys_part2_fail:    1;                       /*0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
+            uint32_t reserved8:        24;                       /*Reserved.*/
+        };
+        uint32_t val;
+    } rd_rs_err1;
+    union {
+        struct {
+            uint32_t mem_force_pd:     1;                        /*Set this bit to force eFuse SRAM into power-saving mode.*/
+            uint32_t mem_clk_force_on: 1;                        /*Set this bit and force to activate clock signal of eFuse SRAM.*/
+            uint32_t mem_force_pu:     1;                        /*Set this bit to force eFuse SRAM into working mode.*/
+            uint32_t reserved3:       13;                        /*Reserved.*/
+            uint32_t clk_en:           1;                        /*Set this bit and force to enable clock signal of eFuse memory.*/
+            uint32_t reserved17:      15;                        /*Reserved.*/
+        };
+        uint32_t val;
+    } clk;
+    union {
+        struct {
+            uint32_t op_code:   16;                              /*0x5A5A: Operate programming command 0x5AA5: Operate read command.*/
+            uint32_t reserved16:16;                              /*Reserved.*/
+        };
+        uint32_t val;
+    } conf;
+    union {
+        struct {
+            uint32_t state:            4;                        /*Indicates the state of the eFuse state machine.*/
+            uint32_t otp_load_sw:      1;                        /*The value of OTP_LOAD_SW.*/
+            uint32_t otp_vddq_c_sync2: 1;                        /*The value of OTP_VDDQ_C_SYNC2.*/
+            uint32_t otp_strobe_sw:    1;                        /*The value of OTP_STROBE_SW.*/
+            uint32_t otp_csb_sw:       1;                        /*The value of OTP_CSB_SW.*/
+            uint32_t otp_pgenb_sw:     1;                        /*The value of OTP_PGENB_SW.*/
+            uint32_t otp_vddq_is_sw:   1;                        /*The value of OTP_VDDQ_IS_SW.*/
+            uint32_t repeat_err_cnt:   8;                        /*Indicates the number of error bits during programming BLOCK0.*/
+            uint32_t reserved18:      14;                        /*Reserved.*/
+        };
+        uint32_t val;
+    } status;
+    union {
+        struct {
+            uint32_t read_cmd:   1;                              /*Set this bit to send read command.*/
+            uint32_t pgm_cmd:    1;                              /*Set this bit to send programming command.*/
+            uint32_t blk_num:    4;                              /*The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10  respectively.*/
+            uint32_t reserved6: 26;                              /*Reserved.*/
+        };
+        uint32_t val;
+    } cmd;
+    union {
+        struct {
+            uint32_t read_done:         1;                       /*The raw bit signal for read_done interrupt.*/
+            uint32_t pgm_done:          1;                       /*The raw bit signal for pgm_done interrupt.*/
+            uint32_t reserved2:        30;                       /*Reserved.*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t read_done:        1;                        /*The status signal for read_done interrupt.*/
+            uint32_t pgm_done:         1;                        /*The status signal for pgm_done interrupt.*/
+            uint32_t reserved2:       30;                        /*Reserved.*/
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t read_done:         1;                       /*The enable signal for read_done interrupt.*/
+            uint32_t pgm_done:          1;                       /*The enable signal for pgm_done interrupt.*/
+            uint32_t reserved2:        30;                       /*Reserved.*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t read_done:         1;                       /*The clear signal for read_done interrupt.*/
+            uint32_t pgm_done:          1;                       /*The clear signal for pgm_done interrupt.*/
+            uint32_t reserved2:        30;                       /*Reserved.*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t dac_clk_div:     8;                         /*Controls the division factor of the rising clock of the programming voltage.*/
+            uint32_t dac_clk_pad_sel: 1;                         /*Don't care.*/
+            uint32_t dac_num:         8;                         /*Controls the rising period of the programming voltage.*/
+            uint32_t oe_clr:          1;                         /*Reduces the power supply of the programming voltage.*/
+            uint32_t reserved18:     14;                         /*Reserved.*/
+        };
+        uint32_t val;
+    } dac_conf;
+    union {
+        struct {
+            uint32_t reserved0:    24;                           /*Configures the setup time of read operation.*/
+            uint32_t read_init_num: 8;                           /*Configures the initial read time of eFuse.*/
+        };
+        uint32_t val;
+    } rd_tim_conf;
+    union {
+        struct {
+            uint32_t reserved0:  8;                              /*Configures the setup time of programming operation.*/
+            uint32_t pwr_on_num:16;                              /*Configures the power up time for VDDQ.*/
+            uint32_t reserved24: 8;                              /*Reserved.*/
+        };
+        uint32_t val;
+    } wr_tim_conf1;
+    union {
+        struct {
+            uint32_t pwr_off_num:16;                             /*Configures the power outage time for VDDQ.*/
+            uint32_t reserved16: 16;                             /*Reserved.*/
+        };
+        uint32_t val;
+    } wr_tim_conf2;
+    uint32_t reserved_1f8;
+    union {
+        struct {
+            uint32_t date:      28;                              /*Stores eFuse version.*/
+            uint32_t reserved28: 4;                              /*Reserved.*/
+        };
+        uint32_t val;
+    } date;
+} efuse_dev_t;
+extern efuse_dev_t EFUSE;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_EFUSE_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/extmem_reg.h b/components/soc/esp32c3/include/soc/extmem_reg.h
new file mode 100644
index 0000000000..71ab60f640
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/extmem_reg.h
@@ -0,0 +1,992 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_EXTMEM_REG_H_
+#define _SOC_EXTMEM_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define EXTMEM_ICACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x000)
+/* EXTMEM_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to activate the data cache. 0: disable  1: enable*/
+#define EXTMEM_ICACHE_ENABLE  (BIT(0))
+#define EXTMEM_ICACHE_ENABLE_M  (BIT(0))
+#define EXTMEM_ICACHE_ENABLE_V  0x1
+#define EXTMEM_ICACHE_ENABLE_S  0
+
+#define EXTMEM_ICACHE_CTRL1_REG          (DR_REG_EXTMEM_BASE + 0x004)
+/* EXTMEM_ICACHE_SHUT_DBUS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: The bit is used to disable core1 ibus  0: enable  1: disable*/
+#define EXTMEM_ICACHE_SHUT_DBUS  (BIT(1))
+#define EXTMEM_ICACHE_SHUT_DBUS_M  (BIT(1))
+#define EXTMEM_ICACHE_SHUT_DBUS_V  0x1
+#define EXTMEM_ICACHE_SHUT_DBUS_S  1
+/* EXTMEM_ICACHE_SHUT_IBUS : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to disable core0 ibus  0: enable  1: disable*/
+#define EXTMEM_ICACHE_SHUT_IBUS  (BIT(0))
+#define EXTMEM_ICACHE_SHUT_IBUS_M  (BIT(0))
+#define EXTMEM_ICACHE_SHUT_IBUS_V  0x1
+#define EXTMEM_ICACHE_SHUT_IBUS_S  0
+
+#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x008)
+/* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to power  icache tag memory up  0: follow rtc_lslp  1: power up*/
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU  (BIT(2))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M  (BIT(2))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V  0x1
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S  2
+/* EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to power  icache tag memory down  0: follow rtc_lslp
+  1: power down*/
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD  (BIT(1))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M  (BIT(1))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V  0x1
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S  1
+/* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to close clock gating of  icache tag memory.
+ 1: close gating  0: open clock gating.*/
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON  (BIT(0))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M  (BIT(0))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V  0x1
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S  0
+
+#define EXTMEM_ICACHE_PRELOCK_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x00C)
+/* EXTMEM_ICACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The bit is used to enable the second section of prelock function.*/
+#define EXTMEM_ICACHE_PRELOCK_SCT1_EN  (BIT(1))
+#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_V  0x1
+#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_S  1
+/* EXTMEM_ICACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The bit is used to enable the first section of prelock function.*/
+#define EXTMEM_ICACHE_PRELOCK_SCT0_EN  (BIT(0))
+#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_M  (BIT(0))
+#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_V  0x1
+#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_S  0
+
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x010)
+/* EXTMEM_ICACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to configure the first start virtual address
+ of data prelock  which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG*/
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR  0xFFFFFFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_M  ((EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S))
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S  0
+
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x014)
+/* EXTMEM_ICACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to configure the second start virtual address
+ of data prelock  which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG*/
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR  0xFFFFFFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_M  ((EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S))
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S  0
+
+#define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x018)
+/* EXTMEM_ICACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: The bits are used to configure the first length of data locking
+  which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/
+#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE  0x0000FFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_M  ((EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S))
+#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V  0xFFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S  16
+/* EXTMEM_ICACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: The bits are used to configure the second length of data locking
+  which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/
+#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE  0x0000FFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_M  ((EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S))
+#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V  0xFFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S  0
+
+#define EXTMEM_ICACHE_LOCK_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x01C)
+/* EXTMEM_ICACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to indicate unlock/lock operation is finished.*/
+#define EXTMEM_ICACHE_LOCK_DONE  (BIT(2))
+#define EXTMEM_ICACHE_LOCK_DONE_M  (BIT(2))
+#define EXTMEM_ICACHE_LOCK_DONE_V  0x1
+#define EXTMEM_ICACHE_LOCK_DONE_S  2
+/* EXTMEM_ICACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable unlock operation. It will be cleared
+ by hardware after unlock operation done.*/
+#define EXTMEM_ICACHE_UNLOCK_ENA  (BIT(1))
+#define EXTMEM_ICACHE_UNLOCK_ENA_M  (BIT(1))
+#define EXTMEM_ICACHE_UNLOCK_ENA_V  0x1
+#define EXTMEM_ICACHE_UNLOCK_ENA_S  1
+/* EXTMEM_ICACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable lock operation. It will be cleared
+ by hardware after lock operation done.*/
+#define EXTMEM_ICACHE_LOCK_ENA  (BIT(0))
+#define EXTMEM_ICACHE_LOCK_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_LOCK_ENA_V  0x1
+#define EXTMEM_ICACHE_LOCK_ENA_S  0
+
+#define EXTMEM_ICACHE_LOCK_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x020)
+/* EXTMEM_ICACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address for
+ lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.*/
+#define EXTMEM_ICACHE_LOCK_ADDR  0xFFFFFFFF
+#define EXTMEM_ICACHE_LOCK_ADDR_M  ((EXTMEM_ICACHE_LOCK_ADDR_V)<<(EXTMEM_ICACHE_LOCK_ADDR_S))
+#define EXTMEM_ICACHE_LOCK_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_LOCK_ADDR_S  0
+
+#define EXTMEM_ICACHE_LOCK_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x024)
+/* EXTMEM_ICACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: The bits are used to configure the length for lock operations.
+ The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/
+#define EXTMEM_ICACHE_LOCK_SIZE  0x0000FFFF
+#define EXTMEM_ICACHE_LOCK_SIZE_M  ((EXTMEM_ICACHE_LOCK_SIZE_V)<<(EXTMEM_ICACHE_LOCK_SIZE_S))
+#define EXTMEM_ICACHE_LOCK_SIZE_V  0xFFFF
+#define EXTMEM_ICACHE_LOCK_SIZE_S  0
+
+#define EXTMEM_ICACHE_SYNC_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x028)
+/* EXTMEM_ICACHE_SYNC_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to indicate invalidate operation is finished.*/
+#define EXTMEM_ICACHE_SYNC_DONE  (BIT(1))
+#define EXTMEM_ICACHE_SYNC_DONE_M  (BIT(1))
+#define EXTMEM_ICACHE_SYNC_DONE_V  0x1
+#define EXTMEM_ICACHE_SYNC_DONE_S  1
+/* EXTMEM_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to enable invalidate operation. It will be cleared
+ by hardware after invalidate operation done.*/
+#define EXTMEM_ICACHE_INVALIDATE_ENA  (BIT(0))
+#define EXTMEM_ICACHE_INVALIDATE_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_INVALIDATE_ENA_V  0x1
+#define EXTMEM_ICACHE_INVALIDATE_ENA_S  0
+
+#define EXTMEM_ICACHE_SYNC_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x02C)
+/* EXTMEM_ICACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address for
+ clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.*/
+#define EXTMEM_ICACHE_SYNC_ADDR  0xFFFFFFFF
+#define EXTMEM_ICACHE_SYNC_ADDR_M  ((EXTMEM_ICACHE_SYNC_ADDR_V)<<(EXTMEM_ICACHE_SYNC_ADDR_S))
+#define EXTMEM_ICACHE_SYNC_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_SYNC_ADDR_S  0
+
+#define EXTMEM_ICACHE_SYNC_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x030)
+/* EXTMEM_ICACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */
+/*description: The bits are used to configure the length for sync operations.
+ The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/
+#define EXTMEM_ICACHE_SYNC_SIZE  0x007FFFFF
+#define EXTMEM_ICACHE_SYNC_SIZE_M  ((EXTMEM_ICACHE_SYNC_SIZE_V)<<(EXTMEM_ICACHE_SYNC_SIZE_S))
+#define EXTMEM_ICACHE_SYNC_SIZE_V  0x7FFFFF
+#define EXTMEM_ICACHE_SYNC_SIZE_S  0
+
+#define EXTMEM_ICACHE_PRELOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x034)
+/* EXTMEM_ICACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to configure the direction of preload operation.
+ 1: descending  0: ascending.*/
+#define EXTMEM_ICACHE_PRELOAD_ORDER  (BIT(2))
+#define EXTMEM_ICACHE_PRELOAD_ORDER_M  (BIT(2))
+#define EXTMEM_ICACHE_PRELOAD_ORDER_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_ORDER_S  2
+/* EXTMEM_ICACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: The bit is used to indicate preload operation is finished.*/
+#define EXTMEM_ICACHE_PRELOAD_DONE  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_DONE_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_DONE_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_DONE_S  1
+/* EXTMEM_ICACHE_PRELOAD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable preload operation. It will be cleared
+ by hardware after preload operation done.*/
+#define EXTMEM_ICACHE_PRELOAD_ENA  (BIT(0))
+#define EXTMEM_ICACHE_PRELOAD_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_PRELOAD_ENA_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_ENA_S  0
+
+#define EXTMEM_ICACHE_PRELOAD_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x038)
+/* EXTMEM_ICACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address for
+ preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.*/
+#define EXTMEM_ICACHE_PRELOAD_ADDR  0xFFFFFFFF
+#define EXTMEM_ICACHE_PRELOAD_ADDR_M  ((EXTMEM_ICACHE_PRELOAD_ADDR_V)<<(EXTMEM_ICACHE_PRELOAD_ADDR_S))
+#define EXTMEM_ICACHE_PRELOAD_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_PRELOAD_ADDR_S  0
+
+#define EXTMEM_ICACHE_PRELOAD_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x03C)
+/* EXTMEM_ICACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: The bits are used to configure the length for preload operation.
+ The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/
+#define EXTMEM_ICACHE_PRELOAD_SIZE  0x0000FFFF
+#define EXTMEM_ICACHE_PRELOAD_SIZE_M  ((EXTMEM_ICACHE_PRELOAD_SIZE_V)<<(EXTMEM_ICACHE_PRELOAD_SIZE_S))
+#define EXTMEM_ICACHE_PRELOAD_SIZE_V  0xFFFF
+#define EXTMEM_ICACHE_PRELOAD_SIZE_S  0
+
+#define EXTMEM_ICACHE_AUTOLOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x040)
+/* EXTMEM_ICACHE_AUTOLOAD_RQST : R/W ;bitpos:[6:5] ;default: 2'b0 ; */
+/*description: The bits are used to configure trigger conditions for autoload.
+ 0/3: cache miss  1: cache hit  2: both cache miss and hit.*/
+#define EXTMEM_ICACHE_AUTOLOAD_RQST  0x00000003
+#define EXTMEM_ICACHE_AUTOLOAD_RQST_M  ((EXTMEM_ICACHE_AUTOLOAD_RQST_V)<<(EXTMEM_ICACHE_AUTOLOAD_RQST_S))
+#define EXTMEM_ICACHE_AUTOLOAD_RQST_V  0x3
+#define EXTMEM_ICACHE_AUTOLOAD_RQST_S  5
+/* EXTMEM_ICACHE_AUTOLOAD_ORDER : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bits are used to configure the direction of autoload. 1:
+ descending  0: ascending.*/
+#define EXTMEM_ICACHE_AUTOLOAD_ORDER  (BIT(4))
+#define EXTMEM_ICACHE_AUTOLOAD_ORDER_M  (BIT(4))
+#define EXTMEM_ICACHE_AUTOLOAD_ORDER_V  0x1
+#define EXTMEM_ICACHE_AUTOLOAD_ORDER_S  4
+/* EXTMEM_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b1 ; */
+/*description: The bit is used to indicate autoload operation is finished.*/
+#define EXTMEM_ICACHE_AUTOLOAD_DONE  (BIT(3))
+#define EXTMEM_ICACHE_AUTOLOAD_DONE_M  (BIT(3))
+#define EXTMEM_ICACHE_AUTOLOAD_DONE_V  0x1
+#define EXTMEM_ICACHE_AUTOLOAD_DONE_S  3
+/* EXTMEM_ICACHE_AUTOLOAD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to enable and disable autoload operation. It
+ is combined with icache_autoload_done. 1: enable  0: disable.*/
+#define EXTMEM_ICACHE_AUTOLOAD_ENA  (BIT(2))
+#define EXTMEM_ICACHE_AUTOLOAD_ENA_M  (BIT(2))
+#define EXTMEM_ICACHE_AUTOLOAD_ENA_V  0x1
+#define EXTMEM_ICACHE_AUTOLOAD_ENA_S  2
+/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bits are used to enable the second section for autoload operation.*/
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA  (BIT(1))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_M  (BIT(1))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V  0x1
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S  1
+/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bits are used to enable the first section for autoload operation.*/
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA  (BIT(0))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V  0x1
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S  0
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x044)
+/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address of the
+ first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR  0xFFFFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x048)
+/* EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
+/*description: The bits are used to configure the length of the first section
+ for autoload operation. It should be combined with icache_autoload_sct0_ena.*/
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE  0x07FFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V  0x7FFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x04C)
+/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address of the
+ second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR  0xFFFFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x050)
+/* EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
+/*description: The bits are used to configure the length of the second section
+ for autoload operation. It should be combined with icache_autoload_sct1_ena.*/
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE  0x07FFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V  0x7FFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x054)
+/* EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h42000000 ; */
+/*description: The bits are used to configure the start virtual address of ibus
+ to access flash. The register is used to give constraints to ibus access counter.*/
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR  0xFFFFFFFF
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_M  ((EXTMEM_IBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_START_VADDR_S))
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_V  0xFFFFFFFF
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_S  0
+
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x058)
+/* EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h427FFFFF ; */
+/*description: The bits are used to configure the end virtual address of ibus
+ to access flash. The register is used to give constraints to ibus access counter.*/
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR  0xFFFFFFFF
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_M  ((EXTMEM_IBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_END_VADDR_S))
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_V  0xFFFFFFFF
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_S  0
+
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x05C)
+/* EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3C000000 ; */
+/*description: The bits are used to configure the start virtual address of dbus
+ to access flash. The register is used to give constraints to dbus access counter.*/
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR  0xFFFFFFFF
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_M  ((EXTMEM_DBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_START_VADDR_S))
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_V  0xFFFFFFFF
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_S  0
+
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x060)
+/* EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3C7FFFFF ; */
+/*description: The bits are used to configure the end virtual address of dbus
+ to access flash. The register is used to give constraints to dbus access counter.*/
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR  0xFFFFFFFF
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_M  ((EXTMEM_DBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_END_VADDR_S))
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_V  0xFFFFFFFF
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_S  0
+
+#define EXTMEM_CACHE_ACS_CNT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x064)
+/* EXTMEM_DBUS_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to clear dbus counter.*/
+#define EXTMEM_DBUS_ACS_CNT_CLR  (BIT(1))
+#define EXTMEM_DBUS_ACS_CNT_CLR_M  (BIT(1))
+#define EXTMEM_DBUS_ACS_CNT_CLR_V  0x1
+#define EXTMEM_DBUS_ACS_CNT_CLR_S  1
+/* EXTMEM_IBUS_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to clear ibus counter.*/
+#define EXTMEM_IBUS_ACS_CNT_CLR  (BIT(0))
+#define EXTMEM_IBUS_ACS_CNT_CLR_M  (BIT(0))
+#define EXTMEM_IBUS_ACS_CNT_CLR_V  0x1
+#define EXTMEM_IBUS_ACS_CNT_CLR_S  0
+
+#define EXTMEM_IBUS_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x068)
+/* EXTMEM_IBUS_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to count the number of the cache miss caused
+ by ibus access flash.*/
+#define EXTMEM_IBUS_ACS_MISS_CNT  0xFFFFFFFF
+#define EXTMEM_IBUS_ACS_MISS_CNT_M  ((EXTMEM_IBUS_ACS_MISS_CNT_V)<<(EXTMEM_IBUS_ACS_MISS_CNT_S))
+#define EXTMEM_IBUS_ACS_MISS_CNT_V  0xFFFFFFFF
+#define EXTMEM_IBUS_ACS_MISS_CNT_S  0
+
+#define EXTMEM_IBUS_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x06C)
+/* EXTMEM_IBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to count the number of ibus access flash through icache.*/
+#define EXTMEM_IBUS_ACS_CNT  0xFFFFFFFF
+#define EXTMEM_IBUS_ACS_CNT_M  ((EXTMEM_IBUS_ACS_CNT_V)<<(EXTMEM_IBUS_ACS_CNT_S))
+#define EXTMEM_IBUS_ACS_CNT_V  0xFFFFFFFF
+#define EXTMEM_IBUS_ACS_CNT_S  0
+
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x070)
+/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to count the number of the cache miss caused
+ by dbus access flash.*/
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT  0xFFFFFFFF
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_M  ((EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S))
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V  0xFFFFFFFF
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S  0
+
+#define EXTMEM_DBUS_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x074)
+/* EXTMEM_DBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to count the number of dbus access flash through icache.*/
+#define EXTMEM_DBUS_ACS_CNT  0xFFFFFFFF
+#define EXTMEM_DBUS_ACS_CNT_M  ((EXTMEM_DBUS_ACS_CNT_V)<<(EXTMEM_DBUS_ACS_CNT_S))
+#define EXTMEM_DBUS_ACS_CNT_V  0xFFFFFFFF
+#define EXTMEM_DBUS_ACS_CNT_S  0
+
+#define EXTMEM_CACHE_ILG_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x078)
+/* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by dbus counter overflow.*/
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA  (BIT(8))
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M  (BIT(8))
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V  0x1
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S  8
+/* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by ibus counter overflow.*/
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA  (BIT(7))
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M  (BIT(7))
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V  0x1
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S  7
+/* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by mmu entry fault.*/
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA  (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M  (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V  0x1
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S  5
+/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by preload configurations fault.*/
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S  1
+/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by sync configurations fault.*/
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V  0x1
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S  0
+
+#define EXTMEM_CACHE_ILG_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x07C)
+/* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by dbus counter overflow.*/
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR  (BIT(8))
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M  (BIT(8))
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V  0x1
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S  8
+/* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by ibus counter overflow.*/
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR  (BIT(7))
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M  (BIT(7))
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V  0x1
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S  7
+/* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by mmu entry fault.*/
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR  (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M  (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V  0x1
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S  5
+/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by preload configurations fault.*/
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S  1
+/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by sync configurations fault.*/
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V  0x1
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S  0
+
+#define EXTMEM_CACHE_ILG_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x080)
+/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by dbus access flash miss
+ counter overflow.*/
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST  (BIT(10))
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M  (BIT(10))
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V  0x1
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S  10
+/* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by dbus access flash/spiram
+ counter overflow.*/
+#define EXTMEM_DBUS_ACS_CNT_OVF_ST  (BIT(9))
+#define EXTMEM_DBUS_ACS_CNT_OVF_ST_M  (BIT(9))
+#define EXTMEM_DBUS_ACS_CNT_OVF_ST_V  0x1
+#define EXTMEM_DBUS_ACS_CNT_OVF_ST_S  9
+/* EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by ibus access flash/spiram
+ miss counter overflow.*/
+#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST  (BIT(8))
+#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M  (BIT(8))
+#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V  0x1
+#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S  8
+/* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by ibus access flash/spiram
+ counter overflow.*/
+#define EXTMEM_IBUS_ACS_CNT_OVF_ST  (BIT(7))
+#define EXTMEM_IBUS_ACS_CNT_OVF_ST_M  (BIT(7))
+#define EXTMEM_IBUS_ACS_CNT_OVF_ST_V  0x1
+#define EXTMEM_IBUS_ACS_CNT_OVF_ST_S  7
+/* EXTMEM_MMU_ENTRY_FAULT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by mmu entry fault.*/
+#define EXTMEM_MMU_ENTRY_FAULT_ST  (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_ST_M  (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_ST_V  0x1
+#define EXTMEM_MMU_ENTRY_FAULT_ST_S  5
+/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by preload configurations fault.*/
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S  1
+/* EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by sync configurations fault.*/
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V  0x1
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S  0
+
+#define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x084)
+/* EXTMEM_CORE0_DBUS_WR_IC_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by dbus trying to write icache*/
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA  (BIT(5))
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_M  (BIT(5))
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_V  0x1
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_S  5
+/* EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by authentication fail.*/
+#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA  (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M  (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V  0x1
+#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S  4
+/* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by cpu access icache while
+ the corresponding dbus is disabled which include speculative access.*/
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA  (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_M  (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_V  0x1
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_S  3
+/* EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by authentication fail.*/
+#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA  (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M  (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V  0x1
+#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S  2
+/* EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by ibus trying to write icache*/
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA  (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M  (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V  0x1
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S  1
+/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by cpu access icache while
+ the corresponding ibus is disabled which include speculative access.*/
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA  (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M  (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V  0x1
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S  0
+
+#define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x088)
+/* EXTMEM_CORE0_DBUS_WR_IC_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by dbus trying to write icache*/
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR  (BIT(5))
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_M  (BIT(5))
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_V  0x1
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_S  5
+/* EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by authentication fail.*/
+#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR  (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M  (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V  0x1
+#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S  4
+/* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by cpu access icache while
+ the corresponding dbus is disabled or icache is disabled which include speculative access.*/
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR  (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_M  (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_V  0x1
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_S  3
+/* EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by authentication fail.*/
+#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR  (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M  (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V  0x1
+#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S  2
+/* EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by ibus trying to write icache*/
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR  (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M  (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V  0x1
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S  1
+/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by cpu access icache while
+ the corresponding ibus is disabled or icache is disabled which include speculative access.*/
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR  (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M  (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V  0x1
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S  0
+
+#define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x08C)
+/* EXTMEM_CORE0_DBUS_WR_ICACHE_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by dbus trying to write icache*/
+#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST  (BIT(5))
+#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_M  (BIT(5))
+#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_V  0x1
+#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_S  5
+/* EXTMEM_CORE0_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by authentication fail.*/
+#define EXTMEM_CORE0_DBUS_REJECT_ST  (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_ST_M  (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_ST_V  0x1
+#define EXTMEM_CORE0_DBUS_REJECT_ST_S  4
+/* EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by cpu access icache while
+ the core0_dbus is disabled or icache is disabled which include speculative access.*/
+#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST  (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_M  (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_V  0x1
+#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_S  3
+/* EXTMEM_CORE0_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by authentication fail.*/
+#define EXTMEM_CORE0_IBUS_REJECT_ST  (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_ST_M  (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_ST_V  0x1
+#define EXTMEM_CORE0_IBUS_REJECT_ST_S  2
+/* EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by ibus trying to write icache*/
+#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST  (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M  (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V  0x1
+#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S  1
+/* EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by cpu access  icache while
+ the core0_ibus is disabled or icache is disabled which include speculative access.*/
+#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST  (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M  (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V  0x1
+#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S  0
+
+#define EXTMEM_CORE0_DBUS_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x090)
+/* EXTMEM_CORE0_DBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the world of CPU access dbus when
+ authentication fail. 0: WORLD0  1: WORLD1*/
+#define EXTMEM_CORE0_DBUS_WORLD  (BIT(3))
+#define EXTMEM_CORE0_DBUS_WORLD_M  (BIT(3))
+#define EXTMEM_CORE0_DBUS_WORLD_V  0x1
+#define EXTMEM_CORE0_DBUS_WORLD_S  3
+/* EXTMEM_CORE0_DBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: The bits are used to indicate the attribute of CPU access dbus
+ when authentication fail. 0: invalidate  1: execute-able  2: read-able  4: write-able.*/
+#define EXTMEM_CORE0_DBUS_ATTR  0x00000007
+#define EXTMEM_CORE0_DBUS_ATTR_M  ((EXTMEM_CORE0_DBUS_ATTR_V)<<(EXTMEM_CORE0_DBUS_ATTR_S))
+#define EXTMEM_CORE0_DBUS_ATTR_V  0x7
+#define EXTMEM_CORE0_DBUS_ATTR_S  0
+
+#define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x094)
+/* EXTMEM_CORE0_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: The bits are used to indicate the virtual address of CPU access
+ dbus when authentication fail.*/
+#define EXTMEM_CORE0_DBUS_VADDR  0xFFFFFFFF
+#define EXTMEM_CORE0_DBUS_VADDR_M  ((EXTMEM_CORE0_DBUS_VADDR_V)<<(EXTMEM_CORE0_DBUS_VADDR_S))
+#define EXTMEM_CORE0_DBUS_VADDR_V  0xFFFFFFFF
+#define EXTMEM_CORE0_DBUS_VADDR_S  0
+
+#define EXTMEM_CORE0_IBUS_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x098)
+/* EXTMEM_CORE0_IBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the world of CPU access ibus when
+ authentication fail. 0: WORLD0  1: WORLD1*/
+#define EXTMEM_CORE0_IBUS_WORLD  (BIT(3))
+#define EXTMEM_CORE0_IBUS_WORLD_M  (BIT(3))
+#define EXTMEM_CORE0_IBUS_WORLD_V  0x1
+#define EXTMEM_CORE0_IBUS_WORLD_S  3
+/* EXTMEM_CORE0_IBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: The bits are used to indicate the attribute of CPU access ibus
+ when authentication fail. 0: invalidate  1: execute-able  2: read-able*/
+#define EXTMEM_CORE0_IBUS_ATTR  0x00000007
+#define EXTMEM_CORE0_IBUS_ATTR_M  ((EXTMEM_CORE0_IBUS_ATTR_V)<<(EXTMEM_CORE0_IBUS_ATTR_S))
+#define EXTMEM_CORE0_IBUS_ATTR_V  0x7
+#define EXTMEM_CORE0_IBUS_ATTR_S  0
+
+#define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x09C)
+/* EXTMEM_CORE0_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: The bits are used to indicate the virtual address of CPU access
+  ibus when authentication fail.*/
+#define EXTMEM_CORE0_IBUS_VADDR  0xFFFFFFFF
+#define EXTMEM_CORE0_IBUS_VADDR_M  ((EXTMEM_CORE0_IBUS_VADDR_V)<<(EXTMEM_CORE0_IBUS_VADDR_S))
+#define EXTMEM_CORE0_IBUS_VADDR_V  0xFFFFFFFF
+#define EXTMEM_CORE0_IBUS_VADDR_S  0
+
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG          (DR_REG_EXTMEM_BASE + 0x0A0)
+/* EXTMEM_CACHE_MMU_FAULT_CODE : RO ;bitpos:[13:10] ;default: 4'h0 ; */
+/*description: The right-most 3 bits are used to indicate the operations which
+ cause mmu fault occurrence. 0: default  1: cpu miss  2: preload miss  3: writeback  4: cpu miss evict recovery address  5: load miss evict recovery address  6: external dma tx  7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.*/
+#define EXTMEM_CACHE_MMU_FAULT_CODE  0x0000000F
+#define EXTMEM_CACHE_MMU_FAULT_CODE_M  ((EXTMEM_CACHE_MMU_FAULT_CODE_V)<<(EXTMEM_CACHE_MMU_FAULT_CODE_S))
+#define EXTMEM_CACHE_MMU_FAULT_CODE_V  0xF
+#define EXTMEM_CACHE_MMU_FAULT_CODE_S  10
+/* EXTMEM_CACHE_MMU_FAULT_CONTENT : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The bits are used to indicate the content of mmu entry which cause mmu fault..*/
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT  0x000003FF
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT_M  ((EXTMEM_CACHE_MMU_FAULT_CONTENT_V)<<(EXTMEM_CACHE_MMU_FAULT_CONTENT_S))
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT_V  0x3FF
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT_S  0
+
+#define EXTMEM_CACHE_MMU_FAULT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x0A4)
+/* EXTMEM_CACHE_MMU_FAULT_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to indicate the virtual address which cause mmu fault..*/
+#define EXTMEM_CACHE_MMU_FAULT_VADDR  0xFFFFFFFF
+#define EXTMEM_CACHE_MMU_FAULT_VADDR_M  ((EXTMEM_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_CACHE_MMU_FAULT_VADDR_S))
+#define EXTMEM_CACHE_MMU_FAULT_VADDR_V  0xFFFFFFFF
+#define EXTMEM_CACHE_MMU_FAULT_VADDR_S  0
+
+#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x0A8)
+/* EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable wrap around mode when read data from flash.*/
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND  (BIT(0))
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M  (BIT(0))
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V  0x1
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND_S  0
+
+#define EXTMEM_CACHE_MMU_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x0AC)
+/* EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to power mmu memory down  0: follow_rtc_lslp_pd  1: power up*/
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PU  (BIT(2))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M  (BIT(2))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V  0x1
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S  2
+/* EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to power mmu memory down  0: follow_rtc_lslp_pd  1: power down*/
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PD  (BIT(1))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M  (BIT(1))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V  0x1
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S  1
+/* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to enable clock gating to save power when access
+ mmu memory  0: enable  1: disable*/
+#define EXTMEM_CACHE_MMU_MEM_FORCE_ON  (BIT(0))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M  (BIT(0))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V  0x1
+#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S  0
+
+#define EXTMEM_CACHE_STATE_REG          (DR_REG_EXTMEM_BASE + 0x0B0)
+/* EXTMEM_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h1 ; */
+/*description: The bit is used to indicate whether  icache main fsm is in idle
+ state or not. 1: in idle state   0: not in idle state*/
+#define EXTMEM_ICACHE_STATE  0x00000FFF
+#define EXTMEM_ICACHE_STATE_M  ((EXTMEM_ICACHE_STATE_V)<<(EXTMEM_ICACHE_STATE_S))
+#define EXTMEM_ICACHE_STATE_V  0xFFF
+#define EXTMEM_ICACHE_STATE_S  0
+
+#define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG          (DR_REG_EXTMEM_BASE + 0x0B4)
+/* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Reserved.*/
+#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT  (BIT(1))
+#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M  (BIT(1))
+#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V  0x1
+#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S  1
+/* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Reserved.*/
+#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT  (BIT(0))
+#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M  (BIT(0))
+#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V  0x1
+#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S  0
+
+#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG          (DR_REG_EXTMEM_BASE + 0x0B8)
+/* EXTMEM_CLK_FORCE_ON_CRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to close clock gating of external memory encrypt
+ and decrypt clock. 1: close gating  0: open clock gating.*/
+#define EXTMEM_CLK_FORCE_ON_CRYPT  (BIT(2))
+#define EXTMEM_CLK_FORCE_ON_CRYPT_M  (BIT(2))
+#define EXTMEM_CLK_FORCE_ON_CRYPT_V  0x1
+#define EXTMEM_CLK_FORCE_ON_CRYPT_S  2
+/* EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: The bit is used to close clock gating of automatic crypt clock.
+ 1: close gating  0: open clock gating.*/
+#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT  (BIT(1))
+#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M  (BIT(1))
+#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V  0x1
+#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S  1
+/* EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to close clock gating of manual crypt clock.
+ 1: close gating  0: open clock gating.*/
+#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT  (BIT(0))
+#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M  (BIT(0))
+#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V  0x1
+#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S  0
+
+#define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x0BC)
+/* EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to clear the interrupt by  icache pre-load done.*/
+#define EXTMEM_ICACHE_PRELOAD_INT_CLR  (BIT(2))
+#define EXTMEM_ICACHE_PRELOAD_INT_CLR_M  (BIT(2))
+#define EXTMEM_ICACHE_PRELOAD_INT_CLR_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_INT_CLR_S  2
+/* EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt by  icache pre-load done.*/
+#define EXTMEM_ICACHE_PRELOAD_INT_ENA  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_INT_ENA_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_INT_ENA_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_INT_ENA_S  1
+/* EXTMEM_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the interrupt by  icache pre-load done.*/
+#define EXTMEM_ICACHE_PRELOAD_INT_ST  (BIT(0))
+#define EXTMEM_ICACHE_PRELOAD_INT_ST_M  (BIT(0))
+#define EXTMEM_ICACHE_PRELOAD_INT_ST_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_INT_ST_S  0
+
+#define EXTMEM_CACHE_SYNC_INT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x0C0)
+/* EXTMEM_ICACHE_SYNC_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to clear the interrupt by  icache sync done.*/
+#define EXTMEM_ICACHE_SYNC_INT_CLR  (BIT(2))
+#define EXTMEM_ICACHE_SYNC_INT_CLR_M  (BIT(2))
+#define EXTMEM_ICACHE_SYNC_INT_CLR_V  0x1
+#define EXTMEM_ICACHE_SYNC_INT_CLR_S  2
+/* EXTMEM_ICACHE_SYNC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt by  icache sync done.*/
+#define EXTMEM_ICACHE_SYNC_INT_ENA  (BIT(1))
+#define EXTMEM_ICACHE_SYNC_INT_ENA_M  (BIT(1))
+#define EXTMEM_ICACHE_SYNC_INT_ENA_V  0x1
+#define EXTMEM_ICACHE_SYNC_INT_ENA_S  1
+/* EXTMEM_ICACHE_SYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the interrupt by  icache sync done.*/
+#define EXTMEM_ICACHE_SYNC_INT_ST  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_INT_ST_M  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_INT_ST_V  0x1
+#define EXTMEM_ICACHE_SYNC_INT_ST_S  0
+
+#define EXTMEM_CACHE_MMU_OWNER_REG          (DR_REG_EXTMEM_BASE + 0x0C4)
+/* EXTMEM_CACHE_MMU_OWNER : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: The bits are used to specify the owner of MMU.bit0/bit2: ibus  bit1/bit3: dbus*/
+#define EXTMEM_CACHE_MMU_OWNER  0x0000000F
+#define EXTMEM_CACHE_MMU_OWNER_M  ((EXTMEM_CACHE_MMU_OWNER_V)<<(EXTMEM_CACHE_MMU_OWNER_S))
+#define EXTMEM_CACHE_MMU_OWNER_V  0xF
+#define EXTMEM_CACHE_MMU_OWNER_S  0
+
+#define EXTMEM_CACHE_CONF_MISC_REG          (DR_REG_EXTMEM_BASE + 0x0C8)
+/* EXTMEM_CACHE_TRACE_ENA : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to enable cache trace function.*/
+#define EXTMEM_CACHE_TRACE_ENA  (BIT(2))
+#define EXTMEM_CACHE_TRACE_ENA_M  (BIT(2))
+#define EXTMEM_CACHE_TRACE_ENA_V  0x1
+#define EXTMEM_CACHE_TRACE_ENA_S  2
+/* EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: The bit is used to disable checking mmu entry fault by sync operation.*/
+#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT  (BIT(1))
+#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M  (BIT(1))
+#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V  0x1
+#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S  1
+/* EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to disable checking mmu entry fault by preload operation.*/
+#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT  (BIT(0))
+#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M  (BIT(0))
+#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V  0x1
+#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S  0
+
+#define EXTMEM_ICACHE_FREEZE_REG          (DR_REG_EXTMEM_BASE + 0x0CC)
+/* EXTMEM_ICACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to indicate icache freeze success*/
+#define EXTMEM_ICACHE_FREEZE_DONE  (BIT(2))
+#define EXTMEM_ICACHE_FREEZE_DONE_M  (BIT(2))
+#define EXTMEM_ICACHE_FREEZE_DONE_V  0x1
+#define EXTMEM_ICACHE_FREEZE_DONE_S  2
+/* EXTMEM_ICACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to configure freeze mode  0:  assert busy if
+ CPU miss 1: assert hit if CPU miss*/
+#define EXTMEM_ICACHE_FREEZE_MODE  (BIT(1))
+#define EXTMEM_ICACHE_FREEZE_MODE_M  (BIT(1))
+#define EXTMEM_ICACHE_FREEZE_MODE_V  0x1
+#define EXTMEM_ICACHE_FREEZE_MODE_S  1
+/* EXTMEM_ICACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable icache freeze mode*/
+#define EXTMEM_ICACHE_FREEZE_ENA  (BIT(0))
+#define EXTMEM_ICACHE_FREEZE_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_FREEZE_ENA_V  0x1
+#define EXTMEM_ICACHE_FREEZE_ENA_S  0
+
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG          (DR_REG_EXTMEM_BASE + 0x0D0)
+/* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to activate icache atomic operation protection.
+ In this case  sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA  (BIT(0))
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V  0x1
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S  0
+
+#define EXTMEM_CACHE_REQUEST_REG          (DR_REG_EXTMEM_BASE + 0x0D4)
+/* EXTMEM_CACHE_REQUEST_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to disable request recording which could cause performance issue*/
+#define EXTMEM_CACHE_REQUEST_BYPASS  (BIT(0))
+#define EXTMEM_CACHE_REQUEST_BYPASS_M  (BIT(0))
+#define EXTMEM_CACHE_REQUEST_BYPASS_V  0x1
+#define EXTMEM_CACHE_REQUEST_BYPASS_S  0
+
+#define EXTMEM_IBUS_PMS_TBL_LOCK_REG          (DR_REG_EXTMEM_BASE + 0x0D8)
+/* EXTMEM_IBUS_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to configure the ibus permission control section boundary0*/
+#define EXTMEM_IBUS_PMS_LOCK  (BIT(0))
+#define EXTMEM_IBUS_PMS_LOCK_M  (BIT(0))
+#define EXTMEM_IBUS_PMS_LOCK_V  0x1
+#define EXTMEM_IBUS_PMS_LOCK_S  0
+
+#define EXTMEM_IBUS_PMS_TBL_BOUNDARY0_REG          (DR_REG_EXTMEM_BASE + 0x0DC)
+/* EXTMEM_IBUS_PMS_BOUNDARY0 : R/W ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: The bit is used to configure the ibus permission control section boundary0*/
+#define EXTMEM_IBUS_PMS_BOUNDARY0  0x00000FFF
+#define EXTMEM_IBUS_PMS_BOUNDARY0_M  ((EXTMEM_IBUS_PMS_BOUNDARY0_V)<<(EXTMEM_IBUS_PMS_BOUNDARY0_S))
+#define EXTMEM_IBUS_PMS_BOUNDARY0_V  0xFFF
+#define EXTMEM_IBUS_PMS_BOUNDARY0_S  0
+
+#define EXTMEM_IBUS_PMS_TBL_BOUNDARY1_REG          (DR_REG_EXTMEM_BASE + 0x0E0)
+/* EXTMEM_IBUS_PMS_BOUNDARY1 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */
+/*description: The bit is used to configure the ibus permission control section boundary1*/
+#define EXTMEM_IBUS_PMS_BOUNDARY1  0x00000FFF
+#define EXTMEM_IBUS_PMS_BOUNDARY1_M  ((EXTMEM_IBUS_PMS_BOUNDARY1_V)<<(EXTMEM_IBUS_PMS_BOUNDARY1_S))
+#define EXTMEM_IBUS_PMS_BOUNDARY1_V  0xFFF
+#define EXTMEM_IBUS_PMS_BOUNDARY1_S  0
+
+#define EXTMEM_IBUS_PMS_TBL_BOUNDARY2_REG          (DR_REG_EXTMEM_BASE + 0x0E4)
+/* EXTMEM_IBUS_PMS_BOUNDARY2 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */
+/*description: The bit is used to configure the ibus permission control section boundary2*/
+#define EXTMEM_IBUS_PMS_BOUNDARY2  0x00000FFF
+#define EXTMEM_IBUS_PMS_BOUNDARY2_M  ((EXTMEM_IBUS_PMS_BOUNDARY2_V)<<(EXTMEM_IBUS_PMS_BOUNDARY2_S))
+#define EXTMEM_IBUS_PMS_BOUNDARY2_V  0xFFF
+#define EXTMEM_IBUS_PMS_BOUNDARY2_S  0
+
+#define EXTMEM_IBUS_PMS_TBL_ATTR_REG          (DR_REG_EXTMEM_BASE + 0x0E8)
+/* EXTMEM_IBUS_PMS_SCT2_ATTR : R/W ;bitpos:[7:4] ;default: 4'hF ; */
+/*description: The bit is used to configure attribute of the ibus permission
+ control section2  bit0: fetch in world0  bit1: load in world0  bit2: fetch in world1  bit3: load in world1*/
+#define EXTMEM_IBUS_PMS_SCT2_ATTR  0x0000000F
+#define EXTMEM_IBUS_PMS_SCT2_ATTR_M  ((EXTMEM_IBUS_PMS_SCT2_ATTR_V)<<(EXTMEM_IBUS_PMS_SCT2_ATTR_S))
+#define EXTMEM_IBUS_PMS_SCT2_ATTR_V  0xF
+#define EXTMEM_IBUS_PMS_SCT2_ATTR_S  4
+/* EXTMEM_IBUS_PMS_SCT1_ATTR : R/W ;bitpos:[3:0] ;default: 4'hF ; */
+/*description: The bit is used to configure attribute of the ibus permission
+ control section1  bit0: fetch in world0  bit1: load in world0  bit2: fetch in world1  bit3: load in world1*/
+#define EXTMEM_IBUS_PMS_SCT1_ATTR  0x0000000F
+#define EXTMEM_IBUS_PMS_SCT1_ATTR_M  ((EXTMEM_IBUS_PMS_SCT1_ATTR_V)<<(EXTMEM_IBUS_PMS_SCT1_ATTR_S))
+#define EXTMEM_IBUS_PMS_SCT1_ATTR_V  0xF
+#define EXTMEM_IBUS_PMS_SCT1_ATTR_S  0
+
+#define EXTMEM_DBUS_PMS_TBL_LOCK_REG          (DR_REG_EXTMEM_BASE + 0x0EC)
+/* EXTMEM_DBUS_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to configure the ibus permission control section boundary0*/
+#define EXTMEM_DBUS_PMS_LOCK  (BIT(0))
+#define EXTMEM_DBUS_PMS_LOCK_M  (BIT(0))
+#define EXTMEM_DBUS_PMS_LOCK_V  0x1
+#define EXTMEM_DBUS_PMS_LOCK_S  0
+
+#define EXTMEM_DBUS_PMS_TBL_BOUNDARY0_REG          (DR_REG_EXTMEM_BASE + 0x0F0)
+/* EXTMEM_DBUS_PMS_BOUNDARY0 : R/W ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: The bit is used to configure the dbus permission control section boundary0*/
+#define EXTMEM_DBUS_PMS_BOUNDARY0  0x00000FFF
+#define EXTMEM_DBUS_PMS_BOUNDARY0_M  ((EXTMEM_DBUS_PMS_BOUNDARY0_V)<<(EXTMEM_DBUS_PMS_BOUNDARY0_S))
+#define EXTMEM_DBUS_PMS_BOUNDARY0_V  0xFFF
+#define EXTMEM_DBUS_PMS_BOUNDARY0_S  0
+
+#define EXTMEM_DBUS_PMS_TBL_BOUNDARY1_REG          (DR_REG_EXTMEM_BASE + 0x0F4)
+/* EXTMEM_DBUS_PMS_BOUNDARY1 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */
+/*description: The bit is used to configure the dbus permission control section boundary1*/
+#define EXTMEM_DBUS_PMS_BOUNDARY1  0x00000FFF
+#define EXTMEM_DBUS_PMS_BOUNDARY1_M  ((EXTMEM_DBUS_PMS_BOUNDARY1_V)<<(EXTMEM_DBUS_PMS_BOUNDARY1_S))
+#define EXTMEM_DBUS_PMS_BOUNDARY1_V  0xFFF
+#define EXTMEM_DBUS_PMS_BOUNDARY1_S  0
+
+#define EXTMEM_DBUS_PMS_TBL_BOUNDARY2_REG          (DR_REG_EXTMEM_BASE + 0x0F8)
+/* EXTMEM_DBUS_PMS_BOUNDARY2 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */
+/*description: The bit is used to configure the dbus permission control section boundary2*/
+#define EXTMEM_DBUS_PMS_BOUNDARY2  0x00000FFF
+#define EXTMEM_DBUS_PMS_BOUNDARY2_M  ((EXTMEM_DBUS_PMS_BOUNDARY2_V)<<(EXTMEM_DBUS_PMS_BOUNDARY2_S))
+#define EXTMEM_DBUS_PMS_BOUNDARY2_V  0xFFF
+#define EXTMEM_DBUS_PMS_BOUNDARY2_S  0
+
+#define EXTMEM_DBUS_PMS_TBL_ATTR_REG          (DR_REG_EXTMEM_BASE + 0x0FC)
+/* EXTMEM_DBUS_PMS_SCT2_ATTR : R/W ;bitpos:[3:2] ;default: 2'd3 ; */
+/*description: The bit is used to configure attribute of the dbus permission
+ control section2  bit0: load in world0  bit2: load in world1*/
+#define EXTMEM_DBUS_PMS_SCT2_ATTR  0x00000003
+#define EXTMEM_DBUS_PMS_SCT2_ATTR_M  ((EXTMEM_DBUS_PMS_SCT2_ATTR_V)<<(EXTMEM_DBUS_PMS_SCT2_ATTR_S))
+#define EXTMEM_DBUS_PMS_SCT2_ATTR_V  0x3
+#define EXTMEM_DBUS_PMS_SCT2_ATTR_S  2
+/* EXTMEM_DBUS_PMS_SCT1_ATTR : R/W ;bitpos:[1:0] ;default: 2'd3 ; */
+/*description: The bit is used to configure attribute of the dbus permission
+ control section1  bit0: load in world0  bit2: load in world1*/
+#define EXTMEM_DBUS_PMS_SCT1_ATTR  0x00000003
+#define EXTMEM_DBUS_PMS_SCT1_ATTR_M  ((EXTMEM_DBUS_PMS_SCT1_ATTR_V)<<(EXTMEM_DBUS_PMS_SCT1_ATTR_S))
+#define EXTMEM_DBUS_PMS_SCT1_ATTR_V  0x3
+#define EXTMEM_DBUS_PMS_SCT1_ATTR_S  0
+
+#define EXTMEM_CLOCK_GATE_REG          (DR_REG_EXTMEM_BASE + 0x100)
+/* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Reserved.*/
+#define EXTMEM_CLK_EN  (BIT(0))
+#define EXTMEM_CLK_EN_M  (BIT(0))
+#define EXTMEM_CLK_EN_V  0x1
+#define EXTMEM_CLK_EN_S  0
+
+#define EXTMEM_DATE_REG          (DR_REG_EXTMEM_BASE + 0x3FC)
+/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007160 ; */
+/*description: Reserved.*/
+#define EXTMEM_DATE  0x0FFFFFFF
+#define EXTMEM_DATE_M  ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S))
+#define EXTMEM_DATE_V  0xFFFFFFF
+#define EXTMEM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_EXTMEM_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/gdma_caps.h b/components/soc/esp32c3/include/soc/gdma_caps.h
new file mode 100644
index 0000000000..7263c992da
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/gdma_caps.h
@@ -0,0 +1,17 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#define SOC_GDMA_CHANNELS_NUM (3)       /*!< GDMA has 3 TX and 3 RX */
diff --git a/components/soc/esp32c3/include/soc/gdma_reg.h b/components/soc/esp32c3/include/soc/gdma_reg.h
new file mode 100644
index 0000000000..4ade5dcee7
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/gdma_reg.h
@@ -0,0 +1,2419 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_DMA_REG_H_
+#define _SOC_DMA_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define DMA_INT_RAW_CH0_REG          (DR_REG_GDMA_BASE + 0x000)
+/* DMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
+/*description: This raw interrupt bit turns to high level when level 1 fifo
+ of Tx channel 0 is underflow.*/
+#define DMA_OUTFIFO_UDF_CH0_INT_RAW  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH0_INT_RAW_M  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH0_INT_RAW_V  0x1
+#define DMA_OUTFIFO_UDF_CH0_INT_RAW_S  12
+/* DMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
+/*description: This raw interrupt bit turns to high level when level 1 fifo
+ of Tx channel 0 is overflow.*/
+#define DMA_OUTFIFO_OVF_CH0_INT_RAW  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH0_INT_RAW_M  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH0_INT_RAW_V  0x1
+#define DMA_OUTFIFO_OVF_CH0_INT_RAW_S  11
+/* DMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This raw interrupt bit turns to high level when level 1 fifo
+ of Rx channel 0 is underflow.*/
+#define DMA_INFIFO_UDF_CH0_INT_RAW  (BIT(10))
+#define DMA_INFIFO_UDF_CH0_INT_RAW_M  (BIT(10))
+#define DMA_INFIFO_UDF_CH0_INT_RAW_V  0x1
+#define DMA_INFIFO_UDF_CH0_INT_RAW_S  10
+/* DMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
+/*description: This raw interrupt bit turns to high level when level 1 fifo
+ of Rx channel 0 is overflow.*/
+#define DMA_INFIFO_OVF_CH0_INT_RAW  (BIT(9))
+#define DMA_INFIFO_OVF_CH0_INT_RAW_M  (BIT(9))
+#define DMA_INFIFO_OVF_CH0_INT_RAW_V  0x1
+#define DMA_INFIFO_OVF_CH0_INT_RAW_S  9
+/* DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when data corresponding
+ a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/
+#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V  0x1
+#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S  8
+/* DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when Rx buffer pointed
+ by inlink is full and receiving data is not completed  but there is no more inlink for Rx channel 0.*/
+#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V  0x1
+#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S  7
+/* DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when detecting outlink
+ descriptor error  including owner error  the second and third word error of outlink descriptor for Tx channel 0.*/
+#define DMA_OUT_DSCR_ERR_CH0_INT_RAW  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_M  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_V  0x1
+#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_S  6
+/* DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when detecting inlink
+ descriptor error  including owner error  the second and third word error of inlink descriptor for Rx channel 0.*/
+#define DMA_IN_DSCR_ERR_CH0_INT_RAW  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH0_INT_RAW_M  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH0_INT_RAW_V  0x1
+#define DMA_IN_DSCR_ERR_CH0_INT_RAW_S  5
+/* DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when the last data
+ pointed by one outlink descriptor has been read from memory for Tx channel 0.*/
+#define DMA_OUT_EOF_CH0_INT_RAW  (BIT(4))
+#define DMA_OUT_EOF_CH0_INT_RAW_M  (BIT(4))
+#define DMA_OUT_EOF_CH0_INT_RAW_V  0x1
+#define DMA_OUT_EOF_CH0_INT_RAW_S  4
+/* DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when the last data
+ pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/
+#define DMA_OUT_DONE_CH0_INT_RAW  (BIT(3))
+#define DMA_OUT_DONE_CH0_INT_RAW_M  (BIT(3))
+#define DMA_OUT_DONE_CH0_INT_RAW_V  0x1
+#define DMA_OUT_DONE_CH0_INT_RAW_S  3
+/* DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when data error is
+ detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals  this raw interrupt is reserved.*/
+#define DMA_IN_ERR_EOF_CH0_INT_RAW  (BIT(2))
+#define DMA_IN_ERR_EOF_CH0_INT_RAW_M  (BIT(2))
+#define DMA_IN_ERR_EOF_CH0_INT_RAW_V  0x1
+#define DMA_IN_ERR_EOF_CH0_INT_RAW_S  2
+/* DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when the last data
+ pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0  the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/
+#define DMA_IN_SUC_EOF_CH0_INT_RAW  (BIT(1))
+#define DMA_IN_SUC_EOF_CH0_INT_RAW_M  (BIT(1))
+#define DMA_IN_SUC_EOF_CH0_INT_RAW_V  0x1
+#define DMA_IN_SUC_EOF_CH0_INT_RAW_S  1
+/* DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when the last data
+ pointed by one inlink descriptor has been received for Rx channel 0.*/
+#define DMA_IN_DONE_CH0_INT_RAW  (BIT(0))
+#define DMA_IN_DONE_CH0_INT_RAW_M  (BIT(0))
+#define DMA_IN_DONE_CH0_INT_RAW_V  0x1
+#define DMA_IN_DONE_CH0_INT_RAW_S  0
+
+#define DMA_INT_ST_CH0_REG          (DR_REG_GDMA_BASE + 0x004)
+/* DMA_OUTFIFO_UDF_CH0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
+#define DMA_OUTFIFO_UDF_CH0_INT_ST  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH0_INT_ST_M  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH0_INT_ST_V  0x1
+#define DMA_OUTFIFO_UDF_CH0_INT_ST_S  12
+/* DMA_OUTFIFO_OVF_CH0_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
+#define DMA_OUTFIFO_OVF_CH0_INT_ST  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH0_INT_ST_M  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH0_INT_ST_V  0x1
+#define DMA_OUTFIFO_OVF_CH0_INT_ST_S  11
+/* DMA_INFIFO_UDF_CH0_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
+#define DMA_INFIFO_UDF_CH0_INT_ST  (BIT(10))
+#define DMA_INFIFO_UDF_CH0_INT_ST_M  (BIT(10))
+#define DMA_INFIFO_UDF_CH0_INT_ST_V  0x1
+#define DMA_INFIFO_UDF_CH0_INT_ST_S  10
+/* DMA_INFIFO_OVF_CH0_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
+#define DMA_INFIFO_OVF_CH0_INT_ST  (BIT(9))
+#define DMA_INFIFO_OVF_CH0_INT_ST_M  (BIT(9))
+#define DMA_INFIFO_OVF_CH0_INT_ST_V  0x1
+#define DMA_INFIFO_OVF_CH0_INT_ST_S  9
+/* DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
+#define DMA_OUT_TOTAL_EOF_CH0_INT_ST  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_M  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_V  0x1
+#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_S  8
+/* DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
+#define DMA_IN_DSCR_EMPTY_CH0_INT_ST  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_M  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_V  0x1
+#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_S  7
+/* DMA_OUT_DSCR_ERR_CH0_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
+#define DMA_OUT_DSCR_ERR_CH0_INT_ST  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH0_INT_ST_M  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH0_INT_ST_V  0x1
+#define DMA_OUT_DSCR_ERR_CH0_INT_ST_S  6
+/* DMA_IN_DSCR_ERR_CH0_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/
+#define DMA_IN_DSCR_ERR_CH0_INT_ST  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH0_INT_ST_M  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH0_INT_ST_V  0x1
+#define DMA_IN_DSCR_ERR_CH0_INT_ST_S  5
+/* DMA_OUT_EOF_CH0_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/
+#define DMA_OUT_EOF_CH0_INT_ST  (BIT(4))
+#define DMA_OUT_EOF_CH0_INT_ST_M  (BIT(4))
+#define DMA_OUT_EOF_CH0_INT_ST_V  0x1
+#define DMA_OUT_EOF_CH0_INT_ST_S  4
+/* DMA_OUT_DONE_CH0_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/
+#define DMA_OUT_DONE_CH0_INT_ST  (BIT(3))
+#define DMA_OUT_DONE_CH0_INT_ST_M  (BIT(3))
+#define DMA_OUT_DONE_CH0_INT_ST_V  0x1
+#define DMA_OUT_DONE_CH0_INT_ST_S  3
+/* DMA_IN_ERR_EOF_CH0_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/
+#define DMA_IN_ERR_EOF_CH0_INT_ST  (BIT(2))
+#define DMA_IN_ERR_EOF_CH0_INT_ST_M  (BIT(2))
+#define DMA_IN_ERR_EOF_CH0_INT_ST_V  0x1
+#define DMA_IN_ERR_EOF_CH0_INT_ST_S  2
+/* DMA_IN_SUC_EOF_CH0_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/
+#define DMA_IN_SUC_EOF_CH0_INT_ST  (BIT(1))
+#define DMA_IN_SUC_EOF_CH0_INT_ST_M  (BIT(1))
+#define DMA_IN_SUC_EOF_CH0_INT_ST_V  0x1
+#define DMA_IN_SUC_EOF_CH0_INT_ST_S  1
+/* DMA_IN_DONE_CH0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/
+#define DMA_IN_DONE_CH0_INT_ST  (BIT(0))
+#define DMA_IN_DONE_CH0_INT_ST_M  (BIT(0))
+#define DMA_IN_DONE_CH0_INT_ST_V  0x1
+#define DMA_IN_DONE_CH0_INT_ST_S  0
+
+#define DMA_INT_ENA_CH0_REG          (DR_REG_GDMA_BASE + 0x008)
+/* DMA_OUTFIFO_UDF_CH0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
+#define DMA_OUTFIFO_UDF_CH0_INT_ENA  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH0_INT_ENA_M  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH0_INT_ENA_V  0x1
+#define DMA_OUTFIFO_UDF_CH0_INT_ENA_S  12
+/* DMA_OUTFIFO_OVF_CH0_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
+#define DMA_OUTFIFO_OVF_CH0_INT_ENA  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH0_INT_ENA_M  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH0_INT_ENA_V  0x1
+#define DMA_OUTFIFO_OVF_CH0_INT_ENA_S  11
+/* DMA_INFIFO_UDF_CH0_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
+#define DMA_INFIFO_UDF_CH0_INT_ENA  (BIT(10))
+#define DMA_INFIFO_UDF_CH0_INT_ENA_M  (BIT(10))
+#define DMA_INFIFO_UDF_CH0_INT_ENA_V  0x1
+#define DMA_INFIFO_UDF_CH0_INT_ENA_S  10
+/* DMA_INFIFO_OVF_CH0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
+#define DMA_INFIFO_OVF_CH0_INT_ENA  (BIT(9))
+#define DMA_INFIFO_OVF_CH0_INT_ENA_M  (BIT(9))
+#define DMA_INFIFO_OVF_CH0_INT_ENA_V  0x1
+#define DMA_INFIFO_OVF_CH0_INT_ENA_S  9
+/* DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
+#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V  0x1
+#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S  8
+/* DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
+#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V  0x1
+#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S  7
+/* DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
+#define DMA_OUT_DSCR_ERR_CH0_INT_ENA  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_M  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_V  0x1
+#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_S  6
+/* DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/
+#define DMA_IN_DSCR_ERR_CH0_INT_ENA  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH0_INT_ENA_M  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH0_INT_ENA_V  0x1
+#define DMA_IN_DSCR_ERR_CH0_INT_ENA_S  5
+/* DMA_OUT_EOF_CH0_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/
+#define DMA_OUT_EOF_CH0_INT_ENA  (BIT(4))
+#define DMA_OUT_EOF_CH0_INT_ENA_M  (BIT(4))
+#define DMA_OUT_EOF_CH0_INT_ENA_V  0x1
+#define DMA_OUT_EOF_CH0_INT_ENA_S  4
+/* DMA_OUT_DONE_CH0_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/
+#define DMA_OUT_DONE_CH0_INT_ENA  (BIT(3))
+#define DMA_OUT_DONE_CH0_INT_ENA_M  (BIT(3))
+#define DMA_OUT_DONE_CH0_INT_ENA_V  0x1
+#define DMA_OUT_DONE_CH0_INT_ENA_S  3
+/* DMA_IN_ERR_EOF_CH0_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/
+#define DMA_IN_ERR_EOF_CH0_INT_ENA  (BIT(2))
+#define DMA_IN_ERR_EOF_CH0_INT_ENA_M  (BIT(2))
+#define DMA_IN_ERR_EOF_CH0_INT_ENA_V  0x1
+#define DMA_IN_ERR_EOF_CH0_INT_ENA_S  2
+/* DMA_IN_SUC_EOF_CH0_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/
+#define DMA_IN_SUC_EOF_CH0_INT_ENA  (BIT(1))
+#define DMA_IN_SUC_EOF_CH0_INT_ENA_M  (BIT(1))
+#define DMA_IN_SUC_EOF_CH0_INT_ENA_V  0x1
+#define DMA_IN_SUC_EOF_CH0_INT_ENA_S  1
+/* DMA_IN_DONE_CH0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/
+#define DMA_IN_DONE_CH0_INT_ENA  (BIT(0))
+#define DMA_IN_DONE_CH0_INT_ENA_M  (BIT(0))
+#define DMA_IN_DONE_CH0_INT_ENA_V  0x1
+#define DMA_IN_DONE_CH0_INT_ENA_S  0
+
+#define DMA_INT_CLR_CH0_REG          (DR_REG_GDMA_BASE + 0x00C)
+/* DMA_OUTFIFO_UDF_CH0_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/
+#define DMA_OUTFIFO_UDF_CH0_INT_CLR  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH0_INT_CLR_M  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH0_INT_CLR_V  0x1
+#define DMA_OUTFIFO_UDF_CH0_INT_CLR_S  12
+/* DMA_OUTFIFO_OVF_CH0_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/
+#define DMA_OUTFIFO_OVF_CH0_INT_CLR  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH0_INT_CLR_M  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH0_INT_CLR_V  0x1
+#define DMA_OUTFIFO_OVF_CH0_INT_CLR_S  11
+/* DMA_INFIFO_UDF_CH0_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/
+#define DMA_INFIFO_UDF_CH0_INT_CLR  (BIT(10))
+#define DMA_INFIFO_UDF_CH0_INT_CLR_M  (BIT(10))
+#define DMA_INFIFO_UDF_CH0_INT_CLR_V  0x1
+#define DMA_INFIFO_UDF_CH0_INT_CLR_S  10
+/* DMA_INFIFO_OVF_CH0_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/
+#define DMA_INFIFO_OVF_CH0_INT_CLR  (BIT(9))
+#define DMA_INFIFO_OVF_CH0_INT_CLR_M  (BIT(9))
+#define DMA_INFIFO_OVF_CH0_INT_CLR_V  0x1
+#define DMA_INFIFO_OVF_CH0_INT_CLR_S  9
+/* DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/
+#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V  0x1
+#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S  8
+/* DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/
+#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V  0x1
+#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S  7
+/* DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/
+#define DMA_OUT_DSCR_ERR_CH0_INT_CLR  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_M  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_V  0x1
+#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_S  6
+/* DMA_IN_DSCR_ERR_CH0_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/
+#define DMA_IN_DSCR_ERR_CH0_INT_CLR  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH0_INT_CLR_M  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH0_INT_CLR_V  0x1
+#define DMA_IN_DSCR_ERR_CH0_INT_CLR_S  5
+/* DMA_OUT_EOF_CH0_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt.*/
+#define DMA_OUT_EOF_CH0_INT_CLR  (BIT(4))
+#define DMA_OUT_EOF_CH0_INT_CLR_M  (BIT(4))
+#define DMA_OUT_EOF_CH0_INT_CLR_V  0x1
+#define DMA_OUT_EOF_CH0_INT_CLR_S  4
+/* DMA_OUT_DONE_CH0_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt.*/
+#define DMA_OUT_DONE_CH0_INT_CLR  (BIT(3))
+#define DMA_OUT_DONE_CH0_INT_CLR_M  (BIT(3))
+#define DMA_OUT_DONE_CH0_INT_CLR_V  0x1
+#define DMA_OUT_DONE_CH0_INT_CLR_S  3
+/* DMA_IN_ERR_EOF_CH0_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/
+#define DMA_IN_ERR_EOF_CH0_INT_CLR  (BIT(2))
+#define DMA_IN_ERR_EOF_CH0_INT_CLR_M  (BIT(2))
+#define DMA_IN_ERR_EOF_CH0_INT_CLR_V  0x1
+#define DMA_IN_ERR_EOF_CH0_INT_CLR_S  2
+/* DMA_IN_SUC_EOF_CH0_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/
+#define DMA_IN_SUC_EOF_CH0_INT_CLR  (BIT(1))
+#define DMA_IN_SUC_EOF_CH0_INT_CLR_M  (BIT(1))
+#define DMA_IN_SUC_EOF_CH0_INT_CLR_V  0x1
+#define DMA_IN_SUC_EOF_CH0_INT_CLR_S  1
+/* DMA_IN_DONE_CH0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear the IN_DONE_CH_INT interrupt.*/
+#define DMA_IN_DONE_CH0_INT_CLR  (BIT(0))
+#define DMA_IN_DONE_CH0_INT_CLR_M  (BIT(0))
+#define DMA_IN_DONE_CH0_INT_CLR_V  0x1
+#define DMA_IN_DONE_CH0_INT_CLR_S  0
+
+#define DMA_INT_RAW_CH1_REG          (DR_REG_GDMA_BASE + 0x010)
+/* DMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
+/*description: This raw interrupt bit turns to high level when level 1 fifo
+ of Tx channel 1 is underflow.*/
+#define DMA_OUTFIFO_UDF_CH1_INT_RAW  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH1_INT_RAW_M  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH1_INT_RAW_V  0x1
+#define DMA_OUTFIFO_UDF_CH1_INT_RAW_S  12
+/* DMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
+/*description: This raw interrupt bit turns to high level when level 1 fifo
+ of Tx channel 1 is overflow.*/
+#define DMA_OUTFIFO_OVF_CH1_INT_RAW  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH1_INT_RAW_M  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH1_INT_RAW_V  0x1
+#define DMA_OUTFIFO_OVF_CH1_INT_RAW_S  11
+/* DMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This raw interrupt bit turns to high level when level 1 fifo
+ of Rx channel 1 is underflow.*/
+#define DMA_INFIFO_UDF_CH1_INT_RAW  (BIT(10))
+#define DMA_INFIFO_UDF_CH1_INT_RAW_M  (BIT(10))
+#define DMA_INFIFO_UDF_CH1_INT_RAW_V  0x1
+#define DMA_INFIFO_UDF_CH1_INT_RAW_S  10
+/* DMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
+/*description: This raw interrupt bit turns to high level when level 1 fifo
+ of Rx channel 1 is overflow.*/
+#define DMA_INFIFO_OVF_CH1_INT_RAW  (BIT(9))
+#define DMA_INFIFO_OVF_CH1_INT_RAW_M  (BIT(9))
+#define DMA_INFIFO_OVF_CH1_INT_RAW_V  0x1
+#define DMA_INFIFO_OVF_CH1_INT_RAW_S  9
+/* DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when data corresponding
+ a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1.*/
+#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V  0x1
+#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S  8
+/* DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when Rx buffer pointed
+ by inlink is full and receiving data is not completed  but there is no more inlink for Rx channel 1.*/
+#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V  0x1
+#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S  7
+/* DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when detecting outlink
+ descriptor error  including owner error  the second and third word error of outlink descriptor for Tx channel 1.*/
+#define DMA_OUT_DSCR_ERR_CH1_INT_RAW  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_M  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_V  0x1
+#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_S  6
+/* DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when detecting inlink
+ descriptor error  including owner error  the second and third word error of inlink descriptor for Rx channel 1.*/
+#define DMA_IN_DSCR_ERR_CH1_INT_RAW  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH1_INT_RAW_M  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH1_INT_RAW_V  0x1
+#define DMA_IN_DSCR_ERR_CH1_INT_RAW_S  5
+/* DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when the last data
+ pointed by one outlink descriptor has been read from memory for Tx channel 1.*/
+#define DMA_OUT_EOF_CH1_INT_RAW  (BIT(4))
+#define DMA_OUT_EOF_CH1_INT_RAW_M  (BIT(4))
+#define DMA_OUT_EOF_CH1_INT_RAW_V  0x1
+#define DMA_OUT_EOF_CH1_INT_RAW_S  4
+/* DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when the last data
+ pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1.*/
+#define DMA_OUT_DONE_CH1_INT_RAW  (BIT(3))
+#define DMA_OUT_DONE_CH1_INT_RAW_M  (BIT(3))
+#define DMA_OUT_DONE_CH1_INT_RAW_V  0x1
+#define DMA_OUT_DONE_CH1_INT_RAW_S  3
+/* DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when data error is
+ detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals  this raw interrupt is reserved.*/
+#define DMA_IN_ERR_EOF_CH1_INT_RAW  (BIT(2))
+#define DMA_IN_ERR_EOF_CH1_INT_RAW_M  (BIT(2))
+#define DMA_IN_ERR_EOF_CH1_INT_RAW_V  0x1
+#define DMA_IN_ERR_EOF_CH1_INT_RAW_S  2
+/* DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when the last data
+ pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0  the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1.*/
+#define DMA_IN_SUC_EOF_CH1_INT_RAW  (BIT(1))
+#define DMA_IN_SUC_EOF_CH1_INT_RAW_M  (BIT(1))
+#define DMA_IN_SUC_EOF_CH1_INT_RAW_V  0x1
+#define DMA_IN_SUC_EOF_CH1_INT_RAW_S  1
+/* DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when the last data
+ pointed by one inlink descriptor has been received for Rx channel 1.*/
+#define DMA_IN_DONE_CH1_INT_RAW  (BIT(0))
+#define DMA_IN_DONE_CH1_INT_RAW_M  (BIT(0))
+#define DMA_IN_DONE_CH1_INT_RAW_V  0x1
+#define DMA_IN_DONE_CH1_INT_RAW_S  0
+
+#define DMA_INT_ST_CH1_REG          (DR_REG_GDMA_BASE + 0x014)
+/* DMA_OUTFIFO_UDF_CH1_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
+#define DMA_OUTFIFO_UDF_CH1_INT_ST  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH1_INT_ST_M  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH1_INT_ST_V  0x1
+#define DMA_OUTFIFO_UDF_CH1_INT_ST_S  12
+/* DMA_OUTFIFO_OVF_CH1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
+#define DMA_OUTFIFO_OVF_CH1_INT_ST  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH1_INT_ST_M  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH1_INT_ST_V  0x1
+#define DMA_OUTFIFO_OVF_CH1_INT_ST_S  11
+/* DMA_INFIFO_UDF_CH1_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
+#define DMA_INFIFO_UDF_CH1_INT_ST  (BIT(10))
+#define DMA_INFIFO_UDF_CH1_INT_ST_M  (BIT(10))
+#define DMA_INFIFO_UDF_CH1_INT_ST_V  0x1
+#define DMA_INFIFO_UDF_CH1_INT_ST_S  10
+/* DMA_INFIFO_OVF_CH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
+#define DMA_INFIFO_OVF_CH1_INT_ST  (BIT(9))
+#define DMA_INFIFO_OVF_CH1_INT_ST_M  (BIT(9))
+#define DMA_INFIFO_OVF_CH1_INT_ST_V  0x1
+#define DMA_INFIFO_OVF_CH1_INT_ST_S  9
+/* DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
+#define DMA_OUT_TOTAL_EOF_CH1_INT_ST  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_M  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_V  0x1
+#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_S  8
+/* DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
+#define DMA_IN_DSCR_EMPTY_CH1_INT_ST  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_M  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_V  0x1
+#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_S  7
+/* DMA_OUT_DSCR_ERR_CH1_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
+#define DMA_OUT_DSCR_ERR_CH1_INT_ST  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH1_INT_ST_M  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH1_INT_ST_V  0x1
+#define DMA_OUT_DSCR_ERR_CH1_INT_ST_S  6
+/* DMA_IN_DSCR_ERR_CH1_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/
+#define DMA_IN_DSCR_ERR_CH1_INT_ST  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH1_INT_ST_M  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH1_INT_ST_V  0x1
+#define DMA_IN_DSCR_ERR_CH1_INT_ST_S  5
+/* DMA_OUT_EOF_CH1_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/
+#define DMA_OUT_EOF_CH1_INT_ST  (BIT(4))
+#define DMA_OUT_EOF_CH1_INT_ST_M  (BIT(4))
+#define DMA_OUT_EOF_CH1_INT_ST_V  0x1
+#define DMA_OUT_EOF_CH1_INT_ST_S  4
+/* DMA_OUT_DONE_CH1_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/
+#define DMA_OUT_DONE_CH1_INT_ST  (BIT(3))
+#define DMA_OUT_DONE_CH1_INT_ST_M  (BIT(3))
+#define DMA_OUT_DONE_CH1_INT_ST_V  0x1
+#define DMA_OUT_DONE_CH1_INT_ST_S  3
+/* DMA_IN_ERR_EOF_CH1_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/
+#define DMA_IN_ERR_EOF_CH1_INT_ST  (BIT(2))
+#define DMA_IN_ERR_EOF_CH1_INT_ST_M  (BIT(2))
+#define DMA_IN_ERR_EOF_CH1_INT_ST_V  0x1
+#define DMA_IN_ERR_EOF_CH1_INT_ST_S  2
+/* DMA_IN_SUC_EOF_CH1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/
+#define DMA_IN_SUC_EOF_CH1_INT_ST  (BIT(1))
+#define DMA_IN_SUC_EOF_CH1_INT_ST_M  (BIT(1))
+#define DMA_IN_SUC_EOF_CH1_INT_ST_V  0x1
+#define DMA_IN_SUC_EOF_CH1_INT_ST_S  1
+/* DMA_IN_DONE_CH1_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/
+#define DMA_IN_DONE_CH1_INT_ST  (BIT(0))
+#define DMA_IN_DONE_CH1_INT_ST_M  (BIT(0))
+#define DMA_IN_DONE_CH1_INT_ST_V  0x1
+#define DMA_IN_DONE_CH1_INT_ST_S  0
+
+#define DMA_INT_ENA_CH1_REG          (DR_REG_GDMA_BASE + 0x018)
+/* DMA_OUTFIFO_UDF_CH1_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
+#define DMA_OUTFIFO_UDF_CH1_INT_ENA  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH1_INT_ENA_M  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH1_INT_ENA_V  0x1
+#define DMA_OUTFIFO_UDF_CH1_INT_ENA_S  12
+/* DMA_OUTFIFO_OVF_CH1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
+#define DMA_OUTFIFO_OVF_CH1_INT_ENA  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH1_INT_ENA_M  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH1_INT_ENA_V  0x1
+#define DMA_OUTFIFO_OVF_CH1_INT_ENA_S  11
+/* DMA_INFIFO_UDF_CH1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
+#define DMA_INFIFO_UDF_CH1_INT_ENA  (BIT(10))
+#define DMA_INFIFO_UDF_CH1_INT_ENA_M  (BIT(10))
+#define DMA_INFIFO_UDF_CH1_INT_ENA_V  0x1
+#define DMA_INFIFO_UDF_CH1_INT_ENA_S  10
+/* DMA_INFIFO_OVF_CH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
+#define DMA_INFIFO_OVF_CH1_INT_ENA  (BIT(9))
+#define DMA_INFIFO_OVF_CH1_INT_ENA_M  (BIT(9))
+#define DMA_INFIFO_OVF_CH1_INT_ENA_V  0x1
+#define DMA_INFIFO_OVF_CH1_INT_ENA_S  9
+/* DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
+#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V  0x1
+#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S  8
+/* DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
+#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V  0x1
+#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S  7
+/* DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
+#define DMA_OUT_DSCR_ERR_CH1_INT_ENA  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_M  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_V  0x1
+#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_S  6
+/* DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/
+#define DMA_IN_DSCR_ERR_CH1_INT_ENA  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH1_INT_ENA_M  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH1_INT_ENA_V  0x1
+#define DMA_IN_DSCR_ERR_CH1_INT_ENA_S  5
+/* DMA_OUT_EOF_CH1_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/
+#define DMA_OUT_EOF_CH1_INT_ENA  (BIT(4))
+#define DMA_OUT_EOF_CH1_INT_ENA_M  (BIT(4))
+#define DMA_OUT_EOF_CH1_INT_ENA_V  0x1
+#define DMA_OUT_EOF_CH1_INT_ENA_S  4
+/* DMA_OUT_DONE_CH1_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/
+#define DMA_OUT_DONE_CH1_INT_ENA  (BIT(3))
+#define DMA_OUT_DONE_CH1_INT_ENA_M  (BIT(3))
+#define DMA_OUT_DONE_CH1_INT_ENA_V  0x1
+#define DMA_OUT_DONE_CH1_INT_ENA_S  3
+/* DMA_IN_ERR_EOF_CH1_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/
+#define DMA_IN_ERR_EOF_CH1_INT_ENA  (BIT(2))
+#define DMA_IN_ERR_EOF_CH1_INT_ENA_M  (BIT(2))
+#define DMA_IN_ERR_EOF_CH1_INT_ENA_V  0x1
+#define DMA_IN_ERR_EOF_CH1_INT_ENA_S  2
+/* DMA_IN_SUC_EOF_CH1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/
+#define DMA_IN_SUC_EOF_CH1_INT_ENA  (BIT(1))
+#define DMA_IN_SUC_EOF_CH1_INT_ENA_M  (BIT(1))
+#define DMA_IN_SUC_EOF_CH1_INT_ENA_V  0x1
+#define DMA_IN_SUC_EOF_CH1_INT_ENA_S  1
+/* DMA_IN_DONE_CH1_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/
+#define DMA_IN_DONE_CH1_INT_ENA  (BIT(0))
+#define DMA_IN_DONE_CH1_INT_ENA_M  (BIT(0))
+#define DMA_IN_DONE_CH1_INT_ENA_V  0x1
+#define DMA_IN_DONE_CH1_INT_ENA_S  0
+
+#define DMA_INT_CLR_CH1_REG          (DR_REG_GDMA_BASE + 0x01C)
+/* DMA_OUTFIFO_UDF_CH1_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/
+#define DMA_OUTFIFO_UDF_CH1_INT_CLR  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH1_INT_CLR_M  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH1_INT_CLR_V  0x1
+#define DMA_OUTFIFO_UDF_CH1_INT_CLR_S  12
+/* DMA_OUTFIFO_OVF_CH1_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/
+#define DMA_OUTFIFO_OVF_CH1_INT_CLR  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH1_INT_CLR_M  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH1_INT_CLR_V  0x1
+#define DMA_OUTFIFO_OVF_CH1_INT_CLR_S  11
+/* DMA_INFIFO_UDF_CH1_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/
+#define DMA_INFIFO_UDF_CH1_INT_CLR  (BIT(10))
+#define DMA_INFIFO_UDF_CH1_INT_CLR_M  (BIT(10))
+#define DMA_INFIFO_UDF_CH1_INT_CLR_V  0x1
+#define DMA_INFIFO_UDF_CH1_INT_CLR_S  10
+/* DMA_INFIFO_OVF_CH1_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/
+#define DMA_INFIFO_OVF_CH1_INT_CLR  (BIT(9))
+#define DMA_INFIFO_OVF_CH1_INT_CLR_M  (BIT(9))
+#define DMA_INFIFO_OVF_CH1_INT_CLR_V  0x1
+#define DMA_INFIFO_OVF_CH1_INT_CLR_S  9
+/* DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/
+#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V  0x1
+#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S  8
+/* DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/
+#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V  0x1
+#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S  7
+/* DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/
+#define DMA_OUT_DSCR_ERR_CH1_INT_CLR  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_M  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_V  0x1
+#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_S  6
+/* DMA_IN_DSCR_ERR_CH1_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/
+#define DMA_IN_DSCR_ERR_CH1_INT_CLR  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH1_INT_CLR_M  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH1_INT_CLR_V  0x1
+#define DMA_IN_DSCR_ERR_CH1_INT_CLR_S  5
+/* DMA_OUT_EOF_CH1_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt.*/
+#define DMA_OUT_EOF_CH1_INT_CLR  (BIT(4))
+#define DMA_OUT_EOF_CH1_INT_CLR_M  (BIT(4))
+#define DMA_OUT_EOF_CH1_INT_CLR_V  0x1
+#define DMA_OUT_EOF_CH1_INT_CLR_S  4
+/* DMA_OUT_DONE_CH1_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt.*/
+#define DMA_OUT_DONE_CH1_INT_CLR  (BIT(3))
+#define DMA_OUT_DONE_CH1_INT_CLR_M  (BIT(3))
+#define DMA_OUT_DONE_CH1_INT_CLR_V  0x1
+#define DMA_OUT_DONE_CH1_INT_CLR_S  3
+/* DMA_IN_ERR_EOF_CH1_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/
+#define DMA_IN_ERR_EOF_CH1_INT_CLR  (BIT(2))
+#define DMA_IN_ERR_EOF_CH1_INT_CLR_M  (BIT(2))
+#define DMA_IN_ERR_EOF_CH1_INT_CLR_V  0x1
+#define DMA_IN_ERR_EOF_CH1_INT_CLR_S  2
+/* DMA_IN_SUC_EOF_CH1_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/
+#define DMA_IN_SUC_EOF_CH1_INT_CLR  (BIT(1))
+#define DMA_IN_SUC_EOF_CH1_INT_CLR_M  (BIT(1))
+#define DMA_IN_SUC_EOF_CH1_INT_CLR_V  0x1
+#define DMA_IN_SUC_EOF_CH1_INT_CLR_S  1
+/* DMA_IN_DONE_CH1_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear the IN_DONE_CH_INT interrupt.*/
+#define DMA_IN_DONE_CH1_INT_CLR  (BIT(0))
+#define DMA_IN_DONE_CH1_INT_CLR_M  (BIT(0))
+#define DMA_IN_DONE_CH1_INT_CLR_V  0x1
+#define DMA_IN_DONE_CH1_INT_CLR_S  0
+
+#define DMA_INT_RAW_CH2_REG          (DR_REG_GDMA_BASE + 0x020)
+/* DMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
+/*description: This raw interrupt bit turns to high level when level 1 fifo
+ of Tx channel 2 is underflow.*/
+#define DMA_OUTFIFO_UDF_CH2_INT_RAW  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH2_INT_RAW_M  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH2_INT_RAW_V  0x1
+#define DMA_OUTFIFO_UDF_CH2_INT_RAW_S  12
+/* DMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
+/*description: This raw interrupt bit turns to high level when level 1 fifo
+ of Tx channel 2 is overflow.*/
+#define DMA_OUTFIFO_OVF_CH2_INT_RAW  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH2_INT_RAW_M  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH2_INT_RAW_V  0x1
+#define DMA_OUTFIFO_OVF_CH2_INT_RAW_S  11
+/* DMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This raw interrupt bit turns to high level when level 1 fifo
+ of Rx channel 2 is underflow.*/
+#define DMA_INFIFO_UDF_CH2_INT_RAW  (BIT(10))
+#define DMA_INFIFO_UDF_CH2_INT_RAW_M  (BIT(10))
+#define DMA_INFIFO_UDF_CH2_INT_RAW_V  0x1
+#define DMA_INFIFO_UDF_CH2_INT_RAW_S  10
+/* DMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
+/*description: This raw interrupt bit turns to high level when level 1 fifo
+ of Rx channel 2 is overflow.*/
+#define DMA_INFIFO_OVF_CH2_INT_RAW  (BIT(9))
+#define DMA_INFIFO_OVF_CH2_INT_RAW_M  (BIT(9))
+#define DMA_INFIFO_OVF_CH2_INT_RAW_V  0x1
+#define DMA_INFIFO_OVF_CH2_INT_RAW_S  9
+/* DMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when data corresponding
+ a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2.*/
+#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V  0x1
+#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S  8
+/* DMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when Rx buffer pointed
+ by inlink is full and receiving data is not completed  but there is no more inlink for Rx channel 2.*/
+#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V  0x1
+#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S  7
+/* DMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when detecting outlink
+ descriptor error  including owner error  the second and third word error of outlink descriptor for Tx channel 2.*/
+#define DMA_OUT_DSCR_ERR_CH2_INT_RAW  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_M  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_V  0x1
+#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_S  6
+/* DMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when detecting inlink
+ descriptor error  including owner error  the second and third word error of inlink descriptor for Rx channel 2.*/
+#define DMA_IN_DSCR_ERR_CH2_INT_RAW  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH2_INT_RAW_M  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH2_INT_RAW_V  0x1
+#define DMA_IN_DSCR_ERR_CH2_INT_RAW_S  5
+/* DMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when the last data
+ pointed by one outlink descriptor has been read from memory for Tx channel 2.*/
+#define DMA_OUT_EOF_CH2_INT_RAW  (BIT(4))
+#define DMA_OUT_EOF_CH2_INT_RAW_M  (BIT(4))
+#define DMA_OUT_EOF_CH2_INT_RAW_V  0x1
+#define DMA_OUT_EOF_CH2_INT_RAW_S  4
+/* DMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when the last data
+ pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2.*/
+#define DMA_OUT_DONE_CH2_INT_RAW  (BIT(3))
+#define DMA_OUT_DONE_CH2_INT_RAW_M  (BIT(3))
+#define DMA_OUT_DONE_CH2_INT_RAW_V  0x1
+#define DMA_OUT_DONE_CH2_INT_RAW_S  3
+/* DMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when data error is
+ detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals  this raw interrupt is reserved.*/
+#define DMA_IN_ERR_EOF_CH2_INT_RAW  (BIT(2))
+#define DMA_IN_ERR_EOF_CH2_INT_RAW_M  (BIT(2))
+#define DMA_IN_ERR_EOF_CH2_INT_RAW_V  0x1
+#define DMA_IN_ERR_EOF_CH2_INT_RAW_S  2
+/* DMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when the last data
+ pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0  the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2.*/
+#define DMA_IN_SUC_EOF_CH2_INT_RAW  (BIT(1))
+#define DMA_IN_SUC_EOF_CH2_INT_RAW_M  (BIT(1))
+#define DMA_IN_SUC_EOF_CH2_INT_RAW_V  0x1
+#define DMA_IN_SUC_EOF_CH2_INT_RAW_S  1
+/* DMA_IN_DONE_CH2_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when the last data
+ pointed by one inlink descriptor has been received for Rx channel 2.*/
+#define DMA_IN_DONE_CH2_INT_RAW  (BIT(0))
+#define DMA_IN_DONE_CH2_INT_RAW_M  (BIT(0))
+#define DMA_IN_DONE_CH2_INT_RAW_V  0x1
+#define DMA_IN_DONE_CH2_INT_RAW_S  0
+
+#define DMA_INT_ST_CH2_REG          (DR_REG_GDMA_BASE + 0x024)
+/* DMA_OUTFIFO_UDF_CH2_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
+#define DMA_OUTFIFO_UDF_CH2_INT_ST  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH2_INT_ST_M  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH2_INT_ST_V  0x1
+#define DMA_OUTFIFO_UDF_CH2_INT_ST_S  12
+/* DMA_OUTFIFO_OVF_CH2_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
+#define DMA_OUTFIFO_OVF_CH2_INT_ST  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH2_INT_ST_M  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH2_INT_ST_V  0x1
+#define DMA_OUTFIFO_OVF_CH2_INT_ST_S  11
+/* DMA_INFIFO_UDF_CH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
+#define DMA_INFIFO_UDF_CH2_INT_ST  (BIT(10))
+#define DMA_INFIFO_UDF_CH2_INT_ST_M  (BIT(10))
+#define DMA_INFIFO_UDF_CH2_INT_ST_V  0x1
+#define DMA_INFIFO_UDF_CH2_INT_ST_S  10
+/* DMA_INFIFO_OVF_CH2_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
+#define DMA_INFIFO_OVF_CH2_INT_ST  (BIT(9))
+#define DMA_INFIFO_OVF_CH2_INT_ST_M  (BIT(9))
+#define DMA_INFIFO_OVF_CH2_INT_ST_V  0x1
+#define DMA_INFIFO_OVF_CH2_INT_ST_S  9
+/* DMA_OUT_TOTAL_EOF_CH2_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
+#define DMA_OUT_TOTAL_EOF_CH2_INT_ST  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_M  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_V  0x1
+#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_S  8
+/* DMA_IN_DSCR_EMPTY_CH2_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
+#define DMA_IN_DSCR_EMPTY_CH2_INT_ST  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_M  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_V  0x1
+#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_S  7
+/* DMA_OUT_DSCR_ERR_CH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
+#define DMA_OUT_DSCR_ERR_CH2_INT_ST  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH2_INT_ST_M  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH2_INT_ST_V  0x1
+#define DMA_OUT_DSCR_ERR_CH2_INT_ST_S  6
+/* DMA_IN_DSCR_ERR_CH2_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/
+#define DMA_IN_DSCR_ERR_CH2_INT_ST  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH2_INT_ST_M  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH2_INT_ST_V  0x1
+#define DMA_IN_DSCR_ERR_CH2_INT_ST_S  5
+/* DMA_OUT_EOF_CH2_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/
+#define DMA_OUT_EOF_CH2_INT_ST  (BIT(4))
+#define DMA_OUT_EOF_CH2_INT_ST_M  (BIT(4))
+#define DMA_OUT_EOF_CH2_INT_ST_V  0x1
+#define DMA_OUT_EOF_CH2_INT_ST_S  4
+/* DMA_OUT_DONE_CH2_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/
+#define DMA_OUT_DONE_CH2_INT_ST  (BIT(3))
+#define DMA_OUT_DONE_CH2_INT_ST_M  (BIT(3))
+#define DMA_OUT_DONE_CH2_INT_ST_V  0x1
+#define DMA_OUT_DONE_CH2_INT_ST_S  3
+/* DMA_IN_ERR_EOF_CH2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/
+#define DMA_IN_ERR_EOF_CH2_INT_ST  (BIT(2))
+#define DMA_IN_ERR_EOF_CH2_INT_ST_M  (BIT(2))
+#define DMA_IN_ERR_EOF_CH2_INT_ST_V  0x1
+#define DMA_IN_ERR_EOF_CH2_INT_ST_S  2
+/* DMA_IN_SUC_EOF_CH2_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/
+#define DMA_IN_SUC_EOF_CH2_INT_ST  (BIT(1))
+#define DMA_IN_SUC_EOF_CH2_INT_ST_M  (BIT(1))
+#define DMA_IN_SUC_EOF_CH2_INT_ST_V  0x1
+#define DMA_IN_SUC_EOF_CH2_INT_ST_S  1
+/* DMA_IN_DONE_CH2_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/
+#define DMA_IN_DONE_CH2_INT_ST  (BIT(0))
+#define DMA_IN_DONE_CH2_INT_ST_M  (BIT(0))
+#define DMA_IN_DONE_CH2_INT_ST_V  0x1
+#define DMA_IN_DONE_CH2_INT_ST_S  0
+
+#define DMA_INT_ENA_CH2_REG          (DR_REG_GDMA_BASE + 0x028)
+/* DMA_OUTFIFO_UDF_CH2_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
+#define DMA_OUTFIFO_UDF_CH2_INT_ENA  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH2_INT_ENA_M  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH2_INT_ENA_V  0x1
+#define DMA_OUTFIFO_UDF_CH2_INT_ENA_S  12
+/* DMA_OUTFIFO_OVF_CH2_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
+#define DMA_OUTFIFO_OVF_CH2_INT_ENA  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH2_INT_ENA_M  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH2_INT_ENA_V  0x1
+#define DMA_OUTFIFO_OVF_CH2_INT_ENA_S  11
+/* DMA_INFIFO_UDF_CH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
+#define DMA_INFIFO_UDF_CH2_INT_ENA  (BIT(10))
+#define DMA_INFIFO_UDF_CH2_INT_ENA_M  (BIT(10))
+#define DMA_INFIFO_UDF_CH2_INT_ENA_V  0x1
+#define DMA_INFIFO_UDF_CH2_INT_ENA_S  10
+/* DMA_INFIFO_OVF_CH2_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
+#define DMA_INFIFO_OVF_CH2_INT_ENA  (BIT(9))
+#define DMA_INFIFO_OVF_CH2_INT_ENA_M  (BIT(9))
+#define DMA_INFIFO_OVF_CH2_INT_ENA_V  0x1
+#define DMA_INFIFO_OVF_CH2_INT_ENA_S  9
+/* DMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
+#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_M  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V  0x1
+#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S  8
+/* DMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
+#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_M  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V  0x1
+#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S  7
+/* DMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
+#define DMA_OUT_DSCR_ERR_CH2_INT_ENA  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_M  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_V  0x1
+#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_S  6
+/* DMA_IN_DSCR_ERR_CH2_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/
+#define DMA_IN_DSCR_ERR_CH2_INT_ENA  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH2_INT_ENA_M  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH2_INT_ENA_V  0x1
+#define DMA_IN_DSCR_ERR_CH2_INT_ENA_S  5
+/* DMA_OUT_EOF_CH2_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/
+#define DMA_OUT_EOF_CH2_INT_ENA  (BIT(4))
+#define DMA_OUT_EOF_CH2_INT_ENA_M  (BIT(4))
+#define DMA_OUT_EOF_CH2_INT_ENA_V  0x1
+#define DMA_OUT_EOF_CH2_INT_ENA_S  4
+/* DMA_OUT_DONE_CH2_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/
+#define DMA_OUT_DONE_CH2_INT_ENA  (BIT(3))
+#define DMA_OUT_DONE_CH2_INT_ENA_M  (BIT(3))
+#define DMA_OUT_DONE_CH2_INT_ENA_V  0x1
+#define DMA_OUT_DONE_CH2_INT_ENA_S  3
+/* DMA_IN_ERR_EOF_CH2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/
+#define DMA_IN_ERR_EOF_CH2_INT_ENA  (BIT(2))
+#define DMA_IN_ERR_EOF_CH2_INT_ENA_M  (BIT(2))
+#define DMA_IN_ERR_EOF_CH2_INT_ENA_V  0x1
+#define DMA_IN_ERR_EOF_CH2_INT_ENA_S  2
+/* DMA_IN_SUC_EOF_CH2_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/
+#define DMA_IN_SUC_EOF_CH2_INT_ENA  (BIT(1))
+#define DMA_IN_SUC_EOF_CH2_INT_ENA_M  (BIT(1))
+#define DMA_IN_SUC_EOF_CH2_INT_ENA_V  0x1
+#define DMA_IN_SUC_EOF_CH2_INT_ENA_S  1
+/* DMA_IN_DONE_CH2_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/
+#define DMA_IN_DONE_CH2_INT_ENA  (BIT(0))
+#define DMA_IN_DONE_CH2_INT_ENA_M  (BIT(0))
+#define DMA_IN_DONE_CH2_INT_ENA_V  0x1
+#define DMA_IN_DONE_CH2_INT_ENA_S  0
+
+#define DMA_INT_CLR_CH2_REG          (DR_REG_GDMA_BASE + 0x02C)
+/* DMA_OUTFIFO_UDF_CH2_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/
+#define DMA_OUTFIFO_UDF_CH2_INT_CLR  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH2_INT_CLR_M  (BIT(12))
+#define DMA_OUTFIFO_UDF_CH2_INT_CLR_V  0x1
+#define DMA_OUTFIFO_UDF_CH2_INT_CLR_S  12
+/* DMA_OUTFIFO_OVF_CH2_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/
+#define DMA_OUTFIFO_OVF_CH2_INT_CLR  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH2_INT_CLR_M  (BIT(11))
+#define DMA_OUTFIFO_OVF_CH2_INT_CLR_V  0x1
+#define DMA_OUTFIFO_OVF_CH2_INT_CLR_S  11
+/* DMA_INFIFO_UDF_CH2_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/
+#define DMA_INFIFO_UDF_CH2_INT_CLR  (BIT(10))
+#define DMA_INFIFO_UDF_CH2_INT_CLR_M  (BIT(10))
+#define DMA_INFIFO_UDF_CH2_INT_CLR_V  0x1
+#define DMA_INFIFO_UDF_CH2_INT_CLR_S  10
+/* DMA_INFIFO_OVF_CH2_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/
+#define DMA_INFIFO_OVF_CH2_INT_CLR  (BIT(9))
+#define DMA_INFIFO_OVF_CH2_INT_CLR_M  (BIT(9))
+#define DMA_INFIFO_OVF_CH2_INT_CLR_V  0x1
+#define DMA_INFIFO_OVF_CH2_INT_CLR_S  9
+/* DMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/
+#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_M  (BIT(8))
+#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V  0x1
+#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S  8
+/* DMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/
+#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_M  (BIT(7))
+#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V  0x1
+#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S  7
+/* DMA_OUT_DSCR_ERR_CH2_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/
+#define DMA_OUT_DSCR_ERR_CH2_INT_CLR  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_M  (BIT(6))
+#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_V  0x1
+#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_S  6
+/* DMA_IN_DSCR_ERR_CH2_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/
+#define DMA_IN_DSCR_ERR_CH2_INT_CLR  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH2_INT_CLR_M  (BIT(5))
+#define DMA_IN_DSCR_ERR_CH2_INT_CLR_V  0x1
+#define DMA_IN_DSCR_ERR_CH2_INT_CLR_S  5
+/* DMA_OUT_EOF_CH2_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt.*/
+#define DMA_OUT_EOF_CH2_INT_CLR  (BIT(4))
+#define DMA_OUT_EOF_CH2_INT_CLR_M  (BIT(4))
+#define DMA_OUT_EOF_CH2_INT_CLR_V  0x1
+#define DMA_OUT_EOF_CH2_INT_CLR_S  4
+/* DMA_OUT_DONE_CH2_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt.*/
+#define DMA_OUT_DONE_CH2_INT_CLR  (BIT(3))
+#define DMA_OUT_DONE_CH2_INT_CLR_M  (BIT(3))
+#define DMA_OUT_DONE_CH2_INT_CLR_V  0x1
+#define DMA_OUT_DONE_CH2_INT_CLR_S  3
+/* DMA_IN_ERR_EOF_CH2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/
+#define DMA_IN_ERR_EOF_CH2_INT_CLR  (BIT(2))
+#define DMA_IN_ERR_EOF_CH2_INT_CLR_M  (BIT(2))
+#define DMA_IN_ERR_EOF_CH2_INT_CLR_V  0x1
+#define DMA_IN_ERR_EOF_CH2_INT_CLR_S  2
+/* DMA_IN_SUC_EOF_CH2_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/
+#define DMA_IN_SUC_EOF_CH2_INT_CLR  (BIT(1))
+#define DMA_IN_SUC_EOF_CH2_INT_CLR_M  (BIT(1))
+#define DMA_IN_SUC_EOF_CH2_INT_CLR_V  0x1
+#define DMA_IN_SUC_EOF_CH2_INT_CLR_S  1
+/* DMA_IN_DONE_CH2_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear the IN_DONE_CH_INT interrupt.*/
+#define DMA_IN_DONE_CH2_INT_CLR  (BIT(0))
+#define DMA_IN_DONE_CH2_INT_CLR_M  (BIT(0))
+#define DMA_IN_DONE_CH2_INT_CLR_V  0x1
+#define DMA_IN_DONE_CH2_INT_CLR_S  0
+
+#define DMA_AHB_TEST_REG          (DR_REG_GDMA_BASE + 0x040)
+/* DMA_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: reserved*/
+#define DMA_AHB_TESTADDR  0x00000003
+#define DMA_AHB_TESTADDR_M  ((DMA_AHB_TESTADDR_V)<<(DMA_AHB_TESTADDR_S))
+#define DMA_AHB_TESTADDR_V  0x3
+#define DMA_AHB_TESTADDR_S  4
+/* DMA_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: reserved*/
+#define DMA_AHB_TESTMODE  0x00000007
+#define DMA_AHB_TESTMODE_M  ((DMA_AHB_TESTMODE_V)<<(DMA_AHB_TESTMODE_S))
+#define DMA_AHB_TESTMODE_V  0x7
+#define DMA_AHB_TESTMODE_S  0
+
+#define DMA_MISC_CONF_REG          (DR_REG_GDMA_BASE + 0x044)
+/* DMA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define DMA_CLK_EN  (BIT(3))
+#define DMA_CLK_EN_M  (BIT(3))
+#define DMA_CLK_EN_V  0x1
+#define DMA_CLK_EN_S  3
+/* DMA_ARB_PRI_DIS : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to disable priority arbitration function.*/
+#define DMA_ARB_PRI_DIS  (BIT(2))
+#define DMA_ARB_PRI_DIS_M  (BIT(2))
+#define DMA_ARB_PRI_DIS_V  0x1
+#define DMA_ARB_PRI_DIS_S  2
+/* DMA_AHBM_RST_INTER : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit  then clear this bit to reset the internal ahb FSM.*/
+#define DMA_AHBM_RST_INTER  (BIT(0))
+#define DMA_AHBM_RST_INTER_M  (BIT(0))
+#define DMA_AHBM_RST_INTER_V  0x1
+#define DMA_AHBM_RST_INTER_S  0
+
+#define DMA_DATE_REG          (DR_REG_GDMA_BASE + 0x048)
+/* DMA_DATE : R/W ;bitpos:[31:0] ;default: 32'h2008250 ; */
+/*description: register version.*/
+#define DMA_DATE  0xFFFFFFFF
+#define DMA_DATE_M  ((DMA_DATE_V)<<(DMA_DATE_S))
+#define DMA_DATE_V  0xFFFFFFFF
+#define DMA_DATE_S  0
+
+#define DMA_IN_CONF0_CH0_REG          (DR_REG_GDMA_BASE + 0x070)
+/* DMA_MEM_TRANS_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit 1 to enable automatic transmitting data from memory
+ to memory via DMA.*/
+#define DMA_MEM_TRANS_EN_CH0  (BIT(4))
+#define DMA_MEM_TRANS_EN_CH0_M  (BIT(4))
+#define DMA_MEM_TRANS_EN_CH0_V  0x1
+#define DMA_MEM_TRANS_EN_CH0_S  4
+/* DMA_IN_DATA_BURST_EN_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel
+ 0 receiving data when accessing internal SRAM.*/
+#define DMA_IN_DATA_BURST_EN_CH0  (BIT(3))
+#define DMA_IN_DATA_BURST_EN_CH0_M  (BIT(3))
+#define DMA_IN_DATA_BURST_EN_CH0_V  0x1
+#define DMA_IN_DATA_BURST_EN_CH0_S  3
+/* DMA_INDSCR_BURST_EN_CH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel
+ 0 reading link descriptor when accessing internal SRAM.*/
+#define DMA_INDSCR_BURST_EN_CH0  (BIT(2))
+#define DMA_INDSCR_BURST_EN_CH0_M  (BIT(2))
+#define DMA_INDSCR_BURST_EN_CH0_V  0x1
+#define DMA_INDSCR_BURST_EN_CH0_S  2
+/* DMA_IN_LOOP_TEST_CH0 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: reserved*/
+#define DMA_IN_LOOP_TEST_CH0  (BIT(1))
+#define DMA_IN_LOOP_TEST_CH0_M  (BIT(1))
+#define DMA_IN_LOOP_TEST_CH0_V  0x1
+#define DMA_IN_LOOP_TEST_CH0_S  1
+/* DMA_IN_RST_CH0 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/
+#define DMA_IN_RST_CH0  (BIT(0))
+#define DMA_IN_RST_CH0_M  (BIT(0))
+#define DMA_IN_RST_CH0_V  0x1
+#define DMA_IN_RST_CH0_S  0
+
+#define DMA_IN_CONF1_CH0_REG          (DR_REG_GDMA_BASE + 0x074)
+/* DMA_IN_CHECK_OWNER_CH0 : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/
+#define DMA_IN_CHECK_OWNER_CH0  (BIT(12))
+#define DMA_IN_CHECK_OWNER_CH0_M  (BIT(12))
+#define DMA_IN_CHECK_OWNER_CH0_V  0x1
+#define DMA_IN_CHECK_OWNER_CH0_S  12
+
+#define DMA_INFIFO_STATUS_CH0_REG          (DR_REG_GDMA_BASE + 0x078)
+/* DMA_IN_BUF_HUNGRY_CH0 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: reserved*/
+#define DMA_IN_BUF_HUNGRY_CH0  (BIT(27))
+#define DMA_IN_BUF_HUNGRY_CH0_M  (BIT(27))
+#define DMA_IN_BUF_HUNGRY_CH0_V  0x1
+#define DMA_IN_BUF_HUNGRY_CH0_S  27
+/* DMA_IN_REMAIN_UNDER_4B_CH0 : RO ;bitpos:[26] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_IN_REMAIN_UNDER_4B_CH0  (BIT(26))
+#define DMA_IN_REMAIN_UNDER_4B_CH0_M  (BIT(26))
+#define DMA_IN_REMAIN_UNDER_4B_CH0_V  0x1
+#define DMA_IN_REMAIN_UNDER_4B_CH0_S  26
+/* DMA_IN_REMAIN_UNDER_3B_CH0 : RO ;bitpos:[25] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_IN_REMAIN_UNDER_3B_CH0  (BIT(25))
+#define DMA_IN_REMAIN_UNDER_3B_CH0_M  (BIT(25))
+#define DMA_IN_REMAIN_UNDER_3B_CH0_V  0x1
+#define DMA_IN_REMAIN_UNDER_3B_CH0_S  25
+/* DMA_IN_REMAIN_UNDER_2B_CH0 : RO ;bitpos:[24] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_IN_REMAIN_UNDER_2B_CH0  (BIT(24))
+#define DMA_IN_REMAIN_UNDER_2B_CH0_M  (BIT(24))
+#define DMA_IN_REMAIN_UNDER_2B_CH0_V  0x1
+#define DMA_IN_REMAIN_UNDER_2B_CH0_S  24
+/* DMA_IN_REMAIN_UNDER_1B_CH0 : RO ;bitpos:[23] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_IN_REMAIN_UNDER_1B_CH0  (BIT(23))
+#define DMA_IN_REMAIN_UNDER_1B_CH0_M  (BIT(23))
+#define DMA_IN_REMAIN_UNDER_1B_CH0_V  0x1
+#define DMA_IN_REMAIN_UNDER_1B_CH0_S  23
+/* DMA_INFIFO_CNT_CH0 : RO ;bitpos:[7:2] ;default: 6'b0 ; */
+/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/
+#define DMA_INFIFO_CNT_CH0  0x0000003F
+#define DMA_INFIFO_CNT_CH0_M  ((DMA_INFIFO_CNT_CH0_V)<<(DMA_INFIFO_CNT_CH0_S))
+#define DMA_INFIFO_CNT_CH0_V  0x3F
+#define DMA_INFIFO_CNT_CH0_S  2
+/* DMA_INFIFO_EMPTY_CH0 : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: L1 Rx FIFO empty signal for Rx channel 0.*/
+#define DMA_INFIFO_EMPTY_CH0  (BIT(1))
+#define DMA_INFIFO_EMPTY_CH0_M  (BIT(1))
+#define DMA_INFIFO_EMPTY_CH0_V  0x1
+#define DMA_INFIFO_EMPTY_CH0_S  1
+/* DMA_INFIFO_FULL_CH0 : RO ;bitpos:[0] ;default: 1'b1 ; */
+/*description: L1 Rx FIFO full signal for Rx channel 0.*/
+#define DMA_INFIFO_FULL_CH0  (BIT(0))
+#define DMA_INFIFO_FULL_CH0_M  (BIT(0))
+#define DMA_INFIFO_FULL_CH0_V  0x1
+#define DMA_INFIFO_FULL_CH0_S  0
+
+#define DMA_IN_POP_CH0_REG          (DR_REG_GDMA_BASE + 0x07C)
+/* DMA_INFIFO_POP_CH0 : R/W/SC ;bitpos:[12] ;default: 1'h0 ; */
+/*description: Set this bit to pop data from DMA FIFO.*/
+#define DMA_INFIFO_POP_CH0  (BIT(12))
+#define DMA_INFIFO_POP_CH0_M  (BIT(12))
+#define DMA_INFIFO_POP_CH0_V  0x1
+#define DMA_INFIFO_POP_CH0_S  12
+/* DMA_INFIFO_RDATA_CH0 : RO ;bitpos:[11:0] ;default: 12'h800 ; */
+/*description: This register stores the data popping from DMA FIFO.*/
+#define DMA_INFIFO_RDATA_CH0  0x00000FFF
+#define DMA_INFIFO_RDATA_CH0_M  ((DMA_INFIFO_RDATA_CH0_V)<<(DMA_INFIFO_RDATA_CH0_S))
+#define DMA_INFIFO_RDATA_CH0_V  0xFFF
+#define DMA_INFIFO_RDATA_CH0_S  0
+
+#define DMA_IN_LINK_CH0_REG          (DR_REG_GDMA_BASE + 0x080)
+/* DMA_INLINK_PARK_CH0 : RO ;bitpos:[24] ;default: 1'h1 ; */
+/*description: 1: the inlink descriptor's FSM is in idle state.  0: the inlink
+ descriptor's FSM is working.*/
+#define DMA_INLINK_PARK_CH0  (BIT(24))
+#define DMA_INLINK_PARK_CH0_M  (BIT(24))
+#define DMA_INLINK_PARK_CH0_V  0x1
+#define DMA_INLINK_PARK_CH0_S  24
+/* DMA_INLINK_RESTART_CH0 : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Set this bit to mount a new inlink descriptor.*/
+#define DMA_INLINK_RESTART_CH0  (BIT(23))
+#define DMA_INLINK_RESTART_CH0_M  (BIT(23))
+#define DMA_INLINK_RESTART_CH0_V  0x1
+#define DMA_INLINK_RESTART_CH0_S  23
+/* DMA_INLINK_START_CH0 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Set this bit to start dealing with the inlink descriptors.*/
+#define DMA_INLINK_START_CH0  (BIT(22))
+#define DMA_INLINK_START_CH0_M  (BIT(22))
+#define DMA_INLINK_START_CH0_V  0x1
+#define DMA_INLINK_START_CH0_S  22
+/* DMA_INLINK_STOP_CH0 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Set this bit to stop dealing with the inlink descriptors.*/
+#define DMA_INLINK_STOP_CH0  (BIT(21))
+#define DMA_INLINK_STOP_CH0_M  (BIT(21))
+#define DMA_INLINK_STOP_CH0_V  0x1
+#define DMA_INLINK_STOP_CH0_S  21
+/* DMA_INLINK_AUTO_RET_CH0 : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: Set this bit to return to current inlink descriptor's address
+  when there are some errors in current receiving data.*/
+#define DMA_INLINK_AUTO_RET_CH0  (BIT(20))
+#define DMA_INLINK_AUTO_RET_CH0_M  (BIT(20))
+#define DMA_INLINK_AUTO_RET_CH0_V  0x1
+#define DMA_INLINK_AUTO_RET_CH0_S  20
+/* DMA_INLINK_ADDR_CH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: This register stores the 20 least significant bits of the first
+ inlink descriptor's address.*/
+#define DMA_INLINK_ADDR_CH0  0x000FFFFF
+#define DMA_INLINK_ADDR_CH0_M  ((DMA_INLINK_ADDR_CH0_V)<<(DMA_INLINK_ADDR_CH0_S))
+#define DMA_INLINK_ADDR_CH0_V  0xFFFFF
+#define DMA_INLINK_ADDR_CH0_S  0
+
+#define DMA_IN_STATE_CH0_REG          (DR_REG_GDMA_BASE + 0x084)
+/* DMA_IN_STATE_CH0 : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: reserved*/
+#define DMA_IN_STATE_CH0  0x00000007
+#define DMA_IN_STATE_CH0_M  ((DMA_IN_STATE_CH0_V)<<(DMA_IN_STATE_CH0_S))
+#define DMA_IN_STATE_CH0_V  0x7
+#define DMA_IN_STATE_CH0_S  20
+/* DMA_IN_DSCR_STATE_CH0 : RO ;bitpos:[19:18] ;default: 2'b0 ; */
+/*description: reserved*/
+#define DMA_IN_DSCR_STATE_CH0  0x00000003
+#define DMA_IN_DSCR_STATE_CH0_M  ((DMA_IN_DSCR_STATE_CH0_V)<<(DMA_IN_DSCR_STATE_CH0_S))
+#define DMA_IN_DSCR_STATE_CH0_V  0x3
+#define DMA_IN_DSCR_STATE_CH0_S  18
+/* DMA_INLINK_DSCR_ADDR_CH0 : RO ;bitpos:[17:0] ;default: 18'b0 ; */
+/*description: This register stores the current inlink descriptor's address.*/
+#define DMA_INLINK_DSCR_ADDR_CH0  0x0003FFFF
+#define DMA_INLINK_DSCR_ADDR_CH0_M  ((DMA_INLINK_DSCR_ADDR_CH0_V)<<(DMA_INLINK_DSCR_ADDR_CH0_S))
+#define DMA_INLINK_DSCR_ADDR_CH0_V  0x3FFFF
+#define DMA_INLINK_DSCR_ADDR_CH0_S  0
+
+#define DMA_IN_SUC_EOF_DES_ADDR_CH0_REG          (DR_REG_GDMA_BASE + 0x088)
+/* DMA_IN_SUC_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the address of the inlink descriptor when
+ the EOF bit in this descriptor is 1.*/
+#define DMA_IN_SUC_EOF_DES_ADDR_CH0  0xFFFFFFFF
+#define DMA_IN_SUC_EOF_DES_ADDR_CH0_M  ((DMA_IN_SUC_EOF_DES_ADDR_CH0_V)<<(DMA_IN_SUC_EOF_DES_ADDR_CH0_S))
+#define DMA_IN_SUC_EOF_DES_ADDR_CH0_V  0xFFFFFFFF
+#define DMA_IN_SUC_EOF_DES_ADDR_CH0_S  0
+
+#define DMA_IN_ERR_EOF_DES_ADDR_CH0_REG          (DR_REG_GDMA_BASE + 0x08C)
+/* DMA_IN_ERR_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the address of the inlink descriptor when
+ there are some errors in current receiving data. Only used when peripheral is UHCI0.*/
+#define DMA_IN_ERR_EOF_DES_ADDR_CH0  0xFFFFFFFF
+#define DMA_IN_ERR_EOF_DES_ADDR_CH0_M  ((DMA_IN_ERR_EOF_DES_ADDR_CH0_V)<<(DMA_IN_ERR_EOF_DES_ADDR_CH0_S))
+#define DMA_IN_ERR_EOF_DES_ADDR_CH0_V  0xFFFFFFFF
+#define DMA_IN_ERR_EOF_DES_ADDR_CH0_S  0
+
+#define DMA_IN_DSCR_CH0_REG          (DR_REG_GDMA_BASE + 0x090)
+/* DMA_INLINK_DSCR_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of the current inlink descriptor x.*/
+#define DMA_INLINK_DSCR_CH0  0xFFFFFFFF
+#define DMA_INLINK_DSCR_CH0_M  ((DMA_INLINK_DSCR_CH0_V)<<(DMA_INLINK_DSCR_CH0_S))
+#define DMA_INLINK_DSCR_CH0_V  0xFFFFFFFF
+#define DMA_INLINK_DSCR_CH0_S  0
+
+#define DMA_IN_DSCR_BF0_CH0_REG          (DR_REG_GDMA_BASE + 0x094)
+/* DMA_INLINK_DSCR_BF0_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of the last inlink descriptor x-1.*/
+#define DMA_INLINK_DSCR_BF0_CH0  0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF0_CH0_M  ((DMA_INLINK_DSCR_BF0_CH0_V)<<(DMA_INLINK_DSCR_BF0_CH0_S))
+#define DMA_INLINK_DSCR_BF0_CH0_V  0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF0_CH0_S  0
+
+#define DMA_IN_DSCR_BF1_CH0_REG          (DR_REG_GDMA_BASE + 0x098)
+/* DMA_INLINK_DSCR_BF1_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of the second-to-last inlink descriptor x-2.*/
+#define DMA_INLINK_DSCR_BF1_CH0  0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF1_CH0_M  ((DMA_INLINK_DSCR_BF1_CH0_V)<<(DMA_INLINK_DSCR_BF1_CH0_S))
+#define DMA_INLINK_DSCR_BF1_CH0_V  0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF1_CH0_S  0
+
+#define DMA_IN_PRI_CH0_REG          (DR_REG_GDMA_BASE + 0x09C)
+/* DMA_RX_PRI_CH0 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: The priority of Rx channel 0. The larger of the value  the higher
+ of the priority.*/
+#define DMA_RX_PRI_CH0  0x0000000F
+#define DMA_RX_PRI_CH0_M  ((DMA_RX_PRI_CH0_V)<<(DMA_RX_PRI_CH0_S))
+#define DMA_RX_PRI_CH0_V  0xF
+#define DMA_RX_PRI_CH0_S  0
+
+#define DMA_IN_PERI_SEL_CH0_REG          (DR_REG_GDMA_BASE + 0x0A0)
+/* DMA_PERI_IN_SEL_CH0 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */
+/*description: This register is used to select peripheral for Rx channel 0.
+ 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/
+#define DMA_PERI_IN_SEL_CH0  0x0000003F
+#define DMA_PERI_IN_SEL_CH0_M  ((DMA_PERI_IN_SEL_CH0_V)<<(DMA_PERI_IN_SEL_CH0_S))
+#define DMA_PERI_IN_SEL_CH0_V  0x3F
+#define DMA_PERI_IN_SEL_CH0_S  0
+
+#define DMA_OUT_CONF0_CH0_REG          (DR_REG_GDMA_BASE + 0x0D0)
+/* DMA_OUT_DATA_BURST_EN_CH0 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel
+ 0 transmitting data when accessing internal SRAM.*/
+#define DMA_OUT_DATA_BURST_EN_CH0  (BIT(5))
+#define DMA_OUT_DATA_BURST_EN_CH0_M  (BIT(5))
+#define DMA_OUT_DATA_BURST_EN_CH0_V  0x1
+#define DMA_OUT_DATA_BURST_EN_CH0_S  5
+/* DMA_OUTDSCR_BURST_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel
+ 0 reading link descriptor when accessing internal SRAM.*/
+#define DMA_OUTDSCR_BURST_EN_CH0  (BIT(4))
+#define DMA_OUTDSCR_BURST_EN_CH0_M  (BIT(4))
+#define DMA_OUTDSCR_BURST_EN_CH0_V  0x1
+#define DMA_OUTDSCR_BURST_EN_CH0_S  4
+/* DMA_OUT_EOF_MODE_CH0 : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: EOF flag generation mode when transmitting data. 1: EOF flag
+ for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/
+#define DMA_OUT_EOF_MODE_CH0  (BIT(3))
+#define DMA_OUT_EOF_MODE_CH0_M  (BIT(3))
+#define DMA_OUT_EOF_MODE_CH0_V  0x1
+#define DMA_OUT_EOF_MODE_CH0_S  3
+/* DMA_OUT_AUTO_WRBACK_CH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to enable automatic outlink-writeback when all the
+ data in tx buffer has been transmitted.*/
+#define DMA_OUT_AUTO_WRBACK_CH0  (BIT(2))
+#define DMA_OUT_AUTO_WRBACK_CH0_M  (BIT(2))
+#define DMA_OUT_AUTO_WRBACK_CH0_V  0x1
+#define DMA_OUT_AUTO_WRBACK_CH0_S  2
+/* DMA_OUT_LOOP_TEST_CH0 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: reserved*/
+#define DMA_OUT_LOOP_TEST_CH0  (BIT(1))
+#define DMA_OUT_LOOP_TEST_CH0_M  (BIT(1))
+#define DMA_OUT_LOOP_TEST_CH0_V  0x1
+#define DMA_OUT_LOOP_TEST_CH0_S  1
+/* DMA_OUT_RST_CH0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/
+#define DMA_OUT_RST_CH0  (BIT(0))
+#define DMA_OUT_RST_CH0_M  (BIT(0))
+#define DMA_OUT_RST_CH0_V  0x1
+#define DMA_OUT_RST_CH0_S  0
+
+#define DMA_OUT_CONF1_CH0_REG          (DR_REG_GDMA_BASE + 0x0D4)
+/* DMA_OUT_CHECK_OWNER_CH0 : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/
+#define DMA_OUT_CHECK_OWNER_CH0  (BIT(12))
+#define DMA_OUT_CHECK_OWNER_CH0_M  (BIT(12))
+#define DMA_OUT_CHECK_OWNER_CH0_V  0x1
+#define DMA_OUT_CHECK_OWNER_CH0_S  12
+
+#define DMA_OUTFIFO_STATUS_CH0_REG          (DR_REG_GDMA_BASE + 0x0D8)
+/* DMA_OUT_REMAIN_UNDER_4B_CH0 : RO ;bitpos:[26] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_OUT_REMAIN_UNDER_4B_CH0  (BIT(26))
+#define DMA_OUT_REMAIN_UNDER_4B_CH0_M  (BIT(26))
+#define DMA_OUT_REMAIN_UNDER_4B_CH0_V  0x1
+#define DMA_OUT_REMAIN_UNDER_4B_CH0_S  26
+/* DMA_OUT_REMAIN_UNDER_3B_CH0 : RO ;bitpos:[25] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_OUT_REMAIN_UNDER_3B_CH0  (BIT(25))
+#define DMA_OUT_REMAIN_UNDER_3B_CH0_M  (BIT(25))
+#define DMA_OUT_REMAIN_UNDER_3B_CH0_V  0x1
+#define DMA_OUT_REMAIN_UNDER_3B_CH0_S  25
+/* DMA_OUT_REMAIN_UNDER_2B_CH0 : RO ;bitpos:[24] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_OUT_REMAIN_UNDER_2B_CH0  (BIT(24))
+#define DMA_OUT_REMAIN_UNDER_2B_CH0_M  (BIT(24))
+#define DMA_OUT_REMAIN_UNDER_2B_CH0_V  0x1
+#define DMA_OUT_REMAIN_UNDER_2B_CH0_S  24
+/* DMA_OUT_REMAIN_UNDER_1B_CH0 : RO ;bitpos:[23] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_OUT_REMAIN_UNDER_1B_CH0  (BIT(23))
+#define DMA_OUT_REMAIN_UNDER_1B_CH0_M  (BIT(23))
+#define DMA_OUT_REMAIN_UNDER_1B_CH0_V  0x1
+#define DMA_OUT_REMAIN_UNDER_1B_CH0_S  23
+/* DMA_OUTFIFO_CNT_CH0 : RO ;bitpos:[7:2] ;default: 6'b0 ; */
+/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/
+#define DMA_OUTFIFO_CNT_CH0  0x0000003F
+#define DMA_OUTFIFO_CNT_CH0_M  ((DMA_OUTFIFO_CNT_CH0_V)<<(DMA_OUTFIFO_CNT_CH0_S))
+#define DMA_OUTFIFO_CNT_CH0_V  0x3F
+#define DMA_OUTFIFO_CNT_CH0_S  2
+/* DMA_OUTFIFO_EMPTY_CH0 : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: L1 Tx FIFO empty signal for Tx channel 0.*/
+#define DMA_OUTFIFO_EMPTY_CH0  (BIT(1))
+#define DMA_OUTFIFO_EMPTY_CH0_M  (BIT(1))
+#define DMA_OUTFIFO_EMPTY_CH0_V  0x1
+#define DMA_OUTFIFO_EMPTY_CH0_S  1
+/* DMA_OUTFIFO_FULL_CH0 : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: L1 Tx FIFO full signal for Tx channel 0.*/
+#define DMA_OUTFIFO_FULL_CH0  (BIT(0))
+#define DMA_OUTFIFO_FULL_CH0_M  (BIT(0))
+#define DMA_OUTFIFO_FULL_CH0_V  0x1
+#define DMA_OUTFIFO_FULL_CH0_S  0
+
+#define DMA_OUT_PUSH_CH0_REG          (DR_REG_GDMA_BASE + 0x0DC)
+/* DMA_OUTFIFO_PUSH_CH0 : R/W/SC ;bitpos:[9] ;default: 1'h0 ; */
+/*description: Set this bit to push data into DMA FIFO.*/
+#define DMA_OUTFIFO_PUSH_CH0  (BIT(9))
+#define DMA_OUTFIFO_PUSH_CH0_M  (BIT(9))
+#define DMA_OUTFIFO_PUSH_CH0_V  0x1
+#define DMA_OUTFIFO_PUSH_CH0_S  9
+/* DMA_OUTFIFO_WDATA_CH0 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: This register stores the data that need to be pushed into DMA FIFO.*/
+#define DMA_OUTFIFO_WDATA_CH0  0x000001FF
+#define DMA_OUTFIFO_WDATA_CH0_M  ((DMA_OUTFIFO_WDATA_CH0_V)<<(DMA_OUTFIFO_WDATA_CH0_S))
+#define DMA_OUTFIFO_WDATA_CH0_V  0x1FF
+#define DMA_OUTFIFO_WDATA_CH0_S  0
+
+#define DMA_OUT_LINK_CH0_REG          (DR_REG_GDMA_BASE + 0x0E0)
+/* DMA_OUTLINK_PARK_CH0 : RO ;bitpos:[23] ;default: 1'h1 ; */
+/*description: 1: the outlink descriptor's FSM is in idle state.  0: the outlink
+ descriptor's FSM is working.*/
+#define DMA_OUTLINK_PARK_CH0  (BIT(23))
+#define DMA_OUTLINK_PARK_CH0_M  (BIT(23))
+#define DMA_OUTLINK_PARK_CH0_V  0x1
+#define DMA_OUTLINK_PARK_CH0_S  23
+/* DMA_OUTLINK_RESTART_CH0 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Set this bit to restart a new outlink from the last address.*/
+#define DMA_OUTLINK_RESTART_CH0  (BIT(22))
+#define DMA_OUTLINK_RESTART_CH0_M  (BIT(22))
+#define DMA_OUTLINK_RESTART_CH0_V  0x1
+#define DMA_OUTLINK_RESTART_CH0_S  22
+/* DMA_OUTLINK_START_CH0 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Set this bit to start dealing with the outlink descriptors.*/
+#define DMA_OUTLINK_START_CH0  (BIT(21))
+#define DMA_OUTLINK_START_CH0_M  (BIT(21))
+#define DMA_OUTLINK_START_CH0_V  0x1
+#define DMA_OUTLINK_START_CH0_S  21
+/* DMA_OUTLINK_STOP_CH0 : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Set this bit to stop dealing with the outlink descriptors.*/
+#define DMA_OUTLINK_STOP_CH0  (BIT(20))
+#define DMA_OUTLINK_STOP_CH0_M  (BIT(20))
+#define DMA_OUTLINK_STOP_CH0_V  0x1
+#define DMA_OUTLINK_STOP_CH0_S  20
+/* DMA_OUTLINK_ADDR_CH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: This register stores the 20 least significant bits of the first
+ outlink descriptor's address.*/
+#define DMA_OUTLINK_ADDR_CH0  0x000FFFFF
+#define DMA_OUTLINK_ADDR_CH0_M  ((DMA_OUTLINK_ADDR_CH0_V)<<(DMA_OUTLINK_ADDR_CH0_S))
+#define DMA_OUTLINK_ADDR_CH0_V  0xFFFFF
+#define DMA_OUTLINK_ADDR_CH0_S  0
+
+#define DMA_OUT_STATE_CH0_REG          (DR_REG_GDMA_BASE + 0x0E4)
+/* DMA_OUT_STATE_CH0 : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: reserved*/
+#define DMA_OUT_STATE_CH0  0x00000007
+#define DMA_OUT_STATE_CH0_M  ((DMA_OUT_STATE_CH0_V)<<(DMA_OUT_STATE_CH0_S))
+#define DMA_OUT_STATE_CH0_V  0x7
+#define DMA_OUT_STATE_CH0_S  20
+/* DMA_OUT_DSCR_STATE_CH0 : RO ;bitpos:[19:18] ;default: 2'b0 ; */
+/*description: reserved*/
+#define DMA_OUT_DSCR_STATE_CH0  0x00000003
+#define DMA_OUT_DSCR_STATE_CH0_M  ((DMA_OUT_DSCR_STATE_CH0_V)<<(DMA_OUT_DSCR_STATE_CH0_S))
+#define DMA_OUT_DSCR_STATE_CH0_V  0x3
+#define DMA_OUT_DSCR_STATE_CH0_S  18
+/* DMA_OUTLINK_DSCR_ADDR_CH0 : RO ;bitpos:[17:0] ;default: 18'b0 ; */
+/*description: This register stores the current outlink descriptor's address.*/
+#define DMA_OUTLINK_DSCR_ADDR_CH0  0x0003FFFF
+#define DMA_OUTLINK_DSCR_ADDR_CH0_M  ((DMA_OUTLINK_DSCR_ADDR_CH0_V)<<(DMA_OUTLINK_DSCR_ADDR_CH0_S))
+#define DMA_OUTLINK_DSCR_ADDR_CH0_V  0x3FFFF
+#define DMA_OUTLINK_DSCR_ADDR_CH0_S  0
+
+#define DMA_OUT_EOF_DES_ADDR_CH0_REG          (DR_REG_GDMA_BASE + 0x0E8)
+/* DMA_OUT_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the address of the outlink descriptor when
+ the EOF bit in this descriptor is 1.*/
+#define DMA_OUT_EOF_DES_ADDR_CH0  0xFFFFFFFF
+#define DMA_OUT_EOF_DES_ADDR_CH0_M  ((DMA_OUT_EOF_DES_ADDR_CH0_V)<<(DMA_OUT_EOF_DES_ADDR_CH0_S))
+#define DMA_OUT_EOF_DES_ADDR_CH0_V  0xFFFFFFFF
+#define DMA_OUT_EOF_DES_ADDR_CH0_S  0
+
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG          (DR_REG_GDMA_BASE + 0x0EC)
+/* DMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the address of the outlink descriptor before
+ the last outlink descriptor.*/
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH0  0xFFFFFFFF
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_M  ((DMA_OUT_EOF_BFR_DES_ADDR_CH0_V)<<(DMA_OUT_EOF_BFR_DES_ADDR_CH0_S))
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_V  0xFFFFFFFF
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_S  0
+
+#define DMA_OUT_DSCR_CH0_REG          (DR_REG_GDMA_BASE + 0x0F0)
+/* DMA_OUTLINK_DSCR_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of the current outlink descriptor y.*/
+#define DMA_OUTLINK_DSCR_CH0  0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_CH0_M  ((DMA_OUTLINK_DSCR_CH0_V)<<(DMA_OUTLINK_DSCR_CH0_S))
+#define DMA_OUTLINK_DSCR_CH0_V  0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_CH0_S  0
+
+#define DMA_OUT_DSCR_BF0_CH0_REG          (DR_REG_GDMA_BASE + 0x0F4)
+/* DMA_OUTLINK_DSCR_BF0_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of the last outlink descriptor y-1.*/
+#define DMA_OUTLINK_DSCR_BF0_CH0  0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF0_CH0_M  ((DMA_OUTLINK_DSCR_BF0_CH0_V)<<(DMA_OUTLINK_DSCR_BF0_CH0_S))
+#define DMA_OUTLINK_DSCR_BF0_CH0_V  0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF0_CH0_S  0
+
+#define DMA_OUT_DSCR_BF1_CH0_REG          (DR_REG_GDMA_BASE + 0x0F8)
+/* DMA_OUTLINK_DSCR_BF1_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of the second-to-last inlink descriptor x-2.*/
+#define DMA_OUTLINK_DSCR_BF1_CH0  0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF1_CH0_M  ((DMA_OUTLINK_DSCR_BF1_CH0_V)<<(DMA_OUTLINK_DSCR_BF1_CH0_S))
+#define DMA_OUTLINK_DSCR_BF1_CH0_V  0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF1_CH0_S  0
+
+#define DMA_OUT_PRI_CH0_REG          (DR_REG_GDMA_BASE + 0x0FC)
+/* DMA_TX_PRI_CH0 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: The priority of Tx channel 0. The larger of the value  the higher
+ of the priority.*/
+#define DMA_TX_PRI_CH0  0x0000000F
+#define DMA_TX_PRI_CH0_M  ((DMA_TX_PRI_CH0_V)<<(DMA_TX_PRI_CH0_S))
+#define DMA_TX_PRI_CH0_V  0xF
+#define DMA_TX_PRI_CH0_S  0
+
+#define DMA_OUT_PERI_SEL_CH0_REG          (DR_REG_GDMA_BASE + 0x100)
+/* DMA_PERI_OUT_SEL_CH0 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */
+/*description: This register is used to select peripheral for Tx channel 0.
+ 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/
+#define DMA_PERI_OUT_SEL_CH0  0x0000003F
+#define DMA_PERI_OUT_SEL_CH0_M  ((DMA_PERI_OUT_SEL_CH0_V)<<(DMA_PERI_OUT_SEL_CH0_S))
+#define DMA_PERI_OUT_SEL_CH0_V  0x3F
+#define DMA_PERI_OUT_SEL_CH0_S  0
+
+#define DMA_IN_CONF0_CH1_REG          (DR_REG_GDMA_BASE + 0x130)
+/* DMA_MEM_TRANS_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit 1 to enable automatic transmitting data from memory
+ to memory via DMA.*/
+#define DMA_MEM_TRANS_EN_CH1  (BIT(4))
+#define DMA_MEM_TRANS_EN_CH1_M  (BIT(4))
+#define DMA_MEM_TRANS_EN_CH1_V  0x1
+#define DMA_MEM_TRANS_EN_CH1_S  4
+/* DMA_IN_DATA_BURST_EN_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel
+ 1 receiving data when accessing internal SRAM.*/
+#define DMA_IN_DATA_BURST_EN_CH1  (BIT(3))
+#define DMA_IN_DATA_BURST_EN_CH1_M  (BIT(3))
+#define DMA_IN_DATA_BURST_EN_CH1_V  0x1
+#define DMA_IN_DATA_BURST_EN_CH1_S  3
+/* DMA_INDSCR_BURST_EN_CH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel
+ 1 reading link descriptor when accessing internal SRAM.*/
+#define DMA_INDSCR_BURST_EN_CH1  (BIT(2))
+#define DMA_INDSCR_BURST_EN_CH1_M  (BIT(2))
+#define DMA_INDSCR_BURST_EN_CH1_V  0x1
+#define DMA_INDSCR_BURST_EN_CH1_S  2
+/* DMA_IN_LOOP_TEST_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: reserved*/
+#define DMA_IN_LOOP_TEST_CH1  (BIT(1))
+#define DMA_IN_LOOP_TEST_CH1_M  (BIT(1))
+#define DMA_IN_LOOP_TEST_CH1_V  0x1
+#define DMA_IN_LOOP_TEST_CH1_S  1
+/* DMA_IN_RST_CH1 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.*/
+#define DMA_IN_RST_CH1  (BIT(0))
+#define DMA_IN_RST_CH1_M  (BIT(0))
+#define DMA_IN_RST_CH1_V  0x1
+#define DMA_IN_RST_CH1_S  0
+
+#define DMA_IN_CONF1_CH1_REG          (DR_REG_GDMA_BASE + 0x134)
+/* DMA_IN_CHECK_OWNER_CH1 : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/
+#define DMA_IN_CHECK_OWNER_CH1  (BIT(12))
+#define DMA_IN_CHECK_OWNER_CH1_M  (BIT(12))
+#define DMA_IN_CHECK_OWNER_CH1_V  0x1
+#define DMA_IN_CHECK_OWNER_CH1_S  12
+
+#define DMA_INFIFO_STATUS_CH1_REG          (DR_REG_GDMA_BASE + 0x138)
+/* DMA_IN_BUF_HUNGRY_CH1 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: reserved*/
+#define DMA_IN_BUF_HUNGRY_CH1  (BIT(27))
+#define DMA_IN_BUF_HUNGRY_CH1_M  (BIT(27))
+#define DMA_IN_BUF_HUNGRY_CH1_V  0x1
+#define DMA_IN_BUF_HUNGRY_CH1_S  27
+/* DMA_IN_REMAIN_UNDER_4B_CH1 : RO ;bitpos:[26] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_IN_REMAIN_UNDER_4B_CH1  (BIT(26))
+#define DMA_IN_REMAIN_UNDER_4B_CH1_M  (BIT(26))
+#define DMA_IN_REMAIN_UNDER_4B_CH1_V  0x1
+#define DMA_IN_REMAIN_UNDER_4B_CH1_S  26
+/* DMA_IN_REMAIN_UNDER_3B_CH1 : RO ;bitpos:[25] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_IN_REMAIN_UNDER_3B_CH1  (BIT(25))
+#define DMA_IN_REMAIN_UNDER_3B_CH1_M  (BIT(25))
+#define DMA_IN_REMAIN_UNDER_3B_CH1_V  0x1
+#define DMA_IN_REMAIN_UNDER_3B_CH1_S  25
+/* DMA_IN_REMAIN_UNDER_2B_CH1 : RO ;bitpos:[24] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_IN_REMAIN_UNDER_2B_CH1  (BIT(24))
+#define DMA_IN_REMAIN_UNDER_2B_CH1_M  (BIT(24))
+#define DMA_IN_REMAIN_UNDER_2B_CH1_V  0x1
+#define DMA_IN_REMAIN_UNDER_2B_CH1_S  24
+/* DMA_IN_REMAIN_UNDER_1B_CH1 : RO ;bitpos:[23] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_IN_REMAIN_UNDER_1B_CH1  (BIT(23))
+#define DMA_IN_REMAIN_UNDER_1B_CH1_M  (BIT(23))
+#define DMA_IN_REMAIN_UNDER_1B_CH1_V  0x1
+#define DMA_IN_REMAIN_UNDER_1B_CH1_S  23
+/* DMA_INFIFO_CNT_CH1 : RO ;bitpos:[7:2] ;default: 6'b0 ; */
+/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.*/
+#define DMA_INFIFO_CNT_CH1  0x0000003F
+#define DMA_INFIFO_CNT_CH1_M  ((DMA_INFIFO_CNT_CH1_V)<<(DMA_INFIFO_CNT_CH1_S))
+#define DMA_INFIFO_CNT_CH1_V  0x3F
+#define DMA_INFIFO_CNT_CH1_S  2
+/* DMA_INFIFO_EMPTY_CH1 : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: L1 Rx FIFO empty signal for Rx channel 1.*/
+#define DMA_INFIFO_EMPTY_CH1  (BIT(1))
+#define DMA_INFIFO_EMPTY_CH1_M  (BIT(1))
+#define DMA_INFIFO_EMPTY_CH1_V  0x1
+#define DMA_INFIFO_EMPTY_CH1_S  1
+/* DMA_INFIFO_FULL_CH1 : RO ;bitpos:[0] ;default: 1'b1 ; */
+/*description: L1 Rx FIFO full signal for Rx channel 1.*/
+#define DMA_INFIFO_FULL_CH1  (BIT(0))
+#define DMA_INFIFO_FULL_CH1_M  (BIT(0))
+#define DMA_INFIFO_FULL_CH1_V  0x1
+#define DMA_INFIFO_FULL_CH1_S  0
+
+#define DMA_IN_POP_CH1_REG          (DR_REG_GDMA_BASE + 0x13C)
+/* DMA_INFIFO_POP_CH1 : R/W/SC ;bitpos:[12] ;default: 1'h0 ; */
+/*description: Set this bit to pop data from DMA FIFO.*/
+#define DMA_INFIFO_POP_CH1  (BIT(12))
+#define DMA_INFIFO_POP_CH1_M  (BIT(12))
+#define DMA_INFIFO_POP_CH1_V  0x1
+#define DMA_INFIFO_POP_CH1_S  12
+/* DMA_INFIFO_RDATA_CH1 : RO ;bitpos:[11:0] ;default: 12'h800 ; */
+/*description: This register stores the data popping from DMA FIFO.*/
+#define DMA_INFIFO_RDATA_CH1  0x00000FFF
+#define DMA_INFIFO_RDATA_CH1_M  ((DMA_INFIFO_RDATA_CH1_V)<<(DMA_INFIFO_RDATA_CH1_S))
+#define DMA_INFIFO_RDATA_CH1_V  0xFFF
+#define DMA_INFIFO_RDATA_CH1_S  0
+
+#define DMA_IN_LINK_CH1_REG          (DR_REG_GDMA_BASE + 0x140)
+/* DMA_INLINK_PARK_CH1 : RO ;bitpos:[24] ;default: 1'h1 ; */
+/*description: 1: the inlink descriptor's FSM is in idle state.  0: the inlink
+ descriptor's FSM is working.*/
+#define DMA_INLINK_PARK_CH1  (BIT(24))
+#define DMA_INLINK_PARK_CH1_M  (BIT(24))
+#define DMA_INLINK_PARK_CH1_V  0x1
+#define DMA_INLINK_PARK_CH1_S  24
+/* DMA_INLINK_RESTART_CH1 : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Set this bit to mount a new inlink descriptor.*/
+#define DMA_INLINK_RESTART_CH1  (BIT(23))
+#define DMA_INLINK_RESTART_CH1_M  (BIT(23))
+#define DMA_INLINK_RESTART_CH1_V  0x1
+#define DMA_INLINK_RESTART_CH1_S  23
+/* DMA_INLINK_START_CH1 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Set this bit to start dealing with the inlink descriptors.*/
+#define DMA_INLINK_START_CH1  (BIT(22))
+#define DMA_INLINK_START_CH1_M  (BIT(22))
+#define DMA_INLINK_START_CH1_V  0x1
+#define DMA_INLINK_START_CH1_S  22
+/* DMA_INLINK_STOP_CH1 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Set this bit to stop dealing with the inlink descriptors.*/
+#define DMA_INLINK_STOP_CH1  (BIT(21))
+#define DMA_INLINK_STOP_CH1_M  (BIT(21))
+#define DMA_INLINK_STOP_CH1_V  0x1
+#define DMA_INLINK_STOP_CH1_S  21
+/* DMA_INLINK_AUTO_RET_CH1 : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: Set this bit to return to current inlink descriptor's address
+  when there are some errors in current receiving data.*/
+#define DMA_INLINK_AUTO_RET_CH1  (BIT(20))
+#define DMA_INLINK_AUTO_RET_CH1_M  (BIT(20))
+#define DMA_INLINK_AUTO_RET_CH1_V  0x1
+#define DMA_INLINK_AUTO_RET_CH1_S  20
+/* DMA_INLINK_ADDR_CH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: This register stores the 20 least significant bits of the first
+ inlink descriptor's address.*/
+#define DMA_INLINK_ADDR_CH1  0x000FFFFF
+#define DMA_INLINK_ADDR_CH1_M  ((DMA_INLINK_ADDR_CH1_V)<<(DMA_INLINK_ADDR_CH1_S))
+#define DMA_INLINK_ADDR_CH1_V  0xFFFFF
+#define DMA_INLINK_ADDR_CH1_S  0
+
+#define DMA_IN_STATE_CH1_REG          (DR_REG_GDMA_BASE + 0x144)
+/* DMA_IN_STATE_CH1 : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: reserved*/
+#define DMA_IN_STATE_CH1  0x00000007
+#define DMA_IN_STATE_CH1_M  ((DMA_IN_STATE_CH1_V)<<(DMA_IN_STATE_CH1_S))
+#define DMA_IN_STATE_CH1_V  0x7
+#define DMA_IN_STATE_CH1_S  20
+/* DMA_IN_DSCR_STATE_CH1 : RO ;bitpos:[19:18] ;default: 2'b0 ; */
+/*description: reserved*/
+#define DMA_IN_DSCR_STATE_CH1  0x00000003
+#define DMA_IN_DSCR_STATE_CH1_M  ((DMA_IN_DSCR_STATE_CH1_V)<<(DMA_IN_DSCR_STATE_CH1_S))
+#define DMA_IN_DSCR_STATE_CH1_V  0x3
+#define DMA_IN_DSCR_STATE_CH1_S  18
+/* DMA_INLINK_DSCR_ADDR_CH1 : RO ;bitpos:[17:0] ;default: 18'b0 ; */
+/*description: This register stores the current inlink descriptor's address.*/
+#define DMA_INLINK_DSCR_ADDR_CH1  0x0003FFFF
+#define DMA_INLINK_DSCR_ADDR_CH1_M  ((DMA_INLINK_DSCR_ADDR_CH1_V)<<(DMA_INLINK_DSCR_ADDR_CH1_S))
+#define DMA_INLINK_DSCR_ADDR_CH1_V  0x3FFFF
+#define DMA_INLINK_DSCR_ADDR_CH1_S  0
+
+#define DMA_IN_SUC_EOF_DES_ADDR_CH1_REG          (DR_REG_GDMA_BASE + 0x148)
+/* DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the address of the inlink descriptor when
+ the EOF bit in this descriptor is 1.*/
+#define DMA_IN_SUC_EOF_DES_ADDR_CH1  0xFFFFFFFF
+#define DMA_IN_SUC_EOF_DES_ADDR_CH1_M  ((DMA_IN_SUC_EOF_DES_ADDR_CH1_V)<<(DMA_IN_SUC_EOF_DES_ADDR_CH1_S))
+#define DMA_IN_SUC_EOF_DES_ADDR_CH1_V  0xFFFFFFFF
+#define DMA_IN_SUC_EOF_DES_ADDR_CH1_S  0
+
+#define DMA_IN_ERR_EOF_DES_ADDR_CH1_REG          (DR_REG_GDMA_BASE + 0x14C)
+/* DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the address of the inlink descriptor when
+ there are some errors in current receiving data. Only used when peripheral is UHCI0.*/
+#define DMA_IN_ERR_EOF_DES_ADDR_CH1  0xFFFFFFFF
+#define DMA_IN_ERR_EOF_DES_ADDR_CH1_M  ((DMA_IN_ERR_EOF_DES_ADDR_CH1_V)<<(DMA_IN_ERR_EOF_DES_ADDR_CH1_S))
+#define DMA_IN_ERR_EOF_DES_ADDR_CH1_V  0xFFFFFFFF
+#define DMA_IN_ERR_EOF_DES_ADDR_CH1_S  0
+
+#define DMA_IN_DSCR_CH1_REG          (DR_REG_GDMA_BASE + 0x150)
+/* DMA_INLINK_DSCR_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of the current inlink descriptor x.*/
+#define DMA_INLINK_DSCR_CH1  0xFFFFFFFF
+#define DMA_INLINK_DSCR_CH1_M  ((DMA_INLINK_DSCR_CH1_V)<<(DMA_INLINK_DSCR_CH1_S))
+#define DMA_INLINK_DSCR_CH1_V  0xFFFFFFFF
+#define DMA_INLINK_DSCR_CH1_S  0
+
+#define DMA_IN_DSCR_BF0_CH1_REG          (DR_REG_GDMA_BASE + 0x154)
+/* DMA_INLINK_DSCR_BF0_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of the last inlink descriptor x-1.*/
+#define DMA_INLINK_DSCR_BF0_CH1  0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF0_CH1_M  ((DMA_INLINK_DSCR_BF0_CH1_V)<<(DMA_INLINK_DSCR_BF0_CH1_S))
+#define DMA_INLINK_DSCR_BF0_CH1_V  0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF0_CH1_S  0
+
+#define DMA_IN_DSCR_BF1_CH1_REG          (DR_REG_GDMA_BASE + 0x158)
+/* DMA_INLINK_DSCR_BF1_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of the second-to-last inlink descriptor x-2.*/
+#define DMA_INLINK_DSCR_BF1_CH1  0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF1_CH1_M  ((DMA_INLINK_DSCR_BF1_CH1_V)<<(DMA_INLINK_DSCR_BF1_CH1_S))
+#define DMA_INLINK_DSCR_BF1_CH1_V  0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF1_CH1_S  0
+
+#define DMA_IN_PRI_CH1_REG          (DR_REG_GDMA_BASE + 0x15C)
+/* DMA_RX_PRI_CH1 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: The priority of Rx channel 1. The larger of the value  the higher
+ of the priority.*/
+#define DMA_RX_PRI_CH1  0x0000000F
+#define DMA_RX_PRI_CH1_M  ((DMA_RX_PRI_CH1_V)<<(DMA_RX_PRI_CH1_S))
+#define DMA_RX_PRI_CH1_V  0xF
+#define DMA_RX_PRI_CH1_S  0
+
+#define DMA_IN_PERI_SEL_CH1_REG          (DR_REG_GDMA_BASE + 0x160)
+/* DMA_PERI_IN_SEL_CH1 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */
+/*description: This register is used to select peripheral for Rx channel 1.
+ 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/
+#define DMA_PERI_IN_SEL_CH1  0x0000003F
+#define DMA_PERI_IN_SEL_CH1_M  ((DMA_PERI_IN_SEL_CH1_V)<<(DMA_PERI_IN_SEL_CH1_S))
+#define DMA_PERI_IN_SEL_CH1_V  0x3F
+#define DMA_PERI_IN_SEL_CH1_S  0
+
+#define DMA_OUT_CONF0_CH1_REG          (DR_REG_GDMA_BASE + 0x190)
+/* DMA_OUT_DATA_BURST_EN_CH1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel
+ 1 transmitting data when accessing internal SRAM.*/
+#define DMA_OUT_DATA_BURST_EN_CH1  (BIT(5))
+#define DMA_OUT_DATA_BURST_EN_CH1_M  (BIT(5))
+#define DMA_OUT_DATA_BURST_EN_CH1_V  0x1
+#define DMA_OUT_DATA_BURST_EN_CH1_S  5
+/* DMA_OUTDSCR_BURST_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel
+ 1 reading link descriptor when accessing internal SRAM.*/
+#define DMA_OUTDSCR_BURST_EN_CH1  (BIT(4))
+#define DMA_OUTDSCR_BURST_EN_CH1_M  (BIT(4))
+#define DMA_OUTDSCR_BURST_EN_CH1_V  0x1
+#define DMA_OUTDSCR_BURST_EN_CH1_S  4
+/* DMA_OUT_EOF_MODE_CH1 : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: EOF flag generation mode when transmitting data. 1: EOF flag
+ for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA*/
+#define DMA_OUT_EOF_MODE_CH1  (BIT(3))
+#define DMA_OUT_EOF_MODE_CH1_M  (BIT(3))
+#define DMA_OUT_EOF_MODE_CH1_V  0x1
+#define DMA_OUT_EOF_MODE_CH1_S  3
+/* DMA_OUT_AUTO_WRBACK_CH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to enable automatic outlink-writeback when all the
+ data in tx buffer has been transmitted.*/
+#define DMA_OUT_AUTO_WRBACK_CH1  (BIT(2))
+#define DMA_OUT_AUTO_WRBACK_CH1_M  (BIT(2))
+#define DMA_OUT_AUTO_WRBACK_CH1_V  0x1
+#define DMA_OUT_AUTO_WRBACK_CH1_S  2
+/* DMA_OUT_LOOP_TEST_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: reserved*/
+#define DMA_OUT_LOOP_TEST_CH1  (BIT(1))
+#define DMA_OUT_LOOP_TEST_CH1_M  (BIT(1))
+#define DMA_OUT_LOOP_TEST_CH1_V  0x1
+#define DMA_OUT_LOOP_TEST_CH1_S  1
+/* DMA_OUT_RST_CH1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.*/
+#define DMA_OUT_RST_CH1  (BIT(0))
+#define DMA_OUT_RST_CH1_M  (BIT(0))
+#define DMA_OUT_RST_CH1_V  0x1
+#define DMA_OUT_RST_CH1_S  0
+
+#define DMA_OUT_CONF1_CH1_REG          (DR_REG_GDMA_BASE + 0x194)
+/* DMA_OUT_CHECK_OWNER_CH1 : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/
+#define DMA_OUT_CHECK_OWNER_CH1  (BIT(12))
+#define DMA_OUT_CHECK_OWNER_CH1_M  (BIT(12))
+#define DMA_OUT_CHECK_OWNER_CH1_V  0x1
+#define DMA_OUT_CHECK_OWNER_CH1_S  12
+
+#define DMA_OUTFIFO_STATUS_CH1_REG          (DR_REG_GDMA_BASE + 0x198)
+/* DMA_OUT_REMAIN_UNDER_4B_CH1 : RO ;bitpos:[26] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_OUT_REMAIN_UNDER_4B_CH1  (BIT(26))
+#define DMA_OUT_REMAIN_UNDER_4B_CH1_M  (BIT(26))
+#define DMA_OUT_REMAIN_UNDER_4B_CH1_V  0x1
+#define DMA_OUT_REMAIN_UNDER_4B_CH1_S  26
+/* DMA_OUT_REMAIN_UNDER_3B_CH1 : RO ;bitpos:[25] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_OUT_REMAIN_UNDER_3B_CH1  (BIT(25))
+#define DMA_OUT_REMAIN_UNDER_3B_CH1_M  (BIT(25))
+#define DMA_OUT_REMAIN_UNDER_3B_CH1_V  0x1
+#define DMA_OUT_REMAIN_UNDER_3B_CH1_S  25
+/* DMA_OUT_REMAIN_UNDER_2B_CH1 : RO ;bitpos:[24] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_OUT_REMAIN_UNDER_2B_CH1  (BIT(24))
+#define DMA_OUT_REMAIN_UNDER_2B_CH1_M  (BIT(24))
+#define DMA_OUT_REMAIN_UNDER_2B_CH1_V  0x1
+#define DMA_OUT_REMAIN_UNDER_2B_CH1_S  24
+/* DMA_OUT_REMAIN_UNDER_1B_CH1 : RO ;bitpos:[23] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_OUT_REMAIN_UNDER_1B_CH1  (BIT(23))
+#define DMA_OUT_REMAIN_UNDER_1B_CH1_M  (BIT(23))
+#define DMA_OUT_REMAIN_UNDER_1B_CH1_V  0x1
+#define DMA_OUT_REMAIN_UNDER_1B_CH1_S  23
+/* DMA_OUTFIFO_CNT_CH1 : RO ;bitpos:[7:2] ;default: 6'b0 ; */
+/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.*/
+#define DMA_OUTFIFO_CNT_CH1  0x0000003F
+#define DMA_OUTFIFO_CNT_CH1_M  ((DMA_OUTFIFO_CNT_CH1_V)<<(DMA_OUTFIFO_CNT_CH1_S))
+#define DMA_OUTFIFO_CNT_CH1_V  0x3F
+#define DMA_OUTFIFO_CNT_CH1_S  2
+/* DMA_OUTFIFO_EMPTY_CH1 : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: L1 Tx FIFO empty signal for Tx channel 1.*/
+#define DMA_OUTFIFO_EMPTY_CH1  (BIT(1))
+#define DMA_OUTFIFO_EMPTY_CH1_M  (BIT(1))
+#define DMA_OUTFIFO_EMPTY_CH1_V  0x1
+#define DMA_OUTFIFO_EMPTY_CH1_S  1
+/* DMA_OUTFIFO_FULL_CH1 : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: L1 Tx FIFO full signal for Tx channel 1.*/
+#define DMA_OUTFIFO_FULL_CH1  (BIT(0))
+#define DMA_OUTFIFO_FULL_CH1_M  (BIT(0))
+#define DMA_OUTFIFO_FULL_CH1_V  0x1
+#define DMA_OUTFIFO_FULL_CH1_S  0
+
+#define DMA_OUT_PUSH_CH1_REG          (DR_REG_GDMA_BASE + 0x19C)
+/* DMA_OUTFIFO_PUSH_CH1 : R/W/SC ;bitpos:[9] ;default: 1'h0 ; */
+/*description: Set this bit to push data into DMA FIFO.*/
+#define DMA_OUTFIFO_PUSH_CH1  (BIT(9))
+#define DMA_OUTFIFO_PUSH_CH1_M  (BIT(9))
+#define DMA_OUTFIFO_PUSH_CH1_V  0x1
+#define DMA_OUTFIFO_PUSH_CH1_S  9
+/* DMA_OUTFIFO_WDATA_CH1 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: This register stores the data that need to be pushed into DMA FIFO.*/
+#define DMA_OUTFIFO_WDATA_CH1  0x000001FF
+#define DMA_OUTFIFO_WDATA_CH1_M  ((DMA_OUTFIFO_WDATA_CH1_V)<<(DMA_OUTFIFO_WDATA_CH1_S))
+#define DMA_OUTFIFO_WDATA_CH1_V  0x1FF
+#define DMA_OUTFIFO_WDATA_CH1_S  0
+
+#define DMA_OUT_LINK_CH1_REG          (DR_REG_GDMA_BASE + 0x1A0)
+/* DMA_OUTLINK_PARK_CH1 : RO ;bitpos:[23] ;default: 1'h1 ; */
+/*description: 1: the outlink descriptor's FSM is in idle state.  0: the outlink
+ descriptor's FSM is working.*/
+#define DMA_OUTLINK_PARK_CH1  (BIT(23))
+#define DMA_OUTLINK_PARK_CH1_M  (BIT(23))
+#define DMA_OUTLINK_PARK_CH1_V  0x1
+#define DMA_OUTLINK_PARK_CH1_S  23
+/* DMA_OUTLINK_RESTART_CH1 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Set this bit to restart a new outlink from the last address.*/
+#define DMA_OUTLINK_RESTART_CH1  (BIT(22))
+#define DMA_OUTLINK_RESTART_CH1_M  (BIT(22))
+#define DMA_OUTLINK_RESTART_CH1_V  0x1
+#define DMA_OUTLINK_RESTART_CH1_S  22
+/* DMA_OUTLINK_START_CH1 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Set this bit to start dealing with the outlink descriptors.*/
+#define DMA_OUTLINK_START_CH1  (BIT(21))
+#define DMA_OUTLINK_START_CH1_M  (BIT(21))
+#define DMA_OUTLINK_START_CH1_V  0x1
+#define DMA_OUTLINK_START_CH1_S  21
+/* DMA_OUTLINK_STOP_CH1 : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Set this bit to stop dealing with the outlink descriptors.*/
+#define DMA_OUTLINK_STOP_CH1  (BIT(20))
+#define DMA_OUTLINK_STOP_CH1_M  (BIT(20))
+#define DMA_OUTLINK_STOP_CH1_V  0x1
+#define DMA_OUTLINK_STOP_CH1_S  20
+/* DMA_OUTLINK_ADDR_CH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: This register stores the 20 least significant bits of the first
+ outlink descriptor's address.*/
+#define DMA_OUTLINK_ADDR_CH1  0x000FFFFF
+#define DMA_OUTLINK_ADDR_CH1_M  ((DMA_OUTLINK_ADDR_CH1_V)<<(DMA_OUTLINK_ADDR_CH1_S))
+#define DMA_OUTLINK_ADDR_CH1_V  0xFFFFF
+#define DMA_OUTLINK_ADDR_CH1_S  0
+
+#define DMA_OUT_STATE_CH1_REG          (DR_REG_GDMA_BASE + 0x1A4)
+/* DMA_OUT_STATE_CH1 : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: reserved*/
+#define DMA_OUT_STATE_CH1  0x00000007
+#define DMA_OUT_STATE_CH1_M  ((DMA_OUT_STATE_CH1_V)<<(DMA_OUT_STATE_CH1_S))
+#define DMA_OUT_STATE_CH1_V  0x7
+#define DMA_OUT_STATE_CH1_S  20
+/* DMA_OUT_DSCR_STATE_CH1 : RO ;bitpos:[19:18] ;default: 2'b0 ; */
+/*description: reserved*/
+#define DMA_OUT_DSCR_STATE_CH1  0x00000003
+#define DMA_OUT_DSCR_STATE_CH1_M  ((DMA_OUT_DSCR_STATE_CH1_V)<<(DMA_OUT_DSCR_STATE_CH1_S))
+#define DMA_OUT_DSCR_STATE_CH1_V  0x3
+#define DMA_OUT_DSCR_STATE_CH1_S  18
+/* DMA_OUTLINK_DSCR_ADDR_CH1 : RO ;bitpos:[17:0] ;default: 18'b0 ; */
+/*description: This register stores the current outlink descriptor's address.*/
+#define DMA_OUTLINK_DSCR_ADDR_CH1  0x0003FFFF
+#define DMA_OUTLINK_DSCR_ADDR_CH1_M  ((DMA_OUTLINK_DSCR_ADDR_CH1_V)<<(DMA_OUTLINK_DSCR_ADDR_CH1_S))
+#define DMA_OUTLINK_DSCR_ADDR_CH1_V  0x3FFFF
+#define DMA_OUTLINK_DSCR_ADDR_CH1_S  0
+
+#define DMA_OUT_EOF_DES_ADDR_CH1_REG          (DR_REG_GDMA_BASE + 0x1A8)
+/* DMA_OUT_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the address of the outlink descriptor when
+ the EOF bit in this descriptor is 1.*/
+#define DMA_OUT_EOF_DES_ADDR_CH1  0xFFFFFFFF
+#define DMA_OUT_EOF_DES_ADDR_CH1_M  ((DMA_OUT_EOF_DES_ADDR_CH1_V)<<(DMA_OUT_EOF_DES_ADDR_CH1_S))
+#define DMA_OUT_EOF_DES_ADDR_CH1_V  0xFFFFFFFF
+#define DMA_OUT_EOF_DES_ADDR_CH1_S  0
+
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG          (DR_REG_GDMA_BASE + 0x1AC)
+/* DMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the address of the outlink descriptor before
+ the last outlink descriptor.*/
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH1  0xFFFFFFFF
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_M  ((DMA_OUT_EOF_BFR_DES_ADDR_CH1_V)<<(DMA_OUT_EOF_BFR_DES_ADDR_CH1_S))
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_V  0xFFFFFFFF
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_S  0
+
+#define DMA_OUT_DSCR_CH1_REG          (DR_REG_GDMA_BASE + 0x1B0)
+/* DMA_OUTLINK_DSCR_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of the current outlink descriptor y.*/
+#define DMA_OUTLINK_DSCR_CH1  0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_CH1_M  ((DMA_OUTLINK_DSCR_CH1_V)<<(DMA_OUTLINK_DSCR_CH1_S))
+#define DMA_OUTLINK_DSCR_CH1_V  0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_CH1_S  0
+
+#define DMA_OUT_DSCR_BF0_CH1_REG          (DR_REG_GDMA_BASE + 0x1B4)
+/* DMA_OUTLINK_DSCR_BF0_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of the last outlink descriptor y-1.*/
+#define DMA_OUTLINK_DSCR_BF0_CH1  0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF0_CH1_M  ((DMA_OUTLINK_DSCR_BF0_CH1_V)<<(DMA_OUTLINK_DSCR_BF0_CH1_S))
+#define DMA_OUTLINK_DSCR_BF0_CH1_V  0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF0_CH1_S  0
+
+#define DMA_OUT_DSCR_BF1_CH1_REG          (DR_REG_GDMA_BASE + 0x1B8)
+/* DMA_OUTLINK_DSCR_BF1_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of the second-to-last inlink descriptor x-2.*/
+#define DMA_OUTLINK_DSCR_BF1_CH1  0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF1_CH1_M  ((DMA_OUTLINK_DSCR_BF1_CH1_V)<<(DMA_OUTLINK_DSCR_BF1_CH1_S))
+#define DMA_OUTLINK_DSCR_BF1_CH1_V  0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF1_CH1_S  0
+
+#define DMA_OUT_PRI_CH1_REG          (DR_REG_GDMA_BASE + 0x1BC)
+/* DMA_TX_PRI_CH1 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: The priority of Tx channel 1. The larger of the value  the higher
+ of the priority.*/
+#define DMA_TX_PRI_CH1  0x0000000F
+#define DMA_TX_PRI_CH1_M  ((DMA_TX_PRI_CH1_V)<<(DMA_TX_PRI_CH1_S))
+#define DMA_TX_PRI_CH1_V  0xF
+#define DMA_TX_PRI_CH1_S  0
+
+#define DMA_OUT_PERI_SEL_CH1_REG          (DR_REG_GDMA_BASE + 0x1C0)
+/* DMA_PERI_OUT_SEL_CH1 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */
+/*description: This register is used to select peripheral for Tx channel 1.
+ 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/
+#define DMA_PERI_OUT_SEL_CH1  0x0000003F
+#define DMA_PERI_OUT_SEL_CH1_M  ((DMA_PERI_OUT_SEL_CH1_V)<<(DMA_PERI_OUT_SEL_CH1_S))
+#define DMA_PERI_OUT_SEL_CH1_V  0x3F
+#define DMA_PERI_OUT_SEL_CH1_S  0
+
+#define DMA_IN_CONF0_CH2_REG          (DR_REG_GDMA_BASE + 0x1F0)
+/* DMA_MEM_TRANS_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit 1 to enable automatic transmitting data from memory
+ to memory via DMA.*/
+#define DMA_MEM_TRANS_EN_CH2  (BIT(4))
+#define DMA_MEM_TRANS_EN_CH2_M  (BIT(4))
+#define DMA_MEM_TRANS_EN_CH2_V  0x1
+#define DMA_MEM_TRANS_EN_CH2_S  4
+/* DMA_IN_DATA_BURST_EN_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel
+ 2 receiving data when accessing internal SRAM.*/
+#define DMA_IN_DATA_BURST_EN_CH2  (BIT(3))
+#define DMA_IN_DATA_BURST_EN_CH2_M  (BIT(3))
+#define DMA_IN_DATA_BURST_EN_CH2_V  0x1
+#define DMA_IN_DATA_BURST_EN_CH2_S  3
+/* DMA_INDSCR_BURST_EN_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel
+ 2 reading link descriptor when accessing internal SRAM.*/
+#define DMA_INDSCR_BURST_EN_CH2  (BIT(2))
+#define DMA_INDSCR_BURST_EN_CH2_M  (BIT(2))
+#define DMA_INDSCR_BURST_EN_CH2_V  0x1
+#define DMA_INDSCR_BURST_EN_CH2_S  2
+/* DMA_IN_LOOP_TEST_CH2 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: reserved*/
+#define DMA_IN_LOOP_TEST_CH2  (BIT(1))
+#define DMA_IN_LOOP_TEST_CH2_M  (BIT(1))
+#define DMA_IN_LOOP_TEST_CH2_V  0x1
+#define DMA_IN_LOOP_TEST_CH2_S  1
+/* DMA_IN_RST_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.*/
+#define DMA_IN_RST_CH2  (BIT(0))
+#define DMA_IN_RST_CH2_M  (BIT(0))
+#define DMA_IN_RST_CH2_V  0x1
+#define DMA_IN_RST_CH2_S  0
+
+#define DMA_IN_CONF1_CH2_REG          (DR_REG_GDMA_BASE + 0x1F4)
+/* DMA_IN_CHECK_OWNER_CH2 : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/
+#define DMA_IN_CHECK_OWNER_CH2  (BIT(12))
+#define DMA_IN_CHECK_OWNER_CH2_M  (BIT(12))
+#define DMA_IN_CHECK_OWNER_CH2_V  0x1
+#define DMA_IN_CHECK_OWNER_CH2_S  12
+
+#define DMA_INFIFO_STATUS_CH2_REG          (DR_REG_GDMA_BASE + 0x1F8)
+/* DMA_IN_BUF_HUNGRY_CH2 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: reserved*/
+#define DMA_IN_BUF_HUNGRY_CH2  (BIT(27))
+#define DMA_IN_BUF_HUNGRY_CH2_M  (BIT(27))
+#define DMA_IN_BUF_HUNGRY_CH2_V  0x1
+#define DMA_IN_BUF_HUNGRY_CH2_S  27
+/* DMA_IN_REMAIN_UNDER_4B_CH2 : RO ;bitpos:[26] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_IN_REMAIN_UNDER_4B_CH2  (BIT(26))
+#define DMA_IN_REMAIN_UNDER_4B_CH2_M  (BIT(26))
+#define DMA_IN_REMAIN_UNDER_4B_CH2_V  0x1
+#define DMA_IN_REMAIN_UNDER_4B_CH2_S  26
+/* DMA_IN_REMAIN_UNDER_3B_CH2 : RO ;bitpos:[25] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_IN_REMAIN_UNDER_3B_CH2  (BIT(25))
+#define DMA_IN_REMAIN_UNDER_3B_CH2_M  (BIT(25))
+#define DMA_IN_REMAIN_UNDER_3B_CH2_V  0x1
+#define DMA_IN_REMAIN_UNDER_3B_CH2_S  25
+/* DMA_IN_REMAIN_UNDER_2B_CH2 : RO ;bitpos:[24] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_IN_REMAIN_UNDER_2B_CH2  (BIT(24))
+#define DMA_IN_REMAIN_UNDER_2B_CH2_M  (BIT(24))
+#define DMA_IN_REMAIN_UNDER_2B_CH2_V  0x1
+#define DMA_IN_REMAIN_UNDER_2B_CH2_S  24
+/* DMA_IN_REMAIN_UNDER_1B_CH2 : RO ;bitpos:[23] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_IN_REMAIN_UNDER_1B_CH2  (BIT(23))
+#define DMA_IN_REMAIN_UNDER_1B_CH2_M  (BIT(23))
+#define DMA_IN_REMAIN_UNDER_1B_CH2_V  0x1
+#define DMA_IN_REMAIN_UNDER_1B_CH2_S  23
+/* DMA_INFIFO_CNT_CH2 : RO ;bitpos:[7:2] ;default: 6'b0 ; */
+/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.*/
+#define DMA_INFIFO_CNT_CH2  0x0000003F
+#define DMA_INFIFO_CNT_CH2_M  ((DMA_INFIFO_CNT_CH2_V)<<(DMA_INFIFO_CNT_CH2_S))
+#define DMA_INFIFO_CNT_CH2_V  0x3F
+#define DMA_INFIFO_CNT_CH2_S  2
+/* DMA_INFIFO_EMPTY_CH2 : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: L1 Rx FIFO empty signal for Rx channel 2.*/
+#define DMA_INFIFO_EMPTY_CH2  (BIT(1))
+#define DMA_INFIFO_EMPTY_CH2_M  (BIT(1))
+#define DMA_INFIFO_EMPTY_CH2_V  0x1
+#define DMA_INFIFO_EMPTY_CH2_S  1
+/* DMA_INFIFO_FULL_CH2 : RO ;bitpos:[0] ;default: 1'b1 ; */
+/*description: L1 Rx FIFO full signal for Rx channel 2.*/
+#define DMA_INFIFO_FULL_CH2  (BIT(0))
+#define DMA_INFIFO_FULL_CH2_M  (BIT(0))
+#define DMA_INFIFO_FULL_CH2_V  0x1
+#define DMA_INFIFO_FULL_CH2_S  0
+
+#define DMA_IN_POP_CH2_REG          (DR_REG_GDMA_BASE + 0x1FC)
+/* DMA_INFIFO_POP_CH2 : R/W/SC ;bitpos:[12] ;default: 1'h0 ; */
+/*description: Set this bit to pop data from DMA FIFO.*/
+#define DMA_INFIFO_POP_CH2  (BIT(12))
+#define DMA_INFIFO_POP_CH2_M  (BIT(12))
+#define DMA_INFIFO_POP_CH2_V  0x1
+#define DMA_INFIFO_POP_CH2_S  12
+/* DMA_INFIFO_RDATA_CH2 : RO ;bitpos:[11:0] ;default: 12'h800 ; */
+/*description: This register stores the data popping from DMA FIFO.*/
+#define DMA_INFIFO_RDATA_CH2  0x00000FFF
+#define DMA_INFIFO_RDATA_CH2_M  ((DMA_INFIFO_RDATA_CH2_V)<<(DMA_INFIFO_RDATA_CH2_S))
+#define DMA_INFIFO_RDATA_CH2_V  0xFFF
+#define DMA_INFIFO_RDATA_CH2_S  0
+
+#define DMA_IN_LINK_CH2_REG          (DR_REG_GDMA_BASE + 0x200)
+/* DMA_INLINK_PARK_CH2 : RO ;bitpos:[24] ;default: 1'h1 ; */
+/*description: 1: the inlink descriptor's FSM is in idle state.  0: the inlink
+ descriptor's FSM is working.*/
+#define DMA_INLINK_PARK_CH2  (BIT(24))
+#define DMA_INLINK_PARK_CH2_M  (BIT(24))
+#define DMA_INLINK_PARK_CH2_V  0x1
+#define DMA_INLINK_PARK_CH2_S  24
+/* DMA_INLINK_RESTART_CH2 : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Set this bit to mount a new inlink descriptor.*/
+#define DMA_INLINK_RESTART_CH2  (BIT(23))
+#define DMA_INLINK_RESTART_CH2_M  (BIT(23))
+#define DMA_INLINK_RESTART_CH2_V  0x1
+#define DMA_INLINK_RESTART_CH2_S  23
+/* DMA_INLINK_START_CH2 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Set this bit to start dealing with the inlink descriptors.*/
+#define DMA_INLINK_START_CH2  (BIT(22))
+#define DMA_INLINK_START_CH2_M  (BIT(22))
+#define DMA_INLINK_START_CH2_V  0x1
+#define DMA_INLINK_START_CH2_S  22
+/* DMA_INLINK_STOP_CH2 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Set this bit to stop dealing with the inlink descriptors.*/
+#define DMA_INLINK_STOP_CH2  (BIT(21))
+#define DMA_INLINK_STOP_CH2_M  (BIT(21))
+#define DMA_INLINK_STOP_CH2_V  0x1
+#define DMA_INLINK_STOP_CH2_S  21
+/* DMA_INLINK_AUTO_RET_CH2 : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: Set this bit to return to current inlink descriptor's address
+  when there are some errors in current receiving data.*/
+#define DMA_INLINK_AUTO_RET_CH2  (BIT(20))
+#define DMA_INLINK_AUTO_RET_CH2_M  (BIT(20))
+#define DMA_INLINK_AUTO_RET_CH2_V  0x1
+#define DMA_INLINK_AUTO_RET_CH2_S  20
+/* DMA_INLINK_ADDR_CH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: This register stores the 20 least significant bits of the first
+ inlink descriptor's address.*/
+#define DMA_INLINK_ADDR_CH2  0x000FFFFF
+#define DMA_INLINK_ADDR_CH2_M  ((DMA_INLINK_ADDR_CH2_V)<<(DMA_INLINK_ADDR_CH2_S))
+#define DMA_INLINK_ADDR_CH2_V  0xFFFFF
+#define DMA_INLINK_ADDR_CH2_S  0
+
+#define DMA_IN_STATE_CH2_REG          (DR_REG_GDMA_BASE + 0x204)
+/* DMA_IN_STATE_CH2 : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: reserved*/
+#define DMA_IN_STATE_CH2  0x00000007
+#define DMA_IN_STATE_CH2_M  ((DMA_IN_STATE_CH2_V)<<(DMA_IN_STATE_CH2_S))
+#define DMA_IN_STATE_CH2_V  0x7
+#define DMA_IN_STATE_CH2_S  20
+/* DMA_IN_DSCR_STATE_CH2 : RO ;bitpos:[19:18] ;default: 2'b0 ; */
+/*description: reserved*/
+#define DMA_IN_DSCR_STATE_CH2  0x00000003
+#define DMA_IN_DSCR_STATE_CH2_M  ((DMA_IN_DSCR_STATE_CH2_V)<<(DMA_IN_DSCR_STATE_CH2_S))
+#define DMA_IN_DSCR_STATE_CH2_V  0x3
+#define DMA_IN_DSCR_STATE_CH2_S  18
+/* DMA_INLINK_DSCR_ADDR_CH2 : RO ;bitpos:[17:0] ;default: 18'b0 ; */
+/*description: This register stores the current inlink descriptor's address.*/
+#define DMA_INLINK_DSCR_ADDR_CH2  0x0003FFFF
+#define DMA_INLINK_DSCR_ADDR_CH2_M  ((DMA_INLINK_DSCR_ADDR_CH2_V)<<(DMA_INLINK_DSCR_ADDR_CH2_S))
+#define DMA_INLINK_DSCR_ADDR_CH2_V  0x3FFFF
+#define DMA_INLINK_DSCR_ADDR_CH2_S  0
+
+#define DMA_IN_SUC_EOF_DES_ADDR_CH2_REG          (DR_REG_GDMA_BASE + 0x208)
+/* DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the address of the inlink descriptor when
+ the EOF bit in this descriptor is 1.*/
+#define DMA_IN_SUC_EOF_DES_ADDR_CH2  0xFFFFFFFF
+#define DMA_IN_SUC_EOF_DES_ADDR_CH2_M  ((DMA_IN_SUC_EOF_DES_ADDR_CH2_V)<<(DMA_IN_SUC_EOF_DES_ADDR_CH2_S))
+#define DMA_IN_SUC_EOF_DES_ADDR_CH2_V  0xFFFFFFFF
+#define DMA_IN_SUC_EOF_DES_ADDR_CH2_S  0
+
+#define DMA_IN_ERR_EOF_DES_ADDR_CH2_REG          (DR_REG_GDMA_BASE + 0x20C)
+/* DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the address of the inlink descriptor when
+ there are some errors in current receiving data. Only used when peripheral is UHCI0.*/
+#define DMA_IN_ERR_EOF_DES_ADDR_CH2  0xFFFFFFFF
+#define DMA_IN_ERR_EOF_DES_ADDR_CH2_M  ((DMA_IN_ERR_EOF_DES_ADDR_CH2_V)<<(DMA_IN_ERR_EOF_DES_ADDR_CH2_S))
+#define DMA_IN_ERR_EOF_DES_ADDR_CH2_V  0xFFFFFFFF
+#define DMA_IN_ERR_EOF_DES_ADDR_CH2_S  0
+
+#define DMA_IN_DSCR_CH2_REG          (DR_REG_GDMA_BASE + 0x210)
+/* DMA_INLINK_DSCR_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of the current inlink descriptor x.*/
+#define DMA_INLINK_DSCR_CH2  0xFFFFFFFF
+#define DMA_INLINK_DSCR_CH2_M  ((DMA_INLINK_DSCR_CH2_V)<<(DMA_INLINK_DSCR_CH2_S))
+#define DMA_INLINK_DSCR_CH2_V  0xFFFFFFFF
+#define DMA_INLINK_DSCR_CH2_S  0
+
+#define DMA_IN_DSCR_BF0_CH2_REG          (DR_REG_GDMA_BASE + 0x214)
+/* DMA_INLINK_DSCR_BF0_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of the last inlink descriptor x-1.*/
+#define DMA_INLINK_DSCR_BF0_CH2  0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF0_CH2_M  ((DMA_INLINK_DSCR_BF0_CH2_V)<<(DMA_INLINK_DSCR_BF0_CH2_S))
+#define DMA_INLINK_DSCR_BF0_CH2_V  0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF0_CH2_S  0
+
+#define DMA_IN_DSCR_BF1_CH2_REG          (DR_REG_GDMA_BASE + 0x218)
+/* DMA_INLINK_DSCR_BF1_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of the second-to-last inlink descriptor x-2.*/
+#define DMA_INLINK_DSCR_BF1_CH2  0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF1_CH2_M  ((DMA_INLINK_DSCR_BF1_CH2_V)<<(DMA_INLINK_DSCR_BF1_CH2_S))
+#define DMA_INLINK_DSCR_BF1_CH2_V  0xFFFFFFFF
+#define DMA_INLINK_DSCR_BF1_CH2_S  0
+
+#define DMA_IN_PRI_CH2_REG          (DR_REG_GDMA_BASE + 0x21C)
+/* DMA_RX_PRI_CH2 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: The priority of Rx channel 2. The larger of the value  the higher
+ of the priority.*/
+#define DMA_RX_PRI_CH2  0x0000000F
+#define DMA_RX_PRI_CH2_M  ((DMA_RX_PRI_CH2_V)<<(DMA_RX_PRI_CH2_S))
+#define DMA_RX_PRI_CH2_V  0xF
+#define DMA_RX_PRI_CH2_S  0
+
+#define DMA_IN_PERI_SEL_CH2_REG          (DR_REG_GDMA_BASE + 0x220)
+/* DMA_PERI_IN_SEL_CH2 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */
+/*description: This register is used to select peripheral for Rx channel 2.
+ 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/
+#define DMA_PERI_IN_SEL_CH2  0x0000003F
+#define DMA_PERI_IN_SEL_CH2_M  ((DMA_PERI_IN_SEL_CH2_V)<<(DMA_PERI_IN_SEL_CH2_S))
+#define DMA_PERI_IN_SEL_CH2_V  0x3F
+#define DMA_PERI_IN_SEL_CH2_S  0
+
+#define DMA_OUT_CONF0_CH2_REG          (DR_REG_GDMA_BASE + 0x250)
+/* DMA_OUT_DATA_BURST_EN_CH2 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel
+ 2 transmitting data when accessing internal SRAM.*/
+#define DMA_OUT_DATA_BURST_EN_CH2  (BIT(5))
+#define DMA_OUT_DATA_BURST_EN_CH2_M  (BIT(5))
+#define DMA_OUT_DATA_BURST_EN_CH2_V  0x1
+#define DMA_OUT_DATA_BURST_EN_CH2_S  5
+/* DMA_OUTDSCR_BURST_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel
+ 2 reading link descriptor when accessing internal SRAM.*/
+#define DMA_OUTDSCR_BURST_EN_CH2  (BIT(4))
+#define DMA_OUTDSCR_BURST_EN_CH2_M  (BIT(4))
+#define DMA_OUTDSCR_BURST_EN_CH2_V  0x1
+#define DMA_OUTDSCR_BURST_EN_CH2_S  4
+/* DMA_OUT_EOF_MODE_CH2 : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: EOF flag generation mode when transmitting data. 1: EOF flag
+ for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA*/
+#define DMA_OUT_EOF_MODE_CH2  (BIT(3))
+#define DMA_OUT_EOF_MODE_CH2_M  (BIT(3))
+#define DMA_OUT_EOF_MODE_CH2_V  0x1
+#define DMA_OUT_EOF_MODE_CH2_S  3
+/* DMA_OUT_AUTO_WRBACK_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to enable automatic outlink-writeback when all the
+ data in tx buffer has been transmitted.*/
+#define DMA_OUT_AUTO_WRBACK_CH2  (BIT(2))
+#define DMA_OUT_AUTO_WRBACK_CH2_M  (BIT(2))
+#define DMA_OUT_AUTO_WRBACK_CH2_V  0x1
+#define DMA_OUT_AUTO_WRBACK_CH2_S  2
+/* DMA_OUT_LOOP_TEST_CH2 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: reserved*/
+#define DMA_OUT_LOOP_TEST_CH2  (BIT(1))
+#define DMA_OUT_LOOP_TEST_CH2_M  (BIT(1))
+#define DMA_OUT_LOOP_TEST_CH2_V  0x1
+#define DMA_OUT_LOOP_TEST_CH2_S  1
+/* DMA_OUT_RST_CH2 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.*/
+#define DMA_OUT_RST_CH2  (BIT(0))
+#define DMA_OUT_RST_CH2_M  (BIT(0))
+#define DMA_OUT_RST_CH2_V  0x1
+#define DMA_OUT_RST_CH2_S  0
+
+#define DMA_OUT_CONF1_CH2_REG          (DR_REG_GDMA_BASE + 0x254)
+/* DMA_OUT_CHECK_OWNER_CH2 : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/
+#define DMA_OUT_CHECK_OWNER_CH2  (BIT(12))
+#define DMA_OUT_CHECK_OWNER_CH2_M  (BIT(12))
+#define DMA_OUT_CHECK_OWNER_CH2_V  0x1
+#define DMA_OUT_CHECK_OWNER_CH2_S  12
+
+#define DMA_OUTFIFO_STATUS_CH2_REG          (DR_REG_GDMA_BASE + 0x258)
+/* DMA_OUT_REMAIN_UNDER_4B_CH2 : RO ;bitpos:[26] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_OUT_REMAIN_UNDER_4B_CH2  (BIT(26))
+#define DMA_OUT_REMAIN_UNDER_4B_CH2_M  (BIT(26))
+#define DMA_OUT_REMAIN_UNDER_4B_CH2_V  0x1
+#define DMA_OUT_REMAIN_UNDER_4B_CH2_S  26
+/* DMA_OUT_REMAIN_UNDER_3B_CH2 : RO ;bitpos:[25] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_OUT_REMAIN_UNDER_3B_CH2  (BIT(25))
+#define DMA_OUT_REMAIN_UNDER_3B_CH2_M  (BIT(25))
+#define DMA_OUT_REMAIN_UNDER_3B_CH2_V  0x1
+#define DMA_OUT_REMAIN_UNDER_3B_CH2_S  25
+/* DMA_OUT_REMAIN_UNDER_2B_CH2 : RO ;bitpos:[24] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_OUT_REMAIN_UNDER_2B_CH2  (BIT(24))
+#define DMA_OUT_REMAIN_UNDER_2B_CH2_M  (BIT(24))
+#define DMA_OUT_REMAIN_UNDER_2B_CH2_V  0x1
+#define DMA_OUT_REMAIN_UNDER_2B_CH2_S  24
+/* DMA_OUT_REMAIN_UNDER_1B_CH2 : RO ;bitpos:[23] ;default: 1'b1 ; */
+/*description: reserved*/
+#define DMA_OUT_REMAIN_UNDER_1B_CH2  (BIT(23))
+#define DMA_OUT_REMAIN_UNDER_1B_CH2_M  (BIT(23))
+#define DMA_OUT_REMAIN_UNDER_1B_CH2_V  0x1
+#define DMA_OUT_REMAIN_UNDER_1B_CH2_S  23
+/* DMA_OUTFIFO_CNT_CH2 : RO ;bitpos:[7:2] ;default: 6'b0 ; */
+/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.*/
+#define DMA_OUTFIFO_CNT_CH2  0x0000003F
+#define DMA_OUTFIFO_CNT_CH2_M  ((DMA_OUTFIFO_CNT_CH2_V)<<(DMA_OUTFIFO_CNT_CH2_S))
+#define DMA_OUTFIFO_CNT_CH2_V  0x3F
+#define DMA_OUTFIFO_CNT_CH2_S  2
+/* DMA_OUTFIFO_EMPTY_CH2 : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: L1 Tx FIFO empty signal for Tx channel 2.*/
+#define DMA_OUTFIFO_EMPTY_CH2  (BIT(1))
+#define DMA_OUTFIFO_EMPTY_CH2_M  (BIT(1))
+#define DMA_OUTFIFO_EMPTY_CH2_V  0x1
+#define DMA_OUTFIFO_EMPTY_CH2_S  1
+/* DMA_OUTFIFO_FULL_CH2 : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: L1 Tx FIFO full signal for Tx channel 2.*/
+#define DMA_OUTFIFO_FULL_CH2  (BIT(0))
+#define DMA_OUTFIFO_FULL_CH2_M  (BIT(0))
+#define DMA_OUTFIFO_FULL_CH2_V  0x1
+#define DMA_OUTFIFO_FULL_CH2_S  0
+
+#define DMA_OUT_PUSH_CH2_REG          (DR_REG_GDMA_BASE + 0x25C)
+/* DMA_OUTFIFO_PUSH_CH2 : R/W/SC ;bitpos:[9] ;default: 1'h0 ; */
+/*description: Set this bit to push data into DMA FIFO.*/
+#define DMA_OUTFIFO_PUSH_CH2  (BIT(9))
+#define DMA_OUTFIFO_PUSH_CH2_M  (BIT(9))
+#define DMA_OUTFIFO_PUSH_CH2_V  0x1
+#define DMA_OUTFIFO_PUSH_CH2_S  9
+/* DMA_OUTFIFO_WDATA_CH2 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: This register stores the data that need to be pushed into DMA FIFO.*/
+#define DMA_OUTFIFO_WDATA_CH2  0x000001FF
+#define DMA_OUTFIFO_WDATA_CH2_M  ((DMA_OUTFIFO_WDATA_CH2_V)<<(DMA_OUTFIFO_WDATA_CH2_S))
+#define DMA_OUTFIFO_WDATA_CH2_V  0x1FF
+#define DMA_OUTFIFO_WDATA_CH2_S  0
+
+#define DMA_OUT_LINK_CH2_REG          (DR_REG_GDMA_BASE + 0x260)
+/* DMA_OUTLINK_PARK_CH2 : RO ;bitpos:[23] ;default: 1'h1 ; */
+/*description: 1: the outlink descriptor's FSM is in idle state.  0: the outlink
+ descriptor's FSM is working.*/
+#define DMA_OUTLINK_PARK_CH2  (BIT(23))
+#define DMA_OUTLINK_PARK_CH2_M  (BIT(23))
+#define DMA_OUTLINK_PARK_CH2_V  0x1
+#define DMA_OUTLINK_PARK_CH2_S  23
+/* DMA_OUTLINK_RESTART_CH2 : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Set this bit to restart a new outlink from the last address.*/
+#define DMA_OUTLINK_RESTART_CH2  (BIT(22))
+#define DMA_OUTLINK_RESTART_CH2_M  (BIT(22))
+#define DMA_OUTLINK_RESTART_CH2_V  0x1
+#define DMA_OUTLINK_RESTART_CH2_S  22
+/* DMA_OUTLINK_START_CH2 : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Set this bit to start dealing with the outlink descriptors.*/
+#define DMA_OUTLINK_START_CH2  (BIT(21))
+#define DMA_OUTLINK_START_CH2_M  (BIT(21))
+#define DMA_OUTLINK_START_CH2_V  0x1
+#define DMA_OUTLINK_START_CH2_S  21
+/* DMA_OUTLINK_STOP_CH2 : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Set this bit to stop dealing with the outlink descriptors.*/
+#define DMA_OUTLINK_STOP_CH2  (BIT(20))
+#define DMA_OUTLINK_STOP_CH2_M  (BIT(20))
+#define DMA_OUTLINK_STOP_CH2_V  0x1
+#define DMA_OUTLINK_STOP_CH2_S  20
+/* DMA_OUTLINK_ADDR_CH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: This register stores the 20 least significant bits of the first
+ outlink descriptor's address.*/
+#define DMA_OUTLINK_ADDR_CH2  0x000FFFFF
+#define DMA_OUTLINK_ADDR_CH2_M  ((DMA_OUTLINK_ADDR_CH2_V)<<(DMA_OUTLINK_ADDR_CH2_S))
+#define DMA_OUTLINK_ADDR_CH2_V  0xFFFFF
+#define DMA_OUTLINK_ADDR_CH2_S  0
+
+#define DMA_OUT_STATE_CH2_REG          (DR_REG_GDMA_BASE + 0x264)
+/* DMA_OUT_STATE_CH2 : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: reserved*/
+#define DMA_OUT_STATE_CH2  0x00000007
+#define DMA_OUT_STATE_CH2_M  ((DMA_OUT_STATE_CH2_V)<<(DMA_OUT_STATE_CH2_S))
+#define DMA_OUT_STATE_CH2_V  0x7
+#define DMA_OUT_STATE_CH2_S  20
+/* DMA_OUT_DSCR_STATE_CH2 : RO ;bitpos:[19:18] ;default: 2'b0 ; */
+/*description: reserved*/
+#define DMA_OUT_DSCR_STATE_CH2  0x00000003
+#define DMA_OUT_DSCR_STATE_CH2_M  ((DMA_OUT_DSCR_STATE_CH2_V)<<(DMA_OUT_DSCR_STATE_CH2_S))
+#define DMA_OUT_DSCR_STATE_CH2_V  0x3
+#define DMA_OUT_DSCR_STATE_CH2_S  18
+/* DMA_OUTLINK_DSCR_ADDR_CH2 : RO ;bitpos:[17:0] ;default: 18'b0 ; */
+/*description: This register stores the current outlink descriptor's address.*/
+#define DMA_OUTLINK_DSCR_ADDR_CH2  0x0003FFFF
+#define DMA_OUTLINK_DSCR_ADDR_CH2_M  ((DMA_OUTLINK_DSCR_ADDR_CH2_V)<<(DMA_OUTLINK_DSCR_ADDR_CH2_S))
+#define DMA_OUTLINK_DSCR_ADDR_CH2_V  0x3FFFF
+#define DMA_OUTLINK_DSCR_ADDR_CH2_S  0
+
+#define DMA_OUT_EOF_DES_ADDR_CH2_REG          (DR_REG_GDMA_BASE + 0x268)
+/* DMA_OUT_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the address of the outlink descriptor when
+ the EOF bit in this descriptor is 1.*/
+#define DMA_OUT_EOF_DES_ADDR_CH2  0xFFFFFFFF
+#define DMA_OUT_EOF_DES_ADDR_CH2_M  ((DMA_OUT_EOF_DES_ADDR_CH2_V)<<(DMA_OUT_EOF_DES_ADDR_CH2_S))
+#define DMA_OUT_EOF_DES_ADDR_CH2_V  0xFFFFFFFF
+#define DMA_OUT_EOF_DES_ADDR_CH2_S  0
+
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG          (DR_REG_GDMA_BASE + 0x26C)
+/* DMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This register stores the address of the outlink descriptor before
+ the last outlink descriptor.*/
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH2  0xFFFFFFFF
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_M  ((DMA_OUT_EOF_BFR_DES_ADDR_CH2_V)<<(DMA_OUT_EOF_BFR_DES_ADDR_CH2_S))
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_V  0xFFFFFFFF
+#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_S  0
+
+#define DMA_OUT_DSCR_CH2_REG          (DR_REG_GDMA_BASE + 0x270)
+/* DMA_OUTLINK_DSCR_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of the current outlink descriptor y.*/
+#define DMA_OUTLINK_DSCR_CH2  0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_CH2_M  ((DMA_OUTLINK_DSCR_CH2_V)<<(DMA_OUTLINK_DSCR_CH2_S))
+#define DMA_OUTLINK_DSCR_CH2_V  0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_CH2_S  0
+
+#define DMA_OUT_DSCR_BF0_CH2_REG          (DR_REG_GDMA_BASE + 0x274)
+/* DMA_OUTLINK_DSCR_BF0_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of the last outlink descriptor y-1.*/
+#define DMA_OUTLINK_DSCR_BF0_CH2  0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF0_CH2_M  ((DMA_OUTLINK_DSCR_BF0_CH2_V)<<(DMA_OUTLINK_DSCR_BF0_CH2_S))
+#define DMA_OUTLINK_DSCR_BF0_CH2_V  0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF0_CH2_S  0
+
+#define DMA_OUT_DSCR_BF1_CH2_REG          (DR_REG_GDMA_BASE + 0x278)
+/* DMA_OUTLINK_DSCR_BF1_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of the second-to-last inlink descriptor x-2.*/
+#define DMA_OUTLINK_DSCR_BF1_CH2  0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF1_CH2_M  ((DMA_OUTLINK_DSCR_BF1_CH2_V)<<(DMA_OUTLINK_DSCR_BF1_CH2_S))
+#define DMA_OUTLINK_DSCR_BF1_CH2_V  0xFFFFFFFF
+#define DMA_OUTLINK_DSCR_BF1_CH2_S  0
+
+#define DMA_OUT_PRI_CH2_REG          (DR_REG_GDMA_BASE + 0x27C)
+/* DMA_TX_PRI_CH2 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: The priority of Tx channel 2. The larger of the value  the higher
+ of the priority.*/
+#define DMA_TX_PRI_CH2  0x0000000F
+#define DMA_TX_PRI_CH2_M  ((DMA_TX_PRI_CH2_V)<<(DMA_TX_PRI_CH2_S))
+#define DMA_TX_PRI_CH2_V  0xF
+#define DMA_TX_PRI_CH2_S  0
+
+#define DMA_OUT_PERI_SEL_CH2_REG          (DR_REG_GDMA_BASE + 0x280)
+/* DMA_PERI_OUT_SEL_CH2 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */
+/*description: This register is used to select peripheral for Tx channel 2.
+ 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/
+#define DMA_PERI_OUT_SEL_CH2  0x0000003F
+#define DMA_PERI_OUT_SEL_CH2_M  ((DMA_PERI_OUT_SEL_CH2_V)<<(DMA_PERI_OUT_SEL_CH2_S))
+#define DMA_PERI_OUT_SEL_CH2_V  0x3F
+#define DMA_PERI_OUT_SEL_CH2_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_DMA_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/gdma_struct.h b/components/soc/esp32c3/include/soc/gdma_struct.h
new file mode 100644
index 0000000000..446ff4c112
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/gdma_struct.h
@@ -0,0 +1,331 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    struct {
+        union {
+            struct {
+                uint32_t in_done:                   1;       /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/
+                uint32_t in_suc_eof:                1;       /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0  the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/
+                uint32_t in_err_eof:                1;       /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals  this raw interrupt is reserved.*/
+                uint32_t out_done:                  1;       /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/
+                uint32_t out_eof:                   1;       /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.*/
+                uint32_t in_dscr_err:               1;       /*The raw interrupt bit turns to high level when detecting inlink descriptor error  including owner error  the second and third word error of inlink descriptor for Rx channel 0.*/
+                uint32_t out_dscr_err:              1;       /*The raw interrupt bit turns to high level when detecting outlink descriptor error  including owner error  the second and third word error of outlink descriptor for Tx channel 0.*/
+                uint32_t in_dscr_empty:             1;       /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed  but there is no more inlink for Rx channel 0.*/
+                uint32_t out_total_eof:             1;       /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/
+                uint32_t infifo_ovf:                1;       /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.*/
+                uint32_t infifo_udf:                1;       /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.*/
+                uint32_t outfifo_ovf:               1;       /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.*/
+                uint32_t outfifo_udf:               1;       /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.*/
+                uint32_t reserved13:               19;       /*reserved*/
+            };
+            uint32_t val;
+        } raw;
+        union {
+            struct {
+                uint32_t in_done:                  1;        /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/
+                uint32_t in_suc_eof:               1;        /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/
+                uint32_t in_err_eof:               1;        /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/
+                uint32_t out_done:                 1;        /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/
+                uint32_t out_eof:                  1;        /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/
+                uint32_t in_dscr_err:              1;        /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/
+                uint32_t out_dscr_err:             1;        /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
+                uint32_t in_dscr_empty:            1;        /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
+                uint32_t out_total_eof:            1;        /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
+                uint32_t infifo_ovf:               1;        /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
+                uint32_t infifo_udf:               1;        /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
+                uint32_t outfifo_ovf:              1;        /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
+                uint32_t outfifo_udf:              1;        /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
+                uint32_t reserved13:              19;        /*reserved*/
+            };
+            uint32_t val;
+        } st;
+        union {
+            struct {
+                uint32_t in_done:                   1;       /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/
+                uint32_t in_suc_eof:                1;       /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/
+                uint32_t in_err_eof:                1;       /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/
+                uint32_t out_done:                  1;       /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/
+                uint32_t out_eof:                   1;       /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/
+                uint32_t in_dscr_err:               1;       /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/
+                uint32_t out_dscr_err:              1;       /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
+                uint32_t in_dscr_empty:             1;       /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
+                uint32_t out_total_eof:             1;       /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
+                uint32_t infifo_ovf:                1;       /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
+                uint32_t infifo_udf:                1;       /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
+                uint32_t outfifo_ovf:               1;       /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
+                uint32_t outfifo_udf:               1;       /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
+                uint32_t reserved13:               19;       /*reserved*/
+            };
+            uint32_t val;
+        } ena;
+        union {
+            struct {
+                uint32_t in_done:                   1;       /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/
+                uint32_t in_suc_eof:                1;       /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/
+                uint32_t in_err_eof:                1;       /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/
+                uint32_t out_done:                  1;       /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/
+                uint32_t out_eof:                   1;       /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/
+                uint32_t in_dscr_err:               1;       /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/
+                uint32_t out_dscr_err:              1;       /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/
+                uint32_t in_dscr_empty:             1;       /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/
+                uint32_t out_total_eof:             1;       /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/
+                uint32_t infifo_ovf:                1;       /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/
+                uint32_t infifo_udf:                1;       /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/
+                uint32_t outfifo_ovf:               1;       /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/
+                uint32_t outfifo_udf:               1;       /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/
+                uint32_t reserved13:               19;       /*reserved*/
+            };
+            uint32_t val;
+        } clr;
+    } intr[3];
+    uint32_t reserved_30;
+    uint32_t reserved_34;
+    uint32_t reserved_38;
+    uint32_t reserved_3c;
+    union {
+        struct {
+            uint32_t ahb_testmode: 3;                    /*reserved*/
+            uint32_t reserved3:    1;                    /*reserved*/
+            uint32_t ahb_testaddr: 2;                    /*reserved*/
+            uint32_t reserved6:   26;                    /*reserved*/
+        };
+        uint32_t val;
+    } ahb_test;
+    union {
+        struct {
+            uint32_t ahbm_rst_inter: 1;                  /*Set this bit  then clear this bit to reset the internal ahb FSM.*/
+            uint32_t reserved1:      1;
+            uint32_t arb_pri_dis:    1;                  /*Set this bit to disable priority arbitration function.*/
+            uint32_t clk_en:         1;
+            uint32_t reserved4:     28;
+        };
+        uint32_t val;
+    } misc_conf;
+    uint32_t date;                                       /**/
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    uint32_t reserved_54;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    struct {
+        struct {
+            union {
+                struct {
+                    uint32_t in_rst:               1;            /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/
+                    uint32_t in_loop_test:         1;            /*reserved*/
+                    uint32_t indscr_burst_en:      1;            /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.*/
+                    uint32_t in_data_burst_en:     1;            /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.*/
+                    uint32_t mem_trans_en:         1;            /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/
+                    uint32_t reserved5:           27;            /*reserved*/
+                };
+                uint32_t val;
+            } in_conf0;
+            union {
+                struct {
+                    uint32_t reserved0:         12;
+                    uint32_t in_check_owner:     1;              /*Set this bit to enable checking the owner attribute of the link descriptor.*/
+                    uint32_t reserved13:        19;              /*reserved*/
+                };
+                uint32_t val;
+            } in_conf1;
+            union {
+                struct {
+                    uint32_t infifo_full:            1;          /*L1 Rx FIFO full signal for Rx channel 0.*/
+                    uint32_t infifo_empty:           1;          /*L1 Rx FIFO empty signal for Rx channel 0.*/
+                    uint32_t infifo_cnt:             6;          /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/
+                    uint32_t reserved8:             15;          /*reserved*/
+                    uint32_t in_remain_under_1b:     1;          /*reserved*/
+                    uint32_t in_remain_under_2b:     1;          /*reserved*/
+                    uint32_t in_remain_under_3b:     1;          /*reserved*/
+                    uint32_t in_remain_under_4b:     1;          /*reserved*/
+                    uint32_t in_buf_hungry:          1;          /*reserved*/
+                    uint32_t reserved28:             4;          /*reserved*/
+                };
+                uint32_t val;
+            } infifo_status;
+            union {
+                struct {
+                    uint32_t infifo_rdata:    12;                /*This register stores the data popping from DMA FIFO.*/
+                    uint32_t infifo_pop:       1;                /*Set this bit to pop data from DMA FIFO.*/
+                    uint32_t reserved13:      19;                /*reserved*/
+                };
+                uint32_t val;
+            } in_pop;
+            union {
+                struct {
+                    uint32_t addr:               20;             /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/
+                    uint32_t auto_ret:            1;             /*Set this bit to return to current inlink descriptor's address  when there are some errors in current receiving data.*/
+                    uint32_t stop:                1;             /*Set this bit to stop dealing with the inlink descriptors.*/
+                    uint32_t start:               1;             /*Set this bit to start dealing with the inlink descriptors.*/
+                    uint32_t restart:             1;             /*Set this bit to mount a new inlink descriptor.*/
+                    uint32_t park:                1;             /*1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.*/
+                    uint32_t reserved25:          7;
+                };
+                uint32_t val;
+            } in_link;
+            union {
+                struct {
+                    uint32_t inlink_dscr_addr:    18;            /*This register stores the current inlink descriptor's address.*/
+                    uint32_t in_dscr_state:        2;            /*reserved*/
+                    uint32_t in_state:             3;            /*reserved*/
+                    uint32_t reserved23:           9;            /*reserved*/
+                };
+                uint32_t val;
+            } in_state;
+            uint32_t in_suc_eof_des_addr;                    /**/
+            uint32_t in_err_eof_des_addr;                    /**/
+            uint32_t in_dscr;                                /**/
+            uint32_t in_dscr_bf0;                            /**/
+            uint32_t in_dscr_bf1;                            /**/
+            union {
+                struct {
+                    uint32_t rx_pri:     4;                      /*The priority of Rx channel 0. The larger of the value  the higher of the priority.*/
+                    uint32_t reserved4: 28;
+                };
+                uint32_t val;
+            } in_pri;
+            union {
+                struct {
+                    uint32_t sel:             6;                 /*This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/
+                    uint32_t reserved6:      26;
+                };
+                uint32_t val;
+            } in_peri_sel;
+        } in;
+        uint32_t reserved_a4;
+        uint32_t reserved_a8;
+        uint32_t reserved_ac;
+        uint32_t reserved_b0;
+        uint32_t reserved_b4;
+        uint32_t reserved_b8;
+        uint32_t reserved_bc;
+        uint32_t reserved_c0;
+        uint32_t reserved_c4;
+        uint32_t reserved_c8;
+        uint32_t reserved_cc;
+        struct {
+            union {
+                struct {
+                    uint32_t out_rst:               1;           /*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/
+                    uint32_t out_loop_test:         1;           /*reserved*/
+                    uint32_t out_auto_wrback:       1;           /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/
+                    uint32_t out_eof_mode:          1;           /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/
+                    uint32_t outdscr_burst_en:      1;           /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.*/
+                    uint32_t out_data_burst_en:     1;           /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.*/
+                    uint32_t reserved6:            26;
+                };
+                uint32_t val;
+            } out_conf0;
+            union {
+                struct {
+                    uint32_t reserved0:          12;
+                    uint32_t out_check_owner:     1;             /*Set this bit to enable checking the owner attribute of the link descriptor.*/
+                    uint32_t reserved13:         19;             /*reserved*/
+                };
+                uint32_t val;
+            } out_conf1;
+            union {
+                struct {
+                    uint32_t outfifo_full:            1;         /*L1 Tx FIFO full signal for Tx channel 0.*/
+                    uint32_t outfifo_empty:           1;         /*L1 Tx FIFO empty signal for Tx channel 0.*/
+                    uint32_t outfifo_cnt:             6;         /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/
+                    uint32_t reserved8:              15;         /*reserved*/
+                    uint32_t out_remain_under_1b:     1;         /*reserved*/
+                    uint32_t out_remain_under_2b:     1;         /*reserved*/
+                    uint32_t out_remain_under_3b:     1;         /*reserved*/
+                    uint32_t out_remain_under_4b:     1;         /*reserved*/
+                    uint32_t reserved27:              5;         /*reserved*/
+                };
+                uint32_t val;
+            } outfifo_status;
+            union {
+                struct {
+                    uint32_t outfifo_wdata:     9;               /*This register stores the data that need to be pushed into DMA FIFO.*/
+                    uint32_t outfifo_push:      1;               /*Set this bit to push data into DMA FIFO.*/
+                    uint32_t reserved10:       22;               /*reserved*/
+                };
+                uint32_t val;
+            } out_push;
+            union {
+                struct {
+                    uint32_t addr:               20;             /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/
+                    uint32_t stop:                1;             /*Set this bit to stop dealing with the outlink descriptors.*/
+                    uint32_t start:               1;             /*Set this bit to start dealing with the outlink descriptors.*/
+                    uint32_t restart:             1;             /*Set this bit to restart a new outlink from the last address.*/
+                    uint32_t park:                1;             /*1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.*/
+                    uint32_t reserved24:          8;
+                };
+                uint32_t val;
+            } out_link;
+            union {
+                struct {
+                    uint32_t outlink_dscr_addr:    18;           /*This register stores the current outlink descriptor's address.*/
+                    uint32_t out_dscr_state:        2;           /*reserved*/
+                    uint32_t out_state:             3;           /*reserved*/
+                    uint32_t reserved23:            9;           /*reserved*/
+                };
+                uint32_t val;
+            } out_state;
+            uint32_t out_eof_des_addr;                       /**/
+            uint32_t out_eof_bfr_des_addr;                   /**/
+            uint32_t out_dscr;                               /**/
+            uint32_t out_dscr_bf0;                           /**/
+            uint32_t out_dscr_bf1;                           /**/
+            union {
+                struct {
+                    uint32_t tx_pri:     4;                      /*The priority of Tx channel 0. The larger of the value  the higher of the priority.*/
+                    uint32_t reserved4: 28;
+                };
+                uint32_t val;
+            } out_pri;
+            union {
+                struct {
+                    uint32_t sel:              6;                /*This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/
+                    uint32_t reserved6:       26;
+                };
+                uint32_t val;
+            } out_peri_sel;
+        } out;
+        uint32_t reserved_104;
+        uint32_t reserved_108;
+        uint32_t reserved_10c;
+        uint32_t reserved_110;
+        uint32_t reserved_114;
+        uint32_t reserved_118;
+        uint32_t reserved_11c;
+        uint32_t reserved_120;
+        uint32_t reserved_124;
+        uint32_t reserved_128;
+        uint32_t reserved_12c;
+    } channel[3];
+} gdma_dev_t;
+
+extern gdma_dev_t GDMA;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/include/soc/gpio_caps.h b/components/soc/esp32c3/include/soc/gpio_caps.h
new file mode 100644
index 0000000000..ec0ff52cca
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/gpio_caps.h
@@ -0,0 +1,43 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SOC_GPIO_PORT           (1)
+#define SOC_GPIO_PIN_COUNT          (22)
+
+// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
+#define GPIO_SUPPORTS_RTC_INDEPENDENT (1)
+
+#define GPIO_SUPPORTS_FORCE_HOLD      (1)
+
+#define GPIO_PRO_CPU_INTR_ENA      (BIT(0))
+#define GPIO_PRO_CPU_NMI_INTR_ENA  (BIT(1))
+
+#define GPIO_MODE_DEF_DISABLE         (0)
+#define GPIO_MODE_DEF_INPUT           (BIT0)
+#define GPIO_MODE_DEF_OUTPUT          (BIT1)
+#define GPIO_MODE_DEF_OD              (BIT2)
+
+// TODO ESP32-C3 IDF-2119 - check if any IOs are not full featured GPIO
+#define SOC_GPIO_VALID_GPIO_MASK        ((1U<<SOC_GPIO_PIN_COUNT) - 1)
+#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/include/soc/gpio_pins.h b/components/soc/esp32c3/include/soc/gpio_pins.h
new file mode 100644
index 0000000000..f5a35b9975
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/gpio_pins.h
@@ -0,0 +1,27 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define GPIO_MATRIX_CONST_ONE_INPUT   (0x1E)
+#define GPIO_MATRIX_CONST_ZERO_INPUT  (0x1F)
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/include/soc/gpio_reg.h b/components/soc/esp32c3/include/soc/gpio_reg.h
new file mode 100644
index 0000000000..a674277f99
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/gpio_reg.h
@@ -0,0 +1,4588 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_GPIO_REG_H_
+#define _SOC_GPIO_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define GPIO_PIN_CONFIG_MSB                    12
+#define GPIO_PIN_CONFIG_LSB                     11
+#define GPIO_PIN_CONFIG_MASK                   0x00001800
+#define GPIO_PIN_CONFIG_GET(x)                 (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB)
+#define GPIO_PIN_CONFIG_SET(x)                  (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK)
+
+#define GPIO_WAKEUP_ENABLE                     1
+#define GPIO_WAKEUP_DISABLE                    (~GPIO_WAKEUP_ENABLE)
+#define GPIO_PIN_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK)
+
+#define GPIO_PIN_INT_TYPE_MASK                 0x380
+#define GPIO_PIN_INT_TYPE_MSB                  9
+#define GPIO_PIN_INT_TYPE_LSB                  7
+#define GPIO_PIN_INT_TYPE_GET(x)               (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
+#define GPIO_PIN_INT_TYPE_SET(x)               (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK)
+
+#define GPIO_PAD_DRIVER_ENABLE                 1
+#define GPIO_PAD_DRIVER_DISABLE                        (~GPIO_PAD_DRIVER_ENABLE)
+#define GPIO_PIN_PAD_DRIVER_MSB                        2
+#define GPIO_PIN_PAD_DRIVER_LSB                        2
+#define GPIO_PIN_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB)
+#define GPIO_PIN_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK)
+
+#define GPIO_BT_SELECT_REG          (DR_REG_GPIO_BASE + 0x0)
+/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define GPIO_BT_SEL  0xFFFFFFFF
+#define GPIO_BT_SEL_M  ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S))
+#define GPIO_BT_SEL_V  0xFFFFFFFF
+#define GPIO_BT_SEL_S  0
+
+#define GPIO_OUT_REG          (DR_REG_GPIO_BASE + 0x4)
+/* GPIO_OUT_DATA : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_OUT_DATA  0x03FFFFFF
+#define GPIO_OUT_DATA_M  ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S))
+#define GPIO_OUT_DATA_V  0x3FFFFFF
+#define GPIO_OUT_DATA_S  0
+
+#define GPIO_OUT_W1TS_REG          (DR_REG_GPIO_BASE + 0x8)
+/* GPIO_OUT_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_OUT_W1TS  0x03FFFFFF
+#define GPIO_OUT_W1TS_M  ((GPIO_OUT_W1TS_V)<<(GPIO_OUT_W1TS_S))
+#define GPIO_OUT_W1TS_V  0x3FFFFFF
+#define GPIO_OUT_W1TS_S  0
+
+#define GPIO_OUT_W1TC_REG          (DR_REG_GPIO_BASE + 0xC)
+/* GPIO_OUT_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_OUT_W1TC  0x03FFFFFF
+#define GPIO_OUT_W1TC_M  ((GPIO_OUT_W1TC_V)<<(GPIO_OUT_W1TC_S))
+#define GPIO_OUT_W1TC_V  0x3FFFFFF
+#define GPIO_OUT_W1TC_S  0
+
+#define GPIO_SDIO_SELECT_REG          (DR_REG_GPIO_BASE + 0x1C)
+/* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SDIO_SEL  0x000000FF
+#define GPIO_SDIO_SEL_M  ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S))
+#define GPIO_SDIO_SEL_V  0xFF
+#define GPIO_SDIO_SEL_S  0
+
+#define GPIO_ENABLE_REG          (DR_REG_GPIO_BASE + 0x20)
+/* GPIO_ENABLE_DATA : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_ENABLE_DATA  0x03FFFFFF
+#define GPIO_ENABLE_DATA_M  ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S))
+#define GPIO_ENABLE_DATA_V  0x3FFFFFF
+#define GPIO_ENABLE_DATA_S  0
+
+#define GPIO_ENABLE_W1TS_REG          (DR_REG_GPIO_BASE + 0x24)
+/* GPIO_ENABLE_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_ENABLE_W1TS  0x03FFFFFF
+#define GPIO_ENABLE_W1TS_M  ((GPIO_ENABLE_W1TS_V)<<(GPIO_ENABLE_W1TS_S))
+#define GPIO_ENABLE_W1TS_V  0x3FFFFFF
+#define GPIO_ENABLE_W1TS_S  0
+
+#define GPIO_ENABLE_W1TC_REG          (DR_REG_GPIO_BASE + 0x28)
+/* GPIO_ENABLE_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_ENABLE_W1TC  0x03FFFFFF
+#define GPIO_ENABLE_W1TC_M  ((GPIO_ENABLE_W1TC_V)<<(GPIO_ENABLE_W1TC_S))
+#define GPIO_ENABLE_W1TC_V  0x3FFFFFF
+#define GPIO_ENABLE_W1TC_S  0
+
+#define GPIO_STRAP_REG          (DR_REG_GPIO_BASE + 0x38)
+/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default:  ; */
+/*description: */
+#define GPIO_STRAPPING  0x0000FFFF
+#define GPIO_STRAPPING_M  ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S))
+#define GPIO_STRAPPING_V  0xFFFF
+#define GPIO_STRAPPING_S  0
+
+#define GPIO_IN_REG          (DR_REG_GPIO_BASE + 0x3C)
+/* GPIO_IN_DATA : RO ;bitpos:[25:0] ;default:  ; */
+/*description: */
+#define GPIO_IN_DATA  0x03FFFFFF
+#define GPIO_IN_DATA_M  ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S))
+#define GPIO_IN_DATA_V  0x3FFFFFF
+#define GPIO_IN_DATA_S  0
+
+#define GPIO_STATUS_REG          (DR_REG_GPIO_BASE + 0x44)
+/* GPIO_STATUS_INT : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_STATUS_INT  0x03FFFFFF
+#define GPIO_STATUS_INT_M  ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S))
+#define GPIO_STATUS_INT_V  0x3FFFFFF
+#define GPIO_STATUS_INT_S  0
+
+#define GPIO_STATUS_W1TS_REG          (DR_REG_GPIO_BASE + 0x48)
+/* GPIO_STATUS_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_STATUS_W1TS  0x03FFFFFF
+#define GPIO_STATUS_W1TS_M  ((GPIO_STATUS_W1TS_V)<<(GPIO_STATUS_W1TS_S))
+#define GPIO_STATUS_W1TS_V  0x3FFFFFF
+#define GPIO_STATUS_W1TS_S  0
+
+#define GPIO_STATUS_W1TC_REG          (DR_REG_GPIO_BASE + 0x4C)
+/* GPIO_STATUS_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_STATUS_W1TC  0x03FFFFFF
+#define GPIO_STATUS_W1TC_M  ((GPIO_STATUS_W1TC_V)<<(GPIO_STATUS_W1TC_S))
+#define GPIO_STATUS_W1TC_V  0x3FFFFFF
+#define GPIO_STATUS_W1TC_S  0
+
+#define GPIO_PCPU_INT_REG          (DR_REG_GPIO_BASE + 0x5C)
+/* GPIO_PROCPU_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_PROCPU_INT  0x03FFFFFF
+#define GPIO_PROCPU_INT_M  ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S))
+#define GPIO_PROCPU_INT_V  0x3FFFFFF
+#define GPIO_PROCPU_INT_S  0
+
+#define GPIO_PCPU_NMI_INT_REG          (DR_REG_GPIO_BASE + 0x60)
+/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_PROCPU_NMI_INT  0x03FFFFFF
+#define GPIO_PROCPU_NMI_INT_M  ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S))
+#define GPIO_PROCPU_NMI_INT_V  0x3FFFFFF
+#define GPIO_PROCPU_NMI_INT_S  0
+
+#define GPIO_CPUSDIO_INT_REG          (DR_REG_GPIO_BASE + 0x64)
+/* GPIO_SDIO_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_SDIO_INT  0x03FFFFFF
+#define GPIO_SDIO_INT_M  ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S))
+#define GPIO_SDIO_INT_V  0x3FFFFFF
+#define GPIO_SDIO_INT_S  0
+
+#define GPIO_PIN0_REG          (DR_REG_GPIO_BASE + 0x74)
+/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN0_INT_ENA  0x0000001F
+#define GPIO_PIN0_INT_ENA_M  ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S))
+#define GPIO_PIN0_INT_ENA_V  0x1F
+#define GPIO_PIN0_INT_ENA_S  13
+/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN0_CONFIG  0x00000003
+#define GPIO_PIN0_CONFIG_M  ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S))
+#define GPIO_PIN0_CONFIG_V  0x3
+#define GPIO_PIN0_CONFIG_S  11
+/* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN0_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN0_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN0_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN0_WAKEUP_ENABLE_S  10
+/* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN0_INT_TYPE  0x00000007
+#define GPIO_PIN0_INT_TYPE_M  ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S))
+#define GPIO_PIN0_INT_TYPE_V  0x7
+#define GPIO_PIN0_INT_TYPE_S  7
+/* GPIO_PIN0_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN0_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN0_SYNC1_BYPASS_M  ((GPIO_PIN0_SYNC1_BYPASS_V)<<(GPIO_PIN0_SYNC1_BYPASS_S))
+#define GPIO_PIN0_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN0_SYNC1_BYPASS_S  3
+/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN0_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN0_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN0_PAD_DRIVER_V  0x1
+#define GPIO_PIN0_PAD_DRIVER_S  2
+/* GPIO_PIN0_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN0_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN0_SYNC2_BYPASS_M  ((GPIO_PIN0_SYNC2_BYPASS_V)<<(GPIO_PIN0_SYNC2_BYPASS_S))
+#define GPIO_PIN0_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN0_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN1_REG          (DR_REG_GPIO_BASE + 0x78)
+/* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN1_INT_ENA  0x0000001F
+#define GPIO_PIN1_INT_ENA_M  ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S))
+#define GPIO_PIN1_INT_ENA_V  0x1F
+#define GPIO_PIN1_INT_ENA_S  13
+/* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN1_CONFIG  0x00000003
+#define GPIO_PIN1_CONFIG_M  ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S))
+#define GPIO_PIN1_CONFIG_V  0x3
+#define GPIO_PIN1_CONFIG_S  11
+/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN1_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN1_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN1_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN1_WAKEUP_ENABLE_S  10
+/* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN1_INT_TYPE  0x00000007
+#define GPIO_PIN1_INT_TYPE_M  ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S))
+#define GPIO_PIN1_INT_TYPE_V  0x7
+#define GPIO_PIN1_INT_TYPE_S  7
+/* GPIO_PIN1_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN1_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN1_SYNC1_BYPASS_M  ((GPIO_PIN1_SYNC1_BYPASS_V)<<(GPIO_PIN1_SYNC1_BYPASS_S))
+#define GPIO_PIN1_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN1_SYNC1_BYPASS_S  3
+/* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN1_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN1_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN1_PAD_DRIVER_V  0x1
+#define GPIO_PIN1_PAD_DRIVER_S  2
+/* GPIO_PIN1_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN1_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN1_SYNC2_BYPASS_M  ((GPIO_PIN1_SYNC2_BYPASS_V)<<(GPIO_PIN1_SYNC2_BYPASS_S))
+#define GPIO_PIN1_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN1_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN2_REG          (DR_REG_GPIO_BASE + 0x7C)
+/* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN2_INT_ENA  0x0000001F
+#define GPIO_PIN2_INT_ENA_M  ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S))
+#define GPIO_PIN2_INT_ENA_V  0x1F
+#define GPIO_PIN2_INT_ENA_S  13
+/* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN2_CONFIG  0x00000003
+#define GPIO_PIN2_CONFIG_M  ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S))
+#define GPIO_PIN2_CONFIG_V  0x3
+#define GPIO_PIN2_CONFIG_S  11
+/* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN2_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN2_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN2_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN2_WAKEUP_ENABLE_S  10
+/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN2_INT_TYPE  0x00000007
+#define GPIO_PIN2_INT_TYPE_M  ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S))
+#define GPIO_PIN2_INT_TYPE_V  0x7
+#define GPIO_PIN2_INT_TYPE_S  7
+/* GPIO_PIN2_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN2_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN2_SYNC1_BYPASS_M  ((GPIO_PIN2_SYNC1_BYPASS_V)<<(GPIO_PIN2_SYNC1_BYPASS_S))
+#define GPIO_PIN2_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN2_SYNC1_BYPASS_S  3
+/* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN2_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN2_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN2_PAD_DRIVER_V  0x1
+#define GPIO_PIN2_PAD_DRIVER_S  2
+/* GPIO_PIN2_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN2_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN2_SYNC2_BYPASS_M  ((GPIO_PIN2_SYNC2_BYPASS_V)<<(GPIO_PIN2_SYNC2_BYPASS_S))
+#define GPIO_PIN2_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN2_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN3_REG          (DR_REG_GPIO_BASE + 0x80)
+/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN3_INT_ENA  0x0000001F
+#define GPIO_PIN3_INT_ENA_M  ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S))
+#define GPIO_PIN3_INT_ENA_V  0x1F
+#define GPIO_PIN3_INT_ENA_S  13
+/* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN3_CONFIG  0x00000003
+#define GPIO_PIN3_CONFIG_M  ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S))
+#define GPIO_PIN3_CONFIG_V  0x3
+#define GPIO_PIN3_CONFIG_S  11
+/* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN3_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN3_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN3_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN3_WAKEUP_ENABLE_S  10
+/* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN3_INT_TYPE  0x00000007
+#define GPIO_PIN3_INT_TYPE_M  ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S))
+#define GPIO_PIN3_INT_TYPE_V  0x7
+#define GPIO_PIN3_INT_TYPE_S  7
+/* GPIO_PIN3_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN3_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN3_SYNC1_BYPASS_M  ((GPIO_PIN3_SYNC1_BYPASS_V)<<(GPIO_PIN3_SYNC1_BYPASS_S))
+#define GPIO_PIN3_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN3_SYNC1_BYPASS_S  3
+/* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN3_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN3_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN3_PAD_DRIVER_V  0x1
+#define GPIO_PIN3_PAD_DRIVER_S  2
+/* GPIO_PIN3_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN3_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN3_SYNC2_BYPASS_M  ((GPIO_PIN3_SYNC2_BYPASS_V)<<(GPIO_PIN3_SYNC2_BYPASS_S))
+#define GPIO_PIN3_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN3_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN4_REG          (DR_REG_GPIO_BASE + 0x84)
+/* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN4_INT_ENA  0x0000001F
+#define GPIO_PIN4_INT_ENA_M  ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S))
+#define GPIO_PIN4_INT_ENA_V  0x1F
+#define GPIO_PIN4_INT_ENA_S  13
+/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN4_CONFIG  0x00000003
+#define GPIO_PIN4_CONFIG_M  ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S))
+#define GPIO_PIN4_CONFIG_V  0x3
+#define GPIO_PIN4_CONFIG_S  11
+/* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN4_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN4_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN4_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN4_WAKEUP_ENABLE_S  10
+/* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN4_INT_TYPE  0x00000007
+#define GPIO_PIN4_INT_TYPE_M  ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S))
+#define GPIO_PIN4_INT_TYPE_V  0x7
+#define GPIO_PIN4_INT_TYPE_S  7
+/* GPIO_PIN4_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN4_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN4_SYNC1_BYPASS_M  ((GPIO_PIN4_SYNC1_BYPASS_V)<<(GPIO_PIN4_SYNC1_BYPASS_S))
+#define GPIO_PIN4_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN4_SYNC1_BYPASS_S  3
+/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN4_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN4_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN4_PAD_DRIVER_V  0x1
+#define GPIO_PIN4_PAD_DRIVER_S  2
+/* GPIO_PIN4_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN4_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN4_SYNC2_BYPASS_M  ((GPIO_PIN4_SYNC2_BYPASS_V)<<(GPIO_PIN4_SYNC2_BYPASS_S))
+#define GPIO_PIN4_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN4_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN5_REG          (DR_REG_GPIO_BASE + 0x88)
+/* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN5_INT_ENA  0x0000001F
+#define GPIO_PIN5_INT_ENA_M  ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S))
+#define GPIO_PIN5_INT_ENA_V  0x1F
+#define GPIO_PIN5_INT_ENA_S  13
+/* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN5_CONFIG  0x00000003
+#define GPIO_PIN5_CONFIG_M  ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S))
+#define GPIO_PIN5_CONFIG_V  0x3
+#define GPIO_PIN5_CONFIG_S  11
+/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN5_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN5_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN5_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN5_WAKEUP_ENABLE_S  10
+/* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN5_INT_TYPE  0x00000007
+#define GPIO_PIN5_INT_TYPE_M  ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S))
+#define GPIO_PIN5_INT_TYPE_V  0x7
+#define GPIO_PIN5_INT_TYPE_S  7
+/* GPIO_PIN5_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN5_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN5_SYNC1_BYPASS_M  ((GPIO_PIN5_SYNC1_BYPASS_V)<<(GPIO_PIN5_SYNC1_BYPASS_S))
+#define GPIO_PIN5_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN5_SYNC1_BYPASS_S  3
+/* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN5_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN5_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN5_PAD_DRIVER_V  0x1
+#define GPIO_PIN5_PAD_DRIVER_S  2
+/* GPIO_PIN5_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN5_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN5_SYNC2_BYPASS_M  ((GPIO_PIN5_SYNC2_BYPASS_V)<<(GPIO_PIN5_SYNC2_BYPASS_S))
+#define GPIO_PIN5_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN5_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN6_REG          (DR_REG_GPIO_BASE + 0x8C)
+/* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN6_INT_ENA  0x0000001F
+#define GPIO_PIN6_INT_ENA_M  ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S))
+#define GPIO_PIN6_INT_ENA_V  0x1F
+#define GPIO_PIN6_INT_ENA_S  13
+/* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN6_CONFIG  0x00000003
+#define GPIO_PIN6_CONFIG_M  ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S))
+#define GPIO_PIN6_CONFIG_V  0x3
+#define GPIO_PIN6_CONFIG_S  11
+/* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN6_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN6_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN6_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN6_WAKEUP_ENABLE_S  10
+/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN6_INT_TYPE  0x00000007
+#define GPIO_PIN6_INT_TYPE_M  ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S))
+#define GPIO_PIN6_INT_TYPE_V  0x7
+#define GPIO_PIN6_INT_TYPE_S  7
+/* GPIO_PIN6_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN6_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN6_SYNC1_BYPASS_M  ((GPIO_PIN6_SYNC1_BYPASS_V)<<(GPIO_PIN6_SYNC1_BYPASS_S))
+#define GPIO_PIN6_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN6_SYNC1_BYPASS_S  3
+/* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN6_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN6_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN6_PAD_DRIVER_V  0x1
+#define GPIO_PIN6_PAD_DRIVER_S  2
+/* GPIO_PIN6_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN6_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN6_SYNC2_BYPASS_M  ((GPIO_PIN6_SYNC2_BYPASS_V)<<(GPIO_PIN6_SYNC2_BYPASS_S))
+#define GPIO_PIN6_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN6_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN7_REG          (DR_REG_GPIO_BASE + 0x90)
+/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN7_INT_ENA  0x0000001F
+#define GPIO_PIN7_INT_ENA_M  ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S))
+#define GPIO_PIN7_INT_ENA_V  0x1F
+#define GPIO_PIN7_INT_ENA_S  13
+/* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN7_CONFIG  0x00000003
+#define GPIO_PIN7_CONFIG_M  ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S))
+#define GPIO_PIN7_CONFIG_V  0x3
+#define GPIO_PIN7_CONFIG_S  11
+/* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN7_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN7_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN7_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN7_WAKEUP_ENABLE_S  10
+/* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN7_INT_TYPE  0x00000007
+#define GPIO_PIN7_INT_TYPE_M  ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S))
+#define GPIO_PIN7_INT_TYPE_V  0x7
+#define GPIO_PIN7_INT_TYPE_S  7
+/* GPIO_PIN7_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN7_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN7_SYNC1_BYPASS_M  ((GPIO_PIN7_SYNC1_BYPASS_V)<<(GPIO_PIN7_SYNC1_BYPASS_S))
+#define GPIO_PIN7_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN7_SYNC1_BYPASS_S  3
+/* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN7_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN7_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN7_PAD_DRIVER_V  0x1
+#define GPIO_PIN7_PAD_DRIVER_S  2
+/* GPIO_PIN7_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN7_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN7_SYNC2_BYPASS_M  ((GPIO_PIN7_SYNC2_BYPASS_V)<<(GPIO_PIN7_SYNC2_BYPASS_S))
+#define GPIO_PIN7_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN7_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN8_REG          (DR_REG_GPIO_BASE + 0x94)
+/* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN8_INT_ENA  0x0000001F
+#define GPIO_PIN8_INT_ENA_M  ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S))
+#define GPIO_PIN8_INT_ENA_V  0x1F
+#define GPIO_PIN8_INT_ENA_S  13
+/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN8_CONFIG  0x00000003
+#define GPIO_PIN8_CONFIG_M  ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S))
+#define GPIO_PIN8_CONFIG_V  0x3
+#define GPIO_PIN8_CONFIG_S  11
+/* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN8_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN8_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN8_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN8_WAKEUP_ENABLE_S  10
+/* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN8_INT_TYPE  0x00000007
+#define GPIO_PIN8_INT_TYPE_M  ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S))
+#define GPIO_PIN8_INT_TYPE_V  0x7
+#define GPIO_PIN8_INT_TYPE_S  7
+/* GPIO_PIN8_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN8_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN8_SYNC1_BYPASS_M  ((GPIO_PIN8_SYNC1_BYPASS_V)<<(GPIO_PIN8_SYNC1_BYPASS_S))
+#define GPIO_PIN8_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN8_SYNC1_BYPASS_S  3
+/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN8_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN8_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN8_PAD_DRIVER_V  0x1
+#define GPIO_PIN8_PAD_DRIVER_S  2
+/* GPIO_PIN8_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN8_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN8_SYNC2_BYPASS_M  ((GPIO_PIN8_SYNC2_BYPASS_V)<<(GPIO_PIN8_SYNC2_BYPASS_S))
+#define GPIO_PIN8_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN8_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN9_REG          (DR_REG_GPIO_BASE + 0x98)
+/* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN9_INT_ENA  0x0000001F
+#define GPIO_PIN9_INT_ENA_M  ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S))
+#define GPIO_PIN9_INT_ENA_V  0x1F
+#define GPIO_PIN9_INT_ENA_S  13
+/* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN9_CONFIG  0x00000003
+#define GPIO_PIN9_CONFIG_M  ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S))
+#define GPIO_PIN9_CONFIG_V  0x3
+#define GPIO_PIN9_CONFIG_S  11
+/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN9_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN9_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN9_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN9_WAKEUP_ENABLE_S  10
+/* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN9_INT_TYPE  0x00000007
+#define GPIO_PIN9_INT_TYPE_M  ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S))
+#define GPIO_PIN9_INT_TYPE_V  0x7
+#define GPIO_PIN9_INT_TYPE_S  7
+/* GPIO_PIN9_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN9_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN9_SYNC1_BYPASS_M  ((GPIO_PIN9_SYNC1_BYPASS_V)<<(GPIO_PIN9_SYNC1_BYPASS_S))
+#define GPIO_PIN9_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN9_SYNC1_BYPASS_S  3
+/* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN9_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN9_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN9_PAD_DRIVER_V  0x1
+#define GPIO_PIN9_PAD_DRIVER_S  2
+/* GPIO_PIN9_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN9_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN9_SYNC2_BYPASS_M  ((GPIO_PIN9_SYNC2_BYPASS_V)<<(GPIO_PIN9_SYNC2_BYPASS_S))
+#define GPIO_PIN9_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN9_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN10_REG          (DR_REG_GPIO_BASE + 0x9C)
+/* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN10_INT_ENA  0x0000001F
+#define GPIO_PIN10_INT_ENA_M  ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S))
+#define GPIO_PIN10_INT_ENA_V  0x1F
+#define GPIO_PIN10_INT_ENA_S  13
+/* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN10_CONFIG  0x00000003
+#define GPIO_PIN10_CONFIG_M  ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S))
+#define GPIO_PIN10_CONFIG_V  0x3
+#define GPIO_PIN10_CONFIG_S  11
+/* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN10_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN10_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN10_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN10_WAKEUP_ENABLE_S  10
+/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN10_INT_TYPE  0x00000007
+#define GPIO_PIN10_INT_TYPE_M  ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S))
+#define GPIO_PIN10_INT_TYPE_V  0x7
+#define GPIO_PIN10_INT_TYPE_S  7
+/* GPIO_PIN10_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN10_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN10_SYNC1_BYPASS_M  ((GPIO_PIN10_SYNC1_BYPASS_V)<<(GPIO_PIN10_SYNC1_BYPASS_S))
+#define GPIO_PIN10_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN10_SYNC1_BYPASS_S  3
+/* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN10_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN10_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN10_PAD_DRIVER_V  0x1
+#define GPIO_PIN10_PAD_DRIVER_S  2
+/* GPIO_PIN10_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN10_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN10_SYNC2_BYPASS_M  ((GPIO_PIN10_SYNC2_BYPASS_V)<<(GPIO_PIN10_SYNC2_BYPASS_S))
+#define GPIO_PIN10_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN10_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN11_REG          (DR_REG_GPIO_BASE + 0xA0)
+/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN11_INT_ENA  0x0000001F
+#define GPIO_PIN11_INT_ENA_M  ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S))
+#define GPIO_PIN11_INT_ENA_V  0x1F
+#define GPIO_PIN11_INT_ENA_S  13
+/* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN11_CONFIG  0x00000003
+#define GPIO_PIN11_CONFIG_M  ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S))
+#define GPIO_PIN11_CONFIG_V  0x3
+#define GPIO_PIN11_CONFIG_S  11
+/* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN11_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN11_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN11_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN11_WAKEUP_ENABLE_S  10
+/* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN11_INT_TYPE  0x00000007
+#define GPIO_PIN11_INT_TYPE_M  ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S))
+#define GPIO_PIN11_INT_TYPE_V  0x7
+#define GPIO_PIN11_INT_TYPE_S  7
+/* GPIO_PIN11_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN11_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN11_SYNC1_BYPASS_M  ((GPIO_PIN11_SYNC1_BYPASS_V)<<(GPIO_PIN11_SYNC1_BYPASS_S))
+#define GPIO_PIN11_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN11_SYNC1_BYPASS_S  3
+/* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN11_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN11_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN11_PAD_DRIVER_V  0x1
+#define GPIO_PIN11_PAD_DRIVER_S  2
+/* GPIO_PIN11_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN11_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN11_SYNC2_BYPASS_M  ((GPIO_PIN11_SYNC2_BYPASS_V)<<(GPIO_PIN11_SYNC2_BYPASS_S))
+#define GPIO_PIN11_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN11_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN12_REG          (DR_REG_GPIO_BASE + 0xA4)
+/* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN12_INT_ENA  0x0000001F
+#define GPIO_PIN12_INT_ENA_M  ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S))
+#define GPIO_PIN12_INT_ENA_V  0x1F
+#define GPIO_PIN12_INT_ENA_S  13
+/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN12_CONFIG  0x00000003
+#define GPIO_PIN12_CONFIG_M  ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S))
+#define GPIO_PIN12_CONFIG_V  0x3
+#define GPIO_PIN12_CONFIG_S  11
+/* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN12_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN12_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN12_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN12_WAKEUP_ENABLE_S  10
+/* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN12_INT_TYPE  0x00000007
+#define GPIO_PIN12_INT_TYPE_M  ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S))
+#define GPIO_PIN12_INT_TYPE_V  0x7
+#define GPIO_PIN12_INT_TYPE_S  7
+/* GPIO_PIN12_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN12_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN12_SYNC1_BYPASS_M  ((GPIO_PIN12_SYNC1_BYPASS_V)<<(GPIO_PIN12_SYNC1_BYPASS_S))
+#define GPIO_PIN12_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN12_SYNC1_BYPASS_S  3
+/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN12_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN12_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN12_PAD_DRIVER_V  0x1
+#define GPIO_PIN12_PAD_DRIVER_S  2
+/* GPIO_PIN12_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN12_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN12_SYNC2_BYPASS_M  ((GPIO_PIN12_SYNC2_BYPASS_V)<<(GPIO_PIN12_SYNC2_BYPASS_S))
+#define GPIO_PIN12_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN12_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN13_REG          (DR_REG_GPIO_BASE + 0xA8)
+/* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN13_INT_ENA  0x0000001F
+#define GPIO_PIN13_INT_ENA_M  ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S))
+#define GPIO_PIN13_INT_ENA_V  0x1F
+#define GPIO_PIN13_INT_ENA_S  13
+/* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN13_CONFIG  0x00000003
+#define GPIO_PIN13_CONFIG_M  ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S))
+#define GPIO_PIN13_CONFIG_V  0x3
+#define GPIO_PIN13_CONFIG_S  11
+/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN13_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN13_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN13_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN13_WAKEUP_ENABLE_S  10
+/* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN13_INT_TYPE  0x00000007
+#define GPIO_PIN13_INT_TYPE_M  ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S))
+#define GPIO_PIN13_INT_TYPE_V  0x7
+#define GPIO_PIN13_INT_TYPE_S  7
+/* GPIO_PIN13_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN13_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN13_SYNC1_BYPASS_M  ((GPIO_PIN13_SYNC1_BYPASS_V)<<(GPIO_PIN13_SYNC1_BYPASS_S))
+#define GPIO_PIN13_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN13_SYNC1_BYPASS_S  3
+/* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN13_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN13_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN13_PAD_DRIVER_V  0x1
+#define GPIO_PIN13_PAD_DRIVER_S  2
+/* GPIO_PIN13_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN13_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN13_SYNC2_BYPASS_M  ((GPIO_PIN13_SYNC2_BYPASS_V)<<(GPIO_PIN13_SYNC2_BYPASS_S))
+#define GPIO_PIN13_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN13_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN14_REG          (DR_REG_GPIO_BASE + 0xAC)
+/* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN14_INT_ENA  0x0000001F
+#define GPIO_PIN14_INT_ENA_M  ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S))
+#define GPIO_PIN14_INT_ENA_V  0x1F
+#define GPIO_PIN14_INT_ENA_S  13
+/* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN14_CONFIG  0x00000003
+#define GPIO_PIN14_CONFIG_M  ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S))
+#define GPIO_PIN14_CONFIG_V  0x3
+#define GPIO_PIN14_CONFIG_S  11
+/* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN14_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN14_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN14_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN14_WAKEUP_ENABLE_S  10
+/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN14_INT_TYPE  0x00000007
+#define GPIO_PIN14_INT_TYPE_M  ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S))
+#define GPIO_PIN14_INT_TYPE_V  0x7
+#define GPIO_PIN14_INT_TYPE_S  7
+/* GPIO_PIN14_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN14_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN14_SYNC1_BYPASS_M  ((GPIO_PIN14_SYNC1_BYPASS_V)<<(GPIO_PIN14_SYNC1_BYPASS_S))
+#define GPIO_PIN14_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN14_SYNC1_BYPASS_S  3
+/* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN14_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN14_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN14_PAD_DRIVER_V  0x1
+#define GPIO_PIN14_PAD_DRIVER_S  2
+/* GPIO_PIN14_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN14_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN14_SYNC2_BYPASS_M  ((GPIO_PIN14_SYNC2_BYPASS_V)<<(GPIO_PIN14_SYNC2_BYPASS_S))
+#define GPIO_PIN14_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN14_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN15_REG          (DR_REG_GPIO_BASE + 0xB0)
+/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN15_INT_ENA  0x0000001F
+#define GPIO_PIN15_INT_ENA_M  ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S))
+#define GPIO_PIN15_INT_ENA_V  0x1F
+#define GPIO_PIN15_INT_ENA_S  13
+/* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN15_CONFIG  0x00000003
+#define GPIO_PIN15_CONFIG_M  ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S))
+#define GPIO_PIN15_CONFIG_V  0x3
+#define GPIO_PIN15_CONFIG_S  11
+/* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN15_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN15_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN15_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN15_WAKEUP_ENABLE_S  10
+/* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN15_INT_TYPE  0x00000007
+#define GPIO_PIN15_INT_TYPE_M  ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S))
+#define GPIO_PIN15_INT_TYPE_V  0x7
+#define GPIO_PIN15_INT_TYPE_S  7
+/* GPIO_PIN15_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN15_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN15_SYNC1_BYPASS_M  ((GPIO_PIN15_SYNC1_BYPASS_V)<<(GPIO_PIN15_SYNC1_BYPASS_S))
+#define GPIO_PIN15_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN15_SYNC1_BYPASS_S  3
+/* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN15_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN15_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN15_PAD_DRIVER_V  0x1
+#define GPIO_PIN15_PAD_DRIVER_S  2
+/* GPIO_PIN15_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN15_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN15_SYNC2_BYPASS_M  ((GPIO_PIN15_SYNC2_BYPASS_V)<<(GPIO_PIN15_SYNC2_BYPASS_S))
+#define GPIO_PIN15_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN15_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN16_REG          (DR_REG_GPIO_BASE + 0xB4)
+/* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN16_INT_ENA  0x0000001F
+#define GPIO_PIN16_INT_ENA_M  ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S))
+#define GPIO_PIN16_INT_ENA_V  0x1F
+#define GPIO_PIN16_INT_ENA_S  13
+/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN16_CONFIG  0x00000003
+#define GPIO_PIN16_CONFIG_M  ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S))
+#define GPIO_PIN16_CONFIG_V  0x3
+#define GPIO_PIN16_CONFIG_S  11
+/* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN16_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN16_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN16_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN16_WAKEUP_ENABLE_S  10
+/* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN16_INT_TYPE  0x00000007
+#define GPIO_PIN16_INT_TYPE_M  ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S))
+#define GPIO_PIN16_INT_TYPE_V  0x7
+#define GPIO_PIN16_INT_TYPE_S  7
+/* GPIO_PIN16_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN16_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN16_SYNC1_BYPASS_M  ((GPIO_PIN16_SYNC1_BYPASS_V)<<(GPIO_PIN16_SYNC1_BYPASS_S))
+#define GPIO_PIN16_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN16_SYNC1_BYPASS_S  3
+/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN16_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN16_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN16_PAD_DRIVER_V  0x1
+#define GPIO_PIN16_PAD_DRIVER_S  2
+/* GPIO_PIN16_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN16_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN16_SYNC2_BYPASS_M  ((GPIO_PIN16_SYNC2_BYPASS_V)<<(GPIO_PIN16_SYNC2_BYPASS_S))
+#define GPIO_PIN16_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN16_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN17_REG          (DR_REG_GPIO_BASE + 0xB8)
+/* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN17_INT_ENA  0x0000001F
+#define GPIO_PIN17_INT_ENA_M  ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S))
+#define GPIO_PIN17_INT_ENA_V  0x1F
+#define GPIO_PIN17_INT_ENA_S  13
+/* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN17_CONFIG  0x00000003
+#define GPIO_PIN17_CONFIG_M  ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S))
+#define GPIO_PIN17_CONFIG_V  0x3
+#define GPIO_PIN17_CONFIG_S  11
+/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN17_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN17_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN17_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN17_WAKEUP_ENABLE_S  10
+/* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN17_INT_TYPE  0x00000007
+#define GPIO_PIN17_INT_TYPE_M  ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S))
+#define GPIO_PIN17_INT_TYPE_V  0x7
+#define GPIO_PIN17_INT_TYPE_S  7
+/* GPIO_PIN17_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN17_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN17_SYNC1_BYPASS_M  ((GPIO_PIN17_SYNC1_BYPASS_V)<<(GPIO_PIN17_SYNC1_BYPASS_S))
+#define GPIO_PIN17_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN17_SYNC1_BYPASS_S  3
+/* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN17_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN17_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN17_PAD_DRIVER_V  0x1
+#define GPIO_PIN17_PAD_DRIVER_S  2
+/* GPIO_PIN17_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN17_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN17_SYNC2_BYPASS_M  ((GPIO_PIN17_SYNC2_BYPASS_V)<<(GPIO_PIN17_SYNC2_BYPASS_S))
+#define GPIO_PIN17_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN17_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN18_REG          (DR_REG_GPIO_BASE + 0xBC)
+/* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN18_INT_ENA  0x0000001F
+#define GPIO_PIN18_INT_ENA_M  ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S))
+#define GPIO_PIN18_INT_ENA_V  0x1F
+#define GPIO_PIN18_INT_ENA_S  13
+/* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN18_CONFIG  0x00000003
+#define GPIO_PIN18_CONFIG_M  ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S))
+#define GPIO_PIN18_CONFIG_V  0x3
+#define GPIO_PIN18_CONFIG_S  11
+/* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN18_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN18_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN18_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN18_WAKEUP_ENABLE_S  10
+/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN18_INT_TYPE  0x00000007
+#define GPIO_PIN18_INT_TYPE_M  ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S))
+#define GPIO_PIN18_INT_TYPE_V  0x7
+#define GPIO_PIN18_INT_TYPE_S  7
+/* GPIO_PIN18_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN18_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN18_SYNC1_BYPASS_M  ((GPIO_PIN18_SYNC1_BYPASS_V)<<(GPIO_PIN18_SYNC1_BYPASS_S))
+#define GPIO_PIN18_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN18_SYNC1_BYPASS_S  3
+/* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN18_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN18_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN18_PAD_DRIVER_V  0x1
+#define GPIO_PIN18_PAD_DRIVER_S  2
+/* GPIO_PIN18_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN18_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN18_SYNC2_BYPASS_M  ((GPIO_PIN18_SYNC2_BYPASS_V)<<(GPIO_PIN18_SYNC2_BYPASS_S))
+#define GPIO_PIN18_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN18_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN19_REG          (DR_REG_GPIO_BASE + 0xC0)
+/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN19_INT_ENA  0x0000001F
+#define GPIO_PIN19_INT_ENA_M  ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S))
+#define GPIO_PIN19_INT_ENA_V  0x1F
+#define GPIO_PIN19_INT_ENA_S  13
+/* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN19_CONFIG  0x00000003
+#define GPIO_PIN19_CONFIG_M  ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S))
+#define GPIO_PIN19_CONFIG_V  0x3
+#define GPIO_PIN19_CONFIG_S  11
+/* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN19_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN19_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN19_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN19_WAKEUP_ENABLE_S  10
+/* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN19_INT_TYPE  0x00000007
+#define GPIO_PIN19_INT_TYPE_M  ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S))
+#define GPIO_PIN19_INT_TYPE_V  0x7
+#define GPIO_PIN19_INT_TYPE_S  7
+/* GPIO_PIN19_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN19_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN19_SYNC1_BYPASS_M  ((GPIO_PIN19_SYNC1_BYPASS_V)<<(GPIO_PIN19_SYNC1_BYPASS_S))
+#define GPIO_PIN19_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN19_SYNC1_BYPASS_S  3
+/* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN19_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN19_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN19_PAD_DRIVER_V  0x1
+#define GPIO_PIN19_PAD_DRIVER_S  2
+/* GPIO_PIN19_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN19_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN19_SYNC2_BYPASS_M  ((GPIO_PIN19_SYNC2_BYPASS_V)<<(GPIO_PIN19_SYNC2_BYPASS_S))
+#define GPIO_PIN19_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN19_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN20_REG          (DR_REG_GPIO_BASE + 0xC4)
+/* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN20_INT_ENA  0x0000001F
+#define GPIO_PIN20_INT_ENA_M  ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S))
+#define GPIO_PIN20_INT_ENA_V  0x1F
+#define GPIO_PIN20_INT_ENA_S  13
+/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN20_CONFIG  0x00000003
+#define GPIO_PIN20_CONFIG_M  ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S))
+#define GPIO_PIN20_CONFIG_V  0x3
+#define GPIO_PIN20_CONFIG_S  11
+/* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN20_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN20_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN20_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN20_WAKEUP_ENABLE_S  10
+/* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN20_INT_TYPE  0x00000007
+#define GPIO_PIN20_INT_TYPE_M  ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S))
+#define GPIO_PIN20_INT_TYPE_V  0x7
+#define GPIO_PIN20_INT_TYPE_S  7
+/* GPIO_PIN20_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN20_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN20_SYNC1_BYPASS_M  ((GPIO_PIN20_SYNC1_BYPASS_V)<<(GPIO_PIN20_SYNC1_BYPASS_S))
+#define GPIO_PIN20_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN20_SYNC1_BYPASS_S  3
+/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN20_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN20_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN20_PAD_DRIVER_V  0x1
+#define GPIO_PIN20_PAD_DRIVER_S  2
+/* GPIO_PIN20_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN20_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN20_SYNC2_BYPASS_M  ((GPIO_PIN20_SYNC2_BYPASS_V)<<(GPIO_PIN20_SYNC2_BYPASS_S))
+#define GPIO_PIN20_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN20_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN21_REG          (DR_REG_GPIO_BASE + 0xC8)
+/* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN21_INT_ENA  0x0000001F
+#define GPIO_PIN21_INT_ENA_M  ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S))
+#define GPIO_PIN21_INT_ENA_V  0x1F
+#define GPIO_PIN21_INT_ENA_S  13
+/* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN21_CONFIG  0x00000003
+#define GPIO_PIN21_CONFIG_M  ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S))
+#define GPIO_PIN21_CONFIG_V  0x3
+#define GPIO_PIN21_CONFIG_S  11
+/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN21_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN21_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN21_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN21_WAKEUP_ENABLE_S  10
+/* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN21_INT_TYPE  0x00000007
+#define GPIO_PIN21_INT_TYPE_M  ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S))
+#define GPIO_PIN21_INT_TYPE_V  0x7
+#define GPIO_PIN21_INT_TYPE_S  7
+/* GPIO_PIN21_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN21_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN21_SYNC1_BYPASS_M  ((GPIO_PIN21_SYNC1_BYPASS_V)<<(GPIO_PIN21_SYNC1_BYPASS_S))
+#define GPIO_PIN21_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN21_SYNC1_BYPASS_S  3
+/* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN21_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN21_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN21_PAD_DRIVER_V  0x1
+#define GPIO_PIN21_PAD_DRIVER_S  2
+/* GPIO_PIN21_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN21_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN21_SYNC2_BYPASS_M  ((GPIO_PIN21_SYNC2_BYPASS_V)<<(GPIO_PIN21_SYNC2_BYPASS_S))
+#define GPIO_PIN21_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN21_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN22_REG          (DR_REG_GPIO_BASE + 0xCC)
+/* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN22_INT_ENA  0x0000001F
+#define GPIO_PIN22_INT_ENA_M  ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S))
+#define GPIO_PIN22_INT_ENA_V  0x1F
+#define GPIO_PIN22_INT_ENA_S  13
+/* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN22_CONFIG  0x00000003
+#define GPIO_PIN22_CONFIG_M  ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S))
+#define GPIO_PIN22_CONFIG_V  0x3
+#define GPIO_PIN22_CONFIG_S  11
+/* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN22_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN22_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN22_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN22_WAKEUP_ENABLE_S  10
+/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN22_INT_TYPE  0x00000007
+#define GPIO_PIN22_INT_TYPE_M  ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S))
+#define GPIO_PIN22_INT_TYPE_V  0x7
+#define GPIO_PIN22_INT_TYPE_S  7
+/* GPIO_PIN22_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN22_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN22_SYNC1_BYPASS_M  ((GPIO_PIN22_SYNC1_BYPASS_V)<<(GPIO_PIN22_SYNC1_BYPASS_S))
+#define GPIO_PIN22_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN22_SYNC1_BYPASS_S  3
+/* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN22_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN22_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN22_PAD_DRIVER_V  0x1
+#define GPIO_PIN22_PAD_DRIVER_S  2
+/* GPIO_PIN22_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN22_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN22_SYNC2_BYPASS_M  ((GPIO_PIN22_SYNC2_BYPASS_V)<<(GPIO_PIN22_SYNC2_BYPASS_S))
+#define GPIO_PIN22_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN22_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN23_REG          (DR_REG_GPIO_BASE + 0xD0)
+/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN23_INT_ENA  0x0000001F
+#define GPIO_PIN23_INT_ENA_M  ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S))
+#define GPIO_PIN23_INT_ENA_V  0x1F
+#define GPIO_PIN23_INT_ENA_S  13
+/* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN23_CONFIG  0x00000003
+#define GPIO_PIN23_CONFIG_M  ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S))
+#define GPIO_PIN23_CONFIG_V  0x3
+#define GPIO_PIN23_CONFIG_S  11
+/* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN23_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN23_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN23_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN23_WAKEUP_ENABLE_S  10
+/* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN23_INT_TYPE  0x00000007
+#define GPIO_PIN23_INT_TYPE_M  ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S))
+#define GPIO_PIN23_INT_TYPE_V  0x7
+#define GPIO_PIN23_INT_TYPE_S  7
+/* GPIO_PIN23_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN23_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN23_SYNC1_BYPASS_M  ((GPIO_PIN23_SYNC1_BYPASS_V)<<(GPIO_PIN23_SYNC1_BYPASS_S))
+#define GPIO_PIN23_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN23_SYNC1_BYPASS_S  3
+/* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN23_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN23_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN23_PAD_DRIVER_V  0x1
+#define GPIO_PIN23_PAD_DRIVER_S  2
+/* GPIO_PIN23_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN23_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN23_SYNC2_BYPASS_M  ((GPIO_PIN23_SYNC2_BYPASS_V)<<(GPIO_PIN23_SYNC2_BYPASS_S))
+#define GPIO_PIN23_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN23_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN24_REG          (DR_REG_GPIO_BASE + 0xD4)
+/* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN24_INT_ENA  0x0000001F
+#define GPIO_PIN24_INT_ENA_M  ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S))
+#define GPIO_PIN24_INT_ENA_V  0x1F
+#define GPIO_PIN24_INT_ENA_S  13
+/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN24_CONFIG  0x00000003
+#define GPIO_PIN24_CONFIG_M  ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S))
+#define GPIO_PIN24_CONFIG_V  0x3
+#define GPIO_PIN24_CONFIG_S  11
+/* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN24_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN24_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN24_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN24_WAKEUP_ENABLE_S  10
+/* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN24_INT_TYPE  0x00000007
+#define GPIO_PIN24_INT_TYPE_M  ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S))
+#define GPIO_PIN24_INT_TYPE_V  0x7
+#define GPIO_PIN24_INT_TYPE_S  7
+/* GPIO_PIN24_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN24_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN24_SYNC1_BYPASS_M  ((GPIO_PIN24_SYNC1_BYPASS_V)<<(GPIO_PIN24_SYNC1_BYPASS_S))
+#define GPIO_PIN24_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN24_SYNC1_BYPASS_S  3
+/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN24_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN24_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN24_PAD_DRIVER_V  0x1
+#define GPIO_PIN24_PAD_DRIVER_S  2
+/* GPIO_PIN24_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN24_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN24_SYNC2_BYPASS_M  ((GPIO_PIN24_SYNC2_BYPASS_V)<<(GPIO_PIN24_SYNC2_BYPASS_S))
+#define GPIO_PIN24_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN24_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN25_REG          (DR_REG_GPIO_BASE + 0xD8)
+/* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN25_INT_ENA  0x0000001F
+#define GPIO_PIN25_INT_ENA_M  ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S))
+#define GPIO_PIN25_INT_ENA_V  0x1F
+#define GPIO_PIN25_INT_ENA_S  13
+/* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN25_CONFIG  0x00000003
+#define GPIO_PIN25_CONFIG_M  ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S))
+#define GPIO_PIN25_CONFIG_V  0x3
+#define GPIO_PIN25_CONFIG_S  11
+/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN25_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN25_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN25_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN25_WAKEUP_ENABLE_S  10
+/* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN25_INT_TYPE  0x00000007
+#define GPIO_PIN25_INT_TYPE_M  ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S))
+#define GPIO_PIN25_INT_TYPE_V  0x7
+#define GPIO_PIN25_INT_TYPE_S  7
+/* GPIO_PIN25_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN25_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN25_SYNC1_BYPASS_M  ((GPIO_PIN25_SYNC1_BYPASS_V)<<(GPIO_PIN25_SYNC1_BYPASS_S))
+#define GPIO_PIN25_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN25_SYNC1_BYPASS_S  3
+/* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN25_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN25_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN25_PAD_DRIVER_V  0x1
+#define GPIO_PIN25_PAD_DRIVER_S  2
+/* GPIO_PIN25_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN25_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN25_SYNC2_BYPASS_M  ((GPIO_PIN25_SYNC2_BYPASS_V)<<(GPIO_PIN25_SYNC2_BYPASS_S))
+#define GPIO_PIN25_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN25_SYNC2_BYPASS_S  0
+
+#define GPIO_STATUS_NEXT_REG          (DR_REG_GPIO_BASE + 0x14C)
+/* GPIO_STATUS_INTERRUPT_NEXT : RO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_STATUS_INTERRUPT_NEXT  0x03FFFFFF
+#define GPIO_STATUS_INTERRUPT_NEXT_M  ((GPIO_STATUS_INTERRUPT_NEXT_V)<<(GPIO_STATUS_INTERRUPT_NEXT_S))
+#define GPIO_STATUS_INTERRUPT_NEXT_V  0x3FFFFFF
+#define GPIO_STATUS_INTERRUPT_NEXT_S  0
+
+#define GPIO_FUNC0_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x154)
+/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG0_IN_SEL  (BIT(6))
+#define GPIO_SIG0_IN_SEL_M  (BIT(6))
+#define GPIO_SIG0_IN_SEL_V  0x1
+#define GPIO_SIG0_IN_SEL_S  6
+/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC0_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC0_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC0_IN_INV_SEL_V  0x1
+#define GPIO_FUNC0_IN_INV_SEL_S  5
+/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC0_IN_SEL  0x0000001F
+#define GPIO_FUNC0_IN_SEL_M  ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S))
+#define GPIO_FUNC0_IN_SEL_V  0x1F
+#define GPIO_FUNC0_IN_SEL_S  0
+
+#define GPIO_FUNC1_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x158)
+/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG1_IN_SEL  (BIT(6))
+#define GPIO_SIG1_IN_SEL_M  (BIT(6))
+#define GPIO_SIG1_IN_SEL_V  0x1
+#define GPIO_SIG1_IN_SEL_S  6
+/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC1_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC1_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC1_IN_INV_SEL_V  0x1
+#define GPIO_FUNC1_IN_INV_SEL_S  5
+/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC1_IN_SEL  0x0000001F
+#define GPIO_FUNC1_IN_SEL_M  ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S))
+#define GPIO_FUNC1_IN_SEL_V  0x1F
+#define GPIO_FUNC1_IN_SEL_S  0
+
+#define GPIO_FUNC2_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x15C)
+/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG2_IN_SEL  (BIT(6))
+#define GPIO_SIG2_IN_SEL_M  (BIT(6))
+#define GPIO_SIG2_IN_SEL_V  0x1
+#define GPIO_SIG2_IN_SEL_S  6
+/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC2_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC2_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC2_IN_INV_SEL_V  0x1
+#define GPIO_FUNC2_IN_INV_SEL_S  5
+/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC2_IN_SEL  0x0000001F
+#define GPIO_FUNC2_IN_SEL_M  ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S))
+#define GPIO_FUNC2_IN_SEL_V  0x1F
+#define GPIO_FUNC2_IN_SEL_S  0
+
+#define GPIO_FUNC3_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x160)
+/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG3_IN_SEL  (BIT(6))
+#define GPIO_SIG3_IN_SEL_M  (BIT(6))
+#define GPIO_SIG3_IN_SEL_V  0x1
+#define GPIO_SIG3_IN_SEL_S  6
+/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC3_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC3_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC3_IN_INV_SEL_V  0x1
+#define GPIO_FUNC3_IN_INV_SEL_S  5
+/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC3_IN_SEL  0x0000001F
+#define GPIO_FUNC3_IN_SEL_M  ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S))
+#define GPIO_FUNC3_IN_SEL_V  0x1F
+#define GPIO_FUNC3_IN_SEL_S  0
+
+#define GPIO_FUNC4_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x164)
+/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG4_IN_SEL  (BIT(6))
+#define GPIO_SIG4_IN_SEL_M  (BIT(6))
+#define GPIO_SIG4_IN_SEL_V  0x1
+#define GPIO_SIG4_IN_SEL_S  6
+/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC4_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC4_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC4_IN_INV_SEL_V  0x1
+#define GPIO_FUNC4_IN_INV_SEL_S  5
+/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC4_IN_SEL  0x0000001F
+#define GPIO_FUNC4_IN_SEL_M  ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S))
+#define GPIO_FUNC4_IN_SEL_V  0x1F
+#define GPIO_FUNC4_IN_SEL_S  0
+
+#define GPIO_FUNC5_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x168)
+/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG5_IN_SEL  (BIT(6))
+#define GPIO_SIG5_IN_SEL_M  (BIT(6))
+#define GPIO_SIG5_IN_SEL_V  0x1
+#define GPIO_SIG5_IN_SEL_S  6
+/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC5_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC5_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC5_IN_INV_SEL_V  0x1
+#define GPIO_FUNC5_IN_INV_SEL_S  5
+/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC5_IN_SEL  0x0000001F
+#define GPIO_FUNC5_IN_SEL_M  ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S))
+#define GPIO_FUNC5_IN_SEL_V  0x1F
+#define GPIO_FUNC5_IN_SEL_S  0
+
+#define GPIO_FUNC6_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x16C)
+/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG6_IN_SEL  (BIT(6))
+#define GPIO_SIG6_IN_SEL_M  (BIT(6))
+#define GPIO_SIG6_IN_SEL_V  0x1
+#define GPIO_SIG6_IN_SEL_S  6
+/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC6_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC6_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC6_IN_INV_SEL_V  0x1
+#define GPIO_FUNC6_IN_INV_SEL_S  5
+/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC6_IN_SEL  0x0000001F
+#define GPIO_FUNC6_IN_SEL_M  ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S))
+#define GPIO_FUNC6_IN_SEL_V  0x1F
+#define GPIO_FUNC6_IN_SEL_S  0
+
+#define GPIO_FUNC7_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x170)
+/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG7_IN_SEL  (BIT(6))
+#define GPIO_SIG7_IN_SEL_M  (BIT(6))
+#define GPIO_SIG7_IN_SEL_V  0x1
+#define GPIO_SIG7_IN_SEL_S  6
+/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC7_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC7_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC7_IN_INV_SEL_V  0x1
+#define GPIO_FUNC7_IN_INV_SEL_S  5
+/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC7_IN_SEL  0x0000001F
+#define GPIO_FUNC7_IN_SEL_M  ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S))
+#define GPIO_FUNC7_IN_SEL_V  0x1F
+#define GPIO_FUNC7_IN_SEL_S  0
+
+#define GPIO_FUNC8_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x174)
+/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG8_IN_SEL  (BIT(6))
+#define GPIO_SIG8_IN_SEL_M  (BIT(6))
+#define GPIO_SIG8_IN_SEL_V  0x1
+#define GPIO_SIG8_IN_SEL_S  6
+/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC8_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC8_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC8_IN_INV_SEL_V  0x1
+#define GPIO_FUNC8_IN_INV_SEL_S  5
+/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC8_IN_SEL  0x0000001F
+#define GPIO_FUNC8_IN_SEL_M  ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S))
+#define GPIO_FUNC8_IN_SEL_V  0x1F
+#define GPIO_FUNC8_IN_SEL_S  0
+
+#define GPIO_FUNC9_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x178)
+/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG9_IN_SEL  (BIT(6))
+#define GPIO_SIG9_IN_SEL_M  (BIT(6))
+#define GPIO_SIG9_IN_SEL_V  0x1
+#define GPIO_SIG9_IN_SEL_S  6
+/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC9_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC9_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC9_IN_INV_SEL_V  0x1
+#define GPIO_FUNC9_IN_INV_SEL_S  5
+/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC9_IN_SEL  0x0000001F
+#define GPIO_FUNC9_IN_SEL_M  ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S))
+#define GPIO_FUNC9_IN_SEL_V  0x1F
+#define GPIO_FUNC9_IN_SEL_S  0
+
+#define GPIO_FUNC10_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x17C)
+/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG10_IN_SEL  (BIT(6))
+#define GPIO_SIG10_IN_SEL_M  (BIT(6))
+#define GPIO_SIG10_IN_SEL_V  0x1
+#define GPIO_SIG10_IN_SEL_S  6
+/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC10_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC10_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC10_IN_INV_SEL_V  0x1
+#define GPIO_FUNC10_IN_INV_SEL_S  5
+/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC10_IN_SEL  0x0000001F
+#define GPIO_FUNC10_IN_SEL_M  ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S))
+#define GPIO_FUNC10_IN_SEL_V  0x1F
+#define GPIO_FUNC10_IN_SEL_S  0
+
+#define GPIO_FUNC11_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x180)
+/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG11_IN_SEL  (BIT(6))
+#define GPIO_SIG11_IN_SEL_M  (BIT(6))
+#define GPIO_SIG11_IN_SEL_V  0x1
+#define GPIO_SIG11_IN_SEL_S  6
+/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC11_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC11_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC11_IN_INV_SEL_V  0x1
+#define GPIO_FUNC11_IN_INV_SEL_S  5
+/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC11_IN_SEL  0x0000001F
+#define GPIO_FUNC11_IN_SEL_M  ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S))
+#define GPIO_FUNC11_IN_SEL_V  0x1F
+#define GPIO_FUNC11_IN_SEL_S  0
+
+#define GPIO_FUNC12_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x184)
+/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG12_IN_SEL  (BIT(6))
+#define GPIO_SIG12_IN_SEL_M  (BIT(6))
+#define GPIO_SIG12_IN_SEL_V  0x1
+#define GPIO_SIG12_IN_SEL_S  6
+/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC12_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC12_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC12_IN_INV_SEL_V  0x1
+#define GPIO_FUNC12_IN_INV_SEL_S  5
+/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC12_IN_SEL  0x0000001F
+#define GPIO_FUNC12_IN_SEL_M  ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S))
+#define GPIO_FUNC12_IN_SEL_V  0x1F
+#define GPIO_FUNC12_IN_SEL_S  0
+
+#define GPIO_FUNC13_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x188)
+/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG13_IN_SEL  (BIT(6))
+#define GPIO_SIG13_IN_SEL_M  (BIT(6))
+#define GPIO_SIG13_IN_SEL_V  0x1
+#define GPIO_SIG13_IN_SEL_S  6
+/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC13_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC13_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC13_IN_INV_SEL_V  0x1
+#define GPIO_FUNC13_IN_INV_SEL_S  5
+/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC13_IN_SEL  0x0000001F
+#define GPIO_FUNC13_IN_SEL_M  ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S))
+#define GPIO_FUNC13_IN_SEL_V  0x1F
+#define GPIO_FUNC13_IN_SEL_S  0
+
+#define GPIO_FUNC14_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x18C)
+/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG14_IN_SEL  (BIT(6))
+#define GPIO_SIG14_IN_SEL_M  (BIT(6))
+#define GPIO_SIG14_IN_SEL_V  0x1
+#define GPIO_SIG14_IN_SEL_S  6
+/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC14_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC14_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC14_IN_INV_SEL_V  0x1
+#define GPIO_FUNC14_IN_INV_SEL_S  5
+/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC14_IN_SEL  0x0000001F
+#define GPIO_FUNC14_IN_SEL_M  ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S))
+#define GPIO_FUNC14_IN_SEL_V  0x1F
+#define GPIO_FUNC14_IN_SEL_S  0
+
+#define GPIO_FUNC15_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x190)
+/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG15_IN_SEL  (BIT(6))
+#define GPIO_SIG15_IN_SEL_M  (BIT(6))
+#define GPIO_SIG15_IN_SEL_V  0x1
+#define GPIO_SIG15_IN_SEL_S  6
+/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC15_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC15_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC15_IN_INV_SEL_V  0x1
+#define GPIO_FUNC15_IN_INV_SEL_S  5
+/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC15_IN_SEL  0x0000001F
+#define GPIO_FUNC15_IN_SEL_M  ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S))
+#define GPIO_FUNC15_IN_SEL_V  0x1F
+#define GPIO_FUNC15_IN_SEL_S  0
+
+#define GPIO_FUNC16_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x194)
+/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG16_IN_SEL  (BIT(6))
+#define GPIO_SIG16_IN_SEL_M  (BIT(6))
+#define GPIO_SIG16_IN_SEL_V  0x1
+#define GPIO_SIG16_IN_SEL_S  6
+/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC16_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC16_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC16_IN_INV_SEL_V  0x1
+#define GPIO_FUNC16_IN_INV_SEL_S  5
+/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC16_IN_SEL  0x0000001F
+#define GPIO_FUNC16_IN_SEL_M  ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S))
+#define GPIO_FUNC16_IN_SEL_V  0x1F
+#define GPIO_FUNC16_IN_SEL_S  0
+
+#define GPIO_FUNC17_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x198)
+/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG17_IN_SEL  (BIT(6))
+#define GPIO_SIG17_IN_SEL_M  (BIT(6))
+#define GPIO_SIG17_IN_SEL_V  0x1
+#define GPIO_SIG17_IN_SEL_S  6
+/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC17_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC17_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC17_IN_INV_SEL_V  0x1
+#define GPIO_FUNC17_IN_INV_SEL_S  5
+/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC17_IN_SEL  0x0000001F
+#define GPIO_FUNC17_IN_SEL_M  ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S))
+#define GPIO_FUNC17_IN_SEL_V  0x1F
+#define GPIO_FUNC17_IN_SEL_S  0
+
+#define GPIO_FUNC18_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x19C)
+/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG18_IN_SEL  (BIT(6))
+#define GPIO_SIG18_IN_SEL_M  (BIT(6))
+#define GPIO_SIG18_IN_SEL_V  0x1
+#define GPIO_SIG18_IN_SEL_S  6
+/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC18_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC18_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC18_IN_INV_SEL_V  0x1
+#define GPIO_FUNC18_IN_INV_SEL_S  5
+/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC18_IN_SEL  0x0000001F
+#define GPIO_FUNC18_IN_SEL_M  ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S))
+#define GPIO_FUNC18_IN_SEL_V  0x1F
+#define GPIO_FUNC18_IN_SEL_S  0
+
+#define GPIO_FUNC19_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1A0)
+/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG19_IN_SEL  (BIT(6))
+#define GPIO_SIG19_IN_SEL_M  (BIT(6))
+#define GPIO_SIG19_IN_SEL_V  0x1
+#define GPIO_SIG19_IN_SEL_S  6
+/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC19_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC19_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC19_IN_INV_SEL_V  0x1
+#define GPIO_FUNC19_IN_INV_SEL_S  5
+/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC19_IN_SEL  0x0000001F
+#define GPIO_FUNC19_IN_SEL_M  ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S))
+#define GPIO_FUNC19_IN_SEL_V  0x1F
+#define GPIO_FUNC19_IN_SEL_S  0
+
+#define GPIO_FUNC20_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1A4)
+/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG20_IN_SEL  (BIT(6))
+#define GPIO_SIG20_IN_SEL_M  (BIT(6))
+#define GPIO_SIG20_IN_SEL_V  0x1
+#define GPIO_SIG20_IN_SEL_S  6
+/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC20_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC20_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC20_IN_INV_SEL_V  0x1
+#define GPIO_FUNC20_IN_INV_SEL_S  5
+/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC20_IN_SEL  0x0000001F
+#define GPIO_FUNC20_IN_SEL_M  ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S))
+#define GPIO_FUNC20_IN_SEL_V  0x1F
+#define GPIO_FUNC20_IN_SEL_S  0
+
+#define GPIO_FUNC21_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1A8)
+/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG21_IN_SEL  (BIT(6))
+#define GPIO_SIG21_IN_SEL_M  (BIT(6))
+#define GPIO_SIG21_IN_SEL_V  0x1
+#define GPIO_SIG21_IN_SEL_S  6
+/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC21_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC21_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC21_IN_INV_SEL_V  0x1
+#define GPIO_FUNC21_IN_INV_SEL_S  5
+/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC21_IN_SEL  0x0000001F
+#define GPIO_FUNC21_IN_SEL_M  ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S))
+#define GPIO_FUNC21_IN_SEL_V  0x1F
+#define GPIO_FUNC21_IN_SEL_S  0
+
+#define GPIO_FUNC22_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1AC)
+/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG22_IN_SEL  (BIT(6))
+#define GPIO_SIG22_IN_SEL_M  (BIT(6))
+#define GPIO_SIG22_IN_SEL_V  0x1
+#define GPIO_SIG22_IN_SEL_S  6
+/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC22_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC22_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC22_IN_INV_SEL_V  0x1
+#define GPIO_FUNC22_IN_INV_SEL_S  5
+/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC22_IN_SEL  0x0000001F
+#define GPIO_FUNC22_IN_SEL_M  ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S))
+#define GPIO_FUNC22_IN_SEL_V  0x1F
+#define GPIO_FUNC22_IN_SEL_S  0
+
+#define GPIO_FUNC23_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1B0)
+/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG23_IN_SEL  (BIT(6))
+#define GPIO_SIG23_IN_SEL_M  (BIT(6))
+#define GPIO_SIG23_IN_SEL_V  0x1
+#define GPIO_SIG23_IN_SEL_S  6
+/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC23_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC23_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC23_IN_INV_SEL_V  0x1
+#define GPIO_FUNC23_IN_INV_SEL_S  5
+/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC23_IN_SEL  0x0000001F
+#define GPIO_FUNC23_IN_SEL_M  ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S))
+#define GPIO_FUNC23_IN_SEL_V  0x1F
+#define GPIO_FUNC23_IN_SEL_S  0
+
+#define GPIO_FUNC24_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1B4)
+/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG24_IN_SEL  (BIT(6))
+#define GPIO_SIG24_IN_SEL_M  (BIT(6))
+#define GPIO_SIG24_IN_SEL_V  0x1
+#define GPIO_SIG24_IN_SEL_S  6
+/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC24_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC24_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC24_IN_INV_SEL_V  0x1
+#define GPIO_FUNC24_IN_INV_SEL_S  5
+/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC24_IN_SEL  0x0000001F
+#define GPIO_FUNC24_IN_SEL_M  ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S))
+#define GPIO_FUNC24_IN_SEL_V  0x1F
+#define GPIO_FUNC24_IN_SEL_S  0
+
+#define GPIO_FUNC25_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1B8)
+/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG25_IN_SEL  (BIT(6))
+#define GPIO_SIG25_IN_SEL_M  (BIT(6))
+#define GPIO_SIG25_IN_SEL_V  0x1
+#define GPIO_SIG25_IN_SEL_S  6
+/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC25_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC25_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC25_IN_INV_SEL_V  0x1
+#define GPIO_FUNC25_IN_INV_SEL_S  5
+/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC25_IN_SEL  0x0000001F
+#define GPIO_FUNC25_IN_SEL_M  ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S))
+#define GPIO_FUNC25_IN_SEL_V  0x1F
+#define GPIO_FUNC25_IN_SEL_S  0
+
+#define GPIO_FUNC26_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1BC)
+/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG26_IN_SEL  (BIT(6))
+#define GPIO_SIG26_IN_SEL_M  (BIT(6))
+#define GPIO_SIG26_IN_SEL_V  0x1
+#define GPIO_SIG26_IN_SEL_S  6
+/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC26_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC26_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC26_IN_INV_SEL_V  0x1
+#define GPIO_FUNC26_IN_INV_SEL_S  5
+/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC26_IN_SEL  0x0000001F
+#define GPIO_FUNC26_IN_SEL_M  ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S))
+#define GPIO_FUNC26_IN_SEL_V  0x1F
+#define GPIO_FUNC26_IN_SEL_S  0
+
+#define GPIO_FUNC27_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1C0)
+/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG27_IN_SEL  (BIT(6))
+#define GPIO_SIG27_IN_SEL_M  (BIT(6))
+#define GPIO_SIG27_IN_SEL_V  0x1
+#define GPIO_SIG27_IN_SEL_S  6
+/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC27_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC27_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC27_IN_INV_SEL_V  0x1
+#define GPIO_FUNC27_IN_INV_SEL_S  5
+/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC27_IN_SEL  0x0000001F
+#define GPIO_FUNC27_IN_SEL_M  ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S))
+#define GPIO_FUNC27_IN_SEL_V  0x1F
+#define GPIO_FUNC27_IN_SEL_S  0
+
+#define GPIO_FUNC28_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1C4)
+/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG28_IN_SEL  (BIT(6))
+#define GPIO_SIG28_IN_SEL_M  (BIT(6))
+#define GPIO_SIG28_IN_SEL_V  0x1
+#define GPIO_SIG28_IN_SEL_S  6
+/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC28_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC28_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC28_IN_INV_SEL_V  0x1
+#define GPIO_FUNC28_IN_INV_SEL_S  5
+/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC28_IN_SEL  0x0000001F
+#define GPIO_FUNC28_IN_SEL_M  ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S))
+#define GPIO_FUNC28_IN_SEL_V  0x1F
+#define GPIO_FUNC28_IN_SEL_S  0
+
+#define GPIO_FUNC29_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1C8)
+/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG29_IN_SEL  (BIT(6))
+#define GPIO_SIG29_IN_SEL_M  (BIT(6))
+#define GPIO_SIG29_IN_SEL_V  0x1
+#define GPIO_SIG29_IN_SEL_S  6
+/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC29_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC29_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC29_IN_INV_SEL_V  0x1
+#define GPIO_FUNC29_IN_INV_SEL_S  5
+/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC29_IN_SEL  0x0000001F
+#define GPIO_FUNC29_IN_SEL_M  ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S))
+#define GPIO_FUNC29_IN_SEL_V  0x1F
+#define GPIO_FUNC29_IN_SEL_S  0
+
+#define GPIO_FUNC30_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1CC)
+/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG30_IN_SEL  (BIT(6))
+#define GPIO_SIG30_IN_SEL_M  (BIT(6))
+#define GPIO_SIG30_IN_SEL_V  0x1
+#define GPIO_SIG30_IN_SEL_S  6
+/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC30_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC30_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC30_IN_INV_SEL_V  0x1
+#define GPIO_FUNC30_IN_INV_SEL_S  5
+/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC30_IN_SEL  0x0000001F
+#define GPIO_FUNC30_IN_SEL_M  ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S))
+#define GPIO_FUNC30_IN_SEL_V  0x1F
+#define GPIO_FUNC30_IN_SEL_S  0
+
+#define GPIO_FUNC31_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1D0)
+/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG31_IN_SEL  (BIT(6))
+#define GPIO_SIG31_IN_SEL_M  (BIT(6))
+#define GPIO_SIG31_IN_SEL_V  0x1
+#define GPIO_SIG31_IN_SEL_S  6
+/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC31_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC31_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC31_IN_INV_SEL_V  0x1
+#define GPIO_FUNC31_IN_INV_SEL_S  5
+/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC31_IN_SEL  0x0000001F
+#define GPIO_FUNC31_IN_SEL_M  ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S))
+#define GPIO_FUNC31_IN_SEL_V  0x1F
+#define GPIO_FUNC31_IN_SEL_S  0
+
+#define GPIO_FUNC32_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1D4)
+/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG32_IN_SEL  (BIT(6))
+#define GPIO_SIG32_IN_SEL_M  (BIT(6))
+#define GPIO_SIG32_IN_SEL_V  0x1
+#define GPIO_SIG32_IN_SEL_S  6
+/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC32_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC32_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC32_IN_INV_SEL_V  0x1
+#define GPIO_FUNC32_IN_INV_SEL_S  5
+/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC32_IN_SEL  0x0000001F
+#define GPIO_FUNC32_IN_SEL_M  ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S))
+#define GPIO_FUNC32_IN_SEL_V  0x1F
+#define GPIO_FUNC32_IN_SEL_S  0
+
+#define GPIO_FUNC33_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1D8)
+/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG33_IN_SEL  (BIT(6))
+#define GPIO_SIG33_IN_SEL_M  (BIT(6))
+#define GPIO_SIG33_IN_SEL_V  0x1
+#define GPIO_SIG33_IN_SEL_S  6
+/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC33_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC33_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC33_IN_INV_SEL_V  0x1
+#define GPIO_FUNC33_IN_INV_SEL_S  5
+/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC33_IN_SEL  0x0000001F
+#define GPIO_FUNC33_IN_SEL_M  ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S))
+#define GPIO_FUNC33_IN_SEL_V  0x1F
+#define GPIO_FUNC33_IN_SEL_S  0
+
+#define GPIO_FUNC34_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1DC)
+/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG34_IN_SEL  (BIT(6))
+#define GPIO_SIG34_IN_SEL_M  (BIT(6))
+#define GPIO_SIG34_IN_SEL_V  0x1
+#define GPIO_SIG34_IN_SEL_S  6
+/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC34_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC34_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC34_IN_INV_SEL_V  0x1
+#define GPIO_FUNC34_IN_INV_SEL_S  5
+/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC34_IN_SEL  0x0000001F
+#define GPIO_FUNC34_IN_SEL_M  ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S))
+#define GPIO_FUNC34_IN_SEL_V  0x1F
+#define GPIO_FUNC34_IN_SEL_S  0
+
+#define GPIO_FUNC35_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1E0)
+/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG35_IN_SEL  (BIT(6))
+#define GPIO_SIG35_IN_SEL_M  (BIT(6))
+#define GPIO_SIG35_IN_SEL_V  0x1
+#define GPIO_SIG35_IN_SEL_S  6
+/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC35_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC35_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC35_IN_INV_SEL_V  0x1
+#define GPIO_FUNC35_IN_INV_SEL_S  5
+/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC35_IN_SEL  0x0000001F
+#define GPIO_FUNC35_IN_SEL_M  ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S))
+#define GPIO_FUNC35_IN_SEL_V  0x1F
+#define GPIO_FUNC35_IN_SEL_S  0
+
+#define GPIO_FUNC36_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1E4)
+/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG36_IN_SEL  (BIT(6))
+#define GPIO_SIG36_IN_SEL_M  (BIT(6))
+#define GPIO_SIG36_IN_SEL_V  0x1
+#define GPIO_SIG36_IN_SEL_S  6
+/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC36_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC36_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC36_IN_INV_SEL_V  0x1
+#define GPIO_FUNC36_IN_INV_SEL_S  5
+/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC36_IN_SEL  0x0000001F
+#define GPIO_FUNC36_IN_SEL_M  ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S))
+#define GPIO_FUNC36_IN_SEL_V  0x1F
+#define GPIO_FUNC36_IN_SEL_S  0
+
+#define GPIO_FUNC37_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1E8)
+/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG37_IN_SEL  (BIT(6))
+#define GPIO_SIG37_IN_SEL_M  (BIT(6))
+#define GPIO_SIG37_IN_SEL_V  0x1
+#define GPIO_SIG37_IN_SEL_S  6
+/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC37_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC37_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC37_IN_INV_SEL_V  0x1
+#define GPIO_FUNC37_IN_INV_SEL_S  5
+/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC37_IN_SEL  0x0000001F
+#define GPIO_FUNC37_IN_SEL_M  ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S))
+#define GPIO_FUNC37_IN_SEL_V  0x1F
+#define GPIO_FUNC37_IN_SEL_S  0
+
+#define GPIO_FUNC38_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1EC)
+/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG38_IN_SEL  (BIT(6))
+#define GPIO_SIG38_IN_SEL_M  (BIT(6))
+#define GPIO_SIG38_IN_SEL_V  0x1
+#define GPIO_SIG38_IN_SEL_S  6
+/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC38_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC38_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC38_IN_INV_SEL_V  0x1
+#define GPIO_FUNC38_IN_INV_SEL_S  5
+/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC38_IN_SEL  0x0000001F
+#define GPIO_FUNC38_IN_SEL_M  ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S))
+#define GPIO_FUNC38_IN_SEL_V  0x1F
+#define GPIO_FUNC38_IN_SEL_S  0
+
+#define GPIO_FUNC39_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1F0)
+/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG39_IN_SEL  (BIT(6))
+#define GPIO_SIG39_IN_SEL_M  (BIT(6))
+#define GPIO_SIG39_IN_SEL_V  0x1
+#define GPIO_SIG39_IN_SEL_S  6
+/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC39_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC39_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC39_IN_INV_SEL_V  0x1
+#define GPIO_FUNC39_IN_INV_SEL_S  5
+/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC39_IN_SEL  0x0000001F
+#define GPIO_FUNC39_IN_SEL_M  ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S))
+#define GPIO_FUNC39_IN_SEL_V  0x1F
+#define GPIO_FUNC39_IN_SEL_S  0
+
+#define GPIO_FUNC40_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1F4)
+/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG40_IN_SEL  (BIT(6))
+#define GPIO_SIG40_IN_SEL_M  (BIT(6))
+#define GPIO_SIG40_IN_SEL_V  0x1
+#define GPIO_SIG40_IN_SEL_S  6
+/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC40_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC40_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC40_IN_INV_SEL_V  0x1
+#define GPIO_FUNC40_IN_INV_SEL_S  5
+/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC40_IN_SEL  0x0000001F
+#define GPIO_FUNC40_IN_SEL_M  ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S))
+#define GPIO_FUNC40_IN_SEL_V  0x1F
+#define GPIO_FUNC40_IN_SEL_S  0
+
+#define GPIO_FUNC41_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1F8)
+/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG41_IN_SEL  (BIT(6))
+#define GPIO_SIG41_IN_SEL_M  (BIT(6))
+#define GPIO_SIG41_IN_SEL_V  0x1
+#define GPIO_SIG41_IN_SEL_S  6
+/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC41_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC41_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC41_IN_INV_SEL_V  0x1
+#define GPIO_FUNC41_IN_INV_SEL_S  5
+/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC41_IN_SEL  0x0000001F
+#define GPIO_FUNC41_IN_SEL_M  ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S))
+#define GPIO_FUNC41_IN_SEL_V  0x1F
+#define GPIO_FUNC41_IN_SEL_S  0
+
+#define GPIO_FUNC42_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1FC)
+/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG42_IN_SEL  (BIT(6))
+#define GPIO_SIG42_IN_SEL_M  (BIT(6))
+#define GPIO_SIG42_IN_SEL_V  0x1
+#define GPIO_SIG42_IN_SEL_S  6
+/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC42_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC42_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC42_IN_INV_SEL_V  0x1
+#define GPIO_FUNC42_IN_INV_SEL_S  5
+/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC42_IN_SEL  0x0000001F
+#define GPIO_FUNC42_IN_SEL_M  ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S))
+#define GPIO_FUNC42_IN_SEL_V  0x1F
+#define GPIO_FUNC42_IN_SEL_S  0
+
+#define GPIO_FUNC43_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x200)
+/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG43_IN_SEL  (BIT(6))
+#define GPIO_SIG43_IN_SEL_M  (BIT(6))
+#define GPIO_SIG43_IN_SEL_V  0x1
+#define GPIO_SIG43_IN_SEL_S  6
+/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC43_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC43_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC43_IN_INV_SEL_V  0x1
+#define GPIO_FUNC43_IN_INV_SEL_S  5
+/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC43_IN_SEL  0x0000001F
+#define GPIO_FUNC43_IN_SEL_M  ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S))
+#define GPIO_FUNC43_IN_SEL_V  0x1F
+#define GPIO_FUNC43_IN_SEL_S  0
+
+#define GPIO_FUNC44_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x204)
+/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG44_IN_SEL  (BIT(6))
+#define GPIO_SIG44_IN_SEL_M  (BIT(6))
+#define GPIO_SIG44_IN_SEL_V  0x1
+#define GPIO_SIG44_IN_SEL_S  6
+/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC44_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC44_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC44_IN_INV_SEL_V  0x1
+#define GPIO_FUNC44_IN_INV_SEL_S  5
+/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC44_IN_SEL  0x0000001F
+#define GPIO_FUNC44_IN_SEL_M  ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S))
+#define GPIO_FUNC44_IN_SEL_V  0x1F
+#define GPIO_FUNC44_IN_SEL_S  0
+
+#define GPIO_FUNC45_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x208)
+/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG45_IN_SEL  (BIT(6))
+#define GPIO_SIG45_IN_SEL_M  (BIT(6))
+#define GPIO_SIG45_IN_SEL_V  0x1
+#define GPIO_SIG45_IN_SEL_S  6
+/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC45_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC45_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC45_IN_INV_SEL_V  0x1
+#define GPIO_FUNC45_IN_INV_SEL_S  5
+/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC45_IN_SEL  0x0000001F
+#define GPIO_FUNC45_IN_SEL_M  ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S))
+#define GPIO_FUNC45_IN_SEL_V  0x1F
+#define GPIO_FUNC45_IN_SEL_S  0
+
+#define GPIO_FUNC46_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x20C)
+/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG46_IN_SEL  (BIT(6))
+#define GPIO_SIG46_IN_SEL_M  (BIT(6))
+#define GPIO_SIG46_IN_SEL_V  0x1
+#define GPIO_SIG46_IN_SEL_S  6
+/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC46_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC46_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC46_IN_INV_SEL_V  0x1
+#define GPIO_FUNC46_IN_INV_SEL_S  5
+/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC46_IN_SEL  0x0000001F
+#define GPIO_FUNC46_IN_SEL_M  ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S))
+#define GPIO_FUNC46_IN_SEL_V  0x1F
+#define GPIO_FUNC46_IN_SEL_S  0
+
+#define GPIO_FUNC47_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x210)
+/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG47_IN_SEL  (BIT(6))
+#define GPIO_SIG47_IN_SEL_M  (BIT(6))
+#define GPIO_SIG47_IN_SEL_V  0x1
+#define GPIO_SIG47_IN_SEL_S  6
+/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC47_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC47_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC47_IN_INV_SEL_V  0x1
+#define GPIO_FUNC47_IN_INV_SEL_S  5
+/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC47_IN_SEL  0x0000001F
+#define GPIO_FUNC47_IN_SEL_M  ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S))
+#define GPIO_FUNC47_IN_SEL_V  0x1F
+#define GPIO_FUNC47_IN_SEL_S  0
+
+#define GPIO_FUNC48_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x214)
+/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG48_IN_SEL  (BIT(6))
+#define GPIO_SIG48_IN_SEL_M  (BIT(6))
+#define GPIO_SIG48_IN_SEL_V  0x1
+#define GPIO_SIG48_IN_SEL_S  6
+/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC48_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC48_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC48_IN_INV_SEL_V  0x1
+#define GPIO_FUNC48_IN_INV_SEL_S  5
+/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC48_IN_SEL  0x0000001F
+#define GPIO_FUNC48_IN_SEL_M  ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S))
+#define GPIO_FUNC48_IN_SEL_V  0x1F
+#define GPIO_FUNC48_IN_SEL_S  0
+
+#define GPIO_FUNC49_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x218)
+/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG49_IN_SEL  (BIT(6))
+#define GPIO_SIG49_IN_SEL_M  (BIT(6))
+#define GPIO_SIG49_IN_SEL_V  0x1
+#define GPIO_SIG49_IN_SEL_S  6
+/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC49_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC49_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC49_IN_INV_SEL_V  0x1
+#define GPIO_FUNC49_IN_INV_SEL_S  5
+/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC49_IN_SEL  0x0000001F
+#define GPIO_FUNC49_IN_SEL_M  ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S))
+#define GPIO_FUNC49_IN_SEL_V  0x1F
+#define GPIO_FUNC49_IN_SEL_S  0
+
+#define GPIO_FUNC50_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x21C)
+/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG50_IN_SEL  (BIT(6))
+#define GPIO_SIG50_IN_SEL_M  (BIT(6))
+#define GPIO_SIG50_IN_SEL_V  0x1
+#define GPIO_SIG50_IN_SEL_S  6
+/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC50_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC50_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC50_IN_INV_SEL_V  0x1
+#define GPIO_FUNC50_IN_INV_SEL_S  5
+/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC50_IN_SEL  0x0000001F
+#define GPIO_FUNC50_IN_SEL_M  ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S))
+#define GPIO_FUNC50_IN_SEL_V  0x1F
+#define GPIO_FUNC50_IN_SEL_S  0
+
+#define GPIO_FUNC51_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x220)
+/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG51_IN_SEL  (BIT(6))
+#define GPIO_SIG51_IN_SEL_M  (BIT(6))
+#define GPIO_SIG51_IN_SEL_V  0x1
+#define GPIO_SIG51_IN_SEL_S  6
+/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC51_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC51_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC51_IN_INV_SEL_V  0x1
+#define GPIO_FUNC51_IN_INV_SEL_S  5
+/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC51_IN_SEL  0x0000001F
+#define GPIO_FUNC51_IN_SEL_M  ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S))
+#define GPIO_FUNC51_IN_SEL_V  0x1F
+#define GPIO_FUNC51_IN_SEL_S  0
+
+#define GPIO_FUNC52_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x224)
+/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG52_IN_SEL  (BIT(6))
+#define GPIO_SIG52_IN_SEL_M  (BIT(6))
+#define GPIO_SIG52_IN_SEL_V  0x1
+#define GPIO_SIG52_IN_SEL_S  6
+/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC52_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC52_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC52_IN_INV_SEL_V  0x1
+#define GPIO_FUNC52_IN_INV_SEL_S  5
+/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC52_IN_SEL  0x0000001F
+#define GPIO_FUNC52_IN_SEL_M  ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S))
+#define GPIO_FUNC52_IN_SEL_V  0x1F
+#define GPIO_FUNC52_IN_SEL_S  0
+
+#define GPIO_FUNC53_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x228)
+/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG53_IN_SEL  (BIT(6))
+#define GPIO_SIG53_IN_SEL_M  (BIT(6))
+#define GPIO_SIG53_IN_SEL_V  0x1
+#define GPIO_SIG53_IN_SEL_S  6
+/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC53_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC53_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC53_IN_INV_SEL_V  0x1
+#define GPIO_FUNC53_IN_INV_SEL_S  5
+/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC53_IN_SEL  0x0000001F
+#define GPIO_FUNC53_IN_SEL_M  ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S))
+#define GPIO_FUNC53_IN_SEL_V  0x1F
+#define GPIO_FUNC53_IN_SEL_S  0
+
+#define GPIO_FUNC54_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x22C)
+/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG54_IN_SEL  (BIT(6))
+#define GPIO_SIG54_IN_SEL_M  (BIT(6))
+#define GPIO_SIG54_IN_SEL_V  0x1
+#define GPIO_SIG54_IN_SEL_S  6
+/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC54_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC54_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC54_IN_INV_SEL_V  0x1
+#define GPIO_FUNC54_IN_INV_SEL_S  5
+/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC54_IN_SEL  0x0000001F
+#define GPIO_FUNC54_IN_SEL_M  ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S))
+#define GPIO_FUNC54_IN_SEL_V  0x1F
+#define GPIO_FUNC54_IN_SEL_S  0
+
+#define GPIO_FUNC55_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x230)
+/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG55_IN_SEL  (BIT(6))
+#define GPIO_SIG55_IN_SEL_M  (BIT(6))
+#define GPIO_SIG55_IN_SEL_V  0x1
+#define GPIO_SIG55_IN_SEL_S  6
+/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC55_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC55_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC55_IN_INV_SEL_V  0x1
+#define GPIO_FUNC55_IN_INV_SEL_S  5
+/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC55_IN_SEL  0x0000001F
+#define GPIO_FUNC55_IN_SEL_M  ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S))
+#define GPIO_FUNC55_IN_SEL_V  0x1F
+#define GPIO_FUNC55_IN_SEL_S  0
+
+#define GPIO_FUNC56_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x234)
+/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG56_IN_SEL  (BIT(6))
+#define GPIO_SIG56_IN_SEL_M  (BIT(6))
+#define GPIO_SIG56_IN_SEL_V  0x1
+#define GPIO_SIG56_IN_SEL_S  6
+/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC56_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC56_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC56_IN_INV_SEL_V  0x1
+#define GPIO_FUNC56_IN_INV_SEL_S  5
+/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC56_IN_SEL  0x0000001F
+#define GPIO_FUNC56_IN_SEL_M  ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S))
+#define GPIO_FUNC56_IN_SEL_V  0x1F
+#define GPIO_FUNC56_IN_SEL_S  0
+
+#define GPIO_FUNC57_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x238)
+/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG57_IN_SEL  (BIT(6))
+#define GPIO_SIG57_IN_SEL_M  (BIT(6))
+#define GPIO_SIG57_IN_SEL_V  0x1
+#define GPIO_SIG57_IN_SEL_S  6
+/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC57_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC57_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC57_IN_INV_SEL_V  0x1
+#define GPIO_FUNC57_IN_INV_SEL_S  5
+/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC57_IN_SEL  0x0000001F
+#define GPIO_FUNC57_IN_SEL_M  ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S))
+#define GPIO_FUNC57_IN_SEL_V  0x1F
+#define GPIO_FUNC57_IN_SEL_S  0
+
+#define GPIO_FUNC58_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x23C)
+/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG58_IN_SEL  (BIT(6))
+#define GPIO_SIG58_IN_SEL_M  (BIT(6))
+#define GPIO_SIG58_IN_SEL_V  0x1
+#define GPIO_SIG58_IN_SEL_S  6
+/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC58_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC58_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC58_IN_INV_SEL_V  0x1
+#define GPIO_FUNC58_IN_INV_SEL_S  5
+/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC58_IN_SEL  0x0000001F
+#define GPIO_FUNC58_IN_SEL_M  ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S))
+#define GPIO_FUNC58_IN_SEL_V  0x1F
+#define GPIO_FUNC58_IN_SEL_S  0
+
+#define GPIO_FUNC59_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x240)
+/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG59_IN_SEL  (BIT(6))
+#define GPIO_SIG59_IN_SEL_M  (BIT(6))
+#define GPIO_SIG59_IN_SEL_V  0x1
+#define GPIO_SIG59_IN_SEL_S  6
+/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC59_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC59_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC59_IN_INV_SEL_V  0x1
+#define GPIO_FUNC59_IN_INV_SEL_S  5
+/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC59_IN_SEL  0x0000001F
+#define GPIO_FUNC59_IN_SEL_M  ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S))
+#define GPIO_FUNC59_IN_SEL_V  0x1F
+#define GPIO_FUNC59_IN_SEL_S  0
+
+#define GPIO_FUNC60_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x244)
+/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG60_IN_SEL  (BIT(6))
+#define GPIO_SIG60_IN_SEL_M  (BIT(6))
+#define GPIO_SIG60_IN_SEL_V  0x1
+#define GPIO_SIG60_IN_SEL_S  6
+/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC60_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC60_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC60_IN_INV_SEL_V  0x1
+#define GPIO_FUNC60_IN_INV_SEL_S  5
+/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC60_IN_SEL  0x0000001F
+#define GPIO_FUNC60_IN_SEL_M  ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S))
+#define GPIO_FUNC60_IN_SEL_V  0x1F
+#define GPIO_FUNC60_IN_SEL_S  0
+
+#define GPIO_FUNC61_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x248)
+/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG61_IN_SEL  (BIT(6))
+#define GPIO_SIG61_IN_SEL_M  (BIT(6))
+#define GPIO_SIG61_IN_SEL_V  0x1
+#define GPIO_SIG61_IN_SEL_S  6
+/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC61_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC61_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC61_IN_INV_SEL_V  0x1
+#define GPIO_FUNC61_IN_INV_SEL_S  5
+/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC61_IN_SEL  0x0000001F
+#define GPIO_FUNC61_IN_SEL_M  ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S))
+#define GPIO_FUNC61_IN_SEL_V  0x1F
+#define GPIO_FUNC61_IN_SEL_S  0
+
+#define GPIO_FUNC62_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x24C)
+/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG62_IN_SEL  (BIT(6))
+#define GPIO_SIG62_IN_SEL_M  (BIT(6))
+#define GPIO_SIG62_IN_SEL_V  0x1
+#define GPIO_SIG62_IN_SEL_S  6
+/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC62_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC62_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC62_IN_INV_SEL_V  0x1
+#define GPIO_FUNC62_IN_INV_SEL_S  5
+/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC62_IN_SEL  0x0000001F
+#define GPIO_FUNC62_IN_SEL_M  ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S))
+#define GPIO_FUNC62_IN_SEL_V  0x1F
+#define GPIO_FUNC62_IN_SEL_S  0
+
+#define GPIO_FUNC63_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x250)
+/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG63_IN_SEL  (BIT(6))
+#define GPIO_SIG63_IN_SEL_M  (BIT(6))
+#define GPIO_SIG63_IN_SEL_V  0x1
+#define GPIO_SIG63_IN_SEL_S  6
+/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC63_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC63_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC63_IN_INV_SEL_V  0x1
+#define GPIO_FUNC63_IN_INV_SEL_S  5
+/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC63_IN_SEL  0x0000001F
+#define GPIO_FUNC63_IN_SEL_M  ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S))
+#define GPIO_FUNC63_IN_SEL_V  0x1F
+#define GPIO_FUNC63_IN_SEL_S  0
+
+#define GPIO_FUNC64_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x254)
+/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG64_IN_SEL  (BIT(6))
+#define GPIO_SIG64_IN_SEL_M  (BIT(6))
+#define GPIO_SIG64_IN_SEL_V  0x1
+#define GPIO_SIG64_IN_SEL_S  6
+/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC64_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC64_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC64_IN_INV_SEL_V  0x1
+#define GPIO_FUNC64_IN_INV_SEL_S  5
+/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC64_IN_SEL  0x0000001F
+#define GPIO_FUNC64_IN_SEL_M  ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S))
+#define GPIO_FUNC64_IN_SEL_V  0x1F
+#define GPIO_FUNC64_IN_SEL_S  0
+
+#define GPIO_FUNC65_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x258)
+/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG65_IN_SEL  (BIT(6))
+#define GPIO_SIG65_IN_SEL_M  (BIT(6))
+#define GPIO_SIG65_IN_SEL_V  0x1
+#define GPIO_SIG65_IN_SEL_S  6
+/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC65_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC65_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC65_IN_INV_SEL_V  0x1
+#define GPIO_FUNC65_IN_INV_SEL_S  5
+/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC65_IN_SEL  0x0000001F
+#define GPIO_FUNC65_IN_SEL_M  ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S))
+#define GPIO_FUNC65_IN_SEL_V  0x1F
+#define GPIO_FUNC65_IN_SEL_S  0
+
+#define GPIO_FUNC66_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x25C)
+/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG66_IN_SEL  (BIT(6))
+#define GPIO_SIG66_IN_SEL_M  (BIT(6))
+#define GPIO_SIG66_IN_SEL_V  0x1
+#define GPIO_SIG66_IN_SEL_S  6
+/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC66_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC66_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC66_IN_INV_SEL_V  0x1
+#define GPIO_FUNC66_IN_INV_SEL_S  5
+/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC66_IN_SEL  0x0000001F
+#define GPIO_FUNC66_IN_SEL_M  ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S))
+#define GPIO_FUNC66_IN_SEL_V  0x1F
+#define GPIO_FUNC66_IN_SEL_S  0
+
+#define GPIO_FUNC67_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x260)
+/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG67_IN_SEL  (BIT(6))
+#define GPIO_SIG67_IN_SEL_M  (BIT(6))
+#define GPIO_SIG67_IN_SEL_V  0x1
+#define GPIO_SIG67_IN_SEL_S  6
+/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC67_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC67_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC67_IN_INV_SEL_V  0x1
+#define GPIO_FUNC67_IN_INV_SEL_S  5
+/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC67_IN_SEL  0x0000001F
+#define GPIO_FUNC67_IN_SEL_M  ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S))
+#define GPIO_FUNC67_IN_SEL_V  0x1F
+#define GPIO_FUNC67_IN_SEL_S  0
+
+#define GPIO_FUNC68_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x264)
+/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG68_IN_SEL  (BIT(6))
+#define GPIO_SIG68_IN_SEL_M  (BIT(6))
+#define GPIO_SIG68_IN_SEL_V  0x1
+#define GPIO_SIG68_IN_SEL_S  6
+/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC68_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC68_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC68_IN_INV_SEL_V  0x1
+#define GPIO_FUNC68_IN_INV_SEL_S  5
+/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC68_IN_SEL  0x0000001F
+#define GPIO_FUNC68_IN_SEL_M  ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S))
+#define GPIO_FUNC68_IN_SEL_V  0x1F
+#define GPIO_FUNC68_IN_SEL_S  0
+
+#define GPIO_FUNC69_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x268)
+/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG69_IN_SEL  (BIT(6))
+#define GPIO_SIG69_IN_SEL_M  (BIT(6))
+#define GPIO_SIG69_IN_SEL_V  0x1
+#define GPIO_SIG69_IN_SEL_S  6
+/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC69_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC69_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC69_IN_INV_SEL_V  0x1
+#define GPIO_FUNC69_IN_INV_SEL_S  5
+/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC69_IN_SEL  0x0000001F
+#define GPIO_FUNC69_IN_SEL_M  ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S))
+#define GPIO_FUNC69_IN_SEL_V  0x1F
+#define GPIO_FUNC69_IN_SEL_S  0
+
+#define GPIO_FUNC70_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x26C)
+/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG70_IN_SEL  (BIT(6))
+#define GPIO_SIG70_IN_SEL_M  (BIT(6))
+#define GPIO_SIG70_IN_SEL_V  0x1
+#define GPIO_SIG70_IN_SEL_S  6
+/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC70_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC70_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC70_IN_INV_SEL_V  0x1
+#define GPIO_FUNC70_IN_INV_SEL_S  5
+/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC70_IN_SEL  0x0000001F
+#define GPIO_FUNC70_IN_SEL_M  ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S))
+#define GPIO_FUNC70_IN_SEL_V  0x1F
+#define GPIO_FUNC70_IN_SEL_S  0
+
+#define GPIO_FUNC71_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x270)
+/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG71_IN_SEL  (BIT(6))
+#define GPIO_SIG71_IN_SEL_M  (BIT(6))
+#define GPIO_SIG71_IN_SEL_V  0x1
+#define GPIO_SIG71_IN_SEL_S  6
+/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC71_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC71_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC71_IN_INV_SEL_V  0x1
+#define GPIO_FUNC71_IN_INV_SEL_S  5
+/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC71_IN_SEL  0x0000001F
+#define GPIO_FUNC71_IN_SEL_M  ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S))
+#define GPIO_FUNC71_IN_SEL_V  0x1F
+#define GPIO_FUNC71_IN_SEL_S  0
+
+#define GPIO_FUNC72_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x274)
+/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG72_IN_SEL  (BIT(6))
+#define GPIO_SIG72_IN_SEL_M  (BIT(6))
+#define GPIO_SIG72_IN_SEL_V  0x1
+#define GPIO_SIG72_IN_SEL_S  6
+/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC72_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC72_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC72_IN_INV_SEL_V  0x1
+#define GPIO_FUNC72_IN_INV_SEL_S  5
+/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC72_IN_SEL  0x0000001F
+#define GPIO_FUNC72_IN_SEL_M  ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S))
+#define GPIO_FUNC72_IN_SEL_V  0x1F
+#define GPIO_FUNC72_IN_SEL_S  0
+
+#define GPIO_FUNC73_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x278)
+/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG73_IN_SEL  (BIT(6))
+#define GPIO_SIG73_IN_SEL_M  (BIT(6))
+#define GPIO_SIG73_IN_SEL_V  0x1
+#define GPIO_SIG73_IN_SEL_S  6
+/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC73_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC73_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC73_IN_INV_SEL_V  0x1
+#define GPIO_FUNC73_IN_INV_SEL_S  5
+/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC73_IN_SEL  0x0000001F
+#define GPIO_FUNC73_IN_SEL_M  ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S))
+#define GPIO_FUNC73_IN_SEL_V  0x1F
+#define GPIO_FUNC73_IN_SEL_S  0
+
+#define GPIO_FUNC74_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x27C)
+/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG74_IN_SEL  (BIT(6))
+#define GPIO_SIG74_IN_SEL_M  (BIT(6))
+#define GPIO_SIG74_IN_SEL_V  0x1
+#define GPIO_SIG74_IN_SEL_S  6
+/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC74_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC74_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC74_IN_INV_SEL_V  0x1
+#define GPIO_FUNC74_IN_INV_SEL_S  5
+/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC74_IN_SEL  0x0000001F
+#define GPIO_FUNC74_IN_SEL_M  ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S))
+#define GPIO_FUNC74_IN_SEL_V  0x1F
+#define GPIO_FUNC74_IN_SEL_S  0
+
+#define GPIO_FUNC75_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x280)
+/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG75_IN_SEL  (BIT(6))
+#define GPIO_SIG75_IN_SEL_M  (BIT(6))
+#define GPIO_SIG75_IN_SEL_V  0x1
+#define GPIO_SIG75_IN_SEL_S  6
+/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC75_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC75_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC75_IN_INV_SEL_V  0x1
+#define GPIO_FUNC75_IN_INV_SEL_S  5
+/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC75_IN_SEL  0x0000001F
+#define GPIO_FUNC75_IN_SEL_M  ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S))
+#define GPIO_FUNC75_IN_SEL_V  0x1F
+#define GPIO_FUNC75_IN_SEL_S  0
+
+#define GPIO_FUNC76_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x284)
+/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG76_IN_SEL  (BIT(6))
+#define GPIO_SIG76_IN_SEL_M  (BIT(6))
+#define GPIO_SIG76_IN_SEL_V  0x1
+#define GPIO_SIG76_IN_SEL_S  6
+/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC76_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC76_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC76_IN_INV_SEL_V  0x1
+#define GPIO_FUNC76_IN_INV_SEL_S  5
+/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC76_IN_SEL  0x0000001F
+#define GPIO_FUNC76_IN_SEL_M  ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S))
+#define GPIO_FUNC76_IN_SEL_V  0x1F
+#define GPIO_FUNC76_IN_SEL_S  0
+
+#define GPIO_FUNC77_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x288)
+/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG77_IN_SEL  (BIT(6))
+#define GPIO_SIG77_IN_SEL_M  (BIT(6))
+#define GPIO_SIG77_IN_SEL_V  0x1
+#define GPIO_SIG77_IN_SEL_S  6
+/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC77_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC77_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC77_IN_INV_SEL_V  0x1
+#define GPIO_FUNC77_IN_INV_SEL_S  5
+/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC77_IN_SEL  0x0000001F
+#define GPIO_FUNC77_IN_SEL_M  ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S))
+#define GPIO_FUNC77_IN_SEL_V  0x1F
+#define GPIO_FUNC77_IN_SEL_S  0
+
+#define GPIO_FUNC78_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x28C)
+/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG78_IN_SEL  (BIT(6))
+#define GPIO_SIG78_IN_SEL_M  (BIT(6))
+#define GPIO_SIG78_IN_SEL_V  0x1
+#define GPIO_SIG78_IN_SEL_S  6
+/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC78_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC78_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC78_IN_INV_SEL_V  0x1
+#define GPIO_FUNC78_IN_INV_SEL_S  5
+/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC78_IN_SEL  0x0000001F
+#define GPIO_FUNC78_IN_SEL_M  ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S))
+#define GPIO_FUNC78_IN_SEL_V  0x1F
+#define GPIO_FUNC78_IN_SEL_S  0
+
+#define GPIO_FUNC79_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x290)
+/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG79_IN_SEL  (BIT(6))
+#define GPIO_SIG79_IN_SEL_M  (BIT(6))
+#define GPIO_SIG79_IN_SEL_V  0x1
+#define GPIO_SIG79_IN_SEL_S  6
+/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC79_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC79_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC79_IN_INV_SEL_V  0x1
+#define GPIO_FUNC79_IN_INV_SEL_S  5
+/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC79_IN_SEL  0x0000001F
+#define GPIO_FUNC79_IN_SEL_M  ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S))
+#define GPIO_FUNC79_IN_SEL_V  0x1F
+#define GPIO_FUNC79_IN_SEL_S  0
+
+#define GPIO_FUNC80_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x294)
+/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG80_IN_SEL  (BIT(6))
+#define GPIO_SIG80_IN_SEL_M  (BIT(6))
+#define GPIO_SIG80_IN_SEL_V  0x1
+#define GPIO_SIG80_IN_SEL_S  6
+/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC80_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC80_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC80_IN_INV_SEL_V  0x1
+#define GPIO_FUNC80_IN_INV_SEL_S  5
+/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC80_IN_SEL  0x0000001F
+#define GPIO_FUNC80_IN_SEL_M  ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S))
+#define GPIO_FUNC80_IN_SEL_V  0x1F
+#define GPIO_FUNC80_IN_SEL_S  0
+
+#define GPIO_FUNC81_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x298)
+/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG81_IN_SEL  (BIT(6))
+#define GPIO_SIG81_IN_SEL_M  (BIT(6))
+#define GPIO_SIG81_IN_SEL_V  0x1
+#define GPIO_SIG81_IN_SEL_S  6
+/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC81_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC81_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC81_IN_INV_SEL_V  0x1
+#define GPIO_FUNC81_IN_INV_SEL_S  5
+/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC81_IN_SEL  0x0000001F
+#define GPIO_FUNC81_IN_SEL_M  ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S))
+#define GPIO_FUNC81_IN_SEL_V  0x1F
+#define GPIO_FUNC81_IN_SEL_S  0
+
+#define GPIO_FUNC82_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x29C)
+/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG82_IN_SEL  (BIT(6))
+#define GPIO_SIG82_IN_SEL_M  (BIT(6))
+#define GPIO_SIG82_IN_SEL_V  0x1
+#define GPIO_SIG82_IN_SEL_S  6
+/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC82_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC82_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC82_IN_INV_SEL_V  0x1
+#define GPIO_FUNC82_IN_INV_SEL_S  5
+/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC82_IN_SEL  0x0000001F
+#define GPIO_FUNC82_IN_SEL_M  ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S))
+#define GPIO_FUNC82_IN_SEL_V  0x1F
+#define GPIO_FUNC82_IN_SEL_S  0
+
+#define GPIO_FUNC83_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2A0)
+/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG83_IN_SEL  (BIT(6))
+#define GPIO_SIG83_IN_SEL_M  (BIT(6))
+#define GPIO_SIG83_IN_SEL_V  0x1
+#define GPIO_SIG83_IN_SEL_S  6
+/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC83_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC83_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC83_IN_INV_SEL_V  0x1
+#define GPIO_FUNC83_IN_INV_SEL_S  5
+/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC83_IN_SEL  0x0000001F
+#define GPIO_FUNC83_IN_SEL_M  ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S))
+#define GPIO_FUNC83_IN_SEL_V  0x1F
+#define GPIO_FUNC83_IN_SEL_S  0
+
+#define GPIO_FUNC84_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2A4)
+/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG84_IN_SEL  (BIT(6))
+#define GPIO_SIG84_IN_SEL_M  (BIT(6))
+#define GPIO_SIG84_IN_SEL_V  0x1
+#define GPIO_SIG84_IN_SEL_S  6
+/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC84_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC84_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC84_IN_INV_SEL_V  0x1
+#define GPIO_FUNC84_IN_INV_SEL_S  5
+/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC84_IN_SEL  0x0000001F
+#define GPIO_FUNC84_IN_SEL_M  ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S))
+#define GPIO_FUNC84_IN_SEL_V  0x1F
+#define GPIO_FUNC84_IN_SEL_S  0
+
+#define GPIO_FUNC85_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2A8)
+/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG85_IN_SEL  (BIT(6))
+#define GPIO_SIG85_IN_SEL_M  (BIT(6))
+#define GPIO_SIG85_IN_SEL_V  0x1
+#define GPIO_SIG85_IN_SEL_S  6
+/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC85_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC85_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC85_IN_INV_SEL_V  0x1
+#define GPIO_FUNC85_IN_INV_SEL_S  5
+/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC85_IN_SEL  0x0000001F
+#define GPIO_FUNC85_IN_SEL_M  ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S))
+#define GPIO_FUNC85_IN_SEL_V  0x1F
+#define GPIO_FUNC85_IN_SEL_S  0
+
+#define GPIO_FUNC86_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2AC)
+/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG86_IN_SEL  (BIT(6))
+#define GPIO_SIG86_IN_SEL_M  (BIT(6))
+#define GPIO_SIG86_IN_SEL_V  0x1
+#define GPIO_SIG86_IN_SEL_S  6
+/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC86_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC86_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC86_IN_INV_SEL_V  0x1
+#define GPIO_FUNC86_IN_INV_SEL_S  5
+/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC86_IN_SEL  0x0000001F
+#define GPIO_FUNC86_IN_SEL_M  ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S))
+#define GPIO_FUNC86_IN_SEL_V  0x1F
+#define GPIO_FUNC86_IN_SEL_S  0
+
+#define GPIO_FUNC87_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2B0)
+/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG87_IN_SEL  (BIT(6))
+#define GPIO_SIG87_IN_SEL_M  (BIT(6))
+#define GPIO_SIG87_IN_SEL_V  0x1
+#define GPIO_SIG87_IN_SEL_S  6
+/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC87_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC87_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC87_IN_INV_SEL_V  0x1
+#define GPIO_FUNC87_IN_INV_SEL_S  5
+/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC87_IN_SEL  0x0000001F
+#define GPIO_FUNC87_IN_SEL_M  ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S))
+#define GPIO_FUNC87_IN_SEL_V  0x1F
+#define GPIO_FUNC87_IN_SEL_S  0
+
+#define GPIO_FUNC88_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2B4)
+/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG88_IN_SEL  (BIT(6))
+#define GPIO_SIG88_IN_SEL_M  (BIT(6))
+#define GPIO_SIG88_IN_SEL_V  0x1
+#define GPIO_SIG88_IN_SEL_S  6
+/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC88_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC88_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC88_IN_INV_SEL_V  0x1
+#define GPIO_FUNC88_IN_INV_SEL_S  5
+/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC88_IN_SEL  0x0000001F
+#define GPIO_FUNC88_IN_SEL_M  ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S))
+#define GPIO_FUNC88_IN_SEL_V  0x1F
+#define GPIO_FUNC88_IN_SEL_S  0
+
+#define GPIO_FUNC89_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2B8)
+/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG89_IN_SEL  (BIT(6))
+#define GPIO_SIG89_IN_SEL_M  (BIT(6))
+#define GPIO_SIG89_IN_SEL_V  0x1
+#define GPIO_SIG89_IN_SEL_S  6
+/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC89_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC89_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC89_IN_INV_SEL_V  0x1
+#define GPIO_FUNC89_IN_INV_SEL_S  5
+/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC89_IN_SEL  0x0000001F
+#define GPIO_FUNC89_IN_SEL_M  ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S))
+#define GPIO_FUNC89_IN_SEL_V  0x1F
+#define GPIO_FUNC89_IN_SEL_S  0
+
+#define GPIO_FUNC90_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2BC)
+/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG90_IN_SEL  (BIT(6))
+#define GPIO_SIG90_IN_SEL_M  (BIT(6))
+#define GPIO_SIG90_IN_SEL_V  0x1
+#define GPIO_SIG90_IN_SEL_S  6
+/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC90_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC90_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC90_IN_INV_SEL_V  0x1
+#define GPIO_FUNC90_IN_INV_SEL_S  5
+/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC90_IN_SEL  0x0000001F
+#define GPIO_FUNC90_IN_SEL_M  ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S))
+#define GPIO_FUNC90_IN_SEL_V  0x1F
+#define GPIO_FUNC90_IN_SEL_S  0
+
+#define GPIO_FUNC91_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2C0)
+/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG91_IN_SEL  (BIT(6))
+#define GPIO_SIG91_IN_SEL_M  (BIT(6))
+#define GPIO_SIG91_IN_SEL_V  0x1
+#define GPIO_SIG91_IN_SEL_S  6
+/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC91_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC91_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC91_IN_INV_SEL_V  0x1
+#define GPIO_FUNC91_IN_INV_SEL_S  5
+/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC91_IN_SEL  0x0000001F
+#define GPIO_FUNC91_IN_SEL_M  ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S))
+#define GPIO_FUNC91_IN_SEL_V  0x1F
+#define GPIO_FUNC91_IN_SEL_S  0
+
+#define GPIO_FUNC92_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2C4)
+/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG92_IN_SEL  (BIT(6))
+#define GPIO_SIG92_IN_SEL_M  (BIT(6))
+#define GPIO_SIG92_IN_SEL_V  0x1
+#define GPIO_SIG92_IN_SEL_S  6
+/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC92_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC92_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC92_IN_INV_SEL_V  0x1
+#define GPIO_FUNC92_IN_INV_SEL_S  5
+/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC92_IN_SEL  0x0000001F
+#define GPIO_FUNC92_IN_SEL_M  ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S))
+#define GPIO_FUNC92_IN_SEL_V  0x1F
+#define GPIO_FUNC92_IN_SEL_S  0
+
+#define GPIO_FUNC93_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2C8)
+/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG93_IN_SEL  (BIT(6))
+#define GPIO_SIG93_IN_SEL_M  (BIT(6))
+#define GPIO_SIG93_IN_SEL_V  0x1
+#define GPIO_SIG93_IN_SEL_S  6
+/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC93_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC93_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC93_IN_INV_SEL_V  0x1
+#define GPIO_FUNC93_IN_INV_SEL_S  5
+/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC93_IN_SEL  0x0000001F
+#define GPIO_FUNC93_IN_SEL_M  ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S))
+#define GPIO_FUNC93_IN_SEL_V  0x1F
+#define GPIO_FUNC93_IN_SEL_S  0
+
+#define GPIO_FUNC94_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2CC)
+/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG94_IN_SEL  (BIT(6))
+#define GPIO_SIG94_IN_SEL_M  (BIT(6))
+#define GPIO_SIG94_IN_SEL_V  0x1
+#define GPIO_SIG94_IN_SEL_S  6
+/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC94_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC94_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC94_IN_INV_SEL_V  0x1
+#define GPIO_FUNC94_IN_INV_SEL_S  5
+/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC94_IN_SEL  0x0000001F
+#define GPIO_FUNC94_IN_SEL_M  ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S))
+#define GPIO_FUNC94_IN_SEL_V  0x1F
+#define GPIO_FUNC94_IN_SEL_S  0
+
+#define GPIO_FUNC95_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2D0)
+/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG95_IN_SEL  (BIT(6))
+#define GPIO_SIG95_IN_SEL_M  (BIT(6))
+#define GPIO_SIG95_IN_SEL_V  0x1
+#define GPIO_SIG95_IN_SEL_S  6
+/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC95_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC95_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC95_IN_INV_SEL_V  0x1
+#define GPIO_FUNC95_IN_INV_SEL_S  5
+/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC95_IN_SEL  0x0000001F
+#define GPIO_FUNC95_IN_SEL_M  ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S))
+#define GPIO_FUNC95_IN_SEL_V  0x1F
+#define GPIO_FUNC95_IN_SEL_S  0
+
+#define GPIO_FUNC96_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2D4)
+/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG96_IN_SEL  (BIT(6))
+#define GPIO_SIG96_IN_SEL_M  (BIT(6))
+#define GPIO_SIG96_IN_SEL_V  0x1
+#define GPIO_SIG96_IN_SEL_S  6
+/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC96_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC96_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC96_IN_INV_SEL_V  0x1
+#define GPIO_FUNC96_IN_INV_SEL_S  5
+/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC96_IN_SEL  0x0000001F
+#define GPIO_FUNC96_IN_SEL_M  ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S))
+#define GPIO_FUNC96_IN_SEL_V  0x1F
+#define GPIO_FUNC96_IN_SEL_S  0
+
+#define GPIO_FUNC97_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2D8)
+/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG97_IN_SEL  (BIT(6))
+#define GPIO_SIG97_IN_SEL_M  (BIT(6))
+#define GPIO_SIG97_IN_SEL_V  0x1
+#define GPIO_SIG97_IN_SEL_S  6
+/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC97_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC97_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC97_IN_INV_SEL_V  0x1
+#define GPIO_FUNC97_IN_INV_SEL_S  5
+/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC97_IN_SEL  0x0000001F
+#define GPIO_FUNC97_IN_SEL_M  ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S))
+#define GPIO_FUNC97_IN_SEL_V  0x1F
+#define GPIO_FUNC97_IN_SEL_S  0
+
+#define GPIO_FUNC98_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2DC)
+/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG98_IN_SEL  (BIT(6))
+#define GPIO_SIG98_IN_SEL_M  (BIT(6))
+#define GPIO_SIG98_IN_SEL_V  0x1
+#define GPIO_SIG98_IN_SEL_S  6
+/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC98_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC98_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC98_IN_INV_SEL_V  0x1
+#define GPIO_FUNC98_IN_INV_SEL_S  5
+/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC98_IN_SEL  0x0000001F
+#define GPIO_FUNC98_IN_SEL_M  ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S))
+#define GPIO_FUNC98_IN_SEL_V  0x1F
+#define GPIO_FUNC98_IN_SEL_S  0
+
+#define GPIO_FUNC99_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2E0)
+/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG99_IN_SEL  (BIT(6))
+#define GPIO_SIG99_IN_SEL_M  (BIT(6))
+#define GPIO_SIG99_IN_SEL_V  0x1
+#define GPIO_SIG99_IN_SEL_S  6
+/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC99_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC99_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC99_IN_INV_SEL_V  0x1
+#define GPIO_FUNC99_IN_INV_SEL_S  5
+/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC99_IN_SEL  0x0000001F
+#define GPIO_FUNC99_IN_SEL_M  ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S))
+#define GPIO_FUNC99_IN_SEL_V  0x1F
+#define GPIO_FUNC99_IN_SEL_S  0
+
+#define GPIO_FUNC100_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2E4)
+/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG100_IN_SEL  (BIT(6))
+#define GPIO_SIG100_IN_SEL_M  (BIT(6))
+#define GPIO_SIG100_IN_SEL_V  0x1
+#define GPIO_SIG100_IN_SEL_S  6
+/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC100_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC100_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC100_IN_INV_SEL_V  0x1
+#define GPIO_FUNC100_IN_INV_SEL_S  5
+/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC100_IN_SEL  0x0000001F
+#define GPIO_FUNC100_IN_SEL_M  ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S))
+#define GPIO_FUNC100_IN_SEL_V  0x1F
+#define GPIO_FUNC100_IN_SEL_S  0
+
+#define GPIO_FUNC101_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2E8)
+/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG101_IN_SEL  (BIT(6))
+#define GPIO_SIG101_IN_SEL_M  (BIT(6))
+#define GPIO_SIG101_IN_SEL_V  0x1
+#define GPIO_SIG101_IN_SEL_S  6
+/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC101_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC101_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC101_IN_INV_SEL_V  0x1
+#define GPIO_FUNC101_IN_INV_SEL_S  5
+/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC101_IN_SEL  0x0000001F
+#define GPIO_FUNC101_IN_SEL_M  ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S))
+#define GPIO_FUNC101_IN_SEL_V  0x1F
+#define GPIO_FUNC101_IN_SEL_S  0
+
+#define GPIO_FUNC102_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2EC)
+/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG102_IN_SEL  (BIT(6))
+#define GPIO_SIG102_IN_SEL_M  (BIT(6))
+#define GPIO_SIG102_IN_SEL_V  0x1
+#define GPIO_SIG102_IN_SEL_S  6
+/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC102_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC102_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC102_IN_INV_SEL_V  0x1
+#define GPIO_FUNC102_IN_INV_SEL_S  5
+/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC102_IN_SEL  0x0000001F
+#define GPIO_FUNC102_IN_SEL_M  ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S))
+#define GPIO_FUNC102_IN_SEL_V  0x1F
+#define GPIO_FUNC102_IN_SEL_S  0
+
+#define GPIO_FUNC103_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2F0)
+/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG103_IN_SEL  (BIT(6))
+#define GPIO_SIG103_IN_SEL_M  (BIT(6))
+#define GPIO_SIG103_IN_SEL_V  0x1
+#define GPIO_SIG103_IN_SEL_S  6
+/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC103_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC103_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC103_IN_INV_SEL_V  0x1
+#define GPIO_FUNC103_IN_INV_SEL_S  5
+/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC103_IN_SEL  0x0000001F
+#define GPIO_FUNC103_IN_SEL_M  ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S))
+#define GPIO_FUNC103_IN_SEL_V  0x1F
+#define GPIO_FUNC103_IN_SEL_S  0
+
+#define GPIO_FUNC104_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2F4)
+/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG104_IN_SEL  (BIT(6))
+#define GPIO_SIG104_IN_SEL_M  (BIT(6))
+#define GPIO_SIG104_IN_SEL_V  0x1
+#define GPIO_SIG104_IN_SEL_S  6
+/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC104_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC104_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC104_IN_INV_SEL_V  0x1
+#define GPIO_FUNC104_IN_INV_SEL_S  5
+/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC104_IN_SEL  0x0000001F
+#define GPIO_FUNC104_IN_SEL_M  ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S))
+#define GPIO_FUNC104_IN_SEL_V  0x1F
+#define GPIO_FUNC104_IN_SEL_S  0
+
+#define GPIO_FUNC105_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2F8)
+/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG105_IN_SEL  (BIT(6))
+#define GPIO_SIG105_IN_SEL_M  (BIT(6))
+#define GPIO_SIG105_IN_SEL_V  0x1
+#define GPIO_SIG105_IN_SEL_S  6
+/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC105_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC105_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC105_IN_INV_SEL_V  0x1
+#define GPIO_FUNC105_IN_INV_SEL_S  5
+/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC105_IN_SEL  0x0000001F
+#define GPIO_FUNC105_IN_SEL_M  ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S))
+#define GPIO_FUNC105_IN_SEL_V  0x1F
+#define GPIO_FUNC105_IN_SEL_S  0
+
+#define GPIO_FUNC106_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2FC)
+/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG106_IN_SEL  (BIT(6))
+#define GPIO_SIG106_IN_SEL_M  (BIT(6))
+#define GPIO_SIG106_IN_SEL_V  0x1
+#define GPIO_SIG106_IN_SEL_S  6
+/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC106_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC106_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC106_IN_INV_SEL_V  0x1
+#define GPIO_FUNC106_IN_INV_SEL_S  5
+/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC106_IN_SEL  0x0000001F
+#define GPIO_FUNC106_IN_SEL_M  ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S))
+#define GPIO_FUNC106_IN_SEL_V  0x1F
+#define GPIO_FUNC106_IN_SEL_S  0
+
+#define GPIO_FUNC107_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x300)
+/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG107_IN_SEL  (BIT(6))
+#define GPIO_SIG107_IN_SEL_M  (BIT(6))
+#define GPIO_SIG107_IN_SEL_V  0x1
+#define GPIO_SIG107_IN_SEL_S  6
+/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC107_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC107_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC107_IN_INV_SEL_V  0x1
+#define GPIO_FUNC107_IN_INV_SEL_S  5
+/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC107_IN_SEL  0x0000001F
+#define GPIO_FUNC107_IN_SEL_M  ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S))
+#define GPIO_FUNC107_IN_SEL_V  0x1F
+#define GPIO_FUNC107_IN_SEL_S  0
+
+#define GPIO_FUNC108_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x304)
+/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG108_IN_SEL  (BIT(6))
+#define GPIO_SIG108_IN_SEL_M  (BIT(6))
+#define GPIO_SIG108_IN_SEL_V  0x1
+#define GPIO_SIG108_IN_SEL_S  6
+/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC108_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC108_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC108_IN_INV_SEL_V  0x1
+#define GPIO_FUNC108_IN_INV_SEL_S  5
+/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC108_IN_SEL  0x0000001F
+#define GPIO_FUNC108_IN_SEL_M  ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S))
+#define GPIO_FUNC108_IN_SEL_V  0x1F
+#define GPIO_FUNC108_IN_SEL_S  0
+
+#define GPIO_FUNC109_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x308)
+/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG109_IN_SEL  (BIT(6))
+#define GPIO_SIG109_IN_SEL_M  (BIT(6))
+#define GPIO_SIG109_IN_SEL_V  0x1
+#define GPIO_SIG109_IN_SEL_S  6
+/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC109_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC109_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC109_IN_INV_SEL_V  0x1
+#define GPIO_FUNC109_IN_INV_SEL_S  5
+/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC109_IN_SEL  0x0000001F
+#define GPIO_FUNC109_IN_SEL_M  ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S))
+#define GPIO_FUNC109_IN_SEL_V  0x1F
+#define GPIO_FUNC109_IN_SEL_S  0
+
+#define GPIO_FUNC110_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x30C)
+/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG110_IN_SEL  (BIT(6))
+#define GPIO_SIG110_IN_SEL_M  (BIT(6))
+#define GPIO_SIG110_IN_SEL_V  0x1
+#define GPIO_SIG110_IN_SEL_S  6
+/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC110_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC110_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC110_IN_INV_SEL_V  0x1
+#define GPIO_FUNC110_IN_INV_SEL_S  5
+/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC110_IN_SEL  0x0000001F
+#define GPIO_FUNC110_IN_SEL_M  ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S))
+#define GPIO_FUNC110_IN_SEL_V  0x1F
+#define GPIO_FUNC110_IN_SEL_S  0
+
+#define GPIO_FUNC111_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x310)
+/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG111_IN_SEL  (BIT(6))
+#define GPIO_SIG111_IN_SEL_M  (BIT(6))
+#define GPIO_SIG111_IN_SEL_V  0x1
+#define GPIO_SIG111_IN_SEL_S  6
+/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC111_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC111_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC111_IN_INV_SEL_V  0x1
+#define GPIO_FUNC111_IN_INV_SEL_S  5
+/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC111_IN_SEL  0x0000001F
+#define GPIO_FUNC111_IN_SEL_M  ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S))
+#define GPIO_FUNC111_IN_SEL_V  0x1F
+#define GPIO_FUNC111_IN_SEL_S  0
+
+#define GPIO_FUNC112_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x314)
+/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG112_IN_SEL  (BIT(6))
+#define GPIO_SIG112_IN_SEL_M  (BIT(6))
+#define GPIO_SIG112_IN_SEL_V  0x1
+#define GPIO_SIG112_IN_SEL_S  6
+/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC112_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC112_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC112_IN_INV_SEL_V  0x1
+#define GPIO_FUNC112_IN_INV_SEL_S  5
+/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC112_IN_SEL  0x0000001F
+#define GPIO_FUNC112_IN_SEL_M  ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S))
+#define GPIO_FUNC112_IN_SEL_V  0x1F
+#define GPIO_FUNC112_IN_SEL_S  0
+
+#define GPIO_FUNC113_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x318)
+/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG113_IN_SEL  (BIT(6))
+#define GPIO_SIG113_IN_SEL_M  (BIT(6))
+#define GPIO_SIG113_IN_SEL_V  0x1
+#define GPIO_SIG113_IN_SEL_S  6
+/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC113_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC113_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC113_IN_INV_SEL_V  0x1
+#define GPIO_FUNC113_IN_INV_SEL_S  5
+/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC113_IN_SEL  0x0000001F
+#define GPIO_FUNC113_IN_SEL_M  ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S))
+#define GPIO_FUNC113_IN_SEL_V  0x1F
+#define GPIO_FUNC113_IN_SEL_S  0
+
+#define GPIO_FUNC114_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x31C)
+/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG114_IN_SEL  (BIT(6))
+#define GPIO_SIG114_IN_SEL_M  (BIT(6))
+#define GPIO_SIG114_IN_SEL_V  0x1
+#define GPIO_SIG114_IN_SEL_S  6
+/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC114_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC114_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC114_IN_INV_SEL_V  0x1
+#define GPIO_FUNC114_IN_INV_SEL_S  5
+/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC114_IN_SEL  0x0000001F
+#define GPIO_FUNC114_IN_SEL_M  ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S))
+#define GPIO_FUNC114_IN_SEL_V  0x1F
+#define GPIO_FUNC114_IN_SEL_S  0
+
+#define GPIO_FUNC115_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x320)
+/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG115_IN_SEL  (BIT(6))
+#define GPIO_SIG115_IN_SEL_M  (BIT(6))
+#define GPIO_SIG115_IN_SEL_V  0x1
+#define GPIO_SIG115_IN_SEL_S  6
+/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC115_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC115_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC115_IN_INV_SEL_V  0x1
+#define GPIO_FUNC115_IN_INV_SEL_S  5
+/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC115_IN_SEL  0x0000001F
+#define GPIO_FUNC115_IN_SEL_M  ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S))
+#define GPIO_FUNC115_IN_SEL_V  0x1F
+#define GPIO_FUNC115_IN_SEL_S  0
+
+#define GPIO_FUNC116_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x324)
+/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG116_IN_SEL  (BIT(6))
+#define GPIO_SIG116_IN_SEL_M  (BIT(6))
+#define GPIO_SIG116_IN_SEL_V  0x1
+#define GPIO_SIG116_IN_SEL_S  6
+/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC116_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC116_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC116_IN_INV_SEL_V  0x1
+#define GPIO_FUNC116_IN_INV_SEL_S  5
+/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC116_IN_SEL  0x0000001F
+#define GPIO_FUNC116_IN_SEL_M  ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S))
+#define GPIO_FUNC116_IN_SEL_V  0x1F
+#define GPIO_FUNC116_IN_SEL_S  0
+
+#define GPIO_FUNC117_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x328)
+/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG117_IN_SEL  (BIT(6))
+#define GPIO_SIG117_IN_SEL_M  (BIT(6))
+#define GPIO_SIG117_IN_SEL_V  0x1
+#define GPIO_SIG117_IN_SEL_S  6
+/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC117_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC117_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC117_IN_INV_SEL_V  0x1
+#define GPIO_FUNC117_IN_INV_SEL_S  5
+/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC117_IN_SEL  0x0000001F
+#define GPIO_FUNC117_IN_SEL_M  ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S))
+#define GPIO_FUNC117_IN_SEL_V  0x1F
+#define GPIO_FUNC117_IN_SEL_S  0
+
+#define GPIO_FUNC118_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x32C)
+/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG118_IN_SEL  (BIT(6))
+#define GPIO_SIG118_IN_SEL_M  (BIT(6))
+#define GPIO_SIG118_IN_SEL_V  0x1
+#define GPIO_SIG118_IN_SEL_S  6
+/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC118_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC118_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC118_IN_INV_SEL_V  0x1
+#define GPIO_FUNC118_IN_INV_SEL_S  5
+/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC118_IN_SEL  0x0000001F
+#define GPIO_FUNC118_IN_SEL_M  ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S))
+#define GPIO_FUNC118_IN_SEL_V  0x1F
+#define GPIO_FUNC118_IN_SEL_S  0
+
+#define GPIO_FUNC119_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x330)
+/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG119_IN_SEL  (BIT(6))
+#define GPIO_SIG119_IN_SEL_M  (BIT(6))
+#define GPIO_SIG119_IN_SEL_V  0x1
+#define GPIO_SIG119_IN_SEL_S  6
+/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC119_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC119_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC119_IN_INV_SEL_V  0x1
+#define GPIO_FUNC119_IN_INV_SEL_S  5
+/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC119_IN_SEL  0x0000001F
+#define GPIO_FUNC119_IN_SEL_M  ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S))
+#define GPIO_FUNC119_IN_SEL_V  0x1F
+#define GPIO_FUNC119_IN_SEL_S  0
+
+#define GPIO_FUNC120_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x334)
+/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG120_IN_SEL  (BIT(6))
+#define GPIO_SIG120_IN_SEL_M  (BIT(6))
+#define GPIO_SIG120_IN_SEL_V  0x1
+#define GPIO_SIG120_IN_SEL_S  6
+/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC120_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC120_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC120_IN_INV_SEL_V  0x1
+#define GPIO_FUNC120_IN_INV_SEL_S  5
+/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC120_IN_SEL  0x0000001F
+#define GPIO_FUNC120_IN_SEL_M  ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S))
+#define GPIO_FUNC120_IN_SEL_V  0x1F
+#define GPIO_FUNC120_IN_SEL_S  0
+
+#define GPIO_FUNC121_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x338)
+/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG121_IN_SEL  (BIT(6))
+#define GPIO_SIG121_IN_SEL_M  (BIT(6))
+#define GPIO_SIG121_IN_SEL_V  0x1
+#define GPIO_SIG121_IN_SEL_S  6
+/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC121_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC121_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC121_IN_INV_SEL_V  0x1
+#define GPIO_FUNC121_IN_INV_SEL_S  5
+/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC121_IN_SEL  0x0000001F
+#define GPIO_FUNC121_IN_SEL_M  ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S))
+#define GPIO_FUNC121_IN_SEL_V  0x1F
+#define GPIO_FUNC121_IN_SEL_S  0
+
+#define GPIO_FUNC122_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x33C)
+/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG122_IN_SEL  (BIT(6))
+#define GPIO_SIG122_IN_SEL_M  (BIT(6))
+#define GPIO_SIG122_IN_SEL_V  0x1
+#define GPIO_SIG122_IN_SEL_S  6
+/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC122_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC122_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC122_IN_INV_SEL_V  0x1
+#define GPIO_FUNC122_IN_INV_SEL_S  5
+/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC122_IN_SEL  0x0000001F
+#define GPIO_FUNC122_IN_SEL_M  ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S))
+#define GPIO_FUNC122_IN_SEL_V  0x1F
+#define GPIO_FUNC122_IN_SEL_S  0
+
+#define GPIO_FUNC123_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x340)
+/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG123_IN_SEL  (BIT(6))
+#define GPIO_SIG123_IN_SEL_M  (BIT(6))
+#define GPIO_SIG123_IN_SEL_V  0x1
+#define GPIO_SIG123_IN_SEL_S  6
+/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC123_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC123_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC123_IN_INV_SEL_V  0x1
+#define GPIO_FUNC123_IN_INV_SEL_S  5
+/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC123_IN_SEL  0x0000001F
+#define GPIO_FUNC123_IN_SEL_M  ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S))
+#define GPIO_FUNC123_IN_SEL_V  0x1F
+#define GPIO_FUNC123_IN_SEL_S  0
+
+#define GPIO_FUNC124_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x344)
+/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG124_IN_SEL  (BIT(6))
+#define GPIO_SIG124_IN_SEL_M  (BIT(6))
+#define GPIO_SIG124_IN_SEL_V  0x1
+#define GPIO_SIG124_IN_SEL_S  6
+/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC124_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC124_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC124_IN_INV_SEL_V  0x1
+#define GPIO_FUNC124_IN_INV_SEL_S  5
+/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC124_IN_SEL  0x0000001F
+#define GPIO_FUNC124_IN_SEL_M  ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S))
+#define GPIO_FUNC124_IN_SEL_V  0x1F
+#define GPIO_FUNC124_IN_SEL_S  0
+
+#define GPIO_FUNC125_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x348)
+/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG125_IN_SEL  (BIT(6))
+#define GPIO_SIG125_IN_SEL_M  (BIT(6))
+#define GPIO_SIG125_IN_SEL_V  0x1
+#define GPIO_SIG125_IN_SEL_S  6
+/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC125_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC125_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC125_IN_INV_SEL_V  0x1
+#define GPIO_FUNC125_IN_INV_SEL_S  5
+/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC125_IN_SEL  0x0000001F
+#define GPIO_FUNC125_IN_SEL_M  ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S))
+#define GPIO_FUNC125_IN_SEL_V  0x1F
+#define GPIO_FUNC125_IN_SEL_S  0
+
+#define GPIO_FUNC126_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x34C)
+/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG126_IN_SEL  (BIT(6))
+#define GPIO_SIG126_IN_SEL_M  (BIT(6))
+#define GPIO_SIG126_IN_SEL_V  0x1
+#define GPIO_SIG126_IN_SEL_S  6
+/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC126_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC126_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC126_IN_INV_SEL_V  0x1
+#define GPIO_FUNC126_IN_INV_SEL_S  5
+/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC126_IN_SEL  0x0000001F
+#define GPIO_FUNC126_IN_SEL_M  ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S))
+#define GPIO_FUNC126_IN_SEL_V  0x1F
+#define GPIO_FUNC126_IN_SEL_S  0
+
+#define GPIO_FUNC127_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x350)
+/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG127_IN_SEL  (BIT(6))
+#define GPIO_SIG127_IN_SEL_M  (BIT(6))
+#define GPIO_SIG127_IN_SEL_V  0x1
+#define GPIO_SIG127_IN_SEL_S  6
+/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC127_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC127_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC127_IN_INV_SEL_V  0x1
+#define GPIO_FUNC127_IN_INV_SEL_S  5
+/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC127_IN_SEL  0x0000001F
+#define GPIO_FUNC127_IN_SEL_M  ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S))
+#define GPIO_FUNC127_IN_SEL_V  0x1F
+#define GPIO_FUNC127_IN_SEL_S  0
+
+#define GPIO_FUNC0_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x554)
+/* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC0_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC0_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC0_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC0_OEN_INV_SEL_S  10
+/* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC0_OEN_SEL  (BIT(9))
+#define GPIO_FUNC0_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC0_OEN_SEL_V  0x1
+#define GPIO_FUNC0_OEN_SEL_S  9
+/* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC0_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC0_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC0_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC0_OUT_INV_SEL_S  8
+/* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC0_OUT_SEL  0x000000FF
+#define GPIO_FUNC0_OUT_SEL_M  ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S))
+#define GPIO_FUNC0_OUT_SEL_V  0xFF
+#define GPIO_FUNC0_OUT_SEL_S  0
+
+#define GPIO_FUNC1_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x558)
+/* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC1_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC1_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC1_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC1_OEN_INV_SEL_S  10
+/* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC1_OEN_SEL  (BIT(9))
+#define GPIO_FUNC1_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC1_OEN_SEL_V  0x1
+#define GPIO_FUNC1_OEN_SEL_S  9
+/* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC1_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC1_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC1_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC1_OUT_INV_SEL_S  8
+/* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC1_OUT_SEL  0x000000FF
+#define GPIO_FUNC1_OUT_SEL_M  ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S))
+#define GPIO_FUNC1_OUT_SEL_V  0xFF
+#define GPIO_FUNC1_OUT_SEL_S  0
+
+#define GPIO_FUNC2_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x55C)
+/* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC2_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC2_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC2_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC2_OEN_INV_SEL_S  10
+/* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC2_OEN_SEL  (BIT(9))
+#define GPIO_FUNC2_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC2_OEN_SEL_V  0x1
+#define GPIO_FUNC2_OEN_SEL_S  9
+/* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC2_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC2_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC2_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC2_OUT_INV_SEL_S  8
+/* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC2_OUT_SEL  0x000000FF
+#define GPIO_FUNC2_OUT_SEL_M  ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S))
+#define GPIO_FUNC2_OUT_SEL_V  0xFF
+#define GPIO_FUNC2_OUT_SEL_S  0
+
+#define GPIO_FUNC3_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x560)
+/* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC3_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC3_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC3_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC3_OEN_INV_SEL_S  10
+/* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC3_OEN_SEL  (BIT(9))
+#define GPIO_FUNC3_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC3_OEN_SEL_V  0x1
+#define GPIO_FUNC3_OEN_SEL_S  9
+/* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC3_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC3_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC3_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC3_OUT_INV_SEL_S  8
+/* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC3_OUT_SEL  0x000000FF
+#define GPIO_FUNC3_OUT_SEL_M  ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S))
+#define GPIO_FUNC3_OUT_SEL_V  0xFF
+#define GPIO_FUNC3_OUT_SEL_S  0
+
+#define GPIO_FUNC4_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x564)
+/* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC4_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC4_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC4_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC4_OEN_INV_SEL_S  10
+/* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC4_OEN_SEL  (BIT(9))
+#define GPIO_FUNC4_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC4_OEN_SEL_V  0x1
+#define GPIO_FUNC4_OEN_SEL_S  9
+/* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC4_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC4_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC4_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC4_OUT_INV_SEL_S  8
+/* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC4_OUT_SEL  0x000000FF
+#define GPIO_FUNC4_OUT_SEL_M  ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S))
+#define GPIO_FUNC4_OUT_SEL_V  0xFF
+#define GPIO_FUNC4_OUT_SEL_S  0
+
+#define GPIO_FUNC5_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x568)
+/* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC5_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC5_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC5_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC5_OEN_INV_SEL_S  10
+/* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC5_OEN_SEL  (BIT(9))
+#define GPIO_FUNC5_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC5_OEN_SEL_V  0x1
+#define GPIO_FUNC5_OEN_SEL_S  9
+/* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC5_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC5_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC5_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC5_OUT_INV_SEL_S  8
+/* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC5_OUT_SEL  0x000000FF
+#define GPIO_FUNC5_OUT_SEL_M  ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S))
+#define GPIO_FUNC5_OUT_SEL_V  0xFF
+#define GPIO_FUNC5_OUT_SEL_S  0
+
+#define GPIO_FUNC6_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x56C)
+/* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC6_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC6_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC6_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC6_OEN_INV_SEL_S  10
+/* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC6_OEN_SEL  (BIT(9))
+#define GPIO_FUNC6_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC6_OEN_SEL_V  0x1
+#define GPIO_FUNC6_OEN_SEL_S  9
+/* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC6_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC6_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC6_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC6_OUT_INV_SEL_S  8
+/* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC6_OUT_SEL  0x000000FF
+#define GPIO_FUNC6_OUT_SEL_M  ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S))
+#define GPIO_FUNC6_OUT_SEL_V  0xFF
+#define GPIO_FUNC6_OUT_SEL_S  0
+
+#define GPIO_FUNC7_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x570)
+/* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC7_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC7_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC7_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC7_OEN_INV_SEL_S  10
+/* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC7_OEN_SEL  (BIT(9))
+#define GPIO_FUNC7_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC7_OEN_SEL_V  0x1
+#define GPIO_FUNC7_OEN_SEL_S  9
+/* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC7_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC7_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC7_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC7_OUT_INV_SEL_S  8
+/* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC7_OUT_SEL  0x000000FF
+#define GPIO_FUNC7_OUT_SEL_M  ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S))
+#define GPIO_FUNC7_OUT_SEL_V  0xFF
+#define GPIO_FUNC7_OUT_SEL_S  0
+
+#define GPIO_FUNC8_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x574)
+/* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC8_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC8_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC8_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC8_OEN_INV_SEL_S  10
+/* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC8_OEN_SEL  (BIT(9))
+#define GPIO_FUNC8_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC8_OEN_SEL_V  0x1
+#define GPIO_FUNC8_OEN_SEL_S  9
+/* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC8_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC8_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC8_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC8_OUT_INV_SEL_S  8
+/* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC8_OUT_SEL  0x000000FF
+#define GPIO_FUNC8_OUT_SEL_M  ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S))
+#define GPIO_FUNC8_OUT_SEL_V  0xFF
+#define GPIO_FUNC8_OUT_SEL_S  0
+
+#define GPIO_FUNC9_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x578)
+/* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC9_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC9_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC9_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC9_OEN_INV_SEL_S  10
+/* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC9_OEN_SEL  (BIT(9))
+#define GPIO_FUNC9_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC9_OEN_SEL_V  0x1
+#define GPIO_FUNC9_OEN_SEL_S  9
+/* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC9_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC9_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC9_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC9_OUT_INV_SEL_S  8
+/* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC9_OUT_SEL  0x000000FF
+#define GPIO_FUNC9_OUT_SEL_M  ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S))
+#define GPIO_FUNC9_OUT_SEL_V  0xFF
+#define GPIO_FUNC9_OUT_SEL_S  0
+
+#define GPIO_FUNC10_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x57C)
+/* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC10_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC10_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC10_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC10_OEN_INV_SEL_S  10
+/* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC10_OEN_SEL  (BIT(9))
+#define GPIO_FUNC10_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC10_OEN_SEL_V  0x1
+#define GPIO_FUNC10_OEN_SEL_S  9
+/* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC10_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC10_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC10_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC10_OUT_INV_SEL_S  8
+/* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC10_OUT_SEL  0x000000FF
+#define GPIO_FUNC10_OUT_SEL_M  ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S))
+#define GPIO_FUNC10_OUT_SEL_V  0xFF
+#define GPIO_FUNC10_OUT_SEL_S  0
+
+#define GPIO_FUNC11_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x580)
+/* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC11_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC11_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC11_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC11_OEN_INV_SEL_S  10
+/* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC11_OEN_SEL  (BIT(9))
+#define GPIO_FUNC11_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC11_OEN_SEL_V  0x1
+#define GPIO_FUNC11_OEN_SEL_S  9
+/* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC11_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC11_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC11_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC11_OUT_INV_SEL_S  8
+/* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC11_OUT_SEL  0x000000FF
+#define GPIO_FUNC11_OUT_SEL_M  ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S))
+#define GPIO_FUNC11_OUT_SEL_V  0xFF
+#define GPIO_FUNC11_OUT_SEL_S  0
+
+#define GPIO_FUNC12_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x584)
+/* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC12_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC12_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC12_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC12_OEN_INV_SEL_S  10
+/* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC12_OEN_SEL  (BIT(9))
+#define GPIO_FUNC12_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC12_OEN_SEL_V  0x1
+#define GPIO_FUNC12_OEN_SEL_S  9
+/* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC12_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC12_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC12_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC12_OUT_INV_SEL_S  8
+/* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC12_OUT_SEL  0x000000FF
+#define GPIO_FUNC12_OUT_SEL_M  ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S))
+#define GPIO_FUNC12_OUT_SEL_V  0xFF
+#define GPIO_FUNC12_OUT_SEL_S  0
+
+#define GPIO_FUNC13_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x588)
+/* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC13_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC13_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC13_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC13_OEN_INV_SEL_S  10
+/* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC13_OEN_SEL  (BIT(9))
+#define GPIO_FUNC13_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC13_OEN_SEL_V  0x1
+#define GPIO_FUNC13_OEN_SEL_S  9
+/* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC13_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC13_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC13_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC13_OUT_INV_SEL_S  8
+/* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC13_OUT_SEL  0x000000FF
+#define GPIO_FUNC13_OUT_SEL_M  ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S))
+#define GPIO_FUNC13_OUT_SEL_V  0xFF
+#define GPIO_FUNC13_OUT_SEL_S  0
+
+#define GPIO_FUNC14_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x58C)
+/* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC14_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC14_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC14_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC14_OEN_INV_SEL_S  10
+/* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC14_OEN_SEL  (BIT(9))
+#define GPIO_FUNC14_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC14_OEN_SEL_V  0x1
+#define GPIO_FUNC14_OEN_SEL_S  9
+/* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC14_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC14_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC14_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC14_OUT_INV_SEL_S  8
+/* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC14_OUT_SEL  0x000000FF
+#define GPIO_FUNC14_OUT_SEL_M  ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S))
+#define GPIO_FUNC14_OUT_SEL_V  0xFF
+#define GPIO_FUNC14_OUT_SEL_S  0
+
+#define GPIO_FUNC15_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x590)
+/* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC15_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC15_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC15_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC15_OEN_INV_SEL_S  10
+/* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC15_OEN_SEL  (BIT(9))
+#define GPIO_FUNC15_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC15_OEN_SEL_V  0x1
+#define GPIO_FUNC15_OEN_SEL_S  9
+/* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC15_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC15_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC15_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC15_OUT_INV_SEL_S  8
+/* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC15_OUT_SEL  0x000000FF
+#define GPIO_FUNC15_OUT_SEL_M  ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S))
+#define GPIO_FUNC15_OUT_SEL_V  0xFF
+#define GPIO_FUNC15_OUT_SEL_S  0
+
+#define GPIO_FUNC16_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x594)
+/* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC16_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC16_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC16_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC16_OEN_INV_SEL_S  10
+/* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC16_OEN_SEL  (BIT(9))
+#define GPIO_FUNC16_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC16_OEN_SEL_V  0x1
+#define GPIO_FUNC16_OEN_SEL_S  9
+/* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC16_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC16_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC16_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC16_OUT_INV_SEL_S  8
+/* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC16_OUT_SEL  0x000000FF
+#define GPIO_FUNC16_OUT_SEL_M  ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S))
+#define GPIO_FUNC16_OUT_SEL_V  0xFF
+#define GPIO_FUNC16_OUT_SEL_S  0
+
+#define GPIO_FUNC17_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x598)
+/* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC17_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC17_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC17_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC17_OEN_INV_SEL_S  10
+/* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC17_OEN_SEL  (BIT(9))
+#define GPIO_FUNC17_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC17_OEN_SEL_V  0x1
+#define GPIO_FUNC17_OEN_SEL_S  9
+/* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC17_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC17_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC17_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC17_OUT_INV_SEL_S  8
+/* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC17_OUT_SEL  0x000000FF
+#define GPIO_FUNC17_OUT_SEL_M  ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S))
+#define GPIO_FUNC17_OUT_SEL_V  0xFF
+#define GPIO_FUNC17_OUT_SEL_S  0
+
+#define GPIO_FUNC18_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x59C)
+/* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC18_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC18_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC18_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC18_OEN_INV_SEL_S  10
+/* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC18_OEN_SEL  (BIT(9))
+#define GPIO_FUNC18_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC18_OEN_SEL_V  0x1
+#define GPIO_FUNC18_OEN_SEL_S  9
+/* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC18_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC18_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC18_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC18_OUT_INV_SEL_S  8
+/* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC18_OUT_SEL  0x000000FF
+#define GPIO_FUNC18_OUT_SEL_M  ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S))
+#define GPIO_FUNC18_OUT_SEL_V  0xFF
+#define GPIO_FUNC18_OUT_SEL_S  0
+
+#define GPIO_FUNC19_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5A0)
+/* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC19_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC19_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC19_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC19_OEN_INV_SEL_S  10
+/* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC19_OEN_SEL  (BIT(9))
+#define GPIO_FUNC19_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC19_OEN_SEL_V  0x1
+#define GPIO_FUNC19_OEN_SEL_S  9
+/* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC19_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC19_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC19_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC19_OUT_INV_SEL_S  8
+/* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC19_OUT_SEL  0x000000FF
+#define GPIO_FUNC19_OUT_SEL_M  ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S))
+#define GPIO_FUNC19_OUT_SEL_V  0xFF
+#define GPIO_FUNC19_OUT_SEL_S  0
+
+#define GPIO_FUNC20_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5A4)
+/* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC20_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC20_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC20_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC20_OEN_INV_SEL_S  10
+/* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC20_OEN_SEL  (BIT(9))
+#define GPIO_FUNC20_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC20_OEN_SEL_V  0x1
+#define GPIO_FUNC20_OEN_SEL_S  9
+/* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC20_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC20_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC20_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC20_OUT_INV_SEL_S  8
+/* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC20_OUT_SEL  0x000000FF
+#define GPIO_FUNC20_OUT_SEL_M  ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S))
+#define GPIO_FUNC20_OUT_SEL_V  0xFF
+#define GPIO_FUNC20_OUT_SEL_S  0
+
+#define GPIO_FUNC21_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5A8)
+/* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC21_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC21_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC21_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC21_OEN_INV_SEL_S  10
+/* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC21_OEN_SEL  (BIT(9))
+#define GPIO_FUNC21_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC21_OEN_SEL_V  0x1
+#define GPIO_FUNC21_OEN_SEL_S  9
+/* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC21_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC21_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC21_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC21_OUT_INV_SEL_S  8
+/* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC21_OUT_SEL  0x000000FF
+#define GPIO_FUNC21_OUT_SEL_M  ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S))
+#define GPIO_FUNC21_OUT_SEL_V  0xFF
+#define GPIO_FUNC21_OUT_SEL_S  0
+
+#define GPIO_FUNC22_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5AC)
+/* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC22_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC22_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC22_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC22_OEN_INV_SEL_S  10
+/* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC22_OEN_SEL  (BIT(9))
+#define GPIO_FUNC22_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC22_OEN_SEL_V  0x1
+#define GPIO_FUNC22_OEN_SEL_S  9
+/* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC22_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC22_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC22_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC22_OUT_INV_SEL_S  8
+/* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC22_OUT_SEL  0x000000FF
+#define GPIO_FUNC22_OUT_SEL_M  ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S))
+#define GPIO_FUNC22_OUT_SEL_V  0xFF
+#define GPIO_FUNC22_OUT_SEL_S  0
+
+#define GPIO_FUNC23_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5B0)
+/* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC23_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC23_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC23_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC23_OEN_INV_SEL_S  10
+/* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC23_OEN_SEL  (BIT(9))
+#define GPIO_FUNC23_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC23_OEN_SEL_V  0x1
+#define GPIO_FUNC23_OEN_SEL_S  9
+/* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC23_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC23_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC23_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC23_OUT_INV_SEL_S  8
+/* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC23_OUT_SEL  0x000000FF
+#define GPIO_FUNC23_OUT_SEL_M  ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S))
+#define GPIO_FUNC23_OUT_SEL_V  0xFF
+#define GPIO_FUNC23_OUT_SEL_S  0
+
+#define GPIO_FUNC24_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5B4)
+/* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC24_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC24_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC24_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC24_OEN_INV_SEL_S  10
+/* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC24_OEN_SEL  (BIT(9))
+#define GPIO_FUNC24_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC24_OEN_SEL_V  0x1
+#define GPIO_FUNC24_OEN_SEL_S  9
+/* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC24_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC24_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC24_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC24_OUT_INV_SEL_S  8
+/* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC24_OUT_SEL  0x000000FF
+#define GPIO_FUNC24_OUT_SEL_M  ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S))
+#define GPIO_FUNC24_OUT_SEL_V  0xFF
+#define GPIO_FUNC24_OUT_SEL_S  0
+
+#define GPIO_FUNC25_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5B8)
+/* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC25_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC25_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC25_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC25_OEN_INV_SEL_S  10
+/* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC25_OEN_SEL  (BIT(9))
+#define GPIO_FUNC25_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC25_OEN_SEL_V  0x1
+#define GPIO_FUNC25_OEN_SEL_S  9
+/* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC25_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC25_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC25_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC25_OUT_INV_SEL_S  8
+/* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC25_OUT_SEL  0x000000FF
+#define GPIO_FUNC25_OUT_SEL_M  ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S))
+#define GPIO_FUNC25_OUT_SEL_V  0xFF
+#define GPIO_FUNC25_OUT_SEL_S  0
+
+#define GPIO_CLOCK_GATE_REG          (DR_REG_GPIO_BASE + 0x62C)
+/* GPIO_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define GPIO_CLK_EN  (BIT(0))
+#define GPIO_CLK_EN_M  (BIT(0))
+#define GPIO_CLK_EN_V  0x1
+#define GPIO_CLK_EN_S  0
+
+#define GPIO_DATE_REG          (DR_REG_GPIO_BASE + 0x6FC)
+/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006130 ; */
+/*description: */
+#define GPIO_DATE  0x0FFFFFFF
+#define GPIO_DATE_M  ((GPIO_DATE_V)<<(GPIO_DATE_S))
+#define GPIO_DATE_V  0xFFFFFFF
+#define GPIO_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_GPIO_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/gpio_sd_reg.h b/components/soc/esp32c3/include/soc/gpio_sd_reg.h
new file mode 100644
index 0000000000..e1293c918d
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/gpio_sd_reg.h
@@ -0,0 +1,114 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_GPIO_SD_REG_H_
+#define _SOC_GPIO_SD_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define GPIO_SIGMADELTA0_REG          (DR_REG_GPIO_SD_BASE + 0x0000)
+/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD0_PRESCALE  0x000000FF
+#define GPIO_SD0_PRESCALE_M  ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S))
+#define GPIO_SD0_PRESCALE_V  0xFF
+#define GPIO_SD0_PRESCALE_S  8
+/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD0_IN  0x000000FF
+#define GPIO_SD0_IN_M  ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S))
+#define GPIO_SD0_IN_V  0xFF
+#define GPIO_SD0_IN_S  0
+
+#define GPIO_SIGMADELTA1_REG          (DR_REG_GPIO_SD_BASE + 0x0004)
+/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD1_PRESCALE  0x000000FF
+#define GPIO_SD1_PRESCALE_M  ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S))
+#define GPIO_SD1_PRESCALE_V  0xFF
+#define GPIO_SD1_PRESCALE_S  8
+/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD1_IN  0x000000FF
+#define GPIO_SD1_IN_M  ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S))
+#define GPIO_SD1_IN_V  0xFF
+#define GPIO_SD1_IN_S  0
+
+#define GPIO_SIGMADELTA2_REG          (DR_REG_GPIO_SD_BASE + 0x0008)
+/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD2_PRESCALE  0x000000FF
+#define GPIO_SD2_PRESCALE_M  ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S))
+#define GPIO_SD2_PRESCALE_V  0xFF
+#define GPIO_SD2_PRESCALE_S  8
+/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD2_IN  0x000000FF
+#define GPIO_SD2_IN_M  ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S))
+#define GPIO_SD2_IN_V  0xFF
+#define GPIO_SD2_IN_S  0
+
+#define GPIO_SIGMADELTA3_REG          (DR_REG_GPIO_SD_BASE + 0x000c)
+/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD3_PRESCALE  0x000000FF
+#define GPIO_SD3_PRESCALE_M  ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S))
+#define GPIO_SD3_PRESCALE_V  0xFF
+#define GPIO_SD3_PRESCALE_S  8
+/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD3_IN  0x000000FF
+#define GPIO_SD3_IN_M  ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S))
+#define GPIO_SD3_IN_V  0xFF
+#define GPIO_SD3_IN_S  0
+
+#define GPIO_SIGMADELTA_CG_REG          (DR_REG_GPIO_SD_BASE + 0x0020)
+/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SD_CLK_EN  (BIT(31))
+#define GPIO_SD_CLK_EN_M  (BIT(31))
+#define GPIO_SD_CLK_EN_V  0x1
+#define GPIO_SD_CLK_EN_S  31
+
+#define GPIO_SIGMADELTA_MISC_REG          (DR_REG_GPIO_SD_BASE + 0x0024)
+/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SPI_SWAP  (BIT(31))
+#define GPIO_SPI_SWAP_M  (BIT(31))
+#define GPIO_SPI_SWAP_V  0x1
+#define GPIO_SPI_SWAP_S  31
+/* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: */
+#define GPIO_FUNCTION_CLK_EN  (BIT(30))
+#define GPIO_FUNCTION_CLK_EN_M  (BIT(30))
+#define GPIO_FUNCTION_CLK_EN_V  0x1
+#define GPIO_FUNCTION_CLK_EN_S  30
+
+#define GPIO_SIGMADELTA_VERSION_REG          (DR_REG_GPIO_SD_BASE + 0x0028)
+/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006230 ; */
+/*description: */
+#define GPIO_SD_DATE  0x0FFFFFFF
+#define GPIO_SD_DATE_M  ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S))
+#define GPIO_SD_DATE_V  0xFFFFFFF
+#define GPIO_SD_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_GPIO_SD_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/gpio_sd_struct.h b/components/soc/esp32c3/include/soc/gpio_sd_struct.h
new file mode 100644
index 0000000000..cc73cebd03
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/gpio_sd_struct.h
@@ -0,0 +1,61 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_GPIO_SD_STRUCT_H_
+#define _SOC_GPIO_SD_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t duty:         8;
+            uint32_t prescale:     8;
+            uint32_t reserved16:  16;
+        };
+        uint32_t val;
+    } channel[4];
+    uint32_t reserved_10;
+    uint32_t reserved_14;
+    uint32_t reserved_18;
+    uint32_t reserved_1c;
+    union {
+        struct {
+            uint32_t reserved0: 31;
+            uint32_t clk_en:     1;
+        };
+        uint32_t val;
+    } cg;
+    union {
+        struct {
+            uint32_t reserved0:      30;
+            uint32_t function_clk_en: 1;
+            uint32_t spi_swap:        1;
+        };
+        uint32_t val;
+    } misc;
+    union {
+        struct {
+            uint32_t date:      28;
+            uint32_t reserved28: 4;
+        };
+        uint32_t val;
+    } version;
+} gpio_sd_dev_t;
+extern gpio_sd_dev_t SIGMADELTA;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_GPIO_SD_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/gpio_sig_map.h b/components/soc/esp32c3/include/soc/gpio_sig_map.h
new file mode 100644
index 0000000000..45be68b3e5
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/gpio_sig_map.h
@@ -0,0 +1,184 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_GPIO_SIG_MAP_H_
+#define _SOC_GPIO_SIG_MAP_H_
+
+#define SPICLK_OUT_MUX_IDX            SPICLK_OUT_IDX
+#define SPIQ_IN_IDX                   0
+#define SPIQ_OUT_IDX                  0
+#define SPID_IN_IDX                   1
+#define SPID_OUT_IDX                  1
+#define SPIHD_IN_IDX                  2
+#define SPIHD_OUT_IDX                 2
+#define SPIWP_IN_IDX                  3
+#define SPIWP_OUT_IDX                 3
+#define SPICLK_OUT_IDX                4
+#define SPICS0_OUT_IDX                5
+#define U0RXD_IN_IDX                  6
+#define U0TXD_OUT_IDX                 6
+#define U0CTS_IN_IDX                  7
+#define U0RTS_OUT_IDX                 7
+#define U0DSR_IN_IDX                  8
+#define U0DTR_OUT_IDX                 8
+#define U1RXD_IN_IDX                  9
+#define U1TXD_OUT_IDX                 9
+#define U1CTS_IN_IDX                  10
+#define U1RTS_OUT_IDX                 10
+#define U1DSR_IN_IDX                  11
+#define U1DTR_OUT_IDX                 11
+#define I2S_MCLK_IN_IDX               12
+#define I2S_MCLK_OUT_IDX              12
+#define I2SO_BCK_IN_IDX               13
+#define I2SO_BCK_OUT_IDX              13
+#define I2SO_WS_IN_IDX                14
+#define I2SO_WS_OUT_IDX               14
+#define I2SI_SD_IN_IDX                15
+#define I2SO_SD_OUT_IDX               15
+#define I2SI_BCK_IN_IDX               16
+#define I2SI_BCK_OUT_IDX              16
+#define I2SI_WS_IN_IDX                17
+#define I2SI_WS_OUT_IDX               17
+#define GPIO_BT_PRIORITY_IDX          18
+#define GPIO_WLAN_PRIO_IDX            18
+#define GPIO_BT_ACTIVE_IDX            19
+#define GPIO_WLAN_ACTIVE_IDX          19
+#define BB_DIAG0_IDX                  20
+#define BB_DIAG1_IDX                  21
+#define BB_DIAG2_IDX                  22
+#define BB_DIAG3_IDX                  23
+#define BB_DIAG4_IDX                  24
+#define BB_DIAG5_IDX                  25
+#define BB_DIAG6_IDX                  26
+#define BB_DIAG7_IDX                  27
+#define BB_DIAG8_IDX                  28
+#define BB_DIAG9_IDX                  29
+#define BB_DIAG10_IDX                 30
+#define BB_DIAG11_IDX                 31
+#define BB_DIAG12_IDX                 32
+#define BB_DIAG13_IDX                 33
+#define BB_DIAG14_IDX                 34
+#define BB_DIAG15_IDX                 35
+#define BB_DIAG16_IDX                 36
+#define BB_DIAG17_IDX                 37
+#define BB_DIAG18_IDX                 38
+#define BB_DIAG19_IDX                 39
+#define USB_EXTPHY_VP_IDX             40
+#define USB_EXTPHY_OEN_IDX            40
+#define USB_EXTPHY_VM_IDX             41
+#define USB_EXTPHY_SPEED_IDX          41
+#define USB_EXTPHY_RCV_IDX            42
+#define USB_EXTPHY_VPO_IDX            42
+#define USB_EXTPHY_VMO_IDX            43
+#define USB_EXTPHY_SUSPND_IDX         44
+#define EXT_ADC_START_IDX             45
+#define LEDC_LS_SIG_OUT0_IDX          45
+#define LEDC_LS_SIG_OUT1_IDX          46
+#define LEDC_LS_SIG_OUT2_IDX          47
+#define LEDC_LS_SIG_OUT3_IDX          48
+#define LEDC_LS_SIG_OUT4_IDX          49
+#define LEDC_LS_SIG_OUT5_IDX          50
+#define RMT_SIG_IN0_IDX               51
+#define RMT_SIG_OUT0_IDX              51
+#define RMT_SIG_IN1_IDX               52
+#define RMT_SIG_OUT1_IDX              52
+#define I2CEXT0_SCL_IN_IDX            53
+#define I2CEXT0_SCL_OUT_IDX           53
+#define I2CEXT0_SDA_IN_IDX            54
+#define I2CEXT0_SDA_OUT_IDX           54
+#define GPIO_SD0_OUT_IDX              55
+#define GPIO_SD1_OUT_IDX              56
+#define GPIO_SD2_OUT_IDX              57
+#define GPIO_SD3_OUT_IDX              58
+#define FSPICLK_IN_IDX                63
+#define FSPICLK_OUT_IDX               63
+#define FSPIQ_IN_IDX                  64
+#define FSPIQ_OUT_IDX                 64
+#define FSPID_IN_IDX                  65
+#define FSPID_OUT_IDX                 65
+#define FSPIHD_IN_IDX                 66
+#define FSPIHD_OUT_IDX                66
+#define FSPIWP_IN_IDX                 67
+#define FSPIWP_OUT_IDX                67
+#define FSPICS0_IN_IDX                68
+#define FSPICS0_OUT_IDX               68
+#define FSPICS1_OUT_IDX               69
+#define FSPICS2_OUT_IDX               70
+#define FSPICS3_OUT_IDX               71
+#define FSPICS4_OUT_IDX               72
+#define FSPICS5_OUT_IDX               73
+#define TWAI_RX_IDX                    74
+#define TWAI_TX_IDX                    74
+#define TWAI_BUS_OFF_ON_IDX            75
+#define TWAI_CLKOUT_IDX                76
+#define PCMFSYNC_IN_IDX               77
+#define BT_AUDIO0_IRQ_IDX             77
+#define PCMCLK_IN_IDX                 78
+#define BT_AUDIO1_IRQ_IDX             78
+#define PCMDIN_IDX                    79
+#define BT_AUDIO2_IRQ_IDX             79
+#define RW_WAKEUP_REQ_IDX             80
+#define BLE_AUDIO0_IRQ_IDX            80
+#define BLE_AUDIO1_IRQ_IDX            81
+#define BLE_AUDIO2_IRQ_IDX            82
+#define PCMFSYNC_OUT_IDX              83
+#define PCMCLK_OUT_IDX                84
+#define PCMDOUT_IDX                   85
+#define BLE_AUDIO_SYNC0_P_IDX         86
+#define BLE_AUDIO_SYNC1_P_IDX         87
+#define BLE_AUDIO_SYNC2_P_IDX         88
+#define ANT_SEL0_IDX                  89
+#define ANT_SEL1_IDX                  90
+#define ANT_SEL2_IDX                  91
+#define ANT_SEL3_IDX                  92
+#define ANT_SEL4_IDX                  93
+#define ANT_SEL5_IDX                  94
+#define ANT_SEL6_IDX                  95
+#define ANT_SEL7_IDX                  96
+#define SIG_IN_FUNC_97_IDX            97
+#define SIG_IN_FUNC97_IDX             97
+#define SIG_IN_FUNC_98_IDX            98
+#define SIG_IN_FUNC98_IDX             98
+#define SIG_IN_FUNC_99_IDX            99
+#define SIG_IN_FUNC99_IDX             99
+#define SIG_IN_FUNC_100_IDX           100
+#define SIG_IN_FUNC100_IDX            100
+#define SYNCERR_IDX                   101
+#define SYNCFOUND_FLAG_IDX            102
+#define EVT_CNTL_IMMEDIATE_ABORT_IDX  103
+#define LINKLBL_IDX                   104
+#define DATA_EN_IDX                   105
+#define DATA_IDX                      106
+#define PKT_TX_ON_IDX                 107
+#define PKT_RX_ON_IDX                 108
+#define RW_TX_ON_IDX                  109
+#define RW_RX_ON_IDX                  110
+#define EVT_REQ_P_IDX                 111
+#define EVT_STOP_P_IDX                112
+#define BT_MODE_ON_IDX                113
+#define GPIO_LC_DIAG0_IDX             114
+#define GPIO_LC_DIAG1_IDX             115
+#define GPIO_LC_DIAG2_IDX             116
+#define CH_IDX_IDX                    117
+#define RX_WINDOW_IDX                 118
+#define UPDATE_RX_IDX                 119
+#define RX_STATUS_IDX                 120
+#define CLK_GPIO_IDX                  121
+#define NBT_BLE_IDX                   122
+#define CLK_OUT_OUT1_IDX              123
+#define CLK_OUT_OUT2_IDX              124
+#define CLK_OUT_OUT3_IDX              125
+#define SPICS1_OUT_IDX                126
+#define SIG_GPIO_OUT_IDX              128
+#define GPIO_MAP_DATE_IDX             0x2006130
+#endif  /* _SOC_GPIO_SIG_MAP_H_ */
diff --git a/components/soc/esp32c3/include/soc/gpio_struct.h b/components/soc/esp32c3/include/soc/gpio_struct.h
new file mode 100644
index 0000000000..0dfa33f510
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/gpio_struct.h
@@ -0,0 +1,436 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_GPIO_STRUCT_H_
+#define _SOC_GPIO_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    uint32_t bt_select;                               /**/
+    union {
+        struct {
+            uint32_t data:         26;
+            uint32_t reserved26:    6;
+        };
+        uint32_t val;
+    } out;
+    union {
+        struct {
+            uint32_t out_w1ts:  26;
+            uint32_t reserved26: 6;
+        };
+        uint32_t val;
+    } out_w1ts;
+    union {
+        struct {
+            uint32_t out_w1tc:  26;
+            uint32_t reserved26: 6;
+        };
+        uint32_t val;
+    } out_w1tc;
+    uint32_t reserved_10;
+    uint32_t reserved_14;
+    uint32_t reserved_18;
+    union {
+        struct {
+            uint32_t sel:        8;
+            uint32_t reserved8: 24;
+        };
+        uint32_t val;
+    } sdio_select;
+    union {
+        struct {
+            uint32_t data:       26;
+            uint32_t reserved26:  6;
+        };
+        uint32_t val;
+    } enable;
+    union {
+        struct {
+            uint32_t enable_w1ts:26;
+            uint32_t reserved26:  6;
+        };
+        uint32_t val;
+    } enable_w1ts;
+    union {
+        struct {
+            uint32_t enable_w1tc:26;
+            uint32_t reserved26:  6;
+        };
+        uint32_t val;
+    } enable_w1tc;
+    uint32_t reserved_2c;
+    uint32_t reserved_30;
+    uint32_t reserved_34;
+    union {
+        struct {
+            uint32_t strapping: 16;
+            uint32_t reserved16:16;
+        };
+        uint32_t val;
+    } strap;
+    union {
+        struct {
+            uint32_t data:        26;
+            uint32_t reserved26:   6;
+        };
+        uint32_t val;
+    } in;
+    uint32_t reserved_40;
+    union {
+        struct {
+            uint32_t intr_st:         26;
+            uint32_t reserved26:       6;
+        };
+        uint32_t val;
+    } status;
+    union {
+        struct {
+            uint32_t status_w1ts:26;
+            uint32_t reserved26:  6;
+        };
+        uint32_t val;
+    } status_w1ts;
+    union {
+        struct {
+            uint32_t status_w1tc:26;
+            uint32_t reserved26:  6;
+        };
+        uint32_t val;
+    } status_w1tc;
+    uint32_t reserved_50;
+    uint32_t reserved_54;
+    uint32_t reserved_58;
+    union {
+        struct {
+            uint32_t intr:      26;
+            uint32_t reserved26: 6;
+        };
+        uint32_t val;
+    } pcpu_int;
+    union {
+        struct {
+            uint32_t intr:          26;
+            uint32_t reserved26:     6;
+        };
+        uint32_t val;
+    } pcpu_nmi_int;
+    union {
+        struct {
+            uint32_t intr:      26;
+            uint32_t reserved26: 6;
+        };
+        uint32_t val;
+    } cpusdio_int;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    union {
+        struct {
+            uint32_t sync2_bypass:       2;
+            uint32_t pad_driver:         1;
+            uint32_t sync1_bypass:       2;
+            uint32_t reserved5:          2;
+            uint32_t int_type:           3;
+            uint32_t wakeup_enable:      1;
+            uint32_t config:             2;
+            uint32_t int_ena:            5;
+            uint32_t reserved18:        14;
+        };
+        uint32_t val;
+    } pin[26];
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    union {
+        struct {
+            uint32_t intr_st_next:         26;
+            uint32_t reserved26:            6;
+        };
+        uint32_t val;
+    } status_next;
+    uint32_t reserved_150;
+    union {
+        struct {
+            uint32_t func_sel:         5;
+            uint32_t sig_in_inv:       1;
+            uint32_t sig_in_sel:       1;
+            uint32_t reserved7:       25;
+        };
+        uint32_t val;
+    } func_in_sel_cfg[128];
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    uint32_t reserved_3fc;
+    uint32_t reserved_400;
+    uint32_t reserved_404;
+    uint32_t reserved_408;
+    uint32_t reserved_40c;
+    uint32_t reserved_410;
+    uint32_t reserved_414;
+    uint32_t reserved_418;
+    uint32_t reserved_41c;
+    uint32_t reserved_420;
+    uint32_t reserved_424;
+    uint32_t reserved_428;
+    uint32_t reserved_42c;
+    uint32_t reserved_430;
+    uint32_t reserved_434;
+    uint32_t reserved_438;
+    uint32_t reserved_43c;
+    uint32_t reserved_440;
+    uint32_t reserved_444;
+    uint32_t reserved_448;
+    uint32_t reserved_44c;
+    uint32_t reserved_450;
+    uint32_t reserved_454;
+    uint32_t reserved_458;
+    uint32_t reserved_45c;
+    uint32_t reserved_460;
+    uint32_t reserved_464;
+    uint32_t reserved_468;
+    uint32_t reserved_46c;
+    uint32_t reserved_470;
+    uint32_t reserved_474;
+    uint32_t reserved_478;
+    uint32_t reserved_47c;
+    uint32_t reserved_480;
+    uint32_t reserved_484;
+    uint32_t reserved_488;
+    uint32_t reserved_48c;
+    uint32_t reserved_490;
+    uint32_t reserved_494;
+    uint32_t reserved_498;
+    uint32_t reserved_49c;
+    uint32_t reserved_4a0;
+    uint32_t reserved_4a4;
+    uint32_t reserved_4a8;
+    uint32_t reserved_4ac;
+    uint32_t reserved_4b0;
+    uint32_t reserved_4b4;
+    uint32_t reserved_4b8;
+    uint32_t reserved_4bc;
+    uint32_t reserved_4c0;
+    uint32_t reserved_4c4;
+    uint32_t reserved_4c8;
+    uint32_t reserved_4cc;
+    uint32_t reserved_4d0;
+    uint32_t reserved_4d4;
+    uint32_t reserved_4d8;
+    uint32_t reserved_4dc;
+    uint32_t reserved_4e0;
+    uint32_t reserved_4e4;
+    uint32_t reserved_4e8;
+    uint32_t reserved_4ec;
+    uint32_t reserved_4f0;
+    uint32_t reserved_4f4;
+    uint32_t reserved_4f8;
+    uint32_t reserved_4fc;
+    uint32_t reserved_500;
+    uint32_t reserved_504;
+    uint32_t reserved_508;
+    uint32_t reserved_50c;
+    uint32_t reserved_510;
+    uint32_t reserved_514;
+    uint32_t reserved_518;
+    uint32_t reserved_51c;
+    uint32_t reserved_520;
+    uint32_t reserved_524;
+    uint32_t reserved_528;
+    uint32_t reserved_52c;
+    uint32_t reserved_530;
+    uint32_t reserved_534;
+    uint32_t reserved_538;
+    uint32_t reserved_53c;
+    uint32_t reserved_540;
+    uint32_t reserved_544;
+    uint32_t reserved_548;
+    uint32_t reserved_54c;
+    uint32_t reserved_550;
+    union {
+        struct {
+            uint32_t func_sel:          8;
+            uint32_t inv_sel:           1;
+            uint32_t oen_sel:           1;
+            uint32_t oen_inv_sel:       1;
+            uint32_t reserved11:       21;
+        };
+        uint32_t val;
+    } func_out_sel_cfg[26];
+    uint32_t reserved_5bc;
+    uint32_t reserved_5c0;
+    uint32_t reserved_5c4;
+    uint32_t reserved_5c8;
+    uint32_t reserved_5cc;
+    uint32_t reserved_5d0;
+    uint32_t reserved_5d4;
+    uint32_t reserved_5d8;
+    uint32_t reserved_5dc;
+    uint32_t reserved_5e0;
+    uint32_t reserved_5e4;
+    uint32_t reserved_5e8;
+    uint32_t reserved_5ec;
+    uint32_t reserved_5f0;
+    uint32_t reserved_5f4;
+    uint32_t reserved_5f8;
+    uint32_t reserved_5fc;
+    uint32_t reserved_600;
+    uint32_t reserved_604;
+    uint32_t reserved_608;
+    uint32_t reserved_60c;
+    uint32_t reserved_610;
+    uint32_t reserved_614;
+    uint32_t reserved_618;
+    uint32_t reserved_61c;
+    uint32_t reserved_620;
+    uint32_t reserved_624;
+    uint32_t reserved_628;
+    union {
+        struct {
+            uint32_t clk_en:     1;
+            uint32_t reserved1: 31;
+        };
+        uint32_t val;
+    } clock_gate;
+    uint32_t reserved_630;
+    uint32_t reserved_634;
+    uint32_t reserved_638;
+    uint32_t reserved_63c;
+    uint32_t reserved_640;
+    uint32_t reserved_644;
+    uint32_t reserved_648;
+    uint32_t reserved_64c;
+    uint32_t reserved_650;
+    uint32_t reserved_654;
+    uint32_t reserved_658;
+    uint32_t reserved_65c;
+    uint32_t reserved_660;
+    uint32_t reserved_664;
+    uint32_t reserved_668;
+    uint32_t reserved_66c;
+    uint32_t reserved_670;
+    uint32_t reserved_674;
+    uint32_t reserved_678;
+    uint32_t reserved_67c;
+    uint32_t reserved_680;
+    uint32_t reserved_684;
+    uint32_t reserved_688;
+    uint32_t reserved_68c;
+    uint32_t reserved_690;
+    uint32_t reserved_694;
+    uint32_t reserved_698;
+    uint32_t reserved_69c;
+    uint32_t reserved_6a0;
+    uint32_t reserved_6a4;
+    uint32_t reserved_6a8;
+    uint32_t reserved_6ac;
+    uint32_t reserved_6b0;
+    uint32_t reserved_6b4;
+    uint32_t reserved_6b8;
+    uint32_t reserved_6bc;
+    uint32_t reserved_6c0;
+    uint32_t reserved_6c4;
+    uint32_t reserved_6c8;
+    uint32_t reserved_6cc;
+    uint32_t reserved_6d0;
+    uint32_t reserved_6d4;
+    uint32_t reserved_6d8;
+    uint32_t reserved_6dc;
+    uint32_t reserved_6e0;
+    uint32_t reserved_6e4;
+    uint32_t reserved_6e8;
+    uint32_t reserved_6ec;
+    uint32_t reserved_6f0;
+    uint32_t reserved_6f4;
+    uint32_t reserved_6f8;
+    union {
+        struct {
+            uint32_t date:      28;
+            uint32_t reserved28: 4;
+        };
+        uint32_t val;
+    } date;
+} gpio_dev_t;
+extern gpio_dev_t GPIO;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_GPIO_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/hwcrypto_reg.h b/components/soc/esp32c3/include/soc/hwcrypto_reg.h
new file mode 100644
index 0000000000..3e24b7cde3
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/hwcrypto_reg.h
@@ -0,0 +1,182 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef __HWCRYPTO_REG_H__
+#define __HWCRYPTO_REG_H__
+
+#include "soc.h"
+
+/* registers for RSA acceleration via Multiple Precision Integer ops */
+#define RSA_MEM_M_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x000)
+/* RB & Z use the same memory block, depending on phase of operation */
+#define RSA_MEM_RB_BLOCK_BASE         ((DR_REG_RSA_BASE)+0x200)
+#define RSA_MEM_Z_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x200)
+#define RSA_MEM_Y_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x400)
+#define RSA_MEM_X_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x600)
+
+/* Configuration registers */
+#define RSA_M_DASH_REG                (DR_REG_RSA_BASE + 0x800)
+#define RSA_LENGTH_REG                (DR_REG_RSA_BASE + 0x804)
+#define RSA_CONSTANT_TIME_REG         (DR_REG_RSA_BASE + 0x820)
+#define RSA_SEARCH_ENABLE_REG         (DR_REG_RSA_BASE + 0x824)
+#define RSA_SEARCH_POS_REG            (DR_REG_RSA_BASE + 0x828)
+
+/* Initialization registers */
+#define RSA_QUERY_CLEAN_REG           (DR_REG_RSA_BASE + 0x808)
+
+/* Calculation start registers */
+#define RSA_MODEXP_START_REG          (DR_REG_RSA_BASE + 0x80c)
+#define RSA_MOD_MULT_START_REG        (DR_REG_RSA_BASE + 0x810)
+#define RSA_MULT_START_REG            (DR_REG_RSA_BASE + 0x814)
+
+/* Interrupt registers */
+#define RSA_QUERY_INTERRUPT_REG       (DR_REG_RSA_BASE + 0x818)
+#define RSA_CLEAR_INTERRUPT_REG       (DR_REG_RSA_BASE + 0x81C)
+#define RSA_INTERRUPT_REG             (DR_REG_RSA_BASE + 0x82C)
+#define RSA_DATE_REG                  (DR_REG_RSA_BASE + 0x82C)
+
+#define SHA_MODE_SHA1       0
+#define SHA_MODE_SHA224     1
+#define SHA_MODE_SHA256     2
+
+/* SHA acceleration registers */
+#define SHA_MODE_REG                  ((DR_REG_SHA_BASE) + 0x00)
+#define SHA_BLOCK_NUM_REG             ((DR_REG_SHA_BASE) + 0x0C)
+#define SHA_START_REG                 ((DR_REG_SHA_BASE) + 0x10)
+#define SHA_CONTINUE_REG              ((DR_REG_SHA_BASE) + 0x14)
+#define SHA_BUSY_REG                  ((DR_REG_SHA_BASE) + 0x18)
+#define SHA_DMA_START_REG             ((DR_REG_SHA_BASE) + 0x1C)
+#define SHA_DMA_CONTINUE_REG          ((DR_REG_SHA_BASE) + 0x20)
+#define SHA_CLEAR_IRQ_REG             ((DR_REG_SHA_BASE) + 0x24)
+#define SHA_INT_ENA_REG               ((DR_REG_SHA_BASE) + 0x28)
+#define SHA_DATE_REG                  ((DR_REG_SHA_BASE) + 0x2C)
+
+#define SHA_H_BASE                    ((DR_REG_SHA_BASE) + 0x40)
+#define SHA_TEXT_BASE                 ((DR_REG_SHA_BASE) + 0x80)
+
+/* AES Block operation modes */
+#define AES_BLOCK_MODE_ECB     0
+#define AES_BLOCK_MODE_CBC     1
+#define AES_BLOCK_MODE_OFB     2
+#define AES_BLOCK_MODE_CTR     3
+#define AES_BLOCK_MODE_CFB8    4
+#define AES_BLOCK_MODE_CFB128  5
+
+/* AES Block operation modes (used with DMA) */
+#define AES_BLOCK_MODE_ECB     0
+#define AES_BLOCK_MODE_CBC     1
+#define AES_BLOCK_MODE_OFB     2
+#define AES_BLOCK_MODE_CTR     3
+#define AES_BLOCK_MODE_CFB8    4
+#define AES_BLOCK_MODE_CFB128  5
+
+/* AES acceleration registers */
+#define AES_MODE_REG            ((DR_REG_AES_BASE) + 0x40)
+#define AES_ENDIAN_REG          ((DR_REG_AES_BASE) + 0x44)
+#define AES_TRIGGER_REG         ((DR_REG_AES_BASE) + 0x48)
+#define AES_STATE_REG           ((DR_REG_AES_BASE) + 0x4c)
+#define AES_DMA_ENABLE_REG      ((DR_REG_AES_BASE) + 0x90)
+#define AES_BLOCK_MODE_REG      ((DR_REG_AES_BASE) + 0x94)
+#define AES_BLOCK_NUM_REG       ((DR_REG_AES_BASE) + 0x98)
+#define AES_INC_SEL_REG         ((DR_REG_AES_BASE) + 0x9C)
+#define AES_AAD_BLOCK_NUM_REG   ((DR_REG_AES_BASE) + 0xA0)
+#define AES_BIT_VALID_NUM_REG   ((DR_REG_AES_BASE) + 0xA4)
+#define AES_CONTINUE_REG        ((DR_REG_AES_BASE) + 0xA8)
+#define AES_INT_CLEAR_REG       ((DR_REG_AES_BASE) + 0xAC)
+#define AES_INT_ENA_REG         ((DR_REG_AES_BASE) + 0xB0)
+#define AES_DATE_REG            ((DR_REG_AES_BASE) + 0xB4)
+#define AES_DMA_EXIT_REG        ((DR_REG_AES_BASE) + 0xB8)
+
+#define AES_DMA_ENABLE_REG      ((DR_REG_AES_BASE) + 0x90)
+#define AES_BLOCK_MODE_REG      ((DR_REG_AES_BASE) + 0x94)
+#define AES_BLOCK_NUM_REG       ((DR_REG_AES_BASE) + 0x98)
+#define AES_INC_SEL_REG         ((DR_REG_AES_BASE) + 0x9C)
+#define AES_AAD_BLOCK_NUM_REG   ((DR_REG_AES_BASE) + 0xA0)
+#define AES_BIT_VALID_NUM_REG   ((DR_REG_AES_BASE) + 0xA4)
+#define AES_CONTINUE_REG        ((DR_REG_AES_BASE) + 0xA8)
+
+#define AES_KEY_BASE            ((DR_REG_AES_BASE) + 0x00)
+#define AES_TEXT_IN_BASE        ((DR_REG_AES_BASE) + 0x20)
+#define AES_TEXT_OUT_BASE       ((DR_REG_AES_BASE) + 0x30)
+#define AES_IV_BASE             ((DR_REG_AES_BASE) + 0x50)
+#define AES_H_BASE              ((DR_REG_AES_BASE) + 0x60)
+#define AES_J_BASE              ((DR_REG_AES_BASE) + 0x70)
+#define AES_T_BASE              ((DR_REG_AES_BASE) + 0x80)
+
+#define AES_INT_CLR_REG         ((DR_REG_AES_BASE) + 0xAC)
+#define AES_INT_ENA_REG         ((DR_REG_AES_BASE) + 0xB0)
+#define AES_DATE_REG            ((DR_REG_AES_BASE) + 0xB4)
+#define AES_DMA_EXIT_REG        ((DR_REG_AES_BASE) + 0xB8)
+
+/* AES_STATE_REG values */
+#define AES_STATE_IDLE 0
+#define AES_STATE_BUSY 1
+#define AES_STATE_DONE 2
+
+/* HMAC Module */
+#define HMAC_SET_START_REG             ((DR_REG_HMAC_BASE) + 0x40)
+#define HMAC_SET_PARA_PURPOSE_REG      ((DR_REG_HMAC_BASE) + 0x44)
+#define HMAC_SET_PARA_KEY_REG          ((DR_REG_HMAC_BASE) + 0x48)
+#define HMAC_SET_PARA_FINISH_REG       ((DR_REG_HMAC_BASE) + 0x4c)
+#define HMAC_SET_MESSAGE_ONE_REG       ((DR_REG_HMAC_BASE) + 0x50)
+#define HMAC_SET_MESSAGE_ING_REG       ((DR_REG_HMAC_BASE) + 0x54)
+#define HMAC_SET_MESSAGE_END_REG       ((DR_REG_HMAC_BASE) + 0x58)
+#define HMAC_SET_RESULT_FINISH_REG     ((DR_REG_HMAC_BASE) + 0x5c)
+#define HMAC_SET_INVALIDATE_JTAG_REG   ((DR_REG_HMAC_BASE) + 0x60)
+#define HMAC_SET_INVALIDATE_DS_REG     ((DR_REG_HMAC_BASE) + 0x64)
+#define HMAC_QUERY_ERROR_REG           ((DR_REG_HMAC_BASE) + 0x68)
+#define HMAC_QUERY_BUSY_REG            ((DR_REG_HMAC_BASE) + 0x6c)
+
+#define HMAC_WDATA_BASE                ((DR_REG_HMAC_BASE) + 0x80)
+#define HMAC_RDATA_BASE                ((DR_REG_HMAC_BASE) + 0xC0)
+#define HMAC_SET_MESSAGE_PAD_REG       ((DR_REG_HMAC_BASE) + 0xF0)
+#define HMAC_ONE_BLOCK_REG             ((DR_REG_HMAC_BASE) + 0xF4)
+
+#define HMAC_SOFT_JTAG_CTRL_REG        ((DR_REG_HMAC_BASE) + 0xF8)
+#define HMAC_WR_JTAG_REG               ((DR_REG_HMAC_BASE) + 0xFC)
+
+#define HMAC_DATE_REG                  ((DR_REG_HMAC_BASE) + 0xF8)
+
+
+/* AES-XTS registers */
+#define AES_XTS_PLAIN_BASE        ((DR_REG_AES_XTS_BASE) + 0x00)
+#define AES_XTS_SIZE_REG          ((DR_REG_AES_XTS_BASE) + 0x40)
+#define AES_XTS_DESTINATION_REG   ((DR_REG_AES_XTS_BASE) + 0x44)
+#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_XTS_BASE) + 0x48)
+
+#define AES_XTS_TRIGGER_REG       ((DR_REG_AES_XTS_BASE) + 0x4C)
+#define AES_XTS_RELEASE_REG       ((DR_REG_AES_XTS_BASE) + 0x50)
+#define AES_XTS_DESTROY_REG       ((DR_REG_AES_XTS_BASE) + 0x54)
+#define AES_XTS_STATE_REG         ((DR_REG_AES_XTS_BASE) + 0x58)
+#define AES_XTS_DATE_REG          ((DR_REG_AES_XTS_BASE) + 0x5C)
+
+/* Digital Signature registers*/
+#define DS_C_BASE                 ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 )
+#define DS_IV_BASE                ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x630 )
+#define DS_X_BASE                 ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x800 )
+#define DS_Z_BASE                 ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xA00 )
+
+#define DS_SET_START_REG          ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE00)
+#define DS_SET_ME_REG             ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE04)
+#define DS_SET_FINISH_REG         ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE08)
+
+#define DS_QUERY_BUSY_REG         ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE0C)
+#define DS_QUERY_KEY_WRONG_REG    ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE10)
+#define DS_QUERY_CHECK_REG        ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE14)
+
+#define DS_QUERY_CHECK_INVALID_DIGEST  (1<<0)
+#define DS_QUERY_CHECK_INVALID_PADDING (1<<1)
+
+#define DS_DATE_REG               ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE20)
+
+#endif
diff --git a/components/soc/esp32c3/include/soc/i2c_caps.h b/components/soc/esp32c3/include/soc/i2c_caps.h
new file mode 100644
index 0000000000..ae2f19e043
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/i2c_caps.h
@@ -0,0 +1,37 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// ESP32-C3 have 2 I2C.
+#define SOC_I2C_NUM            (1)
+
+#define SOC_I2C_FIFO_LEN       (32) /*!< I2C hardware FIFO depth */
+#define I2C_INTR_MASK          (0x3ffff) /*!< I2C all interrupt bitmap */
+
+//ESP32-C3 support hardware FSM reset
+#define I2C_SUPPORT_HW_FSM_RST  (1)
+//ESP32-C3 support hardware clear bus
+#define I2C_SUPPORT_HW_CLR_BUS  (1)
+
+#define SOC_I2C_SUPPORT_XTAL       (1)
+#define SOC_I2C_SUPPORT_RTC        (1)
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/include/soc/i2c_reg.h b/components/soc/esp32c3/include/soc/i2c_reg.h
new file mode 100644
index 0000000000..6a45d00827
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/i2c_reg.h
@@ -0,0 +1,1062 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_I2C_REG_H_
+#define _SOC_I2C_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define I2C_SCL_LOW_PERIOD_REG(i)          (REG_I2C_BASE(i) + 0x0)
+/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */
+/*description: .*/
+#define I2C_SCL_LOW_PERIOD    0x000001FF
+#define I2C_SCL_LOW_PERIOD_M  ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S))
+#define I2C_SCL_LOW_PERIOD_V  0x1FF
+#define I2C_SCL_LOW_PERIOD_S  0
+
+#define I2C_CTR_REG(i)          (REG_I2C_BASE(i) + 0x4)
+/* I2C_ADDR_BROADCASTING_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_ADDR_BROADCASTING_EN    (BIT(14))
+#define I2C_ADDR_BROADCASTING_EN_M  (BIT(14))
+#define I2C_ADDR_BROADCASTING_EN_V  0x1
+#define I2C_ADDR_BROADCASTING_EN_S  14
+/* I2C_ADDR_10BIT_RW_CHECK_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_ADDR_10BIT_RW_CHECK_EN    (BIT(13))
+#define I2C_ADDR_10BIT_RW_CHECK_EN_M  (BIT(13))
+#define I2C_ADDR_10BIT_RW_CHECK_EN_V  0x1
+#define I2C_ADDR_10BIT_RW_CHECK_EN_S  13
+/* I2C_SLV_TX_AUTO_START_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLV_TX_AUTO_START_EN    (BIT(12))
+#define I2C_SLV_TX_AUTO_START_EN_M  (BIT(12))
+#define I2C_SLV_TX_AUTO_START_EN_V  0x1
+#define I2C_SLV_TX_AUTO_START_EN_S  12
+/* I2C_CONF_UPGATE : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_CONF_UPGATE    (BIT(11))
+#define I2C_CONF_UPGATE_M  (BIT(11))
+#define I2C_CONF_UPGATE_V  0x1
+#define I2C_CONF_UPGATE_S  11
+/* I2C_FSM_RST : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_FSM_RST    (BIT(10))
+#define I2C_FSM_RST_M  (BIT(10))
+#define I2C_FSM_RST_V  0x1
+#define I2C_FSM_RST_S  10
+/* I2C_ARBITRATION_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: .*/
+#define I2C_ARBITRATION_EN    (BIT(9))
+#define I2C_ARBITRATION_EN_M  (BIT(9))
+#define I2C_ARBITRATION_EN_V  0x1
+#define I2C_ARBITRATION_EN_S  9
+/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_CLK_EN    (BIT(8))
+#define I2C_CLK_EN_M  (BIT(8))
+#define I2C_CLK_EN_V  0x1
+#define I2C_CLK_EN_S  8
+/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define I2C_RX_LSB_FIRST    (BIT(7))
+#define I2C_RX_LSB_FIRST_M  (BIT(7))
+#define I2C_RX_LSB_FIRST_V  0x1
+#define I2C_RX_LSB_FIRST_S  7
+/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TX_LSB_FIRST    (BIT(6))
+#define I2C_TX_LSB_FIRST_M  (BIT(6))
+#define I2C_TX_LSB_FIRST_V  0x1
+#define I2C_TX_LSB_FIRST_S  6
+/* I2C_TRANS_START : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TRANS_START    (BIT(5))
+#define I2C_TRANS_START_M  (BIT(5))
+#define I2C_TRANS_START_V  0x1
+#define I2C_TRANS_START_S  5
+/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_MS_MODE    (BIT(4))
+#define I2C_MS_MODE_M  (BIT(4))
+#define I2C_MS_MODE_V  0x1
+#define I2C_MS_MODE_S  4
+/* I2C_RX_FULL_ACK_LEVEL : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: .*/
+#define I2C_RX_FULL_ACK_LEVEL    (BIT(3))
+#define I2C_RX_FULL_ACK_LEVEL_M  (BIT(3))
+#define I2C_RX_FULL_ACK_LEVEL_V  0x1
+#define I2C_RX_FULL_ACK_LEVEL_S  3
+/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SAMPLE_SCL_LEVEL    (BIT(2))
+#define I2C_SAMPLE_SCL_LEVEL_M  (BIT(2))
+#define I2C_SAMPLE_SCL_LEVEL_V  0x1
+#define I2C_SAMPLE_SCL_LEVEL_S  2
+/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: .*/
+#define I2C_SCL_FORCE_OUT    (BIT(1))
+#define I2C_SCL_FORCE_OUT_M  (BIT(1))
+#define I2C_SCL_FORCE_OUT_V  0x1
+#define I2C_SCL_FORCE_OUT_S  1
+/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define I2C_SDA_FORCE_OUT    (BIT(0))
+#define I2C_SDA_FORCE_OUT_M  (BIT(0))
+#define I2C_SDA_FORCE_OUT_V  0x1
+#define I2C_SDA_FORCE_OUT_S  0
+
+#define I2C_SR_REG(i)          (REG_I2C_BASE(i) + 0x8)
+/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
+/*description: .*/
+#define I2C_SCL_STATE_LAST    0x00000007
+#define I2C_SCL_STATE_LAST_M  ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S))
+#define I2C_SCL_STATE_LAST_V  0x7
+#define I2C_SCL_STATE_LAST_S  28
+/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
+/*description: .*/
+#define I2C_SCL_MAIN_STATE_LAST    0x00000007
+#define I2C_SCL_MAIN_STATE_LAST_M  ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S))
+#define I2C_SCL_MAIN_STATE_LAST_V  0x7
+#define I2C_SCL_MAIN_STATE_LAST_S  24
+/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_CNT    0x0000003F
+#define I2C_TXFIFO_CNT_M  ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S))
+#define I2C_TXFIFO_CNT_V  0x3F
+#define I2C_TXFIFO_CNT_S  18
+/* I2C_STRETCH_CAUSE : RO ;bitpos:[15:14] ;default: 2'h3 ; */
+/*description: .*/
+#define I2C_STRETCH_CAUSE    0x00000003
+#define I2C_STRETCH_CAUSE_M  ((I2C_STRETCH_CAUSE_V)<<(I2C_STRETCH_CAUSE_S))
+#define I2C_STRETCH_CAUSE_V  0x3
+#define I2C_STRETCH_CAUSE_S  14
+/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_CNT    0x0000003F
+#define I2C_RXFIFO_CNT_M  ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S))
+#define I2C_RXFIFO_CNT_V  0x3F
+#define I2C_RXFIFO_CNT_S  8
+/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_ADDRESSED    (BIT(5))
+#define I2C_SLAVE_ADDRESSED_M  (BIT(5))
+#define I2C_SLAVE_ADDRESSED_V  0x1
+#define I2C_SLAVE_ADDRESSED_S  5
+/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_BUS_BUSY    (BIT(4))
+#define I2C_BUS_BUSY_M  (BIT(4))
+#define I2C_BUS_BUSY_V  0x1
+#define I2C_BUS_BUSY_S  4
+/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_ARB_LOST    (BIT(3))
+#define I2C_ARB_LOST_M  (BIT(3))
+#define I2C_ARB_LOST_V  0x1
+#define I2C_ARB_LOST_S  3
+/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_RW    (BIT(1))
+#define I2C_SLAVE_RW_M  (BIT(1))
+#define I2C_SLAVE_RW_V  0x1
+#define I2C_SLAVE_RW_S  1
+/* I2C_RESP_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RESP_REC    (BIT(0))
+#define I2C_RESP_REC_M  (BIT(0))
+#define I2C_RESP_REC_V  0x1
+#define I2C_RESP_REC_S  0
+
+#define I2C_TO_REG(i)          (REG_I2C_BASE(i) + 0xC)
+/* I2C_TIME_OUT_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TIME_OUT_EN    (BIT(5))
+#define I2C_TIME_OUT_EN_M  (BIT(5))
+#define I2C_TIME_OUT_EN_V  0x1
+#define I2C_TIME_OUT_EN_S  5
+/* I2C_TIME_OUT_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */
+/*description: .*/
+#define I2C_TIME_OUT_REG    0x0000001F
+#define I2C_TIME_OUT_REG_M  ((I2C_TIME_OUT_VALUE_V)<<(I2C_TIME_OUT_VALUE_S))
+#define I2C_TIME_OUT_REG_V  0x1F
+#define I2C_TIME_OUT_REG_S  0
+
+#define I2C_SLAVE_ADDR_REG(i)          (REG_I2C_BASE(i) + 0x10)
+/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_ADDR_10BIT_EN    (BIT(31))
+#define I2C_ADDR_10BIT_EN_M  (BIT(31))
+#define I2C_ADDR_10BIT_EN_V  0x1
+#define I2C_ADDR_10BIT_EN_S  31
+/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_ADDR    0x00007FFF
+#define I2C_SLAVE_ADDR_M  ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S))
+#define I2C_SLAVE_ADDR_V  0x7FFF
+#define I2C_SLAVE_ADDR_S  0
+
+#define I2C_FIFO_ST_REG(i)          (REG_I2C_BASE(i) + 0x14)
+/* I2C_SLAVE_RW_POINT : RO ;bitpos:[29:22] ;default: 8'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_RW_POINT    0x000000FF
+#define I2C_SLAVE_RW_POINT_M  ((I2C_SLAVE_RW_POINT_V)<<(I2C_SLAVE_RW_POINT_S))
+#define I2C_SLAVE_RW_POINT_V  0xFF
+#define I2C_SLAVE_RW_POINT_S  22
+/* I2C_TXFIFO_WADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_WADDR    0x0000001F
+#define I2C_TXFIFO_WADDR_M  ((I2C_TXFIFO_WADDR_V)<<(I2C_TXFIFO_WADDR_S))
+#define I2C_TXFIFO_WADDR_V  0x1F
+#define I2C_TXFIFO_WADDR_S  15
+/* I2C_TXFIFO_RADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_RADDR    0x0000001F
+#define I2C_TXFIFO_RADDR_M  ((I2C_TXFIFO_RADDR_V)<<(I2C_TXFIFO_RADDR_S))
+#define I2C_TXFIFO_RADDR_V  0x1F
+#define I2C_TXFIFO_RADDR_S  10
+/* I2C_RXFIFO_WADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_WADDR    0x0000001F
+#define I2C_RXFIFO_WADDR_M  ((I2C_RXFIFO_WADDR_V)<<(I2C_RXFIFO_WADDR_S))
+#define I2C_RXFIFO_WADDR_V  0x1F
+#define I2C_RXFIFO_WADDR_S  5
+/* I2C_RXFIFO_RADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_RADDR    0x0000001F
+#define I2C_RXFIFO_RADDR_M  ((I2C_RXFIFO_RADDR_V)<<(I2C_RXFIFO_RADDR_S))
+#define I2C_RXFIFO_RADDR_V  0x1F
+#define I2C_RXFIFO_RADDR_S  0
+
+#define I2C_FIFO_CONF_REG(i)          (REG_I2C_BASE(i) + 0x18)
+/* I2C_FIFO_PRT_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: .*/
+#define I2C_FIFO_PRT_EN    (BIT(14))
+#define I2C_FIFO_PRT_EN_M  (BIT(14))
+#define I2C_FIFO_PRT_EN_V  0x1
+#define I2C_FIFO_PRT_EN_S  14
+/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TX_FIFO_RST    (BIT(13))
+#define I2C_TX_FIFO_RST_M  (BIT(13))
+#define I2C_TX_FIFO_RST_V  0x1
+#define I2C_TX_FIFO_RST_S  13
+/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RX_FIFO_RST    (BIT(12))
+#define I2C_RX_FIFO_RST_M  (BIT(12))
+#define I2C_RX_FIFO_RST_V  0x1
+#define I2C_RX_FIFO_RST_S  12
+/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_FIFO_ADDR_CFG_EN    (BIT(11))
+#define I2C_FIFO_ADDR_CFG_EN_M  (BIT(11))
+#define I2C_FIFO_ADDR_CFG_EN_V  0x1
+#define I2C_FIFO_ADDR_CFG_EN_S  11
+/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_NONFIFO_EN    (BIT(10))
+#define I2C_NONFIFO_EN_M  (BIT(10))
+#define I2C_NONFIFO_EN_V  0x1
+#define I2C_NONFIFO_EN_S  10
+/* I2C_TXFIFO_WM_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */
+/*description: .*/
+#define I2C_TXFIFO_WM_THRHD    0x0000001F
+#define I2C_TXFIFO_WM_THRHD_M  ((I2C_TXFIFO_WM_THRHD_V)<<(I2C_TXFIFO_WM_THRHD_S))
+#define I2C_TXFIFO_WM_THRHD_V  0x1F
+#define I2C_TXFIFO_WM_THRHD_S  5
+/* I2C_RXFIFO_WM_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */
+/*description: .*/
+#define I2C_RXFIFO_WM_THRHD    0x0000001F
+#define I2C_RXFIFO_WM_THRHD_M  ((I2C_RXFIFO_WM_THRHD_V)<<(I2C_RXFIFO_WM_THRHD_S))
+#define I2C_RXFIFO_WM_THRHD_V  0x1F
+#define I2C_RXFIFO_WM_THRHD_S  0
+
+#define I2C_DATA_REG(i)          (REG_I2C_BASE(i) + 0x1C)
+/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: .*/
+#define I2C_FIFO_RDATA    0x000000FF
+#define I2C_FIFO_RDATA_M  ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S))
+#define I2C_FIFO_RDATA_V  0xFF
+#define I2C_FIFO_RDATA_S  0
+
+#define I2C_INT_RAW_REG(i)          (REG_I2C_BASE(i) + 0x20)
+/* I2C_GENERAL_CALL_INT_RAW : R/SS/WTC ;bitpos:[17] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_GENERAL_CALL_INT_RAW    (BIT(17))
+#define I2C_GENERAL_CALL_INT_RAW_M  (BIT(17))
+#define I2C_GENERAL_CALL_INT_RAW_V  0x1
+#define I2C_GENERAL_CALL_INT_RAW_S  17
+/* I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC ;bitpos:[16] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_STRETCH_INT_RAW    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_RAW_M  (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_RAW_V  0x1
+#define I2C_SLAVE_STRETCH_INT_RAW_S  16
+/* I2C_DET_START_INT_RAW : R/SS/WTC ;bitpos:[15] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_DET_START_INT_RAW    (BIT(15))
+#define I2C_DET_START_INT_RAW_M  (BIT(15))
+#define I2C_DET_START_INT_RAW_V  0x1
+#define I2C_DET_START_INT_RAW_S  15
+/* I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[14] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_MAIN_ST_TO_INT_RAW    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_M  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_V  0x1
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_S  14
+/* I2C_SCL_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[13] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_ST_TO_INT_RAW    (BIT(13))
+#define I2C_SCL_ST_TO_INT_RAW_M  (BIT(13))
+#define I2C_SCL_ST_TO_INT_RAW_V  0x1
+#define I2C_SCL_ST_TO_INT_RAW_S  13
+/* I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_UDF_INT_RAW    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_RAW_M  (BIT(12))
+#define I2C_RXFIFO_UDF_INT_RAW_V  0x1
+#define I2C_RXFIFO_UDF_INT_RAW_S  12
+/* I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_OVF_INT_RAW    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_RAW_M  (BIT(11))
+#define I2C_TXFIFO_OVF_INT_RAW_V  0x1
+#define I2C_TXFIFO_OVF_INT_RAW_S  11
+/* I2C_NACK_INT_RAW : R/SS/WTC ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_NACK_INT_RAW    (BIT(10))
+#define I2C_NACK_INT_RAW_M  (BIT(10))
+#define I2C_NACK_INT_RAW_V  0x1
+#define I2C_NACK_INT_RAW_S  10
+/* I2C_TRANS_START_INT_RAW : R/SS/WTC ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TRANS_START_INT_RAW    (BIT(9))
+#define I2C_TRANS_START_INT_RAW_M  (BIT(9))
+#define I2C_TRANS_START_INT_RAW_V  0x1
+#define I2C_TRANS_START_INT_RAW_S  9
+/* I2C_TIME_OUT_INT_RAW : R/SS/WTC ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TIME_OUT_INT_RAW    (BIT(8))
+#define I2C_TIME_OUT_INT_RAW_M  (BIT(8))
+#define I2C_TIME_OUT_INT_RAW_V  0x1
+#define I2C_TIME_OUT_INT_RAW_S  8
+/* I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TRANS_COMPLETE_INT_RAW    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_RAW_M  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_RAW_V  0x1
+#define I2C_TRANS_COMPLETE_INT_RAW_S  7
+/* I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_MST_TXFIFO_UDF_INT_RAW    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_RAW_M  (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_RAW_V  0x1
+#define I2C_MST_TXFIFO_UDF_INT_RAW_S  6
+/* I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_ARBITRATION_LOST_INT_RAW    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_RAW_M  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_RAW_V  0x1
+#define I2C_ARBITRATION_LOST_INT_RAW_S  5
+/* I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_BYTE_TRANS_DONE_INT_RAW    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_RAW_M  (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_RAW_V  0x1
+#define I2C_BYTE_TRANS_DONE_INT_RAW_S  4
+/* I2C_END_DETECT_INT_RAW : R/SS/WTC ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_END_DETECT_INT_RAW    (BIT(3))
+#define I2C_END_DETECT_INT_RAW_M  (BIT(3))
+#define I2C_END_DETECT_INT_RAW_V  0x1
+#define I2C_END_DETECT_INT_RAW_S  3
+/* I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_OVF_INT_RAW    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_RAW_M  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_RAW_V  0x1
+#define I2C_RXFIFO_OVF_INT_RAW_S  2
+/* I2C_TXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'b1 ; */
+/*description: .*/
+#define I2C_TXFIFO_WM_INT_RAW    (BIT(1))
+#define I2C_TXFIFO_WM_INT_RAW_M  (BIT(1))
+#define I2C_TXFIFO_WM_INT_RAW_V  0x1
+#define I2C_TXFIFO_WM_INT_RAW_S  1
+/* I2C_RXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_WM_INT_RAW    (BIT(0))
+#define I2C_RXFIFO_WM_INT_RAW_M  (BIT(0))
+#define I2C_RXFIFO_WM_INT_RAW_V  0x1
+#define I2C_RXFIFO_WM_INT_RAW_S  0
+
+#define I2C_INT_CLR_REG(i)          (REG_I2C_BASE(i) + 0x24)
+/* I2C_GENERAL_CALL_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_GENERAL_CALL_INT_CLR    (BIT(17))
+#define I2C_GENERAL_CALL_INT_CLR_M  (BIT(17))
+#define I2C_GENERAL_CALL_INT_CLR_V  0x1
+#define I2C_GENERAL_CALL_INT_CLR_S  17
+/* I2C_SLAVE_STRETCH_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_STRETCH_INT_CLR    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_CLR_M  (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_CLR_V  0x1
+#define I2C_SLAVE_STRETCH_INT_CLR_S  16
+/* I2C_DET_START_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_DET_START_INT_CLR    (BIT(15))
+#define I2C_DET_START_INT_CLR_M  (BIT(15))
+#define I2C_DET_START_INT_CLR_V  0x1
+#define I2C_DET_START_INT_CLR_S  15
+/* I2C_SCL_MAIN_ST_TO_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_MAIN_ST_TO_INT_CLR    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_M  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_V  0x1
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_S  14
+/* I2C_SCL_ST_TO_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_ST_TO_INT_CLR    (BIT(13))
+#define I2C_SCL_ST_TO_INT_CLR_M  (BIT(13))
+#define I2C_SCL_ST_TO_INT_CLR_V  0x1
+#define I2C_SCL_ST_TO_INT_CLR_S  13
+/* I2C_RXFIFO_UDF_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_UDF_INT_CLR    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_CLR_M  (BIT(12))
+#define I2C_RXFIFO_UDF_INT_CLR_V  0x1
+#define I2C_RXFIFO_UDF_INT_CLR_S  12
+/* I2C_TXFIFO_OVF_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_OVF_INT_CLR    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_CLR_M  (BIT(11))
+#define I2C_TXFIFO_OVF_INT_CLR_V  0x1
+#define I2C_TXFIFO_OVF_INT_CLR_S  11
+/* I2C_NACK_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_NACK_INT_CLR    (BIT(10))
+#define I2C_NACK_INT_CLR_M  (BIT(10))
+#define I2C_NACK_INT_CLR_V  0x1
+#define I2C_NACK_INT_CLR_S  10
+/* I2C_TRANS_START_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TRANS_START_INT_CLR    (BIT(9))
+#define I2C_TRANS_START_INT_CLR_M  (BIT(9))
+#define I2C_TRANS_START_INT_CLR_V  0x1
+#define I2C_TRANS_START_INT_CLR_S  9
+/* I2C_TIME_OUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TIME_OUT_INT_CLR    (BIT(8))
+#define I2C_TIME_OUT_INT_CLR_M  (BIT(8))
+#define I2C_TIME_OUT_INT_CLR_V  0x1
+#define I2C_TIME_OUT_INT_CLR_S  8
+/* I2C_TRANS_COMPLETE_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TRANS_COMPLETE_INT_CLR    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_CLR_M  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_CLR_V  0x1
+#define I2C_TRANS_COMPLETE_INT_CLR_S  7
+/* I2C_MST_TXFIFO_UDF_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_MST_TXFIFO_UDF_INT_CLR    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_CLR_M  (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_CLR_V  0x1
+#define I2C_MST_TXFIFO_UDF_INT_CLR_S  6
+/* I2C_ARBITRATION_LOST_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_ARBITRATION_LOST_INT_CLR    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_CLR_M  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_CLR_V  0x1
+#define I2C_ARBITRATION_LOST_INT_CLR_S  5
+/* I2C_BYTE_TRANS_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_BYTE_TRANS_DONE_INT_CLR    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_CLR_M  (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_CLR_V  0x1
+#define I2C_BYTE_TRANS_DONE_INT_CLR_S  4
+/* I2C_END_DETECT_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_END_DETECT_INT_CLR    (BIT(3))
+#define I2C_END_DETECT_INT_CLR_M  (BIT(3))
+#define I2C_END_DETECT_INT_CLR_V  0x1
+#define I2C_END_DETECT_INT_CLR_S  3
+/* I2C_RXFIFO_OVF_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_OVF_INT_CLR    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_CLR_M  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_CLR_V  0x1
+#define I2C_RXFIFO_OVF_INT_CLR_S  2
+/* I2C_TXFIFO_WM_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_WM_INT_CLR    (BIT(1))
+#define I2C_TXFIFO_WM_INT_CLR_M  (BIT(1))
+#define I2C_TXFIFO_WM_INT_CLR_V  0x1
+#define I2C_TXFIFO_WM_INT_CLR_S  1
+/* I2C_RXFIFO_WM_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_WM_INT_CLR    (BIT(0))
+#define I2C_RXFIFO_WM_INT_CLR_M  (BIT(0))
+#define I2C_RXFIFO_WM_INT_CLR_V  0x1
+#define I2C_RXFIFO_WM_INT_CLR_S  0
+
+#define I2C_INT_ENA_REG(i)          (REG_I2C_BASE(i) + 0x28)
+/* I2C_GENERAL_CALL_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_GENERAL_CALL_INT_ENA    (BIT(17))
+#define I2C_GENERAL_CALL_INT_ENA_M  (BIT(17))
+#define I2C_GENERAL_CALL_INT_ENA_V  0x1
+#define I2C_GENERAL_CALL_INT_ENA_S  17
+/* I2C_SLAVE_STRETCH_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_STRETCH_INT_ENA    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ENA_M  (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ENA_V  0x1
+#define I2C_SLAVE_STRETCH_INT_ENA_S  16
+/* I2C_DET_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_DET_START_INT_ENA    (BIT(15))
+#define I2C_DET_START_INT_ENA_M  (BIT(15))
+#define I2C_DET_START_INT_ENA_V  0x1
+#define I2C_DET_START_INT_ENA_S  15
+/* I2C_SCL_MAIN_ST_TO_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_MAIN_ST_TO_INT_ENA    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_M  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_V  0x1
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_S  14
+/* I2C_SCL_ST_TO_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_ST_TO_INT_ENA    (BIT(13))
+#define I2C_SCL_ST_TO_INT_ENA_M  (BIT(13))
+#define I2C_SCL_ST_TO_INT_ENA_V  0x1
+#define I2C_SCL_ST_TO_INT_ENA_S  13
+/* I2C_RXFIFO_UDF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_UDF_INT_ENA    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ENA_M  (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ENA_V  0x1
+#define I2C_RXFIFO_UDF_INT_ENA_S  12
+/* I2C_TXFIFO_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_OVF_INT_ENA    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ENA_M  (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ENA_V  0x1
+#define I2C_TXFIFO_OVF_INT_ENA_S  11
+/* I2C_NACK_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_NACK_INT_ENA    (BIT(10))
+#define I2C_NACK_INT_ENA_M  (BIT(10))
+#define I2C_NACK_INT_ENA_V  0x1
+#define I2C_NACK_INT_ENA_S  10
+/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TRANS_START_INT_ENA    (BIT(9))
+#define I2C_TRANS_START_INT_ENA_M  (BIT(9))
+#define I2C_TRANS_START_INT_ENA_V  0x1
+#define I2C_TRANS_START_INT_ENA_S  9
+/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TIME_OUT_INT_ENA    (BIT(8))
+#define I2C_TIME_OUT_INT_ENA_M  (BIT(8))
+#define I2C_TIME_OUT_INT_ENA_V  0x1
+#define I2C_TIME_OUT_INT_ENA_S  8
+/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TRANS_COMPLETE_INT_ENA    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ENA_M  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ENA_V  0x1
+#define I2C_TRANS_COMPLETE_INT_ENA_S  7
+/* I2C_MST_TXFIFO_UDF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_MST_TXFIFO_UDF_INT_ENA    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ENA_M  (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ENA_V  0x1
+#define I2C_MST_TXFIFO_UDF_INT_ENA_S  6
+/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_ARBITRATION_LOST_INT_ENA    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ENA_M  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ENA_V  0x1
+#define I2C_ARBITRATION_LOST_INT_ENA_S  5
+/* I2C_BYTE_TRANS_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_BYTE_TRANS_DONE_INT_ENA    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ENA_M  (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ENA_V  0x1
+#define I2C_BYTE_TRANS_DONE_INT_ENA_S  4
+/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_END_DETECT_INT_ENA    (BIT(3))
+#define I2C_END_DETECT_INT_ENA_M  (BIT(3))
+#define I2C_END_DETECT_INT_ENA_V  0x1
+#define I2C_END_DETECT_INT_ENA_S  3
+/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_OVF_INT_ENA    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ENA_M  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ENA_V  0x1
+#define I2C_RXFIFO_OVF_INT_ENA_S  2
+/* I2C_TXFIFO_WM_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_WM_INT_ENA    (BIT(1))
+#define I2C_TXFIFO_WM_INT_ENA_M  (BIT(1))
+#define I2C_TXFIFO_WM_INT_ENA_V  0x1
+#define I2C_TXFIFO_WM_INT_ENA_S  1
+/* I2C_RXFIFO_WM_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_WM_INT_ENA    (BIT(0))
+#define I2C_RXFIFO_WM_INT_ENA_M  (BIT(0))
+#define I2C_RXFIFO_WM_INT_ENA_V  0x1
+#define I2C_RXFIFO_WM_INT_ENA_S  0
+
+#define I2C_INT_STATUS_REG(i)          (REG_I2C_BASE(i) + 0x2C)
+/* I2C_GENERAL_CALL_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_GENERAL_CALL_INT_ST    (BIT(17))
+#define I2C_GENERAL_CALL_INT_ST_M  (BIT(17))
+#define I2C_GENERAL_CALL_INT_ST_V  0x1
+#define I2C_GENERAL_CALL_INT_ST_S  17
+/* I2C_SLAVE_STRETCH_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_STRETCH_INT_ST    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ST_M  (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ST_V  0x1
+#define I2C_SLAVE_STRETCH_INT_ST_S  16
+/* I2C_DET_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_DET_START_INT_ST    (BIT(15))
+#define I2C_DET_START_INT_ST_M  (BIT(15))
+#define I2C_DET_START_INT_ST_V  0x1
+#define I2C_DET_START_INT_ST_S  15
+/* I2C_SCL_MAIN_ST_TO_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_MAIN_ST_TO_INT_ST    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ST_M  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ST_V  0x1
+#define I2C_SCL_MAIN_ST_TO_INT_ST_S  14
+/* I2C_SCL_ST_TO_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_ST_TO_INT_ST    (BIT(13))
+#define I2C_SCL_ST_TO_INT_ST_M  (BIT(13))
+#define I2C_SCL_ST_TO_INT_ST_V  0x1
+#define I2C_SCL_ST_TO_INT_ST_S  13
+/* I2C_RXFIFO_UDF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_UDF_INT_ST    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ST_M  (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ST_V  0x1
+#define I2C_RXFIFO_UDF_INT_ST_S  12
+/* I2C_TXFIFO_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_OVF_INT_ST    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ST_M  (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ST_V  0x1
+#define I2C_TXFIFO_OVF_INT_ST_S  11
+/* I2C_NACK_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_NACK_INT_ST    (BIT(10))
+#define I2C_NACK_INT_ST_M  (BIT(10))
+#define I2C_NACK_INT_ST_V  0x1
+#define I2C_NACK_INT_ST_S  10
+/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TRANS_START_INT_ST    (BIT(9))
+#define I2C_TRANS_START_INT_ST_M  (BIT(9))
+#define I2C_TRANS_START_INT_ST_V  0x1
+#define I2C_TRANS_START_INT_ST_S  9
+/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TIME_OUT_INT_ST    (BIT(8))
+#define I2C_TIME_OUT_INT_ST_M  (BIT(8))
+#define I2C_TIME_OUT_INT_ST_V  0x1
+#define I2C_TIME_OUT_INT_ST_S  8
+/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TRANS_COMPLETE_INT_ST    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ST_M  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ST_V  0x1
+#define I2C_TRANS_COMPLETE_INT_ST_S  7
+/* I2C_MST_TXFIFO_UDF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_MST_TXFIFO_UDF_INT_ST    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ST_M  (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ST_V  0x1
+#define I2C_MST_TXFIFO_UDF_INT_ST_S  6
+/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_ARBITRATION_LOST_INT_ST    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ST_M  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ST_V  0x1
+#define I2C_ARBITRATION_LOST_INT_ST_S  5
+/* I2C_BYTE_TRANS_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_BYTE_TRANS_DONE_INT_ST    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ST_M  (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ST_V  0x1
+#define I2C_BYTE_TRANS_DONE_INT_ST_S  4
+/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_END_DETECT_INT_ST    (BIT(3))
+#define I2C_END_DETECT_INT_ST_M  (BIT(3))
+#define I2C_END_DETECT_INT_ST_V  0x1
+#define I2C_END_DETECT_INT_ST_S  3
+/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_OVF_INT_ST    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ST_M  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ST_V  0x1
+#define I2C_RXFIFO_OVF_INT_ST_S  2
+/* I2C_TXFIFO_WM_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_WM_INT_ST    (BIT(1))
+#define I2C_TXFIFO_WM_INT_ST_M  (BIT(1))
+#define I2C_TXFIFO_WM_INT_ST_V  0x1
+#define I2C_TXFIFO_WM_INT_ST_S  1
+/* I2C_RXFIFO_WM_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_WM_INT_ST    (BIT(0))
+#define I2C_RXFIFO_WM_INT_ST_M  (BIT(0))
+#define I2C_RXFIFO_WM_INT_ST_V  0x1
+#define I2C_RXFIFO_WM_INT_ST_S  0
+
+#define I2C_SDA_HOLD_REG(i)          (REG_I2C_BASE(i) + 0x30)
+/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */
+/*description: .*/
+#define I2C_SDA_HOLD_TIME    0x000001FF
+#define I2C_SDA_HOLD_TIME_M  ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S))
+#define I2C_SDA_HOLD_TIME_V  0x1FF
+#define I2C_SDA_HOLD_TIME_S  0
+
+#define I2C_SDA_SAMPLE_REG(i)          (REG_I2C_BASE(i) + 0x34)
+/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */
+/*description: .*/
+#define I2C_SDA_SAMPLE_TIME    0x000001FF
+#define I2C_SDA_SAMPLE_TIME_M  ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S))
+#define I2C_SDA_SAMPLE_TIME_V  0x1FF
+#define I2C_SDA_SAMPLE_TIME_S  0
+
+#define I2C_SCL_HIGH_PERIOD_REG(i)          (REG_I2C_BASE(i) + 0x38)
+/* I2C_SCL_WAIT_HIGH_PERIOD : R/W ;bitpos:[15:9] ;default: 7'b0 ; */
+/*description: .*/
+#define I2C_SCL_WAIT_HIGH_PERIOD    0x0000007F
+#define I2C_SCL_WAIT_HIGH_PERIOD_M  ((I2C_SCL_WAIT_HIGH_PERIOD_V)<<(I2C_SCL_WAIT_HIGH_PERIOD_S))
+#define I2C_SCL_WAIT_HIGH_PERIOD_V  0x7F
+#define I2C_SCL_WAIT_HIGH_PERIOD_S  9
+/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */
+/*description: .*/
+#define I2C_SCL_HIGH_PERIOD    0x000001FF
+#define I2C_SCL_HIGH_PERIOD_M  ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S))
+#define I2C_SCL_HIGH_PERIOD_V  0x1FF
+#define I2C_SCL_HIGH_PERIOD_S  0
+
+#define I2C_SCL_START_HOLD_REG(i)          (REG_I2C_BASE(i) + 0x40)
+/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */
+/*description: .*/
+#define I2C_SCL_START_HOLD_TIME    0x000001FF
+#define I2C_SCL_START_HOLD_TIME_M  ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S))
+#define I2C_SCL_START_HOLD_TIME_V  0x1FF
+#define I2C_SCL_START_HOLD_TIME_S  0
+
+#define I2C_SCL_RSTART_SETUP_REG(i)          (REG_I2C_BASE(i) + 0x44)
+/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */
+/*description: .*/
+#define I2C_SCL_RSTART_SETUP_TIME    0x000001FF
+#define I2C_SCL_RSTART_SETUP_TIME_M  ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S))
+#define I2C_SCL_RSTART_SETUP_TIME_V  0x1FF
+#define I2C_SCL_RSTART_SETUP_TIME_S  0
+
+#define I2C_SCL_STOP_HOLD_REG(i)          (REG_I2C_BASE(i) + 0x48)
+/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */
+/*description: .*/
+#define I2C_SCL_STOP_HOLD_TIME    0x000001FF
+#define I2C_SCL_STOP_HOLD_TIME_M  ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S))
+#define I2C_SCL_STOP_HOLD_TIME_V  0x1FF
+#define I2C_SCL_STOP_HOLD_TIME_S  0
+
+#define I2C_SCL_STOP_SETUP_REG(i)          (REG_I2C_BASE(i) + 0x4C)
+/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */
+/*description: .*/
+#define I2C_SCL_STOP_SETUP_TIME    0x000001FF
+#define I2C_SCL_STOP_SETUP_TIME_M  ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S))
+#define I2C_SCL_STOP_SETUP_TIME_V  0x1FF
+#define I2C_SCL_STOP_SETUP_TIME_S  0
+
+#define I2C_FILTER_CFG_REG(i)          (REG_I2C_BASE(i) + 0x50)
+/* I2C_SDA_FILTER_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: .*/
+#define I2C_SDA_FILTER_EN    (BIT(9))
+#define I2C_SDA_FILTER_EN_M  (BIT(9))
+#define I2C_SDA_FILTER_EN_V  0x1
+#define I2C_SDA_FILTER_EN_S  9
+/* I2C_SCL_FILTER_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: .*/
+#define I2C_SCL_FILTER_EN    (BIT(8))
+#define I2C_SCL_FILTER_EN_M  (BIT(8))
+#define I2C_SCL_FILTER_EN_V  0x1
+#define I2C_SCL_FILTER_EN_S  8
+/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: .*/
+#define I2C_SDA_FILTER_THRES    0x0000000F
+#define I2C_SDA_FILTER_THRES_M  ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S))
+#define I2C_SDA_FILTER_THRES_V  0xF
+#define I2C_SDA_FILTER_THRES_S  4
+/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: .*/
+#define I2C_SCL_FILTER_THRES    0x0000000F
+#define I2C_SCL_FILTER_THRES_M  ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S))
+#define I2C_SCL_FILTER_THRES_V  0xF
+#define I2C_SCL_FILTER_THRES_S  0
+
+#define I2C_CLK_CONF_REG(i)          (REG_I2C_BASE(i) + 0x54)
+/* I2C_SCLK_ACTIVE : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: .*/
+#define I2C_SCLK_ACTIVE    (BIT(21))
+#define I2C_SCLK_ACTIVE_M  (BIT(21))
+#define I2C_SCLK_ACTIVE_V  0x1
+#define I2C_SCLK_ACTIVE_S  21
+/* I2C_SCLK_SEL : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCLK_SEL    (BIT(20))
+#define I2C_SCLK_SEL_M  (BIT(20))
+#define I2C_SCLK_SEL_V  0x1
+#define I2C_SCLK_SEL_S  20
+/* I2C_SCLK_DIV_B : R/W ;bitpos:[19:14] ;default: 6'b0 ; */
+/*description: .*/
+#define I2C_SCLK_DIV_B    0x0000003F
+#define I2C_SCLK_DIV_B_M  ((I2C_SCLK_DIV_B_V)<<(I2C_SCLK_DIV_B_S))
+#define I2C_SCLK_DIV_B_V  0x3F
+#define I2C_SCLK_DIV_B_S  14
+/* I2C_SCLK_DIV_A : R/W ;bitpos:[13:8] ;default: 6'b0 ; */
+/*description: .*/
+#define I2C_SCLK_DIV_A    0x0000003F
+#define I2C_SCLK_DIV_A_M  ((I2C_SCLK_DIV_A_V)<<(I2C_SCLK_DIV_A_S))
+#define I2C_SCLK_DIV_A_V  0x3F
+#define I2C_SCLK_DIV_A_S  8
+/* I2C_SCLK_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: .*/
+#define I2C_SCLK_DIV_NUM    0x000000FF
+#define I2C_SCLK_DIV_NUM_M  ((I2C_SCLK_DIV_NUM_V)<<(I2C_SCLK_DIV_NUM_S))
+#define I2C_SCLK_DIV_NUM_V  0xFF
+#define I2C_SCLK_DIV_NUM_S  0
+
+#define I2C_COMD0_REG(i)          (REG_I2C_BASE(i) + 0x58)
+/* I2C_COMMAND0_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_COMMAND0_DONE    (BIT(31))
+#define I2C_COMMAND0_DONE_M  (BIT(31))
+#define I2C_COMMAND0_DONE_V  0x1
+#define I2C_COMMAND0_DONE_S  31
+/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: .*/
+#define I2C_COMMAND0    0x00003FFF
+#define I2C_COMMAND0_M  ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S))
+#define I2C_COMMAND0_V  0x3FFF
+#define I2C_COMMAND0_S  0
+
+#define I2C_COMD1_REG(i)          (REG_I2C_BASE(i) + 0x5C)
+/* I2C_COMMAND1_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_COMMAND1_DONE    (BIT(31))
+#define I2C_COMMAND1_DONE_M  (BIT(31))
+#define I2C_COMMAND1_DONE_V  0x1
+#define I2C_COMMAND1_DONE_S  31
+/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: .*/
+#define I2C_COMMAND1    0x00003FFF
+#define I2C_COMMAND1_M  ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S))
+#define I2C_COMMAND1_V  0x3FFF
+#define I2C_COMMAND1_S  0
+
+#define I2C_COMD2_REG(i)          (REG_I2C_BASE(i) + 0x60)
+/* I2C_COMMAND2_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_COMMAND2_DONE    (BIT(31))
+#define I2C_COMMAND2_DONE_M  (BIT(31))
+#define I2C_COMMAND2_DONE_V  0x1
+#define I2C_COMMAND2_DONE_S  31
+/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: .*/
+#define I2C_COMMAND2    0x00003FFF
+#define I2C_COMMAND2_M  ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S))
+#define I2C_COMMAND2_V  0x3FFF
+#define I2C_COMMAND2_S  0
+
+#define I2C_COMD3_REG(i)          (REG_I2C_BASE(i) + 0x64)
+/* I2C_COMMAND3_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_COMMAND3_DONE    (BIT(31))
+#define I2C_COMMAND3_DONE_M  (BIT(31))
+#define I2C_COMMAND3_DONE_V  0x1
+#define I2C_COMMAND3_DONE_S  31
+/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: .*/
+#define I2C_COMMAND3    0x00003FFF
+#define I2C_COMMAND3_M  ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S))
+#define I2C_COMMAND3_V  0x3FFF
+#define I2C_COMMAND3_S  0
+
+#define I2C_COMD4_REG(i)          (REG_I2C_BASE(i) + 0x68)
+/* I2C_COMMAND4_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_COMMAND4_DONE    (BIT(31))
+#define I2C_COMMAND4_DONE_M  (BIT(31))
+#define I2C_COMMAND4_DONE_V  0x1
+#define I2C_COMMAND4_DONE_S  31
+/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: .*/
+#define I2C_COMMAND4    0x00003FFF
+#define I2C_COMMAND4_M  ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S))
+#define I2C_COMMAND4_V  0x3FFF
+#define I2C_COMMAND4_S  0
+
+#define I2C_COMD5_REG(i)          (REG_I2C_BASE(i) + 0x6C)
+/* I2C_COMMAND5_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_COMMAND5_DONE    (BIT(31))
+#define I2C_COMMAND5_DONE_M  (BIT(31))
+#define I2C_COMMAND5_DONE_V  0x1
+#define I2C_COMMAND5_DONE_S  31
+/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: .*/
+#define I2C_COMMAND5    0x00003FFF
+#define I2C_COMMAND5_M  ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S))
+#define I2C_COMMAND5_V  0x3FFF
+#define I2C_COMMAND5_S  0
+
+#define I2C_COMD6_REG(i)          (REG_I2C_BASE(i) + 0x70)
+/* I2C_COMMAND6_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_COMMAND6_DONE    (BIT(31))
+#define I2C_COMMAND6_DONE_M  (BIT(31))
+#define I2C_COMMAND6_DONE_V  0x1
+#define I2C_COMMAND6_DONE_S  31
+/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: .*/
+#define I2C_COMMAND6    0x00003FFF
+#define I2C_COMMAND6_M  ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S))
+#define I2C_COMMAND6_V  0x3FFF
+#define I2C_COMMAND6_S  0
+
+#define I2C_COMD7_REG(i)          (REG_I2C_BASE(i) + 0x74)
+/* I2C_COMMAND7_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_COMMAND7_DONE    (BIT(31))
+#define I2C_COMMAND7_DONE_M  (BIT(31))
+#define I2C_COMMAND7_DONE_V  0x1
+#define I2C_COMMAND7_DONE_S  31
+/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: .*/
+#define I2C_COMMAND7    0x00003FFF
+#define I2C_COMMAND7_M  ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S))
+#define I2C_COMMAND7_V  0x3FFF
+#define I2C_COMMAND7_S  0
+
+#define I2C_SCL_ST_TIME_OUT_REG(i)          (REG_I2C_BASE(i) + 0x78)
+/* I2C_SCL_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */
+/*description: no more than 23.*/
+#define I2C_SCL_ST_TO_REG    0x0000001F
+#define I2C_SCL_ST_TO_REG_M  ((I2C_SCL_ST_TO_REG_V)<<(I2C_SCL_ST_TO_REG_S))
+#define I2C_SCL_ST_TO_REG_V  0x1F
+#define I2C_SCL_ST_TO_REG_S  0
+
+#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i)          (REG_I2C_BASE(i) + 0x7C)
+/* I2C_SCL_MAIN_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */
+/*description: no more than 23.*/
+#define I2C_SCL_MAIN_ST_TO_REG    0x0000001F
+#define I2C_SCL_MAIN_ST_TO_REG_M  ((I2C_SCL_MAIN_ST_TO_REG_V)<<(I2C_SCL_MAIN_ST_TO_REG_S))
+#define I2C_SCL_MAIN_ST_TO_REG_V  0x1F
+#define I2C_SCL_MAIN_ST_TO_REG_S  0
+
+#define I2C_SCL_SP_CONF_REG(i)          (REG_I2C_BASE(i) + 0x80)
+/* I2C_SDA_PD_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SDA_PD_EN    (BIT(7))
+#define I2C_SDA_PD_EN_M  (BIT(7))
+#define I2C_SDA_PD_EN_V  0x1
+#define I2C_SDA_PD_EN_S  7
+/* I2C_SCL_PD_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_PD_EN    (BIT(6))
+#define I2C_SCL_PD_EN_M  (BIT(6))
+#define I2C_SCL_PD_EN_V  0x1
+#define I2C_SCL_PD_EN_S  6
+/* I2C_SCL_RST_SLV_NUM : R/W ;bitpos:[5:1] ;default: 5'b0 ; */
+/*description: .*/
+#define I2C_SCL_RST_SLV_NUM    0x0000001F
+#define I2C_SCL_RST_SLV_NUM_M  ((I2C_SCL_RST_SLV_NUM_V)<<(I2C_SCL_RST_SLV_NUM_S))
+#define I2C_SCL_RST_SLV_NUM_V  0x1F
+#define I2C_SCL_RST_SLV_NUM_S  1
+/* I2C_SCL_RST_SLV_EN : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_RST_SLV_EN    (BIT(0))
+#define I2C_SCL_RST_SLV_EN_M  (BIT(0))
+#define I2C_SCL_RST_SLV_EN_V  0x1
+#define I2C_SCL_RST_SLV_EN_S  0
+
+#define I2C_SCL_STRETCH_CONF_REG(i)          (REG_I2C_BASE(i) + 0x84)
+/* I2C_SLAVE_BYTE_ACK_LVL : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_BYTE_ACK_LVL    (BIT(13))
+#define I2C_SLAVE_BYTE_ACK_LVL_M  (BIT(13))
+#define I2C_SLAVE_BYTE_ACK_LVL_V  0x1
+#define I2C_SLAVE_BYTE_ACK_LVL_S  13
+/* I2C_SLAVE_BYTE_ACK_CTL_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_BYTE_ACK_CTL_EN    (BIT(12))
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_M  (BIT(12))
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_V  0x1
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_S  12
+/* I2C_SLAVE_SCL_STRETCH_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_SCL_STRETCH_CLR    (BIT(11))
+#define I2C_SLAVE_SCL_STRETCH_CLR_M  (BIT(11))
+#define I2C_SLAVE_SCL_STRETCH_CLR_V  0x1
+#define I2C_SLAVE_SCL_STRETCH_CLR_S  11
+/* I2C_SLAVE_SCL_STRETCH_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_SCL_STRETCH_EN    (BIT(10))
+#define I2C_SLAVE_SCL_STRETCH_EN_M  (BIT(10))
+#define I2C_SLAVE_SCL_STRETCH_EN_V  0x1
+#define I2C_SLAVE_SCL_STRETCH_EN_S  10
+/* I2C_STRETCH_PROTECT_NUM : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: .*/
+#define I2C_STRETCH_PROTECT_NUM    0x000003FF
+#define I2C_STRETCH_PROTECT_NUM_M  ((I2C_STRETCH_PROTECT_NUM_V)<<(I2C_STRETCH_PROTECT_NUM_S))
+#define I2C_STRETCH_PROTECT_NUM_V  0x3FF
+#define I2C_STRETCH_PROTECT_NUM_S  0
+
+#define I2C_DATE_REG(i)          (REG_I2C_BASE(i) + 0xF8)
+/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h20070201 ; */
+/*description: .*/
+#define I2C_DATE    0xFFFFFFFF
+#define I2C_DATE_M  ((I2C_DATE_V)<<(I2C_DATE_S))
+#define I2C_DATE_V  0xFFFFFFFF
+#define I2C_DATE_S  0
+
+#define I2C_TXFIFO_START_ADDR_REG(i)          (REG_I2C_BASE(i) + 0x100)
+
+#define I2C_RXFIFO_START_ADDR_REG(i)          (REG_I2C_BASE(i) + 0x180)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_I2C_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/i2c_struct.h b/components/soc/esp32c3/include/soc/i2c_struct.h
new file mode 100644
index 0000000000..22c6c47041
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/i2c_struct.h
@@ -0,0 +1,407 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_I2C_STRUCT_H_
+#define _SOC_I2C_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t period                        :    9;
+            uint32_t reserved9                     :    23;
+        };
+        uint32_t val;
+    } scl_low_period;
+    union {
+        struct {
+            uint32_t sda_force_out                 :    1;
+            uint32_t scl_force_out                 :    1;
+            uint32_t sample_scl_level              :    1;
+            uint32_t rx_full_ack_level             :    1;
+            uint32_t ms_mode                       :    1;
+            uint32_t trans_start                   :    1;
+            uint32_t tx_lsb_first                  :    1;
+            uint32_t rx_lsb_first                  :    1;
+            uint32_t clk_en                        :    1;
+            uint32_t arbitration_en                :    1;
+            uint32_t fsm_rst                       :    1;
+            uint32_t conf_upgate                   :    1;
+            uint32_t slv_tx_auto_start_en          :    1;
+            uint32_t addr_10bit_rw_check_en        :    1;
+            uint32_t addr_broadcasting_en          :    1;
+            uint32_t reserved15                    :    17;
+        };
+        uint32_t val;
+    } ctr;
+    union {
+        struct {
+            uint32_t resp_rec                      :    1;
+            uint32_t slave_rw                      :    1;
+            uint32_t reserved2                     :    1;
+            uint32_t arb_lost                      :    1;
+            uint32_t bus_busy                      :    1;
+            uint32_t slave_addressed               :    1;
+            uint32_t reserved6                     :    1;
+            uint32_t reserved7                     :    1;
+            uint32_t rx_fifo_cnt                   :    6;
+            uint32_t stretch_cause                 :    2;
+            uint32_t reserved16                    :    2;
+            uint32_t tx_fifo_cnt                   :    6;
+            uint32_t scl_main_state_last           :    3;
+            uint32_t reserved27                    :    1;
+            uint32_t scl_state_last                :    3;
+            uint32_t reserved31                    :    1;
+        };
+        uint32_t val;
+    } sr;
+    union {
+        struct {
+            uint32_t time_out_value                :    5;
+            uint32_t time_out_en                   :    1;
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } timeout;
+    union {
+        struct {
+            uint32_t addr                          :    15;
+            uint32_t reserved15                    :    16;
+            uint32_t en_10bit                      :    1;
+        };
+        uint32_t val;
+    } slave_addr;
+    union {
+        struct {
+            uint32_t rx_fifo_raddr                 :    5;
+            uint32_t rx_fifo_waddr                 :    5;
+            uint32_t tx_fifo_raddr                 :    5;
+            uint32_t tx_fifo_waddr                 :    5;
+            uint32_t reserved20                    :    1;
+            uint32_t reserved21                    :    1;
+            uint32_t slave_rw_point                :    8;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } fifo_st;
+    union {
+        struct {
+            uint32_t rx_fifo_wm_thrhd              :    5;
+            uint32_t tx_fifo_wm_thrhd              :    5;
+            uint32_t nonfifo_en                    :    1;
+            uint32_t fifo_addr_cfg_en              :    1;
+            uint32_t rx_fifo_rst                   :    1;
+            uint32_t tx_fifo_rst                   :    1;
+            uint32_t fifo_prt_en                   :    1;
+            uint32_t reserved15                    :    5;
+            uint32_t reserved20                    :    6;
+            uint32_t reserved26                    :    1;
+            uint32_t reserved27                    :    5;
+        };
+        uint32_t val;
+    } fifo_conf;
+    union {
+        struct {
+            uint32_t data                          :    8;
+            uint32_t reserved8                     :    24;
+        };
+        uint32_t val;
+    } fifo_data;
+    union {
+        struct {
+            uint32_t rx_fifo_wm                    :    1;
+            uint32_t tx_fifo_wm                    :    1;
+            uint32_t rx_fifo_ovf                   :    1;
+            uint32_t end_detect                    :    1;
+            uint32_t byte_trans_done               :    1;
+            uint32_t arbitration_lost              :    1;
+            uint32_t mst_tx_fifo_udf               :    1;
+            uint32_t trans_complete                :    1;
+            uint32_t time_out                      :    1;
+            uint32_t trans_start                   :    1;
+            uint32_t nack                          :    1;
+            uint32_t tx_fifo_ovf                   :    1;
+            uint32_t rx_fifo_udf                   :    1;
+            uint32_t scl_st_to                     :    1;
+            uint32_t scl_main_st_to                :    1;
+            uint32_t det_start                     :    1;
+            uint32_t slave_stretch                 :    1;
+            uint32_t general_call                  :    1;
+            uint32_t reserved18                    :    14;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t rx_fifo_wm                    :    1;
+            uint32_t tx_fifo_wm                    :    1;
+            uint32_t rx_fifo_ovf                   :    1;
+            uint32_t end_detect                    :    1;
+            uint32_t byte_trans_done               :    1;
+            uint32_t arbitration_lost              :    1;
+            uint32_t mst_tx_fifo_udf               :    1;
+            uint32_t trans_complete                :    1;
+            uint32_t time_out                      :    1;
+            uint32_t trans_start                   :    1;
+            uint32_t nack                          :    1;
+            uint32_t tx_fifo_ovf                   :    1;
+            uint32_t rx_fifo_udf                   :    1;
+            uint32_t scl_st_to                     :    1;
+            uint32_t scl_main_st_to                :    1;
+            uint32_t det_start                     :    1;
+            uint32_t slave_stretch                 :    1;
+            uint32_t general_call                  :    1;
+            uint32_t reserved18                    :    14;
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t rx_fifo_wm                    :    1;
+            uint32_t tx_fifo_wm                    :    1;
+            uint32_t rx_fifo_ovf                   :    1;
+            uint32_t end_detect                    :    1;
+            uint32_t byte_trans_done               :    1;
+            uint32_t arbitration_lost              :    1;
+            uint32_t mst_tx_fifo_udf               :    1;
+            uint32_t trans_complete                :    1;
+            uint32_t time_out                      :    1;
+            uint32_t trans_start                   :    1;
+            uint32_t nack                          :    1;
+            uint32_t tx_fifo_ovf                   :    1;
+            uint32_t rx_fifo_udf                   :    1;
+            uint32_t scl_st_to                     :    1;
+            uint32_t scl_main_st_to                :    1;
+            uint32_t det_start                     :    1;
+            uint32_t slave_stretch                 :    1;
+            uint32_t general_call                  :    1;
+            uint32_t reserved18                    :    14;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t rx_fifo_wm                    :    1;
+            uint32_t tx_fifo_wm                    :    1;
+            uint32_t rx_fifo_ovf                   :    1;
+            uint32_t end_detect                    :    1;
+            uint32_t byte_trans_done               :    1;
+            uint32_t arbitration_lost              :    1;
+            uint32_t mst_tx_fifo_udf               :    1;
+            uint32_t trans_complete                :    1;
+            uint32_t time_out                      :    1;
+            uint32_t trans_start                   :    1;
+            uint32_t nack                          :    1;
+            uint32_t tx_fifo_ovf                   :    1;
+            uint32_t rx_fifo_udf                   :    1;
+            uint32_t scl_st_to                     :    1;
+            uint32_t scl_main_st_to                :    1;
+            uint32_t det_start                     :    1;
+            uint32_t slave_stretch                 :    1;
+            uint32_t general_call                  :    1;
+            uint32_t reserved18                    :    14;
+        };
+        uint32_t val;
+    } int_status;
+    union {
+        struct {
+            uint32_t time                          :    9;
+            uint32_t reserved9                     :    23;
+        };
+        uint32_t val;
+    } sda_hold;
+    union {
+        struct {
+            uint32_t time                          :    9;
+            uint32_t reserved9                     :    23;
+        };
+        uint32_t val;
+    } sda_sample;
+    union {
+        struct {
+            uint32_t period                        :    9;
+            uint32_t scl_wait_high_period          :    7;
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } scl_high_period;
+    uint32_t reserved_3c;
+    union {
+        struct {
+            uint32_t time                          :    9;
+            uint32_t reserved9                     :    23;
+        };
+        uint32_t val;
+    } scl_start_hold;
+    union {
+        struct {
+            uint32_t time                          :    9;
+            uint32_t reserved9                     :    23;
+        };
+        uint32_t val;
+    } scl_rstart_setup;
+    union {
+        struct {
+            uint32_t time                          :    9;
+            uint32_t reserved9                     :    23;
+        };
+        uint32_t val;
+    } scl_stop_hold;
+    union {
+        struct {
+            uint32_t time                          :    9;
+            uint32_t reserved9                     :    23;
+        };
+        uint32_t val;
+    } scl_stop_setup;
+    union {
+        struct {
+            uint32_t scl_thres                     :    4;
+            uint32_t sda_thres                     :    4;
+            uint32_t scl_en                        :    1;
+            uint32_t sda_en                        :    1;
+            uint32_t reserved10                    :    22;
+        };
+        uint32_t val;
+    } filter_cfg;
+    union {
+        struct {
+            uint32_t sclk_div_num                  :    8;
+            uint32_t sclk_div_a                    :    6;
+            uint32_t sclk_div_b                    :    6;
+            uint32_t sclk_sel                      :    1;
+            uint32_t sclk_active                   :    1;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } clk_conf;
+    union {
+        struct {
+            uint32_t command0                      :    14;
+            uint32_t reserved14                    :    17;
+            uint32_t command0_done                 :    1;
+        };
+        uint32_t val;
+    } command[8];
+    union {
+        struct {
+            uint32_t scl_st_to                     :    5;  /*no more than 23*/
+            uint32_t reserved5                     :    27;
+        };
+        uint32_t val;
+    } scl_st_time_out;
+    union {
+        struct {
+            uint32_t scl_main_st_to                :    5;  /*no more than 23*/
+            uint32_t reserved5                     :    27;
+        };
+        uint32_t val;
+    } scl_main_st_time_out;
+    union {
+        struct {
+            uint32_t scl_rst_slv_en                :    1;
+            uint32_t scl_rst_slv_num               :    5;
+            uint32_t scl_pd_en                     :    1;
+            uint32_t sda_pd_en                     :    1;
+            uint32_t reserved8                     :    24;
+        };
+        uint32_t val;
+    } scl_sp_conf;
+    union {
+        struct {
+            uint32_t stretch_protect_num           :    10;
+            uint32_t slave_scl_stretch_en          :    1;
+            uint32_t slave_scl_stretch_clr         :    1;
+            uint32_t slave_byte_ack_ctl_en         :    1;
+            uint32_t slave_byte_ack_level          :    1;
+            uint32_t reserved14                    :    18;
+        };
+        uint32_t val;
+    } scl_stretch_conf;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t date;
+    uint32_t reserved_fc;
+    uint32_t txfifo_start_addr;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t rxfifo_start_addr;
+} i2c_dev_t;
+extern i2c_dev_t I2C0;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_I2C_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/i2s_caps.h b/components/soc/esp32c3/include/soc/i2s_caps.h
new file mode 100644
index 0000000000..44c8075316
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/i2s_caps.h
@@ -0,0 +1,25 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#define APLL_MIN_FREQ                     (250000000)
+#define APLL_MAX_FREQ                     (500000000)
+#define APLL_I2S_MIN_RATE                 (10675) //in Hz, I2S Clock rate limited by hardware
+#define SOC_I2S_MAX_BUFFER_SIZE               (4 * 1024 * 1024) //the maximum RAM can be allocated
+
+// ESP32-S3 have 1 I2S
+#define SOC_I2S_NUM            (1)
+
+#define SOC_I2S_SUPPORT_PDM     (0) // ESP32-S3 do not support PDM
diff --git a/components/soc/esp32c3/include/soc/i2s_reg.h b/components/soc/esp32c3/include/soc/i2s_reg.h
new file mode 100644
index 0000000000..a5c4ed3e35
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/i2s_reg.h
@@ -0,0 +1,1051 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_I2S_REG_H_
+#define _SOC_I2S_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define I2S_INT_RAW_REG(i)          (REG_I2S_BASE(i) + 0x000c)
+/* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_tx_hung_int interrupt*/
+#define I2S_TX_HUNG_INT_RAW  (BIT(3))
+#define I2S_TX_HUNG_INT_RAW_M  (BIT(3))
+#define I2S_TX_HUNG_INT_RAW_V  0x1
+#define I2S_TX_HUNG_INT_RAW_S  3
+/* I2S_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_rx_hung_int interrupt*/
+#define I2S_RX_HUNG_INT_RAW  (BIT(2))
+#define I2S_RX_HUNG_INT_RAW_M  (BIT(2))
+#define I2S_RX_HUNG_INT_RAW_V  0x1
+#define I2S_RX_HUNG_INT_RAW_S  2
+/* I2S_TX_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_tx_done_int interrupt*/
+#define I2S_TX_DONE_INT_RAW  (BIT(1))
+#define I2S_TX_DONE_INT_RAW_M  (BIT(1))
+#define I2S_TX_DONE_INT_RAW_V  0x1
+#define I2S_TX_DONE_INT_RAW_S  1
+/* I2S_RX_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_rx_done_int interrupt*/
+#define I2S_RX_DONE_INT_RAW  (BIT(0))
+#define I2S_RX_DONE_INT_RAW_M  (BIT(0))
+#define I2S_RX_DONE_INT_RAW_V  0x1
+#define I2S_RX_DONE_INT_RAW_S  0
+
+#define I2S_INT_ST_REG(i)          (REG_I2S_BASE(i) + 0x0010)
+/* I2S_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_tx_hung_int interrupt*/
+#define I2S_TX_HUNG_INT_ST  (BIT(3))
+#define I2S_TX_HUNG_INT_ST_M  (BIT(3))
+#define I2S_TX_HUNG_INT_ST_V  0x1
+#define I2S_TX_HUNG_INT_ST_S  3
+/* I2S_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_rx_hung_int interrupt*/
+#define I2S_RX_HUNG_INT_ST  (BIT(2))
+#define I2S_RX_HUNG_INT_ST_M  (BIT(2))
+#define I2S_RX_HUNG_INT_ST_V  0x1
+#define I2S_RX_HUNG_INT_ST_S  2
+/* I2S_TX_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_tx_done_int interrupt*/
+#define I2S_TX_DONE_INT_ST  (BIT(1))
+#define I2S_TX_DONE_INT_ST_M  (BIT(1))
+#define I2S_TX_DONE_INT_ST_V  0x1
+#define I2S_TX_DONE_INT_ST_S  1
+/* I2S_RX_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_rx_done_int interrupt*/
+#define I2S_RX_DONE_INT_ST  (BIT(0))
+#define I2S_RX_DONE_INT_ST_M  (BIT(0))
+#define I2S_RX_DONE_INT_ST_V  0x1
+#define I2S_RX_DONE_INT_ST_S  0
+
+#define I2S_INT_ENA_REG(i)          (REG_I2S_BASE(i) + 0x0014)
+/* I2S_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_tx_hung_int interrupt*/
+#define I2S_TX_HUNG_INT_ENA  (BIT(3))
+#define I2S_TX_HUNG_INT_ENA_M  (BIT(3))
+#define I2S_TX_HUNG_INT_ENA_V  0x1
+#define I2S_TX_HUNG_INT_ENA_S  3
+/* I2S_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_rx_hung_int interrupt*/
+#define I2S_RX_HUNG_INT_ENA  (BIT(2))
+#define I2S_RX_HUNG_INT_ENA_M  (BIT(2))
+#define I2S_RX_HUNG_INT_ENA_V  0x1
+#define I2S_RX_HUNG_INT_ENA_S  2
+/* I2S_TX_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_tx_done_int interrupt*/
+#define I2S_TX_DONE_INT_ENA  (BIT(1))
+#define I2S_TX_DONE_INT_ENA_M  (BIT(1))
+#define I2S_TX_DONE_INT_ENA_V  0x1
+#define I2S_TX_DONE_INT_ENA_S  1
+/* I2S_RX_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_rx_done_int interrupt*/
+#define I2S_RX_DONE_INT_ENA  (BIT(0))
+#define I2S_RX_DONE_INT_ENA_M  (BIT(0))
+#define I2S_RX_DONE_INT_ENA_V  0x1
+#define I2S_RX_DONE_INT_ENA_S  0
+
+#define I2S_INT_CLR_REG(i)          (REG_I2S_BASE(i) + 0x0018)
+/* I2S_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_tx_hung_int interrupt*/
+#define I2S_TX_HUNG_INT_CLR  (BIT(3))
+#define I2S_TX_HUNG_INT_CLR_M  (BIT(3))
+#define I2S_TX_HUNG_INT_CLR_V  0x1
+#define I2S_TX_HUNG_INT_CLR_S  3
+/* I2S_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_rx_hung_int interrupt*/
+#define I2S_RX_HUNG_INT_CLR  (BIT(2))
+#define I2S_RX_HUNG_INT_CLR_M  (BIT(2))
+#define I2S_RX_HUNG_INT_CLR_V  0x1
+#define I2S_RX_HUNG_INT_CLR_S  2
+/* I2S_TX_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_tx_done_int interrupt*/
+#define I2S_TX_DONE_INT_CLR  (BIT(1))
+#define I2S_TX_DONE_INT_CLR_M  (BIT(1))
+#define I2S_TX_DONE_INT_CLR_V  0x1
+#define I2S_TX_DONE_INT_CLR_S  1
+/* I2S_RX_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_rx_done_int interrupt*/
+#define I2S_RX_DONE_INT_CLR  (BIT(0))
+#define I2S_RX_DONE_INT_CLR_M  (BIT(0))
+#define I2S_RX_DONE_INT_CLR_V  0x1
+#define I2S_RX_DONE_INT_CLR_S  0
+
+#define I2S_RX_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0020)
+/* I2S_RX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */
+/*description: 1: Enable I2S PDM Rx mode . 0: Disable.*/
+#define I2S_RX_PDM_EN  (BIT(20))
+#define I2S_RX_PDM_EN_M  (BIT(20))
+#define I2S_RX_PDM_EN_V  0x1
+#define I2S_RX_PDM_EN_S  20
+/* I2S_RX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */
+/*description: 1: Enable I2S TDM Rx mode . 0: Disable.*/
+#define I2S_RX_TDM_EN  (BIT(19))
+#define I2S_RX_TDM_EN_M  (BIT(19))
+#define I2S_RX_TDM_EN_V  0x1
+#define I2S_RX_TDM_EN_S  19
+/* I2S_RX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */
+/*description: I2S Rx bit endian. 1:small endian  the LSB is received first.
+ 0:big endian  the MSB is received first.*/
+#define I2S_RX_BIT_ORDER  (BIT(18))
+#define I2S_RX_BIT_ORDER_M  (BIT(18))
+#define I2S_RX_BIT_ORDER_V  0x1
+#define I2S_RX_BIT_ORDER_S  18
+/* I2S_RX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: 0: WS should be 0 when receiving left channel data  and WS is
+ 1in right channel.  1: WS should be 1 when receiving left channel data  and WS is 0in right channel.*/
+#define I2S_RX_WS_IDLE_POL  (BIT(17))
+#define I2S_RX_WS_IDLE_POL_M  (BIT(17))
+#define I2S_RX_WS_IDLE_POL_V  0x1
+#define I2S_RX_WS_IDLE_POL_S  17
+/* I2S_RX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/
+#define I2S_RX_24_FILL_EN  (BIT(16))
+#define I2S_RX_24_FILL_EN_M  (BIT(16))
+#define I2S_RX_24_FILL_EN_V  0x1
+#define I2S_RX_24_FILL_EN_S  16
+/* I2S_RX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/
+#define I2S_RX_LEFT_ALIGN  (BIT(15))
+#define I2S_RX_LEFT_ALIGN_M  (BIT(15))
+#define I2S_RX_LEFT_ALIGN_V  0x1
+#define I2S_RX_LEFT_ALIGN_S  15
+/* I2S_RX_STOP_MODE : R/W ;bitpos:[14:13] ;default: 2'd0 ; */
+/*description: 0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop
+ when reg_rx_start is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/
+#define I2S_RX_STOP_MODE  0x00000003
+#define I2S_RX_STOP_MODE_M  ((I2S_RX_STOP_MODE_V)<<(I2S_RX_STOP_MODE_S))
+#define I2S_RX_STOP_MODE_V  0x3
+#define I2S_RX_STOP_MODE_S  13
+/* I2S_RX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: Set this bit to bypass Compress/Decompress module for received data.*/
+#define I2S_RX_PCM_BYPASS  (BIT(12))
+#define I2S_RX_PCM_BYPASS_M  (BIT(12))
+#define I2S_RX_PCM_BYPASS_V  0x1
+#define I2S_RX_PCM_BYPASS_S  12
+/* I2S_RX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h1 ; */
+/*description: I2S RX compress/decompress configuration bit. & 0 (atol): A-Law
+ decompress  1 (ltoa) : A-Law compress  2 (utol) : u-Law decompress  3 (ltou) : u-Law compress. &*/
+#define I2S_RX_PCM_CONF  0x00000003
+#define I2S_RX_PCM_CONF_M  ((I2S_RX_PCM_CONF_V)<<(I2S_RX_PCM_CONF_S))
+#define I2S_RX_PCM_CONF_V  0x3
+#define I2S_RX_PCM_CONF_S  10
+/* I2S_RX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: 1: The first channel data value is valid in I2S RX mono mode.
+   0: The second channel data value is valid in I2S RX mono mode.*/
+#define I2S_RX_MONO_FST_VLD  (BIT(9))
+#define I2S_RX_MONO_FST_VLD_M  (BIT(9))
+#define I2S_RX_MONO_FST_VLD_V  0x1
+#define I2S_RX_MONO_FST_VLD_S  9
+/* I2S_RX_UPDATE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set 1 to update I2S RX registers from APB clock domain to I2S
+ RX clock domain. This bit will be cleared by hardware after update register done.*/
+#define I2S_RX_UPDATE  (BIT(8))
+#define I2S_RX_UPDATE_M  (BIT(8))
+#define I2S_RX_UPDATE_V  0x1
+#define I2S_RX_UPDATE_S  8
+/* I2S_RX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: I2S Rx byte endian  1: low addr value to high addr. 0: low addr
+ with low addr value.*/
+#define I2S_RX_BIG_ENDIAN  (BIT(7))
+#define I2S_RX_BIG_ENDIAN_M  (BIT(7))
+#define I2S_RX_BIG_ENDIAN_V  0x1
+#define I2S_RX_BIG_ENDIAN_S  7
+/* I2S_RX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable receiver  in mono mode*/
+#define I2S_RX_MONO  (BIT(5))
+#define I2S_RX_MONO_M  (BIT(5))
+#define I2S_RX_MONO_V  0x1
+#define I2S_RX_MONO_S  5
+/* I2S_RX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to enable slave receiver mode*/
+#define I2S_RX_SLAVE_MOD  (BIT(3))
+#define I2S_RX_SLAVE_MOD_M  (BIT(3))
+#define I2S_RX_SLAVE_MOD_V  0x1
+#define I2S_RX_SLAVE_MOD_S  3
+/* I2S_RX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to start receiving data*/
+#define I2S_RX_START  (BIT(2))
+#define I2S_RX_START_M  (BIT(2))
+#define I2S_RX_START_V  0x1
+#define I2S_RX_START_S  2
+/* I2S_RX_FIFO_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to reset Rx AFIFO*/
+#define I2S_RX_FIFO_RESET  (BIT(1))
+#define I2S_RX_FIFO_RESET_M  (BIT(1))
+#define I2S_RX_FIFO_RESET_V  0x1
+#define I2S_RX_FIFO_RESET_S  1
+/* I2S_RX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to reset receiver*/
+#define I2S_RX_RESET  (BIT(0))
+#define I2S_RX_RESET_M  (BIT(0))
+#define I2S_RX_RESET_V  0x1
+#define I2S_RX_RESET_S  0
+
+#define I2S_TX_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0024)
+/* I2S_SIG_LOOPBACK : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Enable signal loop back mode with transmitter module and receiver
+ module sharing the same WS and BCK signals.*/
+#define I2S_SIG_LOOPBACK  (BIT(27))
+#define I2S_SIG_LOOPBACK_M  (BIT(27))
+#define I2S_SIG_LOOPBACK_V  0x1
+#define I2S_SIG_LOOPBACK_S  27
+/* I2S_TX_CHAN_MOD : R/W ;bitpos:[26:24] ;default: 3'b0 ; */
+/*description: I2S transmitter channel mode configuration bits.*/
+#define I2S_TX_CHAN_MOD  0x00000007
+#define I2S_TX_CHAN_MOD_M  ((I2S_TX_CHAN_MOD_V)<<(I2S_TX_CHAN_MOD_S))
+#define I2S_TX_CHAN_MOD_V  0x7
+#define I2S_TX_CHAN_MOD_S  24
+/* I2S_TX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */
+/*description: 1: Enable I2S PDM Tx mode . 0: Disable.*/
+#define I2S_TX_PDM_EN  (BIT(20))
+#define I2S_TX_PDM_EN_M  (BIT(20))
+#define I2S_TX_PDM_EN_V  0x1
+#define I2S_TX_PDM_EN_S  20
+/* I2S_TX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */
+/*description: 1: Enable I2S TDM Tx mode . 0: Disable.*/
+#define I2S_TX_TDM_EN  (BIT(19))
+#define I2S_TX_TDM_EN_M  (BIT(19))
+#define I2S_TX_TDM_EN_V  0x1
+#define I2S_TX_TDM_EN_S  19
+/* I2S_TX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */
+/*description: I2S Tx bit endian. 1:small endian  the LSB is sent first. 0:big
+ endian  the MSB is sent first.*/
+#define I2S_TX_BIT_ORDER  (BIT(18))
+#define I2S_TX_BIT_ORDER_M  (BIT(18))
+#define I2S_TX_BIT_ORDER_V  0x1
+#define I2S_TX_BIT_ORDER_S  18
+/* I2S_TX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: 0: WS should be 0 when sending left channel data  and WS is 1in
+ right channel.  1: WS should be 1 when sending left channel data  and WS is 0in right channel.*/
+#define I2S_TX_WS_IDLE_POL  (BIT(17))
+#define I2S_TX_WS_IDLE_POL_M  (BIT(17))
+#define I2S_TX_WS_IDLE_POL_V  0x1
+#define I2S_TX_WS_IDLE_POL_S  17
+/* I2S_TX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/
+#define I2S_TX_24_FILL_EN  (BIT(16))
+#define I2S_TX_24_FILL_EN_M  (BIT(16))
+#define I2S_TX_24_FILL_EN_V  0x1
+#define I2S_TX_24_FILL_EN_S  16
+/* I2S_TX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'h1 ; */
+/*description: 1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/
+#define I2S_TX_LEFT_ALIGN  (BIT(15))
+#define I2S_TX_LEFT_ALIGN_M  (BIT(15))
+#define I2S_TX_LEFT_ALIGN_V  0x1
+#define I2S_TX_LEFT_ALIGN_S  15
+/* I2S_TX_STOP_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
+/*description: Set this bit to stop disable output BCK signal and WS signal
+ when tx FIFO is emtpy*/
+#define I2S_TX_STOP_EN  (BIT(13))
+#define I2S_TX_STOP_EN_M  (BIT(13))
+#define I2S_TX_STOP_EN_V  0x1
+#define I2S_TX_STOP_EN_S  13
+/* I2S_TX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: Set this bit to bypass  Compress/Decompress module for transmitted data.*/
+#define I2S_TX_PCM_BYPASS  (BIT(12))
+#define I2S_TX_PCM_BYPASS_M  (BIT(12))
+#define I2S_TX_PCM_BYPASS_V  0x1
+#define I2S_TX_PCM_BYPASS_S  12
+/* I2S_TX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: I2S TX compress/decompress configuration bit. & 0 (atol): A-Law
+ decompress  1 (ltoa) : A-Law compress  2 (utol) : u-Law decompress  3 (ltou) : u-Law compress. &*/
+#define I2S_TX_PCM_CONF  0x00000003
+#define I2S_TX_PCM_CONF_M  ((I2S_TX_PCM_CONF_V)<<(I2S_TX_PCM_CONF_S))
+#define I2S_TX_PCM_CONF_V  0x3
+#define I2S_TX_PCM_CONF_S  10
+/* I2S_TX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: 1: The first channel data value is valid in I2S TX mono mode.
+   0: The second channel data value is valid in I2S TX mono mode.*/
+#define I2S_TX_MONO_FST_VLD  (BIT(9))
+#define I2S_TX_MONO_FST_VLD_M  (BIT(9))
+#define I2S_TX_MONO_FST_VLD_V  0x1
+#define I2S_TX_MONO_FST_VLD_S  9
+/* I2S_TX_UPDATE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set 1 to update I2S TX registers from APB clock domain to I2S
+ TX clock domain. This bit will be cleared by hardware after update register done.*/
+#define I2S_TX_UPDATE  (BIT(8))
+#define I2S_TX_UPDATE_M  (BIT(8))
+#define I2S_TX_UPDATE_V  0x1
+#define I2S_TX_UPDATE_S  8
+/* I2S_TX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: I2S Tx byte endian  1: low addr value to high addr.  0: low addr
+ with low addr value.*/
+#define I2S_TX_BIG_ENDIAN  (BIT(7))
+#define I2S_TX_BIG_ENDIAN_M  (BIT(7))
+#define I2S_TX_BIG_ENDIAN_V  0x1
+#define I2S_TX_BIG_ENDIAN_S  7
+/* I2S_TX_CHAN_EQUAL : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: 1: The value of Left channel data is equal to the value of right
+ channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/
+#define I2S_TX_CHAN_EQUAL  (BIT(6))
+#define I2S_TX_CHAN_EQUAL_M  (BIT(6))
+#define I2S_TX_CHAN_EQUAL_V  0x1
+#define I2S_TX_CHAN_EQUAL_S  6
+/* I2S_TX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable transmitter in mono mode*/
+#define I2S_TX_MONO  (BIT(5))
+#define I2S_TX_MONO_M  (BIT(5))
+#define I2S_TX_MONO_V  0x1
+#define I2S_TX_MONO_S  5
+/* I2S_TX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to enable slave transmitter mode*/
+#define I2S_TX_SLAVE_MOD  (BIT(3))
+#define I2S_TX_SLAVE_MOD_M  (BIT(3))
+#define I2S_TX_SLAVE_MOD_V  0x1
+#define I2S_TX_SLAVE_MOD_S  3
+/* I2S_TX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to start transmitting data*/
+#define I2S_TX_START  (BIT(2))
+#define I2S_TX_START_M  (BIT(2))
+#define I2S_TX_START_V  0x1
+#define I2S_TX_START_S  2
+/* I2S_TX_FIFO_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to reset Tx AFIFO*/
+#define I2S_TX_FIFO_RESET  (BIT(1))
+#define I2S_TX_FIFO_RESET_M  (BIT(1))
+#define I2S_TX_FIFO_RESET_V  0x1
+#define I2S_TX_FIFO_RESET_S  1
+/* I2S_TX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to reset transmitter*/
+#define I2S_TX_RESET  (BIT(0))
+#define I2S_TX_RESET_M  (BIT(0))
+#define I2S_TX_RESET_V  0x1
+#define I2S_TX_RESET_S  0
+
+#define I2S_RX_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x0028)
+/* I2S_RX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: Set this bit to enable receiver in Phillips standard mode*/
+#define I2S_RX_MSB_SHIFT  (BIT(29))
+#define I2S_RX_MSB_SHIFT_M  (BIT(29))
+#define I2S_RX_MSB_SHIFT_V  0x1
+#define I2S_RX_MSB_SHIFT_S  29
+/* I2S_RX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hF ; */
+/*description: The Rx bit number for each channel minus 1in TDM mode.*/
+#define I2S_RX_TDM_CHAN_BITS  0x0000001F
+#define I2S_RX_TDM_CHAN_BITS_M  ((I2S_RX_TDM_CHAN_BITS_V)<<(I2S_RX_TDM_CHAN_BITS_S))
+#define I2S_RX_TDM_CHAN_BITS_V  0x1F
+#define I2S_RX_TDM_CHAN_BITS_S  24
+/* I2S_RX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hF ; */
+/*description: I2S Rx half sample bits -1.*/
+#define I2S_RX_HALF_SAMPLE_BITS  0x0000003F
+#define I2S_RX_HALF_SAMPLE_BITS_M  ((I2S_RX_HALF_SAMPLE_BITS_V)<<(I2S_RX_HALF_SAMPLE_BITS_S))
+#define I2S_RX_HALF_SAMPLE_BITS_V  0x3F
+#define I2S_RX_HALF_SAMPLE_BITS_S  18
+/* I2S_RX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hF ; */
+/*description: Set the bits to configure bit length of I2S receiver channel.*/
+#define I2S_RX_BITS_MOD  0x0000001F
+#define I2S_RX_BITS_MOD_M  ((I2S_RX_BITS_MOD_V)<<(I2S_RX_BITS_MOD_S))
+#define I2S_RX_BITS_MOD_V  0x1F
+#define I2S_RX_BITS_MOD_S  13
+/* I2S_RX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */
+/*description: Bit clock configuration bits in receiver mode.*/
+#define I2S_RX_BCK_DIV_NUM  0x0000003F
+#define I2S_RX_BCK_DIV_NUM_M  ((I2S_RX_BCK_DIV_NUM_V)<<(I2S_RX_BCK_DIV_NUM_S))
+#define I2S_RX_BCK_DIV_NUM_V  0x3F
+#define I2S_RX_BCK_DIV_NUM_S  7
+/* I2S_RX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */
+/*description: The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/
+#define I2S_RX_TDM_WS_WIDTH  0x0000007F
+#define I2S_RX_TDM_WS_WIDTH_M  ((I2S_RX_TDM_WS_WIDTH_V)<<(I2S_RX_TDM_WS_WIDTH_S))
+#define I2S_RX_TDM_WS_WIDTH_V  0x7F
+#define I2S_RX_TDM_WS_WIDTH_S  0
+
+#define I2S_TX_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x002C)
+/* I2S_TX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: Set this bit to enable transmitter in Phillips standard mode*/
+#define I2S_TX_MSB_SHIFT  (BIT(29))
+#define I2S_TX_MSB_SHIFT_M  (BIT(29))
+#define I2S_TX_MSB_SHIFT_V  0x1
+#define I2S_TX_MSB_SHIFT_S  29
+/* I2S_TX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hF ; */
+/*description: The Tx bit number for each channel minus 1in TDM mode.*/
+#define I2S_TX_TDM_CHAN_BITS  0x0000001F
+#define I2S_TX_TDM_CHAN_BITS_M  ((I2S_TX_TDM_CHAN_BITS_V)<<(I2S_TX_TDM_CHAN_BITS_S))
+#define I2S_TX_TDM_CHAN_BITS_V  0x1F
+#define I2S_TX_TDM_CHAN_BITS_S  24
+/* I2S_TX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hF ; */
+/*description: I2S Tx half sample bits -1.*/
+#define I2S_TX_HALF_SAMPLE_BITS  0x0000003F
+#define I2S_TX_HALF_SAMPLE_BITS_M  ((I2S_TX_HALF_SAMPLE_BITS_V)<<(I2S_TX_HALF_SAMPLE_BITS_S))
+#define I2S_TX_HALF_SAMPLE_BITS_V  0x3F
+#define I2S_TX_HALF_SAMPLE_BITS_S  18
+/* I2S_TX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hF ; */
+/*description: Set the bits to configure bit length of I2S transmitter channel.*/
+#define I2S_TX_BITS_MOD  0x0000001F
+#define I2S_TX_BITS_MOD_M  ((I2S_TX_BITS_MOD_V)<<(I2S_TX_BITS_MOD_S))
+#define I2S_TX_BITS_MOD_V  0x1F
+#define I2S_TX_BITS_MOD_S  13
+/* I2S_TX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */
+/*description: Bit clock configuration bits in transmitter mode.*/
+#define I2S_TX_BCK_DIV_NUM  0x0000003F
+#define I2S_TX_BCK_DIV_NUM_M  ((I2S_TX_BCK_DIV_NUM_V)<<(I2S_TX_BCK_DIV_NUM_S))
+#define I2S_TX_BCK_DIV_NUM_V  0x3F
+#define I2S_TX_BCK_DIV_NUM_S  7
+/* I2S_TX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */
+/*description: The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/
+#define I2S_TX_TDM_WS_WIDTH  0x0000007F
+#define I2S_TX_TDM_WS_WIDTH_M  ((I2S_TX_TDM_WS_WIDTH_V)<<(I2S_TX_TDM_WS_WIDTH_S))
+#define I2S_TX_TDM_WS_WIDTH_V  0x7F
+#define I2S_TX_TDM_WS_WIDTH_S  0
+
+#define I2S_RX_CLKM_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0030)
+/* I2S_MCLK_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: 0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module
+ clock as I2S_MCLK_OUT.*/
+#define I2S_MCLK_SEL  (BIT(29))
+#define I2S_MCLK_SEL_M  (BIT(29))
+#define I2S_MCLK_SEL_V  0x1
+#define I2S_MCLK_SEL_S  29
+/* I2S_RX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */
+/*description: Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160.
+ 3: I2S_MCLK_in.*/
+#define I2S_RX_CLK_SEL  0x00000003
+#define I2S_RX_CLK_SEL_M  ((I2S_RX_CLK_SEL_V)<<(I2S_RX_CLK_SEL_S))
+#define I2S_RX_CLK_SEL_V  0x3
+#define I2S_RX_CLK_SEL_S  27
+/* I2S_RX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: I2S Rx module clock enable signal.*/
+#define I2S_RX_CLK_ACTIVE  (BIT(26))
+#define I2S_RX_CLK_ACTIVE_M  (BIT(26))
+#define I2S_RX_CLK_ACTIVE_V  0x1
+#define I2S_RX_CLK_ACTIVE_S  26
+/* I2S_RX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
+/*description: Integral I2S clock divider value*/
+#define I2S_RX_CLKM_DIV_NUM  0x000000FF
+#define I2S_RX_CLKM_DIV_NUM_M  ((I2S_RX_CLKM_DIV_NUM_V)<<(I2S_RX_CLKM_DIV_NUM_S))
+#define I2S_RX_CLKM_DIV_NUM_V  0xFF
+#define I2S_RX_CLKM_DIV_NUM_S  0
+
+#define I2S_TX_CLKM_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0034)
+/* I2S_CLK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to enable clk gate*/
+#define I2S_CLK_EN  (BIT(29))
+#define I2S_CLK_EN_M  (BIT(29))
+#define I2S_CLK_EN_V  0x1
+#define I2S_CLK_EN_S  29
+/* I2S_TX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */
+/*description: Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2:
+ CLK160. 3: I2S_MCLK_in.*/
+#define I2S_TX_CLK_SEL  0x00000003
+#define I2S_TX_CLK_SEL_M  ((I2S_TX_CLK_SEL_V)<<(I2S_TX_CLK_SEL_S))
+#define I2S_TX_CLK_SEL_V  0x3
+#define I2S_TX_CLK_SEL_S  27
+/* I2S_TX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: I2S Tx module clock enable signal.*/
+#define I2S_TX_CLK_ACTIVE  (BIT(26))
+#define I2S_TX_CLK_ACTIVE_M  (BIT(26))
+#define I2S_TX_CLK_ACTIVE_V  0x1
+#define I2S_TX_CLK_ACTIVE_S  26
+/* I2S_TX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
+/*description: Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a).
+ There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <= a/2  z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2  z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/
+#define I2S_TX_CLKM_DIV_NUM  0x000000FF
+#define I2S_TX_CLKM_DIV_NUM_M  ((I2S_TX_CLKM_DIV_NUM_V)<<(I2S_TX_CLKM_DIV_NUM_S))
+#define I2S_TX_CLKM_DIV_NUM_V  0xFF
+#define I2S_TX_CLKM_DIV_NUM_S  0
+
+#define I2S_RX_CLKM_DIV_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0038)
+/* I2S_RX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: For b <= a/2  the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b >
+ a/2  the value of I2S_RX_CLKM_DIV_YN1 is 1.*/
+#define I2S_RX_CLKM_DIV_YN1  (BIT(27))
+#define I2S_RX_CLKM_DIV_YN1_M  (BIT(27))
+#define I2S_RX_CLKM_DIV_YN1_V  0x1
+#define I2S_RX_CLKM_DIV_YN1_S  27
+/* I2S_RX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */
+/*description: For b <= a/2  the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For
+ b > a/2  the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/
+#define I2S_RX_CLKM_DIV_X  0x000001FF
+#define I2S_RX_CLKM_DIV_X_M  ((I2S_RX_CLKM_DIV_X_V)<<(I2S_RX_CLKM_DIV_X_S))
+#define I2S_RX_CLKM_DIV_X_V  0x1FF
+#define I2S_RX_CLKM_DIV_X_S  18
+/* I2S_RX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */
+/*description: For b <= a/2  the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b
+ > a/2  the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/
+#define I2S_RX_CLKM_DIV_Y  0x000001FF
+#define I2S_RX_CLKM_DIV_Y_M  ((I2S_RX_CLKM_DIV_Y_V)<<(I2S_RX_CLKM_DIV_Y_S))
+#define I2S_RX_CLKM_DIV_Y_V  0x1FF
+#define I2S_RX_CLKM_DIV_Y_S  9
+/* I2S_RX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: For b <= a/2  the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2
+  the value of I2S_RX_CLKM_DIV_Z is (a-b).*/
+#define I2S_RX_CLKM_DIV_Z  0x000001FF
+#define I2S_RX_CLKM_DIV_Z_M  ((I2S_RX_CLKM_DIV_Z_V)<<(I2S_RX_CLKM_DIV_Z_S))
+#define I2S_RX_CLKM_DIV_Z_V  0x1FF
+#define I2S_RX_CLKM_DIV_Z_S  0
+
+#define I2S_TX_CLKM_DIV_CONF_REG(i)          (REG_I2S_BASE(i) + 0x003C)
+/* I2S_TX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: For b <= a/2  the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b >
+ a/2  the value of I2S_TX_CLKM_DIV_YN1 is 1.*/
+#define I2S_TX_CLKM_DIV_YN1  (BIT(27))
+#define I2S_TX_CLKM_DIV_YN1_M  (BIT(27))
+#define I2S_TX_CLKM_DIV_YN1_V  0x1
+#define I2S_TX_CLKM_DIV_YN1_S  27
+/* I2S_TX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */
+/*description: For b <= a/2  the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For
+ b > a/2  the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/
+#define I2S_TX_CLKM_DIV_X  0x000001FF
+#define I2S_TX_CLKM_DIV_X_M  ((I2S_TX_CLKM_DIV_X_V)<<(I2S_TX_CLKM_DIV_X_S))
+#define I2S_TX_CLKM_DIV_X_V  0x1FF
+#define I2S_TX_CLKM_DIV_X_S  18
+/* I2S_TX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */
+/*description: For b <= a/2  the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b
+ > a/2  the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/
+#define I2S_TX_CLKM_DIV_Y  0x000001FF
+#define I2S_TX_CLKM_DIV_Y_M  ((I2S_TX_CLKM_DIV_Y_V)<<(I2S_TX_CLKM_DIV_Y_S))
+#define I2S_TX_CLKM_DIV_Y_V  0x1FF
+#define I2S_TX_CLKM_DIV_Y_S  9
+/* I2S_TX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: For b <= a/2  the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2
+  the value of I2S_TX_CLKM_DIV_Z is (a-b).*/
+#define I2S_TX_CLKM_DIV_Z  0x000001FF
+#define I2S_TX_CLKM_DIV_Z_M  ((I2S_TX_CLKM_DIV_Z_V)<<(I2S_TX_CLKM_DIV_Z_S))
+#define I2S_TX_CLKM_DIV_Z_V  0x1FF
+#define I2S_TX_CLKM_DIV_Z_S  0
+
+#define I2S_TX_PCM2PDM_CONF_REG(i)          (REG_I2S_BASE(i) + 0x040)
+/* I2S_PCM2PDM_CONV_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: I2S TX PDM Converter enable.*/
+#define I2S_PCM2PDM_CONV_EN    (BIT(25))
+#define I2S_PCM2PDM_CONV_EN_M  (BIT(25))
+#define I2S_PCM2PDM_CONV_EN_V  0x1
+#define I2S_PCM2PDM_CONV_EN_S  25
+/* I2S_TX_PDM_DAC_MODE_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: I2S TX PDM dac 2channel enable.*/
+#define I2S_TX_PDM_DAC_MODE_EN    (BIT(24))
+#define I2S_TX_PDM_DAC_MODE_EN_M  (BIT(24))
+#define I2S_TX_PDM_DAC_MODE_EN_V  0x1
+#define I2S_TX_PDM_DAC_MODE_EN_S  24
+/* I2S_TX_PDM_DAC_2OUT_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: I2S TX PDM dac mode enable.*/
+#define I2S_TX_PDM_DAC_2OUT_EN    (BIT(23))
+#define I2S_TX_PDM_DAC_2OUT_EN_M  (BIT(23))
+#define I2S_TX_PDM_DAC_2OUT_EN_V  0x1
+#define I2S_TX_PDM_DAC_2OUT_EN_S  23
+/* I2S_TX_PDM_SIGMADELTA_DITHER : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: I2S TX PDM sigmadelta dither value.*/
+#define I2S_TX_PDM_SIGMADELTA_DITHER    (BIT(22))
+#define I2S_TX_PDM_SIGMADELTA_DITHER_M  (BIT(22))
+#define I2S_TX_PDM_SIGMADELTA_DITHER_V  0x1
+#define I2S_TX_PDM_SIGMADELTA_DITHER_S  22
+/* I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: I2S TX PDM sigmadelta dither2 value.*/
+#define I2S_TX_PDM_SIGMADELTA_DITHER2    (BIT(21))
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_M  (BIT(21))
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_V  0x1
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_S  21
+/* I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W ;bitpos:[20:19] ;default: 2'h1 ; */
+/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT    0x00000003
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M  ((I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V)<<(I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S))
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V  0x3
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S  19
+/* I2S_TX_PDM_SINC_IN_SHIFT : R/W ;bitpos:[18:17] ;default: 2'h1 ; */
+/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
+#define I2S_TX_PDM_SINC_IN_SHIFT    0x00000003
+#define I2S_TX_PDM_SINC_IN_SHIFT_M  ((I2S_TX_PDM_SINC_IN_SHIFT_V)<<(I2S_TX_PDM_SINC_IN_SHIFT_S))
+#define I2S_TX_PDM_SINC_IN_SHIFT_V  0x3
+#define I2S_TX_PDM_SINC_IN_SHIFT_S  17
+/* I2S_TX_PDM_LP_IN_SHIFT : R/W ;bitpos:[16:15] ;default: 2'h1 ; */
+/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
+#define I2S_TX_PDM_LP_IN_SHIFT    0x00000003
+#define I2S_TX_PDM_LP_IN_SHIFT_M  ((I2S_TX_PDM_LP_IN_SHIFT_V)<<(I2S_TX_PDM_LP_IN_SHIFT_S))
+#define I2S_TX_PDM_LP_IN_SHIFT_V  0x3
+#define I2S_TX_PDM_LP_IN_SHIFT_S  15
+/* I2S_TX_PDM_HP_IN_SHIFT : R/W ;bitpos:[14:13] ;default: 2'h1 ; */
+/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
+#define I2S_TX_PDM_HP_IN_SHIFT    0x00000003
+#define I2S_TX_PDM_HP_IN_SHIFT_M  ((I2S_TX_PDM_HP_IN_SHIFT_V)<<(I2S_TX_PDM_HP_IN_SHIFT_S))
+#define I2S_TX_PDM_HP_IN_SHIFT_V  0x3
+#define I2S_TX_PDM_HP_IN_SHIFT_S  13
+/* I2S_TX_PDM_PRESCALE : R/W ;bitpos:[12:5] ;default: 8'h0 ; */
+/*description: I2S TX PDM prescale for sigmadelta.*/
+#define I2S_TX_PDM_PRESCALE    0x000000FF
+#define I2S_TX_PDM_PRESCALE_M  ((I2S_TX_PDM_PRESCALE_V)<<(I2S_TX_PDM_PRESCALE_S))
+#define I2S_TX_PDM_PRESCALE_V  0xFF
+#define I2S_TX_PDM_PRESCALE_S  5
+/* I2S_TX_PDM_SINC_OSR2 : R/W ;bitpos:[4:1] ;default: 4'h2 ; */
+/*description: I2S TX PDM OSR2 value.*/
+#define I2S_TX_PDM_SINC_OSR2    0x0000000F
+#define I2S_TX_PDM_SINC_OSR2_M  ((I2S_TX_PDM_SINC_OSR2_V)<<(I2S_TX_PDM_SINC_OSR2_S))
+#define I2S_TX_PDM_SINC_OSR2_V  0xF
+#define I2S_TX_PDM_SINC_OSR2_S  1
+/* I2S_TX_PDM_HP_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: I2S TX PDM bypass hp filter or not. The option has been removed..*/
+#define I2S_TX_PDM_HP_BYPASS    (BIT(0))
+#define I2S_TX_PDM_HP_BYPASS_M  (BIT(0))
+#define I2S_TX_PDM_HP_BYPASS_V  0x1
+#define I2S_TX_PDM_HP_BYPASS_S  0
+
+#define I2S_TX_PCM2PDM_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x44)
+/* I2S_TX_IIR_HP_MULT12_0 : R/W ;bitpos:[25:23] ;default: 3'd7 ; */
+/*description: The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MUL
+T12_0[2:0]).*/
+#define I2S_TX_IIR_HP_MULT12_0    0x00000007
+#define I2S_TX_IIR_HP_MULT12_0_M  ((I2S_TX_IIR_HP_MULT12_0_V)<<(I2S_TX_IIR_HP_MULT12_0_S))
+#define I2S_TX_IIR_HP_MULT12_0_V  0x7
+#define I2S_TX_IIR_HP_MULT12_0_S  23
+/* I2S_TX_IIR_HP_MULT12_5 : R/W ;bitpos:[22:20] ;default: 3'd7 ; */
+/*description: The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MUL
+T12_5[2:0]).*/
+#define I2S_TX_IIR_HP_MULT12_5    0x00000007
+#define I2S_TX_IIR_HP_MULT12_5_M  ((I2S_TX_IIR_HP_MULT12_5_V)<<(I2S_TX_IIR_HP_MULT12_5_S))
+#define I2S_TX_IIR_HP_MULT12_5_V  0x7
+#define I2S_TX_IIR_HP_MULT12_5_S  20
+/* I2S_TX_PDM_FS : R/W ;bitpos:[19:10] ;default: 10'd480 ; */
+/*description: I2S TX PDM Fs.*/
+#define I2S_TX_PDM_FS    0x000003FF
+#define I2S_TX_PDM_FS_M  ((I2S_TX_PDM_FS_V)<<(I2S_TX_PDM_FS_S))
+#define I2S_TX_PDM_FS_V  0x3FF
+#define I2S_TX_PDM_FS_S  10
+/* I2S_TX_PDM_FP : R/W ;bitpos:[9:0] ;default: 10'd960 ; */
+/*description: I2S TX PDM Fp.*/
+#define I2S_TX_PDM_FP    0x000003FF
+#define I2S_TX_PDM_FP_M  ((I2S_TX_PDM_FP_V)<<(I2S_TX_PDM_FP_S))
+#define I2S_TX_PDM_FP_V  0x3FF
+#define I2S_TX_PDM_FP_S  0
+
+#define I2S_RX_TDM_CTRL_REG(i)          (REG_I2S_BASE(i) + 0x050)
+/* I2S_RX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */
+/*description: The total channel number of I2S TX TDM mode.*/
+#define I2S_RX_TDM_TOT_CHAN_NUM  0x0000000F
+#define I2S_RX_TDM_TOT_CHAN_NUM_M  ((I2S_RX_TDM_TOT_CHAN_NUM_V)<<(I2S_RX_TDM_TOT_CHAN_NUM_S))
+#define I2S_RX_TDM_TOT_CHAN_NUM_V  0xF
+#define I2S_RX_TDM_TOT_CHAN_NUM_S  16
+/* I2S_RX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
+ Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_CHAN15_EN  (BIT(15))
+#define I2S_RX_TDM_CHAN15_EN_M  (BIT(15))
+#define I2S_RX_TDM_CHAN15_EN_V  0x1
+#define I2S_RX_TDM_CHAN15_EN_S  15
+/* I2S_RX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
+ Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_CHAN14_EN  (BIT(14))
+#define I2S_RX_TDM_CHAN14_EN_M  (BIT(14))
+#define I2S_RX_TDM_CHAN14_EN_V  0x1
+#define I2S_RX_TDM_CHAN14_EN_S  14
+/* I2S_RX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
+ Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_CHAN13_EN  (BIT(13))
+#define I2S_RX_TDM_CHAN13_EN_M  (BIT(13))
+#define I2S_RX_TDM_CHAN13_EN_V  0x1
+#define I2S_RX_TDM_CHAN13_EN_S  13
+/* I2S_RX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
+ Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_CHAN12_EN  (BIT(12))
+#define I2S_RX_TDM_CHAN12_EN_M  (BIT(12))
+#define I2S_RX_TDM_CHAN12_EN_V  0x1
+#define I2S_RX_TDM_CHAN12_EN_S  12
+/* I2S_RX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
+ Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_CHAN11_EN  (BIT(11))
+#define I2S_RX_TDM_CHAN11_EN_M  (BIT(11))
+#define I2S_RX_TDM_CHAN11_EN_V  0x1
+#define I2S_RX_TDM_CHAN11_EN_S  11
+/* I2S_RX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
+ Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_CHAN10_EN  (BIT(10))
+#define I2S_RX_TDM_CHAN10_EN_M  (BIT(10))
+#define I2S_RX_TDM_CHAN10_EN_V  0x1
+#define I2S_RX_TDM_CHAN10_EN_S  10
+/* I2S_RX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
+ Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_CHAN9_EN  (BIT(9))
+#define I2S_RX_TDM_CHAN9_EN_M  (BIT(9))
+#define I2S_RX_TDM_CHAN9_EN_V  0x1
+#define I2S_RX_TDM_CHAN9_EN_S  9
+/* I2S_RX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
+ Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_CHAN8_EN  (BIT(8))
+#define I2S_RX_TDM_CHAN8_EN_M  (BIT(8))
+#define I2S_RX_TDM_CHAN8_EN_V  0x1
+#define I2S_RX_TDM_CHAN8_EN_S  8
+/* I2S_RX_TDM_PDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
+ 0:  Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_PDM_CHAN7_EN  (BIT(7))
+#define I2S_RX_TDM_PDM_CHAN7_EN_M  (BIT(7))
+#define I2S_RX_TDM_PDM_CHAN7_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN7_EN_S  7
+/* I2S_RX_TDM_PDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
+ 0:  Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_PDM_CHAN6_EN  (BIT(6))
+#define I2S_RX_TDM_PDM_CHAN6_EN_M  (BIT(6))
+#define I2S_RX_TDM_PDM_CHAN6_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN6_EN_S  6
+/* I2S_RX_TDM_PDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
+ 0:  Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_PDM_CHAN5_EN  (BIT(5))
+#define I2S_RX_TDM_PDM_CHAN5_EN_M  (BIT(5))
+#define I2S_RX_TDM_PDM_CHAN5_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN5_EN_S  5
+/* I2S_RX_TDM_PDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
+ 0:  Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_PDM_CHAN4_EN  (BIT(4))
+#define I2S_RX_TDM_PDM_CHAN4_EN_M  (BIT(4))
+#define I2S_RX_TDM_PDM_CHAN4_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN4_EN_S  4
+/* I2S_RX_TDM_PDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
+ 0:  Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_PDM_CHAN3_EN  (BIT(3))
+#define I2S_RX_TDM_PDM_CHAN3_EN_M  (BIT(3))
+#define I2S_RX_TDM_PDM_CHAN3_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN3_EN_S  3
+/* I2S_RX_TDM_PDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
+ 0:  Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_PDM_CHAN2_EN  (BIT(2))
+#define I2S_RX_TDM_PDM_CHAN2_EN_M  (BIT(2))
+#define I2S_RX_TDM_PDM_CHAN2_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN2_EN_S  2
+/* I2S_RX_TDM_PDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
+ 0:  Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_PDM_CHAN1_EN  (BIT(1))
+#define I2S_RX_TDM_PDM_CHAN1_EN_M  (BIT(1))
+#define I2S_RX_TDM_PDM_CHAN1_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN1_EN_S  1
+/* I2S_RX_TDM_PDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
+ 0:  Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_PDM_CHAN0_EN  (BIT(0))
+#define I2S_RX_TDM_PDM_CHAN0_EN_M  (BIT(0))
+#define I2S_RX_TDM_PDM_CHAN0_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN0_EN_S  0
+
+#define I2S_TX_TDM_CTRL_REG(i)          (REG_I2S_BASE(i) + 0x0054)
+/* I2S_TX_TDM_SKIP_MSK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM
+ + 1)  channels  and only the data of the enabled channels is sent  then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/
+#define I2S_TX_TDM_SKIP_MSK_EN  (BIT(20))
+#define I2S_TX_TDM_SKIP_MSK_EN_M  (BIT(20))
+#define I2S_TX_TDM_SKIP_MSK_EN_V  0x1
+#define I2S_TX_TDM_SKIP_MSK_EN_S  20
+/* I2S_TX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */
+/*description: The total channel number minus 1 of I2S TX TDM mode.*/
+#define I2S_TX_TDM_TOT_CHAN_NUM  0x0000000F
+#define I2S_TX_TDM_TOT_CHAN_NUM_M  ((I2S_TX_TDM_TOT_CHAN_NUM_V)<<(I2S_TX_TDM_TOT_CHAN_NUM_S))
+#define I2S_TX_TDM_TOT_CHAN_NUM_V  0xF
+#define I2S_TX_TDM_TOT_CHAN_NUM_S  16
+/* I2S_TX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN15_EN  (BIT(15))
+#define I2S_TX_TDM_CHAN15_EN_M  (BIT(15))
+#define I2S_TX_TDM_CHAN15_EN_V  0x1
+#define I2S_TX_TDM_CHAN15_EN_S  15
+/* I2S_TX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN14_EN  (BIT(14))
+#define I2S_TX_TDM_CHAN14_EN_M  (BIT(14))
+#define I2S_TX_TDM_CHAN14_EN_V  0x1
+#define I2S_TX_TDM_CHAN14_EN_S  14
+/* I2S_TX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN13_EN  (BIT(13))
+#define I2S_TX_TDM_CHAN13_EN_M  (BIT(13))
+#define I2S_TX_TDM_CHAN13_EN_V  0x1
+#define I2S_TX_TDM_CHAN13_EN_S  13
+/* I2S_TX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN12_EN  (BIT(12))
+#define I2S_TX_TDM_CHAN12_EN_M  (BIT(12))
+#define I2S_TX_TDM_CHAN12_EN_V  0x1
+#define I2S_TX_TDM_CHAN12_EN_S  12
+/* I2S_TX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN11_EN  (BIT(11))
+#define I2S_TX_TDM_CHAN11_EN_M  (BIT(11))
+#define I2S_TX_TDM_CHAN11_EN_V  0x1
+#define I2S_TX_TDM_CHAN11_EN_S  11
+/* I2S_TX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN10_EN  (BIT(10))
+#define I2S_TX_TDM_CHAN10_EN_M  (BIT(10))
+#define I2S_TX_TDM_CHAN10_EN_V  0x1
+#define I2S_TX_TDM_CHAN10_EN_S  10
+/* I2S_TX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN9_EN  (BIT(9))
+#define I2S_TX_TDM_CHAN9_EN_M  (BIT(9))
+#define I2S_TX_TDM_CHAN9_EN_V  0x1
+#define I2S_TX_TDM_CHAN9_EN_S  9
+/* I2S_TX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN8_EN  (BIT(8))
+#define I2S_TX_TDM_CHAN8_EN_M  (BIT(8))
+#define I2S_TX_TDM_CHAN8_EN_V  0x1
+#define I2S_TX_TDM_CHAN8_EN_S  8
+/* I2S_TX_TDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN7_EN  (BIT(7))
+#define I2S_TX_TDM_CHAN7_EN_M  (BIT(7))
+#define I2S_TX_TDM_CHAN7_EN_V  0x1
+#define I2S_TX_TDM_CHAN7_EN_S  7
+/* I2S_TX_TDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN6_EN  (BIT(6))
+#define I2S_TX_TDM_CHAN6_EN_M  (BIT(6))
+#define I2S_TX_TDM_CHAN6_EN_V  0x1
+#define I2S_TX_TDM_CHAN6_EN_S  6
+/* I2S_TX_TDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN5_EN  (BIT(5))
+#define I2S_TX_TDM_CHAN5_EN_M  (BIT(5))
+#define I2S_TX_TDM_CHAN5_EN_V  0x1
+#define I2S_TX_TDM_CHAN5_EN_S  5
+/* I2S_TX_TDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN4_EN  (BIT(4))
+#define I2S_TX_TDM_CHAN4_EN_M  (BIT(4))
+#define I2S_TX_TDM_CHAN4_EN_V  0x1
+#define I2S_TX_TDM_CHAN4_EN_S  4
+/* I2S_TX_TDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN3_EN  (BIT(3))
+#define I2S_TX_TDM_CHAN3_EN_M  (BIT(3))
+#define I2S_TX_TDM_CHAN3_EN_V  0x1
+#define I2S_TX_TDM_CHAN3_EN_S  3
+/* I2S_TX_TDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN2_EN  (BIT(2))
+#define I2S_TX_TDM_CHAN2_EN_M  (BIT(2))
+#define I2S_TX_TDM_CHAN2_EN_V  0x1
+#define I2S_TX_TDM_CHAN2_EN_S  2
+/* I2S_TX_TDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN1_EN  (BIT(1))
+#define I2S_TX_TDM_CHAN1_EN_M  (BIT(1))
+#define I2S_TX_TDM_CHAN1_EN_V  0x1
+#define I2S_TX_TDM_CHAN1_EN_S  1
+/* I2S_TX_TDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN0_EN  (BIT(0))
+#define I2S_TX_TDM_CHAN0_EN_M  (BIT(0))
+#define I2S_TX_TDM_CHAN0_EN_V  0x1
+#define I2S_TX_TDM_CHAN0_EN_S  0
+
+#define I2S_RX_TIMING_REG(i)          (REG_I2S_BASE(i) + 0x0058)
+/* I2S_RX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_RX_BCK_IN_DM  0x00000003
+#define I2S_RX_BCK_IN_DM_M  ((I2S_RX_BCK_IN_DM_V)<<(I2S_RX_BCK_IN_DM_S))
+#define I2S_RX_BCK_IN_DM_V  0x3
+#define I2S_RX_BCK_IN_DM_S  28
+/* I2S_RX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_RX_WS_IN_DM  0x00000003
+#define I2S_RX_WS_IN_DM_M  ((I2S_RX_WS_IN_DM_V)<<(I2S_RX_WS_IN_DM_S))
+#define I2S_RX_WS_IN_DM_V  0x3
+#define I2S_RX_WS_IN_DM_S  24
+/* I2S_RX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_RX_BCK_OUT_DM  0x00000003
+#define I2S_RX_BCK_OUT_DM_M  ((I2S_RX_BCK_OUT_DM_V)<<(I2S_RX_BCK_OUT_DM_S))
+#define I2S_RX_BCK_OUT_DM_V  0x3
+#define I2S_RX_BCK_OUT_DM_S  20
+/* I2S_RX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_RX_WS_OUT_DM  0x00000003
+#define I2S_RX_WS_OUT_DM_M  ((I2S_RX_WS_OUT_DM_V)<<(I2S_RX_WS_OUT_DM_S))
+#define I2S_RX_WS_OUT_DM_V  0x3
+#define I2S_RX_WS_OUT_DM_S  16
+/* I2S_RX_SD_IN_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_RX_SD_IN_DM  0x00000003
+#define I2S_RX_SD_IN_DM_M  ((I2S_RX_SD_IN_DM_V)<<(I2S_RX_SD_IN_DM_S))
+#define I2S_RX_SD_IN_DM_V  0x3
+#define I2S_RX_SD_IN_DM_S  0
+
+#define I2S_TX_TIMING_REG(i)          (REG_I2S_BASE(i) + 0x005C)
+/* I2S_TX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Tx BCK input signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_TX_BCK_IN_DM  0x00000003
+#define I2S_TX_BCK_IN_DM_M  ((I2S_TX_BCK_IN_DM_V)<<(I2S_TX_BCK_IN_DM_S))
+#define I2S_TX_BCK_IN_DM_V  0x3
+#define I2S_TX_BCK_IN_DM_S  28
+/* I2S_TX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Tx WS input signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_TX_WS_IN_DM  0x00000003
+#define I2S_TX_WS_IN_DM_M  ((I2S_TX_WS_IN_DM_V)<<(I2S_TX_WS_IN_DM_S))
+#define I2S_TX_WS_IN_DM_V  0x3
+#define I2S_TX_WS_IN_DM_S  24
+/* I2S_TX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Tx BCK output signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_TX_BCK_OUT_DM  0x00000003
+#define I2S_TX_BCK_OUT_DM_M  ((I2S_TX_BCK_OUT_DM_V)<<(I2S_TX_BCK_OUT_DM_S))
+#define I2S_TX_BCK_OUT_DM_V  0x3
+#define I2S_TX_BCK_OUT_DM_S  20
+/* I2S_TX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Tx WS output signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_TX_WS_OUT_DM  0x00000003
+#define I2S_TX_WS_OUT_DM_M  ((I2S_TX_WS_OUT_DM_V)<<(I2S_TX_WS_OUT_DM_S))
+#define I2S_TX_WS_OUT_DM_V  0x3
+#define I2S_TX_WS_OUT_DM_S  16
+/* I2S_TX_SD1_OUT_DM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
+ delay by neg edge. 3: not used..*/
+#define I2S_TX_SD1_OUT_DM    0x00000003
+#define I2S_TX_SD1_OUT_DM_M  ((I2S_TX_SD1_OUT_DM_V)<<(I2S_TX_SD1_OUT_DM_S))
+#define I2S_TX_SD1_OUT_DM_V  0x3
+#define I2S_TX_SD1_OUT_DM_S  4
+/* I2S_TX_SD_OUT_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Tx SD output signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_TX_SD_OUT_DM  0x00000003
+#define I2S_TX_SD_OUT_DM_M  ((I2S_TX_SD_OUT_DM_V)<<(I2S_TX_SD_OUT_DM_S))
+#define I2S_TX_SD_OUT_DM_V  0x3
+#define I2S_TX_SD_OUT_DM_S  0
+
+#define I2S_LC_HUNG_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0060)
+/* I2S_LC_FIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: The enable bit for FIFO timeout*/
+#define I2S_LC_FIFO_TIMEOUT_ENA  (BIT(11))
+#define I2S_LC_FIFO_TIMEOUT_ENA_M  (BIT(11))
+#define I2S_LC_FIFO_TIMEOUT_ENA_V  0x1
+#define I2S_LC_FIFO_TIMEOUT_ENA_S  11
+/* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
+/*description: The bits are used to scale tick counter threshold. The tick counter
+ is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
+#define I2S_LC_FIFO_TIMEOUT_SHIFT  0x00000007
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_M  ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S))
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x7
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
+/* I2S_LC_FIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
+/*description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt
+ will be triggered when fifo hung counter is equal to this value*/
+#define I2S_LC_FIFO_TIMEOUT  0x000000FF
+#define I2S_LC_FIFO_TIMEOUT_M  ((I2S_LC_FIFO_TIMEOUT_V)<<(I2S_LC_FIFO_TIMEOUT_S))
+#define I2S_LC_FIFO_TIMEOUT_V  0xFF
+#define I2S_LC_FIFO_TIMEOUT_S  0
+
+#define I2S_RXEOF_NUM_REG(i)          (REG_I2S_BASE(i) + 0x0064)
+/* I2S_RX_EOF_NUM : R/W ;bitpos:[11:0] ;default: 12'h40 ; */
+/*description: the length of data to be received. It will trigger i2s_in_suc_eof_int.*/
+#define I2S_RX_EOF_NUM  0x00000FFF
+#define I2S_RX_EOF_NUM_M  ((I2S_RX_EOF_NUM_V)<<(I2S_RX_EOF_NUM_S))
+#define I2S_RX_EOF_NUM_V  0xFFF
+#define I2S_RX_EOF_NUM_S  0
+
+#define I2S_CONF_SIGLE_DATA_REG(i)          (REG_I2S_BASE(i) + 0x0068)
+/* I2S_SINGLE_DATA : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: the right channel or left channel put out constant value stored
+ in this register according to tx_chan_mod and reg_tx_msb_right*/
+#define I2S_SINGLE_DATA  0xFFFFFFFF
+#define I2S_SINGLE_DATA_M  ((I2S_SINGLE_DATA_V)<<(I2S_SINGLE_DATA_S))
+#define I2S_SINGLE_DATA_V  0xFFFFFFFF
+#define I2S_SINGLE_DATA_S  0
+
+#define I2S_STATE_REG(i)          (REG_I2S_BASE(i) + 0x006C)
+/* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */
+/*description: 1: i2s_tx is idle state. 0: i2s_tx is working.*/
+#define I2S_TX_IDLE  (BIT(0))
+#define I2S_TX_IDLE_M  (BIT(0))
+#define I2S_TX_IDLE_V  0x1
+#define I2S_TX_IDLE_S  0
+
+#define I2S_DATE_REG(i)          (REG_I2S_BASE(i) + 0x0080)
+/* I2S_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003230 ; */
+/*description: Version control register*/
+#define I2S_DATE  0x0FFFFFFF
+#define I2S_DATE_M  ((I2S_DATE_V)<<(I2S_DATE_S))
+#define I2S_DATE_V  0xFFFFFFF
+#define I2S_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_I2S_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/i2s_struct.h b/components/soc/esp32c3/include/soc/i2s_struct.h
new file mode 100644
index 0000000000..ab788041bf
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/i2s_struct.h
@@ -0,0 +1,336 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_I2S_STRUCT_H_
+#define _SOC_I2S_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    uint32_t reserved_0;
+    uint32_t reserved_4;
+    uint32_t reserved_8;
+    union {
+        struct {
+            uint32_t rx_done:         1;             /*The raw interrupt status bit  for the i2s_rx_done_int interrupt*/
+            uint32_t tx_done:         1;             /*The raw interrupt status bit  for the i2s_tx_done_int interrupt*/
+            uint32_t rx_hung:         1;             /*The raw interrupt status bit  for the i2s_rx_hung_int interrupt*/
+            uint32_t tx_hung:         1;             /*The raw interrupt status bit  for the i2s_tx_hung_int interrupt*/
+            uint32_t reserved4:      28;             /*Reserve*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t rx_done:        1;              /*The masked interrupt status bit  for the i2s_rx_done_int interrupt*/
+            uint32_t tx_done:        1;              /*The masked interrupt status bit  for the i2s_tx_done_int interrupt*/
+            uint32_t rx_hung:        1;              /*The masked interrupt status bit  for the i2s_rx_hung_int interrupt*/
+            uint32_t tx_hung:        1;              /*The masked interrupt status bit  for the i2s_tx_hung_int interrupt*/
+            uint32_t reserved4:     28;              /*Reserve*/
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t rx_done:         1;             /*The interrupt enable bit  for the i2s_rx_done_int interrupt*/
+            uint32_t tx_done:         1;             /*The interrupt enable bit  for the i2s_tx_done_int interrupt*/
+            uint32_t rx_hung:         1;             /*The interrupt enable bit  for the i2s_rx_hung_int interrupt*/
+            uint32_t tx_hung:         1;             /*The interrupt enable bit  for the i2s_tx_hung_int interrupt*/
+            uint32_t reserved4:      28;             /*Reserve*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t rx_done:         1;             /*Set this bit to clear the i2s_rx_done_int interrupt*/
+            uint32_t tx_done:         1;             /*Set this bit to clear the i2s_tx_done_int interrupt*/
+            uint32_t rx_hung:         1;             /*Set this bit to clear the i2s_rx_hung_int interrupt*/
+            uint32_t tx_hung:         1;             /*Set this bit to clear the i2s_tx_hung_int interrupt*/
+            uint32_t reserved4:      28;             /*Reserve*/
+        };
+        uint32_t val;
+    } int_clr;
+    uint32_t reserved_1c;
+    union {
+        struct {
+            uint32_t rx_reset:              1;       /*Set this bit to reset receiver*/
+            uint32_t rx_fifo_reset:         1;       /*Set this bit to reset Rx AFIFO*/
+            uint32_t rx_start:              1;       /*Set this bit to start receiving data*/
+            uint32_t rx_slave_mod:          1;       /*Set this bit to enable slave receiver mode*/
+            uint32_t reserved4:             1;       /*Reserved*/
+            uint32_t rx_mono:               1;       /*Set this bit to enable receiver  in mono mode*/
+            uint32_t reserved6:             1;
+            uint32_t rx_big_endian:         1;       /*I2S Rx byte endian  1: low addr value to high addr. 0: low addr with low addr value.*/
+            uint32_t rx_update:             1;       /*Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.*/
+            uint32_t rx_mono_fst_vld:       1;       /*1: The first channel data value is valid in I2S RX mono mode.   0: The second channel data value is valid in I2S RX mono mode.*/
+            uint32_t rx_pcm_conf:           2;       /*I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress  1 (ltoa) : A-Law compress  2 (utol) : u-Law decompress  3 (ltou) : u-Law compress. &*/
+            uint32_t rx_pcm_bypass:         1;       /*Set this bit to bypass Compress/Decompress module for received data.*/
+            uint32_t rx_stop_mode:          2;       /*0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/
+            uint32_t rx_left_align:         1;       /*1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/
+            uint32_t rx_24_fill_en:         1;       /*1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/
+            uint32_t rx_ws_idle_pol:        1;       /*0: WS should be 0 when receiving left channel data  and WS is 1in right channel.  1: WS should be 1 when receiving left channel data  and WS is 0in right channel.*/
+            uint32_t rx_bit_order:          1;       /*I2S Rx bit endian. 1:small endian  the LSB is received first. 0:big endian  the MSB is received first.*/
+            uint32_t rx_tdm_en:             1;       /*1: Enable I2S TDM Rx mode . 0: Disable.*/
+            uint32_t rx_pdm_en:             1;       /*1: Enable I2S PDM Rx mode . 0: Disable.*/
+            uint32_t reserved23:            11;       /*Reserve*/
+        };
+        uint32_t val;
+    } rx_conf;
+    union {
+        struct {
+            uint32_t tx_reset:        1;             /*Set this bit to reset transmitter*/
+            uint32_t tx_fifo_reset:   1;             /*Set this bit to reset Tx AFIFO*/
+            uint32_t tx_start:        1;             /*Set this bit to start transmitting data*/
+            uint32_t tx_slave_mod:    1;             /*Set this bit to enable slave transmitter mode*/
+            uint32_t reserved4:       1;             /*Reserved*/
+            uint32_t tx_mono:         1;             /*Set this bit to enable transmitter in mono mode*/
+            uint32_t tx_chan_equal:   1;             /*1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/
+            uint32_t tx_big_endian:   1;             /*I2S Tx byte endian  1: low addr value to high addr.  0: low addr with low addr value.*/
+            uint32_t tx_update:       1;             /*Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.*/
+            uint32_t tx_mono_fst_vld: 1;             /*1: The first channel data value is valid in I2S TX mono mode.   0: The second channel data value is valid in I2S TX mono mode.*/
+            uint32_t tx_pcm_conf:     2;             /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress  1 (ltoa) : A-Law compress  2 (utol) : u-Law decompress  3 (ltou) : u-Law compress. &*/
+            uint32_t tx_pcm_bypass:   1;             /*Set this bit to bypass  Compress/Decompress module for transmitted data.*/
+            uint32_t tx_stop_en:      1;             /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
+            uint32_t reserved14:      1;
+            uint32_t tx_left_align:   1;             /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/
+            uint32_t tx_24_fill_en:   1;             /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/
+            uint32_t tx_ws_idle_pol:  1;             /*0: WS should be 0 when sending left channel data  and WS is 1in right channel.  1: WS should be 1 when sending left channel data  and WS is 0in right channel.*/
+            uint32_t tx_bit_order:    1;             /*I2S Tx bit endian. 1:small endian  the LSB is sent first. 0:big endian  the MSB is sent first.*/
+            uint32_t tx_tdm_en:       1;             /*1: Enable I2S TDM Tx mode . 0: Disable.*/
+            uint32_t tx_pdm_en:       1;             /*1: Enable I2S PDM Tx mode . 0: Disable.*/
+            uint32_t reserved21:      3;             /*Reserved*/
+            uint32_t tx_chan_mod:     3;             /*I2S transmitter channel mode configuration bits.*/
+            uint32_t sig_loopback:    1;             /*Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.*/
+            uint32_t reserved28:      4;             /*Reserved*/
+        };
+        uint32_t val;
+    } tx_conf;
+    union {
+        struct {
+            uint32_t rx_tdm_ws_width:     7;         /*The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/
+            uint32_t rx_bck_div_num:      6;         /*Bit clock configuration bits in receiver mode.*/
+            uint32_t rx_bits_mod:         5;         /*Set the bits to configure bit length of I2S receiver channel.*/
+            uint32_t rx_half_sample_bits: 6;         /*I2S Rx half sample bits -1.*/
+            uint32_t rx_tdm_chan_bits:    5;         /*The Rx bit number for each channel minus 1in TDM mode.*/
+            uint32_t rx_msb_shift:        1;         /*Set this bit to enable receiver in Phillips standard mode*/
+            uint32_t reserved30:          2;         /*Reserved*/
+        };
+        uint32_t val;
+    } rx_conf1;
+    union {
+        struct {
+            uint32_t tx_tdm_ws_width:     7;         /*The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/
+            uint32_t tx_bck_div_num:      6;         /*Bit clock configuration bits in transmitter mode.*/
+            uint32_t tx_bits_mod:         5;         /*Set the bits to configure bit length of I2S transmitter channel.*/
+            uint32_t tx_half_sample_bits: 6;         /*I2S Tx half sample bits -1.*/
+            uint32_t tx_tdm_chan_bits:    5;         /*The Tx bit number for each channel minus 1in TDM mode.*/
+            uint32_t tx_msb_shift:        1;         /*Set this bit to enable transmitter in Phillips standard mode*/
+            uint32_t tx_bck_no_dly:       1;         /*1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.*/
+            uint32_t reserved31:          1;               /* Reserved*/
+        };
+        uint32_t val;
+    } tx_conf1;
+    union {
+        struct {
+            uint32_t rx_clkm_div_num: 8;             /*Integral I2S clock divider value*/
+            uint32_t reserved8:      18;             /*Reserved*/
+            uint32_t rx_clk_active:   1;             /*I2S Rx module clock enable signal.*/
+            uint32_t rx_clk_sel:      2;             /*Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
+            uint32_t mclk_sel:        1;             /*0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MCLK_OUT.*/
+            uint32_t reserved30:      2;             /*Reserved*/
+        };
+        uint32_t val;
+    } rx_clkm_conf;
+    union {
+        struct {
+            uint32_t tx_clkm_div_num: 8;             /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <= a/2  z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2  z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/
+            uint32_t reserved8:      18;             /*Reserved*/
+            uint32_t tx_clk_active:   1;             /*I2S Tx module clock enable signal.*/
+            uint32_t tx_clk_sel:      2;             /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
+            uint32_t clk_en:          1;             /*Set this bit to enable clk gate*/
+            uint32_t reserved30:      2;             /*Reserved*/
+        };
+        uint32_t val;
+    } tx_clkm_conf;
+    union {
+        struct {
+            uint32_t rx_clkm_div_z:   9;             /*For b <= a/2  the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2  the value of I2S_RX_CLKM_DIV_Z is (a-b).*/
+            uint32_t rx_clkm_div_y:   9;             /*For b <= a/2  the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2  the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/
+            uint32_t rx_clkm_div_x:   9;             /*For b <= a/2  the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2  the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/
+            uint32_t rx_clkm_div_yn1: 1;             /*For b <= a/2  the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2  the value of I2S_RX_CLKM_DIV_YN1 is 1.*/
+            uint32_t reserved28:      4;             /*Reserved*/
+        };
+        uint32_t val;
+    } rx_clkm_div_conf;
+    union {
+        struct {
+            uint32_t tx_clkm_div_z:   9;             /*For b <= a/2  the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2  the value of I2S_TX_CLKM_DIV_Z is (a-b).*/
+            uint32_t tx_clkm_div_y:   9;             /*For b <= a/2  the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2  the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/
+            uint32_t tx_clkm_div_x:   9;             /*For b <= a/2  the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2  the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/
+            uint32_t tx_clkm_div_yn1: 1;             /*For b <= a/2  the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2  the value of I2S_TX_CLKM_DIV_YN1 is 1.*/
+            uint32_t reserved28:      4;             /*Reserved*/
+        };
+        uint32_t val;
+    } tx_clkm_div_conf;
+    union {
+        struct {
+            uint32_t tx_pdm_hp_bypass              :    1;  /*I2S TX PDM bypass hp filter or not. The option has been removed.*/
+            uint32_t tx_pdm_sinc_osr2              :    4;  /*I2S TX PDM OSR2 value*/
+            uint32_t tx_pdm_prescale               :    8;  /*I2S TX PDM prescale for sigmadelta*/
+            uint32_t tx_pdm_hp_in_shift            :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
+            uint32_t tx_pdm_lp_in_shift            :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
+            uint32_t tx_pdm_sinc_in_shift          :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
+            uint32_t tx_pdm_sigmadelta_in_shift    :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
+            uint32_t tx_pdm_sigmadelta_dither2     :    1;  /*I2S TX PDM sigmadelta dither2 value*/
+            uint32_t tx_pdm_sigmadelta_dither      :    1;  /*I2S TX PDM sigmadelta dither value*/
+            uint32_t tx_pdm_dac_2out_en            :    1;  /*I2S TX PDM dac mode enable*/
+            uint32_t tx_pdm_dac_mode_en            :    1;  /*I2S TX PDM dac 2channel enable*/
+            uint32_t pcm2pdm_conv_en               :    1;  /*I2S TX PDM Converter enable*/
+            uint32_t reserved26                    :    6;  /*Reserved*/
+        };
+        uint32_t val;
+    } tx_pcm2pdm_conf;
+    union {
+        struct {
+            uint32_t tx_pdm_fp                     :    10;  /*I2S TX PDM Fp*/
+            uint32_t tx_pdm_fs                     :    10;  /*I2S TX PDM Fs*/
+            uint32_t tx_iir_hp_mult12_5            :    3;  /*The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])*/
+            uint32_t tx_iir_hp_mult12_0            :    3;  /*The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])*/
+            uint32_t reserved26                    :    6;  /*Reserved*/
+        };
+        uint32_t val;
+    } tx_pcm2pdm_conf1;
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    union {
+        struct {
+            uint32_t rx_tdm_pdm_chan0_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_pdm_chan1_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_pdm_chan2_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_pdm_chan3_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_pdm_chan4_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_pdm_chan5_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_pdm_chan6_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_pdm_chan7_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan8_en               :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan9_en               :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan10_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan11_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan12_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan13_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan14_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan15_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_tot_chan_num: 4;         /*The total channel number of I2S TX TDM mode.*/
+            uint32_t reserved20:         12;         /*Reserved*/
+        };
+        uint32_t val;
+    } rx_tdm_ctrl;
+    union {
+        struct {
+            uint32_t tx_tdm_chan0_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan1_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan2_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan3_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan4_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan5_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan6_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan7_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan8_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan9_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan10_en:    1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan11_en:    1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan12_en:    1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan13_en:    1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan14_en:    1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan15_en:    1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_tot_chan_num: 4;         /*The total channel number minus 1 of I2S TX TDM mode.*/
+            uint32_t tx_tdm_skip_msk_en:  1;         /*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels  and only the data of the enabled channels is sent  then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/
+            uint32_t reserved21:         11;         /*Reserved*/
+        };
+        uint32_t val;
+    } tx_tdm_ctrl;
+    union {
+        struct {
+            uint32_t rx_sd_in_dm:   2;               /*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved2                     :    14;  /* Reserved*/
+            uint32_t rx_ws_out_dm:  2;               /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved18:    2;
+            uint32_t rx_bck_out_dm: 2;               /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved22:    2;
+            uint32_t rx_ws_in_dm:   2;               /*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved26:    2;
+            uint32_t rx_bck_in_dm:  2;               /*The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved30:    2;
+        };
+        uint32_t val;
+    } rx_timing;
+    union {
+        struct {
+            uint32_t tx_sd_out_dm                  :    2;  /*The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved2                     :    2;  /* Reserved*/
+            uint32_t tx_sd1_out_dm                 :    2;  /*The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved6                     :    10;  /* Reserved*/
+            uint32_t tx_ws_out_dm                  :    2;  /*The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved18                    :    2;  /* Reserved*/
+            uint32_t tx_bck_out_dm                 :    2;  /*The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved22                    :    2;  /* Reserved*/
+            uint32_t tx_ws_in_dm                   :    2;  /*The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved26                    :    2;  /* Reserved*/
+            uint32_t tx_bck_in_dm                  :    2;  /*The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved30                    :    2;  /* Reserved*/
+        };
+        uint32_t val;
+    } tx_timing;
+    union {
+        struct {
+            uint32_t fifo_timeout:          8;       /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/
+            uint32_t fifo_timeout_shift:    3;       /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
+            uint32_t fifo_timeout_ena:      1;       /*The enable bit for FIFO timeout*/
+            uint32_t reserved12:           20;       /*Reserved*/
+        };
+        uint32_t val;
+    } lc_hung_conf;
+    union {
+        struct {
+            uint32_t rx_eof_num:12;                  /*the length of data to be received. It will trigger i2s_in_suc_eof_int.*/
+            uint32_t reserved12:20;                  /*Reserved*/
+        };
+        uint32_t val;
+    } rx_eof_num;
+    uint32_t conf_single_data;                     /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/
+    union {
+        struct {
+            uint32_t tx_idle:    1;                  /*1: i2s_tx is idle state. 0: i2s_tx is working.*/
+            uint32_t reserved1: 31;                  /*Reserved*/
+        };
+        uint32_t val;
+    } state;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    union {
+        struct {
+            uint32_t date:      28;                  /*Version control register*/
+            uint32_t reserved28: 4;                  /*Reserved*/
+        };
+        uint32_t val;
+    } date;
+} i2s_dev_t;
+extern i2s_dev_t I2S1;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_I2S_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/interrupt_core0_reg.h b/components/soc/esp32c3/include/soc/interrupt_core0_reg.h
new file mode 100644
index 0000000000..f606cdafca
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/interrupt_core0_reg.h
@@ -0,0 +1,856 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_INTERRUPT_CORE0_REG_H_
+#define _SOC_INTERRUPT_CORE0_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE
+
+#define INTERRUPT_CORE0_MAC_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x000)
+/* INTERRUPT_CORE0_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_MAC_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_MAC_INTR_MAP_M  ((INTERRUPT_CORE0_MAC_INTR_MAP_V)<<(INTERRUPT_CORE0_MAC_INTR_MAP_S))
+#define INTERRUPT_CORE0_MAC_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_MAC_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_MAC_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x004)
+/* INTERRUPT_CORE0_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_MAC_NMI_MAP  0x0000001F
+#define INTERRUPT_CORE0_MAC_NMI_MAP_M  ((INTERRUPT_CORE0_MAC_NMI_MAP_V)<<(INTERRUPT_CORE0_MAC_NMI_MAP_S))
+#define INTERRUPT_CORE0_MAC_NMI_MAP_V  0x1F
+#define INTERRUPT_CORE0_MAC_NMI_MAP_S  0
+
+#define INTERRUPT_CORE0_PWR_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x008)
+/* INTERRUPT_CORE0_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_PWR_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_PWR_INTR_MAP_M  ((INTERRUPT_CORE0_PWR_INTR_MAP_V)<<(INTERRUPT_CORE0_PWR_INTR_MAP_S))
+#define INTERRUPT_CORE0_PWR_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_PWR_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_BB_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x00C)
+/* INTERRUPT_CORE0_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_BB_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_BB_INT_MAP_M  ((INTERRUPT_CORE0_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BB_INT_MAP_S))
+#define INTERRUPT_CORE0_BB_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_BB_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x010)
+/* INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M  ((INTERRUPT_CORE0_BT_MAC_INT_MAP_V)<<(INTERRUPT_CORE0_BT_MAC_INT_MAP_S))
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x014)
+/* INTERRUPT_CORE0_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_BT_BB_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_BT_BB_INT_MAP_M  ((INTERRUPT_CORE0_BT_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BT_BB_INT_MAP_S))
+#define INTERRUPT_CORE0_BT_BB_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_BT_BB_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x018)
+/* INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP  0x0000001F
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M  ((INTERRUPT_CORE0_BT_BB_NMI_MAP_V)<<(INTERRUPT_CORE0_BT_BB_NMI_MAP_S))
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V  0x1F
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S  0
+
+#define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x01C)
+/* INTERRUPT_CORE0_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_RWBT_IRQ_MAP  0x0000001F
+#define INTERRUPT_CORE0_RWBT_IRQ_MAP_M  ((INTERRUPT_CORE0_RWBT_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBT_IRQ_MAP_S))
+#define INTERRUPT_CORE0_RWBT_IRQ_MAP_V  0x1F
+#define INTERRUPT_CORE0_RWBT_IRQ_MAP_S  0
+
+#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x020)
+/* INTERRUPT_CORE0_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_RWBLE_IRQ_MAP  0x0000001F
+#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_M  ((INTERRUPT_CORE0_RWBLE_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBLE_IRQ_MAP_S))
+#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_V  0x1F
+#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_S  0
+
+#define INTERRUPT_CORE0_RWBT_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x024)
+/* INTERRUPT_CORE0_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_RWBT_NMI_MAP  0x0000001F
+#define INTERRUPT_CORE0_RWBT_NMI_MAP_M  ((INTERRUPT_CORE0_RWBT_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBT_NMI_MAP_S))
+#define INTERRUPT_CORE0_RWBT_NMI_MAP_V  0x1F
+#define INTERRUPT_CORE0_RWBT_NMI_MAP_S  0
+
+#define INTERRUPT_CORE0_RWBLE_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x028)
+/* INTERRUPT_CORE0_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_RWBLE_NMI_MAP  0x0000001F
+#define INTERRUPT_CORE0_RWBLE_NMI_MAP_M  ((INTERRUPT_CORE0_RWBLE_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBLE_NMI_MAP_S))
+#define INTERRUPT_CORE0_RWBLE_NMI_MAP_V  0x1F
+#define INTERRUPT_CORE0_RWBLE_NMI_MAP_S  0
+
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x02C)
+/* INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M  ((INTERRUPT_CORE0_I2C_MST_INT_MAP_V)<<(INTERRUPT_CORE0_I2C_MST_INT_MAP_S))
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x030)
+/* INTERRUPT_CORE0_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_SLC0_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_SLC0_INTR_MAP_M  ((INTERRUPT_CORE0_SLC0_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC0_INTR_MAP_S))
+#define INTERRUPT_CORE0_SLC0_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_SLC0_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x034)
+/* INTERRUPT_CORE0_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_SLC1_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_SLC1_INTR_MAP_M  ((INTERRUPT_CORE0_SLC1_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC1_INTR_MAP_S))
+#define INTERRUPT_CORE0_SLC1_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_SLC1_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x038)
+/* INTERRUPT_CORE0_APB_CTRL_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_M  ((INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V)<<(INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S))
+#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x03C)
+/* INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M  ((INTERRUPT_CORE0_UHCI0_INTR_MAP_V)<<(INTERRUPT_CORE0_UHCI0_INTR_MAP_S))
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x040)
+/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP  0x0000001F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M  ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S))
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V  0x1F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S  0
+
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x044)
+/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP  0x0000001F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M  ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S))
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V  0x1F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S  0
+
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x048)
+/* INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP  0x0000001F
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M  ((INTERRUPT_CORE0_SPI_INTR_1_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_1_MAP_S))
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V  0x1F
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP_S  0
+
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x04C)
+/* INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP  0x0000001F
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M  ((INTERRUPT_CORE0_SPI_INTR_2_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_2_MAP_S))
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V  0x1F
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S  0
+
+#define INTERRUPT_CORE0_I2S1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x050)
+/* INTERRUPT_CORE0_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_I2S1_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_I2S1_INT_MAP_M  ((INTERRUPT_CORE0_I2S1_INT_MAP_V)<<(INTERRUPT_CORE0_I2S1_INT_MAP_S))
+#define INTERRUPT_CORE0_I2S1_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_I2S1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_UART_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x054)
+/* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_UART_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_UART_INTR_MAP_M  ((INTERRUPT_CORE0_UART_INTR_MAP_V)<<(INTERRUPT_CORE0_UART_INTR_MAP_S))
+#define INTERRUPT_CORE0_UART_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_UART_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_UART1_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x058)
+/* INTERRUPT_CORE0_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_UART1_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_UART1_INTR_MAP_M  ((INTERRUPT_CORE0_UART1_INTR_MAP_V)<<(INTERRUPT_CORE0_UART1_INTR_MAP_S))
+#define INTERRUPT_CORE0_UART1_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_UART1_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_LEDC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x05C)
+/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_LEDC_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_LEDC_INT_MAP_M  ((INTERRUPT_CORE0_LEDC_INT_MAP_V)<<(INTERRUPT_CORE0_LEDC_INT_MAP_S))
+#define INTERRUPT_CORE0_LEDC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_LEDC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x060)
+/* INTERRUPT_CORE0_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_EFUSE_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_EFUSE_INT_MAP_M  ((INTERRUPT_CORE0_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE0_EFUSE_INT_MAP_S))
+#define INTERRUPT_CORE0_EFUSE_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_EFUSE_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_CAN_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x064)
+/* INTERRUPT_CORE0_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CAN_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_CAN_INT_MAP_M  ((INTERRUPT_CORE0_CAN_INT_MAP_V)<<(INTERRUPT_CORE0_CAN_INT_MAP_S))
+#define INTERRUPT_CORE0_CAN_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_CAN_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_USB_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x068)
+/* INTERRUPT_CORE0_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_USB_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_USB_INTR_MAP_M  ((INTERRUPT_CORE0_USB_INTR_MAP_V)<<(INTERRUPT_CORE0_USB_INTR_MAP_S))
+#define INTERRUPT_CORE0_USB_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_USB_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x06C)
+/* INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M  ((INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V)<<(INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S))
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_RMT_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x070)
+/* INTERRUPT_CORE0_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_RMT_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_RMT_INTR_MAP_M  ((INTERRUPT_CORE0_RMT_INTR_MAP_V)<<(INTERRUPT_CORE0_RMT_INTR_MAP_S))
+#define INTERRUPT_CORE0_RMT_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_RMT_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x074)
+/* INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M  ((INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S))
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_TIMER_INT1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x078)
+/* INTERRUPT_CORE0_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_TIMER_INT1_MAP  0x0000001F
+#define INTERRUPT_CORE0_TIMER_INT1_MAP_M  ((INTERRUPT_CORE0_TIMER_INT1_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT1_MAP_S))
+#define INTERRUPT_CORE0_TIMER_INT1_MAP_V  0x1F
+#define INTERRUPT_CORE0_TIMER_INT1_MAP_S  0
+
+#define INTERRUPT_CORE0_TIMER_INT2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x07C)
+/* INTERRUPT_CORE0_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_TIMER_INT2_MAP  0x0000001F
+#define INTERRUPT_CORE0_TIMER_INT2_MAP_M  ((INTERRUPT_CORE0_TIMER_INT2_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT2_MAP_S))
+#define INTERRUPT_CORE0_TIMER_INT2_MAP_V  0x1F
+#define INTERRUPT_CORE0_TIMER_INT2_MAP_S  0
+
+#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x080)
+/* INTERRUPT_CORE0_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_TG_T0_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_TG_T0_INT_MAP_M  ((INTERRUPT_CORE0_TG_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T0_INT_MAP_S))
+#define INTERRUPT_CORE0_TG_T0_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_TG_T0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x084)
+/* INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M  ((INTERRUPT_CORE0_TG_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG_WDT_INT_MAP_S))
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TG1_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x088)
+/* INTERRUPT_CORE0_TG1_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_TG1_T0_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_TG1_T0_INT_MAP_M  ((INTERRUPT_CORE0_TG1_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_T0_INT_MAP_S))
+#define INTERRUPT_CORE0_TG1_T0_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_TG1_T0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x08C)
+/* INTERRUPT_CORE0_TG1_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_TG1_WDT_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_M  ((INTERRUPT_CORE0_TG1_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_WDT_INT_MAP_S))
+#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x090)
+/* INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M  ((INTERRUPT_CORE0_CACHE_IA_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_IA_INT_MAP_S))
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x094)
+/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S))
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x098)
+/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S))
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x09C)
+/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S))
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0A0)
+/* INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M  ((INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V)<<(INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S))
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0A4)
+/* INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M  ((INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S))
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0A8)
+/* INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M  ((INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S))
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0AC)
+/* INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M  ((INTERRUPT_CORE0_APB_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_APB_ADC_INT_MAP_S))
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0B0)
+/* INTERRUPT_CORE0_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_CH0_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_M  ((INTERRUPT_CORE0_DMA_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH0_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0B4)
+/* INTERRUPT_CORE0_DMA_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_CH1_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_M  ((INTERRUPT_CORE0_DMA_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH1_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0B8)
+/* INTERRUPT_CORE0_DMA_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_CH2_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_M  ((INTERRUPT_CORE0_DMA_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH2_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_RSA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0BC)
+/* INTERRUPT_CORE0_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_RSA_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_RSA_INT_MAP_M  ((INTERRUPT_CORE0_RSA_INT_MAP_V)<<(INTERRUPT_CORE0_RSA_INT_MAP_S))
+#define INTERRUPT_CORE0_RSA_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_RSA_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_AES_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0C0)
+/* INTERRUPT_CORE0_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_AES_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_AES_INT_MAP_M  ((INTERRUPT_CORE0_AES_INT_MAP_V)<<(INTERRUPT_CORE0_AES_INT_MAP_S))
+#define INTERRUPT_CORE0_AES_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_AES_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SHA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0C4)
+/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_SHA_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_SHA_INT_MAP_M  ((INTERRUPT_CORE0_SHA_INT_MAP_V)<<(INTERRUPT_CORE0_SHA_INT_MAP_S))
+#define INTERRUPT_CORE0_SHA_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SHA_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0C8)
+/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP  0x0000001F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S))
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V  0x1F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0CC)
+/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP  0x0000001F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S))
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V  0x1F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0D0)
+/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP  0x0000001F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S))
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V  0x1F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0D4)
+/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP  0x0000001F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S))
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V  0x1F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S  0
+
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0D8)
+/* INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M  ((INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V)<<(INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S))
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0DC)
+/* INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S))
+#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0E0)
+/* INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
+#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0E4)
+/* INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
+#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0E8)
+/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S))
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0EC)
+/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0F0)
+/* INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S))
+#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0F4)
+/* INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M  ((INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S))
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_INTR_STATUS_0_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0F8)
+/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define INTERRUPT_CORE0_INTR_STATUS_0  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_0_M  ((INTERRUPT_CORE0_INTR_STATUS_0_V)<<(INTERRUPT_CORE0_INTR_STATUS_0_S))
+#define INTERRUPT_CORE0_INTR_STATUS_0_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_0_S  0
+
+#define INTERRUPT_CORE0_INTR_STATUS_1_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0FC)
+/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define INTERRUPT_CORE0_INTR_STATUS_1  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_1_M  ((INTERRUPT_CORE0_INTR_STATUS_1_V)<<(INTERRUPT_CORE0_INTR_STATUS_1_S))
+#define INTERRUPT_CORE0_INTR_STATUS_1_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_1_S  0
+
+#define INTERRUPT_CORE0_CLOCK_GATE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
+/* INTERRUPT_CORE0_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define INTERRUPT_CORE0_CLK_EN  (BIT(0))
+#define INTERRUPT_CORE0_CLK_EN_M  (BIT(0))
+#define INTERRUPT_CORE0_CLK_EN_V  0x1
+#define INTERRUPT_CORE0_CLK_EN_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
+/* INTERRUPT_CORE0_CPU_INT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INT_ENABLE  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_ENABLE_M  ((INTERRUPT_CORE0_CPU_INT_ENABLE_V)<<(INTERRUPT_CORE0_CPU_INT_ENABLE_S))
+#define INTERRUPT_CORE0_CPU_INT_ENABLE_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_ENABLE_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_TYPE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
+/* INTERRUPT_CORE0_CPU_INT_TYPE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INT_TYPE  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_TYPE_M  ((INTERRUPT_CORE0_CPU_INT_TYPE_V)<<(INTERRUPT_CORE0_CPU_INT_TYPE_S))
+#define INTERRUPT_CORE0_CPU_INT_TYPE_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_TYPE_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x10C)
+/* INTERRUPT_CORE0_CPU_INT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INT_CLEAR  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_CLEAR_M  ((INTERRUPT_CORE0_CPU_INT_CLEAR_V)<<(INTERRUPT_CORE0_CPU_INT_CLEAR_S))
+#define INTERRUPT_CORE0_CPU_INT_CLEAR_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_CLEAR_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
+/* INTERRUPT_CORE0_CPU_INT_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_M  ((INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V)<<(INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S))
+#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_0_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
+/* INTERRUPT_CORE0_CPU_PRI_0_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_0_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_0_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_0_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_0_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_0_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_0_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_1_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
+/* INTERRUPT_CORE0_CPU_PRI_1_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_1_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_1_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_1_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_1_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_1_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_1_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_2_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x11C)
+/* INTERRUPT_CORE0_CPU_PRI_2_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_2_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_2_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_2_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_2_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_2_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_2_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_3_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
+/* INTERRUPT_CORE0_CPU_PRI_3_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_3_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_3_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_3_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_3_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_3_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_3_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_4_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
+/* INTERRUPT_CORE0_CPU_PRI_4_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_4_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_4_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_4_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_4_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_4_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_4_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_5_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
+/* INTERRUPT_CORE0_CPU_PRI_5_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_5_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_5_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_5_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_5_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_5_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_5_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_6_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x12C)
+/* INTERRUPT_CORE0_CPU_PRI_6_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_6_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_6_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_6_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_6_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_6_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_6_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_7_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
+/* INTERRUPT_CORE0_CPU_PRI_7_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_7_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_7_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_7_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_7_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_7_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_7_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_8_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
+/* INTERRUPT_CORE0_CPU_PRI_8_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_8_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_8_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_8_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_8_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_8_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_8_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_9_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
+/* INTERRUPT_CORE0_CPU_PRI_9_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_9_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_9_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_9_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_9_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_9_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_9_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_10_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x13C)
+/* INTERRUPT_CORE0_CPU_PRI_10_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_10_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_10_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_10_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_10_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_10_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_10_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_11_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
+/* INTERRUPT_CORE0_CPU_PRI_11_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_11_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_11_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_11_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_11_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_11_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_11_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_12_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
+/* INTERRUPT_CORE0_CPU_PRI_12_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_12_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_12_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_12_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_12_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_12_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_12_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_13_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
+/* INTERRUPT_CORE0_CPU_PRI_13_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_13_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_13_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_13_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_13_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_13_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_13_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_14_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x14C)
+/* INTERRUPT_CORE0_CPU_PRI_14_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_14_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_14_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_14_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_14_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_14_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_14_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_15_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
+/* INTERRUPT_CORE0_CPU_PRI_15_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_15_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_15_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_15_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_15_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_15_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_15_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_16_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
+/* INTERRUPT_CORE0_CPU_PRI_16_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_16_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_16_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_16_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_16_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_16_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_16_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_17_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
+/* INTERRUPT_CORE0_CPU_PRI_17_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_17_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_17_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_17_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_17_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_17_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_17_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_18_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x15C)
+/* INTERRUPT_CORE0_CPU_PRI_18_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_18_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_18_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_18_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_18_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_18_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_18_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_19_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
+/* INTERRUPT_CORE0_CPU_PRI_19_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_19_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_19_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_19_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_19_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_19_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_19_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_20_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
+/* INTERRUPT_CORE0_CPU_PRI_20_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_20_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_20_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_20_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_20_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_20_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_20_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_21_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
+/* INTERRUPT_CORE0_CPU_PRI_21_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_21_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_21_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_21_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_21_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_21_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_21_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_22_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x16C)
+/* INTERRUPT_CORE0_CPU_PRI_22_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_22_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_22_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_22_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_22_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_22_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_22_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_23_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
+/* INTERRUPT_CORE0_CPU_PRI_23_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_23_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_23_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_23_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_23_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_23_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_23_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_24_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
+/* INTERRUPT_CORE0_CPU_PRI_24_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_24_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_24_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_24_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_24_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_24_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_24_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_25_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x178)
+/* INTERRUPT_CORE0_CPU_PRI_25_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_25_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_25_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_25_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_25_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_25_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_25_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_26_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x17C)
+/* INTERRUPT_CORE0_CPU_PRI_26_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_26_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_26_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_26_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_26_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_26_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_26_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_27_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x180)
+/* INTERRUPT_CORE0_CPU_PRI_27_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_27_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_27_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_27_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_27_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_27_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_27_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_28_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x184)
+/* INTERRUPT_CORE0_CPU_PRI_28_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_28_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_28_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_28_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_28_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_28_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_28_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_29_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x188)
+/* INTERRUPT_CORE0_CPU_PRI_29_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_29_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_29_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_29_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_29_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_29_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_29_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_30_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x18C)
+/* INTERRUPT_CORE0_CPU_PRI_30_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_30_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_30_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_30_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_30_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_30_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_30_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_31_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x190)
+/* INTERRUPT_CORE0_CPU_PRI_31_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_31_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_31_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_31_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_31_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_31_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_31_MAP_S  0
+#define INTC_INT_PRIO_REG(n)                        (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4)
+
+#define INTERRUPT_CORE0_CPU_INT_THRESH_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x194)
+/* INTERRUPT_CORE0_CPU_INT_THRESH : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INT_THRESH  0x0000000F
+#define INTERRUPT_CORE0_CPU_INT_THRESH_M  ((INTERRUPT_CORE0_CPU_INT_THRESH_V)<<(INTERRUPT_CORE0_CPU_INT_THRESH_S))
+#define INTERRUPT_CORE0_CPU_INT_THRESH_V  0xF
+#define INTERRUPT_CORE0_CPU_INT_THRESH_S  0
+
+#define INTERRUPT_CORE0_INTERRUPT_DATE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC)
+/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007210 ; */
+/*description: */
+#define INTERRUPT_CORE0_INTERRUPT_DATE  0x0FFFFFFF
+#define INTERRUPT_CORE0_INTERRUPT_DATE_M  ((INTERRUPT_CORE0_INTERRUPT_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_DATE_S))
+#define INTERRUPT_CORE0_INTERRUPT_DATE_V  0xFFFFFFF
+#define INTERRUPT_CORE0_INTERRUPT_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/interrupt_reg.h b/components/soc/esp32c3/include/soc/interrupt_reg.h
new file mode 100644
index 0000000000..9d41c72a75
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/interrupt_reg.h
@@ -0,0 +1 @@
+#include "interrupt_core0_reg.h"
diff --git a/components/soc/esp32c3/include/soc/io_mux_reg.h b/components/soc/esp32c3/include/soc/io_mux_reg.h
new file mode 100644
index 0000000000..0ba14b6609
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/io_mux_reg.h
@@ -0,0 +1,262 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_IO_MUX_REG_H_
+#define _SOC_IO_MUX_REG_H_
+
+#include "soc.h"
+
+/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
+/* Output enable in sleep mode */
+#define SLP_OE (BIT(0))
+#define SLP_OE_M (BIT(0))
+#define SLP_OE_V 1
+#define SLP_OE_S 0
+/* Pin used for wakeup from sleep */
+#define SLP_SEL (BIT(1))
+#define SLP_SEL_M (BIT(1))
+#define SLP_SEL_V 1
+#define SLP_SEL_S 1
+/* Pulldown enable in sleep mode */
+#define SLP_PD (BIT(2))
+#define SLP_PD_M (BIT(2))
+#define SLP_PD_V 1
+#define SLP_PD_S 2
+/* Pullup enable in sleep mode */
+#define SLP_PU (BIT(3))
+#define SLP_PU_M (BIT(3))
+#define SLP_PU_V 1
+#define SLP_PU_S 3
+/* Input enable in sleep mode */
+#define SLP_IE (BIT(4))
+#define SLP_IE_M (BIT(4))
+#define SLP_IE_V 1
+#define SLP_IE_S 4
+/* Drive strength in sleep mode */
+#define SLP_DRV 0x3
+#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
+#define SLP_DRV_V 0x3
+#define SLP_DRV_S 5
+/* Pulldown enable */
+#define FUN_PD (BIT(7))
+#define FUN_PD_M (BIT(7))
+#define FUN_PD_V 1
+#define FUN_PD_S 7
+/* Pullup enable */
+#define FUN_PU (BIT(8))
+#define FUN_PU_M (BIT(8))
+#define FUN_PU_V 1
+#define FUN_PU_S 8
+/* Input enable */
+#define FUN_IE (BIT(9))
+#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
+#define FUN_IE_V 1
+#define FUN_IE_S 9
+/* Drive strength */
+#define FUN_DRV 0x3
+#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
+#define FUN_DRV_V 0x3
+#define FUN_DRV_S 10
+/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
+#define MCU_SEL 0x7
+#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
+#define MCU_SEL_V 0x7
+#define MCU_SEL_S 12
+
+#define PIN_INPUT_ENABLE(PIN_NAME)               SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_INPUT_DISABLE(PIN_NAME)              CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_SET_DRV(PIN_NAME, drv)            REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
+#define PIN_PULLUP_DIS(PIN_NAME)                 REG_CLR_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLUP_EN(PIN_NAME)                  REG_SET_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLDWN_DIS(PIN_NAME)             REG_CLR_BIT(PIN_NAME, FUN_PD)
+#define PIN_PULLDWN_EN(PIN_NAME)              REG_SET_BIT(PIN_NAME, FUN_PD)
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC)      REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+
+#define IO_MUX_GPIO0_REG		PERIPHS_IO_MUX_XTAL_32K_P_U
+#define IO_MUX_GPIO1_REG		PERIPHS_IO_MUX_XTAL_32K_N_U
+#define IO_MUX_GPIO2_REG		PERIPHS_IO_MUX_GPIO2_U
+#define IO_MUX_GPIO3_REG		PERIPHS_IO_MUX_GPIO3_U
+#define IO_MUX_GPIO4_REG		PERIPHS_IO_MUX_MTMS_U
+#define IO_MUX_GPIO5_REG		PERIPHS_IO_MUX_MTDI_U
+#define IO_MUX_GPIO6_REG		PERIPHS_IO_MUX_MTCK_U
+#define IO_MUX_GPIO7_REG		PERIPHS_IO_MUX_MTDO_U
+#define IO_MUX_GPIO8_REG		PERIPHS_IO_MUX_GPIO8_U
+#define IO_MUX_GPIO9_REG		PERIPHS_IO_MUX_GPIO9_U
+#define IO_MUX_GPIO10_REG	PERIPHS_IO_MUX_GPIO10_U
+#define IO_MUX_GPIO11_REG	PERIPHS_IO_MUX_VDD_SPI_U
+#define IO_MUX_GPIO12_REG	PERIPHS_IO_MUX_SPIHD_U
+#define IO_MUX_GPIO13_REG	PERIPHS_IO_MUX_SPIWP_U
+#define IO_MUX_GPIO14_REG	PERIPHS_IO_MUX_SPICS0_U
+#define IO_MUX_GPIO15_REG	PERIPHS_IO_MUX_SPICLK_U
+#define IO_MUX_GPIO16_REG	PERIPHS_IO_MUX_SPID_U
+#define IO_MUX_GPIO17_REG	PERIPHS_IO_MUX_SPIQ_U
+#define IO_MUX_GPIO18_REG	PERIPHS_IO_MUX_GPIO18_U
+#define IO_MUX_GPIO19_REG	PERIPHS_IO_MUX_GPIO19_U
+#define IO_MUX_GPIO20_REG	PERIPHS_IO_MUX_U0RXD_U
+#define IO_MUX_GPIO21_REG	PERIPHS_IO_MUX_U0TXD_U
+
+#define FUNC_GPIO_GPIO                              1
+#define PIN_FUNC_GPIO								1
+
+#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
+
+#define U0RXD_GPIO_NUM 20
+#define U0TXD_GPIO_NUM 21
+
+#define SPI_HD_GPIO_NUM  12
+#define SPI_WP_GPIO_NUM  13
+#define SPI_CS0_GPIO_NUM 14
+#define SPI_CLK_GPIO_NUM 15
+#define SPI_D_GPIO_NUM   16
+#define SPI_Q_GPIO_NUM   17
+
+#define SD_CLK_GPIO_NUM 12
+#define SD_CMD_GPIO_NUM 11
+#define SD_DATA0_GPIO_NUM 13
+#define SD_DATA1_GPIO_NUM 14
+#define SD_DATA2_GPIO_NUM 9
+#define SD_DATA3_GPIO_NUM 10
+
+#define MAX_RTC_GPIO_NUM 0
+#define MAX_PAD_GPIO_NUM 22
+#define MAX_GPIO_NUM    22
+
+#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
+#define PIN_CTRL                          (REG_IO_MUX_BASE +0x00)
+#define PAD_POWER_SEL                               BIT(15)
+#define PAD_POWER_SEL_V                             0x1
+#define PAD_POWER_SEL_M                             BIT(15)
+#define PAD_POWER_SEL_S                             15
+
+
+#define PAD_POWER_SWITCH_DELAY                      0x7
+#define PAD_POWER_SWITCH_DELAY_V                    0x7
+#define PAD_POWER_SWITCH_DELAY_M                    (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
+#define PAD_POWER_SWITCH_DELAY_S                    12
+
+
+#define CLK_OUT3                                    0xf
+#define CLK_OUT3_V                                  CLK_OUT3
+#define CLK_OUT3_S                                  8
+#define CLK_OUT3_M                                  (CLK_OUT3_V << CLK_OUT3_S)
+#define CLK_OUT2                                    0xf
+#define CLK_OUT2_V                                  CLK_OUT2
+#define CLK_OUT2_S                                  4
+#define CLK_OUT2_M                                  (CLK_OUT2_V << CLK_OUT2_S)
+#define CLK_OUT1                                    0xf
+#define CLK_OUT1_V                                  CLK_OUT1
+#define CLK_OUT1_S                                  0
+#define CLK_OUT1_M                                  (CLK_OUT1_V << CLK_OUT1_S)
+
+#define PERIPHS_IO_MUX_XTAL_32K_P_U       (REG_IO_MUX_BASE +0x04)
+#define FUNC_XTAL_32K_P_GPIO0                       1
+#define FUNC_XTAL_32K_P_GPIO0_0                     0
+
+#define PERIPHS_IO_MUX_XTAL_32K_N_U       (REG_IO_MUX_BASE +0x08)
+#define FUNC_XTAL_32K_N_GPIO1                       1
+#define FUNC_XTAL_32K_N_GPIO1_0                     0
+
+#define PERIPHS_IO_MUX_GPIO2_U            (REG_IO_MUX_BASE +0x0c)
+#define FUNC_GPIO2_FSPIQ                            2
+#define FUNC_GPIO2_GPIO2                            1
+#define FUNC_GPIO2_GPIO2_0                          0
+
+#define PERIPHS_IO_MUX_GPIO3_U            (REG_IO_MUX_BASE +0x10)
+#define FUNC_GPIO3_GPIO3                            1
+#define FUNC_GPIO3_GPIO3_0                          0
+
+#define PERIPHS_IO_MUX_MTMS_U             (REG_IO_MUX_BASE +0x14)
+#define FUNC_MTMS_FSPIHD                            2
+#define FUNC_MTMS_GPIO4                             1
+#define FUNC_MTMS_MTMS                              0
+
+#define PERIPHS_IO_MUX_MTDI_U             (REG_IO_MUX_BASE +0x18)
+#define FUNC_MTDI_FSPIWP                            2
+#define FUNC_MTDI_GPIO5                             1
+#define FUNC_MTDI_MTDI                              0
+
+#define PERIPHS_IO_MUX_MTCK_U             (REG_IO_MUX_BASE +0x1c)
+#define FUNC_MTCK_FSPICLK                           2
+#define FUNC_MTCK_GPIO6                             1
+#define FUNC_MTCK_MTCK                              0
+
+#define PERIPHS_IO_MUX_MTDO_U             (REG_IO_MUX_BASE +0x20)
+#define FUNC_MTDO_FSPID                             2
+#define FUNC_MTDO_GPIO7                             1
+#define FUNC_MTDO_MTDO                              0
+
+#define PERIPHS_IO_MUX_GPIO8_U            (REG_IO_MUX_BASE +0x24)
+#define FUNC_GPIO8_GPIO8                            1
+#define FUNC_GPIO8_GPIO8_0                          0
+
+#define PERIPHS_IO_MUX_GPIO9_U            (REG_IO_MUX_BASE +0x28)
+#define FUNC_GPIO9_GPIO9                            1
+#define FUNC_GPIO9_GPIO9_0                          0
+
+#define PERIPHS_IO_MUX_GPIO10_U           (REG_IO_MUX_BASE +0x2c)
+#define FUNC_GPIO10_FSPICS0                         2
+#define FUNC_GPIO10_GPIO10                          1
+#define FUNC_GPIO10_GPIO10_0                        0
+
+#define PERIPHS_IO_MUX_VDD_SPI_U          (REG_IO_MUX_BASE +0x30)
+#define FUNC_VDD_SPI_GPIO11                         1
+#define FUNC_VDD_SPI_GPIO11_0                       0
+
+#define PERIPHS_IO_MUX_SPIHD_U            (REG_IO_MUX_BASE +0x34)
+#define FUNC_SPIHD_GPIO12                           1
+#define FUNC_SPIHD_SPIHD                            0
+
+#define PERIPHS_IO_MUX_SPIWP_U            (REG_IO_MUX_BASE +0x38)
+#define FUNC_SPIWP_GPIO13                           1
+#define FUNC_SPIWP_SPIWP                            0
+
+#define PERIPHS_IO_MUX_SPICS0_U           (REG_IO_MUX_BASE +0x3c)
+#define FUNC_SPICS0_GPIO14                          1
+#define FUNC_SPICS0_SPICS0                          0
+
+#define PERIPHS_IO_MUX_SPICLK_U           (REG_IO_MUX_BASE +0x40)
+#define FUNC_SPICLK_GPIO15                          1
+#define FUNC_SPICLK_SPICLK                          0
+
+#define PERIPHS_IO_MUX_SPID_U             (REG_IO_MUX_BASE +0x44)
+#define FUNC_SPID_GPIO16                            1
+#define FUNC_SPID_SPID                              0
+
+#define PERIPHS_IO_MUX_SPIQ_U             (REG_IO_MUX_BASE +0x48)
+#define FUNC_SPIQ_GPIO17                            1
+#define FUNC_SPIQ_SPIQ                              0
+
+#define PERIPHS_IO_MUX_GPIO18_U           (REG_IO_MUX_BASE +0x4c)
+#define FUNC_GPIO18_GPIO18                          1
+#define FUNC_GPIO18_GPIO18_0                        0
+
+#define PERIPHS_IO_MUX_GPIO19_U           (REG_IO_MUX_BASE +0x50)
+#define FUNC_GPIO19_GPIO19                          1
+#define FUNC_GPIO19_GPIO19_0                        0
+
+#define PERIPHS_IO_MUX_U0RXD_U            (REG_IO_MUX_BASE +0x54)
+#define FUNC_U0RXD_GPIO20                           1
+#define FUNC_U0RXD_U0RXD                            0
+
+#define PERIPHS_IO_MUX_U0TXD_U            (REG_IO_MUX_BASE +0x58)
+#define FUNC_U0TXD_GPIO21                           1
+#define FUNC_U0TXD_U0TXD                            0
+
+#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
+#define IO_MUX_DATE 0xFFFFFFFF
+#define IO_MUX_DATE_S 0
+#define IO_MUX_DATE_VERSION 0x2006050
+
+#endif
diff --git a/components/soc/esp32c3/include/soc/ledc_caps.h b/components/soc/esp32c3/include/soc/ledc_caps.h
new file mode 100644
index 0000000000..7a003f6419
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/ledc_caps.h
@@ -0,0 +1,26 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SOC_LEDC_SUPPORT_XTAL_CLOCK  (1)
+#define SOC_LEDC_CHANNEL_NUM         (6)
+#define SOC_LEDC_TIMER_BIT_WIDE_NUM  (14)
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/include/soc/ledc_reg.h b/components/soc/esp32c3/include/soc/ledc_reg.h
new file mode 100644
index 0000000000..0cc9334130
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/ledc_reg.h
@@ -0,0 +1,1226 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_LEDC_REG_H_
+#define _SOC_LEDC_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define LEDC_LSCH0_CONF0_REG          (DR_REG_LEDC_BASE + 0x0000)
+/* LEDC_OVF_CNT_RESET_LSCH0 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH0  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH0_M  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH0_V  0x1
+#define LEDC_OVF_CNT_RESET_LSCH0_S  16
+/* LEDC_OVF_CNT_EN_LSCH0 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH0  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH0_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH0_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH0_S  15
+/* LEDC_OVF_NUM_LSCH0 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH0  0x000003FF
+#define LEDC_OVF_NUM_LSCH0_M  ((LEDC_OVF_NUM_LSCH0_V)<<(LEDC_OVF_NUM_LSCH0_S))
+#define LEDC_OVF_NUM_LSCH0_V  0x3FF
+#define LEDC_OVF_NUM_LSCH0_S  5
+/* LEDC_PARA_UP_LSCH0 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH0  (BIT(4))
+#define LEDC_PARA_UP_LSCH0_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH0_V  0x1
+#define LEDC_PARA_UP_LSCH0_S  4
+/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH0  (BIT(3))
+#define LEDC_IDLE_LV_LSCH0_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH0_V  0x1
+#define LEDC_IDLE_LV_LSCH0_S  3
+/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH0  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH0_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH0_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH0_S  2
+/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH0  0x00000003
+#define LEDC_TIMER_SEL_LSCH0_M  ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S))
+#define LEDC_TIMER_SEL_LSCH0_V  0x3
+#define LEDC_TIMER_SEL_LSCH0_S  0
+
+#define LEDC_LSCH0_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0004)
+/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH0  0x00003FFF
+#define LEDC_HPOINT_LSCH0_M  ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S))
+#define LEDC_HPOINT_LSCH0_V  0x3FFF
+#define LEDC_HPOINT_LSCH0_S  0
+
+#define LEDC_LSCH0_DUTY_REG          (DR_REG_LEDC_BASE + 0x0008)
+/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH0  0x0007FFFF
+#define LEDC_DUTY_LSCH0_M  ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))
+#define LEDC_DUTY_LSCH0_V  0x7FFFF
+#define LEDC_DUTY_LSCH0_S  0
+
+#define LEDC_LSCH0_CONF1_REG          (DR_REG_LEDC_BASE + 0x000C)
+/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH0  (BIT(31))
+#define LEDC_DUTY_START_LSCH0_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH0_V  0x1
+#define LEDC_DUTY_START_LSCH0_S  31
+/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH0  (BIT(30))
+#define LEDC_DUTY_INC_LSCH0_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH0_V  0x1
+#define LEDC_DUTY_INC_LSCH0_S  30
+/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH0  0x000003FF
+#define LEDC_DUTY_NUM_LSCH0_M  ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S))
+#define LEDC_DUTY_NUM_LSCH0_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH0_S  20
+/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH0  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH0_M  ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S))
+#define LEDC_DUTY_CYCLE_LSCH0_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH0_S  10
+/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH0  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH0_M  ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S))
+#define LEDC_DUTY_SCALE_LSCH0_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH0_S  0
+
+#define LEDC_LSCH0_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0010)
+/* LEDC_DUTY_LSCH0 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH0  0x0007FFFF
+#define LEDC_DUTY_LSCH0_M  ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))
+#define LEDC_DUTY_LSCH0_V  0x7FFFF
+#define LEDC_DUTY_LSCH0_S  0
+
+#define LEDC_LSCH1_CONF0_REG          (DR_REG_LEDC_BASE + 0x0014)
+/* LEDC_OVF_CNT_RESET_LSCH1 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH1  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH1_M  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH1_V  0x1
+#define LEDC_OVF_CNT_RESET_LSCH1_S  16
+/* LEDC_OVF_CNT_EN_LSCH1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH1  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH1_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH1_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH1_S  15
+/* LEDC_OVF_NUM_LSCH1 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH1  0x000003FF
+#define LEDC_OVF_NUM_LSCH1_M  ((LEDC_OVF_NUM_LSCH1_V)<<(LEDC_OVF_NUM_LSCH1_S))
+#define LEDC_OVF_NUM_LSCH1_V  0x3FF
+#define LEDC_OVF_NUM_LSCH1_S  5
+/* LEDC_PARA_UP_LSCH1 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH1  (BIT(4))
+#define LEDC_PARA_UP_LSCH1_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH1_V  0x1
+#define LEDC_PARA_UP_LSCH1_S  4
+/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH1  (BIT(3))
+#define LEDC_IDLE_LV_LSCH1_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH1_V  0x1
+#define LEDC_IDLE_LV_LSCH1_S  3
+/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH1  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH1_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH1_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH1_S  2
+/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH1  0x00000003
+#define LEDC_TIMER_SEL_LSCH1_M  ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S))
+#define LEDC_TIMER_SEL_LSCH1_V  0x3
+#define LEDC_TIMER_SEL_LSCH1_S  0
+
+#define LEDC_LSCH1_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0018)
+/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH1  0x00003FFF
+#define LEDC_HPOINT_LSCH1_M  ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S))
+#define LEDC_HPOINT_LSCH1_V  0x3FFF
+#define LEDC_HPOINT_LSCH1_S  0
+
+#define LEDC_LSCH1_DUTY_REG          (DR_REG_LEDC_BASE + 0x001C)
+/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH1  0x0007FFFF
+#define LEDC_DUTY_LSCH1_M  ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))
+#define LEDC_DUTY_LSCH1_V  0x7FFFF
+#define LEDC_DUTY_LSCH1_S  0
+
+#define LEDC_LSCH1_CONF1_REG          (DR_REG_LEDC_BASE + 0x0020)
+/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH1  (BIT(31))
+#define LEDC_DUTY_START_LSCH1_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH1_V  0x1
+#define LEDC_DUTY_START_LSCH1_S  31
+/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH1  (BIT(30))
+#define LEDC_DUTY_INC_LSCH1_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH1_V  0x1
+#define LEDC_DUTY_INC_LSCH1_S  30
+/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH1  0x000003FF
+#define LEDC_DUTY_NUM_LSCH1_M  ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S))
+#define LEDC_DUTY_NUM_LSCH1_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH1_S  20
+/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH1  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH1_M  ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S))
+#define LEDC_DUTY_CYCLE_LSCH1_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH1_S  10
+/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH1  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH1_M  ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S))
+#define LEDC_DUTY_SCALE_LSCH1_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH1_S  0
+
+#define LEDC_LSCH1_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0024)
+/* LEDC_DUTY_LSCH1 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH1  0x0007FFFF
+#define LEDC_DUTY_LSCH1_M  ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))
+#define LEDC_DUTY_LSCH1_V  0x7FFFF
+#define LEDC_DUTY_LSCH1_S  0
+
+#define LEDC_LSCH2_CONF0_REG          (DR_REG_LEDC_BASE + 0x0028)
+/* LEDC_OVF_CNT_RESET_LSCH2 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH2  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH2_M  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH2_V  0x1
+#define LEDC_OVF_CNT_RESET_LSCH2_S  16
+/* LEDC_OVF_CNT_EN_LSCH2 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH2  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH2_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH2_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH2_S  15
+/* LEDC_OVF_NUM_LSCH2 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH2  0x000003FF
+#define LEDC_OVF_NUM_LSCH2_M  ((LEDC_OVF_NUM_LSCH2_V)<<(LEDC_OVF_NUM_LSCH2_S))
+#define LEDC_OVF_NUM_LSCH2_V  0x3FF
+#define LEDC_OVF_NUM_LSCH2_S  5
+/* LEDC_PARA_UP_LSCH2 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH2  (BIT(4))
+#define LEDC_PARA_UP_LSCH2_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH2_V  0x1
+#define LEDC_PARA_UP_LSCH2_S  4
+/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH2  (BIT(3))
+#define LEDC_IDLE_LV_LSCH2_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH2_V  0x1
+#define LEDC_IDLE_LV_LSCH2_S  3
+/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH2  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH2_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH2_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH2_S  2
+/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH2  0x00000003
+#define LEDC_TIMER_SEL_LSCH2_M  ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S))
+#define LEDC_TIMER_SEL_LSCH2_V  0x3
+#define LEDC_TIMER_SEL_LSCH2_S  0
+
+#define LEDC_LSCH2_HPOINT_REG          (DR_REG_LEDC_BASE + 0x002C)
+/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH2  0x00003FFF
+#define LEDC_HPOINT_LSCH2_M  ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S))
+#define LEDC_HPOINT_LSCH2_V  0x3FFF
+#define LEDC_HPOINT_LSCH2_S  0
+
+#define LEDC_LSCH2_DUTY_REG          (DR_REG_LEDC_BASE + 0x0030)
+/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH2  0x0007FFFF
+#define LEDC_DUTY_LSCH2_M  ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))
+#define LEDC_DUTY_LSCH2_V  0x7FFFF
+#define LEDC_DUTY_LSCH2_S  0
+
+#define LEDC_LSCH2_CONF1_REG          (DR_REG_LEDC_BASE + 0x0034)
+/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH2  (BIT(31))
+#define LEDC_DUTY_START_LSCH2_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH2_V  0x1
+#define LEDC_DUTY_START_LSCH2_S  31
+/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH2  (BIT(30))
+#define LEDC_DUTY_INC_LSCH2_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH2_V  0x1
+#define LEDC_DUTY_INC_LSCH2_S  30
+/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH2  0x000003FF
+#define LEDC_DUTY_NUM_LSCH2_M  ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S))
+#define LEDC_DUTY_NUM_LSCH2_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH2_S  20
+/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH2  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH2_M  ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S))
+#define LEDC_DUTY_CYCLE_LSCH2_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH2_S  10
+/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH2  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH2_M  ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S))
+#define LEDC_DUTY_SCALE_LSCH2_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH2_S  0
+
+#define LEDC_LSCH2_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0038)
+/* LEDC_DUTY_LSCH2 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH2  0x0007FFFF
+#define LEDC_DUTY_LSCH2_M  ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))
+#define LEDC_DUTY_LSCH2_V  0x7FFFF
+#define LEDC_DUTY_LSCH2_S  0
+
+#define LEDC_LSCH3_CONF0_REG          (DR_REG_LEDC_BASE + 0x003C)
+/* LEDC_OVF_CNT_RESET_LSCH3 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH3  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH3_M  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH3_V  0x1
+#define LEDC_OVF_CNT_RESET_LSCH3_S  16
+/* LEDC_OVF_CNT_EN_LSCH3 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH3  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH3_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH3_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH3_S  15
+/* LEDC_OVF_NUM_LSCH3 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH3  0x000003FF
+#define LEDC_OVF_NUM_LSCH3_M  ((LEDC_OVF_NUM_LSCH3_V)<<(LEDC_OVF_NUM_LSCH3_S))
+#define LEDC_OVF_NUM_LSCH3_V  0x3FF
+#define LEDC_OVF_NUM_LSCH3_S  5
+/* LEDC_PARA_UP_LSCH3 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH3  (BIT(4))
+#define LEDC_PARA_UP_LSCH3_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH3_V  0x1
+#define LEDC_PARA_UP_LSCH3_S  4
+/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH3  (BIT(3))
+#define LEDC_IDLE_LV_LSCH3_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH3_V  0x1
+#define LEDC_IDLE_LV_LSCH3_S  3
+/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH3  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH3_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH3_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH3_S  2
+/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH3  0x00000003
+#define LEDC_TIMER_SEL_LSCH3_M  ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S))
+#define LEDC_TIMER_SEL_LSCH3_V  0x3
+#define LEDC_TIMER_SEL_LSCH3_S  0
+
+#define LEDC_LSCH3_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0040)
+/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH3  0x00003FFF
+#define LEDC_HPOINT_LSCH3_M  ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S))
+#define LEDC_HPOINT_LSCH3_V  0x3FFF
+#define LEDC_HPOINT_LSCH3_S  0
+
+#define LEDC_LSCH3_DUTY_REG          (DR_REG_LEDC_BASE + 0x0044)
+/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH3  0x0007FFFF
+#define LEDC_DUTY_LSCH3_M  ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))
+#define LEDC_DUTY_LSCH3_V  0x7FFFF
+#define LEDC_DUTY_LSCH3_S  0
+
+#define LEDC_LSCH3_CONF1_REG          (DR_REG_LEDC_BASE + 0x0048)
+/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH3  (BIT(31))
+#define LEDC_DUTY_START_LSCH3_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH3_V  0x1
+#define LEDC_DUTY_START_LSCH3_S  31
+/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH3  (BIT(30))
+#define LEDC_DUTY_INC_LSCH3_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH3_V  0x1
+#define LEDC_DUTY_INC_LSCH3_S  30
+/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH3  0x000003FF
+#define LEDC_DUTY_NUM_LSCH3_M  ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S))
+#define LEDC_DUTY_NUM_LSCH3_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH3_S  20
+/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH3  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH3_M  ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S))
+#define LEDC_DUTY_CYCLE_LSCH3_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH3_S  10
+/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH3  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH3_M  ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S))
+#define LEDC_DUTY_SCALE_LSCH3_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH3_S  0
+
+#define LEDC_LSCH3_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x004C)
+/* LEDC_DUTY_LSCH3 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH3  0x0007FFFF
+#define LEDC_DUTY_LSCH3_M  ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))
+#define LEDC_DUTY_LSCH3_V  0x7FFFF
+#define LEDC_DUTY_LSCH3_S  0
+
+#define LEDC_LSCH4_CONF0_REG          (DR_REG_LEDC_BASE + 0x0050)
+/* LEDC_OVF_CNT_RESET_LSCH4 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH4  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH4_M  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH4_V  0x1
+#define LEDC_OVF_CNT_RESET_LSCH4_S  16
+/* LEDC_OVF_CNT_EN_LSCH4 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH4  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH4_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH4_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH4_S  15
+/* LEDC_OVF_NUM_LSCH4 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH4  0x000003FF
+#define LEDC_OVF_NUM_LSCH4_M  ((LEDC_OVF_NUM_LSCH4_V)<<(LEDC_OVF_NUM_LSCH4_S))
+#define LEDC_OVF_NUM_LSCH4_V  0x3FF
+#define LEDC_OVF_NUM_LSCH4_S  5
+/* LEDC_PARA_UP_LSCH4 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH4  (BIT(4))
+#define LEDC_PARA_UP_LSCH4_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH4_V  0x1
+#define LEDC_PARA_UP_LSCH4_S  4
+/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH4  (BIT(3))
+#define LEDC_IDLE_LV_LSCH4_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH4_V  0x1
+#define LEDC_IDLE_LV_LSCH4_S  3
+/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH4  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH4_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH4_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH4_S  2
+/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH4  0x00000003
+#define LEDC_TIMER_SEL_LSCH4_M  ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S))
+#define LEDC_TIMER_SEL_LSCH4_V  0x3
+#define LEDC_TIMER_SEL_LSCH4_S  0
+
+#define LEDC_LSCH4_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0054)
+/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH4  0x00003FFF
+#define LEDC_HPOINT_LSCH4_M  ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S))
+#define LEDC_HPOINT_LSCH4_V  0x3FFF
+#define LEDC_HPOINT_LSCH4_S  0
+
+#define LEDC_LSCH4_DUTY_REG          (DR_REG_LEDC_BASE + 0x0058)
+/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH4  0x0007FFFF
+#define LEDC_DUTY_LSCH4_M  ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))
+#define LEDC_DUTY_LSCH4_V  0x7FFFF
+#define LEDC_DUTY_LSCH4_S  0
+
+#define LEDC_LSCH4_CONF1_REG          (DR_REG_LEDC_BASE + 0x005C)
+/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH4  (BIT(31))
+#define LEDC_DUTY_START_LSCH4_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH4_V  0x1
+#define LEDC_DUTY_START_LSCH4_S  31
+/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH4  (BIT(30))
+#define LEDC_DUTY_INC_LSCH4_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH4_V  0x1
+#define LEDC_DUTY_INC_LSCH4_S  30
+/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH4  0x000003FF
+#define LEDC_DUTY_NUM_LSCH4_M  ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S))
+#define LEDC_DUTY_NUM_LSCH4_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH4_S  20
+/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH4  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH4_M  ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S))
+#define LEDC_DUTY_CYCLE_LSCH4_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH4_S  10
+/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH4  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH4_M  ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S))
+#define LEDC_DUTY_SCALE_LSCH4_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH4_S  0
+
+#define LEDC_LSCH4_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0060)
+/* LEDC_DUTY_LSCH4 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH4  0x0007FFFF
+#define LEDC_DUTY_LSCH4_M  ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))
+#define LEDC_DUTY_LSCH4_V  0x7FFFF
+#define LEDC_DUTY_LSCH4_S  0
+
+#define LEDC_LSCH5_CONF0_REG          (DR_REG_LEDC_BASE + 0x0064)
+/* LEDC_OVF_CNT_RESET_LSCH5 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH5  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH5_M  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH5_V  0x1
+#define LEDC_OVF_CNT_RESET_LSCH5_S  16
+/* LEDC_OVF_CNT_EN_LSCH5 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH5  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH5_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH5_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH5_S  15
+/* LEDC_OVF_NUM_LSCH5 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH5  0x000003FF
+#define LEDC_OVF_NUM_LSCH5_M  ((LEDC_OVF_NUM_LSCH5_V)<<(LEDC_OVF_NUM_LSCH5_S))
+#define LEDC_OVF_NUM_LSCH5_V  0x3FF
+#define LEDC_OVF_NUM_LSCH5_S  5
+/* LEDC_PARA_UP_LSCH5 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH5  (BIT(4))
+#define LEDC_PARA_UP_LSCH5_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH5_V  0x1
+#define LEDC_PARA_UP_LSCH5_S  4
+/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH5  (BIT(3))
+#define LEDC_IDLE_LV_LSCH5_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH5_V  0x1
+#define LEDC_IDLE_LV_LSCH5_S  3
+/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH5  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH5_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH5_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH5_S  2
+/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH5  0x00000003
+#define LEDC_TIMER_SEL_LSCH5_M  ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S))
+#define LEDC_TIMER_SEL_LSCH5_V  0x3
+#define LEDC_TIMER_SEL_LSCH5_S  0
+
+#define LEDC_LSCH5_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0068)
+/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH5  0x00003FFF
+#define LEDC_HPOINT_LSCH5_M  ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S))
+#define LEDC_HPOINT_LSCH5_V  0x3FFF
+#define LEDC_HPOINT_LSCH5_S  0
+
+#define LEDC_LSCH5_DUTY_REG          (DR_REG_LEDC_BASE + 0x006C)
+/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH5  0x0007FFFF
+#define LEDC_DUTY_LSCH5_M  ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))
+#define LEDC_DUTY_LSCH5_V  0x7FFFF
+#define LEDC_DUTY_LSCH5_S  0
+
+#define LEDC_LSCH5_CONF1_REG          (DR_REG_LEDC_BASE + 0x0070)
+/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH5  (BIT(31))
+#define LEDC_DUTY_START_LSCH5_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH5_V  0x1
+#define LEDC_DUTY_START_LSCH5_S  31
+/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH5  (BIT(30))
+#define LEDC_DUTY_INC_LSCH5_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH5_V  0x1
+#define LEDC_DUTY_INC_LSCH5_S  30
+/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH5  0x000003FF
+#define LEDC_DUTY_NUM_LSCH5_M  ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S))
+#define LEDC_DUTY_NUM_LSCH5_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH5_S  20
+/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH5  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH5_M  ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S))
+#define LEDC_DUTY_CYCLE_LSCH5_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH5_S  10
+/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH5  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH5_M  ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S))
+#define LEDC_DUTY_SCALE_LSCH5_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH5_S  0
+
+#define LEDC_LSCH5_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0074)
+/* LEDC_DUTY_LSCH5 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH5  0x0007FFFF
+#define LEDC_DUTY_LSCH5_M  ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))
+#define LEDC_DUTY_LSCH5_V  0x7FFFF
+#define LEDC_DUTY_LSCH5_S  0
+
+#define LEDC_LSTIMER0_CONF_REG          (DR_REG_LEDC_BASE + 0x00a0)
+/* LEDC_LSTIMER0_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_LSTIMER0_PARA_UP  (BIT(25))
+#define LEDC_LSTIMER0_PARA_UP_M  (BIT(25))
+#define LEDC_LSTIMER0_PARA_UP_V  0x1
+#define LEDC_LSTIMER0_PARA_UP_S  25
+/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_TICK_SEL_LSTIMER0  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER0_M  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER0_V  0x1
+#define LEDC_TICK_SEL_LSTIMER0_S  24
+/* LEDC_LSTIMER0_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_LSTIMER0_RST  (BIT(23))
+#define LEDC_LSTIMER0_RST_M  (BIT(23))
+#define LEDC_LSTIMER0_RST_V  0x1
+#define LEDC_LSTIMER0_RST_S  23
+/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_PAUSE  (BIT(22))
+#define LEDC_LSTIMER0_PAUSE_M  (BIT(22))
+#define LEDC_LSTIMER0_PAUSE_V  0x1
+#define LEDC_LSTIMER0_PAUSE_S  22
+/* LEDC_CLK_DIV_LSTIMER0 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER0  0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER0_M  ((LEDC_CLK_DIV_LSTIMER0_V)<<(LEDC_CLK_DIV_LSTIMER0_S))
+#define LEDC_CLK_DIV_LSTIMER0_V  0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER0_S  4
+/* LEDC_LSTIMER0_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: */
+#define LEDC_LSTIMER0_DUTY_RES  0x0000000F
+#define LEDC_LSTIMER0_DUTY_RES_M  ((LEDC_LSTIMER0_DUTY_RES_V)<<(LEDC_LSTIMER0_DUTY_RES_S))
+#define LEDC_LSTIMER0_DUTY_RES_V  0xF
+#define LEDC_LSTIMER0_DUTY_RES_S  0
+
+#define LEDC_LSTIMER0_VALUE_REG          (DR_REG_LEDC_BASE + 0x00a4)
+/* LEDC_LSTIMER0_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_CNT  0x00003FFF
+#define LEDC_LSTIMER0_CNT_M  ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S))
+#define LEDC_LSTIMER0_CNT_V  0x3FFF
+#define LEDC_LSTIMER0_CNT_S  0
+
+#define LEDC_LSTIMER1_CONF_REG          (DR_REG_LEDC_BASE + 0x00a8)
+/* LEDC_LSTIMER1_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_LSTIMER1_PARA_UP  (BIT(25))
+#define LEDC_LSTIMER1_PARA_UP_M  (BIT(25))
+#define LEDC_LSTIMER1_PARA_UP_V  0x1
+#define LEDC_LSTIMER1_PARA_UP_S  25
+/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_TICK_SEL_LSTIMER1  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER1_M  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER1_V  0x1
+#define LEDC_TICK_SEL_LSTIMER1_S  24
+/* LEDC_LSTIMER1_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_LSTIMER1_RST  (BIT(23))
+#define LEDC_LSTIMER1_RST_M  (BIT(23))
+#define LEDC_LSTIMER1_RST_V  0x1
+#define LEDC_LSTIMER1_RST_S  23
+/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_PAUSE  (BIT(22))
+#define LEDC_LSTIMER1_PAUSE_M  (BIT(22))
+#define LEDC_LSTIMER1_PAUSE_V  0x1
+#define LEDC_LSTIMER1_PAUSE_S  22
+/* LEDC_CLK_DIV_LSTIMER1 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER1  0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER1_M  ((LEDC_CLK_DIV_LSTIMER1_V)<<(LEDC_CLK_DIV_LSTIMER1_S))
+#define LEDC_CLK_DIV_LSTIMER1_V  0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER1_S  4
+/* LEDC_LSTIMER1_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: */
+#define LEDC_LSTIMER1_DUTY_RES  0x0000000F
+#define LEDC_LSTIMER1_DUTY_RES_M  ((LEDC_LSTIMER1_DUTY_RES_V)<<(LEDC_LSTIMER1_DUTY_RES_S))
+#define LEDC_LSTIMER1_DUTY_RES_V  0xF
+#define LEDC_LSTIMER1_DUTY_RES_S  0
+
+#define LEDC_LSTIMER1_VALUE_REG          (DR_REG_LEDC_BASE + 0x00aC)
+/* LEDC_LSTIMER1_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_CNT  0x00003FFF
+#define LEDC_LSTIMER1_CNT_M  ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S))
+#define LEDC_LSTIMER1_CNT_V  0x3FFF
+#define LEDC_LSTIMER1_CNT_S  0
+
+#define LEDC_LSTIMER2_CONF_REG          (DR_REG_LEDC_BASE + 0x00b0)
+/* LEDC_LSTIMER2_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_LSTIMER2_PARA_UP  (BIT(25))
+#define LEDC_LSTIMER2_PARA_UP_M  (BIT(25))
+#define LEDC_LSTIMER2_PARA_UP_V  0x1
+#define LEDC_LSTIMER2_PARA_UP_S  25
+/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_TICK_SEL_LSTIMER2  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER2_M  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER2_V  0x1
+#define LEDC_TICK_SEL_LSTIMER2_S  24
+/* LEDC_LSTIMER2_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_LSTIMER2_RST  (BIT(23))
+#define LEDC_LSTIMER2_RST_M  (BIT(23))
+#define LEDC_LSTIMER2_RST_V  0x1
+#define LEDC_LSTIMER2_RST_S  23
+/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_PAUSE  (BIT(22))
+#define LEDC_LSTIMER2_PAUSE_M  (BIT(22))
+#define LEDC_LSTIMER2_PAUSE_V  0x1
+#define LEDC_LSTIMER2_PAUSE_S  22
+/* LEDC_CLK_DIV_LSTIMER2 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER2  0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER2_M  ((LEDC_CLK_DIV_LSTIMER2_V)<<(LEDC_CLK_DIV_LSTIMER2_S))
+#define LEDC_CLK_DIV_LSTIMER2_V  0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER2_S  4
+/* LEDC_LSTIMER2_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: */
+#define LEDC_LSTIMER2_DUTY_RES  0x0000000F
+#define LEDC_LSTIMER2_DUTY_RES_M  ((LEDC_LSTIMER2_DUTY_RES_V)<<(LEDC_LSTIMER2_DUTY_RES_S))
+#define LEDC_LSTIMER2_DUTY_RES_V  0xF
+#define LEDC_LSTIMER2_DUTY_RES_S  0
+
+#define LEDC_LSTIMER2_VALUE_REG          (DR_REG_LEDC_BASE + 0x00b4)
+/* LEDC_LSTIMER2_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_CNT  0x00003FFF
+#define LEDC_LSTIMER2_CNT_M  ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S))
+#define LEDC_LSTIMER2_CNT_V  0x3FFF
+#define LEDC_LSTIMER2_CNT_S  0
+
+#define LEDC_LSTIMER3_CONF_REG          (DR_REG_LEDC_BASE + 0x00b8)
+/* LEDC_LSTIMER3_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_LSTIMER3_PARA_UP  (BIT(25))
+#define LEDC_LSTIMER3_PARA_UP_M  (BIT(25))
+#define LEDC_LSTIMER3_PARA_UP_V  0x1
+#define LEDC_LSTIMER3_PARA_UP_S  25
+/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_TICK_SEL_LSTIMER3  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER3_M  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER3_V  0x1
+#define LEDC_TICK_SEL_LSTIMER3_S  24
+/* LEDC_LSTIMER3_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_LSTIMER3_RST  (BIT(23))
+#define LEDC_LSTIMER3_RST_M  (BIT(23))
+#define LEDC_LSTIMER3_RST_V  0x1
+#define LEDC_LSTIMER3_RST_S  23
+/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_PAUSE  (BIT(22))
+#define LEDC_LSTIMER3_PAUSE_M  (BIT(22))
+#define LEDC_LSTIMER3_PAUSE_V  0x1
+#define LEDC_LSTIMER3_PAUSE_S  22
+/* LEDC_CLK_DIV_LSTIMER3 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER3  0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER3_M  ((LEDC_CLK_DIV_LSTIMER3_V)<<(LEDC_CLK_DIV_LSTIMER3_S))
+#define LEDC_CLK_DIV_LSTIMER3_V  0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER3_S  4
+/* LEDC_LSTIMER3_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: */
+#define LEDC_LSTIMER3_DUTY_RES  0x0000000F
+#define LEDC_LSTIMER3_DUTY_RES_M  ((LEDC_LSTIMER3_DUTY_RES_V)<<(LEDC_LSTIMER3_DUTY_RES_S))
+#define LEDC_LSTIMER3_DUTY_RES_V  0xF
+#define LEDC_LSTIMER3_DUTY_RES_S  0
+
+#define LEDC_LSTIMER3_VALUE_REG          (DR_REG_LEDC_BASE + 0x00BC)
+/* LEDC_LSTIMER3_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_CNT  0x00003FFF
+#define LEDC_LSTIMER3_CNT_M  ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S))
+#define LEDC_LSTIMER3_CNT_V  0x3FFF
+#define LEDC_LSTIMER3_CNT_S  0
+
+#define LEDC_INT_RAW_REG          (DR_REG_LEDC_BASE + 0x00C0)
+/* LEDC_OVF_CNT_LSCH5_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_RAW    (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_RAW_M  (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH5_INT_RAW_S  15
+/* LEDC_OVF_CNT_LSCH4_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_RAW    (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_RAW_M  (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH4_INT_RAW_S  14
+/* LEDC_OVF_CNT_LSCH3_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_RAW    (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_RAW_M  (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH3_INT_RAW_S  13
+/* LEDC_OVF_CNT_LSCH2_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_RAW    (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_RAW_M  (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH2_INT_RAW_S  12
+/* LEDC_OVF_CNT_LSCH1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_RAW    (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_RAW_M  (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH1_INT_RAW_S  11
+/* LEDC_OVF_CNT_LSCH0_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_RAW    (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_RAW_M  (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH0_INT_RAW_S  10
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S  9
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S  8
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S  7
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S  6
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S  5
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S  4
+/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_OVF_INT_RAW  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_RAW_M  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_RAW_V  0x1
+#define LEDC_LSTIMER3_OVF_INT_RAW_S  3
+/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_OVF_INT_RAW  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_RAW_M  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_RAW_V  0x1
+#define LEDC_LSTIMER2_OVF_INT_RAW_S  2
+/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_OVF_INT_RAW  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_RAW_M  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_RAW_V  0x1
+#define LEDC_LSTIMER1_OVF_INT_RAW_S  1
+/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_OVF_INT_RAW  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_RAW_M  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_RAW_V  0x1
+#define LEDC_LSTIMER0_OVF_INT_RAW_S  0
+
+#define LEDC_INT_ST_REG          (DR_REG_LEDC_BASE + 0x00c4)
+/* LEDC_OVF_CNT_LSCH5_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_ST  (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_ST_M  (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH5_INT_ST_S  15
+/* LEDC_OVF_CNT_LSCH4_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_ST  (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_ST_M  (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH4_INT_ST_S  14
+/* LEDC_OVF_CNT_LSCH3_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_ST  (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_ST_M  (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH3_INT_ST_S  13
+/* LEDC_OVF_CNT_LSCH2_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_ST    (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_ST_M  (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH2_INT_ST_S  12
+/* LEDC_OVF_CNT_LSCH1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_ST    (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_ST_M  (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH1_INT_ST_S  11
+/* LEDC_OVF_CNT_LSCH0_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_ST    (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_ST_M  (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH0_INT_ST_S  10
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S  9
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S  8
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S  7
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S  6
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S  5
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S  4
+/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_OVF_INT_ST  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_ST_M  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_ST_V  0x1
+#define LEDC_LSTIMER3_OVF_INT_ST_S  3
+/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_OVF_INT_ST  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_ST_M  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_ST_V  0x1
+#define LEDC_LSTIMER2_OVF_INT_ST_S  2
+/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_OVF_INT_ST  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_ST_M  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_ST_V  0x1
+#define LEDC_LSTIMER1_OVF_INT_ST_S  1
+/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_OVF_INT_ST  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_ST_M  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_ST_V  0x1
+#define LEDC_LSTIMER0_OVF_INT_ST_S  0
+
+#define LEDC_INT_ENA_REG          (DR_REG_LEDC_BASE + 0xC8)
+/* LEDC_OVF_CNT_LSCH5_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_ENA    (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_ENA_M  (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH5_INT_ENA_S  15
+/* LEDC_OVF_CNT_LSCH4_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_ENA    (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_ENA_M  (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH4_INT_ENA_S  14
+/* LEDC_OVF_CNT_LSCH3_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_ENA    (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_ENA_M  (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH3_INT_ENA_S  13
+/* LEDC_OVF_CNT_LSCH2_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_ENA    (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_ENA_M  (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH2_INT_ENA_S  12
+/* LEDC_OVF_CNT_LSCH1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_ENA    (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_ENA_M  (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH1_INT_ENA_S  11
+/* LEDC_OVF_CNT_LSCH0_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_ENA    (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_ENA_M  (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH0_INT_ENA_S  10
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S  9
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S  8
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S  7
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S  6
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S  5
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S  4
+/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_OVF_INT_ENA  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_ENA_M  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_ENA_V  0x1
+#define LEDC_LSTIMER3_OVF_INT_ENA_S  3
+/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_OVF_INT_ENA  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_ENA_M  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_ENA_V  0x1
+#define LEDC_LSTIMER2_OVF_INT_ENA_S  2
+/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_OVF_INT_ENA  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_ENA_M  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_ENA_V  0x1
+#define LEDC_LSTIMER1_OVF_INT_ENA_S  1
+/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_OVF_INT_ENA  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_ENA_M  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_ENA_V  0x1
+#define LEDC_LSTIMER0_OVF_INT_ENA_S  0
+
+#define LEDC_INT_CLR_REG          (DR_REG_LEDC_BASE + 0xCC)
+/* LEDC_OVF_CNT_LSCH5_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_CLR    (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_CLR_M  (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH5_INT_CLR_S  15
+/* LEDC_OVF_CNT_LSCH4_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_CLR    (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_CLR_M  (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH4_INT_CLR_S  14
+/* LEDC_OVF_CNT_LSCH3_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_CLR    (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_CLR_M  (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH3_INT_CLR_S  13
+/* LEDC_OVF_CNT_LSCH2_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_CLR    (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_CLR_M  (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH2_INT_CLR_S  12
+/* LEDC_OVF_CNT_LSCH1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_CLR    (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_CLR_M  (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH1_INT_CLR_S  11
+/* LEDC_OVF_CNT_LSCH0_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_CLR    (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_CLR_M  (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH0_INT_CLR_S  10
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: reg_duty_chng_end_lsch5_int_clr..*/
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S  9
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S  8
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S  7
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S  6
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S  5
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S  4
+/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_OVF_INT_CLR  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_CLR_M  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_CLR_V  0x1
+#define LEDC_LSTIMER3_OVF_INT_CLR_S  3
+/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_OVF_INT_CLR  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_CLR_M  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_CLR_V  0x1
+#define LEDC_LSTIMER2_OVF_INT_CLR_S  2
+/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_OVF_INT_CLR  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_CLR_M  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_CLR_V  0x1
+#define LEDC_LSTIMER1_OVF_INT_CLR_S  1
+/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_OVF_INT_CLR  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_CLR_M  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_CLR_V  0x1
+#define LEDC_LSTIMER0_OVF_INT_CLR_S  0
+
+#define LEDC_CONF_REG          (DR_REG_LEDC_BASE + 0x00d0)
+/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_CLK_EN  (BIT(31))
+#define LEDC_CLK_EN_M  (BIT(31))
+#define LEDC_CLK_EN_V  0x1
+#define LEDC_CLK_EN_S  31
+/* LEDC_APB_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define LEDC_APB_CLK_SEL  0x00000003
+#define LEDC_APB_CLK_SEL_M  ((LEDC_APB_CLK_SEL_V)<<(LEDC_APB_CLK_SEL_S))
+#define LEDC_APB_CLK_SEL_V  0x3
+#define LEDC_APB_CLK_SEL_S  0
+
+#define LEDC_DATE_REG          (DR_REG_LEDC_BASE + 0x00FC)
+/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h19061700 ; */
+/*description: */
+#define LEDC_DATE  0xFFFFFFFF
+#define LEDC_DATE_M  ((LEDC_DATE_V)<<(LEDC_DATE_S))
+#define LEDC_DATE_V  0xFFFFFFFF
+#define LEDC_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_LEDC_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/ledc_struct.h b/components/soc/esp32c3/include/soc/ledc_struct.h
new file mode 100644
index 0000000000..9e5a2a96c1
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/ledc_struct.h
@@ -0,0 +1,220 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_LEDC_STRUCT_H_
+#define _SOC_LEDC_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    struct {
+        struct {
+            union {
+                struct {
+                    uint32_t timer_sel:           2;
+                    uint32_t sig_out_en:          1;
+                    uint32_t idle_lv:             1;
+                    uint32_t low_speed_update:    1;
+                    uint32_t ovf_num:            10;
+                    uint32_t ovf_cnt_en:          1;
+                    uint32_t ovf_cnt_rst:         1;
+                    uint32_t reserved17:         15;
+                };
+                uint32_t val;
+            } conf0;
+            union {
+                struct {
+                    uint32_t hpoint:      14;
+                    uint32_t reserved14:  18;
+                };
+                uint32_t val;
+            } hpoint;
+            union {
+                struct {
+                    uint32_t duty:      19;
+                    uint32_t reserved19:13;
+                };
+                uint32_t val;
+            } duty;
+            union {
+                struct {
+                    uint32_t duty_scale:      10;
+                    uint32_t duty_cycle:      10;
+                    uint32_t duty_num:        10;
+                    uint32_t duty_inc:         1;
+                    uint32_t duty_start:       1;
+                };
+                uint32_t val;
+            } conf1;
+            union {
+                struct {
+                    uint32_t duty_read: 19;
+                    uint32_t reserved19:  13;
+                };
+                uint32_t val;
+            } duty_rd;
+        } channel[6];
+    } channel_group[1];
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    struct {
+        struct {
+            union {
+                struct {
+                    uint32_t duty_resolution:   4;
+                    uint32_t clock_divider:    18;
+                    uint32_t pause:             1;
+                    uint32_t rst:               1;
+                    uint32_t tick_sel:          1;
+                    uint32_t low_speed_update:  1;
+                    uint32_t reserved26:        6;
+                };
+                uint32_t val;
+            } conf;
+            union {
+                struct {
+                    uint32_t timer_cnt:   14;
+                    uint32_t reserved14:  18;
+                };
+                uint32_t val;
+            } value;
+        } timer[4];
+    } timer_group[1];
+    union {
+        struct {
+            uint32_t lstimer0_ovf:                1;
+            uint32_t lstimer1_ovf:                1;
+            uint32_t lstimer2_ovf:                1;
+            uint32_t lstimer3_ovf:                1;
+            uint32_t duty_chng_end_lsch0:         1;
+            uint32_t duty_chng_end_lsch1:         1;
+            uint32_t duty_chng_end_lsch2:         1;
+            uint32_t duty_chng_end_lsch3:         1;
+            uint32_t duty_chng_end_lsch4:         1;
+            uint32_t duty_chng_end_lsch5:         1;
+            uint32_t ovf_cnt_lsch0:               1;
+            uint32_t ovf_cnt_lsch1:               1;
+            uint32_t ovf_cnt_lsch2:               1;
+            uint32_t ovf_cnt_lsch3:               1;
+            uint32_t ovf_cnt_lsch4:               1;
+            uint32_t ovf_cnt_lsch5:               1;
+            uint32_t reserved16:                 16;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t lstimer0_ovf:               1;
+            uint32_t lstimer1_ovf:               1;
+            uint32_t lstimer2_ovf:               1;
+            uint32_t lstimer3_ovf:               1;
+            uint32_t duty_chng_end_lsch0:        1;
+            uint32_t duty_chng_end_lsch1:        1;
+            uint32_t duty_chng_end_lsch2:        1;
+            uint32_t duty_chng_end_lsch3:        1;
+            uint32_t duty_chng_end_lsch4:        1;
+            uint32_t duty_chng_end_lsch5:        1;
+            uint32_t ovf_cnt_lsch0:              1;
+            uint32_t ovf_cnt_lsch1:              1;
+            uint32_t ovf_cnt_lsch2:              1;
+            uint32_t ovf_cnt_lsch3:              1;
+            uint32_t ovf_cnt_lsch4:              1;
+            uint32_t ovf_cnt_lsch5:              1;
+            uint32_t reserved16:                16;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t lstimer0_ovf:                1;
+            uint32_t lstimer1_ovf:                1;
+            uint32_t lstimer2_ovf:                1;
+            uint32_t lstimer3_ovf:                1;
+            uint32_t duty_chng_end_lsch0:         1;
+            uint32_t duty_chng_end_lsch1:         1;
+            uint32_t duty_chng_end_lsch2:         1;
+            uint32_t duty_chng_end_lsch3:         1;
+            uint32_t duty_chng_end_lsch4:         1;
+            uint32_t duty_chng_end_lsch5:         1;
+            uint32_t ovf_cnt_lsch0:               1;
+            uint32_t ovf_cnt_lsch1:               1;
+            uint32_t ovf_cnt_lsch2:               1;
+            uint32_t ovf_cnt_lsch3:               1;
+            uint32_t ovf_cnt_lsch4:               1;
+            uint32_t ovf_cnt_lsch5:               1;
+            uint32_t reserved16:                 16;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t lstimer0_ovf:                1;
+            uint32_t lstimer1_ovf:                1;
+            uint32_t lstimer2_ovf:                1;
+            uint32_t lstimer3_ovf:                1;
+            uint32_t duty_chng_end_lsch0:         1;
+            uint32_t duty_chng_end_lsch1:         1;
+            uint32_t duty_chng_end_lsch2:         1;
+            uint32_t duty_chng_end_lsch3:         1;
+            uint32_t duty_chng_end_lsch4:         1;
+            uint32_t duty_chng_end_lsch5:         1;
+            uint32_t ovf_cnt_lsch0:               1;
+            uint32_t ovf_cnt_lsch1:               1;
+            uint32_t ovf_cnt_lsch2:               1;
+            uint32_t ovf_cnt_lsch3:               1;
+            uint32_t ovf_cnt_lsch4:               1;
+            uint32_t ovf_cnt_lsch5:               1;
+            uint32_t reserved16:                 16;
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t apb_clk_sel: 2;
+            uint32_t reserved2:  29;
+            uint32_t clk_en:      1;
+        };
+        uint32_t val;
+    } conf;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    union {
+        struct {
+            uint32_t date:      32;
+        };
+        uint32_t val;
+    } date;
+} ledc_dev_t;
+extern ledc_dev_t LEDC;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_LEDC_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/mpu_caps.h b/components/soc/esp32c3/include/soc/mpu_caps.h
new file mode 100644
index 0000000000..b267547590
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/mpu_caps.h
@@ -0,0 +1,21 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED    0
+#define SOC_MPU_MIN_REGION_SIZE                   0x20000000
+#define SOC_MPU_REGIONS_MAX_NUM                   8
+#define SOC_MPU_REGION_RO_SUPPORTED               0
+#define SOC_MPU_REGION_WO_SUPPORTED               0
diff --git a/components/soc/esp32c3/include/soc/periph_defs.h b/components/soc/esp32c3/include/soc/periph_defs.h
new file mode 100644
index 0000000000..4b1045aba9
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/periph_defs.h
@@ -0,0 +1,119 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PERIPH_LEDC_MODULE = 0,
+    PERIPH_UART0_MODULE,
+    PERIPH_UART1_MODULE,
+    PERIPH_USB_DEVICE_MODULE,
+    PERIPH_I2C0_MODULE,
+    PERIPH_I2S1_MODULE,
+    PERIPH_TIMG0_MODULE,
+    PERIPH_TIMG1_MODULE,
+    PERIPH_UHCI0_MODULE,
+    PERIPH_RMT_MODULE,
+    PERIPH_SPI_MODULE,  //SPI1
+    PERIPH_SPI2_MODULE, //SPI2
+    PERIPH_TWAI_MODULE,
+    PERIPH_RNG_MODULE,
+    PERIPH_WIFI_MODULE,
+    PERIPH_BT_MODULE,
+    PERIPH_WIFI_BT_COMMON_MODULE,
+    PERIPH_BT_BASEBAND_MODULE,
+    PERIPH_BT_LC_MODULE,
+    PERIPH_RSA_MODULE,
+    PERIPH_AES_MODULE,
+    PERIPH_SHA_MODULE,
+    PERIPH_HMAC_MODULE,
+    PERIPH_DS_MODULE,
+    PERIPH_GDMA_MODULE,
+    PERIPH_SYSTIMER_MODULE,
+    PERIPH_MODULE_MAX
+} periph_module_t;
+
+typedef enum {
+    ETS_WIFI_MAC_INTR_SOURCE = 0,               /**< interrupt of WiFi MAC, level*/
+    ETS_WIFI_MAC_NMI_SOURCE,                    /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
+    ETS_WIFI_PWR_INTR_SOURCE,                   /**< */
+    ETS_WIFI_BB_INTR_SOURCE,                    /**< interrupt of WiFi BB, level, we can do some calibartion*/
+    ETS_BT_MAC_INTR_SOURCE,                     /**< will be cancelled*/
+    ETS_BT_BB_INTR_SOURCE,                      /**< interrupt of BT BB, level*/
+    ETS_BT_BB_NMI_SOURCE,                       /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
+    ETS_RWBT_INTR_SOURCE,                       /**< interrupt of RWBT, level*/
+    ETS_RWBLE_INTR_SOURCE,                      /**< interrupt of RWBLE, level*/
+    ETS_RWBT_NMI_SOURCE,                        /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
+    ETS_RWBLE_NMI_SOURCE,                       /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
+    ETS_I2C_MASTER_SOURCE,                      /**< interrupt of I2C Master, level*/
+    ETS_SLC0_INTR_SOURCE,                       /**< interrupt of SLC0, level*/
+    ETS_SLC1_INTR_SOURCE,                       /**< interrupt of SLC1, level*/
+    ETS_APB_CTRL_INTR_SOURCE,                   /**< interrupt of APB ctrl, ?*/
+    ETS_UHCI0_INTR_SOURCE,                      /**< interrupt of UHCI0, level*/
+    ETS_GPIO_INTR_SOURCE,                       /**< interrupt of GPIO, level*/
+    ETS_GPIO_NMI_SOURCE,                        /**< interrupt of GPIO, NMI*/
+    ETS_SPI1_INTR_SOURCE,                       /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
+    ETS_SPI2_INTR_SOURCE,                       /**< interrupt of SPI2, level*/
+    ETS_I2S1_INTR_SOURCE,                       /**< interrupt of I2S1, level*/
+    ETS_UART0_INTR_SOURCE,                      /**< interrupt of UART0, level*/
+    ETS_UART1_INTR_SOURCE,                      /**< interrupt of UART1, level*/
+    ETS_LEDC_INTR_SOURCE,                       /**< interrupt of LED PWM, level*/
+    ETS_EFUSE_INTR_SOURCE,                      /**< interrupt of efuse, level, not likely to use*/
+    ETS_TWAI_INTR_SOURCE,                        /**< interrupt of can, level*/
+    ETS_USB_INTR_SOURCE,                        /**< interrupt of USB, level*/
+    ETS_RTC_CORE_INTR_SOURCE,                   /**< interrupt of rtc core, level, include rtc watchdog*/
+    ETS_RMT_INTR_SOURCE,                        /**< interrupt of remote controller, level*/
+    ETS_I2C_EXT0_INTR_SOURCE,                   /**< interrupt of I2C controller1, level*/
+    ETS_TIMER1_INTR_SOURCE,
+    ETS_TIMER2_INTR_SOURCE,
+    ETS_TG0_T0_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP0, TIMER0, level*/
+    ETS_TG0_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
+    ETS_TG1_T0_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP1, TIMER0, level*/
+    ETS_TG1_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
+    ETS_CACHE_IA_INTR_SOURCE,                   /**< interrupt of Cache Invalied Access, LEVEL*/
+    ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE,      /**< interrupt of system timer 0, EDGE*/
+    ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE,      /**< interrupt of system timer 1, EDGE*/
+    ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE,      /**< interrupt of system timer 2, EDGE*/
+    ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE,       /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
+    ETS_ICACHE_PRELOAD0_INTR_SOURCE,            /**< interrupt of ICache perload operation, LEVEL*/
+    ETS_ICACHE_SYNC0_INTR_SOURCE,               /**< interrupt of instruction cache sync done, LEVEL*/
+    ETS_APB_ADC_INTR_SOURCE,                    /**< interrupt of APB ADC, LEVEL*/
+    ETS_DMA_CH0_INTR_SOURCE,                    /**< interrupt of general DMA channel 0, LEVEL*/
+    ETS_DMA_CH1_INTR_SOURCE,                    /**< interrupt of general DMA channel 1, LEVEL*/
+    ETS_DMA_CH2_INTR_SOURCE,                    /**< interrupt of general DMA channel 2, LEVEL*/
+    ETS_RSA_INTR_SOURCE,                        /**< interrupt of RSA accelerator, level*/
+    ETS_AES_INTR_SOURCE,                        /**< interrupt of AES accelerator, level*/
+    ETS_SHA_INTR_SOURCE,                        /**< interrupt of SHA accelerator, level*/
+    ETS_FROM_CPU_INTR0_SOURCE,                  /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
+    ETS_FROM_CPU_INTR1_SOURCE,                  /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
+    ETS_FROM_CPU_INTR2_SOURCE,                  /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
+    ETS_FROM_CPU_INTR3_SOURCE,                  /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
+    ETS_ASSIST_DEBUG_INTR_SOURCE,               /**< interrupt of Assist debug module, LEVEL*/
+    ETS_DMA_APBPERI_PMS_INTR_SOURCE,
+    ETS_CORE0_IRAM0_PMS_INTR_SOURCE,
+    ETS_CORE0_DRAM0_PMS_INTR_SOURCE,
+    ETS_CORE0_PIF_PMS_INTR_SOURCE,
+    ETS_CORE0_PIF_PMS_SIZE_INTR_SOURCE,
+    ETS_BAK_PMS_VIOLATE_INTR_SOURCE,
+    ETS_CACHE_CORE0_ACS_INTR_SOURCE,
+    ETS_MAX_INTR_SOURCE,
+} periph_interrput_t;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/include/soc/rmt_caps.h b/components/soc/esp32c3/include/soc/rmt_caps.h
new file mode 100644
index 0000000000..1004c1f1d5
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/rmt_caps.h
@@ -0,0 +1,33 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SOC_RMT_CHANNEL_MEM_WORDS       (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
+#define SOC_RMT_TX_CHANNELS_NUM         (2)  /*!< Number of channels that capable of Transmit */
+#define SOC_RMT_RX_CHANNELS_NUM         (2)  /*!< Number of channels that capable of Receive */
+#define SOC_RMT_CHANNELS_NUM            (4)  /*!< Total 8 channels (each channel can be configured to either TX or RX) */
+#define SOC_RMT_SUPPORT_RX_PINGPONG     (1)  /*!< Support Ping-Pong mode on RX path */
+#define SOC_RMT_SUPPORT_RX_DEMODULATION (1)  /*!< Support signal demodulation on RX path (i.e. remove carrier) */
+#define SOC_RMT_SUPPORT_TX_LOOP_COUNT   (1)  /*!< Support transmit specified number of cycles in loop mode */
+#define SOC_RMT_SUPPORT_TX_GROUP        (1)  /*!< Support a group of TX channels to transmit simultaneously */
+#define SOC_RMT_SUPPORT_XTAL            (1)  /*!< Support set XTAL clock as the RMT clock source */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/include/soc/rmt_reg.h b/components/soc/esp32c3/include/soc/rmt_reg.h
new file mode 100644
index 0000000000..4a916e99d0
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/rmt_reg.h
@@ -0,0 +1,1144 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_RMT_REG_H_
+#define _SOC_RMT_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define RMT_CH0DATA_REG          (DR_REG_RMT_BASE + 0x0000)
+
+#define RMT_CH1DATA_REG          (DR_REG_RMT_BASE + 0x0004)
+
+#define RMT_CH2DATA_REG          (DR_REG_RMT_BASE + 0x0008)
+
+#define RMT_CH3DATA_REG          (DR_REG_RMT_BASE + 0x000c)
+
+#define RMT_CH0CONF0_REG          (DR_REG_RMT_BASE + 0x0010)
+/* RMT_CONF_UPDATE_CH0 : WT ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CONF_UPDATE_CH0  (BIT(24))
+#define RMT_CONF_UPDATE_CH0_M  (BIT(24))
+#define RMT_CONF_UPDATE_CH0_V  0x1
+#define RMT_CONF_UPDATE_CH0_S  24
+/* RMT_AFIFO_RST_CH0 : WT ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define RMT_AFIFO_RST_CH0  (BIT(23))
+#define RMT_AFIFO_RST_CH0_M  (BIT(23))
+#define RMT_AFIFO_RST_CH0_V  0x1
+#define RMT_AFIFO_RST_CH0_S  23
+/* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: */
+#define RMT_CARRIER_OUT_LV_CH0  (BIT(22))
+#define RMT_CARRIER_OUT_LV_CH0_M  (BIT(22))
+#define RMT_CARRIER_OUT_LV_CH0_V  0x1
+#define RMT_CARRIER_OUT_LV_CH0_S  22
+/* RMT_CARRIER_EN_CH0 : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: */
+#define RMT_CARRIER_EN_CH0  (BIT(21))
+#define RMT_CARRIER_EN_CH0_M  (BIT(21))
+#define RMT_CARRIER_EN_CH0_V  0x1
+#define RMT_CARRIER_EN_CH0_S  21
+/* RMT_CARRIER_EFF_EN_CH0 : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: */
+#define RMT_CARRIER_EFF_EN_CH0  (BIT(20))
+#define RMT_CARRIER_EFF_EN_CH0_M  (BIT(20))
+#define RMT_CARRIER_EFF_EN_CH0_V  0x1
+#define RMT_CARRIER_EFF_EN_CH0_S  20
+/* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[18:16] ;default: 3'h1 ; */
+/*description: */
+#define RMT_MEM_SIZE_CH0  0x00000007
+#define RMT_MEM_SIZE_CH0_M  ((RMT_MEM_SIZE_CH0_V)<<(RMT_MEM_SIZE_CH0_S))
+#define RMT_MEM_SIZE_CH0_V  0x7
+#define RMT_MEM_SIZE_CH0_S  16
+/* RMT_DIV_CNT_CH0 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */
+/*description: */
+#define RMT_DIV_CNT_CH0  0x000000FF
+#define RMT_DIV_CNT_CH0_M  ((RMT_DIV_CNT_CH0_V)<<(RMT_DIV_CNT_CH0_S))
+#define RMT_DIV_CNT_CH0_V  0xFF
+#define RMT_DIV_CNT_CH0_S  8
+/* RMT_TX_STOP_CH0 : R/W/SC ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_STOP_CH0  (BIT(7))
+#define RMT_TX_STOP_CH0_M  (BIT(7))
+#define RMT_TX_STOP_CH0_V  0x1
+#define RMT_TX_STOP_CH0_S  7
+/* RMT_IDLE_OUT_EN_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define RMT_IDLE_OUT_EN_CH0  (BIT(6))
+#define RMT_IDLE_OUT_EN_CH0_M  (BIT(6))
+#define RMT_IDLE_OUT_EN_CH0_V  0x1
+#define RMT_IDLE_OUT_EN_CH0_S  6
+/* RMT_IDLE_OUT_LV_CH0 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define RMT_IDLE_OUT_LV_CH0  (BIT(5))
+#define RMT_IDLE_OUT_LV_CH0_M  (BIT(5))
+#define RMT_IDLE_OUT_LV_CH0_V  0x1
+#define RMT_IDLE_OUT_LV_CH0_S  5
+/* RMT_MEM_TX_WRAP_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_TX_WRAP_EN_CH0  (BIT(4))
+#define RMT_MEM_TX_WRAP_EN_CH0_M  (BIT(4))
+#define RMT_MEM_TX_WRAP_EN_CH0_V  0x1
+#define RMT_MEM_TX_WRAP_EN_CH0_S  4
+/* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_CONTI_MODE_CH0  (BIT(3))
+#define RMT_TX_CONTI_MODE_CH0_M  (BIT(3))
+#define RMT_TX_CONTI_MODE_CH0_V  0x1
+#define RMT_TX_CONTI_MODE_CH0_S  3
+/* RMT_APB_MEM_RST_CH0 : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RST_CH0  (BIT(2))
+#define RMT_APB_MEM_RST_CH0_M  (BIT(2))
+#define RMT_APB_MEM_RST_CH0_V  0x1
+#define RMT_APB_MEM_RST_CH0_S  2
+/* RMT_MEM_RD_RST_CH0 : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_RD_RST_CH0  (BIT(1))
+#define RMT_MEM_RD_RST_CH0_M  (BIT(1))
+#define RMT_MEM_RD_RST_CH0_V  0x1
+#define RMT_MEM_RD_RST_CH0_S  1
+/* RMT_TX_START_CH0 : WT ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define RMT_TX_START_CH0  (BIT(0))
+#define RMT_TX_START_CH0_M  (BIT(0))
+#define RMT_TX_START_CH0_V  0x1
+#define RMT_TX_START_CH0_S  0
+
+#define RMT_CH1CONF0_REG          (DR_REG_RMT_BASE + 0x0014)
+/* RMT_CONF_UPDATE_CH1 : WT ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CONF_UPDATE_CH1  (BIT(24))
+#define RMT_CONF_UPDATE_CH1_M  (BIT(24))
+#define RMT_CONF_UPDATE_CH1_V  0x1
+#define RMT_CONF_UPDATE_CH1_S  24
+/* RMT_AFIFO_RST_CH1 : WT ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define RMT_AFIFO_RST_CH1  (BIT(23))
+#define RMT_AFIFO_RST_CH1_M  (BIT(23))
+#define RMT_AFIFO_RST_CH1_V  0x1
+#define RMT_AFIFO_RST_CH1_S  23
+/* RMT_CARRIER_OUT_LV_CH1 : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: */
+#define RMT_CARRIER_OUT_LV_CH1  (BIT(22))
+#define RMT_CARRIER_OUT_LV_CH1_M  (BIT(22))
+#define RMT_CARRIER_OUT_LV_CH1_V  0x1
+#define RMT_CARRIER_OUT_LV_CH1_S  22
+/* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: */
+#define RMT_CARRIER_EN_CH1  (BIT(21))
+#define RMT_CARRIER_EN_CH1_M  (BIT(21))
+#define RMT_CARRIER_EN_CH1_V  0x1
+#define RMT_CARRIER_EN_CH1_S  21
+/* RMT_CARRIER_EFF_EN_CH1 : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: */
+#define RMT_CARRIER_EFF_EN_CH1  (BIT(20))
+#define RMT_CARRIER_EFF_EN_CH1_M  (BIT(20))
+#define RMT_CARRIER_EFF_EN_CH1_V  0x1
+#define RMT_CARRIER_EFF_EN_CH1_S  20
+/* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[18:16] ;default: 3'h1 ; */
+/*description: */
+#define RMT_MEM_SIZE_CH1  0x00000007
+#define RMT_MEM_SIZE_CH1_M  ((RMT_MEM_SIZE_CH1_V)<<(RMT_MEM_SIZE_CH1_S))
+#define RMT_MEM_SIZE_CH1_V  0x7
+#define RMT_MEM_SIZE_CH1_S  16
+/* RMT_DIV_CNT_CH1 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */
+/*description: */
+#define RMT_DIV_CNT_CH1  0x000000FF
+#define RMT_DIV_CNT_CH1_M  ((RMT_DIV_CNT_CH1_V)<<(RMT_DIV_CNT_CH1_S))
+#define RMT_DIV_CNT_CH1_V  0xFF
+#define RMT_DIV_CNT_CH1_S  8
+/* RMT_TX_STOP_CH1 : R/W/SC ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_STOP_CH1  (BIT(7))
+#define RMT_TX_STOP_CH1_M  (BIT(7))
+#define RMT_TX_STOP_CH1_V  0x1
+#define RMT_TX_STOP_CH1_S  7
+/* RMT_IDLE_OUT_EN_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define RMT_IDLE_OUT_EN_CH1  (BIT(6))
+#define RMT_IDLE_OUT_EN_CH1_M  (BIT(6))
+#define RMT_IDLE_OUT_EN_CH1_V  0x1
+#define RMT_IDLE_OUT_EN_CH1_S  6
+/* RMT_IDLE_OUT_LV_CH1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define RMT_IDLE_OUT_LV_CH1  (BIT(5))
+#define RMT_IDLE_OUT_LV_CH1_M  (BIT(5))
+#define RMT_IDLE_OUT_LV_CH1_V  0x1
+#define RMT_IDLE_OUT_LV_CH1_S  5
+/* RMT_MEM_TX_WRAP_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_TX_WRAP_EN_CH1  (BIT(4))
+#define RMT_MEM_TX_WRAP_EN_CH1_M  (BIT(4))
+#define RMT_MEM_TX_WRAP_EN_CH1_V  0x1
+#define RMT_MEM_TX_WRAP_EN_CH1_S  4
+/* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_CONTI_MODE_CH1  (BIT(3))
+#define RMT_TX_CONTI_MODE_CH1_M  (BIT(3))
+#define RMT_TX_CONTI_MODE_CH1_V  0x1
+#define RMT_TX_CONTI_MODE_CH1_S  3
+/* RMT_APB_MEM_RST_CH1 : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RST_CH1  (BIT(2))
+#define RMT_APB_MEM_RST_CH1_M  (BIT(2))
+#define RMT_APB_MEM_RST_CH1_V  0x1
+#define RMT_APB_MEM_RST_CH1_S  2
+/* RMT_MEM_RD_RST_CH1 : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_RD_RST_CH1  (BIT(1))
+#define RMT_MEM_RD_RST_CH1_M  (BIT(1))
+#define RMT_MEM_RD_RST_CH1_V  0x1
+#define RMT_MEM_RD_RST_CH1_S  1
+/* RMT_TX_START_CH1 : WT ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define RMT_TX_START_CH1  (BIT(0))
+#define RMT_TX_START_CH1_M  (BIT(0))
+#define RMT_TX_START_CH1_V  0x1
+#define RMT_TX_START_CH1_S  0
+
+#define RMT_CH2CONF0_REG          (DR_REG_RMT_BASE + 0x0018)
+/* RMT_CARRIER_OUT_LV_CH2 : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: */
+#define RMT_CARRIER_OUT_LV_CH2  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH2_M  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH2_V  0x1
+#define RMT_CARRIER_OUT_LV_CH2_S  29
+/* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: */
+#define RMT_CARRIER_EN_CH2  (BIT(28))
+#define RMT_CARRIER_EN_CH2_M  (BIT(28))
+#define RMT_CARRIER_EN_CH2_V  0x1
+#define RMT_CARRIER_EN_CH2_S  28
+/* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[25:23] ;default: 3'h1 ; */
+/*description: */
+#define RMT_MEM_SIZE_CH2  0x00000007
+#define RMT_MEM_SIZE_CH2_M  ((RMT_MEM_SIZE_CH2_V)<<(RMT_MEM_SIZE_CH2_S))
+#define RMT_MEM_SIZE_CH2_V  0x7
+#define RMT_MEM_SIZE_CH2_S  23
+/* RMT_IDLE_THRES_CH2 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */
+/*description: */
+#define RMT_IDLE_THRES_CH2  0x00007FFF
+#define RMT_IDLE_THRES_CH2_M  ((RMT_IDLE_THRES_CH2_V)<<(RMT_IDLE_THRES_CH2_S))
+#define RMT_IDLE_THRES_CH2_V  0x7FFF
+#define RMT_IDLE_THRES_CH2_S  8
+/* RMT_DIV_CNT_CH2 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
+/*description: */
+#define RMT_DIV_CNT_CH2  0x000000FF
+#define RMT_DIV_CNT_CH2_M  ((RMT_DIV_CNT_CH2_V)<<(RMT_DIV_CNT_CH2_S))
+#define RMT_DIV_CNT_CH2_V  0xFF
+#define RMT_DIV_CNT_CH2_S  0
+
+#define RMT_CH2CONF1_REG          (DR_REG_RMT_BASE + 0x001c)
+/* RMT_CONF_UPDATE_CH2 : WT ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CONF_UPDATE_CH2  (BIT(15))
+#define RMT_CONF_UPDATE_CH2_M  (BIT(15))
+#define RMT_CONF_UPDATE_CH2_V  0x1
+#define RMT_CONF_UPDATE_CH2_S  15
+/* RMT_AFIFO_RST_CH2 : WT ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define RMT_AFIFO_RST_CH2  (BIT(14))
+#define RMT_AFIFO_RST_CH2_M  (BIT(14))
+#define RMT_AFIFO_RST_CH2_V  0x1
+#define RMT_AFIFO_RST_CH2_S  14
+/* RMT_MEM_RX_WRAP_EN_CH2 : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_RX_WRAP_EN_CH2  (BIT(13))
+#define RMT_MEM_RX_WRAP_EN_CH2_M  (BIT(13))
+#define RMT_MEM_RX_WRAP_EN_CH2_V  0x1
+#define RMT_MEM_RX_WRAP_EN_CH2_S  13
+/* RMT_RX_FILTER_THRES_CH2 : R/W ;bitpos:[12:5] ;default: 8'hf ; */
+/*description: */
+#define RMT_RX_FILTER_THRES_CH2  0x000000FF
+#define RMT_RX_FILTER_THRES_CH2_M  ((RMT_RX_FILTER_THRES_CH2_V)<<(RMT_RX_FILTER_THRES_CH2_S))
+#define RMT_RX_FILTER_THRES_CH2_V  0xFF
+#define RMT_RX_FILTER_THRES_CH2_S  5
+/* RMT_RX_FILTER_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RMT_RX_FILTER_EN_CH2  (BIT(4))
+#define RMT_RX_FILTER_EN_CH2_M  (BIT(4))
+#define RMT_RX_FILTER_EN_CH2_V  0x1
+#define RMT_RX_FILTER_EN_CH2_S  4
+/* RMT_MEM_OWNER_CH2 : R/W/SC ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define RMT_MEM_OWNER_CH2  (BIT(3))
+#define RMT_MEM_OWNER_CH2_M  (BIT(3))
+#define RMT_MEM_OWNER_CH2_V  0x1
+#define RMT_MEM_OWNER_CH2_S  3
+/* RMT_APB_MEM_RST_CH2 : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RST_CH2  (BIT(2))
+#define RMT_APB_MEM_RST_CH2_M  (BIT(2))
+#define RMT_APB_MEM_RST_CH2_V  0x1
+#define RMT_APB_MEM_RST_CH2_S  2
+/* RMT_MEM_WR_RST_CH2 : WT ;bitpos:[1] ;default: 1'h0 ; */
+/*description: */
+#define RMT_MEM_WR_RST_CH2  (BIT(1))
+#define RMT_MEM_WR_RST_CH2_M  (BIT(1))
+#define RMT_MEM_WR_RST_CH2_V  0x1
+#define RMT_MEM_WR_RST_CH2_S  1
+/* RMT_RX_EN_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define RMT_RX_EN_CH2  (BIT(0))
+#define RMT_RX_EN_CH2_M  (BIT(0))
+#define RMT_RX_EN_CH2_V  0x1
+#define RMT_RX_EN_CH2_S  0
+
+#define RMT_CH3CONF0_REG          (DR_REG_RMT_BASE + 0x0020)
+/* RMT_CARRIER_OUT_LV_CH3 : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: */
+#define RMT_CARRIER_OUT_LV_CH3  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH3_M  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH3_V  0x1
+#define RMT_CARRIER_OUT_LV_CH3_S  29
+/* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: */
+#define RMT_CARRIER_EN_CH3  (BIT(28))
+#define RMT_CARRIER_EN_CH3_M  (BIT(28))
+#define RMT_CARRIER_EN_CH3_V  0x1
+#define RMT_CARRIER_EN_CH3_S  28
+/* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[25:23] ;default: 3'h1 ; */
+/*description: */
+#define RMT_MEM_SIZE_CH3  0x00000007
+#define RMT_MEM_SIZE_CH3_M  ((RMT_MEM_SIZE_CH3_V)<<(RMT_MEM_SIZE_CH3_S))
+#define RMT_MEM_SIZE_CH3_V  0x7
+#define RMT_MEM_SIZE_CH3_S  23
+/* RMT_IDLE_THRES_CH3 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */
+/*description: */
+#define RMT_IDLE_THRES_CH3  0x00007FFF
+#define RMT_IDLE_THRES_CH3_M  ((RMT_IDLE_THRES_CH3_V)<<(RMT_IDLE_THRES_CH3_S))
+#define RMT_IDLE_THRES_CH3_V  0x7FFF
+#define RMT_IDLE_THRES_CH3_S  8
+/* RMT_DIV_CNT_CH3 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
+/*description: */
+#define RMT_DIV_CNT_CH3  0x000000FF
+#define RMT_DIV_CNT_CH3_M  ((RMT_DIV_CNT_CH3_V)<<(RMT_DIV_CNT_CH3_S))
+#define RMT_DIV_CNT_CH3_V  0xFF
+#define RMT_DIV_CNT_CH3_S  0
+
+#define RMT_CH3CONF1_REG          (DR_REG_RMT_BASE + 0x0024)
+/* RMT_CONF_UPDATE_CH3 : WT ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CONF_UPDATE_CH3  (BIT(15))
+#define RMT_CONF_UPDATE_CH3_M  (BIT(15))
+#define RMT_CONF_UPDATE_CH3_V  0x1
+#define RMT_CONF_UPDATE_CH3_S  15
+/* RMT_AFIFO_RST_CH3 : WT ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define RMT_AFIFO_RST_CH3  (BIT(14))
+#define RMT_AFIFO_RST_CH3_M  (BIT(14))
+#define RMT_AFIFO_RST_CH3_V  0x1
+#define RMT_AFIFO_RST_CH3_S  14
+/* RMT_MEM_RX_WRAP_EN_CH3 : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_RX_WRAP_EN_CH3  (BIT(13))
+#define RMT_MEM_RX_WRAP_EN_CH3_M  (BIT(13))
+#define RMT_MEM_RX_WRAP_EN_CH3_V  0x1
+#define RMT_MEM_RX_WRAP_EN_CH3_S  13
+/* RMT_RX_FILTER_THRES_CH3 : R/W ;bitpos:[12:5] ;default: 8'hf ; */
+/*description: */
+#define RMT_RX_FILTER_THRES_CH3  0x000000FF
+#define RMT_RX_FILTER_THRES_CH3_M  ((RMT_RX_FILTER_THRES_CH3_V)<<(RMT_RX_FILTER_THRES_CH3_S))
+#define RMT_RX_FILTER_THRES_CH3_V  0xFF
+#define RMT_RX_FILTER_THRES_CH3_S  5
+/* RMT_RX_FILTER_EN_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RMT_RX_FILTER_EN_CH3  (BIT(4))
+#define RMT_RX_FILTER_EN_CH3_M  (BIT(4))
+#define RMT_RX_FILTER_EN_CH3_V  0x1
+#define RMT_RX_FILTER_EN_CH3_S  4
+/* RMT_MEM_OWNER_CH3 : R/W/SC ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define RMT_MEM_OWNER_CH3  (BIT(3))
+#define RMT_MEM_OWNER_CH3_M  (BIT(3))
+#define RMT_MEM_OWNER_CH3_V  0x1
+#define RMT_MEM_OWNER_CH3_S  3
+/* RMT_APB_MEM_RST_CH3 : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RST_CH3  (BIT(2))
+#define RMT_APB_MEM_RST_CH3_M  (BIT(2))
+#define RMT_APB_MEM_RST_CH3_V  0x1
+#define RMT_APB_MEM_RST_CH3_S  2
+/* RMT_MEM_WR_RST_CH3 : WT ;bitpos:[1] ;default: 1'h0 ; */
+/*description: */
+#define RMT_MEM_WR_RST_CH3  (BIT(1))
+#define RMT_MEM_WR_RST_CH3_M  (BIT(1))
+#define RMT_MEM_WR_RST_CH3_V  0x1
+#define RMT_MEM_WR_RST_CH3_S  1
+/* RMT_RX_EN_CH3 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define RMT_RX_EN_CH3  (BIT(0))
+#define RMT_RX_EN_CH3_M  (BIT(0))
+#define RMT_RX_EN_CH3_V  0x1
+#define RMT_RX_EN_CH3_S  0
+
+#define RMT_CH0STATUS_REG          (DR_REG_RMT_BASE + 0x0028)
+/* RMT_APB_MEM_RADDR_CH0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define RMT_APB_MEM_RADDR_CH0  0x000000FF
+#define RMT_APB_MEM_RADDR_CH0_M  ((RMT_APB_MEM_RADDR_CH0_V)<<(RMT_APB_MEM_RADDR_CH0_S))
+#define RMT_APB_MEM_RADDR_CH0_V  0xFF
+#define RMT_APB_MEM_RADDR_CH0_S  24
+/* RMT_APB_MEM_WR_ERR_CH0 : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WR_ERR_CH0  (BIT(23))
+#define RMT_APB_MEM_WR_ERR_CH0_M  (BIT(23))
+#define RMT_APB_MEM_WR_ERR_CH0_V  0x1
+#define RMT_APB_MEM_WR_ERR_CH0_S  23
+/* RMT_MEM_EMPTY_CH0 : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_EMPTY_CH0  (BIT(22))
+#define RMT_MEM_EMPTY_CH0_M  (BIT(22))
+#define RMT_MEM_EMPTY_CH0_V  0x1
+#define RMT_MEM_EMPTY_CH0_S  22
+/* RMT_APB_MEM_RD_ERR_CH0 : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RD_ERR_CH0  (BIT(21))
+#define RMT_APB_MEM_RD_ERR_CH0_M  (BIT(21))
+#define RMT_APB_MEM_RD_ERR_CH0_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH0_S  21
+/* RMT_APB_MEM_WADDR_CH0 : RO ;bitpos:[20:12] ;default: 9'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WADDR_CH0  0x000001FF
+#define RMT_APB_MEM_WADDR_CH0_M  ((RMT_APB_MEM_WADDR_CH0_V)<<(RMT_APB_MEM_WADDR_CH0_S))
+#define RMT_APB_MEM_WADDR_CH0_V  0x1FF
+#define RMT_APB_MEM_WADDR_CH0_S  12
+/* RMT_STATE_CH0 : RO ;bitpos:[11:9] ;default: 3'b0 ; */
+/*description: */
+#define RMT_STATE_CH0  0x00000007
+#define RMT_STATE_CH0_M  ((RMT_STATE_CH0_V)<<(RMT_STATE_CH0_S))
+#define RMT_STATE_CH0_V  0x7
+#define RMT_STATE_CH0_S  9
+/* RMT_MEM_RADDR_EX_CH0 : RO ;bitpos:[8:0] ;default: 9'b0 ; */
+/*description: */
+#define RMT_MEM_RADDR_EX_CH0  0x000001FF
+#define RMT_MEM_RADDR_EX_CH0_M  ((RMT_MEM_RADDR_EX_CH0_V)<<(RMT_MEM_RADDR_EX_CH0_S))
+#define RMT_MEM_RADDR_EX_CH0_V  0x1FF
+#define RMT_MEM_RADDR_EX_CH0_S  0
+
+#define RMT_CH1STATUS_REG          (DR_REG_RMT_BASE + 0x002c)
+/* RMT_APB_MEM_RADDR_CH1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define RMT_APB_MEM_RADDR_CH1  0x000000FF
+#define RMT_APB_MEM_RADDR_CH1_M  ((RMT_APB_MEM_RADDR_CH1_V)<<(RMT_APB_MEM_RADDR_CH1_S))
+#define RMT_APB_MEM_RADDR_CH1_V  0xFF
+#define RMT_APB_MEM_RADDR_CH1_S  24
+/* RMT_APB_MEM_WR_ERR_CH1 : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WR_ERR_CH1  (BIT(23))
+#define RMT_APB_MEM_WR_ERR_CH1_M  (BIT(23))
+#define RMT_APB_MEM_WR_ERR_CH1_V  0x1
+#define RMT_APB_MEM_WR_ERR_CH1_S  23
+/* RMT_MEM_EMPTY_CH1 : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_EMPTY_CH1  (BIT(22))
+#define RMT_MEM_EMPTY_CH1_M  (BIT(22))
+#define RMT_MEM_EMPTY_CH1_V  0x1
+#define RMT_MEM_EMPTY_CH1_S  22
+/* RMT_APB_MEM_RD_ERR_CH1 : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RD_ERR_CH1  (BIT(21))
+#define RMT_APB_MEM_RD_ERR_CH1_M  (BIT(21))
+#define RMT_APB_MEM_RD_ERR_CH1_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH1_S  21
+/* RMT_APB_MEM_WADDR_CH1 : RO ;bitpos:[20:12] ;default: 9'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WADDR_CH1  0x000001FF
+#define RMT_APB_MEM_WADDR_CH1_M  ((RMT_APB_MEM_WADDR_CH1_V)<<(RMT_APB_MEM_WADDR_CH1_S))
+#define RMT_APB_MEM_WADDR_CH1_V  0x1FF
+#define RMT_APB_MEM_WADDR_CH1_S  12
+/* RMT_STATE_CH1 : RO ;bitpos:[11:9] ;default: 3'b0 ; */
+/*description: */
+#define RMT_STATE_CH1  0x00000007
+#define RMT_STATE_CH1_M  ((RMT_STATE_CH1_V)<<(RMT_STATE_CH1_S))
+#define RMT_STATE_CH1_V  0x7
+#define RMT_STATE_CH1_S  9
+/* RMT_MEM_RADDR_EX_CH1 : RO ;bitpos:[8:0] ;default: 9'b0 ; */
+/*description: */
+#define RMT_MEM_RADDR_EX_CH1  0x000001FF
+#define RMT_MEM_RADDR_EX_CH1_M  ((RMT_MEM_RADDR_EX_CH1_V)<<(RMT_MEM_RADDR_EX_CH1_S))
+#define RMT_MEM_RADDR_EX_CH1_V  0x1FF
+#define RMT_MEM_RADDR_EX_CH1_S  0
+
+#define RMT_CH2STATUS_REG          (DR_REG_RMT_BASE + 0x0030)
+/* RMT_APB_MEM_RD_ERR_CH2 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RD_ERR_CH2  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH2_M  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH2_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH2_S  27
+/* RMT_MEM_FULL_CH2 : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_FULL_CH2  (BIT(26))
+#define RMT_MEM_FULL_CH2_M  (BIT(26))
+#define RMT_MEM_FULL_CH2_V  0x1
+#define RMT_MEM_FULL_CH2_S  26
+/* RMT_MEM_OWNER_ERR_CH2 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_OWNER_ERR_CH2  (BIT(25))
+#define RMT_MEM_OWNER_ERR_CH2_M  (BIT(25))
+#define RMT_MEM_OWNER_ERR_CH2_V  0x1
+#define RMT_MEM_OWNER_ERR_CH2_S  25
+/* RMT_STATE_CH2 : RO ;bitpos:[24:22] ;default: 3'b0 ; */
+/*description: */
+#define RMT_STATE_CH2  0x00000007
+#define RMT_STATE_CH2_M  ((RMT_STATE_CH2_V)<<(RMT_STATE_CH2_S))
+#define RMT_STATE_CH2_V  0x7
+#define RMT_STATE_CH2_S  22
+/* RMT_APB_MEM_RADDR_CH2 : RO ;bitpos:[20:12] ;default: 9'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RADDR_CH2  0x000001FF
+#define RMT_APB_MEM_RADDR_CH2_M  ((RMT_APB_MEM_RADDR_CH2_V)<<(RMT_APB_MEM_RADDR_CH2_S))
+#define RMT_APB_MEM_RADDR_CH2_V  0x1FF
+#define RMT_APB_MEM_RADDR_CH2_S  12
+/* RMT_MEM_WADDR_EX_CH2 : RO ;bitpos:[8:0] ;default: 9'b0 ; */
+/*description: */
+#define RMT_MEM_WADDR_EX_CH2  0x000001FF
+#define RMT_MEM_WADDR_EX_CH2_M  ((RMT_MEM_WADDR_EX_CH2_V)<<(RMT_MEM_WADDR_EX_CH2_S))
+#define RMT_MEM_WADDR_EX_CH2_V  0x1FF
+#define RMT_MEM_WADDR_EX_CH2_S  0
+
+#define RMT_CH3STATUS_REG          (DR_REG_RMT_BASE + 0x0034)
+/* RMT_APB_MEM_RD_ERR_CH3 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RD_ERR_CH3  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH3_M  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH3_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH3_S  27
+/* RMT_MEM_FULL_CH3 : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_FULL_CH3  (BIT(26))
+#define RMT_MEM_FULL_CH3_M  (BIT(26))
+#define RMT_MEM_FULL_CH3_V  0x1
+#define RMT_MEM_FULL_CH3_S  26
+/* RMT_MEM_OWNER_ERR_CH3 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_OWNER_ERR_CH3  (BIT(25))
+#define RMT_MEM_OWNER_ERR_CH3_M  (BIT(25))
+#define RMT_MEM_OWNER_ERR_CH3_V  0x1
+#define RMT_MEM_OWNER_ERR_CH3_S  25
+/* RMT_STATE_CH3 : RO ;bitpos:[24:22] ;default: 3'b0 ; */
+/*description: */
+#define RMT_STATE_CH3  0x00000007
+#define RMT_STATE_CH3_M  ((RMT_STATE_CH3_V)<<(RMT_STATE_CH3_S))
+#define RMT_STATE_CH3_V  0x7
+#define RMT_STATE_CH3_S  22
+/* RMT_APB_MEM_RADDR_CH3 : RO ;bitpos:[20:12] ;default: 9'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RADDR_CH3  0x000001FF
+#define RMT_APB_MEM_RADDR_CH3_M  ((RMT_APB_MEM_RADDR_CH3_V)<<(RMT_APB_MEM_RADDR_CH3_S))
+#define RMT_APB_MEM_RADDR_CH3_V  0x1FF
+#define RMT_APB_MEM_RADDR_CH3_S  12
+/* RMT_MEM_WADDR_EX_CH3 : RO ;bitpos:[8:0] ;default: 9'b0 ; */
+/*description: */
+#define RMT_MEM_WADDR_EX_CH3  0x000001FF
+#define RMT_MEM_WADDR_EX_CH3_M  ((RMT_MEM_WADDR_EX_CH3_V)<<(RMT_MEM_WADDR_EX_CH3_S))
+#define RMT_MEM_WADDR_EX_CH3_V  0x1FF
+#define RMT_MEM_WADDR_EX_CH3_S  0
+
+#define RMT_INT_RAW_REG          (DR_REG_RMT_BASE + 0x0038)
+/* RMT_CH1_TX_LOOP_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_TX_LOOP_INT_RAW  (BIT(13))
+#define RMT_CH1_TX_LOOP_INT_RAW_M  (BIT(13))
+#define RMT_CH1_TX_LOOP_INT_RAW_V  0x1
+#define RMT_CH1_TX_LOOP_INT_RAW_S  13
+/* RMT_CH0_TX_LOOP_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_TX_LOOP_INT_RAW  (BIT(12))
+#define RMT_CH0_TX_LOOP_INT_RAW_M  (BIT(12))
+#define RMT_CH0_TX_LOOP_INT_RAW_V  0x1
+#define RMT_CH0_TX_LOOP_INT_RAW_S  12
+/* RMT_CH3_RX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH3_RX_THR_EVENT_INT_RAW  (BIT(11))
+#define RMT_CH3_RX_THR_EVENT_INT_RAW_M  (BIT(11))
+#define RMT_CH3_RX_THR_EVENT_INT_RAW_V  0x1
+#define RMT_CH3_RX_THR_EVENT_INT_RAW_S  11
+/* RMT_CH2_RX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH2_RX_THR_EVENT_INT_RAW  (BIT(10))
+#define RMT_CH2_RX_THR_EVENT_INT_RAW_M  (BIT(10))
+#define RMT_CH2_RX_THR_EVENT_INT_RAW_V  0x1
+#define RMT_CH2_RX_THR_EVENT_INT_RAW_S  10
+/* RMT_CH1_TX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_TX_THR_EVENT_INT_RAW  (BIT(9))
+#define RMT_CH1_TX_THR_EVENT_INT_RAW_M  (BIT(9))
+#define RMT_CH1_TX_THR_EVENT_INT_RAW_V  0x1
+#define RMT_CH1_TX_THR_EVENT_INT_RAW_S  9
+/* RMT_CH0_TX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_TX_THR_EVENT_INT_RAW  (BIT(8))
+#define RMT_CH0_TX_THR_EVENT_INT_RAW_M  (BIT(8))
+#define RMT_CH0_TX_THR_EVENT_INT_RAW_V  0x1
+#define RMT_CH0_TX_THR_EVENT_INT_RAW_S  8
+/* RMT_CH3_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH3_ERR_INT_RAW  (BIT(7))
+#define RMT_CH3_ERR_INT_RAW_M  (BIT(7))
+#define RMT_CH3_ERR_INT_RAW_V  0x1
+#define RMT_CH3_ERR_INT_RAW_S  7
+/* RMT_CH2_ERR_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH2_ERR_INT_RAW  (BIT(6))
+#define RMT_CH2_ERR_INT_RAW_M  (BIT(6))
+#define RMT_CH2_ERR_INT_RAW_V  0x1
+#define RMT_CH2_ERR_INT_RAW_S  6
+/* RMT_CH1_ERR_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_ERR_INT_RAW  (BIT(5))
+#define RMT_CH1_ERR_INT_RAW_M  (BIT(5))
+#define RMT_CH1_ERR_INT_RAW_V  0x1
+#define RMT_CH1_ERR_INT_RAW_S  5
+/* RMT_CH0_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_ERR_INT_RAW  (BIT(4))
+#define RMT_CH0_ERR_INT_RAW_M  (BIT(4))
+#define RMT_CH0_ERR_INT_RAW_V  0x1
+#define RMT_CH0_ERR_INT_RAW_S  4
+/* RMT_CH3_RX_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH3_RX_END_INT_RAW  (BIT(3))
+#define RMT_CH3_RX_END_INT_RAW_M  (BIT(3))
+#define RMT_CH3_RX_END_INT_RAW_V  0x1
+#define RMT_CH3_RX_END_INT_RAW_S  3
+/* RMT_CH2_RX_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH2_RX_END_INT_RAW  (BIT(2))
+#define RMT_CH2_RX_END_INT_RAW_M  (BIT(2))
+#define RMT_CH2_RX_END_INT_RAW_V  0x1
+#define RMT_CH2_RX_END_INT_RAW_S  2
+/* RMT_CH1_TX_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_TX_END_INT_RAW  (BIT(1))
+#define RMT_CH1_TX_END_INT_RAW_M  (BIT(1))
+#define RMT_CH1_TX_END_INT_RAW_V  0x1
+#define RMT_CH1_TX_END_INT_RAW_S  1
+/* RMT_CH0_TX_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_TX_END_INT_RAW  (BIT(0))
+#define RMT_CH0_TX_END_INT_RAW_M  (BIT(0))
+#define RMT_CH0_TX_END_INT_RAW_V  0x1
+#define RMT_CH0_TX_END_INT_RAW_S  0
+
+#define RMT_INT_ST_REG          (DR_REG_RMT_BASE + 0x003c)
+/* RMT_CH1_TX_LOOP_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_TX_LOOP_INT_ST  (BIT(13))
+#define RMT_CH1_TX_LOOP_INT_ST_M  (BIT(13))
+#define RMT_CH1_TX_LOOP_INT_ST_V  0x1
+#define RMT_CH1_TX_LOOP_INT_ST_S  13
+/* RMT_CH0_TX_LOOP_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_TX_LOOP_INT_ST  (BIT(12))
+#define RMT_CH0_TX_LOOP_INT_ST_M  (BIT(12))
+#define RMT_CH0_TX_LOOP_INT_ST_V  0x1
+#define RMT_CH0_TX_LOOP_INT_ST_S  12
+/* RMT_CH3_RX_THR_EVENT_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH3_RX_THR_EVENT_INT_ST  (BIT(11))
+#define RMT_CH3_RX_THR_EVENT_INT_ST_M  (BIT(11))
+#define RMT_CH3_RX_THR_EVENT_INT_ST_V  0x1
+#define RMT_CH3_RX_THR_EVENT_INT_ST_S  11
+/* RMT_CH2_RX_THR_EVENT_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH2_RX_THR_EVENT_INT_ST  (BIT(10))
+#define RMT_CH2_RX_THR_EVENT_INT_ST_M  (BIT(10))
+#define RMT_CH2_RX_THR_EVENT_INT_ST_V  0x1
+#define RMT_CH2_RX_THR_EVENT_INT_ST_S  10
+/* RMT_CH1_TX_THR_EVENT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_TX_THR_EVENT_INT_ST  (BIT(9))
+#define RMT_CH1_TX_THR_EVENT_INT_ST_M  (BIT(9))
+#define RMT_CH1_TX_THR_EVENT_INT_ST_V  0x1
+#define RMT_CH1_TX_THR_EVENT_INT_ST_S  9
+/* RMT_CH0_TX_THR_EVENT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_TX_THR_EVENT_INT_ST  (BIT(8))
+#define RMT_CH0_TX_THR_EVENT_INT_ST_M  (BIT(8))
+#define RMT_CH0_TX_THR_EVENT_INT_ST_V  0x1
+#define RMT_CH0_TX_THR_EVENT_INT_ST_S  8
+/* RMT_CH3_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH3_ERR_INT_ST  (BIT(7))
+#define RMT_CH3_ERR_INT_ST_M  (BIT(7))
+#define RMT_CH3_ERR_INT_ST_V  0x1
+#define RMT_CH3_ERR_INT_ST_S  7
+/* RMT_CH2_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH2_ERR_INT_ST  (BIT(6))
+#define RMT_CH2_ERR_INT_ST_M  (BIT(6))
+#define RMT_CH2_ERR_INT_ST_V  0x1
+#define RMT_CH2_ERR_INT_ST_S  6
+/* RMT_CH1_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_ERR_INT_ST  (BIT(5))
+#define RMT_CH1_ERR_INT_ST_M  (BIT(5))
+#define RMT_CH1_ERR_INT_ST_V  0x1
+#define RMT_CH1_ERR_INT_ST_S  5
+/* RMT_CH0_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_ERR_INT_ST  (BIT(4))
+#define RMT_CH0_ERR_INT_ST_M  (BIT(4))
+#define RMT_CH0_ERR_INT_ST_V  0x1
+#define RMT_CH0_ERR_INT_ST_S  4
+/* RMT_CH3_RX_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH3_RX_END_INT_ST  (BIT(3))
+#define RMT_CH3_RX_END_INT_ST_M  (BIT(3))
+#define RMT_CH3_RX_END_INT_ST_V  0x1
+#define RMT_CH3_RX_END_INT_ST_S  3
+/* RMT_CH2_RX_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH2_RX_END_INT_ST  (BIT(2))
+#define RMT_CH2_RX_END_INT_ST_M  (BIT(2))
+#define RMT_CH2_RX_END_INT_ST_V  0x1
+#define RMT_CH2_RX_END_INT_ST_S  2
+/* RMT_CH1_TX_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_TX_END_INT_ST  (BIT(1))
+#define RMT_CH1_TX_END_INT_ST_M  (BIT(1))
+#define RMT_CH1_TX_END_INT_ST_V  0x1
+#define RMT_CH1_TX_END_INT_ST_S  1
+/* RMT_CH0_TX_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_TX_END_INT_ST  (BIT(0))
+#define RMT_CH0_TX_END_INT_ST_M  (BIT(0))
+#define RMT_CH0_TX_END_INT_ST_V  0x1
+#define RMT_CH0_TX_END_INT_ST_S  0
+
+#define RMT_INT_ENA_REG          (DR_REG_RMT_BASE + 0x0040)
+/* RMT_CH1_TX_LOOP_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_TX_LOOP_INT_ENA  (BIT(13))
+#define RMT_CH1_TX_LOOP_INT_ENA_M  (BIT(13))
+#define RMT_CH1_TX_LOOP_INT_ENA_V  0x1
+#define RMT_CH1_TX_LOOP_INT_ENA_S  13
+/* RMT_CH0_TX_LOOP_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_TX_LOOP_INT_ENA  (BIT(12))
+#define RMT_CH0_TX_LOOP_INT_ENA_M  (BIT(12))
+#define RMT_CH0_TX_LOOP_INT_ENA_V  0x1
+#define RMT_CH0_TX_LOOP_INT_ENA_S  12
+/* RMT_CH3_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH3_RX_THR_EVENT_INT_ENA  (BIT(11))
+#define RMT_CH3_RX_THR_EVENT_INT_ENA_M  (BIT(11))
+#define RMT_CH3_RX_THR_EVENT_INT_ENA_V  0x1
+#define RMT_CH3_RX_THR_EVENT_INT_ENA_S  11
+/* RMT_CH2_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH2_RX_THR_EVENT_INT_ENA  (BIT(10))
+#define RMT_CH2_RX_THR_EVENT_INT_ENA_M  (BIT(10))
+#define RMT_CH2_RX_THR_EVENT_INT_ENA_V  0x1
+#define RMT_CH2_RX_THR_EVENT_INT_ENA_S  10
+/* RMT_CH1_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_TX_THR_EVENT_INT_ENA  (BIT(9))
+#define RMT_CH1_TX_THR_EVENT_INT_ENA_M  (BIT(9))
+#define RMT_CH1_TX_THR_EVENT_INT_ENA_V  0x1
+#define RMT_CH1_TX_THR_EVENT_INT_ENA_S  9
+/* RMT_CH0_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_TX_THR_EVENT_INT_ENA  (BIT(8))
+#define RMT_CH0_TX_THR_EVENT_INT_ENA_M  (BIT(8))
+#define RMT_CH0_TX_THR_EVENT_INT_ENA_V  0x1
+#define RMT_CH0_TX_THR_EVENT_INT_ENA_S  8
+/* RMT_CH3_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH3_ERR_INT_ENA  (BIT(7))
+#define RMT_CH3_ERR_INT_ENA_M  (BIT(7))
+#define RMT_CH3_ERR_INT_ENA_V  0x1
+#define RMT_CH3_ERR_INT_ENA_S  7
+/* RMT_CH2_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH2_ERR_INT_ENA  (BIT(6))
+#define RMT_CH2_ERR_INT_ENA_M  (BIT(6))
+#define RMT_CH2_ERR_INT_ENA_V  0x1
+#define RMT_CH2_ERR_INT_ENA_S  6
+/* RMT_CH1_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_ERR_INT_ENA  (BIT(5))
+#define RMT_CH1_ERR_INT_ENA_M  (BIT(5))
+#define RMT_CH1_ERR_INT_ENA_V  0x1
+#define RMT_CH1_ERR_INT_ENA_S  5
+/* RMT_CH0_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_ERR_INT_ENA  (BIT(4))
+#define RMT_CH0_ERR_INT_ENA_M  (BIT(4))
+#define RMT_CH0_ERR_INT_ENA_V  0x1
+#define RMT_CH0_ERR_INT_ENA_S  4
+/* RMT_CH3_RX_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH3_RX_END_INT_ENA  (BIT(3))
+#define RMT_CH3_RX_END_INT_ENA_M  (BIT(3))
+#define RMT_CH3_RX_END_INT_ENA_V  0x1
+#define RMT_CH3_RX_END_INT_ENA_S  3
+/* RMT_CH2_RX_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH2_RX_END_INT_ENA  (BIT(2))
+#define RMT_CH2_RX_END_INT_ENA_M  (BIT(2))
+#define RMT_CH2_RX_END_INT_ENA_V  0x1
+#define RMT_CH2_RX_END_INT_ENA_S  2
+/* RMT_CH1_TX_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_TX_END_INT_ENA  (BIT(1))
+#define RMT_CH1_TX_END_INT_ENA_M  (BIT(1))
+#define RMT_CH1_TX_END_INT_ENA_V  0x1
+#define RMT_CH1_TX_END_INT_ENA_S  1
+/* RMT_CH0_TX_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_TX_END_INT_ENA  (BIT(0))
+#define RMT_CH0_TX_END_INT_ENA_M  (BIT(0))
+#define RMT_CH0_TX_END_INT_ENA_V  0x1
+#define RMT_CH0_TX_END_INT_ENA_S  0
+
+#define RMT_INT_CLR_REG          (DR_REG_RMT_BASE + 0x0044)
+/* RMT_CH1_TX_LOOP_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_TX_LOOP_INT_CLR  (BIT(13))
+#define RMT_CH1_TX_LOOP_INT_CLR_M  (BIT(13))
+#define RMT_CH1_TX_LOOP_INT_CLR_V  0x1
+#define RMT_CH1_TX_LOOP_INT_CLR_S  13
+/* RMT_CH0_TX_LOOP_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_TX_LOOP_INT_CLR  (BIT(12))
+#define RMT_CH0_TX_LOOP_INT_CLR_M  (BIT(12))
+#define RMT_CH0_TX_LOOP_INT_CLR_V  0x1
+#define RMT_CH0_TX_LOOP_INT_CLR_S  12
+/* RMT_CH3_RX_THR_EVENT_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH3_RX_THR_EVENT_INT_CLR  (BIT(11))
+#define RMT_CH3_RX_THR_EVENT_INT_CLR_M  (BIT(11))
+#define RMT_CH3_RX_THR_EVENT_INT_CLR_V  0x1
+#define RMT_CH3_RX_THR_EVENT_INT_CLR_S  11
+/* RMT_CH2_RX_THR_EVENT_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH2_RX_THR_EVENT_INT_CLR  (BIT(10))
+#define RMT_CH2_RX_THR_EVENT_INT_CLR_M  (BIT(10))
+#define RMT_CH2_RX_THR_EVENT_INT_CLR_V  0x1
+#define RMT_CH2_RX_THR_EVENT_INT_CLR_S  10
+/* RMT_CH1_TX_THR_EVENT_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_TX_THR_EVENT_INT_CLR  (BIT(9))
+#define RMT_CH1_TX_THR_EVENT_INT_CLR_M  (BIT(9))
+#define RMT_CH1_TX_THR_EVENT_INT_CLR_V  0x1
+#define RMT_CH1_TX_THR_EVENT_INT_CLR_S  9
+/* RMT_CH0_TX_THR_EVENT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_TX_THR_EVENT_INT_CLR  (BIT(8))
+#define RMT_CH0_TX_THR_EVENT_INT_CLR_M  (BIT(8))
+#define RMT_CH0_TX_THR_EVENT_INT_CLR_V  0x1
+#define RMT_CH0_TX_THR_EVENT_INT_CLR_S  8
+/* RMT_CH3_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH3_ERR_INT_CLR  (BIT(7))
+#define RMT_CH3_ERR_INT_CLR_M  (BIT(7))
+#define RMT_CH3_ERR_INT_CLR_V  0x1
+#define RMT_CH3_ERR_INT_CLR_S  7
+/* RMT_CH2_ERR_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH2_ERR_INT_CLR  (BIT(6))
+#define RMT_CH2_ERR_INT_CLR_M  (BIT(6))
+#define RMT_CH2_ERR_INT_CLR_V  0x1
+#define RMT_CH2_ERR_INT_CLR_S  6
+/* RMT_CH1_ERR_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_ERR_INT_CLR  (BIT(5))
+#define RMT_CH1_ERR_INT_CLR_M  (BIT(5))
+#define RMT_CH1_ERR_INT_CLR_V  0x1
+#define RMT_CH1_ERR_INT_CLR_S  5
+/* RMT_CH0_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_ERR_INT_CLR  (BIT(4))
+#define RMT_CH0_ERR_INT_CLR_M  (BIT(4))
+#define RMT_CH0_ERR_INT_CLR_V  0x1
+#define RMT_CH0_ERR_INT_CLR_S  4
+/* RMT_CH3_RX_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH3_RX_END_INT_CLR  (BIT(3))
+#define RMT_CH3_RX_END_INT_CLR_M  (BIT(3))
+#define RMT_CH3_RX_END_INT_CLR_V  0x1
+#define RMT_CH3_RX_END_INT_CLR_S  3
+/* RMT_CH2_RX_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH2_RX_END_INT_CLR  (BIT(2))
+#define RMT_CH2_RX_END_INT_CLR_M  (BIT(2))
+#define RMT_CH2_RX_END_INT_CLR_V  0x1
+#define RMT_CH2_RX_END_INT_CLR_S  2
+/* RMT_CH1_TX_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_TX_END_INT_CLR  (BIT(1))
+#define RMT_CH1_TX_END_INT_CLR_M  (BIT(1))
+#define RMT_CH1_TX_END_INT_CLR_V  0x1
+#define RMT_CH1_TX_END_INT_CLR_S  1
+/* RMT_CH0_TX_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_TX_END_INT_CLR  (BIT(0))
+#define RMT_CH0_TX_END_INT_CLR_M  (BIT(0))
+#define RMT_CH0_TX_END_INT_CLR_V  0x1
+#define RMT_CH0_TX_END_INT_CLR_S  0
+
+#define RMT_CH0CARRIER_DUTY_REG          (DR_REG_RMT_BASE + 0x0048)
+/* RMT_CARRIER_HIGH_CH0 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
+/*description: */
+#define RMT_CARRIER_HIGH_CH0  0x0000FFFF
+#define RMT_CARRIER_HIGH_CH0_M  ((RMT_CARRIER_HIGH_CH0_V)<<(RMT_CARRIER_HIGH_CH0_S))
+#define RMT_CARRIER_HIGH_CH0_V  0xFFFF
+#define RMT_CARRIER_HIGH_CH0_S  16
+/* RMT_CARRIER_LOW_CH0 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
+/*description: */
+#define RMT_CARRIER_LOW_CH0  0x0000FFFF
+#define RMT_CARRIER_LOW_CH0_M  ((RMT_CARRIER_LOW_CH0_V)<<(RMT_CARRIER_LOW_CH0_S))
+#define RMT_CARRIER_LOW_CH0_V  0xFFFF
+#define RMT_CARRIER_LOW_CH0_S  0
+
+#define RMT_CH1CARRIER_DUTY_REG          (DR_REG_RMT_BASE + 0x004c)
+/* RMT_CARRIER_HIGH_CH1 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
+/*description: */
+#define RMT_CARRIER_HIGH_CH1  0x0000FFFF
+#define RMT_CARRIER_HIGH_CH1_M  ((RMT_CARRIER_HIGH_CH1_V)<<(RMT_CARRIER_HIGH_CH1_S))
+#define RMT_CARRIER_HIGH_CH1_V  0xFFFF
+#define RMT_CARRIER_HIGH_CH1_S  16
+/* RMT_CARRIER_LOW_CH1 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
+/*description: */
+#define RMT_CARRIER_LOW_CH1  0x0000FFFF
+#define RMT_CARRIER_LOW_CH1_M  ((RMT_CARRIER_LOW_CH1_V)<<(RMT_CARRIER_LOW_CH1_S))
+#define RMT_CARRIER_LOW_CH1_V  0xFFFF
+#define RMT_CARRIER_LOW_CH1_S  0
+
+#define RMT_CH2_RX_CARRIER_RM_REG          (DR_REG_RMT_BASE + 0x0050)
+/* RMT_CARRIER_HIGH_THRES_CH2 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: */
+#define RMT_CARRIER_HIGH_THRES_CH2  0x0000FFFF
+#define RMT_CARRIER_HIGH_THRES_CH2_M  ((RMT_CARRIER_HIGH_THRES_CH2_V)<<(RMT_CARRIER_HIGH_THRES_CH2_S))
+#define RMT_CARRIER_HIGH_THRES_CH2_V  0xFFFF
+#define RMT_CARRIER_HIGH_THRES_CH2_S  16
+/* RMT_CARRIER_LOW_THRES_CH2 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define RMT_CARRIER_LOW_THRES_CH2  0x0000FFFF
+#define RMT_CARRIER_LOW_THRES_CH2_M  ((RMT_CARRIER_LOW_THRES_CH2_V)<<(RMT_CARRIER_LOW_THRES_CH2_S))
+#define RMT_CARRIER_LOW_THRES_CH2_V  0xFFFF
+#define RMT_CARRIER_LOW_THRES_CH2_S  0
+
+#define RMT_CH3_RX_CARRIER_RM_REG          (DR_REG_RMT_BASE + 0x0054)
+/* RMT_CARRIER_HIGH_THRES_CH3 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: */
+#define RMT_CARRIER_HIGH_THRES_CH3  0x0000FFFF
+#define RMT_CARRIER_HIGH_THRES_CH3_M  ((RMT_CARRIER_HIGH_THRES_CH3_V)<<(RMT_CARRIER_HIGH_THRES_CH3_S))
+#define RMT_CARRIER_HIGH_THRES_CH3_V  0xFFFF
+#define RMT_CARRIER_HIGH_THRES_CH3_S  16
+/* RMT_CARRIER_LOW_THRES_CH3 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define RMT_CARRIER_LOW_THRES_CH3  0x0000FFFF
+#define RMT_CARRIER_LOW_THRES_CH3_M  ((RMT_CARRIER_LOW_THRES_CH3_V)<<(RMT_CARRIER_LOW_THRES_CH3_S))
+#define RMT_CARRIER_LOW_THRES_CH3_V  0xFFFF
+#define RMT_CARRIER_LOW_THRES_CH3_S  0
+
+#define RMT_CH0_TX_LIM_REG          (DR_REG_RMT_BASE + 0x0058)
+/* RMT_LOOP_COUNT_RESET_CH0 : WT ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RMT_LOOP_COUNT_RESET_CH0  (BIT(20))
+#define RMT_LOOP_COUNT_RESET_CH0_M  (BIT(20))
+#define RMT_LOOP_COUNT_RESET_CH0_V  0x1
+#define RMT_LOOP_COUNT_RESET_CH0_S  20
+/* RMT_TX_LOOP_CNT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_CNT_EN_CH0  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH0_M  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH0_V  0x1
+#define RMT_TX_LOOP_CNT_EN_CH0_S  19
+/* RMT_TX_LOOP_NUM_CH0 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_NUM_CH0  0x000003FF
+#define RMT_TX_LOOP_NUM_CH0_M  ((RMT_TX_LOOP_NUM_CH0_V)<<(RMT_TX_LOOP_NUM_CH0_S))
+#define RMT_TX_LOOP_NUM_CH0_V  0x3FF
+#define RMT_TX_LOOP_NUM_CH0_S  9
+/* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: */
+#define RMT_TX_LIM_CH0  0x000001FF
+#define RMT_TX_LIM_CH0_M  ((RMT_TX_LIM_CH0_V)<<(RMT_TX_LIM_CH0_S))
+#define RMT_TX_LIM_CH0_V  0x1FF
+#define RMT_TX_LIM_CH0_S  0
+
+#define RMT_CH1_TX_LIM_REG          (DR_REG_RMT_BASE + 0x005c)
+/* RMT_LOOP_COUNT_RESET_CH1 : WT ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RMT_LOOP_COUNT_RESET_CH1  (BIT(20))
+#define RMT_LOOP_COUNT_RESET_CH1_M  (BIT(20))
+#define RMT_LOOP_COUNT_RESET_CH1_V  0x1
+#define RMT_LOOP_COUNT_RESET_CH1_S  20
+/* RMT_TX_LOOP_CNT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_CNT_EN_CH1  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH1_M  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH1_V  0x1
+#define RMT_TX_LOOP_CNT_EN_CH1_S  19
+/* RMT_TX_LOOP_NUM_CH1 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_NUM_CH1  0x000003FF
+#define RMT_TX_LOOP_NUM_CH1_M  ((RMT_TX_LOOP_NUM_CH1_V)<<(RMT_TX_LOOP_NUM_CH1_S))
+#define RMT_TX_LOOP_NUM_CH1_V  0x3FF
+#define RMT_TX_LOOP_NUM_CH1_S  9
+/* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: */
+#define RMT_TX_LIM_CH1  0x000001FF
+#define RMT_TX_LIM_CH1_M  ((RMT_TX_LIM_CH1_V)<<(RMT_TX_LIM_CH1_S))
+#define RMT_TX_LIM_CH1_V  0x1FF
+#define RMT_TX_LIM_CH1_S  0
+
+#define RMT_CH2_RX_LIM_REG          (DR_REG_RMT_BASE + 0x0060)
+/* RMT_RX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: */
+#define RMT_RX_LIM_CH2  0x000001FF
+#define RMT_RX_LIM_CH2_M  ((RMT_RX_LIM_CH2_V)<<(RMT_RX_LIM_CH2_S))
+#define RMT_RX_LIM_CH2_V  0x1FF
+#define RMT_RX_LIM_CH2_S  0
+
+#define RMT_CH3_RX_LIM_REG          (DR_REG_RMT_BASE + 0x0064)
+/* RMT_RX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: */
+#define RMT_RX_LIM_CH3  0x000001FF
+#define RMT_RX_LIM_CH3_M  ((RMT_RX_LIM_CH3_V)<<(RMT_RX_LIM_CH3_S))
+#define RMT_RX_LIM_CH3_V  0x1FF
+#define RMT_RX_LIM_CH3_S  0
+
+#define RMT_SYS_CONF_REG          (DR_REG_RMT_BASE + 0x0068)
+/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define RMT_CLK_EN  (BIT(31))
+#define RMT_CLK_EN_M  (BIT(31))
+#define RMT_CLK_EN_V  0x1
+#define RMT_CLK_EN_S  31
+/* RMT_SCLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'h1 ; */
+/*description: */
+#define RMT_SCLK_ACTIVE  (BIT(26))
+#define RMT_SCLK_ACTIVE_M  (BIT(26))
+#define RMT_SCLK_ACTIVE_V  0x1
+#define RMT_SCLK_ACTIVE_S  26
+/* RMT_SCLK_SEL : R/W ;bitpos:[25:24] ;default: 2'h1 ; */
+/*description: */
+#define RMT_SCLK_SEL  0x00000003
+#define RMT_SCLK_SEL_M  ((RMT_SCLK_SEL_V)<<(RMT_SCLK_SEL_S))
+#define RMT_SCLK_SEL_V  0x3
+#define RMT_SCLK_SEL_S  24
+/* RMT_SCLK_DIV_B : R/W ;bitpos:[23:18] ;default: 6'h0 ; */
+/*description: */
+#define RMT_SCLK_DIV_B  0x0000003F
+#define RMT_SCLK_DIV_B_M  ((RMT_SCLK_DIV_B_V)<<(RMT_SCLK_DIV_B_S))
+#define RMT_SCLK_DIV_B_V  0x3F
+#define RMT_SCLK_DIV_B_S  18
+/* RMT_SCLK_DIV_A : R/W ;bitpos:[17:12] ;default: 6'h0 ; */
+/*description: */
+#define RMT_SCLK_DIV_A  0x0000003F
+#define RMT_SCLK_DIV_A_M  ((RMT_SCLK_DIV_A_V)<<(RMT_SCLK_DIV_A_S))
+#define RMT_SCLK_DIV_A_V  0x3F
+#define RMT_SCLK_DIV_A_S  12
+/* RMT_SCLK_DIV_NUM : R/W ;bitpos:[11:4] ;default: 8'h1 ; */
+/*description: */
+#define RMT_SCLK_DIV_NUM  0x000000FF
+#define RMT_SCLK_DIV_NUM_M  ((RMT_SCLK_DIV_NUM_V)<<(RMT_SCLK_DIV_NUM_S))
+#define RMT_SCLK_DIV_NUM_V  0xFF
+#define RMT_SCLK_DIV_NUM_S  4
+/* RMT_MEM_FORCE_PU : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_FORCE_PU  (BIT(3))
+#define RMT_MEM_FORCE_PU_M  (BIT(3))
+#define RMT_MEM_FORCE_PU_V  0x1
+#define RMT_MEM_FORCE_PU_S  3
+/* RMT_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_FORCE_PD  (BIT(2))
+#define RMT_MEM_FORCE_PD_M  (BIT(2))
+#define RMT_MEM_FORCE_PD_V  0x1
+#define RMT_MEM_FORCE_PD_S  2
+/* RMT_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_CLK_FORCE_ON  (BIT(1))
+#define RMT_MEM_CLK_FORCE_ON_M  (BIT(1))
+#define RMT_MEM_CLK_FORCE_ON_V  0x1
+#define RMT_MEM_CLK_FORCE_ON_S  1
+/* RMT_APB_FIFO_MASK : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define RMT_APB_FIFO_MASK  (BIT(0))
+#define RMT_APB_FIFO_MASK_M  (BIT(0))
+#define RMT_APB_FIFO_MASK_V  0x1
+#define RMT_APB_FIFO_MASK_S  0
+
+#define RMT_TX_SIM_REG          (DR_REG_RMT_BASE + 0x006c)
+/* RMT_TX_SIM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_SIM_EN  (BIT(2))
+#define RMT_TX_SIM_EN_M  (BIT(2))
+#define RMT_TX_SIM_EN_V  0x1
+#define RMT_TX_SIM_EN_S  2
+/* RMT_TX_SIM_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_SIM_CH1  (BIT(1))
+#define RMT_TX_SIM_CH1_M  (BIT(1))
+#define RMT_TX_SIM_CH1_V  0x1
+#define RMT_TX_SIM_CH1_S  1
+/* RMT_TX_SIM_CH0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_SIM_CH0  (BIT(0))
+#define RMT_TX_SIM_CH0_M  (BIT(0))
+#define RMT_TX_SIM_CH0_V  0x1
+#define RMT_TX_SIM_CH0_S  0
+
+#define RMT_REF_CNT_RST_REG          (DR_REG_RMT_BASE + 0x0070)
+/* RMT_REF_CNT_RST_CH3 : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RMT_REF_CNT_RST_CH3  (BIT(3))
+#define RMT_REF_CNT_RST_CH3_M  (BIT(3))
+#define RMT_REF_CNT_RST_CH3_V  0x1
+#define RMT_REF_CNT_RST_CH3_S  3
+/* RMT_REF_CNT_RST_CH2 : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RMT_REF_CNT_RST_CH2  (BIT(2))
+#define RMT_REF_CNT_RST_CH2_M  (BIT(2))
+#define RMT_REF_CNT_RST_CH2_V  0x1
+#define RMT_REF_CNT_RST_CH2_S  2
+/* RMT_REF_CNT_RST_CH1 : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RMT_REF_CNT_RST_CH1  (BIT(1))
+#define RMT_REF_CNT_RST_CH1_M  (BIT(1))
+#define RMT_REF_CNT_RST_CH1_V  0x1
+#define RMT_REF_CNT_RST_CH1_S  1
+/* RMT_REF_CNT_RST_CH0 : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define RMT_REF_CNT_RST_CH0  (BIT(0))
+#define RMT_REF_CNT_RST_CH0_M  (BIT(0))
+#define RMT_REF_CNT_RST_CH0_V  0x1
+#define RMT_REF_CNT_RST_CH0_S  0
+
+#define RMT_DATE_REG          (DR_REG_RMT_BASE + 0x00cc)
+/* RMT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006231 ; */
+/*description: */
+#define RMT_DATE  0x0FFFFFFF
+#define RMT_DATE_M  ((RMT_DATE_V)<<(RMT_DATE_S))
+#define RMT_DATE_V  0xFFFFFFF
+#define RMT_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_RMT_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/rmt_struct.h b/components/soc/esp32c3/include/soc/rmt_struct.h
new file mode 100644
index 0000000000..7fc1890b12
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/rmt_struct.h
@@ -0,0 +1,308 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_RMT_STRUCT_H_
+#define _SOC_RMT_STRUCT_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    uint32_t data_ch[4];                                   /**/
+    union {
+        struct {
+            uint32_t tx_start:           1;
+            uint32_t mem_rd_rst:         1;
+            uint32_t mem_rst:            1;
+            uint32_t tx_conti_mode:      1;
+            uint32_t mem_tx_wrap_en:     1;
+            uint32_t idle_out_lv:        1;
+            uint32_t idle_out_en:        1;
+            uint32_t tx_stop:            1;
+            uint32_t div_cnt:            8;
+            uint32_t mem_size:           3;
+            uint32_t reserved19:         1;
+            uint32_t carrier_eff_en:     1;
+            uint32_t carrier_en:         1;
+            uint32_t carrier_out_lv:     1;
+            uint32_t afifo_rst:          1;
+            uint32_t conf_update:        1;
+            uint32_t reserved25:         7;
+        };
+        uint32_t val;
+    } tx_conf[2];
+    struct {
+        union {
+            struct {
+                uint32_t div_cnt:            8;
+                uint32_t idle_thres:        15;
+                uint32_t mem_size:           3;
+                uint32_t reserved26:         2;
+                uint32_t carrier_en:         1;
+                uint32_t carrier_out_lv:     1;
+                uint32_t reserved30:         2;
+            };
+            uint32_t val;
+        } conf0;
+        union {
+            struct {
+                uint32_t rx_en:               1;
+                uint32_t mem_wr_rst:          1;
+                uint32_t mem_rst:             1;
+                uint32_t mem_owner:           1;
+                uint32_t rx_filter_en:        1;
+                uint32_t rx_filter_thres:     8;
+                uint32_t mem_rx_wrap_en:      1;
+                uint32_t afifo_rst:           1;
+                uint32_t conf_update:         1;
+                uint32_t reserved16:         16;
+            };
+            uint32_t val;
+        } conf1;
+    } rx_conf[2];
+    union {
+        struct {
+            uint32_t mem_raddr_ex:       9;
+            uint32_t state:              3;
+            uint32_t waddr:              9;
+            uint32_t mem_rd_err:         1;
+            uint32_t mem_empty:          1;
+            uint32_t mem_wr_err:         1;
+            uint32_t raddr:              8;
+        };
+        uint32_t val;
+    } tx_status[2];
+    union {
+        struct {
+            uint32_t mem_waddr_ex:       9;
+            uint32_t reserved9:          3;
+            uint32_t mem_raddr:          9;
+            uint32_t reserved21:         1;
+            uint32_t state:              3;
+            uint32_t mem_owner_err:      1;
+            uint32_t mem_full:           1;
+            uint32_t mem_rd_err:         1;
+            uint32_t reserved28:         4;
+        };
+        uint32_t val;
+    } rx_status[2];
+    union {
+        struct {
+            uint32_t ch0_tx_end:               1;
+            uint32_t ch1_tx_end:               1;
+            uint32_t ch2_rx_end:               1;
+            uint32_t ch3_rx_end:               1;
+            uint32_t ch0_err:                  1;
+            uint32_t ch1_err:                  1;
+            uint32_t ch2_err:                  1;
+            uint32_t ch3_err:                  1;
+            uint32_t ch0_tx_thr_event:         1;
+            uint32_t ch1_tx_thr_event:         1;
+            uint32_t ch2_rx_thr_event:         1;
+            uint32_t ch3_rx_thr_event:         1;
+            uint32_t ch0_tx_loop:              1;
+            uint32_t ch1_tx_loop:              1;
+            uint32_t reserved14:              18;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t ch0_tx_end:              1;
+            uint32_t ch1_tx_end:              1;
+            uint32_t ch2_rx_end:              1;
+            uint32_t ch3_rx_end:              1;
+            uint32_t ch0_err:                 1;
+            uint32_t ch1_err:                 1;
+            uint32_t ch2_err:                 1;
+            uint32_t ch3_err:                 1;
+            uint32_t ch0_tx_thr_event:        1;
+            uint32_t ch1_tx_thr_event:        1;
+            uint32_t ch2_rx_thr_event:        1;
+            uint32_t ch3_rx_thr_event:        1;
+            uint32_t ch0_tx_loop:             1;
+            uint32_t ch1_tx_loop:             1;
+            uint32_t reserved14:             18;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t ch0_tx_end:               1;
+            uint32_t ch1_tx_end:               1;
+            uint32_t ch2_rx_end:               1;
+            uint32_t ch3_rx_end:               1;
+            uint32_t ch0_err:                  1;
+            uint32_t ch1_err:                  1;
+            uint32_t ch2_err:                  1;
+            uint32_t ch3_err:                  1;
+            uint32_t ch0_tx_thr_event:         1;
+            uint32_t ch1_tx_thr_event:         1;
+            uint32_t ch2_rx_thr_event:         1;
+            uint32_t ch3_rx_thr_event:         1;
+            uint32_t ch0_tx_loop:              1;
+            uint32_t ch1_tx_loop:              1;
+            uint32_t reserved14:              18;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t ch0_tx_end:               1;
+            uint32_t ch1_tx_end:               1;
+            uint32_t ch2_rx_end:               1;
+            uint32_t ch3_rx_end:               1;
+            uint32_t ch0_err:                  1;
+            uint32_t ch1_err:                  1;
+            uint32_t ch2_err:                  1;
+            uint32_t ch3_err:                  1;
+            uint32_t ch0_tx_thr_event:         1;
+            uint32_t ch1_tx_thr_event:         1;
+            uint32_t ch2_rx_thr_event:         1;
+            uint32_t ch3_rx_thr_event:         1;
+            uint32_t ch0_tx_loop:              1;
+            uint32_t ch1_tx_loop:              1;
+            uint32_t reserved14:              18;
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t low:             16;
+            uint32_t high:            16;
+        };
+        uint32_t val;
+    } tx_carrier[2];
+    union {
+        struct {
+            uint32_t low_thres:             16;
+            uint32_t high_thres:            16;
+        };
+        uint32_t val;
+    } rx_carrier[2];
+    union {
+        struct {
+            uint32_t limit:                9;
+            uint32_t tx_loop_num:         10;
+            uint32_t tx_loop_cnt_en:       1;
+            uint32_t loop_count_reset:     1;
+            uint32_t reserved21:          11;
+        };
+        uint32_t val;
+    } tx_lim[2];
+    union {
+        struct {
+            uint32_t rx_lim:     9;
+            uint32_t reserved9: 23;
+        };
+        uint32_t val;
+    } rx_lim[2];
+    union {
+        struct {
+            uint32_t fifo_mask:        1;
+            uint32_t mem_clk_force_on: 1;
+            uint32_t mem_force_pd:     1;
+            uint32_t mem_force_pu:     1;
+            uint32_t sclk_div_num:     8;
+            uint32_t sclk_div_a:       6;
+            uint32_t sclk_div_b:       6;
+            uint32_t sclk_sel:         2;
+            uint32_t sclk_active:      1;
+            uint32_t reserved27:       4;
+            uint32_t clk_en:           1;
+        };
+        uint32_t val;
+    } sys_conf;
+    union {
+        struct {
+            uint32_t ch0:        1;
+            uint32_t ch1:        1;
+            uint32_t en:         1;
+            uint32_t reserved3: 29;
+        };
+        uint32_t val;
+    } tx_sim;
+    union {
+        struct {
+            uint32_t ch0:             1;
+            uint32_t ch1:             1;
+            uint32_t ch2:             1;
+            uint32_t ch3:             1;
+            uint32_t reserved4:      28;
+        };
+        uint32_t val;
+    } ref_cnt_rst;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    union {
+        struct {
+            uint32_t date:      28;
+            uint32_t reserved28: 4;
+        };
+        uint32_t val;
+    } date;
+} rmt_dev_t;
+
+extern rmt_dev_t RMT;
+
+typedef struct {
+    union {
+        struct {
+            uint32_t duration0 : 15;
+            uint32_t level0 : 1;
+            uint32_t duration1 : 15;
+            uint32_t level1 : 1;
+        };
+        uint32_t val;
+    };
+} rmt_item32_t;
+
+//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
+typedef volatile struct {
+    struct {
+        union {
+            rmt_item32_t data32[48];
+        };
+    } chan[4];
+} rmt_mem_t;
+
+extern rmt_mem_t RMTMEM;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_RMT_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/rsa_caps.h b/components/soc/esp32c3/include/soc/rsa_caps.h
new file mode 100644
index 0000000000..68504242f7
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/rsa_caps.h
@@ -0,0 +1,26 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define SOC_RSA_MAX_BIT_LEN    (3072)
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/include/soc/rtc.h b/components/soc/esp32c3/include/soc/rtc.h
new file mode 100644
index 0000000000..ed650f4950
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/rtc.h
@@ -0,0 +1,785 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @file rtc.h
+ * @brief Low-level RTC power, clock, and sleep functions.
+ *
+ * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
+ * RTC_CNTL peripheral handles many functions:
+ * - enables/disables clocks and power to various parts of the chip; this is
+ *   done using direct register access (forcing power up or power down) or by
+ *   allowing state machines to control power and clocks automatically
+ * - handles sleep and wakeup functions
+ * - maintains a 48-bit counter which can be used for timekeeping
+ *
+ * These functions are not thread safe, and should not be viewed as high level
+ * APIs. For example, while this file provides a function which can switch
+ * CPU frequency, this function is on its own is not sufficient to implement
+ * frequency switching in ESP-IDF context: some coordination with RTOS,
+ * peripheral drivers, and WiFi/BT stacks is also required.
+ *
+ * These functions will normally not be used in applications directly.
+ * ESP-IDF provides, or will provide, drivers and other facilities to use
+ * RTC subsystem functionality.
+ *
+ * The functions are loosely split into the following groups:
+ * - rtc_clk: clock switching, calibration
+ * - rtc_time: reading RTC counter, conversion between counter values and time
+ * - rtc_sleep: entry into sleep modes
+ * - rtc_init: initialization
+ */
+
+#define MHZ (1000000)
+
+#define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles)  (cycles << 12)
+#define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles)  (cycles << 12)
+#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles)  (cycles << 10)
+
+#define RTC_SLOW_CLK_FREQ_90K      90000
+#define RTC_SLOW_CLK_FREQ_8MD256    (RTC_FAST_CLK_FREQ_APPROX / 256)
+#define RTC_SLOW_CLK_FREQ_32K       32768
+
+#define OTHER_BLOCKS_POWERUP        1
+#define OTHER_BLOCKS_WAIT           1
+
+/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
+ * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
+ * Valid if RTC_CNTL_DBG_ATTEN is 0.
+ */
+#define RTC_CNTL_DBIAS_1V00 0
+#define RTC_CNTL_DBIAS_1V05 4
+#define RTC_CNTL_DBIAS_1V10 5
+#define RTC_CNTL_DBIAS_1V15 6
+#define RTC_CNTL_DBIAS_1V20 7
+
+#define DELAY_FAST_CLK_SWITCH           3
+#define DELAY_SLOW_CLK_SWITCH           300
+#define DELAY_8M_ENABLE                 50
+
+/* Number of 8M/256 clock cycles to use for XTAL frequency estimation.
+ * 10 cycles will take approximately 300 microseconds.
+ */
+#define XTAL_FREQ_EST_CYCLES            10
+
+/* Core voltage needs to be increased in two cases:
+ * 1. running at 240 MHz
+ * 2. running with 80MHz Flash frequency
+ */
+#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M
+#define DIG_DBIAS_80M_160M  RTC_CNTL_DBIAS_1V25
+#else
+#define DIG_DBIAS_80M_160M  RTC_CNTL_DBIAS_1V10
+#endif
+#define DIG_DBIAS_XTAL      RTC_CNTL_DBIAS_1V10
+#define DIG_DBIAS_2M        RTC_CNTL_DBIAS_1V00
+
+#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT  20
+#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT  100
+#define RTC_CNTL_CK8M_WAIT_DEFAULT  20
+#define RTC_CK8M_ENABLE_WAIT_DEFAULT 1
+
+#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172
+#define RTC_CNTL_SCK_DCAP_DEFAULT   255
+
+/*
+set sleep_init default param
+*/
+#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT  6
+#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT  15
+#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT  0
+#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT  0
+#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT  1
+#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT  0
+#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT  1
+
+#define APLL_SDM_STOP_VAL_1         0x09
+#define APLL_SDM_STOP_VAL_2_REV0    0x69
+#define APLL_SDM_STOP_VAL_2_REV1    0x49
+#define APLL_CAL_DELAY_1            0x0f
+#define APLL_CAL_DELAY_2            0x3f
+#define APLL_CAL_DELAY_3            0x1f
+
+/**
+ * @brief Possible main XTAL frequency values.
+ *
+ * Enum values should be equal to frequency in MHz.
+ */
+typedef enum {
+    RTC_XTAL_FREQ_40M = 40,     //!< 40 MHz XTAL
+} rtc_xtal_freq_t;
+
+/**
+ * @brief CPU frequency values
+ */
+typedef enum {
+    RTC_CPU_FREQ_XTAL = 0,      //!< Main XTAL frequency
+    RTC_CPU_FREQ_80M = 1,       //!< 80 MHz
+    RTC_CPU_FREQ_160M = 2,      //!< 160 MHz
+    RTC_CPU_FREQ_240M = 3,      //!< 240 MHz
+    RTC_CPU_FREQ_2M = 4,        //!< 2 MHz
+    RTC_CPU_320M_80M = 5,       //!< for test
+    RTC_CPU_320M_160M = 6,      //!< for test
+    RTC_CPU_FREQ_XTAL_DIV2 = 7, //!< XTAL/2 after reset
+} rtc_cpu_freq_t;
+
+/**
+ * @brief CPU clock source
+ */
+typedef enum {
+    RTC_CPU_FREQ_SRC_XTAL,  //!< XTAL
+    RTC_CPU_FREQ_SRC_PLL,   //!< PLL (480M or 320M)
+    RTC_CPU_FREQ_SRC_8M,    //!< Internal 8M RTC oscillator
+    RTC_CPU_FREQ_SRC_APLL   //!< APLL
+} rtc_cpu_freq_src_t;
+
+/**
+ * @brief CPU clock configuration structure
+ */
+typedef struct rtc_cpu_freq_config_s {
+    rtc_cpu_freq_src_t source;      //!< The clock from which CPU clock is derived
+    uint32_t source_freq_mhz;       //!< Source clock frequency
+    uint32_t div;                   //!< Divider, freq_mhz = source_freq_mhz / div
+    uint32_t freq_mhz;              //!< CPU clock frequency
+} rtc_cpu_freq_config_t;
+
+/**
+ * @brief RTC SLOW_CLK frequency values
+ */
+typedef enum {
+    RTC_SLOW_FREQ_RTC = 0,      //!< Internal 150 kHz RC oscillator
+    RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL
+    RTC_SLOW_FREQ_8MD256 = 2,   //!< Internal 8 MHz RC oscillator, divided by 256
+} rtc_slow_freq_t;
+
+/**
+ * @brief RTC FAST_CLK frequency values
+ */
+typedef enum {
+    RTC_FAST_FREQ_XTALD4 = 0,   //!< Main XTAL, divided by 4
+    RTC_FAST_FREQ_8M = 1,       //!< Internal 8 MHz RC oscillator
+} rtc_fast_freq_t;
+
+/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */
+#define RTC_FAST_CLK_FREQ_APPROX 8500000
+
+#define RTC_CLK_CAL_FRACT  19  //!< Number of fractional bits in values returned by rtc_clk_cal
+
+#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
+#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
+
+/**
+ * @brief Clock source to be calibrated using rtc_clk_cal function
+ */
+typedef enum {
+    RTC_CAL_RTC_MUX = 0,       //!< Currently selected RTC SLOW_CLK
+    RTC_CAL_8MD256 = 1,        //!< Internal 8 MHz RC oscillator, divided by 256
+    RTC_CAL_32K_XTAL = 2       //!< External 32 kHz XTAL
+} rtc_cal_sel_t;
+
+/**
+ * Initialization parameters for rtc_clk_init
+ */
+typedef struct {
+    rtc_xtal_freq_t xtal_freq : 8;  //!< Main XTAL frequency
+    uint32_t cpu_freq_mhz : 10;    //!< CPU frequency to set, in MHz
+    rtc_fast_freq_t fast_freq : 1;  //!< RTC_FAST_CLK frequency to set
+    rtc_slow_freq_t slow_freq : 2;  //!< RTC_SLOW_CLK frequency to set
+    uint32_t clk_rtc_clk_div : 8;
+    uint32_t clk_8m_clk_div : 3;        //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
+    uint32_t slow_clk_dcap : 8;     //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
+    uint32_t clk_8m_dfreq : 8;      //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
+} rtc_clk_config_t;
+
+/**
+ * Default initializer for rtc_clk_config_t
+ */
+#define RTC_CLK_CONFIG_DEFAULT() { \
+    .xtal_freq = RTC_XTAL_FREQ_40M, \
+    .cpu_freq_mhz = 80, \
+    .fast_freq = RTC_FAST_FREQ_8M, \
+    .slow_freq = RTC_SLOW_FREQ_RTC, \
+    .clk_rtc_clk_div = 0, \
+    .clk_8m_clk_div = 0, \
+    .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
+    .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
+}
+
+typedef struct {
+    uint32_t dac : 6;
+    uint32_t dres : 3;
+    uint32_t dgm : 3;
+    uint32_t dbuf: 1;
+} x32k_config_t;
+
+#define X32K_CONFIG_DEFAULT() { \
+    .dac = 1, \
+    .dres = 3, \
+    .dgm = 0, \
+    .dbuf = 1, \
+}
+
+typedef struct {
+    uint16_t wifi_powerup_cycles : 7;
+    uint16_t wifi_wait_cycles : 9;
+    uint16_t rtc_powerup_cycles : 7;
+    uint16_t rtc_wait_cycles : 9;
+    uint16_t dg_wrap_powerup_cycles : 7;
+    uint16_t dg_wrap_wait_cycles : 9;
+    uint16_t rtc_mem_powerup_cycles : 7;
+    uint16_t rtc_mem_wait_cycles : 9;
+} rtc_init_config_t;
+
+#define RTC_INIT_CONFIG_DEFAULT() { \
+    .wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \
+    .wifi_wait_cycles = OTHER_BLOCKS_WAIT, \
+    .rtc_powerup_cycles = OTHER_BLOCKS_POWERUP, \
+    .rtc_wait_cycles = OTHER_BLOCKS_WAIT, \
+    .dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \
+    .dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \
+    .rtc_mem_powerup_cycles = OTHER_BLOCKS_POWERUP, \
+    .rtc_mem_wait_cycles = OTHER_BLOCKS_WAIT, \
+}
+
+void rtc_clk_divider_set(uint32_t div);
+
+void rtc_clk_8m_divider_set(uint32_t div);
+
+/**
+ * Initialize clocks and set CPU frequency
+ *
+ * @param cfg clock configuration as rtc_clk_config_t
+ */
+void rtc_clk_init(rtc_clk_config_t cfg);
+
+/**
+ * @brief Get main XTAL frequency
+ *
+ * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
+ * rtc_clk_init function
+ *
+ * @return XTAL frequency, one of rtc_xtal_freq_t
+ */
+rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
+
+/**
+ * @brief Update XTAL frequency
+ *
+ * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored
+ * after startup.
+ *
+ * @param xtal_freq New frequency value
+ */
+void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
+
+/**
+ * @brief Enable or disable 32 kHz XTAL oscillator
+ * @param en  true to enable, false to disable
+ */
+void rtc_clk_32k_enable(bool en);
+
+/**
+ * @brief Configure 32 kHz XTAL oscillator to accept external clock signal
+ */
+void rtc_clk_32k_enable_external(void);
+
+/**
+ * @brief Get the state of 32k XTAL oscillator
+ * @return true if 32k XTAL oscillator has been enabled
+ */
+bool rtc_clk_32k_enabled(void);
+
+/**
+ * @brief Enable 32k oscillator, configuring it for fast startup time.
+ * Note: to achieve higher frequency stability, rtc_clk_32k_enable function
+ * must be called one the 32k XTAL oscillator has started up. This function
+ * will initially disable the 32k XTAL oscillator, so it should not be called
+ * when the system is using 32k XTAL as RTC_SLOW_CLK.
+ *
+ * @param cycle Number of 32kHz cycles to bootstrap external crystal.
+ *              If 0, no square wave will be used to bootstrap crystal oscillation.
+ */
+void rtc_clk_32k_bootstrap(uint32_t cycle);
+
+/**
+ * @brief Enable or disable 8 MHz internal oscillator
+ *
+ * Output from 8 MHz internal oscillator is passed into a configurable
+ * divider, which by default divides the input clock frequency by 256.
+ * Output of the divider may be used as RTC_SLOW_CLK source.
+ * Output of the divider is referred to in register descriptions and code as
+ * 8md256 or simply d256. Divider values other than 256 may be configured, but
+ * this facility is not currently needed, so is not exposed in the code.
+ *
+ * When 8MHz/256 divided output is not needed, the divider should be disabled
+ * to reduce power consumption.
+ *
+ * @param clk_8m_en true to enable 8MHz generator
+ * @param d256_en true to enable /256 divider
+ */
+void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
+
+/**
+ * @brief Get the state of 8 MHz internal oscillator
+ * @return true if the oscillator is enabled
+ */
+bool rtc_clk_8m_enabled(void);
+
+/**
+ * @brief Get the state of /256 divider which is applied to 8MHz clock
+ * @return true if the divided output is enabled
+ */
+bool rtc_clk_8md256_enabled(void);
+
+/**
+ * @brief Enable or disable APLL
+ *
+ * Output frequency is given by the formula:
+ * apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2)
+ *
+ * The dividend in this expression should be in the range of 240 - 600 MHz.
+ *
+ * In rev. 0 of ESP32, sdm0 and sdm1 are unused and always set to 0.
+ *
+ * @param enable  true to enable, false to disable
+ * @param sdm0  frequency adjustment parameter, 0..255
+ * @param sdm1  frequency adjustment parameter, 0..255
+ * @param sdm2  frequency adjustment parameter, 0..63
+ * @param o_div  frequency divider, 0..31
+ */
+void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div);
+
+/**
+ * @brief Set XTAL wait cycles by RTC slow clock's period
+ */
+void rtc_clk_set_xtal_wait(void);
+
+/**
+ * @brief Select source for RTC_SLOW_CLK
+ * @param slow_freq clock source (one of rtc_slow_freq_t values)
+ */
+void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq);
+
+/**
+ * @brief Get the RTC_SLOW_CLK source
+ * @return currently selected clock source (one of rtc_slow_freq_t values)
+ */
+rtc_slow_freq_t rtc_clk_slow_freq_get(void);
+
+/**
+ * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
+ *
+ * - if RTC_SLOW_FREQ_RTC is selected, returns ~150000
+ * - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768
+ * - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000
+ *
+ * rtc_clk_cal function can be used to get more precise value by comparing
+ * RTC_SLOW_CLK frequency to the frequency of main XTAL.
+ *
+ * @return RTC_SLOW_CLK frequency, in Hz
+ */
+uint32_t rtc_clk_slow_freq_get_hz(void);
+
+/**
+ * @brief Select source for RTC_FAST_CLK
+ * @param fast_freq clock source (one of rtc_fast_freq_t values)
+ */
+void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq);
+
+/**
+ * @brief Get the RTC_FAST_CLK source
+ * @return currently selected clock source (one of rtc_fast_freq_t values)
+ */
+rtc_fast_freq_t rtc_clk_fast_freq_get(void);
+
+/**
+ * @brief Get CPU frequency config for a given frequency
+ * @param freq_mhz  Frequency in MHz
+ * @param[out] out_config Output, CPU frequency configuration structure
+ * @return true if frequency can be obtained, false otherwise
+ */
+bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config);
+
+/**
+ * @brief Switch CPU frequency
+ *
+ * This function sets CPU frequency according to the given configuration
+ * structure. It enables PLLs, if necessary.
+ *
+ * @note This function in not intended to be called by applications in FreeRTOS
+ * environment. This is because it does not adjust various timers based on the
+ * new CPU frequency.
+ *
+ * @param config  CPU frequency configuration structure
+ */
+void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config);
+
+/**
+ * @brief Switch CPU frequency (optimized for speed)
+ *
+ * This function is a faster equivalent of rtc_clk_cpu_freq_set_config.
+ * It works faster because it does not disable PLLs when switching from PLL to
+ * XTAL and does not enabled them when switching back. If PLL is not already
+ * enabled when this function is called to switch from XTAL to PLL frequency,
+ * or the PLL which is enabled is the wrong one, this function will fall back
+ * to calling rtc_clk_cpu_freq_set_config.
+ *
+ * Unlike rtc_clk_cpu_freq_set_config, this function relies on static data,
+ * so it is less safe to use it e.g. from a panic handler (when memory might
+ * be corrupted).
+ *
+ * @note This function in not intended to be called by applications in FreeRTOS
+ * environment. This is because it does not adjust various timers based on the
+ * new CPU frequency.
+ *
+ * @param config  CPU frequency configuration structure
+ */
+void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config);
+
+/**
+ * @brief Get the currently used CPU frequency configuration
+ * @param[out] out_config  Output, CPU frequency configuration structure
+ */
+void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
+
+/**
+ * @brief Switch CPU clock source to XTAL
+ *
+ * Short form for filling in rtc_cpu_freq_config_t structure and calling
+ * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
+ * Assumes that XTAL frequency has been determined — don't call in startup code.
+ */
+void rtc_clk_cpu_freq_set_xtal(void);
+
+/**
+ * @brief Store new APB frequency value into RTC_APB_FREQ_REG
+ *
+ * This function doesn't change any hardware clocks.
+ *
+ * Functions which perform frequency switching and change APB frequency call
+ * this function to update the value of APB frequency stored in RTC_APB_FREQ_REG
+ * (one of RTC general purpose retention registers). This should not normally
+ * be called from application code.
+ *
+ * @param apb_freq  new APB frequency, in Hz
+ */
+void rtc_clk_apb_freq_update(uint32_t apb_freq);
+
+/**
+ * @brief Get the current stored APB frequency.
+ * @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz.
+ */
+uint32_t rtc_clk_apb_freq_get(void);
+
+uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
+
+/**
+ * @brief Measure RTC slow clock's period, based on main XTAL frequency
+ *
+ * This function will time out and return 0 if the time for the given number
+ * of cycles to be counted exceeds the expected time twice. This may happen if
+ * 32k XTAL is being calibrated, but the oscillator has not started up (due to
+ * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board).
+ *
+ * @param cal_clk  clock to be measured
+ * @param slow_clk_cycles  number of slow clock cycles to average
+ * @return average slow clock period in microseconds, Q13.19 fixed point format,
+ *         or 0 if calibration has timed out
+ */
+uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
+
+/**
+ * @brief Measure ratio between XTAL frequency and RTC slow clock frequency
+ * @param cal_clk slow clock to be measured
+ * @param slow_clk_cycles number of slow clock cycles to average
+ * @return average ratio between XTAL frequency and slow clock frequency,
+ *         Q13.19 fixed point format, or 0 if calibration has timed out.
+ */
+uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
+
+/**
+ * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles
+ * @param time_in_us Time interval in microseconds
+ * @param slow_clk_period  Period of slow clock in microseconds, Q13.19
+ *                         fixed point format (as returned by rtc_slowck_cali).
+ * @return number of slow clock cycles
+ */
+uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period);
+
+/**
+ * @brief Convert time interval from RTC_SLOW_CLK to microseconds
+ * @param time_in_us Time interval in RTC_SLOW_CLK cycles
+ * @param slow_clk_period  Period of slow clock in microseconds, Q13.19
+ *                         fixed point format (as returned by rtc_slowck_cali).
+ * @return time interval in microseconds
+ */
+uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
+
+/**
+ * @brief Get current value of RTC counter
+ *
+ * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK
+ * cycles. Counter value is not writable by software. The value is not adjusted
+ * when switching to a different RTC_SLOW_CLK source.
+ *
+ * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute
+ *
+ * @return current value of RTC counter
+ */
+uint64_t rtc_time_get(void);
+
+uint64_t rtc_light_slp_time_get(void);
+
+uint64_t rtc_deep_slp_time_get(void);
+
+/**
+ * @brief Busy loop until next RTC_SLOW_CLK cycle
+ *
+ * This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
+ * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
+ * one RTC_SLOW_CLK cycle later.
+ */
+void rtc_clk_wait_for_slow_cycle(void);
+
+/**
+ * @brief Power down flags for rtc_sleep_pd function
+ */
+typedef struct {
+    uint32_t dig_fpu : 1;    //!< Set to 1 to power down digital part in sleep
+    uint32_t rtc_fpu : 1;    //!< Set to 1 to power down RTC memories in sleep
+    uint32_t cpu_fpu : 1;    //!< Set to 1 to power down digital memories and CPU in sleep
+    uint32_t i2s_fpu : 1;    //!< Set to 1 to power down I2S in sleep
+    uint32_t bb_fpu : 1;     //!< Set to 1 to power down WiFi in sleep
+    uint32_t nrx_fpu : 1;    //!< Set to 1 to power down WiFi in sleep
+    uint32_t fe_fpu : 1;     //!< Set to 1 to power down WiFi in sleep
+} rtc_sleep_pd_config_t;
+
+/**
+ * Initializer for rtc_sleep_pd_config_t which sets all flags to the same value
+ */
+#define RTC_SLEEP_PD_CONFIG_ALL(val) {\
+    .dig_fpu = (val), \
+    .rtc_fpu = (val), \
+    .cpu_fpu = (val), \
+    .i2s_fpu = (val), \
+    .bb_fpu = (val), \
+    .nrx_fpu = (val), \
+    .fe_fpu = (val), \
+}
+
+void rtc_sleep_pd(rtc_sleep_pd_config_t cfg);
+
+/**
+ * @brief sleep configuration for rtc_sleep_init function
+ */
+typedef struct {
+    uint32_t lslp_mem_inf_fpu : 1;      //!< force normal voltage in sleep mode (digital domain memory)
+    uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if touch is used)
+    uint32_t rtc_fastmem_pd_en : 1;     //!< power down RTC fast memory
+    uint32_t rtc_slowmem_pd_en : 1;     //!< power down RTC slow memory
+    uint32_t rtc_peri_pd_en : 1;        //!< power down RTC peripherals
+    uint32_t wifi_pd_en : 1;            //!< power down WiFi
+    uint32_t deep_slp : 1;              //!< power down digital domain
+    uint32_t wdt_flashboot_mod_en : 1;  //!< enable WDT flashboot mode
+    uint32_t dig_dbias_wak : 3;         //!< set bias for digital domain, in active mode
+    uint32_t dig_dbias_slp : 3;         //!< set bias for digital domain, in sleep mode
+    uint32_t rtc_dbias_wak : 3;         //!< set bias for RTC domain, in active mode
+    uint32_t rtc_dbias_slp : 3;         //!< set bias for RTC domain, in sleep mode
+    uint32_t vddsdio_pd_en : 1;         //!< power down VDDSDIO regulator
+    uint32_t deep_slp_reject : 1;
+    uint32_t light_slp_reject : 1;
+} rtc_sleep_config_t;
+
+/**
+ * Default initializer for rtc_sleep_config_t
+ *
+ * This initializer sets all fields to "reasonable" values (e.g. suggested for
+ * production use) based on a combination of RTC_SLEEP_PD_x flags.
+ *
+ * @param RTC_SLEEP_PD_x flags combined using bitwise OR
+ */
+#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
+    .lslp_mem_inf_fpu = 0, \
+    .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \
+    .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \
+    .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
+    .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
+    .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \
+    .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
+    .wdt_flashboot_mod_en = 0, \
+    .dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10, \
+    .dig_dbias_slp = RTC_CNTL_DIG_DBIAS_0V90, \
+    .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \
+    .rtc_dbias_slp = RTC_CNTL_DBIAS_1V00, \
+    .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
+    .deep_slp_reject = 1, \
+    .light_slp_reject = 1 \
+};
+
+#define RTC_SLEEP_PD_DIG                BIT(0)  //!< Deep sleep (power down digital domain)
+#define RTC_SLEEP_PD_RTC_PERIPH         BIT(1)  //!< Power down RTC peripherals
+#define RTC_SLEEP_PD_RTC_SLOW_MEM       BIT(2)  //!< Power down RTC SLOW memory
+#define RTC_SLEEP_PD_RTC_FAST_MEM       BIT(3)  //!< Power down RTC FAST memory
+#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4)  //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
+#define RTC_SLEEP_PD_VDDSDIO            BIT(5)  //!< Power down VDDSDIO regulator
+#define RTC_SLEEP_PD_WIFI               BIT(6)
+
+/**
+ * @brief Prepare the chip to enter sleep mode
+ *
+ * This function configures various power control state machines to handle
+ * entry into light sleep or deep sleep mode, switches APB and CPU clock source
+ * (usually to XTAL), and sets bias voltages for digital and RTC power domains.
+ *
+ * This function does not actually enter sleep mode; this is done using
+ * rtc_sleep_start function. Software may do some other actions between
+ * rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure
+ * wakeup sources.
+ * @param cfg sleep mode configuration
+ */
+void rtc_sleep_init(rtc_sleep_config_t cfg);
+
+
+/**
+ * @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source
+ * @param t value of RTC counter at which wakeup from sleep will happen;
+ *          only the lower 48 bits are used
+ */
+void rtc_sleep_set_wakeup_time(uint64_t t);
+
+
+#define RTC_EXT0_TRIG_EN    BIT(0)  //!< EXT0 GPIO wakeup
+#define RTC_EXT1_TRIG_EN    BIT(1)  //!< EXT1 GPIO wakeup
+#define RTC_GPIO_TRIG_EN    BIT(2)  //!< GPIO wakeup (light sleep only)
+#define RTC_TIMER_TRIG_EN   BIT(3)  //!< Timer wakeup
+#define RTC_SDIO_TRIG_EN    BIT(4)  //!< SDIO wakeup (light sleep only)
+#define RTC_MAC_TRIG_EN     BIT(5)  //!< MAC wakeup (light sleep only)
+#define RTC_UART0_TRIG_EN   BIT(6)  //!< UART0 wakeup (light sleep only)
+#define RTC_UART1_TRIG_EN   BIT(7)  //!< UART1 wakeup (light sleep only)
+#define RTC_TOUCH_TRIG_EN   BIT(8)  //!< Touch wakeup
+#define RTC_BT_TRIG_EN      BIT(10) //!< BT wakeup (light sleep only)
+#define RTC_COCPU_TRIG_EN   BIT(11)
+#define RTC_XTAL32K_DEAD_TRIG_EN    BIT(12)
+#define RTC_COCPU_TRAP_TRIG_EN      BIT(13)
+#define RTC_USB_TRIG_EN             BIT(14)
+
+/**
+ * @brief Enter deep or light sleep mode
+ *
+ * This function enters the sleep mode previously configured using rtc_sleep_init
+ * function. Before entering sleep, software should configure wake up sources
+ * appropriately (set up GPIO wakeup registers, timer wakeup registers,
+ * and so on).
+ *
+ * If deep sleep mode was configured using rtc_sleep_init, and sleep is not
+ * rejected by hardware (based on reject_opt flags), this function never returns.
+ * When the chip wakes up from deep sleep, CPU is reset and execution starts
+ * from ROM bootloader.
+ *
+ * If light sleep mode was configured using rtc_sleep_init, this function
+ * returns on wakeup, or if sleep is rejected by hardware.
+ *
+ * @param wakeup_opt  bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags
+ *                    combined with OR)
+ * @param reject_opt  bit mask of sleep reject reasons:
+ *                      - RTC_CNTL_GPIO_REJECT_EN
+ *                      - RTC_CNTL_SDIO_REJECT_EN
+ *                    These flags are used to prevent entering sleep when e.g.
+ *                    an external host is communicating via SDIO slave
+ * @return non-zero if sleep was rejected by hardware
+ */
+uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu);
+
+/**
+ * RTC power and clock control initialization settings
+ */
+typedef struct {
+    uint32_t ck8m_wait : 8;         //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
+    uint32_t xtal_wait : 8;         //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
+    uint32_t pll_wait : 8;          //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
+    uint32_t clkctl_init : 1;       //!< Perform clock control related initialization
+    uint32_t pwrctl_init : 1;       //!< Perform power control related initialization
+    uint32_t rtc_dboost_fpd : 1;    //!< Force power down RTC_DBOOST
+    uint32_t xtal_fpu : 1;
+    uint32_t bbpll_fpu : 1;
+    uint32_t cpu_waiti_clk_gate : 1;
+} rtc_config_t;
+
+/**
+ * Default initializer of rtc_config_t.
+ *
+ * This initializer sets all fields to "reasonable" values (e.g. suggested for
+ * production use).
+ */
+#define RTC_CONFIG_DEFAULT() {\
+    .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \
+    .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \
+    .pll_wait  = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \
+    .clkctl_init = 1, \
+    .pwrctl_init = 1, \
+    .rtc_dboost_fpd = 1, \
+    .xtal_fpu = 0, \
+    .bbpll_fpu = 0, \
+    .cpu_waiti_clk_gate = 1\
+}
+
+/**
+ * Initialize RTC clock and power control related functions
+ * @param cfg configuration options as rtc_config_t
+ */
+void rtc_init(rtc_config_t cfg);
+
+/**
+ * Structure describing vddsdio configuration
+ */
+typedef struct {
+    uint32_t force : 1;     //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins.
+    uint32_t enable : 1;    //!< Enable VDDSDIO regulator
+    uint32_t tieh  : 1;     //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V
+    uint32_t drefh : 2;     //!< Tuning parameter for VDDSDIO regulator
+    uint32_t drefm : 2;     //!< Tuning parameter for VDDSDIO regulator
+    uint32_t drefl : 2;     //!< Tuning parameter for VDDSDIO regulator
+} rtc_vddsdio_config_t;
+
+/**
+ * Get current VDDSDIO configuration
+ * If VDDSDIO configuration is overridden by RTC, get values from RTC
+ * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE
+ * Otherwise, use default values and the level of MTDI bootstrapping pin.
+ * @return currently used VDDSDIO configuration
+ */
+rtc_vddsdio_config_t rtc_vddsdio_get_config(void);
+
+/**
+ * Set new VDDSDIO configuration using RTC registers.
+ * If config.force == 1, this overrides configuration done using bootstrapping
+ * pins and EFUSE.
+ *
+ * @param config new VDDSDIO configuration
+ */
+void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h b/components/soc/esp32c3/include/soc/rtc_cntl_reg.h
new file mode 100644
index 0000000000..ceab298f26
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/rtc_cntl_reg.h
@@ -0,0 +1,2662 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_RTC_CNTL_REG_H_
+#define _SOC_RTC_CNTL_REG_H_
+
+/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
+#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
+/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */
+#define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A
+
+/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
+#define RTC_WDT_RESET_LENGTH_100_NS    0
+#define RTC_WDT_RESET_LENGTH_200_NS    1
+#define RTC_WDT_RESET_LENGTH_300_NS    2
+#define RTC_WDT_RESET_LENGTH_400_NS    3
+#define RTC_WDT_RESET_LENGTH_500_NS    4
+#define RTC_WDT_RESET_LENGTH_800_NS    5
+#define RTC_WDT_RESET_LENGTH_1600_NS   6
+#define RTC_WDT_RESET_LENGTH_3200_NS   7
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define RTC_CNTL_TIME0_REG		RTC_CNTL_TIME_LOW0_REG
+#define RTC_CNTL_TIME1_REG		RTC_CNTL_TIME_HIGH0_REG
+
+#define RTC_CNTL_OPTIONS0_REG          (DR_REG_RTCCNTL_BASE + 0x0000)
+/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */
+/*description: SW system reset*/
+#define RTC_CNTL_SW_SYS_RST  (BIT(31))
+#define RTC_CNTL_SW_SYS_RST_M  (BIT(31))
+#define RTC_CNTL_SW_SYS_RST_V  0x1
+#define RTC_CNTL_SW_SYS_RST_S  31
+/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: digital core force no reset in deep sleep*/
+#define RTC_CNTL_DG_WRAP_FORCE_NORST  (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_M  (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_S  30
+/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: digital wrap force reset in deep sleep*/
+#define RTC_CNTL_DG_WRAP_FORCE_RST  (BIT(29))
+#define RTC_CNTL_DG_WRAP_FORCE_RST_M  (BIT(29))
+#define RTC_CNTL_DG_WRAP_FORCE_RST_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_RST_S  29
+/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_ANALOG_FORCE_NOISO  (BIT(28))
+#define RTC_CNTL_ANALOG_FORCE_NOISO_M  (BIT(28))
+#define RTC_CNTL_ANALOG_FORCE_NOISO_V  0x1
+#define RTC_CNTL_ANALOG_FORCE_NOISO_S  28
+/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_PLL_FORCE_NOISO  (BIT(27))
+#define RTC_CNTL_PLL_FORCE_NOISO_M  (BIT(27))
+#define RTC_CNTL_PLL_FORCE_NOISO_V  0x1
+#define RTC_CNTL_PLL_FORCE_NOISO_S  27
+/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_XTL_FORCE_NOISO  (BIT(26))
+#define RTC_CNTL_XTL_FORCE_NOISO_M  (BIT(26))
+#define RTC_CNTL_XTL_FORCE_NOISO_V  0x1
+#define RTC_CNTL_XTL_FORCE_NOISO_S  26
+/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_ANALOG_FORCE_ISO  (BIT(25))
+#define RTC_CNTL_ANALOG_FORCE_ISO_M  (BIT(25))
+#define RTC_CNTL_ANALOG_FORCE_ISO_V  0x1
+#define RTC_CNTL_ANALOG_FORCE_ISO_S  25
+/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_PLL_FORCE_ISO  (BIT(24))
+#define RTC_CNTL_PLL_FORCE_ISO_M  (BIT(24))
+#define RTC_CNTL_PLL_FORCE_ISO_V  0x1
+#define RTC_CNTL_PLL_FORCE_ISO_S  24
+/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_XTL_FORCE_ISO  (BIT(23))
+#define RTC_CNTL_XTL_FORCE_ISO_M  (BIT(23))
+#define RTC_CNTL_XTL_FORCE_ISO_V  0x1
+#define RTC_CNTL_XTL_FORCE_ISO_S  23
+/* RTC_CNTL_XTL_EXT_CTR_SEL : R/W ;bitpos:[22:20] ;default: 3'd0 ; */
+/*description: */
+#define RTC_CNTL_XTL_EXT_CTR_SEL  0x00000007
+#define RTC_CNTL_XTL_EXT_CTR_SEL_M  ((RTC_CNTL_XTL_EXT_CTR_SEL_V)<<(RTC_CNTL_XTL_EXT_CTR_SEL_S))
+#define RTC_CNTL_XTL_EXT_CTR_SEL_V  0x7
+#define RTC_CNTL_XTL_EXT_CTR_SEL_S  20
+/* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */
+/*description: wait bias_sleep and current source wakeup*/
+#define RTC_CNTL_XTL_EN_WAIT  0x0000000F
+#define RTC_CNTL_XTL_EN_WAIT_M  ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S))
+#define RTC_CNTL_XTL_EN_WAIT_V  0xF
+#define RTC_CNTL_XTL_EN_WAIT_S  14
+/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */
+/*description: crystall force power up*/
+#define RTC_CNTL_XTL_FORCE_PU  (BIT(13))
+#define RTC_CNTL_XTL_FORCE_PU_M  (BIT(13))
+#define RTC_CNTL_XTL_FORCE_PU_V  0x1
+#define RTC_CNTL_XTL_FORCE_PU_S  13
+/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: crystall force power down*/
+#define RTC_CNTL_XTL_FORCE_PD  (BIT(12))
+#define RTC_CNTL_XTL_FORCE_PD_M  (BIT(12))
+#define RTC_CNTL_XTL_FORCE_PD_V  0x1
+#define RTC_CNTL_XTL_FORCE_PD_S  12
+/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: BB_PLL force power up*/
+#define RTC_CNTL_BBPLL_FORCE_PU  (BIT(11))
+#define RTC_CNTL_BBPLL_FORCE_PU_M  (BIT(11))
+#define RTC_CNTL_BBPLL_FORCE_PU_V  0x1
+#define RTC_CNTL_BBPLL_FORCE_PU_S  11
+/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: BB_PLL force power down*/
+#define RTC_CNTL_BBPLL_FORCE_PD  (BIT(10))
+#define RTC_CNTL_BBPLL_FORCE_PD_M  (BIT(10))
+#define RTC_CNTL_BBPLL_FORCE_PD_V  0x1
+#define RTC_CNTL_BBPLL_FORCE_PD_S  10
+/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: BB_PLL_I2C force power up*/
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU  (BIT(9))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M  (BIT(9))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V  0x1
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S  9
+/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: BB_PLL _I2C force power down*/
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD  (BIT(8))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M  (BIT(8))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V  0x1
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S  8
+/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: BB_I2C force power up*/
+#define RTC_CNTL_BB_I2C_FORCE_PU  (BIT(7))
+#define RTC_CNTL_BB_I2C_FORCE_PU_M  (BIT(7))
+#define RTC_CNTL_BB_I2C_FORCE_PU_V  0x1
+#define RTC_CNTL_BB_I2C_FORCE_PU_S  7
+/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: BB_I2C force power down*/
+#define RTC_CNTL_BB_I2C_FORCE_PD  (BIT(6))
+#define RTC_CNTL_BB_I2C_FORCE_PD_M  (BIT(6))
+#define RTC_CNTL_BB_I2C_FORCE_PD_V  0x1
+#define RTC_CNTL_BB_I2C_FORCE_PD_S  6
+/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: PRO CPU SW reset*/
+#define RTC_CNTL_SW_PROCPU_RST  (BIT(5))
+#define RTC_CNTL_SW_PROCPU_RST_M  (BIT(5))
+#define RTC_CNTL_SW_PROCPU_RST_V  0x1
+#define RTC_CNTL_SW_PROCPU_RST_S  5
+/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: APP CPU SW reset*/
+#define RTC_CNTL_SW_APPCPU_RST  (BIT(4))
+#define RTC_CNTL_SW_APPCPU_RST_M  (BIT(4))
+#define RTC_CNTL_SW_APPCPU_RST_V  0x1
+#define RTC_CNTL_SW_APPCPU_RST_S  4
+/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: {reg_sw_stall_procpu_c1[5:0]   reg_sw_stall_procpu_c0[1:0]} ==
+ 0x86 will stall PRO CPU*/
+#define RTC_CNTL_SW_STALL_PROCPU_C0  0x00000003
+#define RTC_CNTL_SW_STALL_PROCPU_C0_M  ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S))
+#define RTC_CNTL_SW_STALL_PROCPU_C0_V  0x3
+#define RTC_CNTL_SW_STALL_PROCPU_C0_S  2
+/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: {reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]} ==
+ 0x86 will stall APP CPU*/
+#define RTC_CNTL_SW_STALL_APPCPU_C0  0x00000003
+#define RTC_CNTL_SW_STALL_APPCPU_C0_M  ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S))
+#define RTC_CNTL_SW_STALL_APPCPU_C0_V  0x3
+#define RTC_CNTL_SW_STALL_APPCPU_C0_S  0
+
+#define RTC_CNTL_SLP_TIMER0_REG          (DR_REG_RTCCNTL_BASE + 0x0004)
+/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define RTC_CNTL_SLP_VAL_LO  0xFFFFFFFF
+#define RTC_CNTL_SLP_VAL_LO_M  ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S))
+#define RTC_CNTL_SLP_VAL_LO_V  0xFFFFFFFF
+#define RTC_CNTL_SLP_VAL_LO_S  0
+
+#define RTC_CNTL_SLP_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x0008)
+/* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */
+/*description: timer alarm enable bit*/
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN  (BIT(16))
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M  (BIT(16))
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V  0x1
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S  16
+/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC sleep timer high 16 bits*/
+#define RTC_CNTL_SLP_VAL_HI  0x0000FFFF
+#define RTC_CNTL_SLP_VAL_HI_M  ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S))
+#define RTC_CNTL_SLP_VAL_HI_V  0xFFFF
+#define RTC_CNTL_SLP_VAL_HI_S  0
+
+#define RTC_CNTL_TIME_UPDATE_REG          (DR_REG_RTCCNTL_BASE + 0x000C)
+/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: Set 1: to update register with RTC timer*/
+#define RTC_CNTL_TIME_UPDATE  (BIT(31))
+#define RTC_CNTL_TIME_UPDATE_M  (BIT(31))
+#define RTC_CNTL_TIME_UPDATE_V  0x1
+#define RTC_CNTL_TIME_UPDATE_S  31
+/* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: enable to record system reset time*/
+#define RTC_CNTL_TIMER_SYS_RST  (BIT(29))
+#define RTC_CNTL_TIMER_SYS_RST_M  (BIT(29))
+#define RTC_CNTL_TIMER_SYS_RST_V  0x1
+#define RTC_CNTL_TIMER_SYS_RST_S  29
+/* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Enable to record 40M XTAL OFF time*/
+#define RTC_CNTL_TIMER_XTL_OFF  (BIT(28))
+#define RTC_CNTL_TIMER_XTL_OFF_M  (BIT(28))
+#define RTC_CNTL_TIMER_XTL_OFF_V  0x1
+#define RTC_CNTL_TIMER_XTL_OFF_S  28
+/* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Enable to record system stall time*/
+#define RTC_CNTL_TIMER_SYS_STALL  (BIT(27))
+#define RTC_CNTL_TIMER_SYS_STALL_M  (BIT(27))
+#define RTC_CNTL_TIMER_SYS_STALL_V  0x1
+#define RTC_CNTL_TIMER_SYS_STALL_S  27
+
+#define RTC_CNTL_TIME_LOW0_REG          (DR_REG_RTCCNTL_BASE + 0x0010)
+/* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: RTC timer low 32 bits*/
+#define RTC_CNTL_TIMER_VALUE0_LOW  0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE0_LOW_M  ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S))
+#define RTC_CNTL_TIMER_VALUE0_LOW_V  0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE0_LOW_S  0
+
+#define RTC_CNTL_TIME_HIGH0_REG          (DR_REG_RTCCNTL_BASE + 0x0014)
+/* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC timer high 16 bits*/
+#define RTC_CNTL_TIMER_VALUE0_HIGH  0x0000FFFF
+#define RTC_CNTL_TIMER_VALUE0_HIGH_M  ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S))
+#define RTC_CNTL_TIMER_VALUE0_HIGH_V  0xFFFF
+#define RTC_CNTL_TIMER_VALUE0_HIGH_S  0
+
+#define RTC_CNTL_STATE0_REG          (DR_REG_RTCCNTL_BASE + 0x0018)
+/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: sleep enable bit*/
+#define RTC_CNTL_SLEEP_EN  (BIT(31))
+#define RTC_CNTL_SLEEP_EN_M  (BIT(31))
+#define RTC_CNTL_SLEEP_EN_V  0x1
+#define RTC_CNTL_SLEEP_EN_S  31
+/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: leep reject bit*/
+#define RTC_CNTL_SLP_REJECT  (BIT(30))
+#define RTC_CNTL_SLP_REJECT_M  (BIT(30))
+#define RTC_CNTL_SLP_REJECT_V  0x1
+#define RTC_CNTL_SLP_REJECT_S  30
+/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: leep wakeup bit*/
+#define RTC_CNTL_SLP_WAKEUP  (BIT(29))
+#define RTC_CNTL_SLP_WAKEUP_M  (BIT(29))
+#define RTC_CNTL_SLP_WAKEUP_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_S  29
+/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */
+/*description: SDIO active indication*/
+#define RTC_CNTL_SDIO_ACTIVE_IND  (BIT(28))
+#define RTC_CNTL_SDIO_ACTIVE_IND_M  (BIT(28))
+#define RTC_CNTL_SDIO_ACTIVE_IND_V  0x1
+#define RTC_CNTL_SDIO_ACTIVE_IND_S  28
+/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: 1: APB to RTC using bridge*/
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL  (BIT(22))
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M  (BIT(22))
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V  0x1
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S  22
+/* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: clear rtc sleep reject cause*/
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V  0x1
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S  1
+/* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: rtc software interrupt to main cpu*/
+#define RTC_CNTL_SW_CPU_INT  (BIT(0))
+#define RTC_CNTL_SW_CPU_INT_M  (BIT(0))
+#define RTC_CNTL_SW_CPU_INT_V  0x1
+#define RTC_CNTL_SW_CPU_INT_S  0
+
+#define RTC_CNTL_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x001C)
+/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */
+/*description: PLL wait cycles in slow_clk_rtc*/
+#define RTC_CNTL_PLL_BUF_WAIT  0x000000FF
+#define RTC_CNTL_PLL_BUF_WAIT_M  ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S))
+#define RTC_CNTL_PLL_BUF_WAIT_V  0xFF
+#define RTC_CNTL_PLL_BUF_WAIT_S  24
+#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT  20
+/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */
+/*description: XTAL wait cycles in slow_clk_rtc*/
+#define RTC_CNTL_XTL_BUF_WAIT  0x000003FF
+#define RTC_CNTL_XTL_BUF_WAIT_M  ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S))
+#define RTC_CNTL_XTL_BUF_WAIT_V  0x3FF
+#define RTC_CNTL_XTL_BUF_WAIT_S  14
+#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT  100
+/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */
+/*description: CK8M wait cycles in slow_clk_rtc*/
+#define RTC_CNTL_CK8M_WAIT  0x000000FF
+#define RTC_CNTL_CK8M_WAIT_M  ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
+#define RTC_CNTL_CK8M_WAIT_V  0xFF
+#define RTC_CNTL_CK8M_WAIT_S  6
+#define RTC_CNTL_CK8M_WAIT_DEFAULT  20
+/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */
+/*description: CPU stall wait cycles in fast_clk_rtc*/
+#define RTC_CNTL_CPU_STALL_WAIT  0x0000001F
+#define RTC_CNTL_CPU_STALL_WAIT_M  ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S))
+#define RTC_CNTL_CPU_STALL_WAIT_V  0x1F
+#define RTC_CNTL_CPU_STALL_WAIT_S  1
+/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */
+/*description: CPU stall enable bit*/
+#define RTC_CNTL_CPU_STALL_EN  (BIT(0))
+#define RTC_CNTL_CPU_STALL_EN_M  (BIT(0))
+#define RTC_CNTL_CPU_STALL_EN_V  0x1
+#define RTC_CNTL_CPU_STALL_EN_S  0
+
+#define RTC_CNTL_TIMER2_REG          (DR_REG_RTCCNTL_BASE + 0x0020)
+/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */
+/*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/
+#define RTC_CNTL_MIN_TIME_CK8M_OFF  0x000000FF
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_M  ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S))
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_V  0xFF
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_S  24
+
+#define RTC_CNTL_TIMER3_REG          (DR_REG_RTCCNTL_BASE + 0x0024)
+/* RTC_CNTL_BT_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */
+/*description: */
+#define RTC_CNTL_BT_POWERUP_TIMER  0x0000007F
+#define RTC_CNTL_BT_POWERUP_TIMER_M  ((RTC_CNTL_BT_POWERUP_TIMER_V)<<(RTC_CNTL_BT_POWERUP_TIMER_S))
+#define RTC_CNTL_BT_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_BT_POWERUP_TIMER_S  25
+/* RTC_CNTL_BT_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */
+/*description: */
+#define RTC_CNTL_BT_WAIT_TIMER  0x000001FF
+#define RTC_CNTL_BT_WAIT_TIMER_M  ((RTC_CNTL_BT_WAIT_TIMER_V)<<(RTC_CNTL_BT_WAIT_TIMER_S))
+#define RTC_CNTL_BT_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_BT_WAIT_TIMER_S  16
+/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
+/*description: */
+#define RTC_CNTL_WIFI_POWERUP_TIMER  0x0000007F
+#define RTC_CNTL_WIFI_POWERUP_TIMER_M  ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S))
+#define RTC_CNTL_WIFI_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_WIFI_POWERUP_TIMER_S  9
+/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
+/*description: */
+#define RTC_CNTL_WIFI_WAIT_TIMER  0x000001FF
+#define RTC_CNTL_WIFI_WAIT_TIMER_M  ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S))
+#define RTC_CNTL_WIFI_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_WIFI_WAIT_TIMER_S  0
+
+#define RTC_CNTL_TIMER4_REG          (DR_REG_RTCCNTL_BASE + 0x0028)
+/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */
+/*description: */
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER  0x0000007F
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M  ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S))
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S  25
+/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */
+/*description: */
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER  0x000001FF
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M  ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S))
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S  16
+/* RTC_CNTL_CPU_TOP_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
+/*description: */
+#define RTC_CNTL_CPU_TOP_POWERUP_TIMER  0x0000007F
+#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M  ((RTC_CNTL_CPU_TOP_POWERUP_TIMER_V)<<(RTC_CNTL_CPU_TOP_POWERUP_TIMER_S))
+#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S  9
+/* RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
+/*description: */
+#define RTC_CNTL_CPU_TOP_WAIT_TIMER  0x000001FF
+#define RTC_CNTL_CPU_TOP_WAIT_TIMER_M  ((RTC_CNTL_CPU_TOP_WAIT_TIMER_V)<<(RTC_CNTL_CPU_TOP_WAIT_TIMER_S))
+#define RTC_CNTL_CPU_TOP_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_CPU_TOP_WAIT_TIMER_S  0
+
+#define RTC_CNTL_TIMER5_REG          (DR_REG_RTCCNTL_BASE + 0x002C)
+/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */
+/*description: minimal sleep cycles in slow_clk_rtc*/
+#define RTC_CNTL_MIN_SLP_VAL  0x000000FF
+#define RTC_CNTL_MIN_SLP_VAL_M  ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S))
+#define RTC_CNTL_MIN_SLP_VAL_V  0xFF
+#define RTC_CNTL_MIN_SLP_VAL_S  8
+
+#define RTC_CNTL_TIMER6_REG          (DR_REG_RTCCNTL_BASE + 0x0030)
+/* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */
+/*description: */
+#define RTC_CNTL_DG_PERI_POWERUP_TIMER  0x0000007F
+#define RTC_CNTL_DG_PERI_POWERUP_TIMER_M  ((RTC_CNTL_DG_PERI_POWERUP_TIMER_V)<<(RTC_CNTL_DG_PERI_POWERUP_TIMER_S))
+#define RTC_CNTL_DG_PERI_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_DG_PERI_POWERUP_TIMER_S  25
+/* RTC_CNTL_DG_PERI_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */
+/*description: */
+#define RTC_CNTL_DG_PERI_WAIT_TIMER  0x000001FF
+#define RTC_CNTL_DG_PERI_WAIT_TIMER_M  ((RTC_CNTL_DG_PERI_WAIT_TIMER_V)<<(RTC_CNTL_DG_PERI_WAIT_TIMER_S))
+#define RTC_CNTL_DG_PERI_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_DG_PERI_WAIT_TIMER_S  16
+
+#define RTC_CNTL_ANA_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0034)
+/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_PLL_I2C_PU  (BIT(31))
+#define RTC_CNTL_PLL_I2C_PU_M  (BIT(31))
+#define RTC_CNTL_PLL_I2C_PU_V  0x1
+#define RTC_CNTL_PLL_I2C_PU_S  31
+/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: 1: CKGEN_I2C power up*/
+#define RTC_CNTL_CKGEN_I2C_PU  (BIT(30))
+#define RTC_CNTL_CKGEN_I2C_PU_M  (BIT(30))
+#define RTC_CNTL_CKGEN_I2C_PU_V  0x1
+#define RTC_CNTL_CKGEN_I2C_PU_S  30
+/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: 1: RFRX_PBUS power up*/
+#define RTC_CNTL_RFRX_PBUS_PU  (BIT(28))
+#define RTC_CNTL_RFRX_PBUS_PU_M  (BIT(28))
+#define RTC_CNTL_RFRX_PBUS_PU_V  0x1
+#define RTC_CNTL_RFRX_PBUS_PU_S  28
+/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: 1: TXRF_I2C power up*/
+#define RTC_CNTL_TXRF_I2C_PU  (BIT(27))
+#define RTC_CNTL_TXRF_I2C_PU_M  (BIT(27))
+#define RTC_CNTL_TXRF_I2C_PU_V  0x1
+#define RTC_CNTL_TXRF_I2C_PU_S  27
+/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: 1: PVTMON power up*/
+#define RTC_CNTL_PVTMON_PU  (BIT(26))
+#define RTC_CNTL_PVTMON_PU_M  (BIT(26))
+#define RTC_CNTL_PVTMON_PU_V  0x1
+#define RTC_CNTL_PVTMON_PU_S  26
+/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: start BBPLL calibration during sleep*/
+#define RTC_CNTL_BBPLL_CAL_SLP_START  (BIT(25))
+#define RTC_CNTL_BBPLL_CAL_SLP_START_M  (BIT(25))
+#define RTC_CNTL_BBPLL_CAL_SLP_START_V  0x1
+#define RTC_CNTL_BBPLL_CAL_SLP_START_S  25
+/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: PLLA force power up*/
+#define RTC_CNTL_PLLA_FORCE_PU  (BIT(24))
+#define RTC_CNTL_PLLA_FORCE_PU_M  (BIT(24))
+#define RTC_CNTL_PLLA_FORCE_PU_V  0x1
+#define RTC_CNTL_PLLA_FORCE_PU_S  24
+/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: PLLA force power down*/
+#define RTC_CNTL_PLLA_FORCE_PD  (BIT(23))
+#define RTC_CNTL_PLLA_FORCE_PD_M  (BIT(23))
+#define RTC_CNTL_PLLA_FORCE_PD_V  0x1
+#define RTC_CNTL_PLLA_FORCE_PD_S  23
+/* RTC_CNTL_SAR_I2C_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: PLLA force power up*/
+#define RTC_CNTL_SAR_I2C_PU  (BIT(22))
+#define RTC_CNTL_SAR_I2C_PU_M  (BIT(22))
+#define RTC_CNTL_SAR_I2C_PU_V  0x1
+#define RTC_CNTL_SAR_I2C_PU_S  22
+/* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GLITCH_RST_EN  (BIT(20))
+#define RTC_CNTL_GLITCH_RST_EN_M  (BIT(20))
+#define RTC_CNTL_GLITCH_RST_EN_V  0x1
+#define RTC_CNTL_GLITCH_RST_EN_S  20
+/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU  (BIT(19))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M  (BIT(19))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V  0x1
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S  19
+/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: */
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD  (BIT(18))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M  (BIT(18))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V  0x1
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S  18
+
+#define RTC_CNTL_RESET_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x0038)
+/* RTC_CNTL_DRESET_MASK_PROCPU : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_DRESET_MASK_PROCPU  (BIT(25))
+#define RTC_CNTL_DRESET_MASK_PROCPU_M  (BIT(25))
+#define RTC_CNTL_DRESET_MASK_PROCPU_V  0x1
+#define RTC_CNTL_DRESET_MASK_PROCPU_S  25
+/* RTC_CNTL_DRESET_MASK_APPCPU : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_DRESET_MASK_APPCPU  (BIT(24))
+#define RTC_CNTL_DRESET_MASK_APPCPU_M  (BIT(24))
+#define RTC_CNTL_DRESET_MASK_APPCPU_V  0x1
+#define RTC_CNTL_DRESET_MASK_APPCPU_S  24
+/* RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU  (BIT(23))
+#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_M  (BIT(23))
+#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_V  0x1
+#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_S  23
+/* RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU  (BIT(22))
+#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_M  (BIT(22))
+#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_V  0x1
+#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_S  22
+/* RTC_CNTL_JTAG_RESET_FLAG_APPCPU : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU  (BIT(21))
+#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_M  (BIT(21))
+#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_V  0x1
+#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_S  21
+/* RTC_CNTL_JTAG_RESET_FLAG_PROCPU : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU  (BIT(20))
+#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_M  (BIT(20))
+#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_V  0x1
+#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_S  20
+/* RTC_CNTL_OCD_HALT_ON_RESET_PROCPU : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: PROCPU OcdHaltOnReset*/
+#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU  (BIT(19))
+#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_M  (BIT(19))
+#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_V  0x1
+#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_S  19
+/* RTC_CNTL_OCD_HALT_ON_RESET_APPCPU : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: APPCPU OcdHaltOnReset*/
+#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU  (BIT(18))
+#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_M  (BIT(18))
+#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_V  0x1
+#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_S  18
+/* RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: clear APP CPU reset flag*/
+#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU  (BIT(17))
+#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_M  (BIT(17))
+#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_V  0x1
+#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_S  17
+/* RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: clear PRO CPU reset_flag*/
+#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU  (BIT(16))
+#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_M  (BIT(16))
+#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_V  0x1
+#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_S  16
+/* RTC_CNTL_ALL_RESET_FLAG_APPCPU : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: APP CPU reset flag*/
+#define RTC_CNTL_ALL_RESET_FLAG_APPCPU  (BIT(15))
+#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_M  (BIT(15))
+#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_V  0x1
+#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_S  15
+/* RTC_CNTL_ALL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: PRO CPU reset_flag*/
+#define RTC_CNTL_ALL_RESET_FLAG_PROCPU  (BIT(14))
+#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_M  (BIT(14))
+#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_V  0x1
+#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_S  14
+/* RTC_CNTL_STAT_VECTOR_SEL_PROCPU : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: PRO CPU state vector sel*/
+#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU  (BIT(13))
+#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_M  (BIT(13))
+#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_V  0x1
+#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_S  13
+/* RTC_CNTL_STAT_VECTOR_SEL_APPCPU : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: APP CPU state vector sel*/
+#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU  (BIT(12))
+#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_M  (BIT(12))
+#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_V  0x1
+#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_S  12
+/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */
+/*description: reset cause of APP CPU*/
+#define RTC_CNTL_RESET_CAUSE_APPCPU  0x0000003F
+#define RTC_CNTL_RESET_CAUSE_APPCPU_M  ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S))
+#define RTC_CNTL_RESET_CAUSE_APPCPU_V  0x3F
+#define RTC_CNTL_RESET_CAUSE_APPCPU_S  6
+/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */
+/*description: reset cause of PRO CPU*/
+#define RTC_CNTL_RESET_CAUSE_PROCPU  0x0000003F
+#define RTC_CNTL_RESET_CAUSE_PROCPU_M  ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S))
+#define RTC_CNTL_RESET_CAUSE_PROCPU_V  0x3F
+#define RTC_CNTL_RESET_CAUSE_PROCPU_S  0
+
+#define RTC_CNTL_WAKEUP_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x003C)
+/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */
+/*description: wakeup enable bitmap*/
+#define RTC_CNTL_WAKEUP_ENA  0x0001FFFF
+#define RTC_CNTL_WAKEUP_ENA_M  ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S))
+#define RTC_CNTL_WAKEUP_ENA_V  0x1FFFF
+#define RTC_CNTL_WAKEUP_ENA_S  15
+
+#define RTC_CNTL_INT_ENA_REG          (DR_REG_RTCCNTL_BASE + 0x0040)
+/* RTC_CNTL_BBPLL_CAL_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BBPLL_CAL_INT_ENA  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_S  20
+/* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: enbale gitch det interrupt*/
+#define RTC_CNTL_GLITCH_DET_INT_ENA  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ENA_M  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ENA_V  0x1
+#define RTC_CNTL_GLITCH_DET_INT_ENA_S  19
+/* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: enable xtal32k_dead  interrupt*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S  16
+/* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable super watch dog interrupt*/
+#define RTC_CNTL_SWD_INT_ENA  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_V  0x1
+#define RTC_CNTL_SWD_INT_ENA_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: enable RTC main timer interrupt*/
+#define RTC_CNTL_MAIN_TIMER_INT_ENA  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: enable brown out interrupt*/
+#define RTC_CNTL_BROWN_OUT_INT_ENA  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ENA_S  9
+/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt*/
+#define RTC_CNTL_WDT_INT_ENA  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_V  0x1
+#define RTC_CNTL_WDT_INT_ENA_S  3
+/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable sleep reject interrupt*/
+#define RTC_CNTL_SLP_REJECT_INT_ENA  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ENA_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable sleep wakeup interrupt*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S  0
+
+#define RTC_CNTL_INT_RAW_REG          (DR_REG_RTCCNTL_BASE + 0x0044)
+/* RTC_CNTL_BBPLL_CAL_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BBPLL_CAL_INT_RAW  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_RAW_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_RAW_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_RAW_S  20
+/* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: glitch_det_interrupt_raw*/
+#define RTC_CNTL_GLITCH_DET_INT_RAW  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_RAW_M  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_RAW_V  0x1
+#define RTC_CNTL_GLITCH_DET_INT_RAW_S  19
+/* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: xtal32k dead detection interrupt raw*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_RAW  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S  16
+/* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: super watch dog interrupt raw*/
+#define RTC_CNTL_SWD_INT_RAW  (BIT(15))
+#define RTC_CNTL_SWD_INT_RAW_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_RAW_V  0x1
+#define RTC_CNTL_SWD_INT_RAW_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: RTC main timer interrupt raw*/
+#define RTC_CNTL_MAIN_TIMER_INT_RAW  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_S  10
+/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: brown out interrupt raw*/
+#define RTC_CNTL_BROWN_OUT_INT_RAW  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_RAW_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_RAW_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_RAW_S  9
+/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: RTC WDT interrupt raw*/
+#define RTC_CNTL_WDT_INT_RAW  (BIT(3))
+#define RTC_CNTL_WDT_INT_RAW_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_RAW_V  0x1
+#define RTC_CNTL_WDT_INT_RAW_S  3
+/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: sleep reject interrupt raw*/
+#define RTC_CNTL_SLP_REJECT_INT_RAW  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_RAW_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_RAW_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_RAW_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: sleep wakeup interrupt raw*/
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S  0
+
+#define RTC_CNTL_INT_ST_REG          (DR_REG_RTCCNTL_BASE + 0x0048)
+/* RTC_CNTL_BBPLL_CAL_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BBPLL_CAL_INT_ST  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ST_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ST_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_ST_S  20
+/* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: glitch_det_interrupt state*/
+#define RTC_CNTL_GLITCH_DET_INT_ST  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ST_M  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ST_V  0x1
+#define RTC_CNTL_GLITCH_DET_INT_ST_S  19
+/* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: xtal32k dead detection interrupt state*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_ST  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S  16
+/* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: super watch dog interrupt state*/
+#define RTC_CNTL_SWD_INT_ST  (BIT(15))
+#define RTC_CNTL_SWD_INT_ST_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ST_V  0x1
+#define RTC_CNTL_SWD_INT_ST_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: RTC main timer interrupt state*/
+#define RTC_CNTL_MAIN_TIMER_INT_ST  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ST_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ST_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ST_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: brown out interrupt state*/
+#define RTC_CNTL_BROWN_OUT_INT_ST  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ST_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ST_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ST_S  9
+/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: RTC WDT interrupt state*/
+#define RTC_CNTL_WDT_INT_ST  (BIT(3))
+#define RTC_CNTL_WDT_INT_ST_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ST_V  0x1
+#define RTC_CNTL_WDT_INT_ST_S  3
+/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: sleep reject interrupt state*/
+#define RTC_CNTL_SLP_REJECT_INT_ST  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ST_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ST_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ST_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: sleep wakeup interrupt state*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ST  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_S  0
+
+#define RTC_CNTL_INT_CLR_REG          (DR_REG_RTCCNTL_BASE + 0x004C)
+/* RTC_CNTL_BBPLL_CAL_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BBPLL_CAL_INT_CLR  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_CLR_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_CLR_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_CLR_S  20
+/* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Clear glitch det interrupt state*/
+#define RTC_CNTL_GLITCH_DET_INT_CLR  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_CLR_M  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_CLR_V  0x1
+#define RTC_CNTL_GLITCH_DET_INT_CLR_S  19
+/* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Clear RTC WDT interrupt state*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_CLR  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S  16
+/* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Clear super watch dog interrupt state*/
+#define RTC_CNTL_SWD_INT_CLR  (BIT(15))
+#define RTC_CNTL_SWD_INT_CLR_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_CLR_V  0x1
+#define RTC_CNTL_SWD_INT_CLR_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Clear RTC main timer interrupt state*/
+#define RTC_CNTL_MAIN_TIMER_INT_CLR  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_S  10
+/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Clear brown out interrupt state*/
+#define RTC_CNTL_BROWN_OUT_INT_CLR  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_CLR_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_CLR_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_CLR_S  9
+/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Clear RTC WDT interrupt state*/
+#define RTC_CNTL_WDT_INT_CLR  (BIT(3))
+#define RTC_CNTL_WDT_INT_CLR_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_CLR_V  0x1
+#define RTC_CNTL_WDT_INT_CLR_S  3
+/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Clear sleep reject interrupt state*/
+#define RTC_CNTL_SLP_REJECT_INT_CLR  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_CLR_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_CLR_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_CLR_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Clear sleep wakeup interrupt state*/
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S  0
+
+#define RTC_CNTL_STORE0_REG          (DR_REG_RTCCNTL_BASE + 0x0050)
+/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH0  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH0_M  ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S))
+#define RTC_CNTL_SCRATCH0_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH0_S  0
+
+#define RTC_CNTL_STORE1_REG          (DR_REG_RTCCNTL_BASE + 0x0054)
+/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH1  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH1_M  ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S))
+#define RTC_CNTL_SCRATCH1_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH1_S  0
+
+#define RTC_CNTL_STORE2_REG          (DR_REG_RTCCNTL_BASE + 0x0058)
+/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH2  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH2_M  ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S))
+#define RTC_CNTL_SCRATCH2_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH2_S  0
+
+#define RTC_CNTL_STORE3_REG          (DR_REG_RTCCNTL_BASE + 0x005C)
+/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH3  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH3_M  ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S))
+#define RTC_CNTL_SCRATCH3_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH3_S  0
+
+#define RTC_CNTL_EXT_XTL_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0060)
+/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_XTL_EXT_CTR_EN  (BIT(31))
+#define RTC_CNTL_XTL_EXT_CTR_EN_M  (BIT(31))
+#define RTC_CNTL_XTL_EXT_CTR_EN_V  0x1
+#define RTC_CNTL_XTL_EXT_CTR_EN_S  31
+/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: 0: power down XTAL at high level*/
+#define RTC_CNTL_XTL_EXT_CTR_LV  (BIT(30))
+#define RTC_CNTL_XTL_EXT_CTR_LV_M  (BIT(30))
+#define RTC_CNTL_XTL_EXT_CTR_LV_V  0x1
+#define RTC_CNTL_XTL_EXT_CTR_LV_S  30
+/* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: XTAL_32K sel. 0: external XTAL_32K*/
+#define RTC_CNTL_XTAL32K_GPIO_SEL  (BIT(23))
+#define RTC_CNTL_XTAL32K_GPIO_SEL_M  (BIT(23))
+#define RTC_CNTL_XTAL32K_GPIO_SEL_V  0x1
+#define RTC_CNTL_XTAL32K_GPIO_SEL_S  23
+/* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */
+/*description: state of 32k_wdt*/
+#define RTC_CNTL_WDT_STATE  0x00000007
+#define RTC_CNTL_WDT_STATE_M  ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S))
+#define RTC_CNTL_WDT_STATE_V  0x7
+#define RTC_CNTL_WDT_STATE_S  20
+/* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */
+/*description: DAC_XTAL_32K*/
+#define RTC_CNTL_DAC_XTAL_32K  0x00000007
+#define RTC_CNTL_DAC_XTAL_32K_M  ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S))
+#define RTC_CNTL_DAC_XTAL_32K_V  0x7
+#define RTC_CNTL_DAC_XTAL_32K_S  17
+/* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: XPD_XTAL_32K*/
+#define RTC_CNTL_XPD_XTAL_32K  (BIT(16))
+#define RTC_CNTL_XPD_XTAL_32K_M  (BIT(16))
+#define RTC_CNTL_XPD_XTAL_32K_V  0x1
+#define RTC_CNTL_XPD_XTAL_32K_S  16
+/* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */
+/*description: DRES_XTAL_32K*/
+#define RTC_CNTL_DRES_XTAL_32K  0x00000007
+#define RTC_CNTL_DRES_XTAL_32K_M  ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S))
+#define RTC_CNTL_DRES_XTAL_32K_V  0x7
+#define RTC_CNTL_DRES_XTAL_32K_S  13
+/* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */
+/*description: xtal_32k gm control*/
+#define RTC_CNTL_DGM_XTAL_32K  0x00000007
+#define RTC_CNTL_DGM_XTAL_32K_M  ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S))
+#define RTC_CNTL_DGM_XTAL_32K_V  0x7
+#define RTC_CNTL_DGM_XTAL_32K_S  10
+/* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 0: single-end buffer 1: differential buffer*/
+#define RTC_CNTL_DBUF_XTAL_32K  (BIT(9))
+#define RTC_CNTL_DBUF_XTAL_32K_M  (BIT(9))
+#define RTC_CNTL_DBUF_XTAL_32K_V  0x1
+#define RTC_CNTL_DBUF_XTAL_32K_S  9
+/* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: apply an internal clock to help xtal 32k to start*/
+#define RTC_CNTL_ENCKINIT_XTAL_32K  (BIT(8))
+#define RTC_CNTL_ENCKINIT_XTAL_32K_M  (BIT(8))
+#define RTC_CNTL_ENCKINIT_XTAL_32K_V  0x1
+#define RTC_CNTL_ENCKINIT_XTAL_32K_S  8
+/* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: Xtal 32k xpd control by sw or fsm*/
+#define RTC_CNTL_XTAL32K_XPD_FORCE  (BIT(7))
+#define RTC_CNTL_XTAL32K_XPD_FORCE_M  (BIT(7))
+#define RTC_CNTL_XTAL32K_XPD_FORCE_V  0x1
+#define RTC_CNTL_XTAL32K_XPD_FORCE_S  7
+/* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: xtal 32k switch back xtal when xtal is restarted*/
+#define RTC_CNTL_XTAL32K_AUTO_RETURN  (BIT(6))
+#define RTC_CNTL_XTAL32K_AUTO_RETURN_M  (BIT(6))
+#define RTC_CNTL_XTAL32K_AUTO_RETURN_V  0x1
+#define RTC_CNTL_XTAL32K_AUTO_RETURN_S  6
+/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: xtal 32k restart xtal when xtal is dead*/
+#define RTC_CNTL_XTAL32K_AUTO_RESTART  (BIT(5))
+#define RTC_CNTL_XTAL32K_AUTO_RESTART_M  (BIT(5))
+#define RTC_CNTL_XTAL32K_AUTO_RESTART_V  0x1
+#define RTC_CNTL_XTAL32K_AUTO_RESTART_S  5
+/* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: xtal 32k switch to back up clock when xtal is dead*/
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP  (BIT(4))
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M  (BIT(4))
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V  0x1
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S  4
+/* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: xtal 32k external xtal clock force on*/
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO  (BIT(3))
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M  (BIT(3))
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V  0x1
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S  3
+/* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: xtal 32k watch dog sw reset*/
+#define RTC_CNTL_XTAL32K_WDT_RESET  (BIT(2))
+#define RTC_CNTL_XTAL32K_WDT_RESET_M  (BIT(2))
+#define RTC_CNTL_XTAL32K_WDT_RESET_V  0x1
+#define RTC_CNTL_XTAL32K_WDT_RESET_S  2
+/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: xtal 32k watch dog clock force on*/
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO  (BIT(1))
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M  (BIT(1))
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V  0x1
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S  1
+/* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: xtal 32k watch dog enable*/
+#define RTC_CNTL_XTAL32K_WDT_EN  (BIT(0))
+#define RTC_CNTL_XTAL32K_WDT_EN_M  (BIT(0))
+#define RTC_CNTL_XTAL32K_WDT_EN_V  0x1
+#define RTC_CNTL_XTAL32K_WDT_EN_S  0
+
+#define RTC_CNTL_EXT_WAKEUP_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0064)
+/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: enable filter for gpio wakeup event*/
+#define RTC_CNTL_GPIO_WAKEUP_FILTER  (BIT(31))
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_M  (BIT(31))
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_V  0x1
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_S  31
+
+#define RTC_CNTL_SLP_REJECT_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0068)
+/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: enable reject for deep sleep*/
+#define RTC_CNTL_DEEP_SLP_REJECT_EN  (BIT(31))
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_M  (BIT(31))
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_V  0x1
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_S  31
+/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: enable reject for light sleep*/
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN  (BIT(30))
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M  (BIT(30))
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V  0x1
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S  30
+/* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:12] ;default: 17'd0 ; */
+/*description: sleep reject enable*/
+#define RTC_CNTL_SLEEP_REJECT_ENA  0x0003FFFF
+#define RTC_CNTL_SLEEP_REJECT_ENA_M  ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S))
+#define RTC_CNTL_SLEEP_REJECT_ENA_V  0x3FFFF
+#define RTC_CNTL_SLEEP_REJECT_ENA_S  12
+
+#define RTC_CNTL_CPU_PERIOD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x006C)
+/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */
+/*description: */
+#define RTC_CNTL_CPUPERIOD_SEL  0x00000003
+#define RTC_CNTL_CPUPERIOD_SEL_M  ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S))
+#define RTC_CNTL_CPUPERIOD_SEL_V  0x3
+#define RTC_CNTL_CPUPERIOD_SEL_S  30
+/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: CPU sel option*/
+#define RTC_CNTL_CPUSEL_CONF  (BIT(29))
+#define RTC_CNTL_CPUSEL_CONF_M  (BIT(29))
+#define RTC_CNTL_CPUSEL_CONF_V  0x1
+#define RTC_CNTL_CPUSEL_CONF_S  29
+
+#define RTC_CNTL_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0070)
+/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: */
+#define RTC_CNTL_ANA_CLK_RTC_SEL  0x00000003
+#define RTC_CNTL_ANA_CLK_RTC_SEL_M  ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S))
+#define RTC_CNTL_ANA_CLK_RTC_SEL_V  0x3
+#define RTC_CNTL_ANA_CLK_RTC_SEL_S  30
+/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: fast_clk_rtc sel. 0: XTAL div 4*/
+#define RTC_CNTL_FAST_CLK_RTC_SEL  (BIT(29))
+#define RTC_CNTL_FAST_CLK_RTC_SEL_M  (BIT(29))
+#define RTC_CNTL_FAST_CLK_RTC_SEL_V  0x1
+#define RTC_CNTL_FAST_CLK_RTC_SEL_S  29
+/* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: */
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING  (BIT(28))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M  (BIT(28))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S  28
+/* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING  (BIT(27))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M  (BIT(27))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V  0x1
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S  27
+/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: CK8M force power up*/
+#define RTC_CNTL_CK8M_FORCE_PU  (BIT(26))
+#define RTC_CNTL_CK8M_FORCE_PU_M  (BIT(26))
+#define RTC_CNTL_CK8M_FORCE_PU_V  0x1
+#define RTC_CNTL_CK8M_FORCE_PU_S  26
+/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: CK8M force power down*/
+#define RTC_CNTL_CK8M_FORCE_PD  (BIT(25))
+#define RTC_CNTL_CK8M_FORCE_PD_M  (BIT(25))
+#define RTC_CNTL_CK8M_FORCE_PD_V  0x1
+#define RTC_CNTL_CK8M_FORCE_PD_S  25
+/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */
+/*description: CK8M_DFREQ*/
+#define RTC_CNTL_CK8M_DFREQ  0x000000FF
+#define RTC_CNTL_CK8M_DFREQ_M  ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S))
+#define RTC_CNTL_CK8M_DFREQ_V  0xFF
+#define RTC_CNTL_CK8M_DFREQ_S  17
+#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172 //TODO, may change in chip7.2.4
+/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: CK8M force no gating during sleep*/
+#define RTC_CNTL_CK8M_FORCE_NOGATING  (BIT(16))
+#define RTC_CNTL_CK8M_FORCE_NOGATING_M  (BIT(16))
+#define RTC_CNTL_CK8M_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_CK8M_FORCE_NOGATING_S  16
+/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: XTAL force no gating during sleep*/
+#define RTC_CNTL_XTAL_FORCE_NOGATING  (BIT(15))
+#define RTC_CNTL_XTAL_FORCE_NOGATING_M  (BIT(15))
+#define RTC_CNTL_XTAL_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_XTAL_FORCE_NOGATING_S  15
+/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */
+/*description: divider = reg_ck8m_div_sel + 1*/
+#define RTC_CNTL_CK8M_DIV_SEL  0x00000007
+#define RTC_CNTL_CK8M_DIV_SEL_M  ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S))
+#define RTC_CNTL_CK8M_DIV_SEL_V  0x7
+#define RTC_CNTL_CK8M_DIV_SEL_S  12
+/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: enable CK8M for digital core (no relationship with RTC core)*/
+#define RTC_CNTL_DIG_CLK8M_EN  (BIT(10))
+#define RTC_CNTL_DIG_CLK8M_EN_M  (BIT(10))
+#define RTC_CNTL_DIG_CLK8M_EN_V  0x1
+#define RTC_CNTL_DIG_CLK8M_EN_S  10
+/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */
+/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
+#define RTC_CNTL_DIG_CLK8M_D256_EN  (BIT(9))
+#define RTC_CNTL_DIG_CLK8M_D256_EN_M  (BIT(9))
+#define RTC_CNTL_DIG_CLK8M_D256_EN_V  0x1
+#define RTC_CNTL_DIG_CLK8M_D256_EN_S  9
+/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
+#define RTC_CNTL_DIG_XTAL32K_EN  (BIT(8))
+#define RTC_CNTL_DIG_XTAL32K_EN_M  (BIT(8))
+#define RTC_CNTL_DIG_XTAL32K_EN_V  0x1
+#define RTC_CNTL_DIG_XTAL32K_EN_S  8
+/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: 1: CK8M_D256_OUT is actually CK8M*/
+#define RTC_CNTL_ENB_CK8M_DIV  (BIT(7))
+#define RTC_CNTL_ENB_CK8M_DIV_M  (BIT(7))
+#define RTC_CNTL_ENB_CK8M_DIV_V  0x1
+#define RTC_CNTL_ENB_CK8M_DIV_S  7
+/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: disable CK8M and CK8M_D256_OUT*/
+#define RTC_CNTL_ENB_CK8M  (BIT(6))
+#define RTC_CNTL_ENB_CK8M_M  (BIT(6))
+#define RTC_CNTL_ENB_CK8M_V  0x1
+#define RTC_CNTL_ENB_CK8M_S  6
+/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */
+/*description: CK8M_D256_OUT divider. 00: div128*/
+#define RTC_CNTL_CK8M_DIV  0x00000003
+#define RTC_CNTL_CK8M_DIV_M  ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S))
+#define RTC_CNTL_CK8M_DIV_V  0x3
+#define RTC_CNTL_CK8M_DIV_S  4
+/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/
+#define RTC_CNTL_CK8M_DIV_SEL_VLD  (BIT(3))
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_M  (BIT(3))
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_V  0x1
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_S  3
+/* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING  (BIT(2))
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M  (BIT(2))
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S  2
+/* RTC_CNTL_EFUSE_CLK_FORCE_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING  (BIT(1))
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M  (BIT(1))
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V  0x1
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S  1
+
+#define RTC_CNTL_SLOW_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0074)
+/* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE  (BIT(31))
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M  (BIT(31))
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V  0x1
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S  31
+/* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */
+/*description: */
+#define RTC_CNTL_ANA_CLK_DIV  0x000000FF
+#define RTC_CNTL_ANA_CLK_DIV_M  ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S))
+#define RTC_CNTL_ANA_CLK_DIV_V  0xFF
+#define RTC_CNTL_ANA_CLK_DIV_S  23
+/* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/
+#define RTC_CNTL_ANA_CLK_DIV_VLD  (BIT(22))
+#define RTC_CNTL_ANA_CLK_DIV_VLD_M  (BIT(22))
+#define RTC_CNTL_ANA_CLK_DIV_VLD_V  0x1
+#define RTC_CNTL_ANA_CLK_DIV_VLD_S  22
+
+#define RTC_CNTL_SDIO_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0078)
+/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_XPD_SDIO_REG  (BIT(31))
+#define RTC_CNTL_XPD_SDIO_REG_M  (BIT(31))
+#define RTC_CNTL_XPD_SDIO_REG_V  0x1
+#define RTC_CNTL_XPD_SDIO_REG_S  31
+/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */
+/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
+#define RTC_CNTL_DREFH_SDIO  0x00000003
+#define RTC_CNTL_DREFH_SDIO_M  ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S))
+#define RTC_CNTL_DREFH_SDIO_V  0x3
+#define RTC_CNTL_DREFH_SDIO_S  29
+/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */
+/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
+#define RTC_CNTL_DREFM_SDIO  0x00000003
+#define RTC_CNTL_DREFM_SDIO_M  ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S))
+#define RTC_CNTL_DREFM_SDIO_V  0x3
+#define RTC_CNTL_DREFM_SDIO_S  27
+/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */
+/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
+#define RTC_CNTL_DREFL_SDIO  0x00000003
+#define RTC_CNTL_DREFL_SDIO_M  ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S))
+#define RTC_CNTL_DREFL_SDIO_V  0x3
+#define RTC_CNTL_DREFL_SDIO_S  25
+/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */
+/*description: read only register for REG1P8_READY*/
+#define RTC_CNTL_REG1P8_READY  (BIT(24))
+#define RTC_CNTL_REG1P8_READY_M  (BIT(24))
+#define RTC_CNTL_REG1P8_READY_V  0x1
+#define RTC_CNTL_REG1P8_READY_S  24
+/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */
+/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
+#define RTC_CNTL_SDIO_TIEH  (BIT(23))
+#define RTC_CNTL_SDIO_TIEH_M  (BIT(23))
+#define RTC_CNTL_SDIO_TIEH_V  0x1
+#define RTC_CNTL_SDIO_TIEH_S  23
+/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: 1: use SW option to control SDIO_REG*/
+#define RTC_CNTL_SDIO_FORCE  (BIT(22))
+#define RTC_CNTL_SDIO_FORCE_M  (BIT(22))
+#define RTC_CNTL_SDIO_FORCE_V  0x1
+#define RTC_CNTL_SDIO_FORCE_S  22
+/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */
+/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
+#define RTC_CNTL_SDIO_PD_EN  (BIT(21))
+#define RTC_CNTL_SDIO_PD_EN_M  (BIT(21))
+#define RTC_CNTL_SDIO_PD_EN_V  0x1
+#define RTC_CNTL_SDIO_PD_EN_S  21
+/* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */
+/*description: enable current limit*/
+#define RTC_CNTL_SDIO_ENCURLIM  (BIT(20))
+#define RTC_CNTL_SDIO_ENCURLIM_M  (BIT(20))
+#define RTC_CNTL_SDIO_ENCURLIM_V  0x1
+#define RTC_CNTL_SDIO_ENCURLIM_S  20
+/* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: select current limit mode*/
+#define RTC_CNTL_SDIO_MODECURLIM  (BIT(19))
+#define RTC_CNTL_SDIO_MODECURLIM_M  (BIT(19))
+#define RTC_CNTL_SDIO_MODECURLIM_V  0x1
+#define RTC_CNTL_SDIO_MODECURLIM_S  19
+/* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */
+/*description: tune current limit threshold when tieh = 0. About 800mA/(8+d)*/
+#define RTC_CNTL_SDIO_DCURLIM  0x00000007
+#define RTC_CNTL_SDIO_DCURLIM_M  ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S))
+#define RTC_CNTL_SDIO_DCURLIM_V  0x7
+#define RTC_CNTL_SDIO_DCURLIM_S  16
+/* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */
+/*description: 0 to set init[1:0]=0*/
+#define RTC_CNTL_SDIO_EN_INITI  (BIT(15))
+#define RTC_CNTL_SDIO_EN_INITI_M  (BIT(15))
+#define RTC_CNTL_SDIO_EN_INITI_V  0x1
+#define RTC_CNTL_SDIO_EN_INITI_S  15
+/* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */
+/*description: add resistor from ldo output to ground. 0: no res*/
+#define RTC_CNTL_SDIO_INITI  0x00000003
+#define RTC_CNTL_SDIO_INITI_M  ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S))
+#define RTC_CNTL_SDIO_INITI_V  0x3
+#define RTC_CNTL_SDIO_INITI_S  13
+/* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */
+/*description: ability to prevent LDO from overshoot*/
+#define RTC_CNTL_SDIO_DCAP  0x00000003
+#define RTC_CNTL_SDIO_DCAP_M  ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S))
+#define RTC_CNTL_SDIO_DCAP_V  0x3
+#define RTC_CNTL_SDIO_DCAP_S  11
+/* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */
+/*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/
+#define RTC_CNTL_SDIO_DTHDRV  0x00000003
+#define RTC_CNTL_SDIO_DTHDRV_M  ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S))
+#define RTC_CNTL_SDIO_DTHDRV_V  0x3
+#define RTC_CNTL_SDIO_DTHDRV_S  9
+/* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */
+/*description: timer count to apply reg_sdio_dcap after sdio power on*/
+#define RTC_CNTL_SDIO_TIMER_TARGET  0x000000FF
+#define RTC_CNTL_SDIO_TIMER_TARGET_M  ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S))
+#define RTC_CNTL_SDIO_TIMER_TARGET_V  0xFF
+#define RTC_CNTL_SDIO_TIMER_TARGET_S  0
+
+#define RTC_CNTL_BIAS_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x007C)
+/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */
+/*description: DBG_ATTEN when rtc in monitor state*/
+#define RTC_CNTL_DBG_ATTEN_MONITOR  0x0000000F
+#define RTC_CNTL_DBG_ATTEN_MONITOR_M  ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S))
+#define RTC_CNTL_DBG_ATTEN_MONITOR_V  0xF
+#define RTC_CNTL_DBG_ATTEN_MONITOR_S  22
+/* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */
+/*description: DBG_ATTEN when rtc in sleep state*/
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP  0x0000000F
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M  ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S))
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V  0xF
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S  18
+/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: bias_sleep when rtc in monitor state*/
+#define RTC_CNTL_BIAS_SLEEP_MONITOR  (BIT(17))
+#define RTC_CNTL_BIAS_SLEEP_MONITOR_M  (BIT(17))
+#define RTC_CNTL_BIAS_SLEEP_MONITOR_V  0x1
+#define RTC_CNTL_BIAS_SLEEP_MONITOR_S  17
+/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: bias_sleep when rtc in sleep_state*/
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP  (BIT(16))
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M  (BIT(16))
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V  0x1
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S  16
+/* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: xpd cur when rtc in monitor state*/
+#define RTC_CNTL_PD_CUR_MONITOR  (BIT(15))
+#define RTC_CNTL_PD_CUR_MONITOR_M  (BIT(15))
+#define RTC_CNTL_PD_CUR_MONITOR_V  0x1
+#define RTC_CNTL_PD_CUR_MONITOR_S  15
+/* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: xpd cur when rtc in sleep_state*/
+#define RTC_CNTL_PD_CUR_DEEP_SLP  (BIT(14))
+#define RTC_CNTL_PD_CUR_DEEP_SLP_M  (BIT(14))
+#define RTC_CNTL_PD_CUR_DEEP_SLP_V  0x1
+#define RTC_CNTL_PD_CUR_DEEP_SLP_S  14
+/* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BIAS_BUF_MONITOR  (BIT(13))
+#define RTC_CNTL_BIAS_BUF_MONITOR_M  (BIT(13))
+#define RTC_CNTL_BIAS_BUF_MONITOR_V  0x1
+#define RTC_CNTL_BIAS_BUF_MONITOR_S  13
+/* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP  (BIT(12))
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M  (BIT(12))
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V  0x1
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S  12
+/* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: */
+#define RTC_CNTL_BIAS_BUF_WAKE  (BIT(11))
+#define RTC_CNTL_BIAS_BUF_WAKE_M  (BIT(11))
+#define RTC_CNTL_BIAS_BUF_WAKE_V  0x1
+#define RTC_CNTL_BIAS_BUF_WAKE_S  11
+/* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BIAS_BUF_IDLE  (BIT(10))
+#define RTC_CNTL_BIAS_BUF_IDLE_M  (BIT(10))
+#define RTC_CNTL_BIAS_BUF_IDLE_V  0x1
+#define RTC_CNTL_BIAS_BUF_IDLE_S  10
+/* RTC_CNTL_DG_VDD_DRV_B_SLP_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN  (BIT(8))
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_M  (BIT(8))
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_V  0x1
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_S  8
+/* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define RTC_CNTL_DG_VDD_DRV_B_SLP  0x000000FF
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_M  ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S))
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_V  0xFF
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_S  0
+
+#define RTC_CNTL_REG          (DR_REG_RTCCNTL_BASE + 0x0080)
+/* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_REGULATOR_FORCE_PU  (BIT(31))
+#define RTC_CNTL_REGULATOR_FORCE_PU_M  (BIT(31))
+#define RTC_CNTL_REGULATOR_FORCE_PU_V  0x1
+#define RTC_CNTL_REGULATOR_FORCE_PU_S  31
+/* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: RTC_REG force power down (for RTC_REG power down means decrease
+ the voltage to 0.8v or lower )*/
+#define RTC_CNTL_REGULATOR_FORCE_PD  (BIT(30))
+#define RTC_CNTL_REGULATOR_FORCE_PD_M  (BIT(30))
+#define RTC_CNTL_REGULATOR_FORCE_PD_V  0x1
+#define RTC_CNTL_REGULATOR_FORCE_PD_S  30
+/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */
+/*description: RTC_DBOOST force power up*/
+#define RTC_CNTL_DBOOST_FORCE_PU  (BIT(29))
+#define RTC_CNTL_DBOOST_FORCE_PU_M  (BIT(29))
+#define RTC_CNTL_DBOOST_FORCE_PU_V  0x1
+#define RTC_CNTL_DBOOST_FORCE_PU_S  29
+/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: RTC_DBOOST force power down*/
+#define RTC_CNTL_DBOOST_FORCE_PD  (BIT(28))
+#define RTC_CNTL_DBOOST_FORCE_PD_M  (BIT(28))
+#define RTC_CNTL_DBOOST_FORCE_PD_V  0x1
+#define RTC_CNTL_DBOOST_FORCE_PD_S  28
+/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
+ * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
+ * Valid if RTC_CNTL_DBG_ATTEN is 0.
+ */
+#define RTC_CNTL_DIG_DBIAS_0V85  0
+#define RTC_CNTL_DIG_DBIAS_0V90  1
+#define RTC_CNTL_DIG_DBIAS_0V95  2
+#define RTC_CNTL_DIG_DBIAS_1V00  3
+#define RTC_CNTL_DIG_DBIAS_1V05  4
+#define RTC_CNTL_DIG_DBIAS_1V10  5
+#define RTC_CNTL_DIG_DBIAS_1V15  6
+#define RTC_CNTL_DIG_DBIAS_1V20  7
+
+/* The value of 1V00 can be adjusted between 0~3*/
+#define RTC_CNTL_DBIAS_1V00  0
+#define RTC_CNTL_DBIAS_1V05  4
+#define RTC_CNTL_DBIAS_1V10  5
+#define RTC_CNTL_DBIAS_1V15  6
+#define RTC_CNTL_DBIAS_1V20  7
+
+/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */
+/*description: SCK_DCAP*/
+#define RTC_CNTL_SCK_DCAP  0x000000FF
+#define RTC_CNTL_SCK_DCAP_M  ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S))
+#define RTC_CNTL_SCK_DCAP_V  0xFF
+#define RTC_CNTL_SCK_DCAP_S  14
+#define RTC_CNTL_SCK_DCAP_DEFAULT   255
+/* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_DIG_CAL_EN  (BIT(7))
+#define RTC_CNTL_DIG_CAL_EN_M  (BIT(7))
+#define RTC_CNTL_DIG_CAL_EN_V  0x1
+#define RTC_CNTL_DIG_CAL_EN_S  7
+
+#define RTC_CNTL_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x0084)
+/* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: rtc pad force hold*/
+#define RTC_CNTL_PAD_FORCE_HOLD  (BIT(21))
+#define RTC_CNTL_PAD_FORCE_HOLD_M  (BIT(21))
+#define RTC_CNTL_PAD_FORCE_HOLD_V  0x1
+#define RTC_CNTL_PAD_FORCE_HOLD_S  21
+
+#define RTC_CNTL_DIG_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x0088)
+/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_DG_WRAP_PD_EN  (BIT(31))
+#define RTC_CNTL_DG_WRAP_PD_EN_M  (BIT(31))
+#define RTC_CNTL_DG_WRAP_PD_EN_V  0x1
+#define RTC_CNTL_DG_WRAP_PD_EN_S  31
+/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: enable power down wifi in sleep*/
+#define RTC_CNTL_WIFI_PD_EN  (BIT(30))
+#define RTC_CNTL_WIFI_PD_EN_M  (BIT(30))
+#define RTC_CNTL_WIFI_PD_EN_V  0x1
+#define RTC_CNTL_WIFI_PD_EN_S  30
+/* RTC_CNTL_CPU_TOP_PD_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_CPU_TOP_PD_EN  (BIT(29))
+#define RTC_CNTL_CPU_TOP_PD_EN_M  (BIT(29))
+#define RTC_CNTL_CPU_TOP_PD_EN_V  0x1
+#define RTC_CNTL_CPU_TOP_PD_EN_S  29
+/* RTC_CNTL_DG_PERI_PD_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_DG_PERI_PD_EN  (BIT(28))
+#define RTC_CNTL_DG_PERI_PD_EN_M  (BIT(28))
+#define RTC_CNTL_DG_PERI_PD_EN_V  0x1
+#define RTC_CNTL_DG_PERI_PD_EN_S  28
+/* RTC_CNTL_BT_PD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BT_PD_EN  (BIT(27))
+#define RTC_CNTL_BT_PD_EN_M  (BIT(27))
+#define RTC_CNTL_BT_PD_EN_V  0x1
+#define RTC_CNTL_BT_PD_EN_S  27
+/* RTC_CNTL_CPU_TOP_FORCE_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: */
+#define RTC_CNTL_CPU_TOP_FORCE_PU  (BIT(22))
+#define RTC_CNTL_CPU_TOP_FORCE_PU_M  (BIT(22))
+#define RTC_CNTL_CPU_TOP_FORCE_PU_V  0x1
+#define RTC_CNTL_CPU_TOP_FORCE_PU_S  22
+/* RTC_CNTL_CPU_TOP_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_CPU_TOP_FORCE_PD  (BIT(21))
+#define RTC_CNTL_CPU_TOP_FORCE_PD_M  (BIT(21))
+#define RTC_CNTL_CPU_TOP_FORCE_PD_V  0x1
+#define RTC_CNTL_CPU_TOP_FORCE_PD_S  21
+/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */
+/*description: digital core force power up*/
+#define RTC_CNTL_DG_WRAP_FORCE_PU  (BIT(20))
+#define RTC_CNTL_DG_WRAP_FORCE_PU_M  (BIT(20))
+#define RTC_CNTL_DG_WRAP_FORCE_PU_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_PU_S  20
+/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: digital core force power down*/
+#define RTC_CNTL_DG_WRAP_FORCE_PD  (BIT(19))
+#define RTC_CNTL_DG_WRAP_FORCE_PD_M  (BIT(19))
+#define RTC_CNTL_DG_WRAP_FORCE_PD_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_PD_S  19
+/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */
+/*description: wifi force power up*/
+#define RTC_CNTL_WIFI_FORCE_PU  (BIT(18))
+#define RTC_CNTL_WIFI_FORCE_PU_M  (BIT(18))
+#define RTC_CNTL_WIFI_FORCE_PU_V  0x1
+#define RTC_CNTL_WIFI_FORCE_PU_S  18
+/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: wifi force power down*/
+#define RTC_CNTL_WIFI_FORCE_PD  (BIT(17))
+#define RTC_CNTL_WIFI_FORCE_PD_M  (BIT(17))
+#define RTC_CNTL_WIFI_FORCE_PD_V  0x1
+#define RTC_CNTL_WIFI_FORCE_PD_S  17
+/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: */
+#define RTC_CNTL_FASTMEM_FORCE_LPU  (BIT(16))
+#define RTC_CNTL_FASTMEM_FORCE_LPU_M  (BIT(16))
+#define RTC_CNTL_FASTMEM_FORCE_LPU_V  0x1
+#define RTC_CNTL_FASTMEM_FORCE_LPU_S  16
+/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_FASTMEM_FORCE_LPD  (BIT(15))
+#define RTC_CNTL_FASTMEM_FORCE_LPD_M  (BIT(15))
+#define RTC_CNTL_FASTMEM_FORCE_LPD_V  0x1
+#define RTC_CNTL_FASTMEM_FORCE_LPD_S  15
+/* RTC_CNTL_DG_PERI_FORCE_PU : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: */
+#define RTC_CNTL_DG_PERI_FORCE_PU  (BIT(14))
+#define RTC_CNTL_DG_PERI_FORCE_PU_M  (BIT(14))
+#define RTC_CNTL_DG_PERI_FORCE_PU_V  0x1
+#define RTC_CNTL_DG_PERI_FORCE_PU_S  14
+/* RTC_CNTL_DG_PERI_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_DG_PERI_FORCE_PD  (BIT(13))
+#define RTC_CNTL_DG_PERI_FORCE_PD_M  (BIT(13))
+#define RTC_CNTL_DG_PERI_FORCE_PD_V  0x1
+#define RTC_CNTL_DG_PERI_FORCE_PD_S  13
+/* RTC_CNTL_BT_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_BT_FORCE_PU  (BIT(12))
+#define RTC_CNTL_BT_FORCE_PU_M  (BIT(12))
+#define RTC_CNTL_BT_FORCE_PU_V  0x1
+#define RTC_CNTL_BT_FORCE_PU_S  12
+/* RTC_CNTL_BT_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BT_FORCE_PD  (BIT(11))
+#define RTC_CNTL_BT_FORCE_PD_M  (BIT(11))
+#define RTC_CNTL_BT_FORCE_PD_V  0x1
+#define RTC_CNTL_BT_FORCE_PD_S  11
+/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: memories in digital core force no PD in sleep*/
+#define RTC_CNTL_LSLP_MEM_FORCE_PU  (BIT(4))
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_M  (BIT(4))
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_V  0x1
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_S  4
+/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: memories in digital core force PD in sleep*/
+#define RTC_CNTL_LSLP_MEM_FORCE_PD  (BIT(3))
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_M  (BIT(3))
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_V  0x1
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_S  3
+/* RTC_CNTL_VDD_SPI_PWR_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_VDD_SPI_PWR_FORCE  (BIT(2))
+#define RTC_CNTL_VDD_SPI_PWR_FORCE_M  (BIT(2))
+#define RTC_CNTL_VDD_SPI_PWR_FORCE_V  0x1
+#define RTC_CNTL_VDD_SPI_PWR_FORCE_S  2
+/* RTC_CNTL_VDD_SPI_PWR_DRV : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define RTC_CNTL_VDD_SPI_PWR_DRV  0x00000003
+#define RTC_CNTL_VDD_SPI_PWR_DRV_M  ((RTC_CNTL_VDD_SPI_PWR_DRV_V)<<(RTC_CNTL_VDD_SPI_PWR_DRV_S))
+#define RTC_CNTL_VDD_SPI_PWR_DRV_V  0x3
+#define RTC_CNTL_VDD_SPI_PWR_DRV_S  0
+
+#define RTC_CNTL_DIG_ISO_REG          (DR_REG_RTCCNTL_BASE + 0x008C)
+/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO  (BIT(31))
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M  (BIT(31))
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S  31
+/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: digital core force ISO*/
+#define RTC_CNTL_DG_WRAP_FORCE_ISO  (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_M  (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_S  30
+/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */
+/*description: wifi force no ISO*/
+#define RTC_CNTL_WIFI_FORCE_NOISO  (BIT(29))
+#define RTC_CNTL_WIFI_FORCE_NOISO_M  (BIT(29))
+#define RTC_CNTL_WIFI_FORCE_NOISO_V  0x1
+#define RTC_CNTL_WIFI_FORCE_NOISO_S  29
+/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: wifi force ISO*/
+#define RTC_CNTL_WIFI_FORCE_ISO  (BIT(28))
+#define RTC_CNTL_WIFI_FORCE_ISO_M  (BIT(28))
+#define RTC_CNTL_WIFI_FORCE_ISO_V  0x1
+#define RTC_CNTL_WIFI_FORCE_ISO_S  28
+/* RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */
+/*description: cpu force no ISO*/
+#define RTC_CNTL_CPU_TOP_FORCE_NOISO  (BIT(27))
+#define RTC_CNTL_CPU_TOP_FORCE_NOISO_M  (BIT(27))
+#define RTC_CNTL_CPU_TOP_FORCE_NOISO_V  0x1
+#define RTC_CNTL_CPU_TOP_FORCE_NOISO_S  27
+/* RTC_CNTL_CPU_TOP_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: cpu force ISO*/
+#define RTC_CNTL_CPU_TOP_FORCE_ISO  (BIT(26))
+#define RTC_CNTL_CPU_TOP_FORCE_ISO_M  (BIT(26))
+#define RTC_CNTL_CPU_TOP_FORCE_ISO_V  0x1
+#define RTC_CNTL_CPU_TOP_FORCE_ISO_S  26
+/* RTC_CNTL_DG_PERI_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_DG_PERI_FORCE_NOISO  (BIT(25))
+#define RTC_CNTL_DG_PERI_FORCE_NOISO_M  (BIT(25))
+#define RTC_CNTL_DG_PERI_FORCE_NOISO_V  0x1
+#define RTC_CNTL_DG_PERI_FORCE_NOISO_S  25
+/* RTC_CNTL_DG_PERI_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_DG_PERI_FORCE_ISO  (BIT(24))
+#define RTC_CNTL_DG_PERI_FORCE_ISO_M  (BIT(24))
+#define RTC_CNTL_DG_PERI_FORCE_ISO_V  0x1
+#define RTC_CNTL_DG_PERI_FORCE_ISO_S  24
+/* RTC_CNTL_BT_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_BT_FORCE_NOISO  (BIT(23))
+#define RTC_CNTL_BT_FORCE_NOISO_M  (BIT(23))
+#define RTC_CNTL_BT_FORCE_NOISO_V  0x1
+#define RTC_CNTL_BT_FORCE_NOISO_S  23
+/* RTC_CNTL_BT_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_BT_FORCE_ISO  (BIT(22))
+#define RTC_CNTL_BT_FORCE_ISO_M  (BIT(22))
+#define RTC_CNTL_BT_FORCE_ISO_V  0x1
+#define RTC_CNTL_BT_FORCE_ISO_S  22
+/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: digital pad force hold*/
+#define RTC_CNTL_DG_PAD_FORCE_HOLD  (BIT(15))
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_M  (BIT(15))
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_S  15
+/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */
+/*description: digital pad force un-hold*/
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD  (BIT(14))
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M  (BIT(14))
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S  14
+/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: digital pad force ISO*/
+#define RTC_CNTL_DG_PAD_FORCE_ISO  (BIT(13))
+#define RTC_CNTL_DG_PAD_FORCE_ISO_M  (BIT(13))
+#define RTC_CNTL_DG_PAD_FORCE_ISO_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_ISO_S  13
+/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */
+/*description: digital pad force no ISO*/
+#define RTC_CNTL_DG_PAD_FORCE_NOISO  (BIT(12))
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_M  (BIT(12))
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_S  12
+/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: digital pad enable auto-hold*/
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN  (BIT(11))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M  (BIT(11))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V  0x1
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S  11
+/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */
+/*description: wtite only register to clear digital pad auto-hold*/
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD  (BIT(10))
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M  (BIT(10))
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V  0x1
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S  10
+/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: read only register to indicate digital pad auto-hold status*/
+#define RTC_CNTL_DG_PAD_AUTOHOLD  (BIT(9))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_M  (BIT(9))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_V  0x1
+#define RTC_CNTL_DG_PAD_AUTOHOLD_S  9
+/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_DIG_ISO_FORCE_ON  (BIT(8))
+#define RTC_CNTL_DIG_ISO_FORCE_ON_M  (BIT(8))
+#define RTC_CNTL_DIG_ISO_FORCE_ON_V  0x1
+#define RTC_CNTL_DIG_ISO_FORCE_ON_S  8
+/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_DIG_ISO_FORCE_OFF  (BIT(7))
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_M  (BIT(7))
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_V  0x1
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_S  7
+
+#define RTC_CNTL_WDTCONFIG0_REG          (DR_REG_RTCCNTL_BASE + 0x0090)
+/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define RTC_CNTL_WDT_EN  (BIT(31))
+#define RTC_CNTL_WDT_EN_M  (BIT(31))
+#define RTC_CNTL_WDT_EN_V  0x1
+#define RTC_CNTL_WDT_EN_S  31
+/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en*/
+#define RTC_CNTL_WDT_STG0  0x00000007
+#define RTC_CNTL_WDT_STG0_M  ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S))
+#define RTC_CNTL_WDT_STG0_V  0x7
+#define RTC_CNTL_WDT_STG0_S  28
+/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en*/
+#define RTC_CNTL_WDT_STG1  0x00000007
+#define RTC_CNTL_WDT_STG1_M  ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S))
+#define RTC_CNTL_WDT_STG1_V  0x7
+#define RTC_CNTL_WDT_STG1_S  25
+/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en*/
+#define RTC_CNTL_WDT_STG2  0x00000007
+#define RTC_CNTL_WDT_STG2_M  ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S))
+#define RTC_CNTL_WDT_STG2_V  0x7
+#define RTC_CNTL_WDT_STG2_S  22
+/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en*/
+#define RTC_CNTL_WDT_STG3  0x00000007
+#define RTC_CNTL_WDT_STG3_M  ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S))
+#define RTC_CNTL_WDT_STG3_V  0x7
+#define RTC_CNTL_WDT_STG3_S  19
+/* RTC_CNTL_WDT_STGX : */
+/*description: stage action selection values */
+#define RTC_WDT_STG_SEL_OFF             0
+#define RTC_WDT_STG_SEL_INT             1
+#define RTC_WDT_STG_SEL_RESET_CPU       2
+#define RTC_WDT_STG_SEL_RESET_SYSTEM    3
+#define RTC_WDT_STG_SEL_RESET_RTC       4
+
+/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */
+/*description: CPU reset counter length*/
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH  0x00000007
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M  ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S))
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V  0x7
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S  16
+/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */
+/*description: system reset counter length*/
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH  0x00000007
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M  ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S))
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V  0x7
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S  13
+/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: enable WDT in flash boot*/
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN  (BIT(12))
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M  (BIT(12))
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V  0x1
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S  12
+/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: enable WDT reset PRO CPU*/
+#define RTC_CNTL_WDT_PROCPU_RESET_EN  (BIT(11))
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_M  (BIT(11))
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_V  0x1
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_S  11
+/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: enable WDT reset APP CPU*/
+#define RTC_CNTL_WDT_APPCPU_RESET_EN  (BIT(10))
+#define RTC_CNTL_WDT_APPCPU_RESET_EN_M  (BIT(10))
+#define RTC_CNTL_WDT_APPCPU_RESET_EN_V  0x1
+#define RTC_CNTL_WDT_APPCPU_RESET_EN_S  10
+/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */
+/*description: pause WDT in sleep*/
+#define RTC_CNTL_WDT_PAUSE_IN_SLP  (BIT(9))
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_M  (BIT(9))
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_V  0x1
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_S  9
+/* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: wdt reset whole chip enable*/
+#define RTC_CNTL_WDT_CHIP_RESET_EN  (BIT(8))
+#define RTC_CNTL_WDT_CHIP_RESET_EN_M  (BIT(8))
+#define RTC_CNTL_WDT_CHIP_RESET_EN_V  0x1
+#define RTC_CNTL_WDT_CHIP_RESET_EN_S  8
+/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */
+/*description: chip reset siginal pulse width*/
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH  0x000000FF
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M  ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S))
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V  0xFF
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S  0
+
+#define RTC_CNTL_WDTCONFIG1_REG          (DR_REG_RTCCNTL_BASE + 0x0094)
+/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */
+/*description: */
+#define RTC_CNTL_WDT_STG0_HOLD  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG0_HOLD_M  ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S))
+#define RTC_CNTL_WDT_STG0_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG0_HOLD_S  0
+
+#define RTC_CNTL_WDTCONFIG2_REG          (DR_REG_RTCCNTL_BASE + 0x0098)
+/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */
+/*description: */
+#define RTC_CNTL_WDT_STG1_HOLD  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG1_HOLD_M  ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S))
+#define RTC_CNTL_WDT_STG1_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG1_HOLD_S  0
+
+#define RTC_CNTL_WDTCONFIG3_REG          (DR_REG_RTCCNTL_BASE + 0x009C)
+/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
+/*description: */
+#define RTC_CNTL_WDT_STG2_HOLD  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG2_HOLD_M  ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S))
+#define RTC_CNTL_WDT_STG2_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG2_HOLD_S  0
+
+#define RTC_CNTL_WDTCONFIG4_REG          (DR_REG_RTCCNTL_BASE + 0x00A0)
+/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
+/*description: */
+#define RTC_CNTL_WDT_STG3_HOLD  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG3_HOLD_M  ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S))
+#define RTC_CNTL_WDT_STG3_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG3_HOLD_S  0
+
+#define RTC_CNTL_WDTFEED_REG          (DR_REG_RTCCNTL_BASE + 0x00A4)
+/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_WDT_FEED  (BIT(31))
+#define RTC_CNTL_WDT_FEED_M  (BIT(31))
+#define RTC_CNTL_WDT_FEED_V  0x1
+#define RTC_CNTL_WDT_FEED_S  31
+
+#define RTC_CNTL_WDTWPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0x00A8)
+/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
+/*description: */
+#define RTC_CNTL_WDT_WKEY  0xFFFFFFFF
+#define RTC_CNTL_WDT_WKEY_M  ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S))
+#define RTC_CNTL_WDT_WKEY_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_WKEY_S  0
+
+#define RTC_CNTL_SWD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x00AC)
+/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: automatically feed swd when int comes*/
+#define RTC_CNTL_SWD_AUTO_FEED_EN  (BIT(31))
+#define RTC_CNTL_SWD_AUTO_FEED_EN_M  (BIT(31))
+#define RTC_CNTL_SWD_AUTO_FEED_EN_V  0x1
+#define RTC_CNTL_SWD_AUTO_FEED_EN_S  31
+/* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: disabel SWD*/
+#define RTC_CNTL_SWD_DISABLE  (BIT(30))
+#define RTC_CNTL_SWD_DISABLE_M  (BIT(30))
+#define RTC_CNTL_SWD_DISABLE_V  0x1
+#define RTC_CNTL_SWD_DISABLE_S  30
+/* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Sw feed swd*/
+#define RTC_CNTL_SWD_FEED  (BIT(29))
+#define RTC_CNTL_SWD_FEED_M  (BIT(29))
+#define RTC_CNTL_SWD_FEED_V  0x1
+#define RTC_CNTL_SWD_FEED_S  29
+/* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: reset swd reset flag*/
+#define RTC_CNTL_SWD_RST_FLAG_CLR  (BIT(28))
+#define RTC_CNTL_SWD_RST_FLAG_CLR_M  (BIT(28))
+#define RTC_CNTL_SWD_RST_FLAG_CLR_V  0x1
+#define RTC_CNTL_SWD_RST_FLAG_CLR_S  28
+/* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */
+/*description: adjust signal width send to swd*/
+#define RTC_CNTL_SWD_SIGNAL_WIDTH  0x000003FF
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_M  ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S))
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_V  0x3FF
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_S  18
+/* RTC_CNTL_SWD_BYPASS_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_SWD_BYPASS_RST  (BIT(17))
+#define RTC_CNTL_SWD_BYPASS_RST_M  (BIT(17))
+#define RTC_CNTL_SWD_BYPASS_RST_V  0x1
+#define RTC_CNTL_SWD_BYPASS_RST_S  17
+/* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: swd interrupt for feeding*/
+#define RTC_CNTL_SWD_FEED_INT  (BIT(1))
+#define RTC_CNTL_SWD_FEED_INT_M  (BIT(1))
+#define RTC_CNTL_SWD_FEED_INT_V  0x1
+#define RTC_CNTL_SWD_FEED_INT_S  1
+/* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: swd reset flag*/
+#define RTC_CNTL_SWD_RESET_FLAG  (BIT(0))
+#define RTC_CNTL_SWD_RESET_FLAG_M  (BIT(0))
+#define RTC_CNTL_SWD_RESET_FLAG_V  0x1
+#define RTC_CNTL_SWD_RESET_FLAG_S  0
+
+#define RTC_CNTL_SWD_WPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0x00B0)
+/* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */
+/*description: */
+#define RTC_CNTL_SWD_WKEY  0xFFFFFFFF
+#define RTC_CNTL_SWD_WKEY_M  ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S))
+#define RTC_CNTL_SWD_WKEY_V  0xFFFFFFFF
+#define RTC_CNTL_SWD_WKEY_S  0
+
+#define RTC_CNTL_SW_CPU_STALL_REG          (DR_REG_RTCCNTL_BASE + 0x00B4)
+/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */
+/*description: */
+#define RTC_CNTL_SW_STALL_PROCPU_C1  0x0000003F
+#define RTC_CNTL_SW_STALL_PROCPU_C1_M  ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S))
+#define RTC_CNTL_SW_STALL_PROCPU_C1_V  0x3F
+#define RTC_CNTL_SW_STALL_PROCPU_C1_S  26
+/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */
+/*description: {reg_sw_stall_appcpu_c1[5:0]*/
+#define RTC_CNTL_SW_STALL_APPCPU_C1  0x0000003F
+#define RTC_CNTL_SW_STALL_APPCPU_C1_M  ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S))
+#define RTC_CNTL_SW_STALL_APPCPU_C1_V  0x3F
+#define RTC_CNTL_SW_STALL_APPCPU_C1_S  20
+
+#define RTC_CNTL_STORE4_REG          (DR_REG_RTCCNTL_BASE + 0x00B8)
+/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH4  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH4_M  ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S))
+#define RTC_CNTL_SCRATCH4_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH4_S  0
+
+#define RTC_CNTL_STORE5_REG          (DR_REG_RTCCNTL_BASE + 0x00BC)
+/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH5  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH5_M  ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S))
+#define RTC_CNTL_SCRATCH5_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH5_S  0
+
+#define RTC_CNTL_STORE6_REG          (DR_REG_RTCCNTL_BASE + 0x00C0)
+/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH6  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH6_M  ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S))
+#define RTC_CNTL_SCRATCH6_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH6_S  0
+
+#define RTC_CNTL_STORE7_REG          (DR_REG_RTCCNTL_BASE + 0x00C4)
+/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH7  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH7_M  ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S))
+#define RTC_CNTL_SCRATCH7_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH7_S  0
+
+#define RTC_CNTL_LOW_POWER_ST_REG          (DR_REG_RTCCNTL_BASE + 0x00C8)
+/* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */
+/*description: rtc main state machine status*/
+#define RTC_CNTL_MAIN_STATE  0x0000000F
+#define RTC_CNTL_MAIN_STATE_M  ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S))
+#define RTC_CNTL_MAIN_STATE_V  0xF
+#define RTC_CNTL_MAIN_STATE_S  28
+/* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: rtc main state machine is in idle state*/
+#define RTC_CNTL_MAIN_STATE_IN_IDLE  (BIT(27))
+#define RTC_CNTL_MAIN_STATE_IN_IDLE_M  (BIT(27))
+#define RTC_CNTL_MAIN_STATE_IN_IDLE_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_IDLE_S  27
+/* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: rtc main state machine is in sleep state*/
+#define RTC_CNTL_MAIN_STATE_IN_SLP  (BIT(26))
+#define RTC_CNTL_MAIN_STATE_IN_SLP_M  (BIT(26))
+#define RTC_CNTL_MAIN_STATE_IN_SLP_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_SLP_S  26
+/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: rtc main state machine is in wait xtal state*/
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL  (BIT(25))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M  (BIT(25))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S  25
+/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: rtc main state machine is in wait pll state*/
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL  (BIT(24))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M  (BIT(24))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S  24
+/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: rtc main state machine is in wait 8m state*/
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M  (BIT(23))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M  (BIT(23))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S  23
+/* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: rtc main state machine is in the states of low power*/
+#define RTC_CNTL_IN_LOW_POWER_STATE  (BIT(22))
+#define RTC_CNTL_IN_LOW_POWER_STATE_M  (BIT(22))
+#define RTC_CNTL_IN_LOW_POWER_STATE_V  0x1
+#define RTC_CNTL_IN_LOW_POWER_STATE_S  22
+/* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: rtc main state machine is in the states of wakeup process*/
+#define RTC_CNTL_IN_WAKEUP_STATE  (BIT(21))
+#define RTC_CNTL_IN_WAKEUP_STATE_M  (BIT(21))
+#define RTC_CNTL_IN_WAKEUP_STATE_V  0x1
+#define RTC_CNTL_IN_WAKEUP_STATE_S  21
+/* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: rtc main state machine has been waited for some cycles*/
+#define RTC_CNTL_MAIN_STATE_WAIT_END  (BIT(20))
+#define RTC_CNTL_MAIN_STATE_WAIT_END_M  (BIT(20))
+#define RTC_CNTL_MAIN_STATE_WAIT_END_V  0x1
+#define RTC_CNTL_MAIN_STATE_WAIT_END_S  20
+/* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: rtc is ready to receive wake up trigger from wake up source*/
+#define RTC_CNTL_RDY_FOR_WAKEUP  (BIT(19))
+#define RTC_CNTL_RDY_FOR_WAKEUP_M  (BIT(19))
+#define RTC_CNTL_RDY_FOR_WAKEUP_V  0x1
+#define RTC_CNTL_RDY_FOR_WAKEUP_S  19
+/* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: rtc main state machine is in states that pll should be running*/
+#define RTC_CNTL_MAIN_STATE_PLL_ON  (BIT(18))
+#define RTC_CNTL_MAIN_STATE_PLL_ON_M  (BIT(18))
+#define RTC_CNTL_MAIN_STATE_PLL_ON_V  0x1
+#define RTC_CNTL_MAIN_STATE_PLL_ON_S  18
+/* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: no use any more*/
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO  (BIT(17))
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M  (BIT(17))
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V  0x1
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S  17
+/* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: ulp/cocpu is done*/
+#define RTC_CNTL_COCPU_STATE_DONE  (BIT(16))
+#define RTC_CNTL_COCPU_STATE_DONE_M  (BIT(16))
+#define RTC_CNTL_COCPU_STATE_DONE_V  0x1
+#define RTC_CNTL_COCPU_STATE_DONE_S  16
+/* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: ulp/cocpu is in sleep state*/
+#define RTC_CNTL_COCPU_STATE_SLP  (BIT(15))
+#define RTC_CNTL_COCPU_STATE_SLP_M  (BIT(15))
+#define RTC_CNTL_COCPU_STATE_SLP_V  0x1
+#define RTC_CNTL_COCPU_STATE_SLP_S  15
+/* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: ulp/cocpu is about to working. Switch rtc main state*/
+#define RTC_CNTL_COCPU_STATE_SWITCH  (BIT(14))
+#define RTC_CNTL_COCPU_STATE_SWITCH_M  (BIT(14))
+#define RTC_CNTL_COCPU_STATE_SWITCH_V  0x1
+#define RTC_CNTL_COCPU_STATE_SWITCH_S  14
+/* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: ulp/cocpu should start to work*/
+#define RTC_CNTL_COCPU_STATE_START  (BIT(13))
+#define RTC_CNTL_COCPU_STATE_START_M  (BIT(13))
+#define RTC_CNTL_COCPU_STATE_START_V  0x1
+#define RTC_CNTL_COCPU_STATE_START_S  13
+/* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: touch is done*/
+#define RTC_CNTL_TOUCH_STATE_DONE  (BIT(12))
+#define RTC_CNTL_TOUCH_STATE_DONE_M  (BIT(12))
+#define RTC_CNTL_TOUCH_STATE_DONE_V  0x1
+#define RTC_CNTL_TOUCH_STATE_DONE_S  12
+/* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: touch is in sleep state*/
+#define RTC_CNTL_TOUCH_STATE_SLP  (BIT(11))
+#define RTC_CNTL_TOUCH_STATE_SLP_M  (BIT(11))
+#define RTC_CNTL_TOUCH_STATE_SLP_V  0x1
+#define RTC_CNTL_TOUCH_STATE_SLP_S  11
+/* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: touch is about to working. Switch rtc main state*/
+#define RTC_CNTL_TOUCH_STATE_SWITCH  (BIT(10))
+#define RTC_CNTL_TOUCH_STATE_SWITCH_M  (BIT(10))
+#define RTC_CNTL_TOUCH_STATE_SWITCH_V  0x1
+#define RTC_CNTL_TOUCH_STATE_SWITCH_S  10
+/* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: touch should start to work*/
+#define RTC_CNTL_TOUCH_STATE_START  (BIT(9))
+#define RTC_CNTL_TOUCH_STATE_START_M  (BIT(9))
+#define RTC_CNTL_TOUCH_STATE_START_V  0x1
+#define RTC_CNTL_TOUCH_STATE_START_S  9
+/* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: digital wrap power down*/
+#define RTC_CNTL_XPD_DIG  (BIT(8))
+#define RTC_CNTL_XPD_DIG_M  (BIT(8))
+#define RTC_CNTL_XPD_DIG_V  0x1
+#define RTC_CNTL_XPD_DIG_S  8
+/* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: digital wrap iso*/
+#define RTC_CNTL_DIG_ISO  (BIT(7))
+#define RTC_CNTL_DIG_ISO_M  (BIT(7))
+#define RTC_CNTL_DIG_ISO_V  0x1
+#define RTC_CNTL_DIG_ISO_S  7
+/* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: wifi wrap power down*/
+#define RTC_CNTL_XPD_WIFI  (BIT(6))
+#define RTC_CNTL_XPD_WIFI_M  (BIT(6))
+#define RTC_CNTL_XPD_WIFI_V  0x1
+#define RTC_CNTL_XPD_WIFI_S  6
+/* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: wifi iso*/
+#define RTC_CNTL_WIFI_ISO  (BIT(5))
+#define RTC_CNTL_WIFI_ISO_M  (BIT(5))
+#define RTC_CNTL_WIFI_ISO_V  0x1
+#define RTC_CNTL_WIFI_ISO_S  5
+/* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: rtc peripheral power down*/
+#define RTC_CNTL_XPD_RTC_PERI  (BIT(4))
+#define RTC_CNTL_XPD_RTC_PERI_M  (BIT(4))
+#define RTC_CNTL_XPD_RTC_PERI_V  0x1
+#define RTC_CNTL_XPD_RTC_PERI_S  4
+/* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: rtc peripheral iso*/
+#define RTC_CNTL_PERI_ISO  (BIT(3))
+#define RTC_CNTL_PERI_ISO_M  (BIT(3))
+#define RTC_CNTL_PERI_ISO_V  0x1
+#define RTC_CNTL_PERI_ISO_S  3
+/* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: External DCDC power down*/
+#define RTC_CNTL_XPD_DIG_DCDC  (BIT(2))
+#define RTC_CNTL_XPD_DIG_DCDC_M  (BIT(2))
+#define RTC_CNTL_XPD_DIG_DCDC_V  0x1
+#define RTC_CNTL_XPD_DIG_DCDC_S  2
+/* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: rom0 power down*/
+#define RTC_CNTL_XPD_ROM0  (BIT(0))
+#define RTC_CNTL_XPD_ROM0_M  (BIT(0))
+#define RTC_CNTL_XPD_ROM0_V  0x1
+#define RTC_CNTL_XPD_ROM0_S  0
+
+#define RTC_CNTL_DIAG0_REG          (DR_REG_RTCCNTL_BASE + 0x00CC)
+/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_LOW_POWER_DIAG1  0xFFFFFFFF
+#define RTC_CNTL_LOW_POWER_DIAG1_M  ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S))
+#define RTC_CNTL_LOW_POWER_DIAG1_V  0xFFFFFFFF
+#define RTC_CNTL_LOW_POWER_DIAG1_S  0
+
+#define RTC_CNTL_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0x00D0)
+/* RTC_CNTL_GPIO_PIN5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN5_HOLD  (BIT(5))
+#define RTC_CNTL_GPIO_PIN5_HOLD_M  (BIT(5))
+#define RTC_CNTL_GPIO_PIN5_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN5_HOLD_S  5
+/* RTC_CNTL_GPIO_PIN4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN4_HOLD  (BIT(4))
+#define RTC_CNTL_GPIO_PIN4_HOLD_M  (BIT(4))
+#define RTC_CNTL_GPIO_PIN4_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN4_HOLD_S  4
+/* RTC_CNTL_GPIO_PIN3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN3_HOLD  (BIT(3))
+#define RTC_CNTL_GPIO_PIN3_HOLD_M  (BIT(3))
+#define RTC_CNTL_GPIO_PIN3_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN3_HOLD_S  3
+/* RTC_CNTL_GPIO_PIN2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN2_HOLD  (BIT(2))
+#define RTC_CNTL_GPIO_PIN2_HOLD_M  (BIT(2))
+#define RTC_CNTL_GPIO_PIN2_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN2_HOLD_S  2
+/* RTC_CNTL_GPIO_PIN1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN1_HOLD  (BIT(1))
+#define RTC_CNTL_GPIO_PIN1_HOLD_M  (BIT(1))
+#define RTC_CNTL_GPIO_PIN1_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN1_HOLD_S  1
+/* RTC_CNTL_GPIO_PIN0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN0_HOLD  (BIT(0))
+#define RTC_CNTL_GPIO_PIN0_HOLD_M  (BIT(0))
+#define RTC_CNTL_GPIO_PIN0_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN0_HOLD_S  0
+
+#define RTC_CNTL_DIG_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0x00D4)
+/* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define RTC_CNTL_DIG_PAD_HOLD  0xFFFFFFFF
+#define RTC_CNTL_DIG_PAD_HOLD_M  ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S))
+#define RTC_CNTL_DIG_PAD_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_DIG_PAD_HOLD_S  0
+
+#define RTC_CNTL_BROWN_OUT_REG          (DR_REG_RTCCNTL_BASE + 0x00D8)
+/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BROWN_OUT_DET  (BIT(31))
+#define RTC_CNTL_BROWN_OUT_DET_M  (BIT(31))
+#define RTC_CNTL_BROWN_OUT_DET_V  0x1
+#define RTC_CNTL_BROWN_OUT_DET_S  31
+/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: enable brown out*/
+#define RTC_CNTL_BROWN_OUT_ENA  (BIT(30))
+#define RTC_CNTL_BROWN_OUT_ENA_M  (BIT(30))
+#define RTC_CNTL_BROWN_OUT_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_ENA_S  30
+/* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: clear brown out counter*/
+#define RTC_CNTL_BROWN_OUT_CNT_CLR  (BIT(29))
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_M  (BIT(29))
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_V  0x1
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_S  29
+/* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN  (BIT(28))
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M  (BIT(28))
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V  0x1
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S  28
+/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: 1:  4-pos reset*/
+#define RTC_CNTL_BROWN_OUT_RST_SEL  (BIT(27))
+#define RTC_CNTL_BROWN_OUT_RST_SEL_M  (BIT(27))
+#define RTC_CNTL_BROWN_OUT_RST_SEL_V  0x1
+#define RTC_CNTL_BROWN_OUT_RST_SEL_S  27
+/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: enable brown out reset*/
+#define RTC_CNTL_BROWN_OUT_RST_ENA  (BIT(26))
+#define RTC_CNTL_BROWN_OUT_RST_ENA_M  (BIT(26))
+#define RTC_CNTL_BROWN_OUT_RST_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_RST_ENA_S  26
+/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */
+/*description: brown out reset wait cycles*/
+#define RTC_CNTL_BROWN_OUT_RST_WAIT  0x000003FF
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_M  ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S))
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_V  0x3FF
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_S  16
+/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable power down RF when brown out happens*/
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA  (BIT(15))
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M  (BIT(15))
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S  15
+/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: enable close flash when brown out happens*/
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA  (BIT(14))
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M  (BIT(14))
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S  14
+/* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h1 ; */
+/*description: brown out interrupt wait cycles*/
+#define RTC_CNTL_BROWN_OUT_INT_WAIT  0x000003FF
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_M  ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S))
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_V  0x3FF
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_S  4
+
+#define RTC_CNTL_TIME_LOW1_REG          (DR_REG_RTCCNTL_BASE + 0x00DC)
+/* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: RTC timer low 32 bits*/
+#define RTC_CNTL_TIMER_VALUE1_LOW  0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE1_LOW_M  ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S))
+#define RTC_CNTL_TIMER_VALUE1_LOW_V  0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE1_LOW_S  0
+
+#define RTC_CNTL_TIME_HIGH1_REG          (DR_REG_RTCCNTL_BASE + 0x00E0)
+/* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC timer high 16 bits*/
+#define RTC_CNTL_TIMER_VALUE1_HIGH  0x0000FFFF
+#define RTC_CNTL_TIMER_VALUE1_HIGH_M  ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S))
+#define RTC_CNTL_TIMER_VALUE1_HIGH_V  0xFFFF
+#define RTC_CNTL_TIMER_VALUE1_HIGH_S  0
+
+#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG          (DR_REG_RTCCNTL_BASE + 0x00E4)
+/* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: xtal 32k watch dog backup clock factor*/
+#define RTC_CNTL_XTAL32K_CLK_FACTOR  0xFFFFFFFF
+#define RTC_CNTL_XTAL32K_CLK_FACTOR_M  ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S))
+#define RTC_CNTL_XTAL32K_CLK_FACTOR_V  0xFFFFFFFF
+#define RTC_CNTL_XTAL32K_CLK_FACTOR_S  0
+
+#define RTC_CNTL_XTAL32K_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x00E8)
+/* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: if restarted xtal32k period is smaller than this*/
+#define RTC_CNTL_XTAL32K_STABLE_THRES  0x0000000F
+#define RTC_CNTL_XTAL32K_STABLE_THRES_M  ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S))
+#define RTC_CNTL_XTAL32K_STABLE_THRES_V  0xF
+#define RTC_CNTL_XTAL32K_STABLE_THRES_S  28
+/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */
+/*description: If no clock detected for this amount of time*/
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT  0x000000FF
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M  ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S))
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V  0xFF
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S  20
+/* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */
+/*description: cycles to wait to repower on xtal 32k*/
+#define RTC_CNTL_XTAL32K_RESTART_WAIT  0x0000FFFF
+#define RTC_CNTL_XTAL32K_RESTART_WAIT_M  ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S))
+#define RTC_CNTL_XTAL32K_RESTART_WAIT_V  0xFFFF
+#define RTC_CNTL_XTAL32K_RESTART_WAIT_S  4
+/* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: cycles to wait to return noral xtal 32k*/
+#define RTC_CNTL_XTAL32K_RETURN_WAIT  0x0000000F
+#define RTC_CNTL_XTAL32K_RETURN_WAIT_M  ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S))
+#define RTC_CNTL_XTAL32K_RETURN_WAIT_V  0xF
+#define RTC_CNTL_XTAL32K_RETURN_WAIT_S  0
+
+#define RTC_CNTL_USB_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x00EC)
+/* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_IO_MUX_RESET_DISABLE  (BIT(18))
+#define RTC_CNTL_IO_MUX_RESET_DISABLE_M  (BIT(18))
+#define RTC_CNTL_IO_MUX_RESET_DISABLE_V  0x1
+#define RTC_CNTL_IO_MUX_RESET_DISABLE_S  18
+
+#define RTC_CNTL_SLP_REJECT_CAUSE_REG          (DR_REG_RTCCNTL_BASE + 0x00F0)
+/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[17:0] ;default: 18'd0 ; */
+/*description: sleep reject cause*/
+#define RTC_CNTL_REJECT_CAUSE  0x0003FFFF
+#define RTC_CNTL_REJECT_CAUSE_M  ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S))
+#define RTC_CNTL_REJECT_CAUSE_V  0x3FFFF
+#define RTC_CNTL_REJECT_CAUSE_S  0
+
+#define RTC_CNTL_OPTION1_REG          (DR_REG_RTCCNTL_BASE + 0x00F4)
+/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT  (BIT(0))
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M  (BIT(0))
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V  0x1
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S  0
+
+#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG          (DR_REG_RTCCNTL_BASE + 0x00F8)
+/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */
+/*description: sleep wakeup cause*/
+#define RTC_CNTL_WAKEUP_CAUSE  0x0001FFFF
+#define RTC_CNTL_WAKEUP_CAUSE_M  ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S))
+#define RTC_CNTL_WAKEUP_CAUSE_V  0x1FFFF
+#define RTC_CNTL_WAKEUP_CAUSE_S  0
+
+#define RTC_CNTL_ULP_CP_TIMER_1_REG          (DR_REG_RTCCNTL_BASE + 0x00FC)
+/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */
+/*description: sleep cycles for ULP-coprocessor timer*/
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE  0x00FFFFFF
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M  ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S))
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V  0xFFFFFF
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S  8
+
+#define RTC_CNTL_INT_ENA_W1TS_REG          (DR_REG_RTCCNTL_BASE + 0x0100)
+/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_S  20
+/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: enbale gitch det interrupt*/
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S  19
+/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: enable xtal32k_dead  interrupt*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S  16
+/* RTC_CNTL_SWD_INT_ENA_W1TS : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable super watch dog interrupt*/
+#define RTC_CNTL_SWD_INT_ENA_W1TS  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TS_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_SWD_INT_ENA_W1TS_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: enable RTC main timer interrupt*/
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: enable brown out interrupt*/
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S  9
+/* RTC_CNTL_WDT_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt*/
+#define RTC_CNTL_WDT_INT_ENA_W1TS  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TS_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_WDT_INT_ENA_W1TS_S  3
+/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable sleep reject interrupt*/
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable sleep wakeup interrupt*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S  0
+
+#define RTC_CNTL_INT_ENA_W1TC_REG          (DR_REG_RTCCNTL_BASE + 0x0104)
+/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_S  20
+/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: enbale gitch det interrupt*/
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S  19
+/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: enable xtal32k_dead  interrupt*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S  16
+/* RTC_CNTL_SWD_INT_ENA_W1TC : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable super watch dog interrupt*/
+#define RTC_CNTL_SWD_INT_ENA_W1TC  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TC_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_SWD_INT_ENA_W1TC_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: enable RTC main timer interrupt*/
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: enable brown out interrupt*/
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S  9
+/* RTC_CNTL_WDT_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt*/
+#define RTC_CNTL_WDT_INT_ENA_W1TC  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TC_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_WDT_INT_ENA_W1TC_S  3
+/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable sleep reject interrupt*/
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable sleep wakeup interrupt*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S  0
+
+#define RTC_CNTL_RETENTION_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x0108)
+/* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:27] ;default: 5'd20 ; */
+/*description: wait cycles for rention operation*/
+#define RTC_CNTL_RETENTION_WAIT  0x0000001F
+#define RTC_CNTL_RETENTION_WAIT_M  ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S))
+#define RTC_CNTL_RETENTION_WAIT_V  0x1F
+#define RTC_CNTL_RETENTION_WAIT_S  27
+/* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_RETENTION_EN  (BIT(26))
+#define RTC_CNTL_RETENTION_EN_M  (BIT(26))
+#define RTC_CNTL_RETENTION_EN_V  0x1
+#define RTC_CNTL_RETENTION_EN_S  26
+/* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W ;bitpos:[25:22] ;default: 4'd3 ; */
+/*description: */
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT  0x0000000F
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT_M  ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S))
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT_V  0xF
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S  22
+/* RTC_CNTL_RETENTION_DONE_WAIT : R/W ;bitpos:[21:19] ;default: 3'd2 ; */
+/*description: */
+#define RTC_CNTL_RETENTION_DONE_WAIT  0x00000007
+#define RTC_CNTL_RETENTION_DONE_WAIT_M  ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S))
+#define RTC_CNTL_RETENTION_DONE_WAIT_V  0x7
+#define RTC_CNTL_RETENTION_DONE_WAIT_S  19
+/* RTC_CNTL_RETENTION_CLK_SEL : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_RETENTION_CLK_SEL  (BIT(18))
+#define RTC_CNTL_RETENTION_CLK_SEL_M  (BIT(18))
+#define RTC_CNTL_RETENTION_CLK_SEL_V  0x1
+#define RTC_CNTL_RETENTION_CLK_SEL_S  18
+
+#define RTC_CNTL_FIB_SEL_REG          (DR_REG_RTCCNTL_BASE + 0x010C)
+/* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
+/*description: select use analog fib signal*/
+#define RTC_CNTL_FIB_SEL  0x00000007
+#define RTC_CNTL_FIB_SEL_M  ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S))
+#define RTC_CNTL_FIB_SEL_V  0x7
+#define RTC_CNTL_FIB_SEL_S  0
+
+#define RTC_CNTL_GPIO_WAKEUP_REG          (DR_REG_RTCCNTL_BASE + 0x0110)
+/* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE  (BIT(31))
+#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_M  (BIT(31))
+#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S  31
+/* RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE  (BIT(30))
+#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_M  (BIT(30))
+#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_S  30
+/* RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE  (BIT(29))
+#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_M  (BIT(29))
+#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_S  29
+/* RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE  (BIT(28))
+#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_M  (BIT(28))
+#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_S  28
+/* RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE  (BIT(27))
+#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_M  (BIT(27))
+#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_S  27
+/* RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE  (BIT(26))
+#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_M  (BIT(26))
+#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_S  26
+/* RTC_CNTL_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[25:23] ;default: 3'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN0_INT_TYPE  0x00000007
+#define RTC_CNTL_GPIO_PIN0_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN0_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN0_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN0_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN0_INT_TYPE_S  23
+/* RTC_CNTL_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[22:20] ;default: 3'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN1_INT_TYPE  0x00000007
+#define RTC_CNTL_GPIO_PIN1_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN1_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN1_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN1_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN1_INT_TYPE_S  20
+/* RTC_CNTL_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[19:17] ;default: 3'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN2_INT_TYPE  0x00000007
+#define RTC_CNTL_GPIO_PIN2_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN2_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN2_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN2_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN2_INT_TYPE_S  17
+/* RTC_CNTL_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[16:14] ;default: 3'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN3_INT_TYPE  0x00000007
+#define RTC_CNTL_GPIO_PIN3_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN3_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN3_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN3_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN3_INT_TYPE_S  14
+/* RTC_CNTL_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[13:11] ;default: 3'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN4_INT_TYPE  0x00000007
+#define RTC_CNTL_GPIO_PIN4_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN4_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN4_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN4_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN4_INT_TYPE_S  11
+/* RTC_CNTL_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[10:8] ;default: 3'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN5_INT_TYPE  0x00000007
+#define RTC_CNTL_GPIO_PIN5_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN5_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN5_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN5_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN5_INT_TYPE_S  8
+/* RTC_CNTL_GPIO_PIN_CLK_GATE : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN_CLK_GATE  (BIT(7))
+#define RTC_CNTL_GPIO_PIN_CLK_GATE_M  (BIT(7))
+#define RTC_CNTL_GPIO_PIN_CLK_GATE_V  0x1
+#define RTC_CNTL_GPIO_PIN_CLK_GATE_S  7
+/* RTC_CNTL_GPIO_WAKEUP_STATUS_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR  (BIT(6))
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_M  (BIT(6))
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_V  0x1
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_S  6
+/* RTC_CNTL_GPIO_WAKEUP_STATUS : RO ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_WAKEUP_STATUS  0x0000003F
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_M  ((RTC_CNTL_GPIO_WAKEUP_STATUS_V)<<(RTC_CNTL_GPIO_WAKEUP_STATUS_S))
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_V  0x3F
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_S  0
+
+#define RTC_CNTL_DBG_SEL_REG          (DR_REG_RTCCNTL_BASE + 0x0114)
+/* RTC_CNTL_DEBUG_SEL4 : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
+/*description: */
+#define RTC_CNTL_DEBUG_SEL4  0x0000001F
+#define RTC_CNTL_DEBUG_SEL4_M  ((RTC_CNTL_DEBUG_SEL4_V)<<(RTC_CNTL_DEBUG_SEL4_S))
+#define RTC_CNTL_DEBUG_SEL4_V  0x1F
+#define RTC_CNTL_DEBUG_SEL4_S  27
+/* RTC_CNTL_DEBUG_SEL3 : R/W ;bitpos:[26:22] ;default: 5'd0 ; */
+/*description: */
+#define RTC_CNTL_DEBUG_SEL3  0x0000001F
+#define RTC_CNTL_DEBUG_SEL3_M  ((RTC_CNTL_DEBUG_SEL3_V)<<(RTC_CNTL_DEBUG_SEL3_S))
+#define RTC_CNTL_DEBUG_SEL3_V  0x1F
+#define RTC_CNTL_DEBUG_SEL3_S  22
+/* RTC_CNTL_DEBUG_SEL2 : R/W ;bitpos:[21:17] ;default: 5'd0 ; */
+/*description: */
+#define RTC_CNTL_DEBUG_SEL2  0x0000001F
+#define RTC_CNTL_DEBUG_SEL2_M  ((RTC_CNTL_DEBUG_SEL2_V)<<(RTC_CNTL_DEBUG_SEL2_S))
+#define RTC_CNTL_DEBUG_SEL2_V  0x1F
+#define RTC_CNTL_DEBUG_SEL2_S  17
+/* RTC_CNTL_DEBUG_SEL1 : R/W ;bitpos:[16:12] ;default: 5'd0 ; */
+/*description: */
+#define RTC_CNTL_DEBUG_SEL1  0x0000001F
+#define RTC_CNTL_DEBUG_SEL1_M  ((RTC_CNTL_DEBUG_SEL1_V)<<(RTC_CNTL_DEBUG_SEL1_S))
+#define RTC_CNTL_DEBUG_SEL1_V  0x1F
+#define RTC_CNTL_DEBUG_SEL1_S  12
+/* RTC_CNTL_DEBUG_SEL0 : R/W ;bitpos:[11:7] ;default: 5'd0 ; */
+/*description: */
+#define RTC_CNTL_DEBUG_SEL0  0x0000001F
+#define RTC_CNTL_DEBUG_SEL0_M  ((RTC_CNTL_DEBUG_SEL0_V)<<(RTC_CNTL_DEBUG_SEL0_S))
+#define RTC_CNTL_DEBUG_SEL0_V  0x1F
+#define RTC_CNTL_DEBUG_SEL0_S  7
+/* RTC_CNTL_DEBUG_BIT_SEL : R/W ;bitpos:[6:2] ;default: 5'd0 ; */
+/*description: */
+#define RTC_CNTL_DEBUG_BIT_SEL  0x0000001F
+#define RTC_CNTL_DEBUG_BIT_SEL_M  ((RTC_CNTL_DEBUG_BIT_SEL_V)<<(RTC_CNTL_DEBUG_BIT_SEL_S))
+#define RTC_CNTL_DEBUG_BIT_SEL_V  0x1F
+#define RTC_CNTL_DEBUG_BIT_SEL_S  2
+/* RTC_CNTL_DEBUG_12M_NO_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_DEBUG_12M_NO_GATING  (BIT(1))
+#define RTC_CNTL_DEBUG_12M_NO_GATING_M  (BIT(1))
+#define RTC_CNTL_DEBUG_12M_NO_GATING_V  0x1
+#define RTC_CNTL_DEBUG_12M_NO_GATING_S  1
+
+#define RTC_CNTL_DBG_MAP_REG          (DR_REG_RTCCNTL_BASE + 0x0118)
+/* RTC_CNTL_GPIO_PIN0_FUN_SEL : R/W ;bitpos:[31:28] ;default: 4'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN0_FUN_SEL  0x0000000F
+#define RTC_CNTL_GPIO_PIN0_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN0_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN0_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN0_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN0_FUN_SEL_S  28
+/* RTC_CNTL_GPIO_PIN1_FUN_SEL : R/W ;bitpos:[27:24] ;default: 4'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN1_FUN_SEL  0x0000000F
+#define RTC_CNTL_GPIO_PIN1_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN1_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN1_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN1_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN1_FUN_SEL_S  24
+/* RTC_CNTL_GPIO_PIN2_FUN_SEL : R/W ;bitpos:[23:20] ;default: 4'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN2_FUN_SEL  0x0000000F
+#define RTC_CNTL_GPIO_PIN2_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN2_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN2_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN2_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN2_FUN_SEL_S  20
+/* RTC_CNTL_GPIO_PIN3_FUN_SEL : R/W ;bitpos:[19:16] ;default: 4'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN3_FUN_SEL  0x0000000F
+#define RTC_CNTL_GPIO_PIN3_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN3_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN3_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN3_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN3_FUN_SEL_S  16
+/* RTC_CNTL_GPIO_PIN4_FUN_SEL : R/W ;bitpos:[15:12] ;default: 4'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN4_FUN_SEL  0x0000000F
+#define RTC_CNTL_GPIO_PIN4_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN4_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN4_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN4_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN4_FUN_SEL_S  12
+/* RTC_CNTL_GPIO_PIN5_FUN_SEL : R/W ;bitpos:[11:8] ;default: 4'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN5_FUN_SEL  0x0000000F
+#define RTC_CNTL_GPIO_PIN5_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN5_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN5_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN5_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN5_FUN_SEL_S  8
+/* RTC_CNTL_GPIO_PIN0_MUX_SEL : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN0_MUX_SEL  (BIT(7))
+#define RTC_CNTL_GPIO_PIN0_MUX_SEL_M  (BIT(7))
+#define RTC_CNTL_GPIO_PIN0_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN0_MUX_SEL_S  7
+/* RTC_CNTL_GPIO_PIN1_MUX_SEL : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN1_MUX_SEL  (BIT(6))
+#define RTC_CNTL_GPIO_PIN1_MUX_SEL_M  (BIT(6))
+#define RTC_CNTL_GPIO_PIN1_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN1_MUX_SEL_S  6
+/* RTC_CNTL_GPIO_PIN2_MUX_SEL : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN2_MUX_SEL  (BIT(5))
+#define RTC_CNTL_GPIO_PIN2_MUX_SEL_M  (BIT(5))
+#define RTC_CNTL_GPIO_PIN2_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN2_MUX_SEL_S  5
+/* RTC_CNTL_GPIO_PIN3_MUX_SEL : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN3_MUX_SEL  (BIT(4))
+#define RTC_CNTL_GPIO_PIN3_MUX_SEL_M  (BIT(4))
+#define RTC_CNTL_GPIO_PIN3_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN3_MUX_SEL_S  4
+/* RTC_CNTL_GPIO_PIN4_MUX_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN4_MUX_SEL  (BIT(3))
+#define RTC_CNTL_GPIO_PIN4_MUX_SEL_M  (BIT(3))
+#define RTC_CNTL_GPIO_PIN4_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN4_MUX_SEL_S  3
+/* RTC_CNTL_GPIO_PIN5_MUX_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN5_MUX_SEL  (BIT(2))
+#define RTC_CNTL_GPIO_PIN5_MUX_SEL_M  (BIT(2))
+#define RTC_CNTL_GPIO_PIN5_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN5_MUX_SEL_S  2
+
+#define RTC_CNTL_SENSOR_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x011C)
+/* RTC_CNTL_FORCE_XPD_SAR : R/W ;bitpos:[31:30] ;default: 2'b0 ; */
+/*description: */
+#define RTC_CNTL_FORCE_XPD_SAR  0x00000003
+#define RTC_CNTL_FORCE_XPD_SAR_M  ((RTC_CNTL_FORCE_XPD_SAR_V)<<(RTC_CNTL_FORCE_XPD_SAR_S))
+#define RTC_CNTL_FORCE_XPD_SAR_V  0x3
+#define RTC_CNTL_FORCE_XPD_SAR_S  30
+/* RTC_CNTL_SAR2_PWDET_CCT : R/W ;bitpos:[29:27] ;default: 3'd0 ; */
+/*description: */
+#define RTC_CNTL_SAR2_PWDET_CCT  0x00000007
+#define RTC_CNTL_SAR2_PWDET_CCT_M  ((RTC_CNTL_SAR2_PWDET_CCT_V)<<(RTC_CNTL_SAR2_PWDET_CCT_S))
+#define RTC_CNTL_SAR2_PWDET_CCT_V  0x7
+#define RTC_CNTL_SAR2_PWDET_CCT_S  27
+
+#define RTC_CNTL_DBG_SAR_SEL_REG          (DR_REG_RTCCNTL_BASE + 0x0120)
+/* RTC_CNTL_SAR_DEBUG_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
+/*description: */
+#define RTC_CNTL_SAR_DEBUG_SEL  0x0000001F
+#define RTC_CNTL_SAR_DEBUG_SEL_M  ((RTC_CNTL_SAR_DEBUG_SEL_V)<<(RTC_CNTL_SAR_DEBUG_SEL_S))
+#define RTC_CNTL_SAR_DEBUG_SEL_V  0x1F
+#define RTC_CNTL_SAR_DEBUG_SEL_S  27
+
+#define RTC_CNTL_PG_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x0124)
+/* RTC_CNTL_POWER_GLITCH_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_POWER_GLITCH_EN  (BIT(31))
+#define RTC_CNTL_POWER_GLITCH_EN_M  (BIT(31))
+#define RTC_CNTL_POWER_GLITCH_EN_V  0x1
+#define RTC_CNTL_POWER_GLITCH_EN_S  31
+/* RTC_CNTL_POWER_GLITCH_EFUSE_SEL : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL  (BIT(30))
+#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_M  (BIT(30))
+#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V  0x1
+#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S  30
+/* RTC_CNTL_POWER_GLITCH_FORCE_PU : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_POWER_GLITCH_FORCE_PU  (BIT(29))
+#define RTC_CNTL_POWER_GLITCH_FORCE_PU_M  (BIT(29))
+#define RTC_CNTL_POWER_GLITCH_FORCE_PU_V  0x1
+#define RTC_CNTL_POWER_GLITCH_FORCE_PU_S  29
+/* RTC_CNTL_POWER_GLITCH_FORCE_PD : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_POWER_GLITCH_FORCE_PD  (BIT(28))
+#define RTC_CNTL_POWER_GLITCH_FORCE_PD_M  (BIT(28))
+#define RTC_CNTL_POWER_GLITCH_FORCE_PD_V  0x1
+#define RTC_CNTL_POWER_GLITCH_FORCE_PD_S  28
+/* RTC_CNTL_POWER_GLITCH_DSENSE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */
+/*description: */
+#define RTC_CNTL_POWER_GLITCH_DSENSE  0x00000003
+#define RTC_CNTL_POWER_GLITCH_DSENSE_M  ((RTC_CNTL_POWER_GLITCH_DSENSE_V)<<(RTC_CNTL_POWER_GLITCH_DSENSE_S))
+#define RTC_CNTL_POWER_GLITCH_DSENSE_V  0x3
+#define RTC_CNTL_POWER_GLITCH_DSENSE_S  26
+
+#define RTC_CNTL_DATE_REG          (DR_REG_RTCCNTL_BASE + 0x01fc)
+/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007270 ; */
+/*description: */
+#define RTC_CNTL_CNTL_DATE  0x0FFFFFFF
+#define RTC_CNTL_CNTL_DATE_M  ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S))
+#define RTC_CNTL_CNTL_DATE_V  0xFFFFFFF
+#define RTC_CNTL_CNTL_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_RTC_CNTL_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/rtc_cntl_struct.h b/components/soc/esp32c3/include/soc/rtc_cntl_struct.h
new file mode 100644
index 0000000000..358ebaded7
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/rtc_cntl_struct.h
@@ -0,0 +1,843 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_RTC_CNTL_STRUCT_H_
+#define _SOC_RTC_CNTL_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t sw_stall_appcpu_c0:  2;               /*{reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
+            uint32_t sw_stall_procpu_c0:  2;               /*{reg_sw_stall_procpu_c1[5:0]   reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/
+            uint32_t sw_appcpu_rst:       1;               /*APP CPU SW reset*/
+            uint32_t sw_procpu_rst:       1;               /*PRO CPU SW reset*/
+            uint32_t bb_i2c_force_pd:     1;               /*BB_I2C force power down*/
+            uint32_t bb_i2c_force_pu:     1;               /*BB_I2C force power up*/
+            uint32_t bbpll_i2c_force_pd:  1;               /*BB_PLL _I2C force power down*/
+            uint32_t bbpll_i2c_force_pu:  1;               /*BB_PLL_I2C force power up*/
+            uint32_t bbpll_force_pd:      1;               /*BB_PLL force power down*/
+            uint32_t bbpll_force_pu:      1;               /*BB_PLL force power up*/
+            uint32_t xtl_force_pd:        1;               /*crystall force power down*/
+            uint32_t xtl_force_pu:        1;               /*crystall force power up*/
+            uint32_t xtl_en_wait:         4;               /*wait bias_sleep and current source wakeup*/
+            uint32_t reserved18:          2;
+            uint32_t ctr_sel:             3;
+            uint32_t xtl_force_iso:       1;
+            uint32_t pll_force_iso:       1;
+            uint32_t analog_force_iso:    1;
+            uint32_t xtl_force_noiso:     1;
+            uint32_t pll_force_noiso:     1;
+            uint32_t analog_force_noiso:  1;
+            uint32_t dg_wrap_force_rst:   1;               /*digital wrap force reset in deep sleep*/
+            uint32_t dg_wrap_force_norst: 1;               /*digital core force no reset in deep sleep*/
+            uint32_t sw_sys_rst:          1;               /*SW system reset*/
+        };
+        uint32_t val;
+    } options0;
+    uint32_t slp_timer0;                               /**/
+    union {
+        struct {
+            uint32_t slp_val_hi:             16;           /*RTC sleep timer high 16 bits*/
+            uint32_t main_timer_alarm_en:     1;           /*timer alarm enable bit*/
+            uint32_t reserved17:             15;
+        };
+        uint32_t val;
+    } slp_timer1;
+    union {
+        struct {
+            uint32_t reserved0:      27;
+            uint32_t timer_sys_stall: 1;                   /*Enable to record system stall time*/
+            uint32_t timer_xtl_off:   1;                   /*Enable to record 40M XTAL OFF time*/
+            uint32_t timer_sys_rst:   1;                   /*enable to record system reset time*/
+            uint32_t reserved30:      1;
+            uint32_t update:          1;                   /*Set 1: to update register with RTC timer*/
+        };
+        uint32_t val;
+    } time_update;
+    uint32_t time_low0;                                /*RTC timer low 32 bits*/
+    union {
+        struct {
+            uint32_t rtc_timer_value0_high:16;             /*RTC timer high 16 bits*/
+            uint32_t reserved16:           16;
+        };
+        uint32_t val;
+    } time_high0;
+    union {
+        struct {
+            uint32_t rtc_sw_cpu_int:           1;          /*rtc software interrupt to main cpu*/
+            uint32_t rtc_slp_reject_cause_clr: 1;          /*clear rtc sleep reject cause*/
+            uint32_t reserved2:               20;
+            uint32_t apb2rtc_bridge_sel:       1;          /*1: APB to RTC using bridge*/
+            uint32_t reserved23:               5;
+            uint32_t sdio_active_ind:          1;          /*SDIO active indication*/
+            uint32_t slp_wakeup:               1;          /*leep wakeup bit*/
+            uint32_t slp_reject:               1;          /*leep reject bit*/
+            uint32_t sleep_en:                 1;          /*sleep enable bit*/
+        };
+        uint32_t val;
+    } state0;
+    union {
+        struct {
+            uint32_t cpu_stall_en:   1;                    /*CPU stall enable bit*/
+            uint32_t cpu_stall_wait: 5;                    /*CPU stall wait cycles in fast_clk_rtc*/
+            uint32_t ck8m_wait:      8;                    /*CK8M wait cycles in slow_clk_rtc*/
+            uint32_t xtl_buf_wait:  10;                    /*XTAL wait cycles in slow_clk_rtc*/
+            uint32_t pll_buf_wait:   8;                    /*PLL wait cycles in slow_clk_rtc*/
+        };
+        uint32_t val;
+    } timer1;
+    union {
+        struct {
+            uint32_t reserved0:        24;
+            uint32_t min_time_ck8m_off: 8;                 /*minimal cycles in slow_clk_rtc for CK8M in power down state*/
+        };
+        uint32_t val;
+    } timer2;
+    union {
+        struct {
+            uint32_t wifi_wait_timer:    9;
+            uint32_t wifi_powerup_timer: 7;
+            uint32_t bt_wait_timer:      9;
+            uint32_t bt_powerup_timer:   7;
+        };
+        uint32_t val;
+    } timer3;
+    union {
+        struct {
+            uint32_t cpu_top_wait_timer:    9;
+            uint32_t cpu_top_powerup_timer: 7;
+            uint32_t dg_wrap_wait_timer:    9;
+            uint32_t dg_wrap_powerup_timer: 7;
+        };
+        uint32_t val;
+    } timer4;
+    union {
+        struct {
+            uint32_t reserved0:   8;
+            uint32_t min_slp_val: 8;                       /*minimal sleep cycles in slow_clk_rtc*/
+            uint32_t reserved16: 16;
+        };
+        uint32_t val;
+    } timer5;
+    union {
+        struct {
+            uint32_t reserved0:            16;
+            uint32_t dg_peri_wait_timer:    9;
+            uint32_t dg_peri_powerup_timer: 7;
+        };
+        uint32_t val;
+    } timer6;
+    union {
+        struct {
+            uint32_t reserved0:             18;
+            uint32_t i2c_reset_por_force_pd: 1;
+            uint32_t i2c_reset_por_force_pu: 1;
+            uint32_t glitch_rst_en:          1;
+            uint32_t reserved21:             1;            /*PLLA force power down*/
+            uint32_t sar_i2c_pu:             1;            /*PLLA force power up*/
+            uint32_t plla_force_pd:          1;            /*PLLA force power down*/
+            uint32_t plla_force_pu:          1;            /*PLLA force power up*/
+            uint32_t bbpll_cal_slp_start:    1;            /*start BBPLL calibration during sleep*/
+            uint32_t pvtmon_pu:              1;            /*1: PVTMON power up*/
+            uint32_t txrf_i2c_pu:            1;            /*1: TXRF_I2C power up*/
+            uint32_t rfrx_pbus_pu:           1;            /*1: RFRX_PBUS power up*/
+            uint32_t reserved29:             1;
+            uint32_t ckgen_i2c_pu:           1;            /*1: CKGEN_I2C power up*/
+            uint32_t pll_i2c_pu:             1;
+        };
+        uint32_t val;
+    } ana_conf;
+    union {
+        struct {
+            uint32_t reset_cause_procpu:         6;        /*reset cause of PRO CPU*/
+            uint32_t reset_cause_appcpu:         6;        /*reset cause of APP CPU*/
+            uint32_t stat_vector_sel_appcpu:     1;        /*APP CPU state vector sel*/
+            uint32_t stat_vector_sel_procpu:     1;        /*PRO CPU state vector sel*/
+            uint32_t all_reset_flag_procpu:      1;        /*PRO CPU reset_flag*/
+            uint32_t all_reset_flag_appcpu:      1;        /*APP CPU reset flag*/
+            uint32_t all_reset_flag_clr_procpu:  1;        /*clear PRO CPU reset_flag*/
+            uint32_t all_reset_flag_clr_appcpu:  1;        /*clear APP CPU reset flag*/
+            uint32_t ocd_halt_on_reset_appcpu:   1;        /*APPCPU OcdHaltOnReset*/
+            uint32_t ocd_halt_on_reset_procpu:   1;        /*PROCPU OcdHaltOnReset*/
+            uint32_t jtag_reset_flag_procpu:     1;
+            uint32_t jtag_reset_flag_appcpu:     1;
+            uint32_t jtag_reset_flag_clr_procpu: 1;
+            uint32_t jtag_reset_flag_clr_appcpu: 1;
+            uint32_t rtc_dreset_mask_appcpu:     1;
+            uint32_t rtc_dreset_mask_procpu:     1;
+            uint32_t reserved26:                 6;
+        };
+        uint32_t val;
+    } reset_state;
+    union {
+        struct {
+            uint32_t reserved0:     15;
+            uint32_t rtc_wakeup_ena:17;                    /*wakeup enable bitmap*/
+        };
+        uint32_t val;
+    } wakeup_state;
+    union {
+        struct {
+            uint32_t slp_wakeup:               1;          /*enable sleep wakeup interrupt*/
+            uint32_t slp_reject:               1;          /*enable sleep reject interrupt*/
+            uint32_t reserved2:                1;          /*enable SDIO idle interrupt*/
+            uint32_t rtc_wdt:                  1;          /*enable RTC WDT interrupt*/
+            uint32_t reserved4:                5;
+            uint32_t rtc_brown_out:            1;          /*enable brown out interrupt*/
+            uint32_t rtc_main_timer:           1;          /*enable RTC main timer interrupt*/
+            uint32_t reserved11:               4;          /*enable saradc2 interrupt*/
+            uint32_t rtc_swd:                  1;          /*enable super watch dog interrupt*/
+            uint32_t rtc_xtal32k_dead:         1;          /*enable xtal32k_dead  interrupt*/
+            uint32_t reserved17:               2;          /*enable touch timeout interrupt*/
+            uint32_t rtc_glitch_det:           1;          /*enbale gitch det interrupt*/
+            uint32_t rtc_bbpll_cal:            1;
+            uint32_t reserved21:              11;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t slp_wakeup:               1;          /*sleep wakeup interrupt raw*/
+            uint32_t slp_reject:               1;          /*sleep reject interrupt raw*/
+            uint32_t reserved2:                1;          /*SDIO idle interrupt raw*/
+            uint32_t rtc_wdt:                  1;          /*RTC WDT interrupt raw*/
+            uint32_t reserved4:                5;          /*touch inactive interrupt raw*/
+            uint32_t rtc_brown_out:            1;          /*brown out interrupt raw*/
+            uint32_t rtc_main_timer:           1;          /*RTC main timer interrupt raw*/
+            uint32_t reserved11:               4;          /*saradc2 interrupt raw*/
+            uint32_t rtc_swd:                  1;          /*super watch dog interrupt raw*/
+            uint32_t rtc_xtal32k_dead:         1;          /*xtal32k dead detection interrupt raw*/
+            uint32_t reserved17:               2;          /*touch timeout interrupt raw*/
+            uint32_t rtc_glitch_det:           1;          /*glitch_det_interrupt_raw*/
+            uint32_t rtc_bbpll_cal:            1;
+            uint32_t reserved21:              11;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t slp_wakeup:              1;           /*sleep wakeup interrupt state*/
+            uint32_t slp_reject:              1;           /*sleep reject interrupt state*/
+            uint32_t reserved2:               1;
+            uint32_t rtc_wdt:                 1;           /*RTC WDT interrupt state*/
+            uint32_t reserved4:               5;
+            uint32_t rtc_brown_out:           1;           /*brown out interrupt state*/
+            uint32_t rtc_main_timer:          1;           /*RTC main timer interrupt state*/
+            uint32_t reserved11:              4;
+            uint32_t rtc_swd:                 1;           /*super watch dog interrupt state*/
+            uint32_t rtc_xtal32k_dead:        1;           /*xtal32k dead detection interrupt state*/
+            uint32_t reserved17:              2;
+            uint32_t rtc_glitch_det:          1;           /*glitch_det_interrupt state*/
+            uint32_t rtc_bbpll_cal:           1;
+            uint32_t reserved21:             11;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t slp_wakeup:               1;          /*Clear sleep wakeup interrupt state*/
+            uint32_t slp_reject:               1;          /*Clear sleep reject interrupt state*/
+            uint32_t reserved2:                1;
+            uint32_t rtc_wdt:                  1;          /*Clear RTC WDT interrupt state*/
+            uint32_t reserved4:                5;
+            uint32_t rtc_brown_out:            1;          /*Clear brown out interrupt state*/
+            uint32_t rtc_main_timer:           1;          /*Clear RTC main timer interrupt state*/
+            uint32_t reserved11:               4;
+            uint32_t rtc_swd:                  1;          /*Clear super watch dog interrupt state*/
+            uint32_t rtc_xtal32k_dead:         1;          /*Clear RTC WDT interrupt state*/
+            uint32_t reserved17:               2;
+            uint32_t rtc_glitch_det:           1;          /*Clear glitch det interrupt state*/
+            uint32_t rtc_bbpll_cal:            1;
+            uint32_t reserved21:              11;
+        };
+        uint32_t val;
+    } int_clr;
+    uint32_t store[4];                                   /**/
+    union {
+        struct {
+            uint32_t xtal32k_wdt_en:       1;              /*xtal 32k watch dog enable*/
+            uint32_t xtal32k_wdt_clk_fo:   1;              /*xtal 32k watch dog clock force on*/
+            uint32_t xtal32k_wdt_reset:    1;              /*xtal 32k watch dog sw reset*/
+            uint32_t xtal32k_ext_clk_fo:   1;              /*xtal 32k external xtal clock force on*/
+            uint32_t xtal32k_auto_backup:  1;              /*xtal 32k switch to back up clock when xtal is dead*/
+            uint32_t xtal32k_auto_restart: 1;              /*xtal 32k restart xtal when xtal is dead*/
+            uint32_t xtal32k_auto_return:  1;              /*xtal 32k switch back xtal when xtal is restarted*/
+            uint32_t xtal32k_xpd_force:    1;              /*Xtal 32k xpd control by sw or fsm*/
+            uint32_t enckinit_xtal_32k:    1;              /*apply an internal clock to help xtal 32k to start*/
+            uint32_t dbuf_xtal_32k:        1;              /*0: single-end buffer 1: differential buffer*/
+            uint32_t dgm_xtal_32k:         3;              /*xtal_32k gm control*/
+            uint32_t dres_xtal_32k:        3;              /*DRES_XTAL_32K*/
+            uint32_t xpd_xtal_32k:         1;              /*XPD_XTAL_32K*/
+            uint32_t dac_xtal_32k:         3;              /*DAC_XTAL_32K*/
+            uint32_t rtc_wdt_state:        3;              /*state of 32k_wdt*/
+            uint32_t rtc_xtal32k_gpio_sel: 1;              /*XTAL_32K sel. 0: external XTAL_32K*/
+            uint32_t reserved24:           6;
+            uint32_t ctr_lv:               1;              /*0: power down XTAL at high level*/
+            uint32_t ctr_en:               1;
+        };
+        uint32_t val;
+    } ext_xtl_conf;
+    union {
+        struct {
+            uint32_t reserved0:         31;
+            uint32_t gpio_wakeup_filter: 1;                /*enable filter for gpio wakeup event*/
+        };
+        uint32_t val;
+    } ext_wakeup_conf;
+    union {
+        struct {
+            uint32_t reserved0:           12;
+            uint32_t rtc_sleep_reject_ena:18;              /*sleep reject enable*/
+            uint32_t light_slp_reject_en:  1;              /*enable reject for light sleep*/
+            uint32_t deep_slp_reject_en:   1;              /*enable reject for deep sleep*/
+        };
+        uint32_t val;
+    } slp_reject_conf;
+    union {
+        struct {
+            uint32_t reserved0:        29;
+            uint32_t cpusel_conf:       1;                 /*CPU sel option*/
+            uint32_t cpuperiod_sel:     2;
+        };
+        uint32_t val;
+    } cpu_period_conf;
+    union {
+        struct {
+            uint32_t reserved0:                  1;
+            uint32_t efuse_clk_force_gating:     1;
+            uint32_t efuse_clk_force_nogating:   1;
+            uint32_t ck8m_div_sel_vld:           1;        /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/
+            uint32_t ck8m_div:                   2;        /*CK8M_D256_OUT divider. 00: div128*/
+            uint32_t enb_ck8m:                   1;        /*disable CK8M and CK8M_D256_OUT*/
+            uint32_t enb_ck8m_div:               1;        /*1: CK8M_D256_OUT is actually CK8M*/
+            uint32_t dig_xtal32k_en:             1;        /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
+            uint32_t dig_clk8m_d256_en:          1;        /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
+            uint32_t dig_clk8m_en:               1;        /*enable CK8M for digital core (no relationship with RTC core)*/
+            uint32_t reserved11:                 1;
+            uint32_t ck8m_div_sel:               3;        /*divider = reg_ck8m_div_sel + 1*/
+            uint32_t xtal_force_nogating:        1;        /*XTAL force no gating during sleep*/
+            uint32_t ck8m_force_nogating:        1;        /*CK8M force no gating during sleep*/
+            uint32_t ck8m_dfreq:                 8;        /*CK8M_DFREQ*/
+            uint32_t ck8m_force_pd:              1;        /*CK8M force power down*/
+            uint32_t ck8m_force_pu:              1;        /*CK8M force power up*/
+            uint32_t xtal_global_force_gating:   1;
+            uint32_t xtal_global_force_nogating: 1;
+            uint32_t fast_clk_rtc_sel:           1;        /*fast_clk_rtc sel. 0: XTAL div 4*/
+            uint32_t ana_clk_rtc_sel:            2;
+        };
+        uint32_t val;
+    } clk_conf;
+    union {
+        struct {
+            uint32_t reserved0:             22;
+            uint32_t rtc_ana_clk_div_vld:    1;            /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/
+            uint32_t rtc_ana_clk_div:        8;
+            uint32_t slow_clk_next_edge:     1;
+        };
+        uint32_t val;
+    } slow_clk_conf;
+    union {
+        struct {
+            uint32_t sdio_timer_target: 8;                 /*timer count to apply reg_sdio_dcap after sdio power on*/
+            uint32_t reserved8:         1;
+            uint32_t sdio_dthdrv:       2;                 /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/
+            uint32_t sdio_dcap:         2;                 /*ability to prevent LDO from overshoot*/
+            uint32_t sdio_initi:        2;                 /*add resistor from ldo output to ground. 0: no res*/
+            uint32_t sdio_en_initi:     1;                 /*0 to set init[1:0]=0*/
+            uint32_t sdio_dcurlim:      3;                 /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/
+            uint32_t sdio_modecurlim:   1;                 /*select current limit mode*/
+            uint32_t sdio_encurlim:     1;                 /*enable current limit*/
+            uint32_t sdio_pd_en:        1;                 /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
+            uint32_t sdio_force:        1;                 /*1: use SW option to control SDIO_REG*/
+            uint32_t sdio_tieh:         1;                 /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
+            uint32_t reg1p8_ready:      1;                 /*read only register for REG1P8_READY*/
+            uint32_t drefl_sdio:        2;                 /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
+            uint32_t drefm_sdio:        2;                 /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
+            uint32_t drefh_sdio:        2;                 /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
+            uint32_t xpd_sdio:          1;
+        };
+        uint32_t val;
+    } sdio_conf;
+    union {
+        struct {
+            uint32_t dg_vdd_drv_b_slp:    8;
+            uint32_t dg_vdd_drv_b_slp_en: 1;
+            uint32_t reserved9:           1;
+            uint32_t bias_buf_idle:       1;
+            uint32_t bias_buf_wake:       1;
+            uint32_t bias_buf_deep_slp:   1;
+            uint32_t bias_buf_monitor:    1;
+            uint32_t pd_cur_deep_slp:     1;               /*xpd cur when rtc in sleep_state*/
+            uint32_t pd_cur_monitor:      1;               /*xpd cur when rtc in monitor state*/
+            uint32_t bias_sleep_deep_slp: 1;               /*bias_sleep when rtc in sleep_state*/
+            uint32_t bias_sleep_monitor:  1;               /*bias_sleep when rtc in monitor state*/
+            uint32_t dbg_atten_deep_slp:  4;               /*DBG_ATTEN when rtc in sleep state*/
+            uint32_t dbg_atten_monitor:   4;               /*DBG_ATTEN when rtc in monitor state*/
+            uint32_t reserved26:          6;
+        };
+        uint32_t val;
+    } bias_conf;
+    union {
+        struct {
+            uint32_t reserved0:           7;
+            uint32_t dig_cal_en:          1;
+            uint32_t reserved8:           6;
+            uint32_t sck_dcap:            8;               /*SCK_DCAP*/
+            uint32_t reserved22:          6;
+            uint32_t rtc_dboost_force_pd: 1;               /*RTC_DBOOST force power down*/
+            uint32_t rtc_dboost_force_pu: 1;               /*RTC_DBOOST force power up*/
+            uint32_t rtculator_force_pd:  1;               /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/
+            uint32_t rtculator_force_pu:  1;
+        };
+        uint32_t val;
+    } rtc;
+    union {
+        struct {
+            uint32_t reserved0:         21;
+            uint32_t rtc_pad_force_hold: 1;                /*rtc pad force hold*/
+            uint32_t reserved22:        10;
+        };
+        uint32_t val;
+    } rtc_pwc;
+    union {
+        struct {
+            uint32_t vdd_spi_pwr_drv:       2;
+            uint32_t vdd_spi_pwr_force:     1;
+            uint32_t lslp_mem_force_pd:     1;             /*memories in digital core force PD in sleep*/
+            uint32_t lslp_mem_force_pu:     1;             /*memories in digital core force no PD in sleep*/
+            uint32_t reserved5:             6;
+            uint32_t bt_force_pd:           1;
+            uint32_t bt_force_pu:           1;
+            uint32_t dg_peri_force_pd:      1;
+            uint32_t dg_peri_force_pu:      1;
+            uint32_t fastmem_force_lpd:     1;
+            uint32_t fastmem_force_lpu:     1;
+            uint32_t wifi_force_pd:         1;             /*wifi force power down*/
+            uint32_t wifi_force_pu:         1;             /*wifi force power up*/
+            uint32_t dg_wrap_force_pd:      1;             /*digital core force power down*/
+            uint32_t dg_wrap_force_pu:      1;             /*digital core force power up*/
+            uint32_t cpu_top_force_pd:      1;
+            uint32_t cpu_top_force_pu:      1;
+            uint32_t reserved23:            4;
+            uint32_t bt_pd_en:              1;
+            uint32_t dg_peri_pd_en:         1;
+            uint32_t cpu_top_pd_en:         1;
+            uint32_t wifi_pd_en:            1;             /*enable power down wifi in sleep*/
+            uint32_t dg_wrap_pd_en:         1;
+        };
+        uint32_t val;
+    } dig_pwc;
+    union {
+        struct {
+            uint32_t reserved0:           7;
+            uint32_t dig_iso_force_off:   1;
+            uint32_t dig_iso_force_on:    1;
+            uint32_t dg_pad_autohold:     1;               /*read only register to indicate digital pad auto-hold status*/
+            uint32_t clr_dg_pad_autohold: 1;               /*wtite only register to clear digital pad auto-hold*/
+            uint32_t dg_pad_autohold_en:  1;               /*digital pad enable auto-hold*/
+            uint32_t dg_pad_force_noiso:  1;               /*digital pad force no ISO*/
+            uint32_t dg_pad_force_iso:    1;               /*digital pad force ISO*/
+            uint32_t dg_pad_force_unhold: 1;               /*digital pad force un-hold*/
+            uint32_t dg_pad_force_hold:   1;               /*digital pad force hold*/
+            uint32_t reserved16:          6;
+            uint32_t bt_force_iso:        1;
+            uint32_t bt_force_noiso:      1;
+            uint32_t dg_peri_force_iso:   1;
+            uint32_t dg_peri_force_noiso: 1;
+            uint32_t cpu_top_force_iso:   1;               /*cpu force ISO*/
+            uint32_t cpu_top_force_noiso: 1;               /*cpu force no ISO*/
+            uint32_t wifi_force_iso:      1;               /*wifi force ISO*/
+            uint32_t wifi_force_noiso:    1;               /*wifi force no ISO*/
+            uint32_t dg_wrap_force_iso:   1;               /*digital core force ISO*/
+            uint32_t dg_wrap_force_noiso: 1;
+        };
+        uint32_t val;
+    } dig_iso;
+    union {
+        struct {
+            uint32_t chip_reset_width:     8;              /*chip reset siginal pulse width*/
+            uint32_t chip_reset_en:        1;              /*wdt reset whole chip enable*/
+            uint32_t pause_in_slp:         1;              /*pause WDT in sleep*/
+            uint32_t appcpu_reset_en:      1;              /*enable WDT reset APP CPU*/
+            uint32_t procpu_reset_en:      1;              /*enable WDT reset PRO CPU*/
+            uint32_t flashboot_mod_en:     1;              /*enable WDT in flash boot*/
+            uint32_t sys_reset_length:     3;              /*system reset counter length*/
+            uint32_t cpu_reset_length:     3;              /*CPU reset counter length*/
+            uint32_t stg3:                 3;              /*1: interrupt stage en*/
+            uint32_t stg2:                 3;              /*1: interrupt stage en*/
+            uint32_t stg1:                 3;              /*1: interrupt stage en*/
+            uint32_t stg0:                 3;              /*1: interrupt stage en*/
+            uint32_t en:                   1;
+        };
+        uint32_t val;
+    } wdt_config0;
+    uint32_t wdt_config1;                               /**/
+    uint32_t wdt_config2;                               /**/
+    uint32_t wdt_config3;                               /**/
+    uint32_t wdt_config4;                               /**/
+    union {
+        struct {
+            uint32_t reserved0:   31;
+            uint32_t feed:         1;
+        };
+        uint32_t val;
+    } wdt_feed;
+    uint32_t wdt_wprotect;                              /**/
+    union {
+        struct {
+            uint32_t swd_reset_flag:   1;                  /*swd reset flag*/
+            uint32_t swd_feed_int:     1;                  /*swd interrupt for feeding*/
+            uint32_t reserved2:       15;
+            uint32_t swd_bypass_rst:   1;
+            uint32_t swd_signal_width:10;                  /*adjust signal width send to swd*/
+            uint32_t swd_rst_flag_clr: 1;                  /*reset swd reset flag*/
+            uint32_t swd_feed:         1;                  /*Sw feed swd*/
+            uint32_t swd_disable:      1;                  /*disabel SWD*/
+            uint32_t swd_auto_feed_en: 1;                  /*automatically feed swd when int comes*/
+        };
+        uint32_t val;
+    } swd_conf;
+    uint32_t swd_wprotect;                             /**/
+    union {
+        struct {
+            uint32_t reserved0:         20;
+            uint32_t appcpu_c1:          6;                /*{reg_sw_stall_appcpu_c1[5:0]*/
+            uint32_t procpu_c1:          6;
+        };
+        uint32_t val;
+    } sw_cpu_stall;
+    uint32_t store4;                                   /**/
+    uint32_t store5;                                   /**/
+    uint32_t store6;                                   /**/
+    uint32_t store7;                                   /**/
+    union {
+        struct {
+            uint32_t xpd_rom0:                   1;        /*rom0 power down*/
+            uint32_t reserved1:                  1;
+            uint32_t xpd_dig_dcdc:               1;        /*External DCDC power down*/
+            uint32_t rtc_peri_iso:               1;        /*rtc peripheral iso*/
+            uint32_t xpd_rtc_peri:               1;        /*rtc peripheral power down*/
+            uint32_t wifi_iso:                   1;        /*wifi iso*/
+            uint32_t xpd_wifi:                   1;        /*wifi wrap power down*/
+            uint32_t dig_iso:                    1;        /*digital wrap iso*/
+            uint32_t xpd_dig:                    1;        /*digital wrap power down*/
+            uint32_t rtc_touch_state_start:      1;        /*touch should start to work*/
+            uint32_t rtc_touch_state_switch:     1;        /*touch is about to working. Switch rtc main state*/
+            uint32_t rtc_touch_state_slp:        1;        /*touch is in sleep state*/
+            uint32_t rtc_touch_state_done:       1;        /*touch is done*/
+            uint32_t rtc_cocpu_state_start:      1;        /*ulp/cocpu should start to work*/
+            uint32_t rtc_cocpu_state_switch:     1;        /*ulp/cocpu is about to working. Switch rtc main state*/
+            uint32_t rtc_cocpu_state_slp:        1;        /*ulp/cocpu is in sleep state*/
+            uint32_t rtc_cocpu_state_done:       1;        /*ulp/cocpu is done*/
+            uint32_t rtc_main_state_xtal_iso:    1;        /*no use any more*/
+            uint32_t rtc_main_state_pll_on:      1;        /*rtc main state machine is in states that pll should be running*/
+            uint32_t rtc_rdy_for_wakeup:         1;        /*rtc is ready to receive wake up trigger from wake up source*/
+            uint32_t rtc_main_state_wait_end:    1;        /*rtc main state machine has been waited for some cycles*/
+            uint32_t rtc_in_wakeup_state:        1;        /*rtc main state machine is in the states of wakeup process*/
+            uint32_t rtc_in_low_power_state:     1;        /*rtc main state machine is in the states of low power*/
+            uint32_t rtc_main_state_in_wait_8m:  1;        /*rtc main state machine is in wait 8m state*/
+            uint32_t rtc_main_state_in_wait_pll: 1;        /*rtc main state machine is in wait pll state*/
+            uint32_t rtc_main_state_in_wait_xtl: 1;        /*rtc main state machine is in wait xtal state*/
+            uint32_t rtc_main_state_in_slp:      1;        /*rtc main state machine is in sleep state*/
+            uint32_t rtc_main_state_in_idle:     1;        /*rtc main state machine is in idle state*/
+            uint32_t rtc_main_state:             4;        /*rtc main state machine status*/
+        };
+        uint32_t val;
+    } low_power_st;
+    uint32_t diag0;                                    /**/
+    union {
+        struct {
+            uint32_t rtc_gpio_pin0_hold: 1;
+            uint32_t rtc_gpio_pin1_hold: 1;
+            uint32_t rtc_gpio_pin2_hold: 1;
+            uint32_t rtc_gpio_pin3_hold: 1;
+            uint32_t rtc_gpio_pin4_hold: 1;
+            uint32_t rtc_gpio_pin5_hold: 1;
+            uint32_t reserved6:         26;
+        };
+        uint32_t val;
+    } pad_hold;
+    uint32_t dig_pad_hold;                                 /**/
+    union {
+        struct {
+            uint32_t reserved0:                 4;
+            uint32_t int_wait:                 10;         /*brown out interrupt wait cycles*/
+            uint32_t close_flash_ena:           1;         /*enable close flash when brown out happens*/
+            uint32_t pd_rf_ena:                 1;         /*enable power down RF when brown out happens*/
+            uint32_t rst_wait:                 10;         /*brown out reset wait cycles*/
+            uint32_t rst_ena:                   1;         /*enable brown out reset*/
+            uint32_t rst_sel:                   1;         /*1:  4-pos reset*/
+            uint32_t ana_rst_en:                1;
+            uint32_t cnt_clr:                   1;         /*clear brown out counter*/
+            uint32_t ena:                       1;         /*enable brown out*/
+            uint32_t det:                       1;
+        };
+        uint32_t val;
+    } brown_out;
+    uint32_t time_low1;                                /*RTC timer low 32 bits*/
+    union {
+        struct {
+            uint32_t rtc_timer_value1_high:16;             /*RTC timer high 16 bits*/
+            uint32_t reserved16:           16;
+        };
+        uint32_t val;
+    } time_high1;
+    uint32_t xtal32k_clk_factor;                       /*xtal 32k watch dog backup clock factor*/
+    union {
+        struct {
+            uint32_t xtal32k_return_wait:  4;              /*cycles to wait to return noral xtal 32k*/
+            uint32_t xtal32k_restart_wait:16;              /*cycles to wait to repower on xtal 32k*/
+            uint32_t xtal32k_wdt_timeout:  8;              /*If no clock detected for this amount of time*/
+            uint32_t xtal32k_stable_thres: 4;              /*if restarted xtal32k period is smaller than this*/
+        };
+        uint32_t val;
+    } xtal32k_conf;
+    union {
+        struct {
+            uint32_t reserved0:           18;
+            uint32_t io_mux_reset_disable: 1;
+            uint32_t reserved19:          13;
+        };
+        uint32_t val;
+    } usb_conf;
+    union {
+        struct {
+            uint32_t reject_cause:18;                      /*sleep reject cause*/
+            uint32_t reserved18:  14;
+        };
+        uint32_t val;
+    } slp_reject_cause;
+    union {
+        struct {
+            uint32_t force_download_boot: 1;
+            uint32_t reserved1:          31;
+        };
+        uint32_t val;
+    } option1;
+    union {
+        struct {
+            uint32_t wakeup_cause:17;                      /*sleep wakeup cause*/
+            uint32_t reserved17:  15;
+        };
+        uint32_t val;
+    } slp_wakeup_cause;
+    union {
+        struct {
+            uint32_t reserved0:              8;
+            uint32_t ulp_cp_timer_slp_cycle:24;            /*sleep cycles for ULP-coprocessor timer*/
+        };
+        uint32_t val;
+    } ulp_cp_timer_1;
+    union {
+        struct {
+            uint32_t slp_wakeup_w1ts:               1;     /*enable sleep wakeup interrupt*/
+            uint32_t slp_reject_w1ts:               1;     /*enable sleep reject interrupt*/
+            uint32_t reserved2:                     1;
+            uint32_t rtc_wdt_w1ts:                  1;     /*enable RTC WDT interrupt*/
+            uint32_t reserved4:                     5;
+            uint32_t w1ts:                          1;     /*enable brown out interrupt*/
+            uint32_t rtc_main_timer_w1ts:           1;     /*enable RTC main timer interrupt*/
+            uint32_t reserved11:                    4;
+            uint32_t rtc_swd_w1ts:                  1;     /*enable super watch dog interrupt*/
+            uint32_t rtc_xtal32k_dead_w1ts:         1;     /*enable xtal32k_dead  interrupt*/
+            uint32_t reserved17:                    2;
+            uint32_t rtc_glitch_det_w1ts:           1;     /*enbale gitch det interrupt*/
+            uint32_t rtc_bbpll_cal_w1ts:            1;
+            uint32_t reserved21:                   11;
+        };
+        uint32_t val;
+    } int_ena_w1ts;
+    union {
+        struct {
+            uint32_t slp_wakeup_w1tc:               1;     /*enable sleep wakeup interrupt*/
+            uint32_t slp_reject_w1tc:               1;     /*enable sleep reject interrupt*/
+            uint32_t reserved2:                     1;
+            uint32_t rtc_wdt_w1tc:                  1;     /*enable RTC WDT interrupt*/
+            uint32_t reserved4:                     5;
+            uint32_t w1tc:                          1;     /*enable brown out interrupt*/
+            uint32_t rtc_main_timer_w1tc:           1;     /*enable RTC main timer interrupt*/
+            uint32_t reserved11:                    4;
+            uint32_t rtc_swd_w1tc:                  1;     /*enable super watch dog interrupt*/
+            uint32_t rtc_xtal32k_dead_w1tc:         1;     /*enable xtal32k_dead  interrupt*/
+            uint32_t reserved17:                    2;
+            uint32_t rtc_glitch_det_w1tc:           1;     /*enbale gitch det interrupt*/
+            uint32_t rtc_bbpll_cal_w1tc:            1;
+            uint32_t reserved21:                   11;
+        };
+        uint32_t val;
+    } int_ena_w1tc;
+    union {
+        struct {
+            uint32_t reserved0:            18;
+            uint32_t retention_clk_sel:     1;
+            uint32_t retention_done_wait:   3;
+            uint32_t retention_clkoff_wait: 4;
+            uint32_t retention_en:          1;
+            uint32_t retention_wait:        5;             /*wait cycles for rention operation*/
+        };
+        uint32_t val;
+    } retention_ctrl;
+    union {
+        struct {
+            uint32_t rtc_fib_sel: 3;                       /*select use analog fib signal*/
+            uint32_t reserved3:  29;
+        };
+        uint32_t val;
+    } fib_sel;
+    union {
+        struct {
+            uint32_t rtc_gpio_wakeup_status:      6;
+            uint32_t rtc_gpio_wakeup_status_clr:  1;
+            uint32_t rtc_gpio_pin_clk_gate:       1;
+            uint32_t rtc_gpio_pin5_int_type:      3;
+            uint32_t rtc_gpio_pin4_int_type:      3;
+            uint32_t rtc_gpio_pin3_int_type:      3;
+            uint32_t rtc_gpio_pin2_int_type:      3;
+            uint32_t rtc_gpio_pin1_int_type:      3;
+            uint32_t rtc_gpio_pin0_int_type:      3;
+            uint32_t rtc_gpio_pin5_wakeup_enable: 1;
+            uint32_t rtc_gpio_pin4_wakeup_enable: 1;
+            uint32_t rtc_gpio_pin3_wakeup_enable: 1;
+            uint32_t rtc_gpio_pin2_wakeup_enable: 1;
+            uint32_t rtc_gpio_pin1_wakeup_enable: 1;
+            uint32_t rtc_gpio_pin0_wakeup_enable: 1;
+        };
+        uint32_t val;
+    } gpio_wakeup;
+    union {
+        struct {
+            uint32_t reserved0:               1;
+            uint32_t rtc_debug_12m_no_gating: 1;
+            uint32_t rtc_debug_bit_sel:       5;
+            uint32_t rtc_debug_sel0:          5;
+            uint32_t rtc_debug_sel1:          5;
+            uint32_t rtc_debug_sel2:          5;
+            uint32_t rtc_debug_sel3:          5;
+            uint32_t rtc_debug_sel4:          5;
+        };
+        uint32_t val;
+    } dbg_sel;
+    union {
+        struct {
+            uint32_t reserved0:             2;
+            uint32_t rtc_gpio_pin5_mux_sel: 1;
+            uint32_t rtc_gpio_pin4_mux_sel: 1;
+            uint32_t rtc_gpio_pin3_mux_sel: 1;
+            uint32_t rtc_gpio_pin2_mux_sel: 1;
+            uint32_t rtc_gpio_pin1_mux_sel: 1;
+            uint32_t rtc_gpio_pin0_mux_sel: 1;
+            uint32_t rtc_gpio_pin5_fun_sel: 4;
+            uint32_t rtc_gpio_pin4_fun_sel: 4;
+            uint32_t rtc_gpio_pin3_fun_sel: 4;
+            uint32_t rtc_gpio_pin2_fun_sel: 4;
+            uint32_t rtc_gpio_pin1_fun_sel: 4;
+            uint32_t rtc_gpio_pin0_fun_sel: 4;
+        };
+        uint32_t val;
+    } dbg_map;
+    union {
+        struct {
+            uint32_t reserved0:     27;
+            uint32_t sar2_pwdet_cct: 3;
+            uint32_t force_xpd_sar:  2;
+        };
+        uint32_t val;
+    } sensor_ctrl;
+    union {
+        struct {
+            uint32_t reserved0:    27;
+            uint32_t sar_debug_sel: 5;
+        };
+        uint32_t val;
+    } dbg_sar_sel;
+    union {
+        struct {
+            uint32_t reserved0:             26;
+            uint32_t power_glitch_dsense:    2;
+            uint32_t power_glitch_force_pd:  1;
+            uint32_t power_glitch_force_pu:  1;
+            uint32_t power_glitch_efuse_sel: 1;
+            uint32_t power_glitch_en:        1;
+        };
+        uint32_t val;
+    } pg_ctrl;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    union {
+        struct {
+            uint32_t date:      28;
+            uint32_t reserved28: 4;
+        };
+        uint32_t val;
+    } date;
+} rtc_cntl_dev_t;
+extern rtc_cntl_dev_t RTCCNTL;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_RTC_CNTL_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/rtc_i2c_reg.h b/components/soc/esp32c3/include/soc/rtc_i2c_reg.h
new file mode 100644
index 0000000000..52bdefc0e5
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/rtc_i2c_reg.h
@@ -0,0 +1,684 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_RTC_I2C_REG_H_
+#define _SOC_RTC_I2C_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define RTC_I2C_SCL_LOW_PERIOD_REG          (DR_REG_RTC_I2C_BASE + 0x0000)
+/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
+/*description: time period that scl = 0*/
+#define RTC_I2C_SCL_LOW_PERIOD  0x000FFFFF
+#define RTC_I2C_SCL_LOW_PERIOD_M  ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S))
+#define RTC_I2C_SCL_LOW_PERIOD_V  0xFFFFF
+#define RTC_I2C_SCL_LOW_PERIOD_S  0
+
+#define RTC_I2C_CTRL_REG          (DR_REG_RTC_I2C_BASE + 0x0004)
+/* RTC_I2C_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: rtc i2c reg clk gating*/
+#define RTC_I2C_CLK_EN  (BIT(31))
+#define RTC_I2C_CLK_EN_M  (BIT(31))
+#define RTC_I2C_CLK_EN_V  0x1
+#define RTC_I2C_CLK_EN_S  31
+/* RTC_I2C_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: rtc i2c sw reset*/
+#define RTC_I2C_RESET  (BIT(30))
+#define RTC_I2C_RESET_M  (BIT(30))
+#define RTC_I2C_RESET_V  0x1
+#define RTC_I2C_RESET_S  30
+/* RTC_I2C_CTRL_CLK_GATE_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define RTC_I2C_CTRL_CLK_GATE_EN  (BIT(29))
+#define RTC_I2C_CTRL_CLK_GATE_EN_M  (BIT(29))
+#define RTC_I2C_CTRL_CLK_GATE_EN_V  0x1
+#define RTC_I2C_CTRL_CLK_GATE_EN_S  29
+/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: receive lsb first*/
+#define RTC_I2C_RX_LSB_FIRST  (BIT(5))
+#define RTC_I2C_RX_LSB_FIRST_M  (BIT(5))
+#define RTC_I2C_RX_LSB_FIRST_V  0x1
+#define RTC_I2C_RX_LSB_FIRST_S  5
+/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: transit lsb first*/
+#define RTC_I2C_TX_LSB_FIRST  (BIT(4))
+#define RTC_I2C_TX_LSB_FIRST_M  (BIT(4))
+#define RTC_I2C_TX_LSB_FIRST_V  0x1
+#define RTC_I2C_TX_LSB_FIRST_S  4
+/* RTC_I2C_TRANS_START : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: force start*/
+#define RTC_I2C_TRANS_START  (BIT(3))
+#define RTC_I2C_TRANS_START_M  (BIT(3))
+#define RTC_I2C_TRANS_START_V  0x1
+#define RTC_I2C_TRANS_START_S  3
+/* RTC_I2C_MS_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1=master  0=slave*/
+#define RTC_I2C_MS_MODE  (BIT(2))
+#define RTC_I2C_MS_MODE_M  (BIT(2))
+#define RTC_I2C_MS_MODE_V  0x1
+#define RTC_I2C_MS_MODE_S  2
+/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: 1=push pull  0=open drain*/
+#define RTC_I2C_SCL_FORCE_OUT  (BIT(1))
+#define RTC_I2C_SCL_FORCE_OUT_M  (BIT(1))
+#define RTC_I2C_SCL_FORCE_OUT_V  0x1
+#define RTC_I2C_SCL_FORCE_OUT_S  1
+/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1=push pull  0=open drain*/
+#define RTC_I2C_SDA_FORCE_OUT  (BIT(0))
+#define RTC_I2C_SDA_FORCE_OUT_M  (BIT(0))
+#define RTC_I2C_SDA_FORCE_OUT_V  0x1
+#define RTC_I2C_SDA_FORCE_OUT_S  0
+
+#define RTC_I2C_STATUS_REG          (DR_REG_RTC_I2C_BASE + 0x0008)
+/* RTC_I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
+/*description: scl last status*/
+#define RTC_I2C_SCL_STATE_LAST  0x00000007
+#define RTC_I2C_SCL_STATE_LAST_M  ((RTC_I2C_SCL_STATE_LAST_V)<<(RTC_I2C_SCL_STATE_LAST_S))
+#define RTC_I2C_SCL_STATE_LAST_V  0x7
+#define RTC_I2C_SCL_STATE_LAST_S  28
+/* RTC_I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
+/*description: i2c last main status*/
+#define RTC_I2C_SCL_MAIN_STATE_LAST  0x00000007
+#define RTC_I2C_SCL_MAIN_STATE_LAST_M  ((RTC_I2C_SCL_MAIN_STATE_LAST_V)<<(RTC_I2C_SCL_MAIN_STATE_LAST_S))
+#define RTC_I2C_SCL_MAIN_STATE_LAST_V  0x7
+#define RTC_I2C_SCL_MAIN_STATE_LAST_S  24
+/* RTC_I2C_SHIFT : RO ;bitpos:[23:16] ;default: 8'b0 ; */
+/*description: shifter content*/
+#define RTC_I2C_SHIFT  0x000000FF
+#define RTC_I2C_SHIFT_M  ((RTC_I2C_SHIFT_V)<<(RTC_I2C_SHIFT_S))
+#define RTC_I2C_SHIFT_V  0xFF
+#define RTC_I2C_SHIFT_S  16
+/* RTC_I2C_OP_CNT : RO ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: which operation is working*/
+#define RTC_I2C_OP_CNT  0x00000003
+#define RTC_I2C_OP_CNT_M  ((RTC_I2C_OP_CNT_V)<<(RTC_I2C_OP_CNT_S))
+#define RTC_I2C_OP_CNT_V  0x3
+#define RTC_I2C_OP_CNT_S  6
+/* RTC_I2C_BYTE_TRANS : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: One byte transit done*/
+#define RTC_I2C_BYTE_TRANS  (BIT(5))
+#define RTC_I2C_BYTE_TRANS_M  (BIT(5))
+#define RTC_I2C_BYTE_TRANS_V  0x1
+#define RTC_I2C_BYTE_TRANS_S  5
+/* RTC_I2C_SLAVE_ADDRESSED : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: slave reg sub address*/
+#define RTC_I2C_SLAVE_ADDRESSED  (BIT(4))
+#define RTC_I2C_SLAVE_ADDRESSED_M  (BIT(4))
+#define RTC_I2C_SLAVE_ADDRESSED_V  0x1
+#define RTC_I2C_SLAVE_ADDRESSED_S  4
+/* RTC_I2C_BUS_BUSY : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: bus is busy*/
+#define RTC_I2C_BUS_BUSY  (BIT(3))
+#define RTC_I2C_BUS_BUSY_M  (BIT(3))
+#define RTC_I2C_BUS_BUSY_V  0x1
+#define RTC_I2C_BUS_BUSY_S  3
+/* RTC_I2C_ARB_LOST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: arbitration is lost*/
+#define RTC_I2C_ARB_LOST  (BIT(2))
+#define RTC_I2C_ARB_LOST_M  (BIT(2))
+#define RTC_I2C_ARB_LOST_V  0x1
+#define RTC_I2C_ARB_LOST_S  2
+/* RTC_I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: slave read or write*/
+#define RTC_I2C_SLAVE_RW  (BIT(1))
+#define RTC_I2C_SLAVE_RW_M  (BIT(1))
+#define RTC_I2C_SLAVE_RW_V  0x1
+#define RTC_I2C_SLAVE_RW_S  1
+/* RTC_I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: ack response*/
+#define RTC_I2C_ACK_REC  (BIT(0))
+#define RTC_I2C_ACK_REC_M  (BIT(0))
+#define RTC_I2C_ACK_REC_V  0x1
+#define RTC_I2C_ACK_REC_S  0
+
+#define RTC_I2C_TIMEOUT_REG          (DR_REG_RTC_I2C_BASE + 0x000c)
+/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'h10000 ; */
+/*description: time out threshold*/
+#define RTC_I2C_TIMEOUT  0x000FFFFF
+#define RTC_I2C_TIMEOUT_M  ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S))
+#define RTC_I2C_TIMEOUT_V  0xFFFFF
+#define RTC_I2C_TIMEOUT_S  0
+
+#define RTC_I2C_SLAVE_ADDR_REG          (DR_REG_RTC_I2C_BASE + 0x0010)
+/* RTC_I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: i2c 10bit mode enable*/
+#define RTC_I2C_ADDR_10BIT_EN  (BIT(31))
+#define RTC_I2C_ADDR_10BIT_EN_M  (BIT(31))
+#define RTC_I2C_ADDR_10BIT_EN_V  0x1
+#define RTC_I2C_ADDR_10BIT_EN_S  31
+/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
+/*description: slave address*/
+#define RTC_I2C_SLAVE_ADDR  0x00007FFF
+#define RTC_I2C_SLAVE_ADDR_M  ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S))
+#define RTC_I2C_SLAVE_ADDR_V  0x7FFF
+#define RTC_I2C_SLAVE_ADDR_S  0
+
+#define RTC_I2C_SCL_HIGH_REG          (DR_REG_RTC_I2C_BASE + 0x0014)
+/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
+/*description: time period that scl = 1*/
+#define RTC_I2C_SCL_HIGH_PERIOD  0x000FFFFF
+#define RTC_I2C_SCL_HIGH_PERIOD_M  ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S))
+#define RTC_I2C_SCL_HIGH_PERIOD_V  0xFFFFF
+#define RTC_I2C_SCL_HIGH_PERIOD_S  0
+
+#define RTC_I2C_SDA_DUTY_REG          (DR_REG_RTC_I2C_BASE + 0x0018)
+/* RTC_I2C_SDA_DUTY_NUM : R/W ;bitpos:[19:0] ;default: 20'h10 ; */
+/*description: time period for SDA to toggle after SCL goes low*/
+#define RTC_I2C_SDA_DUTY_NUM  0x000FFFFF
+#define RTC_I2C_SDA_DUTY_NUM_M  ((RTC_I2C_SDA_DUTY_NUM_V)<<(RTC_I2C_SDA_DUTY_NUM_S))
+#define RTC_I2C_SDA_DUTY_NUM_V  0xFFFFF
+#define RTC_I2C_SDA_DUTY_NUM_S  0
+
+#define RTC_I2C_SCL_START_PERIOD_REG          (DR_REG_RTC_I2C_BASE + 0x001c)
+/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
+/*description: time period for SCL to toggle after I2C start is triggered*/
+#define RTC_I2C_SCL_START_PERIOD  0x000FFFFF
+#define RTC_I2C_SCL_START_PERIOD_M  ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S))
+#define RTC_I2C_SCL_START_PERIOD_V  0xFFFFF
+#define RTC_I2C_SCL_START_PERIOD_S  0
+
+#define RTC_I2C_SCL_STOP_PERIOD_REG          (DR_REG_RTC_I2C_BASE + 0x0020)
+/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
+/*description: time period for SCL to stop after I2C end is triggered*/
+#define RTC_I2C_SCL_STOP_PERIOD  0x000FFFFF
+#define RTC_I2C_SCL_STOP_PERIOD_M  ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S))
+#define RTC_I2C_SCL_STOP_PERIOD_V  0xFFFFF
+#define RTC_I2C_SCL_STOP_PERIOD_S  0
+
+#define RTC_I2C_INT_CLR_REG          (DR_REG_RTC_I2C_BASE + 0x0024)
+/* RTC_I2C_DETECT_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: clear detect start interrupt*/
+#define RTC_I2C_DETECT_START_INT_CLR  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_CLR_M  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_CLR_V  0x1
+#define RTC_I2C_DETECT_START_INT_CLR_S  8
+/* RTC_I2C_TX_DATA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: clear transit load data complete interrupt*/
+#define RTC_I2C_TX_DATA_INT_CLR  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_CLR_M  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_CLR_V  0x1
+#define RTC_I2C_TX_DATA_INT_CLR_S  7
+/* RTC_I2C_RX_DATA_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: clear receive data interrupt*/
+#define RTC_I2C_RX_DATA_INT_CLR  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_CLR_M  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_CLR_V  0x1
+#define RTC_I2C_RX_DATA_INT_CLR_S  6
+/* RTC_I2C_ACK_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: clear ack error interrupt*/
+#define RTC_I2C_ACK_ERR_INT_CLR  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_CLR_M  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_CLR_V  0x1
+#define RTC_I2C_ACK_ERR_INT_CLR_S  5
+/* RTC_I2C_TIMEOUT_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: clear time out interrupt*/
+#define RTC_I2C_TIMEOUT_INT_CLR  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_CLR_M  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_CLR_V  0x1
+#define RTC_I2C_TIMEOUT_INT_CLR_S  4
+/* RTC_I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: clear transit complete interrupt*/
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V  0x1
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S  3
+/* RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: clear master transit complete interrupt*/
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V  0x1
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S  2
+/* RTC_I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: clear arbitration lost interrupt*/
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V  0x1
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S  1
+/* RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: clear slave transit complete interrupt*/
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V  0x1
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S  0
+
+#define RTC_I2C_INT_RAW_REG          (DR_REG_RTC_I2C_BASE + 0x0028)
+/* RTC_I2C_DETECT_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: detect start interrupt raw*/
+#define RTC_I2C_DETECT_START_INT_RAW  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_RAW_M  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_RAW_V  0x1
+#define RTC_I2C_DETECT_START_INT_RAW_S  8
+/* RTC_I2C_TX_DATA_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: transit data interrupt raw*/
+#define RTC_I2C_TX_DATA_INT_RAW  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_RAW_M  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_RAW_V  0x1
+#define RTC_I2C_TX_DATA_INT_RAW_S  7
+/* RTC_I2C_RX_DATA_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: receive data interrupt raw*/
+#define RTC_I2C_RX_DATA_INT_RAW  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_RAW_M  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_RAW_V  0x1
+#define RTC_I2C_RX_DATA_INT_RAW_S  6
+/* RTC_I2C_ACK_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: ack error interrupt raw*/
+#define RTC_I2C_ACK_ERR_INT_RAW  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_RAW_M  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_RAW_V  0x1
+#define RTC_I2C_ACK_ERR_INT_RAW_S  5
+/* RTC_I2C_TIMEOUT_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: time out interrupt raw*/
+#define RTC_I2C_TIMEOUT_INT_RAW  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_RAW_M  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_RAW_V  0x1
+#define RTC_I2C_TIMEOUT_INT_RAW_S  4
+/* RTC_I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: transit complete interrupt raw*/
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V  0x1
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S  3
+/* RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: master transit complete interrupt raw*/
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V  0x1
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S  2
+/* RTC_I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: arbitration lost interrupt raw*/
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V  0x1
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S  1
+/* RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: slave transit complete interrupt raw*/
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V  0x1
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S  0
+
+#define RTC_I2C_INT_ST_REG          (DR_REG_RTC_I2C_BASE + 0x002c)
+/* RTC_I2C_DETECT_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: detect start interrupt state*/
+#define RTC_I2C_DETECT_START_INT_ST  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_ST_M  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_ST_V  0x1
+#define RTC_I2C_DETECT_START_INT_ST_S  8
+/* RTC_I2C_TX_DATA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: transit data interrupt state*/
+#define RTC_I2C_TX_DATA_INT_ST  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_ST_M  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_ST_V  0x1
+#define RTC_I2C_TX_DATA_INT_ST_S  7
+/* RTC_I2C_RX_DATA_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: receive data interrupt state*/
+#define RTC_I2C_RX_DATA_INT_ST  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_ST_M  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_ST_V  0x1
+#define RTC_I2C_RX_DATA_INT_ST_S  6
+/* RTC_I2C_ACK_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: ack error interrupt state*/
+#define RTC_I2C_ACK_ERR_INT_ST  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_ST_M  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_ST_V  0x1
+#define RTC_I2C_ACK_ERR_INT_ST_S  5
+/* RTC_I2C_TIMEOUT_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: time out interrupt state*/
+#define RTC_I2C_TIMEOUT_INT_ST  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_ST_M  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_ST_V  0x1
+#define RTC_I2C_TIMEOUT_INT_ST_S  4
+/* RTC_I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: transit complete interrupt state*/
+#define RTC_I2C_TRANS_COMPLETE_INT_ST  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_ST_M  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_ST_V  0x1
+#define RTC_I2C_TRANS_COMPLETE_INT_ST_S  3
+/* RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: master transit complete interrupt state*/
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V  0x1
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S  2
+/* RTC_I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: arbitration lost interrupt state*/
+#define RTC_I2C_ARBITRATION_LOST_INT_ST  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_ST_M  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_ST_V  0x1
+#define RTC_I2C_ARBITRATION_LOST_INT_ST_S  1
+/* RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: slave transit complete interrupt state*/
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V  0x1
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S  0
+
+#define RTC_I2C_INT_ENA_REG          (DR_REG_RTC_I2C_BASE + 0x0030)
+/* RTC_I2C_DETECT_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: enable detect start interrupt*/
+#define RTC_I2C_DETECT_START_INT_ENA  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_ENA_M  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_ENA_V  0x1
+#define RTC_I2C_DETECT_START_INT_ENA_S  8
+/* RTC_I2C_TX_DATA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: enable transit data interrupt*/
+#define RTC_I2C_TX_DATA_INT_ENA  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_ENA_M  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_ENA_V  0x1
+#define RTC_I2C_TX_DATA_INT_ENA_S  7
+/* RTC_I2C_RX_DATA_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: enable receive data interrupt*/
+#define RTC_I2C_RX_DATA_INT_ENA  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_ENA_M  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_ENA_V  0x1
+#define RTC_I2C_RX_DATA_INT_ENA_S  6
+/* RTC_I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: enable eack error interrupt*/
+#define RTC_I2C_ACK_ERR_INT_ENA  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_ENA_M  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_ENA_V  0x1
+#define RTC_I2C_ACK_ERR_INT_ENA_S  5
+/* RTC_I2C_TIMEOUT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: enable time out interrupt*/
+#define RTC_I2C_TIMEOUT_INT_ENA  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_ENA_M  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_ENA_V  0x1
+#define RTC_I2C_TIMEOUT_INT_ENA_S  4
+/* RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable transit complete interrupt*/
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V  0x1
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S  3
+/* RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: enable master transit complete interrupt*/
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V  0x1
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S  2
+/* RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable arbitration lost interrupt*/
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V  0x1
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S  1
+/* RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable slave transit complete interrupt*/
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V  0x1
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S  0
+
+#define RTC_I2C_DATA_REG          (DR_REG_RTC_I2C_BASE + 0x0034)
+/* RTC_I2C_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: i2c done*/
+#define RTC_I2C_DONE  (BIT(31))
+#define RTC_I2C_DONE_M  (BIT(31))
+#define RTC_I2C_DONE_V  0x1
+#define RTC_I2C_DONE_S  31
+/* RTC_I2C_SLAVE_TX_DATA : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: data sent by slave*/
+#define RTC_I2C_SLAVE_TX_DATA  0x000000FF
+#define RTC_I2C_SLAVE_TX_DATA_M  ((RTC_I2C_SLAVE_TX_DATA_V)<<(RTC_I2C_SLAVE_TX_DATA_S))
+#define RTC_I2C_SLAVE_TX_DATA_V  0xFF
+#define RTC_I2C_SLAVE_TX_DATA_S  8
+/* RTC_I2C_RDATA : RO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: data received*/
+#define RTC_I2C_RDATA  0x000000FF
+#define RTC_I2C_RDATA_M  ((RTC_I2C_RDATA_V)<<(RTC_I2C_RDATA_S))
+#define RTC_I2C_RDATA_V  0xFF
+#define RTC_I2C_RDATA_S  0
+
+#define RTC_I2C_CMD0_REG          (DR_REG_RTC_I2C_BASE + 0x0038)
+/* RTC_I2C_COMMAND0_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command0_done*/
+#define RTC_I2C_COMMAND0_DONE  (BIT(31))
+#define RTC_I2C_COMMAND0_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND0_DONE_V  0x1
+#define RTC_I2C_COMMAND0_DONE_S  31
+/* RTC_I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
+/*description: command0*/
+#define RTC_I2C_COMMAND0  0x00003FFF
+#define RTC_I2C_COMMAND0_M  ((RTC_I2C_COMMAND0_V)<<(RTC_I2C_COMMAND0_S))
+#define RTC_I2C_COMMAND0_V  0x3FFF
+#define RTC_I2C_COMMAND0_S  0
+
+#define RTC_I2C_CMD1_REG          (DR_REG_RTC_I2C_BASE + 0x003c)
+/* RTC_I2C_COMMAND1_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command1_done*/
+#define RTC_I2C_COMMAND1_DONE  (BIT(31))
+#define RTC_I2C_COMMAND1_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND1_DONE_V  0x1
+#define RTC_I2C_COMMAND1_DONE_S  31
+/* RTC_I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
+/*description: command1*/
+#define RTC_I2C_COMMAND1  0x00003FFF
+#define RTC_I2C_COMMAND1_M  ((RTC_I2C_COMMAND1_V)<<(RTC_I2C_COMMAND1_S))
+#define RTC_I2C_COMMAND1_V  0x3FFF
+#define RTC_I2C_COMMAND1_S  0
+
+#define RTC_I2C_CMD2_REG          (DR_REG_RTC_I2C_BASE + 0x0040)
+/* RTC_I2C_COMMAND2_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command2_done*/
+#define RTC_I2C_COMMAND2_DONE  (BIT(31))
+#define RTC_I2C_COMMAND2_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND2_DONE_V  0x1
+#define RTC_I2C_COMMAND2_DONE_S  31
+/* RTC_I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'h0902 ; */
+/*description: command2*/
+#define RTC_I2C_COMMAND2  0x00003FFF
+#define RTC_I2C_COMMAND2_M  ((RTC_I2C_COMMAND2_V)<<(RTC_I2C_COMMAND2_S))
+#define RTC_I2C_COMMAND2_V  0x3FFF
+#define RTC_I2C_COMMAND2_S  0
+
+#define RTC_I2C_CMD3_REG          (DR_REG_RTC_I2C_BASE + 0x0044)
+/* RTC_I2C_COMMAND3_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command3_done*/
+#define RTC_I2C_COMMAND3_DONE  (BIT(31))
+#define RTC_I2C_COMMAND3_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND3_DONE_V  0x1
+#define RTC_I2C_COMMAND3_DONE_S  31
+/* RTC_I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
+/*description: command3*/
+#define RTC_I2C_COMMAND3  0x00003FFF
+#define RTC_I2C_COMMAND3_M  ((RTC_I2C_COMMAND3_V)<<(RTC_I2C_COMMAND3_S))
+#define RTC_I2C_COMMAND3_V  0x3FFF
+#define RTC_I2C_COMMAND3_S  0
+
+#define RTC_I2C_CMD4_REG          (DR_REG_RTC_I2C_BASE + 0x0048)
+/* RTC_I2C_COMMAND4_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command4_done*/
+#define RTC_I2C_COMMAND4_DONE  (BIT(31))
+#define RTC_I2C_COMMAND4_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND4_DONE_V  0x1
+#define RTC_I2C_COMMAND4_DONE_S  31
+/* RTC_I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
+/*description: command4*/
+#define RTC_I2C_COMMAND4  0x00003FFF
+#define RTC_I2C_COMMAND4_M  ((RTC_I2C_COMMAND4_V)<<(RTC_I2C_COMMAND4_S))
+#define RTC_I2C_COMMAND4_V  0x3FFF
+#define RTC_I2C_COMMAND4_S  0
+
+#define RTC_I2C_CMD5_REG          (DR_REG_RTC_I2C_BASE + 0x004c)
+/* RTC_I2C_COMMAND5_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command5_done*/
+#define RTC_I2C_COMMAND5_DONE  (BIT(31))
+#define RTC_I2C_COMMAND5_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND5_DONE_V  0x1
+#define RTC_I2C_COMMAND5_DONE_S  31
+/* RTC_I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
+/*description: command5*/
+#define RTC_I2C_COMMAND5  0x00003FFF
+#define RTC_I2C_COMMAND5_M  ((RTC_I2C_COMMAND5_V)<<(RTC_I2C_COMMAND5_S))
+#define RTC_I2C_COMMAND5_V  0x3FFF
+#define RTC_I2C_COMMAND5_S  0
+
+#define RTC_I2C_CMD6_REG          (DR_REG_RTC_I2C_BASE + 0x0050)
+/* RTC_I2C_COMMAND6_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command6_done*/
+#define RTC_I2C_COMMAND6_DONE  (BIT(31))
+#define RTC_I2C_COMMAND6_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND6_DONE_V  0x1
+#define RTC_I2C_COMMAND6_DONE_S  31
+/* RTC_I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
+/*description: command6*/
+#define RTC_I2C_COMMAND6  0x00003FFF
+#define RTC_I2C_COMMAND6_M  ((RTC_I2C_COMMAND6_V)<<(RTC_I2C_COMMAND6_S))
+#define RTC_I2C_COMMAND6_V  0x3FFF
+#define RTC_I2C_COMMAND6_S  0
+
+#define RTC_I2C_CMD7_REG          (DR_REG_RTC_I2C_BASE + 0x0054)
+/* RTC_I2C_COMMAND7_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command7_done*/
+#define RTC_I2C_COMMAND7_DONE  (BIT(31))
+#define RTC_I2C_COMMAND7_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND7_DONE_V  0x1
+#define RTC_I2C_COMMAND7_DONE_S  31
+/* RTC_I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'h0904 ; */
+/*description: command7*/
+#define RTC_I2C_COMMAND7  0x00003FFF
+#define RTC_I2C_COMMAND7_M  ((RTC_I2C_COMMAND7_V)<<(RTC_I2C_COMMAND7_S))
+#define RTC_I2C_COMMAND7_V  0x3FFF
+#define RTC_I2C_COMMAND7_S  0
+
+#define RTC_I2C_CMD8_REG          (DR_REG_RTC_I2C_BASE + 0x0058)
+/* RTC_I2C_COMMAND8_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command8_done*/
+#define RTC_I2C_COMMAND8_DONE  (BIT(31))
+#define RTC_I2C_COMMAND8_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND8_DONE_V  0x1
+#define RTC_I2C_COMMAND8_DONE_S  31
+/* RTC_I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
+/*description: command8*/
+#define RTC_I2C_COMMAND8  0x00003FFF
+#define RTC_I2C_COMMAND8_M  ((RTC_I2C_COMMAND8_V)<<(RTC_I2C_COMMAND8_S))
+#define RTC_I2C_COMMAND8_V  0x3FFF
+#define RTC_I2C_COMMAND8_S  0
+
+#define RTC_I2C_CMD9_REG          (DR_REG_RTC_I2C_BASE + 0x005c)
+/* RTC_I2C_COMMAND9_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command9_done*/
+#define RTC_I2C_COMMAND9_DONE  (BIT(31))
+#define RTC_I2C_COMMAND9_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND9_DONE_V  0x1
+#define RTC_I2C_COMMAND9_DONE_S  31
+/* RTC_I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
+/*description: command9*/
+#define RTC_I2C_COMMAND9  0x00003FFF
+#define RTC_I2C_COMMAND9_M  ((RTC_I2C_COMMAND9_V)<<(RTC_I2C_COMMAND9_S))
+#define RTC_I2C_COMMAND9_V  0x3FFF
+#define RTC_I2C_COMMAND9_S  0
+
+#define RTC_I2C_CMD10_REG          (DR_REG_RTC_I2C_BASE + 0x0060)
+/* RTC_I2C_COMMAND10_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command10_done*/
+#define RTC_I2C_COMMAND10_DONE  (BIT(31))
+#define RTC_I2C_COMMAND10_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND10_DONE_V  0x1
+#define RTC_I2C_COMMAND10_DONE_S  31
+/* RTC_I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
+/*description: command10*/
+#define RTC_I2C_COMMAND10  0x00003FFF
+#define RTC_I2C_COMMAND10_M  ((RTC_I2C_COMMAND10_V)<<(RTC_I2C_COMMAND10_S))
+#define RTC_I2C_COMMAND10_V  0x3FFF
+#define RTC_I2C_COMMAND10_S  0
+
+#define RTC_I2C_CMD11_REG          (DR_REG_RTC_I2C_BASE + 0x0064)
+/* RTC_I2C_COMMAND11_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command11_done*/
+#define RTC_I2C_COMMAND11_DONE  (BIT(31))
+#define RTC_I2C_COMMAND11_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND11_DONE_V  0x1
+#define RTC_I2C_COMMAND11_DONE_S  31
+/* RTC_I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
+/*description: command11*/
+#define RTC_I2C_COMMAND11  0x00003FFF
+#define RTC_I2C_COMMAND11_M  ((RTC_I2C_COMMAND11_V)<<(RTC_I2C_COMMAND11_S))
+#define RTC_I2C_COMMAND11_V  0x3FFF
+#define RTC_I2C_COMMAND11_S  0
+
+#define RTC_I2C_CMD12_REG          (DR_REG_RTC_I2C_BASE + 0x0068)
+/* RTC_I2C_COMMAND12_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command12_done*/
+#define RTC_I2C_COMMAND12_DONE  (BIT(31))
+#define RTC_I2C_COMMAND12_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND12_DONE_V  0x1
+#define RTC_I2C_COMMAND12_DONE_S  31
+/* RTC_I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
+/*description: command12*/
+#define RTC_I2C_COMMAND12  0x00003FFF
+#define RTC_I2C_COMMAND12_M  ((RTC_I2C_COMMAND12_V)<<(RTC_I2C_COMMAND12_S))
+#define RTC_I2C_COMMAND12_V  0x3FFF
+#define RTC_I2C_COMMAND12_S  0
+
+#define RTC_I2C_CMD13_REG          (DR_REG_RTC_I2C_BASE + 0x006c)
+/* RTC_I2C_COMMAND13_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command13_done*/
+#define RTC_I2C_COMMAND13_DONE  (BIT(31))
+#define RTC_I2C_COMMAND13_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND13_DONE_V  0x1
+#define RTC_I2C_COMMAND13_DONE_S  31
+/* RTC_I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
+/*description: command13*/
+#define RTC_I2C_COMMAND13  0x00003FFF
+#define RTC_I2C_COMMAND13_M  ((RTC_I2C_COMMAND13_V)<<(RTC_I2C_COMMAND13_S))
+#define RTC_I2C_COMMAND13_V  0x3FFF
+#define RTC_I2C_COMMAND13_S  0
+
+#define RTC_I2C_CMD14_REG          (DR_REG_RTC_I2C_BASE + 0x0070)
+/* RTC_I2C_COMMAND14_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command14_done*/
+#define RTC_I2C_COMMAND14_DONE  (BIT(31))
+#define RTC_I2C_COMMAND14_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND14_DONE_V  0x1
+#define RTC_I2C_COMMAND14_DONE_S  31
+/* RTC_I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: command14*/
+#define RTC_I2C_COMMAND14  0x00003FFF
+#define RTC_I2C_COMMAND14_M  ((RTC_I2C_COMMAND14_V)<<(RTC_I2C_COMMAND14_S))
+#define RTC_I2C_COMMAND14_V  0x3FFF
+#define RTC_I2C_COMMAND14_S  0
+
+#define RTC_I2C_CMD15_REG          (DR_REG_RTC_I2C_BASE + 0x0074)
+/* RTC_I2C_COMMAND15_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command15_done*/
+#define RTC_I2C_COMMAND15_DONE  (BIT(31))
+#define RTC_I2C_COMMAND15_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND15_DONE_V  0x1
+#define RTC_I2C_COMMAND15_DONE_S  31
+/* RTC_I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: command15*/
+#define RTC_I2C_COMMAND15  0x00003FFF
+#define RTC_I2C_COMMAND15_M  ((RTC_I2C_COMMAND15_V)<<(RTC_I2C_COMMAND15_S))
+#define RTC_I2C_COMMAND15_V  0x3FFF
+#define RTC_I2C_COMMAND15_S  0
+
+#define RTC_I2C_DATE_REG          (DR_REG_RTC_I2C_BASE + 0x00FC)
+/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905310 ; */
+/*description: */
+#define RTC_I2C_DATE  0x0FFFFFFF
+#define RTC_I2C_DATE_M  ((RTC_I2C_DATE_V)<<(RTC_I2C_DATE_S))
+#define RTC_I2C_DATE_V  0xFFFFFFF
+#define RTC_I2C_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_RTC_I2C_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/rtc_i2c_struct.h b/components/soc/esp32c3/include/soc/rtc_i2c_struct.h
new file mode 100644
index 0000000000..5141eebcd6
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/rtc_i2c_struct.h
@@ -0,0 +1,227 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_RTC_I2C_STRUCT_H_
+#define _SOC_RTC_I2C_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t period:        20;             /*time period that scl = 0*/
+            uint32_t reserved20:    12;
+        };
+        uint32_t val;
+    } scl_low;
+    union {
+        struct {
+            uint32_t sda_force_out:        1;       /*1=push pull  0=open drain*/
+            uint32_t scl_force_out:        1;       /*1=push pull  0=open drain*/
+            uint32_t ms_mode:              1;       /*1=master  0=slave*/
+            uint32_t trans_start:          1;       /*force start*/
+            uint32_t tx_lsb_first:         1;       /*transit lsb first*/
+            uint32_t rx_lsb_first:         1;       /*receive lsb first*/
+            uint32_t reserved6:           23;
+            uint32_t i2c_ctrl_clk_gate_en: 1;
+            uint32_t i2c_reset:            1;       /*rtc i2c sw reset*/
+            uint32_t i2cclk_en:            1;       /*rtc i2c reg clk gating*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t ack_rec:             1;        /*ack response*/
+            uint32_t slave_rw:            1;        /*slave read or write*/
+            uint32_t arb_lost:            1;        /*arbitration is lost*/
+            uint32_t bus_busy:            1;        /*bus is busy*/
+            uint32_t slave_addressed:     1;        /*slave reg sub address*/
+            uint32_t byte_trans:          1;        /*One byte transit done*/
+            uint32_t op_cnt:              2;        /*which operation is working*/
+            uint32_t reserved8:           8;
+            uint32_t shift:               8;        /*shifter content*/
+            uint32_t scl_main_state_last: 3;        /*i2c last main status*/
+            uint32_t reserved27:          1;
+            uint32_t scl_state_last:      3;        /*scl last status*/
+            uint32_t reserved31:          1;
+        };
+        uint32_t val;
+    } status;
+    union {
+        struct {
+            uint32_t time_out:  20;                 /*time out threshold*/
+            uint32_t reserved20:12;
+        };
+        uint32_t val;
+    } timeout;
+    union {
+        struct {
+            uint32_t addr:         15;              /*slave address*/
+            uint32_t reserved15:   16;
+            uint32_t en_10bit:      1;              /*i2c 10bit mode enable*/
+        };
+        uint32_t val;
+    } slave_addr;
+    union {
+        struct {
+            uint32_t period:         20;            /*time period that scl = 1*/
+            uint32_t reserved20:     12;
+        };
+        uint32_t val;
+    } scl_high;
+    union {
+        struct {
+            uint32_t sda_duty_num:20;               /*time period for SDA to toggle after SCL goes low*/
+            uint32_t reserved20:  12;
+        };
+        uint32_t val;
+    } sda_duty;
+    union {
+        struct {
+            uint32_t scl_start_period:20;           /*time period for SCL to toggle after I2C start is triggered*/
+            uint32_t reserved20:      12;
+        };
+        uint32_t val;
+    } scl_start_period;
+    union {
+        struct {
+            uint32_t scl_stop_period:20;            /*time period for SCL to stop after I2C end is triggered*/
+            uint32_t reserved20:     12;
+        };
+        uint32_t val;
+    } scl_stop_period;
+    union {
+        struct {
+            uint32_t slave_tran_comp:          1;   /*clear slave transit complete interrupt*/
+            uint32_t arbitration_lost:         1;   /*clear arbitration lost interrupt*/
+            uint32_t master_tran_comp:         1;   /*clear master transit complete interrupt*/
+            uint32_t trans_complete:           1;   /*clear transit complete interrupt*/
+            uint32_t time_out:                 1;   /*clear time out interrupt*/
+            uint32_t ack_err:                  1;   /*clear ack error interrupt*/
+            uint32_t rx_data:                  1;   /*clear receive data interrupt*/
+            uint32_t tx_data:                  1;   /*clear transit load data complete interrupt*/
+            uint32_t detect_start:             1;   /*clear detect start interrupt*/
+            uint32_t reserved9:               23;
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t slave_tran_comp:          1;   /*slave transit complete interrupt raw*/
+            uint32_t arbitration_lost:         1;   /*arbitration lost interrupt raw*/
+            uint32_t master_tran_comp:         1;   /*master transit complete interrupt raw*/
+            uint32_t trans_complete:           1;   /*transit complete interrupt raw*/
+            uint32_t time_out:                 1;   /*time out interrupt raw*/
+            uint32_t ack_err:                  1;   /*ack error interrupt raw*/
+            uint32_t rx_data:                  1;   /*receive data interrupt raw*/
+            uint32_t tx_data:                  1;   /*transit data interrupt raw*/
+            uint32_t detect_start:             1;   /*detect start interrupt raw*/
+            uint32_t reserved9:               23;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t slave_tran_comp:         1;    /*slave transit complete interrupt state*/
+            uint32_t arbitration_lost:        1;    /*arbitration lost interrupt state*/
+            uint32_t master_tran_comp:        1;    /*master transit complete interrupt state*/
+            uint32_t trans_complete:          1;    /*transit complete interrupt state*/
+            uint32_t time_out:                1;    /*time out interrupt state*/
+            uint32_t ack_err:                 1;    /*ack error interrupt state*/
+            uint32_t rx_data:                 1;    /*receive data interrupt state*/
+            uint32_t tx_data:                 1;    /*transit data interrupt state*/
+            uint32_t detect_start:            1;    /*detect start interrupt state*/
+            uint32_t reserved9:              23;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t slave_tran_comp:          1;   /*enable slave transit complete interrupt*/
+            uint32_t arbitration_lost:         1;   /*enable arbitration lost interrupt*/
+            uint32_t master_tran_comp:         1;   /*enable master transit complete interrupt*/
+            uint32_t trans_complete:           1;   /*enable transit complete interrupt*/
+            uint32_t time_out:                 1;   /*enable time out interrupt*/
+            uint32_t ack_err:                  1;   /*enable eack error interrupt*/
+            uint32_t rx_data:                  1;   /*enable receive data interrupt*/
+            uint32_t tx_data:                  1;   /*enable transit data interrupt*/
+            uint32_t detect_start:             1;   /*enable detect start interrupt*/
+            uint32_t reserved9:               23;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t i2c_rdata:     8;              /*data received*/
+            uint32_t slave_tx_data: 8;              /*data sent by slave*/
+            uint32_t reserved16:   15;
+            uint32_t i2c_done:      1;              /*i2c done*/
+        };
+        uint32_t val;
+    } fifo_data;
+    union {
+        struct {
+            uint32_t command0:     14;              /*command0*/
+            uint32_t reserved14:   17;
+            uint32_t done:          1;              /*command0_done*/
+        };
+        uint32_t val;
+    } command[16];
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    union {
+        struct {
+            uint32_t i2c_date:  28;
+            uint32_t reserved28: 4;
+        };
+        uint32_t val;
+    } date;
+} rtc_i2c_dev_t;
+extern rtc_i2c_dev_t RTC_I2C;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_RTC_I2C_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/rtc_io_caps.h b/components/soc/esp32c3/include/soc/rtc_io_caps.h
new file mode 100644
index 0000000000..17aad447f7
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/rtc_io_caps.h
@@ -0,0 +1,24 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported
+ * for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
+#define SOC_RTCIO_PIN_COUNT    0
+
+#define RTCIO_LL_PIN_FUNC     0
+
+#define SOC_RTCIO_HOLD_SUPPORTED 1
+#define SOC_RTCIO_WAKE_SUPPORTED 1
diff --git a/components/soc/esp32c3/include/soc/sens_reg.h b/components/soc/esp32c3/include/soc/sens_reg.h
new file mode 100644
index 0000000000..95420e84a2
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/sens_reg.h
@@ -0,0 +1,1733 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SENS_REG_H_
+#define _SOC_SENS_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define SENS_SAR_READER1_CTRL_REG          (DR_REG_SENS_BASE + 0x0000)
+/* SENS_SAR1_INT_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: enable saradc1 to send out interrupt*/
+#define SENS_SAR1_INT_EN  (BIT(29))
+#define SENS_SAR1_INT_EN_M  (BIT(29))
+#define SENS_SAR1_INT_EN_V  0x1
+#define SENS_SAR1_INT_EN_S  29
+/* SENS_SAR1_DATA_INV : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: Invert SAR ADC1 data*/
+#define SENS_SAR1_DATA_INV  (BIT(28))
+#define SENS_SAR1_DATA_INV_M  (BIT(28))
+#define SENS_SAR1_DATA_INV_V  0x1
+#define SENS_SAR1_DATA_INV_S  28
+/* SENS_SAR1_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
+/*description: */
+#define SENS_SAR1_SAMPLE_NUM  0x000000FF
+#define SENS_SAR1_SAMPLE_NUM_M  ((SENS_SAR1_SAMPLE_NUM_V)<<(SENS_SAR1_SAMPLE_NUM_S))
+#define SENS_SAR1_SAMPLE_NUM_V  0xFF
+#define SENS_SAR1_SAMPLE_NUM_S  19
+/* SENS_SAR1_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: */
+#define SENS_SAR1_CLK_GATED  (BIT(18))
+#define SENS_SAR1_CLK_GATED_M  (BIT(18))
+#define SENS_SAR1_CLK_GATED_V  0x1
+#define SENS_SAR1_CLK_GATED_S  18
+/* SENS_SAR1_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
+/*description: clock divider*/
+#define SENS_SAR1_CLK_DIV  0x000000FF
+#define SENS_SAR1_CLK_DIV_M  ((SENS_SAR1_CLK_DIV_V)<<(SENS_SAR1_CLK_DIV_S))
+#define SENS_SAR1_CLK_DIV_V  0xFF
+#define SENS_SAR1_CLK_DIV_S  0
+
+#define SENS_SAR_READER1_STATUS_REG          (DR_REG_SENS_BASE + 0x0004)
+/* SENS_SAR1_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SENS_SAR1_READER_STATUS  0xFFFFFFFF
+#define SENS_SAR1_READER_STATUS_M  ((SENS_SAR1_READER_STATUS_V)<<(SENS_SAR1_READER_STATUS_S))
+#define SENS_SAR1_READER_STATUS_V  0xFFFFFFFF
+#define SENS_SAR1_READER_STATUS_S  0
+
+#define SENS_SAR_MEAS1_CTRL1_REG          (DR_REG_SENS_BASE + 0x0008)
+/* SENS_AMP_SHORT_REF_GND_FORCE : R/W ;bitpos:[31:30] ;default: 2'b0 ; */
+/*description: */
+#define SENS_AMP_SHORT_REF_GND_FORCE  0x00000003
+#define SENS_AMP_SHORT_REF_GND_FORCE_M  ((SENS_AMP_SHORT_REF_GND_FORCE_V)<<(SENS_AMP_SHORT_REF_GND_FORCE_S))
+#define SENS_AMP_SHORT_REF_GND_FORCE_V  0x3
+#define SENS_AMP_SHORT_REF_GND_FORCE_S  30
+/* SENS_AMP_SHORT_REF_FORCE : R/W ;bitpos:[29:28] ;default: 2'b0 ; */
+/*description: */
+#define SENS_AMP_SHORT_REF_FORCE  0x00000003
+#define SENS_AMP_SHORT_REF_FORCE_M  ((SENS_AMP_SHORT_REF_FORCE_V)<<(SENS_AMP_SHORT_REF_FORCE_S))
+#define SENS_AMP_SHORT_REF_FORCE_V  0x3
+#define SENS_AMP_SHORT_REF_FORCE_S  28
+/* SENS_AMP_RST_FB_FORCE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */
+/*description: */
+#define SENS_AMP_RST_FB_FORCE  0x00000003
+#define SENS_AMP_RST_FB_FORCE_M  ((SENS_AMP_RST_FB_FORCE_V)<<(SENS_AMP_RST_FB_FORCE_S))
+#define SENS_AMP_RST_FB_FORCE_V  0x3
+#define SENS_AMP_RST_FB_FORCE_S  26
+/* SENS_FORCE_XPD_AMP : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: */
+#define SENS_FORCE_XPD_AMP  0x00000003
+#define SENS_FORCE_XPD_AMP_M  ((SENS_FORCE_XPD_AMP_V)<<(SENS_FORCE_XPD_AMP_S))
+#define SENS_FORCE_XPD_AMP_V  0x3
+#define SENS_FORCE_XPD_AMP_S  24
+#define SENS_FORCE_XPD_AMP_FSM 0 // Use FSM to control power down
+#define SENS_FORCE_XPD_AMP_PD  2 // Force power down
+#define SENS_FORCE_XPD_AMP_PU  3 // Force power up
+
+#define SENS_SAR_MEAS1_CTRL2_REG          (DR_REG_SENS_BASE + 0x000c)
+/* SENS_SAR1_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 1: SAR ADC1 pad enable bitmap is controlled by SW*/
+#define SENS_SAR1_EN_PAD_FORCE  (BIT(31))
+#define SENS_SAR1_EN_PAD_FORCE_M  (BIT(31))
+#define SENS_SAR1_EN_PAD_FORCE_V  0x1
+#define SENS_SAR1_EN_PAD_FORCE_S  31
+/* SENS_SAR1_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */
+/*description: SAR ADC1 pad enable bitmap*/
+#define SENS_SAR1_EN_PAD  0x00000FFF
+#define SENS_SAR1_EN_PAD_M  ((SENS_SAR1_EN_PAD_V)<<(SENS_SAR1_EN_PAD_S))
+#define SENS_SAR1_EN_PAD_V  0xFFF
+#define SENS_SAR1_EN_PAD_S  19
+/* SENS_MEAS1_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: 1: SAR ADC1 controller (in RTC) is started by SW*/
+#define SENS_MEAS1_START_FORCE  (BIT(18))
+#define SENS_MEAS1_START_FORCE_M  (BIT(18))
+#define SENS_MEAS1_START_FORCE_V  0x1
+#define SENS_MEAS1_START_FORCE_S  18
+/* SENS_MEAS1_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: SAR ADC1 controller (in RTC) starts conversion*/
+#define SENS_MEAS1_START_SAR  (BIT(17))
+#define SENS_MEAS1_START_SAR_M  (BIT(17))
+#define SENS_MEAS1_START_SAR_V  0x1
+#define SENS_MEAS1_START_SAR_S  17
+/* SENS_MEAS1_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: SAR ADC1 conversion done indication*/
+#define SENS_MEAS1_DONE_SAR  (BIT(16))
+#define SENS_MEAS1_DONE_SAR_M  (BIT(16))
+#define SENS_MEAS1_DONE_SAR_V  0x1
+#define SENS_MEAS1_DONE_SAR_S  16
+/* SENS_MEAS1_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: SAR ADC1 data*/
+#define SENS_MEAS1_DATA_SAR  0x0000FFFF
+#define SENS_MEAS1_DATA_SAR_M  ((SENS_MEAS1_DATA_SAR_V)<<(SENS_MEAS1_DATA_SAR_S))
+#define SENS_MEAS1_DATA_SAR_V  0xFFFF
+#define SENS_MEAS1_DATA_SAR_S  0
+
+#define SENS_SAR_MEAS1_MUX_REG          (DR_REG_SENS_BASE + 0x0010)
+/* SENS_SAR1_DIG_FORCE : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: 1: SAR ADC1 controlled by DIG ADC1 CTRL*/
+#define SENS_SAR1_DIG_FORCE  (BIT(31))
+#define SENS_SAR1_DIG_FORCE_M  (BIT(31))
+#define SENS_SAR1_DIG_FORCE_V  0x1
+#define SENS_SAR1_DIG_FORCE_S  31
+
+#define SENS_SAR_ATTEN1_REG          (DR_REG_SENS_BASE + 0x0014)
+/* SENS_SAR1_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: 2-bit attenuation for each pad*/
+#define SENS_SAR1_ATTEN  0xFFFFFFFF
+#define SENS_SAR1_ATTEN_M  ((SENS_SAR1_ATTEN_V)<<(SENS_SAR1_ATTEN_S))
+#define SENS_SAR1_ATTEN_V  0xFFFFFFFF
+#define SENS_SAR1_ATTEN_S  0
+
+#define SENS_SAR_AMP_CTRL1_REG          (DR_REG_SENS_BASE + 0x0018)
+/* SENS_SAR_AMP_WAIT2 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */
+/*description: */
+#define SENS_SAR_AMP_WAIT2  0x0000FFFF
+#define SENS_SAR_AMP_WAIT2_M  ((SENS_SAR_AMP_WAIT2_V)<<(SENS_SAR_AMP_WAIT2_S))
+#define SENS_SAR_AMP_WAIT2_V  0xFFFF
+#define SENS_SAR_AMP_WAIT2_S  16
+/* SENS_SAR_AMP_WAIT1 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */
+/*description: */
+#define SENS_SAR_AMP_WAIT1  0x0000FFFF
+#define SENS_SAR_AMP_WAIT1_M  ((SENS_SAR_AMP_WAIT1_V)<<(SENS_SAR_AMP_WAIT1_S))
+#define SENS_SAR_AMP_WAIT1_V  0xFFFF
+#define SENS_SAR_AMP_WAIT1_S  0
+
+#define SENS_SAR_AMP_CTRL2_REG          (DR_REG_SENS_BASE + 0x001c)
+/* SENS_SAR_AMP_WAIT3 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */
+/*description: */
+#define SENS_SAR_AMP_WAIT3  0x0000FFFF
+#define SENS_SAR_AMP_WAIT3_M  ((SENS_SAR_AMP_WAIT3_V)<<(SENS_SAR_AMP_WAIT3_S))
+#define SENS_SAR_AMP_WAIT3_V  0xFFFF
+#define SENS_SAR_AMP_WAIT3_S  16
+/* SENS_SAR_RSTB_FSM_IDLE : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SENS_SAR_RSTB_FSM_IDLE  (BIT(6))
+#define SENS_SAR_RSTB_FSM_IDLE_M  (BIT(6))
+#define SENS_SAR_RSTB_FSM_IDLE_V  0x1
+#define SENS_SAR_RSTB_FSM_IDLE_S  6
+/* SENS_XPD_SAR_FSM_IDLE : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SENS_XPD_SAR_FSM_IDLE  (BIT(5))
+#define SENS_XPD_SAR_FSM_IDLE_M  (BIT(5))
+#define SENS_XPD_SAR_FSM_IDLE_V  0x1
+#define SENS_XPD_SAR_FSM_IDLE_S  5
+/* SENS_AMP_SHORT_REF_GND_FSM_IDLE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SENS_AMP_SHORT_REF_GND_FSM_IDLE  (BIT(4))
+#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_M  (BIT(4))
+#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_V  0x1
+#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_S  4
+/* SENS_AMP_SHORT_REF_FSM_IDLE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SENS_AMP_SHORT_REF_FSM_IDLE  (BIT(3))
+#define SENS_AMP_SHORT_REF_FSM_IDLE_M  (BIT(3))
+#define SENS_AMP_SHORT_REF_FSM_IDLE_V  0x1
+#define SENS_AMP_SHORT_REF_FSM_IDLE_S  3
+/* SENS_AMP_RST_FB_FSM_IDLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SENS_AMP_RST_FB_FSM_IDLE  (BIT(2))
+#define SENS_AMP_RST_FB_FSM_IDLE_M  (BIT(2))
+#define SENS_AMP_RST_FB_FSM_IDLE_V  0x1
+#define SENS_AMP_RST_FB_FSM_IDLE_S  2
+/* SENS_XPD_SAR_AMP_FSM_IDLE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SENS_XPD_SAR_AMP_FSM_IDLE  (BIT(1))
+#define SENS_XPD_SAR_AMP_FSM_IDLE_M  (BIT(1))
+#define SENS_XPD_SAR_AMP_FSM_IDLE_V  0x1
+#define SENS_XPD_SAR_AMP_FSM_IDLE_S  1
+/* SENS_SAR1_DAC_XPD_FSM_IDLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENS_SAR1_DAC_XPD_FSM_IDLE  (BIT(0))
+#define SENS_SAR1_DAC_XPD_FSM_IDLE_M  (BIT(0))
+#define SENS_SAR1_DAC_XPD_FSM_IDLE_V  0x1
+#define SENS_SAR1_DAC_XPD_FSM_IDLE_S  0
+
+#define SENS_SAR_AMP_CTRL3_REG          (DR_REG_SENS_BASE + 0x0020)
+/* SENS_SAR_RSTB_FSM : R/W ;bitpos:[27:24] ;default: 4'b0000 ; */
+/*description: */
+#define SENS_SAR_RSTB_FSM  0x0000000F
+#define SENS_SAR_RSTB_FSM_M  ((SENS_SAR_RSTB_FSM_V)<<(SENS_SAR_RSTB_FSM_S))
+#define SENS_SAR_RSTB_FSM_V  0xF
+#define SENS_SAR_RSTB_FSM_S  24
+/* SENS_XPD_SAR_FSM : R/W ;bitpos:[23:20] ;default: 4'b0111 ; */
+/*description: */
+#define SENS_XPD_SAR_FSM  0x0000000F
+#define SENS_XPD_SAR_FSM_M  ((SENS_XPD_SAR_FSM_V)<<(SENS_XPD_SAR_FSM_S))
+#define SENS_XPD_SAR_FSM_V  0xF
+#define SENS_XPD_SAR_FSM_S  20
+/* SENS_AMP_SHORT_REF_GND_FSM : R/W ;bitpos:[19:16] ;default: 4'b0011 ; */
+/*description: */
+#define SENS_AMP_SHORT_REF_GND_FSM  0x0000000F
+#define SENS_AMP_SHORT_REF_GND_FSM_M  ((SENS_AMP_SHORT_REF_GND_FSM_V)<<(SENS_AMP_SHORT_REF_GND_FSM_S))
+#define SENS_AMP_SHORT_REF_GND_FSM_V  0xF
+#define SENS_AMP_SHORT_REF_GND_FSM_S  16
+/* SENS_AMP_SHORT_REF_FSM : R/W ;bitpos:[15:12] ;default: 4'b0011 ; */
+/*description: */
+#define SENS_AMP_SHORT_REF_FSM  0x0000000F
+#define SENS_AMP_SHORT_REF_FSM_M  ((SENS_AMP_SHORT_REF_FSM_V)<<(SENS_AMP_SHORT_REF_FSM_S))
+#define SENS_AMP_SHORT_REF_FSM_V  0xF
+#define SENS_AMP_SHORT_REF_FSM_S  12
+/* SENS_AMP_RST_FB_FSM : R/W ;bitpos:[11:8] ;default: 4'b1000 ; */
+/*description: */
+#define SENS_AMP_RST_FB_FSM  0x0000000F
+#define SENS_AMP_RST_FB_FSM_M  ((SENS_AMP_RST_FB_FSM_V)<<(SENS_AMP_RST_FB_FSM_S))
+#define SENS_AMP_RST_FB_FSM_V  0xF
+#define SENS_AMP_RST_FB_FSM_S  8
+/* SENS_XPD_SAR_AMP_FSM : R/W ;bitpos:[7:4] ;default: 4'b1111 ; */
+/*description: */
+#define SENS_XPD_SAR_AMP_FSM  0x0000000F
+#define SENS_XPD_SAR_AMP_FSM_M  ((SENS_XPD_SAR_AMP_FSM_V)<<(SENS_XPD_SAR_AMP_FSM_S))
+#define SENS_XPD_SAR_AMP_FSM_V  0xF
+#define SENS_XPD_SAR_AMP_FSM_S  4
+/* SENS_SAR1_DAC_XPD_FSM : R/W ;bitpos:[3:0] ;default: 4'b0011 ; */
+/*description: */
+#define SENS_SAR1_DAC_XPD_FSM  0x0000000F
+#define SENS_SAR1_DAC_XPD_FSM_M  ((SENS_SAR1_DAC_XPD_FSM_V)<<(SENS_SAR1_DAC_XPD_FSM_S))
+#define SENS_SAR1_DAC_XPD_FSM_V  0xF
+#define SENS_SAR1_DAC_XPD_FSM_S  0
+
+#define SENS_SAR_READER2_CTRL_REG          (DR_REG_SENS_BASE + 0x0024)
+/* SENS_SAR2_INT_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: enable saradc2 to send out interrupt*/
+#define SENS_SAR2_INT_EN  (BIT(30))
+#define SENS_SAR2_INT_EN_M  (BIT(30))
+#define SENS_SAR2_INT_EN_V  0x1
+#define SENS_SAR2_INT_EN_S  30
+/* SENS_SAR2_DATA_INV : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Invert SAR ADC2 data*/
+#define SENS_SAR2_DATA_INV  (BIT(29))
+#define SENS_SAR2_DATA_INV_M  (BIT(29))
+#define SENS_SAR2_DATA_INV_V  0x1
+#define SENS_SAR2_DATA_INV_S  29
+/* SENS_SAR2_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
+/*description: */
+#define SENS_SAR2_SAMPLE_NUM  0x000000FF
+#define SENS_SAR2_SAMPLE_NUM_M  ((SENS_SAR2_SAMPLE_NUM_V)<<(SENS_SAR2_SAMPLE_NUM_S))
+#define SENS_SAR2_SAMPLE_NUM_V  0xFF
+#define SENS_SAR2_SAMPLE_NUM_S  19
+/* SENS_SAR2_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: */
+#define SENS_SAR2_CLK_GATED  (BIT(18))
+#define SENS_SAR2_CLK_GATED_M  (BIT(18))
+#define SENS_SAR2_CLK_GATED_V  0x1
+#define SENS_SAR2_CLK_GATED_S  18
+/* SENS_SAR2_WAIT_ARB_CYCLE : R/W ;bitpos:[17:16] ;default: 2'b1 ; */
+/*description: wait arbit stable after sar_done*/
+#define SENS_SAR2_WAIT_ARB_CYCLE  0x00000003
+#define SENS_SAR2_WAIT_ARB_CYCLE_M  ((SENS_SAR2_WAIT_ARB_CYCLE_V)<<(SENS_SAR2_WAIT_ARB_CYCLE_S))
+#define SENS_SAR2_WAIT_ARB_CYCLE_V  0x3
+#define SENS_SAR2_WAIT_ARB_CYCLE_S  16
+/* SENS_SAR2_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
+/*description: clock divider*/
+#define SENS_SAR2_CLK_DIV  0x000000FF
+#define SENS_SAR2_CLK_DIV_M  ((SENS_SAR2_CLK_DIV_V)<<(SENS_SAR2_CLK_DIV_S))
+#define SENS_SAR2_CLK_DIV_V  0xFF
+#define SENS_SAR2_CLK_DIV_S  0
+
+#define SENS_SAR_READER2_STATUS_REG          (DR_REG_SENS_BASE + 0x0028)
+/* SENS_SAR2_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SENS_SAR2_READER_STATUS  0xFFFFFFFF
+#define SENS_SAR2_READER_STATUS_M  ((SENS_SAR2_READER_STATUS_V)<<(SENS_SAR2_READER_STATUS_S))
+#define SENS_SAR2_READER_STATUS_V  0xFFFFFFFF
+#define SENS_SAR2_READER_STATUS_S  0
+
+#define SENS_SAR_MEAS2_CTRL1_REG          (DR_REG_SENS_BASE + 0x002c)
+/* SENS_SAR2_XPD_WAIT : R/W ;bitpos:[31:24] ;default: 8'h7 ; */
+/*description: */
+#define SENS_SAR2_XPD_WAIT  0x000000FF
+#define SENS_SAR2_XPD_WAIT_M  ((SENS_SAR2_XPD_WAIT_V)<<(SENS_SAR2_XPD_WAIT_S))
+#define SENS_SAR2_XPD_WAIT_V  0xFF
+#define SENS_SAR2_XPD_WAIT_S  24
+/* SENS_SAR2_RSTB_WAIT : R/W ;bitpos:[23:16] ;default: 8'd2 ; */
+/*description: */
+#define SENS_SAR2_RSTB_WAIT  0x000000FF
+#define SENS_SAR2_RSTB_WAIT_M  ((SENS_SAR2_RSTB_WAIT_V)<<(SENS_SAR2_RSTB_WAIT_S))
+#define SENS_SAR2_RSTB_WAIT_V  0xFF
+#define SENS_SAR2_RSTB_WAIT_S  16
+/* SENS_SAR2_STANDBY_WAIT : R/W ;bitpos:[15:8] ;default: 8'd2 ; */
+/*description: */
+#define SENS_SAR2_STANDBY_WAIT  0x000000FF
+#define SENS_SAR2_STANDBY_WAIT_M  ((SENS_SAR2_STANDBY_WAIT_V)<<(SENS_SAR2_STANDBY_WAIT_S))
+#define SENS_SAR2_STANDBY_WAIT_V  0xFF
+#define SENS_SAR2_STANDBY_WAIT_S  8
+/* SENS_SAR2_RSTB_FORCE : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: */
+#define SENS_SAR2_RSTB_FORCE  0x00000003
+#define SENS_SAR2_RSTB_FORCE_M  ((SENS_SAR2_RSTB_FORCE_V)<<(SENS_SAR2_RSTB_FORCE_S))
+#define SENS_SAR2_RSTB_FORCE_V  0x3
+#define SENS_SAR2_RSTB_FORCE_S  6
+/* SENS_SAR2_EN_TEST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: SAR2_EN_TEST*/
+#define SENS_SAR2_EN_TEST  (BIT(5))
+#define SENS_SAR2_EN_TEST_M  (BIT(5))
+#define SENS_SAR2_EN_TEST_V  0x1
+#define SENS_SAR2_EN_TEST_S  5
+/* SENS_SAR2_PKDET_CAL_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: rtc control pkdet enable*/
+#define SENS_SAR2_PKDET_CAL_EN  (BIT(4))
+#define SENS_SAR2_PKDET_CAL_EN_M  (BIT(4))
+#define SENS_SAR2_PKDET_CAL_EN_V  0x1
+#define SENS_SAR2_PKDET_CAL_EN_S  4
+/* SENS_SAR2_PWDET_CAL_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: rtc control pwdet enable*/
+#define SENS_SAR2_PWDET_CAL_EN  (BIT(3))
+#define SENS_SAR2_PWDET_CAL_EN_M  (BIT(3))
+#define SENS_SAR2_PWDET_CAL_EN_V  0x1
+#define SENS_SAR2_PWDET_CAL_EN_S  3
+/* SENS_SAR2_CNTL_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: saradc2_cntl_fsm*/
+#define SENS_SAR2_CNTL_STATE  0x00000007
+#define SENS_SAR2_CNTL_STATE_M  ((SENS_SAR2_CNTL_STATE_V)<<(SENS_SAR2_CNTL_STATE_S))
+#define SENS_SAR2_CNTL_STATE_V  0x7
+#define SENS_SAR2_CNTL_STATE_S  0
+
+#define SENS_SAR_MEAS2_CTRL2_REG          (DR_REG_SENS_BASE + 0x0030)
+/* SENS_SAR2_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 1: SAR ADC2 pad enable bitmap is controlled by SW*/
+#define SENS_SAR2_EN_PAD_FORCE  (BIT(31))
+#define SENS_SAR2_EN_PAD_FORCE_M  (BIT(31))
+#define SENS_SAR2_EN_PAD_FORCE_V  0x1
+#define SENS_SAR2_EN_PAD_FORCE_S  31
+/* SENS_SAR2_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */
+/*description: SAR ADC2 pad enable bitmap*/
+#define SENS_SAR2_EN_PAD  0x00000FFF
+#define SENS_SAR2_EN_PAD_M  ((SENS_SAR2_EN_PAD_V)<<(SENS_SAR2_EN_PAD_S))
+#define SENS_SAR2_EN_PAD_V  0xFFF
+#define SENS_SAR2_EN_PAD_S  19
+/* SENS_MEAS2_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: 1: SAR ADC2 controller (in RTC) is started by SW*/
+#define SENS_MEAS2_START_FORCE  (BIT(18))
+#define SENS_MEAS2_START_FORCE_M  (BIT(18))
+#define SENS_MEAS2_START_FORCE_V  0x1
+#define SENS_MEAS2_START_FORCE_S  18
+/* SENS_MEAS2_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: SAR ADC2 controller (in RTC) starts conversion*/
+#define SENS_MEAS2_START_SAR  (BIT(17))
+#define SENS_MEAS2_START_SAR_M  (BIT(17))
+#define SENS_MEAS2_START_SAR_V  0x1
+#define SENS_MEAS2_START_SAR_S  17
+/* SENS_MEAS2_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: SAR ADC2 conversion done indication*/
+#define SENS_MEAS2_DONE_SAR  (BIT(16))
+#define SENS_MEAS2_DONE_SAR_M  (BIT(16))
+#define SENS_MEAS2_DONE_SAR_V  0x1
+#define SENS_MEAS2_DONE_SAR_S  16
+/* SENS_MEAS2_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: SAR ADC2 data*/
+#define SENS_MEAS2_DATA_SAR  0x0000FFFF
+#define SENS_MEAS2_DATA_SAR_M  ((SENS_MEAS2_DATA_SAR_V)<<(SENS_MEAS2_DATA_SAR_S))
+#define SENS_MEAS2_DATA_SAR_V  0xFFFF
+#define SENS_MEAS2_DATA_SAR_S  0
+
+#define SENS_SAR_MEAS2_MUX_REG          (DR_REG_SENS_BASE + 0x0034)
+/* SENS_SAR2_RTC_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: in sleep  force to use rtc to control ADC*/
+#define SENS_SAR2_RTC_FORCE  (BIT(31))
+#define SENS_SAR2_RTC_FORCE_M  (BIT(31))
+#define SENS_SAR2_RTC_FORCE_V  0x1
+#define SENS_SAR2_RTC_FORCE_S  31
+/* SENS_SAR2_PWDET_CCT : R/W ;bitpos:[30:28] ;default: 3'b0 ; */
+/*description: SAR2_PWDET_CCT*/
+#define SENS_SAR2_PWDET_CCT  0x00000007
+#define SENS_SAR2_PWDET_CCT_M  ((SENS_SAR2_PWDET_CCT_V)<<(SENS_SAR2_PWDET_CCT_S))
+#define SENS_SAR2_PWDET_CCT_V  0x7
+#define SENS_SAR2_PWDET_CCT_S  28
+
+#define SENS_SAR_ATTEN2_REG          (DR_REG_SENS_BASE + 0x0038)
+/* SENS_SAR2_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: 2-bit attenuation for each pad*/
+#define SENS_SAR2_ATTEN  0xFFFFFFFF
+#define SENS_SAR2_ATTEN_M  ((SENS_SAR2_ATTEN_V)<<(SENS_SAR2_ATTEN_S))
+#define SENS_SAR2_ATTEN_V  0xFFFFFFFF
+#define SENS_SAR2_ATTEN_S  0
+
+#define SENS_SAR_POWER_XPD_SAR_REG          (DR_REG_SENS_BASE + 0x003c)
+/* SENS_SARCLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define SENS_SARCLK_EN  (BIT(31))
+#define SENS_SARCLK_EN_M  (BIT(31))
+#define SENS_SARCLK_EN_V  0x1
+#define SENS_SARCLK_EN_S  31
+/* SENS_FORCE_XPD_SAR : R/W ;bitpos:[30:29] ;default: 2'd0 ; */
+/*description: */
+#define SENS_FORCE_XPD_SAR  0x00000003
+#define SENS_FORCE_XPD_SAR_M  ((SENS_FORCE_XPD_SAR_V)<<(SENS_FORCE_XPD_SAR_S))
+#define SENS_FORCE_XPD_SAR_V  0x3
+#define SENS_FORCE_XPD_SAR_S  29
+
+#define SENS_SAR_SLAVE_ADDR1_REG          (DR_REG_SENS_BASE + 0x0040)
+/* SENS_MEAS_STATUS : RO ;bitpos:[29:22] ;default: 8'h0 ; */
+/*description: */
+#define SENS_MEAS_STATUS  0x000000FF
+#define SENS_MEAS_STATUS_M  ((SENS_MEAS_STATUS_V)<<(SENS_MEAS_STATUS_S))
+#define SENS_MEAS_STATUS_V  0xFF
+#define SENS_MEAS_STATUS_S  22
+/* SENS_I2C_SLAVE_ADDR0 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR0  0x000007FF
+#define SENS_I2C_SLAVE_ADDR0_M  ((SENS_I2C_SLAVE_ADDR0_V)<<(SENS_I2C_SLAVE_ADDR0_S))
+#define SENS_I2C_SLAVE_ADDR0_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR0_S  11
+/* SENS_I2C_SLAVE_ADDR1 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR1  0x000007FF
+#define SENS_I2C_SLAVE_ADDR1_M  ((SENS_I2C_SLAVE_ADDR1_V)<<(SENS_I2C_SLAVE_ADDR1_S))
+#define SENS_I2C_SLAVE_ADDR1_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR1_S  0
+
+#define SENS_SAR_SLAVE_ADDR2_REG          (DR_REG_SENS_BASE + 0x0044)
+/* SENS_I2C_SLAVE_ADDR2 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR2  0x000007FF
+#define SENS_I2C_SLAVE_ADDR2_M  ((SENS_I2C_SLAVE_ADDR2_V)<<(SENS_I2C_SLAVE_ADDR2_S))
+#define SENS_I2C_SLAVE_ADDR2_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR2_S  11
+/* SENS_I2C_SLAVE_ADDR3 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR3  0x000007FF
+#define SENS_I2C_SLAVE_ADDR3_M  ((SENS_I2C_SLAVE_ADDR3_V)<<(SENS_I2C_SLAVE_ADDR3_S))
+#define SENS_I2C_SLAVE_ADDR3_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR3_S  0
+
+#define SENS_SAR_SLAVE_ADDR3_REG          (DR_REG_SENS_BASE + 0x0048)
+/* SENS_I2C_SLAVE_ADDR4 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR4  0x000007FF
+#define SENS_I2C_SLAVE_ADDR4_M  ((SENS_I2C_SLAVE_ADDR4_V)<<(SENS_I2C_SLAVE_ADDR4_S))
+#define SENS_I2C_SLAVE_ADDR4_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR4_S  11
+/* SENS_I2C_SLAVE_ADDR5 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR5  0x000007FF
+#define SENS_I2C_SLAVE_ADDR5_M  ((SENS_I2C_SLAVE_ADDR5_V)<<(SENS_I2C_SLAVE_ADDR5_S))
+#define SENS_I2C_SLAVE_ADDR5_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR5_S  0
+
+#define SENS_SAR_SLAVE_ADDR4_REG          (DR_REG_SENS_BASE + 0x004c)
+/* SENS_I2C_SLAVE_ADDR6 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR6  0x000007FF
+#define SENS_I2C_SLAVE_ADDR6_M  ((SENS_I2C_SLAVE_ADDR6_V)<<(SENS_I2C_SLAVE_ADDR6_S))
+#define SENS_I2C_SLAVE_ADDR6_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR6_S  11
+/* SENS_I2C_SLAVE_ADDR7 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR7  0x000007FF
+#define SENS_I2C_SLAVE_ADDR7_M  ((SENS_I2C_SLAVE_ADDR7_V)<<(SENS_I2C_SLAVE_ADDR7_S))
+#define SENS_I2C_SLAVE_ADDR7_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR7_S  0
+
+#define SENS_SAR_TSENS_CTRL_REG          (DR_REG_SENS_BASE + 0x0050)
+/* SENS_TSENS_DUMP_OUT : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: temperature sensor dump out*/
+#define SENS_TSENS_DUMP_OUT  (BIT(24))
+#define SENS_TSENS_DUMP_OUT_M  (BIT(24))
+#define SENS_TSENS_DUMP_OUT_V  0x1
+#define SENS_TSENS_DUMP_OUT_S  24
+/* SENS_TSENS_POWER_UP_FORCE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: 1: dump out & power up controlled by SW*/
+#define SENS_TSENS_POWER_UP_FORCE  (BIT(23))
+#define SENS_TSENS_POWER_UP_FORCE_M  (BIT(23))
+#define SENS_TSENS_POWER_UP_FORCE_V  0x1
+#define SENS_TSENS_POWER_UP_FORCE_S  23
+/* SENS_TSENS_POWER_UP : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: temperature sensor power up*/
+#define SENS_TSENS_POWER_UP  (BIT(22))
+#define SENS_TSENS_POWER_UP_M  (BIT(22))
+#define SENS_TSENS_POWER_UP_V  0x1
+#define SENS_TSENS_POWER_UP_S  22
+/* SENS_TSENS_CLK_DIV : R/W ;bitpos:[21:14] ;default: 8'd6 ; */
+/*description: temperature sensor clock divider*/
+#define SENS_TSENS_CLK_DIV  0x000000FF
+#define SENS_TSENS_CLK_DIV_M  ((SENS_TSENS_CLK_DIV_V)<<(SENS_TSENS_CLK_DIV_S))
+#define SENS_TSENS_CLK_DIV_V  0xFF
+#define SENS_TSENS_CLK_DIV_S  14
+/* SENS_TSENS_IN_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: invert temperature sensor data*/
+#define SENS_TSENS_IN_INV  (BIT(13))
+#define SENS_TSENS_IN_INV_M  (BIT(13))
+#define SENS_TSENS_IN_INV_V  0x1
+#define SENS_TSENS_IN_INV_S  13
+/* SENS_TSENS_INT_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: enable temperature sensor to send out interrupt*/
+#define SENS_TSENS_INT_EN  (BIT(12))
+#define SENS_TSENS_INT_EN_M  (BIT(12))
+#define SENS_TSENS_INT_EN_V  0x1
+#define SENS_TSENS_INT_EN_S  12
+/* SENS_TSENS_READY : RO ;bitpos:[8] ;default: 1'h0 ; */
+/*description: indicate temperature sensor out ready*/
+#define SENS_TSENS_READY  (BIT(8))
+#define SENS_TSENS_READY_M  (BIT(8))
+#define SENS_TSENS_READY_V  0x1
+#define SENS_TSENS_READY_S  8
+/* SENS_TSENS_OUT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: temperature sensor data out*/
+#define SENS_TSENS_OUT  0x000000FF
+#define SENS_TSENS_OUT_M  ((SENS_TSENS_OUT_V)<<(SENS_TSENS_OUT_S))
+#define SENS_TSENS_OUT_V  0xFF
+#define SENS_TSENS_OUT_S  0
+
+#define SENS_SAR_TSENS_CTRL2_REG          (DR_REG_SENS_BASE + 0x0054)
+/* SENS_TSENS_CLK_INV : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: */
+#define SENS_TSENS_CLK_INV  (BIT(14))
+#define SENS_TSENS_CLK_INV_M  (BIT(14))
+#define SENS_TSENS_CLK_INV_V  0x1
+#define SENS_TSENS_CLK_INV_S  14
+/* SENS_TSENS_XPD_FORCE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: */
+#define SENS_TSENS_XPD_FORCE  0x00000003
+#define SENS_TSENS_XPD_FORCE_M  ((SENS_TSENS_XPD_FORCE_V)<<(SENS_TSENS_XPD_FORCE_S))
+#define SENS_TSENS_XPD_FORCE_V  0x3
+#define SENS_TSENS_XPD_FORCE_S  12
+/* SENS_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */
+/*description: */
+#define SENS_TSENS_XPD_WAIT  0x00000FFF
+#define SENS_TSENS_XPD_WAIT_M  ((SENS_TSENS_XPD_WAIT_V)<<(SENS_TSENS_XPD_WAIT_S))
+#define SENS_TSENS_XPD_WAIT_V  0xFFF
+#define SENS_TSENS_XPD_WAIT_S  0
+
+#define SENS_SAR_I2C_CTRL_REG          (DR_REG_SENS_BASE + 0x0058)
+/* SENS_SAR_I2C_START_FORCE : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: 1: I2C started by SW*/
+#define SENS_SAR_I2C_START_FORCE  (BIT(29))
+#define SENS_SAR_I2C_START_FORCE_M  (BIT(29))
+#define SENS_SAR_I2C_START_FORCE_V  0x1
+#define SENS_SAR_I2C_START_FORCE_S  29
+/* SENS_SAR_I2C_START : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: start I2C*/
+#define SENS_SAR_I2C_START  (BIT(28))
+#define SENS_SAR_I2C_START_M  (BIT(28))
+#define SENS_SAR_I2C_START_V  0x1
+#define SENS_SAR_I2C_START_S  28
+/* SENS_SAR_I2C_CTRL : R/W ;bitpos:[27:0] ;default: 28'b0 ; */
+/*description: I2C control data*/
+#define SENS_SAR_I2C_CTRL  0x0FFFFFFF
+#define SENS_SAR_I2C_CTRL_M  ((SENS_SAR_I2C_CTRL_V)<<(SENS_SAR_I2C_CTRL_S))
+#define SENS_SAR_I2C_CTRL_V  0xFFFFFFF
+#define SENS_SAR_I2C_CTRL_S  0
+
+#define SENS_SAR_TOUCH_CONF_REG          (DR_REG_SENS_BASE + 0x005c)
+/* SENS_TOUCH_APPROACH_PAD0 : R/W ;bitpos:[31:28] ;default: 4'hF ; */
+/*description: indicate which pad is approach pad0*/
+#define SENS_TOUCH_APPROACH_PAD0  0x0000000F
+#define SENS_TOUCH_APPROACH_PAD0_M  ((SENS_TOUCH_APPROACH_PAD0_V)<<(SENS_TOUCH_APPROACH_PAD0_S))
+#define SENS_TOUCH_APPROACH_PAD0_V  0xF
+#define SENS_TOUCH_APPROACH_PAD0_S  28
+/* SENS_TOUCH_APPROACH_PAD1 : R/W ;bitpos:[27:24] ;default: 4'hF ; */
+/*description: indicate which pad is approach pad1*/
+#define SENS_TOUCH_APPROACH_PAD1  0x0000000F
+#define SENS_TOUCH_APPROACH_PAD1_M  ((SENS_TOUCH_APPROACH_PAD1_V)<<(SENS_TOUCH_APPROACH_PAD1_S))
+#define SENS_TOUCH_APPROACH_PAD1_V  0xF
+#define SENS_TOUCH_APPROACH_PAD1_S  24
+/* SENS_TOUCH_APPROACH_PAD2 : R/W ;bitpos:[23:20] ;default: 4'hF ; */
+/*description: indicate which pad is approach pad2*/
+#define SENS_TOUCH_APPROACH_PAD2  0x0000000F
+#define SENS_TOUCH_APPROACH_PAD2_M  ((SENS_TOUCH_APPROACH_PAD2_V)<<(SENS_TOUCH_APPROACH_PAD2_S))
+#define SENS_TOUCH_APPROACH_PAD2_V  0xF
+#define SENS_TOUCH_APPROACH_PAD2_S  20
+/* SENS_TOUCH_UNIT_END : RO ;bitpos:[19] ;default: 1'd0 ; */
+/*description: touch_unit_done*/
+#define SENS_TOUCH_UNIT_END  (BIT(19))
+#define SENS_TOUCH_UNIT_END_M  (BIT(19))
+#define SENS_TOUCH_UNIT_END_V  0x1
+#define SENS_TOUCH_UNIT_END_S  19
+/* SENS_TOUCH_DENOISE_END : RO ;bitpos:[18] ;default: 1'd0 ; */
+/*description: touch_denoise_done*/
+#define SENS_TOUCH_DENOISE_END  (BIT(18))
+#define SENS_TOUCH_DENOISE_END_M  (BIT(18))
+#define SENS_TOUCH_DENOISE_END_V  0x1
+#define SENS_TOUCH_DENOISE_END_S  18
+/* SENS_TOUCH_DATA_SEL : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: 3: smooth data 2: baseline 1 0: raw_data*/
+#define SENS_TOUCH_DATA_SEL  0x00000003
+#define SENS_TOUCH_DATA_SEL_M  ((SENS_TOUCH_DATA_SEL_V)<<(SENS_TOUCH_DATA_SEL_S))
+#define SENS_TOUCH_DATA_SEL_V  0x3
+#define SENS_TOUCH_DATA_SEL_S  16
+/* SENS_TOUCH_STATUS_CLR : WO ;bitpos:[15] ;default: 1'd0 ; */
+/*description: clear all touch active status*/
+#define SENS_TOUCH_STATUS_CLR  (BIT(15))
+#define SENS_TOUCH_STATUS_CLR_M  (BIT(15))
+#define SENS_TOUCH_STATUS_CLR_V  0x1
+#define SENS_TOUCH_STATUS_CLR_S  15
+/* SENS_TOUCH_OUTEN : R/W ;bitpos:[14:0] ;default: 15'h7FFF ; */
+/*description: touch controller output enable*/
+#define SENS_TOUCH_OUTEN  0x00007FFF
+#define SENS_TOUCH_OUTEN_M  ((SENS_TOUCH_OUTEN_V)<<(SENS_TOUCH_OUTEN_S))
+#define SENS_TOUCH_OUTEN_V  0x7FFF
+#define SENS_TOUCH_OUTEN_S  0
+
+#define SENS_SAR_TOUCH_THRES1_REG          (DR_REG_SENS_BASE + 0x0060)
+/* SENS_TOUCH_OUT_TH1 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: Finger threshold for touch pad 1*/
+#define SENS_TOUCH_OUT_TH1  0x003FFFFF
+#define SENS_TOUCH_OUT_TH1_M  ((SENS_TOUCH_OUT_TH1_V)<<(SENS_TOUCH_OUT_TH1_S))
+#define SENS_TOUCH_OUT_TH1_V  0x3FFFFF
+#define SENS_TOUCH_OUT_TH1_S  0
+
+#define SENS_SAR_TOUCH_THRES2_REG          (DR_REG_SENS_BASE + 0x0064)
+/* SENS_TOUCH_OUT_TH2 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: Finger threshold for touch pad 2*/
+#define SENS_TOUCH_OUT_TH2  0x003FFFFF
+#define SENS_TOUCH_OUT_TH2_M  ((SENS_TOUCH_OUT_TH2_V)<<(SENS_TOUCH_OUT_TH2_S))
+#define SENS_TOUCH_OUT_TH2_V  0x3FFFFF
+#define SENS_TOUCH_OUT_TH2_S  0
+
+#define SENS_SAR_TOUCH_THRES3_REG          (DR_REG_SENS_BASE + 0x0068)
+/* SENS_TOUCH_OUT_TH3 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: Finger threshold for touch pad 3*/
+#define SENS_TOUCH_OUT_TH3  0x003FFFFF
+#define SENS_TOUCH_OUT_TH3_M  ((SENS_TOUCH_OUT_TH3_V)<<(SENS_TOUCH_OUT_TH3_S))
+#define SENS_TOUCH_OUT_TH3_V  0x3FFFFF
+#define SENS_TOUCH_OUT_TH3_S  0
+
+#define SENS_SAR_TOUCH_THRES4_REG          (DR_REG_SENS_BASE + 0x006c)
+/* SENS_TOUCH_OUT_TH4 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: Finger threshold for touch pad 4*/
+#define SENS_TOUCH_OUT_TH4  0x003FFFFF
+#define SENS_TOUCH_OUT_TH4_M  ((SENS_TOUCH_OUT_TH4_V)<<(SENS_TOUCH_OUT_TH4_S))
+#define SENS_TOUCH_OUT_TH4_V  0x3FFFFF
+#define SENS_TOUCH_OUT_TH4_S  0
+
+#define SENS_SAR_TOUCH_THRES5_REG          (DR_REG_SENS_BASE + 0x0070)
+/* SENS_TOUCH_OUT_TH5 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: Finger threshold for touch pad 5*/
+#define SENS_TOUCH_OUT_TH5  0x003FFFFF
+#define SENS_TOUCH_OUT_TH5_M  ((SENS_TOUCH_OUT_TH5_V)<<(SENS_TOUCH_OUT_TH5_S))
+#define SENS_TOUCH_OUT_TH5_V  0x3FFFFF
+#define SENS_TOUCH_OUT_TH5_S  0
+
+#define SENS_SAR_TOUCH_THRES6_REG          (DR_REG_SENS_BASE + 0x0074)
+/* SENS_TOUCH_OUT_TH6 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: Finger threshold for touch pad 6*/
+#define SENS_TOUCH_OUT_TH6  0x003FFFFF
+#define SENS_TOUCH_OUT_TH6_M  ((SENS_TOUCH_OUT_TH6_V)<<(SENS_TOUCH_OUT_TH6_S))
+#define SENS_TOUCH_OUT_TH6_V  0x3FFFFF
+#define SENS_TOUCH_OUT_TH6_S  0
+
+#define SENS_SAR_TOUCH_THRES7_REG          (DR_REG_SENS_BASE + 0x0078)
+/* SENS_TOUCH_OUT_TH7 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: Finger threshold for touch pad 7*/
+#define SENS_TOUCH_OUT_TH7  0x003FFFFF
+#define SENS_TOUCH_OUT_TH7_M  ((SENS_TOUCH_OUT_TH7_V)<<(SENS_TOUCH_OUT_TH7_S))
+#define SENS_TOUCH_OUT_TH7_V  0x3FFFFF
+#define SENS_TOUCH_OUT_TH7_S  0
+
+#define SENS_SAR_TOUCH_THRES8_REG          (DR_REG_SENS_BASE + 0x007c)
+/* SENS_TOUCH_OUT_TH8 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: Finger threshold for touch pad 8*/
+#define SENS_TOUCH_OUT_TH8  0x003FFFFF
+#define SENS_TOUCH_OUT_TH8_M  ((SENS_TOUCH_OUT_TH8_V)<<(SENS_TOUCH_OUT_TH8_S))
+#define SENS_TOUCH_OUT_TH8_V  0x3FFFFF
+#define SENS_TOUCH_OUT_TH8_S  0
+
+#define SENS_SAR_TOUCH_THRES9_REG          (DR_REG_SENS_BASE + 0x0080)
+/* SENS_TOUCH_OUT_TH9 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: Finger threshold for touch pad 9*/
+#define SENS_TOUCH_OUT_TH9  0x003FFFFF
+#define SENS_TOUCH_OUT_TH9_M  ((SENS_TOUCH_OUT_TH9_V)<<(SENS_TOUCH_OUT_TH9_S))
+#define SENS_TOUCH_OUT_TH9_V  0x3FFFFF
+#define SENS_TOUCH_OUT_TH9_S  0
+
+#define SENS_SAR_TOUCH_THRES10_REG          (DR_REG_SENS_BASE + 0x0084)
+/* SENS_TOUCH_OUT_TH10 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: Finger threshold for touch pad 10*/
+#define SENS_TOUCH_OUT_TH10  0x003FFFFF
+#define SENS_TOUCH_OUT_TH10_M  ((SENS_TOUCH_OUT_TH10_V)<<(SENS_TOUCH_OUT_TH10_S))
+#define SENS_TOUCH_OUT_TH10_V  0x3FFFFF
+#define SENS_TOUCH_OUT_TH10_S  0
+
+#define SENS_SAR_TOUCH_THRES11_REG          (DR_REG_SENS_BASE + 0x0088)
+/* SENS_TOUCH_OUT_TH11 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: Finger threshold for touch pad 11*/
+#define SENS_TOUCH_OUT_TH11  0x003FFFFF
+#define SENS_TOUCH_OUT_TH11_M  ((SENS_TOUCH_OUT_TH11_V)<<(SENS_TOUCH_OUT_TH11_S))
+#define SENS_TOUCH_OUT_TH11_V  0x3FFFFF
+#define SENS_TOUCH_OUT_TH11_S  0
+
+#define SENS_SAR_TOUCH_THRES12_REG          (DR_REG_SENS_BASE + 0x008c)
+/* SENS_TOUCH_OUT_TH12 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: Finger threshold for touch pad 12*/
+#define SENS_TOUCH_OUT_TH12  0x003FFFFF
+#define SENS_TOUCH_OUT_TH12_M  ((SENS_TOUCH_OUT_TH12_V)<<(SENS_TOUCH_OUT_TH12_S))
+#define SENS_TOUCH_OUT_TH12_V  0x3FFFFF
+#define SENS_TOUCH_OUT_TH12_S  0
+
+#define SENS_SAR_TOUCH_THRES13_REG          (DR_REG_SENS_BASE + 0x0090)
+/* SENS_TOUCH_OUT_TH13 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: Finger threshold for touch pad 13*/
+#define SENS_TOUCH_OUT_TH13  0x003FFFFF
+#define SENS_TOUCH_OUT_TH13_M  ((SENS_TOUCH_OUT_TH13_V)<<(SENS_TOUCH_OUT_TH13_S))
+#define SENS_TOUCH_OUT_TH13_V  0x3FFFFF
+#define SENS_TOUCH_OUT_TH13_S  0
+
+#define SENS_SAR_TOUCH_THRES14_REG          (DR_REG_SENS_BASE + 0x0094)
+/* SENS_TOUCH_OUT_TH14 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: Finger threshold for touch pad 14*/
+#define SENS_TOUCH_OUT_TH14  0x003FFFFF
+#define SENS_TOUCH_OUT_TH14_M  ((SENS_TOUCH_OUT_TH14_V)<<(SENS_TOUCH_OUT_TH14_S))
+#define SENS_TOUCH_OUT_TH14_V  0x3FFFFF
+#define SENS_TOUCH_OUT_TH14_S  0
+
+#define SENS_SAR_TOUCH_CHN_ST_REG          (DR_REG_SENS_BASE + 0x00d4)
+/* SENS_TOUCH_MEAS_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define SENS_TOUCH_MEAS_DONE  (BIT(31))
+#define SENS_TOUCH_MEAS_DONE_M  (BIT(31))
+#define SENS_TOUCH_MEAS_DONE_V  0x1
+#define SENS_TOUCH_MEAS_DONE_S  31
+/* SENS_TOUCH_CHANNEL_CLR : WO ;bitpos:[29:15] ;default: 15'd0 ; */
+/*description: Clear touch channel*/
+#define SENS_TOUCH_CHANNEL_CLR  0x00007FFF
+#define SENS_TOUCH_CHANNEL_CLR_M  ((SENS_TOUCH_CHANNEL_CLR_V)<<(SENS_TOUCH_CHANNEL_CLR_S))
+#define SENS_TOUCH_CHANNEL_CLR_V  0x7FFF
+#define SENS_TOUCH_CHANNEL_CLR_S  15
+/* SENS_TOUCH_PAD_ACTIVE : RO ;bitpos:[14:0] ;default: 15'd0 ; */
+/*description: touch active status*/
+#define SENS_TOUCH_PAD_ACTIVE  0x00007FFF
+#define SENS_TOUCH_PAD_ACTIVE_M  ((SENS_TOUCH_PAD_ACTIVE_V)<<(SENS_TOUCH_PAD_ACTIVE_S))
+#define SENS_TOUCH_PAD_ACTIVE_V  0x7FFF
+#define SENS_TOUCH_PAD_ACTIVE_S  0
+
+#define SENS_SAR_TOUCH_STATUS0_REG          (DR_REG_SENS_BASE + 0x00d8)
+/* SENS_TOUCH_SCAN_CURR : RO ;bitpos:[25:22] ;default: 4'd0 ; */
+/*description: */
+#define SENS_TOUCH_SCAN_CURR  0x0000000F
+#define SENS_TOUCH_SCAN_CURR_M  ((SENS_TOUCH_SCAN_CURR_V)<<(SENS_TOUCH_SCAN_CURR_S))
+#define SENS_TOUCH_SCAN_CURR_V  0xF
+#define SENS_TOUCH_SCAN_CURR_S  22
+/* SENS_TOUCH_DENOISE_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: the counter for touch pad 0*/
+#define SENS_TOUCH_DENOISE_DATA  0x003FFFFF
+#define SENS_TOUCH_DENOISE_DATA_M  ((SENS_TOUCH_DENOISE_DATA_V)<<(SENS_TOUCH_DENOISE_DATA_S))
+#define SENS_TOUCH_DENOISE_DATA_V  0x3FFFFF
+#define SENS_TOUCH_DENOISE_DATA_S  0
+
+#define SENS_SAR_TOUCH_STATUS1_REG          (DR_REG_SENS_BASE + 0x00dc)
+/* SENS_TOUCH_PAD1_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: */
+#define SENS_TOUCH_PAD1_DEBOUNCE  0x00000007
+#define SENS_TOUCH_PAD1_DEBOUNCE_M  ((SENS_TOUCH_PAD1_DEBOUNCE_V)<<(SENS_TOUCH_PAD1_DEBOUNCE_S))
+#define SENS_TOUCH_PAD1_DEBOUNCE_V  0x7
+#define SENS_TOUCH_PAD1_DEBOUNCE_S  29
+/* SENS_TOUCH_PAD1_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define SENS_TOUCH_PAD1_DATA  0x003FFFFF
+#define SENS_TOUCH_PAD1_DATA_M  ((SENS_TOUCH_PAD1_DATA_V)<<(SENS_TOUCH_PAD1_DATA_S))
+#define SENS_TOUCH_PAD1_DATA_V  0x3FFFFF
+#define SENS_TOUCH_PAD1_DATA_S  0
+
+#define SENS_SAR_TOUCH_STATUS2_REG          (DR_REG_SENS_BASE + 0x00e0)
+/* SENS_TOUCH_PAD2_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: */
+#define SENS_TOUCH_PAD2_DEBOUNCE  0x00000007
+#define SENS_TOUCH_PAD2_DEBOUNCE_M  ((SENS_TOUCH_PAD2_DEBOUNCE_V)<<(SENS_TOUCH_PAD2_DEBOUNCE_S))
+#define SENS_TOUCH_PAD2_DEBOUNCE_V  0x7
+#define SENS_TOUCH_PAD2_DEBOUNCE_S  29
+/* SENS_TOUCH_PAD2_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define SENS_TOUCH_PAD2_DATA  0x003FFFFF
+#define SENS_TOUCH_PAD2_DATA_M  ((SENS_TOUCH_PAD2_DATA_V)<<(SENS_TOUCH_PAD2_DATA_S))
+#define SENS_TOUCH_PAD2_DATA_V  0x3FFFFF
+#define SENS_TOUCH_PAD2_DATA_S  0
+
+#define SENS_SAR_TOUCH_STATUS3_REG          (DR_REG_SENS_BASE + 0x00e4)
+/* SENS_TOUCH_PAD3_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: */
+#define SENS_TOUCH_PAD3_DEBOUNCE  0x00000007
+#define SENS_TOUCH_PAD3_DEBOUNCE_M  ((SENS_TOUCH_PAD3_DEBOUNCE_V)<<(SENS_TOUCH_PAD3_DEBOUNCE_S))
+#define SENS_TOUCH_PAD3_DEBOUNCE_V  0x7
+#define SENS_TOUCH_PAD3_DEBOUNCE_S  29
+/* SENS_TOUCH_PAD3_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define SENS_TOUCH_PAD3_DATA  0x003FFFFF
+#define SENS_TOUCH_PAD3_DATA_M  ((SENS_TOUCH_PAD3_DATA_V)<<(SENS_TOUCH_PAD3_DATA_S))
+#define SENS_TOUCH_PAD3_DATA_V  0x3FFFFF
+#define SENS_TOUCH_PAD3_DATA_S  0
+
+#define SENS_SAR_TOUCH_STATUS4_REG          (DR_REG_SENS_BASE + 0x00e8)
+/* SENS_TOUCH_PAD4_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: */
+#define SENS_TOUCH_PAD4_DEBOUNCE  0x00000007
+#define SENS_TOUCH_PAD4_DEBOUNCE_M  ((SENS_TOUCH_PAD4_DEBOUNCE_V)<<(SENS_TOUCH_PAD4_DEBOUNCE_S))
+#define SENS_TOUCH_PAD4_DEBOUNCE_V  0x7
+#define SENS_TOUCH_PAD4_DEBOUNCE_S  29
+/* SENS_TOUCH_PAD4_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define SENS_TOUCH_PAD4_DATA  0x003FFFFF
+#define SENS_TOUCH_PAD4_DATA_M  ((SENS_TOUCH_PAD4_DATA_V)<<(SENS_TOUCH_PAD4_DATA_S))
+#define SENS_TOUCH_PAD4_DATA_V  0x3FFFFF
+#define SENS_TOUCH_PAD4_DATA_S  0
+
+#define SENS_SAR_TOUCH_STATUS5_REG          (DR_REG_SENS_BASE + 0x00ec)
+/* SENS_TOUCH_PAD5_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: */
+#define SENS_TOUCH_PAD5_DEBOUNCE  0x00000007
+#define SENS_TOUCH_PAD5_DEBOUNCE_M  ((SENS_TOUCH_PAD5_DEBOUNCE_V)<<(SENS_TOUCH_PAD5_DEBOUNCE_S))
+#define SENS_TOUCH_PAD5_DEBOUNCE_V  0x7
+#define SENS_TOUCH_PAD5_DEBOUNCE_S  29
+/* SENS_TOUCH_PAD5_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define SENS_TOUCH_PAD5_DATA  0x003FFFFF
+#define SENS_TOUCH_PAD5_DATA_M  ((SENS_TOUCH_PAD5_DATA_V)<<(SENS_TOUCH_PAD5_DATA_S))
+#define SENS_TOUCH_PAD5_DATA_V  0x3FFFFF
+#define SENS_TOUCH_PAD5_DATA_S  0
+
+#define SENS_SAR_TOUCH_STATUS6_REG          (DR_REG_SENS_BASE + 0x00f0)
+/* SENS_TOUCH_PAD6_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: */
+#define SENS_TOUCH_PAD6_DEBOUNCE  0x00000007
+#define SENS_TOUCH_PAD6_DEBOUNCE_M  ((SENS_TOUCH_PAD6_DEBOUNCE_V)<<(SENS_TOUCH_PAD6_DEBOUNCE_S))
+#define SENS_TOUCH_PAD6_DEBOUNCE_V  0x7
+#define SENS_TOUCH_PAD6_DEBOUNCE_S  29
+/* SENS_TOUCH_PAD6_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define SENS_TOUCH_PAD6_DATA  0x003FFFFF
+#define SENS_TOUCH_PAD6_DATA_M  ((SENS_TOUCH_PAD6_DATA_V)<<(SENS_TOUCH_PAD6_DATA_S))
+#define SENS_TOUCH_PAD6_DATA_V  0x3FFFFF
+#define SENS_TOUCH_PAD6_DATA_S  0
+
+#define SENS_SAR_TOUCH_STATUS7_REG          (DR_REG_SENS_BASE + 0x00f4)
+/* SENS_TOUCH_PAD7_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: */
+#define SENS_TOUCH_PAD7_DEBOUNCE  0x00000007
+#define SENS_TOUCH_PAD7_DEBOUNCE_M  ((SENS_TOUCH_PAD7_DEBOUNCE_V)<<(SENS_TOUCH_PAD7_DEBOUNCE_S))
+#define SENS_TOUCH_PAD7_DEBOUNCE_V  0x7
+#define SENS_TOUCH_PAD7_DEBOUNCE_S  29
+/* SENS_TOUCH_PAD7_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define SENS_TOUCH_PAD7_DATA  0x003FFFFF
+#define SENS_TOUCH_PAD7_DATA_M  ((SENS_TOUCH_PAD7_DATA_V)<<(SENS_TOUCH_PAD7_DATA_S))
+#define SENS_TOUCH_PAD7_DATA_V  0x3FFFFF
+#define SENS_TOUCH_PAD7_DATA_S  0
+
+#define SENS_SAR_TOUCH_STATUS8_REG          (DR_REG_SENS_BASE + 0x00f8)
+/* SENS_TOUCH_PAD8_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: */
+#define SENS_TOUCH_PAD8_DEBOUNCE  0x00000007
+#define SENS_TOUCH_PAD8_DEBOUNCE_M  ((SENS_TOUCH_PAD8_DEBOUNCE_V)<<(SENS_TOUCH_PAD8_DEBOUNCE_S))
+#define SENS_TOUCH_PAD8_DEBOUNCE_V  0x7
+#define SENS_TOUCH_PAD8_DEBOUNCE_S  29
+/* SENS_TOUCH_PAD8_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define SENS_TOUCH_PAD8_DATA  0x003FFFFF
+#define SENS_TOUCH_PAD8_DATA_M  ((SENS_TOUCH_PAD8_DATA_V)<<(SENS_TOUCH_PAD8_DATA_S))
+#define SENS_TOUCH_PAD8_DATA_V  0x3FFFFF
+#define SENS_TOUCH_PAD8_DATA_S  0
+
+#define SENS_SAR_TOUCH_STATUS9_REG          (DR_REG_SENS_BASE + 0x00fc)
+/* SENS_TOUCH_PAD9_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: */
+#define SENS_TOUCH_PAD9_DEBOUNCE  0x00000007
+#define SENS_TOUCH_PAD9_DEBOUNCE_M  ((SENS_TOUCH_PAD9_DEBOUNCE_V)<<(SENS_TOUCH_PAD9_DEBOUNCE_S))
+#define SENS_TOUCH_PAD9_DEBOUNCE_V  0x7
+#define SENS_TOUCH_PAD9_DEBOUNCE_S  29
+/* SENS_TOUCH_PAD9_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define SENS_TOUCH_PAD9_DATA  0x003FFFFF
+#define SENS_TOUCH_PAD9_DATA_M  ((SENS_TOUCH_PAD9_DATA_V)<<(SENS_TOUCH_PAD9_DATA_S))
+#define SENS_TOUCH_PAD9_DATA_V  0x3FFFFF
+#define SENS_TOUCH_PAD9_DATA_S  0
+
+#define SENS_SAR_TOUCH_STATUS10_REG          (DR_REG_SENS_BASE + 0x0100)
+/* SENS_TOUCH_PAD10_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: */
+#define SENS_TOUCH_PAD10_DEBOUNCE  0x00000007
+#define SENS_TOUCH_PAD10_DEBOUNCE_M  ((SENS_TOUCH_PAD10_DEBOUNCE_V)<<(SENS_TOUCH_PAD10_DEBOUNCE_S))
+#define SENS_TOUCH_PAD10_DEBOUNCE_V  0x7
+#define SENS_TOUCH_PAD10_DEBOUNCE_S  29
+/* SENS_TOUCH_PAD10_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define SENS_TOUCH_PAD10_DATA  0x003FFFFF
+#define SENS_TOUCH_PAD10_DATA_M  ((SENS_TOUCH_PAD10_DATA_V)<<(SENS_TOUCH_PAD10_DATA_S))
+#define SENS_TOUCH_PAD10_DATA_V  0x3FFFFF
+#define SENS_TOUCH_PAD10_DATA_S  0
+
+#define SENS_SAR_TOUCH_STATUS11_REG          (DR_REG_SENS_BASE + 0x0104)
+/* SENS_TOUCH_PAD11_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: */
+#define SENS_TOUCH_PAD11_DEBOUNCE  0x00000007
+#define SENS_TOUCH_PAD11_DEBOUNCE_M  ((SENS_TOUCH_PAD11_DEBOUNCE_V)<<(SENS_TOUCH_PAD11_DEBOUNCE_S))
+#define SENS_TOUCH_PAD11_DEBOUNCE_V  0x7
+#define SENS_TOUCH_PAD11_DEBOUNCE_S  29
+/* SENS_TOUCH_PAD11_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define SENS_TOUCH_PAD11_DATA  0x003FFFFF
+#define SENS_TOUCH_PAD11_DATA_M  ((SENS_TOUCH_PAD11_DATA_V)<<(SENS_TOUCH_PAD11_DATA_S))
+#define SENS_TOUCH_PAD11_DATA_V  0x3FFFFF
+#define SENS_TOUCH_PAD11_DATA_S  0
+
+#define SENS_SAR_TOUCH_STATUS12_REG          (DR_REG_SENS_BASE + 0x0108)
+/* SENS_TOUCH_PAD12_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: */
+#define SENS_TOUCH_PAD12_DEBOUNCE  0x00000007
+#define SENS_TOUCH_PAD12_DEBOUNCE_M  ((SENS_TOUCH_PAD12_DEBOUNCE_V)<<(SENS_TOUCH_PAD12_DEBOUNCE_S))
+#define SENS_TOUCH_PAD12_DEBOUNCE_V  0x7
+#define SENS_TOUCH_PAD12_DEBOUNCE_S  29
+/* SENS_TOUCH_PAD12_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define SENS_TOUCH_PAD12_DATA  0x003FFFFF
+#define SENS_TOUCH_PAD12_DATA_M  ((SENS_TOUCH_PAD12_DATA_V)<<(SENS_TOUCH_PAD12_DATA_S))
+#define SENS_TOUCH_PAD12_DATA_V  0x3FFFFF
+#define SENS_TOUCH_PAD12_DATA_S  0
+
+#define SENS_SAR_TOUCH_STATUS13_REG          (DR_REG_SENS_BASE + 0x010c)
+/* SENS_TOUCH_PAD13_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: */
+#define SENS_TOUCH_PAD13_DEBOUNCE  0x00000007
+#define SENS_TOUCH_PAD13_DEBOUNCE_M  ((SENS_TOUCH_PAD13_DEBOUNCE_V)<<(SENS_TOUCH_PAD13_DEBOUNCE_S))
+#define SENS_TOUCH_PAD13_DEBOUNCE_V  0x7
+#define SENS_TOUCH_PAD13_DEBOUNCE_S  29
+/* SENS_TOUCH_PAD13_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define SENS_TOUCH_PAD13_DATA  0x003FFFFF
+#define SENS_TOUCH_PAD13_DATA_M  ((SENS_TOUCH_PAD13_DATA_V)<<(SENS_TOUCH_PAD13_DATA_S))
+#define SENS_TOUCH_PAD13_DATA_V  0x3FFFFF
+#define SENS_TOUCH_PAD13_DATA_S  0
+
+#define SENS_SAR_TOUCH_STATUS14_REG          (DR_REG_SENS_BASE + 0x0110)
+/* SENS_TOUCH_PAD14_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: */
+#define SENS_TOUCH_PAD14_DEBOUNCE  0x00000007
+#define SENS_TOUCH_PAD14_DEBOUNCE_M  ((SENS_TOUCH_PAD14_DEBOUNCE_V)<<(SENS_TOUCH_PAD14_DEBOUNCE_S))
+#define SENS_TOUCH_PAD14_DEBOUNCE_V  0x7
+#define SENS_TOUCH_PAD14_DEBOUNCE_S  29
+/* SENS_TOUCH_PAD14_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define SENS_TOUCH_PAD14_DATA  0x003FFFFF
+#define SENS_TOUCH_PAD14_DATA_M  ((SENS_TOUCH_PAD14_DATA_V)<<(SENS_TOUCH_PAD14_DATA_S))
+#define SENS_TOUCH_PAD14_DATA_V  0x3FFFFF
+#define SENS_TOUCH_PAD14_DATA_S  0
+
+#define SENS_SAR_TOUCH_STATUS15_REG          (DR_REG_SENS_BASE + 0x0114)
+/* SENS_TOUCH_SLP_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: */
+#define SENS_TOUCH_SLP_DEBOUNCE  0x00000007
+#define SENS_TOUCH_SLP_DEBOUNCE_M  ((SENS_TOUCH_SLP_DEBOUNCE_V)<<(SENS_TOUCH_SLP_DEBOUNCE_S))
+#define SENS_TOUCH_SLP_DEBOUNCE_V  0x7
+#define SENS_TOUCH_SLP_DEBOUNCE_S  29
+/* SENS_TOUCH_SLP_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define SENS_TOUCH_SLP_DATA  0x003FFFFF
+#define SENS_TOUCH_SLP_DATA_M  ((SENS_TOUCH_SLP_DATA_V)<<(SENS_TOUCH_SLP_DATA_S))
+#define SENS_TOUCH_SLP_DATA_V  0x3FFFFF
+#define SENS_TOUCH_SLP_DATA_S  0
+
+#define SENS_SAR_TOUCH_STATUS16_REG          (DR_REG_SENS_BASE + 0x0118)
+/* SENS_TOUCH_SLP_APPROACH_CNT : RO ;bitpos:[31:24] ;default: 8'd0 ; */
+/*description: */
+#define SENS_TOUCH_SLP_APPROACH_CNT  0x000000FF
+#define SENS_TOUCH_SLP_APPROACH_CNT_M  ((SENS_TOUCH_SLP_APPROACH_CNT_V)<<(SENS_TOUCH_SLP_APPROACH_CNT_S))
+#define SENS_TOUCH_SLP_APPROACH_CNT_V  0xFF
+#define SENS_TOUCH_SLP_APPROACH_CNT_S  24
+/* SENS_TOUCH_APPROACH_PAD0_CNT : RO ;bitpos:[23:16] ;default: 8'd0 ; */
+/*description: */
+#define SENS_TOUCH_APPROACH_PAD0_CNT  0x000000FF
+#define SENS_TOUCH_APPROACH_PAD0_CNT_M  ((SENS_TOUCH_APPROACH_PAD0_CNT_V)<<(SENS_TOUCH_APPROACH_PAD0_CNT_S))
+#define SENS_TOUCH_APPROACH_PAD0_CNT_V  0xFF
+#define SENS_TOUCH_APPROACH_PAD0_CNT_S  16
+/* SENS_TOUCH_APPROACH_PAD1_CNT : RO ;bitpos:[15:8] ;default: 8'd0 ; */
+/*description: */
+#define SENS_TOUCH_APPROACH_PAD1_CNT  0x000000FF
+#define SENS_TOUCH_APPROACH_PAD1_CNT_M  ((SENS_TOUCH_APPROACH_PAD1_CNT_V)<<(SENS_TOUCH_APPROACH_PAD1_CNT_S))
+#define SENS_TOUCH_APPROACH_PAD1_CNT_V  0xFF
+#define SENS_TOUCH_APPROACH_PAD1_CNT_S  8
+/* SENS_TOUCH_APPROACH_PAD2_CNT : RO ;bitpos:[7:0] ;default: 8'd0 ; */
+/*description: */
+#define SENS_TOUCH_APPROACH_PAD2_CNT  0x000000FF
+#define SENS_TOUCH_APPROACH_PAD2_CNT_M  ((SENS_TOUCH_APPROACH_PAD2_CNT_V)<<(SENS_TOUCH_APPROACH_PAD2_CNT_S))
+#define SENS_TOUCH_APPROACH_PAD2_CNT_V  0xFF
+#define SENS_TOUCH_APPROACH_PAD2_CNT_S  0
+
+#define SENS_SAR_DAC_CTRL1_REG          (DR_REG_SENS_BASE + 0x011c)
+/* SENS_DAC_CLK_INV : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: 1: invert PDAC_CLK*/
+#define SENS_DAC_CLK_INV  (BIT(25))
+#define SENS_DAC_CLK_INV_M  (BIT(25))
+#define SENS_DAC_CLK_INV_V  0x1
+#define SENS_DAC_CLK_INV_S  25
+/* SENS_DAC_CLK_FORCE_HIGH : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: 1: force PDAC_CLK to high*/
+#define SENS_DAC_CLK_FORCE_HIGH  (BIT(24))
+#define SENS_DAC_CLK_FORCE_HIGH_M  (BIT(24))
+#define SENS_DAC_CLK_FORCE_HIGH_V  0x1
+#define SENS_DAC_CLK_FORCE_HIGH_S  24
+/* SENS_DAC_CLK_FORCE_LOW : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: 1: force PDAC_CLK to low*/
+#define SENS_DAC_CLK_FORCE_LOW  (BIT(23))
+#define SENS_DAC_CLK_FORCE_LOW_M  (BIT(23))
+#define SENS_DAC_CLK_FORCE_LOW_V  0x1
+#define SENS_DAC_CLK_FORCE_LOW_S  23
+/* SENS_DAC_DIG_FORCE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: 1: DAC1 & DAC2 use DMA*/
+#define SENS_DAC_DIG_FORCE  (BIT(22))
+#define SENS_DAC_DIG_FORCE_M  (BIT(22))
+#define SENS_DAC_DIG_FORCE_V  0x1
+#define SENS_DAC_DIG_FORCE_S  22
+/* SENS_DEBUG_BIT_SEL : R/W ;bitpos:[21:17] ;default: 5'b0 ; */
+/*description: */
+#define SENS_DEBUG_BIT_SEL  0x0000001F
+#define SENS_DEBUG_BIT_SEL_M  ((SENS_DEBUG_BIT_SEL_V)<<(SENS_DEBUG_BIT_SEL_S))
+#define SENS_DEBUG_BIT_SEL_V  0x1F
+#define SENS_DEBUG_BIT_SEL_S  17
+/* SENS_SW_TONE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: 1: enable CW generator*/
+#define SENS_SW_TONE_EN  (BIT(16))
+#define SENS_SW_TONE_EN_M  (BIT(16))
+#define SENS_SW_TONE_EN_V  0x1
+#define SENS_SW_TONE_EN_S  16
+/* SENS_SW_FSTEP : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: frequency step for CW generator*/
+#define SENS_SW_FSTEP  0x0000FFFF
+#define SENS_SW_FSTEP_M  ((SENS_SW_FSTEP_V)<<(SENS_SW_FSTEP_S))
+#define SENS_SW_FSTEP_V  0xFFFF
+#define SENS_SW_FSTEP_S  0
+
+#define SENS_SAR_DAC_CTRL2_REG          (DR_REG_SENS_BASE + 0x0120)
+/* SENS_DAC_CW_EN2 : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: 1: to select CW generator as source to PDAC2_DAC[7:0]*/
+#define SENS_DAC_CW_EN2  (BIT(25))
+#define SENS_DAC_CW_EN2_M  (BIT(25))
+#define SENS_DAC_CW_EN2_V  0x1
+#define SENS_DAC_CW_EN2_S  25
+/* SENS_DAC_CW_EN1 : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: 1: to select CW generator as source to PDAC1_DAC[7:0]*/
+#define SENS_DAC_CW_EN1  (BIT(24))
+#define SENS_DAC_CW_EN1_M  (BIT(24))
+#define SENS_DAC_CW_EN1_V  0x1
+#define SENS_DAC_CW_EN1_S  24
+/* SENS_DAC_INV2 : R/W ;bitpos:[23:22] ;default: 2'b0 ; */
+/*description: 00: do not invert any bits*/
+#define SENS_DAC_INV2  0x00000003
+#define SENS_DAC_INV2_M  ((SENS_DAC_INV2_V)<<(SENS_DAC_INV2_S))
+#define SENS_DAC_INV2_V  0x3
+#define SENS_DAC_INV2_S  22
+/* SENS_DAC_INV1 : R/W ;bitpos:[21:20] ;default: 2'b0 ; */
+/*description: 00: do not invert any bits*/
+#define SENS_DAC_INV1  0x00000003
+#define SENS_DAC_INV1_M  ((SENS_DAC_INV1_V)<<(SENS_DAC_INV1_S))
+#define SENS_DAC_INV1_V  0x3
+#define SENS_DAC_INV1_S  20
+/* SENS_DAC_SCALE2 : R/W ;bitpos:[19:18] ;default: 2'b0 ; */
+/*description: 00: no scale*/
+#define SENS_DAC_SCALE2  0x00000003
+#define SENS_DAC_SCALE2_M  ((SENS_DAC_SCALE2_V)<<(SENS_DAC_SCALE2_S))
+#define SENS_DAC_SCALE2_V  0x3
+#define SENS_DAC_SCALE2_S  18
+/* SENS_DAC_SCALE1 : R/W ;bitpos:[17:16] ;default: 2'b0 ; */
+/*description: 00: no scale*/
+#define SENS_DAC_SCALE1  0x00000003
+#define SENS_DAC_SCALE1_M  ((SENS_DAC_SCALE1_V)<<(SENS_DAC_SCALE1_S))
+#define SENS_DAC_SCALE1_V  0x3
+#define SENS_DAC_SCALE1_S  16
+/* SENS_DAC_DC2 : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
+/*description: DC offset for DAC2 CW generator*/
+#define SENS_DAC_DC2  0x000000FF
+#define SENS_DAC_DC2_M  ((SENS_DAC_DC2_V)<<(SENS_DAC_DC2_S))
+#define SENS_DAC_DC2_V  0xFF
+#define SENS_DAC_DC2_S  8
+/* SENS_DAC_DC1 : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: DC offset for DAC1 CW generator*/
+#define SENS_DAC_DC1  0x000000FF
+#define SENS_DAC_DC1_M  ((SENS_DAC_DC1_V)<<(SENS_DAC_DC1_S))
+#define SENS_DAC_DC1_V  0xFF
+#define SENS_DAC_DC1_S  0
+
+#define SENS_SAR_COCPU_STATE_REG          (DR_REG_SENS_BASE + 0x0124)
+/* SENS_COCPU_EBREAK : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: check cocpu whether in ebreak*/
+#define SENS_COCPU_EBREAK  (BIT(30))
+#define SENS_COCPU_EBREAK_M  (BIT(30))
+#define SENS_COCPU_EBREAK_V  0x1
+#define SENS_COCPU_EBREAK_S  30
+/* SENS_COCPU_TRAP : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: check cocpu whether in trap state*/
+#define SENS_COCPU_TRAP  (BIT(29))
+#define SENS_COCPU_TRAP_M  (BIT(29))
+#define SENS_COCPU_TRAP_V  0x1
+#define SENS_COCPU_TRAP_S  29
+/* SENS_COCPU_EOI : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: check cocpu whether in interrupt state*/
+#define SENS_COCPU_EOI  (BIT(28))
+#define SENS_COCPU_EOI_M  (BIT(28))
+#define SENS_COCPU_EOI_V  0x1
+#define SENS_COCPU_EOI_S  28
+/* SENS_COCPU_RESET_N : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: check cocpu whether in reset state*/
+#define SENS_COCPU_RESET_N  (BIT(27))
+#define SENS_COCPU_RESET_N_M  (BIT(27))
+#define SENS_COCPU_RESET_N_V  0x1
+#define SENS_COCPU_RESET_N_S  27
+/* SENS_COCPU_CLK_EN_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: check cocpu whether clk on*/
+#define SENS_COCPU_CLK_EN_ST  (BIT(26))
+#define SENS_COCPU_CLK_EN_ST_M  (BIT(26))
+#define SENS_COCPU_CLK_EN_ST_V  0x1
+#define SENS_COCPU_CLK_EN_ST_S  26
+/* SENS_COCPU_DBG_TRIGGER : WO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: trigger cocpu debug registers*/
+#define SENS_COCPU_DBG_TRIGGER  (BIT(25))
+#define SENS_COCPU_DBG_TRIGGER_M  (BIT(25))
+#define SENS_COCPU_DBG_TRIGGER_V  0x1
+#define SENS_COCPU_DBG_TRIGGER_S  25
+
+#define SENS_SAR_COCPU_INT_RAW_REG          (DR_REG_SENS_BASE + 0x0128)
+/* SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW  (BIT(11))
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_M  (BIT(11))
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_V  0x1
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_S  11
+/* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW  (BIT(10))
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M  (BIT(10))
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V  0x1
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S  10
+/* SENS_COCPU_TOUCH_TIMEOUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW  (BIT(9))
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_M  (BIT(9))
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_V  0x1
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_S  9
+/* SENS_COCPU_SWD_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: int from super watch dog*/
+#define SENS_COCPU_SWD_INT_RAW  (BIT(8))
+#define SENS_COCPU_SWD_INT_RAW_M  (BIT(8))
+#define SENS_COCPU_SWD_INT_RAW_V  0x1
+#define SENS_COCPU_SWD_INT_RAW_S  8
+/* SENS_COCPU_SW_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: int from software*/
+#define SENS_COCPU_SW_INT_RAW  (BIT(7))
+#define SENS_COCPU_SW_INT_RAW_M  (BIT(7))
+#define SENS_COCPU_SW_INT_RAW_V  0x1
+#define SENS_COCPU_SW_INT_RAW_S  7
+/* SENS_COCPU_START_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: int from start*/
+#define SENS_COCPU_START_INT_RAW  (BIT(6))
+#define SENS_COCPU_START_INT_RAW_M  (BIT(6))
+#define SENS_COCPU_START_INT_RAW_V  0x1
+#define SENS_COCPU_START_INT_RAW_S  6
+/* SENS_COCPU_TSENS_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: int from tsens*/
+#define SENS_COCPU_TSENS_INT_RAW  (BIT(5))
+#define SENS_COCPU_TSENS_INT_RAW_M  (BIT(5))
+#define SENS_COCPU_TSENS_INT_RAW_V  0x1
+#define SENS_COCPU_TSENS_INT_RAW_S  5
+/* SENS_COCPU_SENS2_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: int from saradc2*/
+#define SENS_COCPU_SENS2_INT_RAW  (BIT(4))
+#define SENS_COCPU_SENS2_INT_RAW_M  (BIT(4))
+#define SENS_COCPU_SENS2_INT_RAW_V  0x1
+#define SENS_COCPU_SENS2_INT_RAW_S  4
+/* SENS_COCPU_SENS1_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: int from saradc1*/
+#define SENS_COCPU_SENS1_INT_RAW  (BIT(3))
+#define SENS_COCPU_SENS1_INT_RAW_M  (BIT(3))
+#define SENS_COCPU_SENS1_INT_RAW_V  0x1
+#define SENS_COCPU_SENS1_INT_RAW_S  3
+/* SENS_COCPU_TOUCH_ACTIVE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: int from touch active*/
+#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW  (BIT(2))
+#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_M  (BIT(2))
+#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_V  0x1
+#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_S  2
+/* SENS_COCPU_TOUCH_INACTIVE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: int from touch inactive*/
+#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW  (BIT(1))
+#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_M  (BIT(1))
+#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_V  0x1
+#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_S  1
+/* SENS_COCPU_TOUCH_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: int from touch done*/
+#define SENS_COCPU_TOUCH_DONE_INT_RAW  (BIT(0))
+#define SENS_COCPU_TOUCH_DONE_INT_RAW_M  (BIT(0))
+#define SENS_COCPU_TOUCH_DONE_INT_RAW_V  0x1
+#define SENS_COCPU_TOUCH_DONE_INT_RAW_S  0
+
+#define SENS_SAR_COCPU_INT_ENA_REG          (DR_REG_SENS_BASE + 0x012c)
+/* SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA  (BIT(11))
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_M  (BIT(11))
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_V  0x1
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_S  11
+/* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA  (BIT(10))
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M  (BIT(10))
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V  0x1
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S  10
+/* SENS_COCPU_TOUCH_TIMEOUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA  (BIT(9))
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_M  (BIT(9))
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_V  0x1
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_S  9
+/* SENS_COCPU_SWD_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_SWD_INT_ENA  (BIT(8))
+#define SENS_COCPU_SWD_INT_ENA_M  (BIT(8))
+#define SENS_COCPU_SWD_INT_ENA_V  0x1
+#define SENS_COCPU_SWD_INT_ENA_S  8
+/* SENS_COCPU_SW_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: cocpu int enable*/
+#define SENS_COCPU_SW_INT_ENA  (BIT(7))
+#define SENS_COCPU_SW_INT_ENA_M  (BIT(7))
+#define SENS_COCPU_SW_INT_ENA_V  0x1
+#define SENS_COCPU_SW_INT_ENA_S  7
+/* SENS_COCPU_START_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_START_INT_ENA  (BIT(6))
+#define SENS_COCPU_START_INT_ENA_M  (BIT(6))
+#define SENS_COCPU_START_INT_ENA_V  0x1
+#define SENS_COCPU_START_INT_ENA_S  6
+/* SENS_COCPU_TSENS_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TSENS_INT_ENA  (BIT(5))
+#define SENS_COCPU_TSENS_INT_ENA_M  (BIT(5))
+#define SENS_COCPU_TSENS_INT_ENA_V  0x1
+#define SENS_COCPU_TSENS_INT_ENA_S  5
+/* SENS_COCPU_SENS2_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_SENS2_INT_ENA  (BIT(4))
+#define SENS_COCPU_SENS2_INT_ENA_M  (BIT(4))
+#define SENS_COCPU_SENS2_INT_ENA_V  0x1
+#define SENS_COCPU_SENS2_INT_ENA_S  4
+/* SENS_COCPU_SENS1_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_SENS1_INT_ENA  (BIT(3))
+#define SENS_COCPU_SENS1_INT_ENA_M  (BIT(3))
+#define SENS_COCPU_SENS1_INT_ENA_V  0x1
+#define SENS_COCPU_SENS1_INT_ENA_S  3
+/* SENS_COCPU_TOUCH_ACTIVE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA  (BIT(2))
+#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_M  (BIT(2))
+#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_V  0x1
+#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_S  2
+/* SENS_COCPU_TOUCH_INACTIVE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA  (BIT(1))
+#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_M  (BIT(1))
+#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_V  0x1
+#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_S  1
+/* SENS_COCPU_TOUCH_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_DONE_INT_ENA  (BIT(0))
+#define SENS_COCPU_TOUCH_DONE_INT_ENA_M  (BIT(0))
+#define SENS_COCPU_TOUCH_DONE_INT_ENA_V  0x1
+#define SENS_COCPU_TOUCH_DONE_INT_ENA_S  0
+
+#define SENS_SAR_COCPU_INT_ST_REG          (DR_REG_SENS_BASE + 0x0130)
+/* SENS_COCPU_TOUCH_SCAN_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST  (BIT(11))
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_M  (BIT(11))
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_V  0x1
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_S  11
+/* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST  (BIT(10))
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_M  (BIT(10))
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_V  0x1
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_S  10
+/* SENS_COCPU_TOUCH_TIMEOUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST  (BIT(9))
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_M  (BIT(9))
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_V  0x1
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_S  9
+/* SENS_COCPU_SWD_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_SWD_INT_ST  (BIT(8))
+#define SENS_COCPU_SWD_INT_ST_M  (BIT(8))
+#define SENS_COCPU_SWD_INT_ST_V  0x1
+#define SENS_COCPU_SWD_INT_ST_S  8
+/* SENS_COCPU_SW_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: cocpu int status*/
+#define SENS_COCPU_SW_INT_ST  (BIT(7))
+#define SENS_COCPU_SW_INT_ST_M  (BIT(7))
+#define SENS_COCPU_SW_INT_ST_V  0x1
+#define SENS_COCPU_SW_INT_ST_S  7
+/* SENS_COCPU_START_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_START_INT_ST  (BIT(6))
+#define SENS_COCPU_START_INT_ST_M  (BIT(6))
+#define SENS_COCPU_START_INT_ST_V  0x1
+#define SENS_COCPU_START_INT_ST_S  6
+/* SENS_COCPU_TSENS_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TSENS_INT_ST  (BIT(5))
+#define SENS_COCPU_TSENS_INT_ST_M  (BIT(5))
+#define SENS_COCPU_TSENS_INT_ST_V  0x1
+#define SENS_COCPU_TSENS_INT_ST_S  5
+/* SENS_COCPU_SENS2_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_SENS2_INT_ST  (BIT(4))
+#define SENS_COCPU_SENS2_INT_ST_M  (BIT(4))
+#define SENS_COCPU_SENS2_INT_ST_V  0x1
+#define SENS_COCPU_SENS2_INT_ST_S  4
+/* SENS_COCPU_SENS1_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_SENS1_INT_ST  (BIT(3))
+#define SENS_COCPU_SENS1_INT_ST_M  (BIT(3))
+#define SENS_COCPU_SENS1_INT_ST_V  0x1
+#define SENS_COCPU_SENS1_INT_ST_S  3
+/* SENS_COCPU_TOUCH_ACTIVE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_ACTIVE_INT_ST  (BIT(2))
+#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_M  (BIT(2))
+#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_V  0x1
+#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_S  2
+/* SENS_COCPU_TOUCH_INACTIVE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_INACTIVE_INT_ST  (BIT(1))
+#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_M  (BIT(1))
+#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_V  0x1
+#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_S  1
+/* SENS_COCPU_TOUCH_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_DONE_INT_ST  (BIT(0))
+#define SENS_COCPU_TOUCH_DONE_INT_ST_M  (BIT(0))
+#define SENS_COCPU_TOUCH_DONE_INT_ST_V  0x1
+#define SENS_COCPU_TOUCH_DONE_INT_ST_S  0
+
+#define SENS_SAR_COCPU_INT_CLR_REG          (DR_REG_SENS_BASE + 0x0134)
+/* SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR  (BIT(11))
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_M  (BIT(11))
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_V  0x1
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_S  11
+/* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR  (BIT(10))
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M  (BIT(10))
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V  0x1
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S  10
+/* SENS_COCPU_TOUCH_TIMEOUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR  (BIT(9))
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_M  (BIT(9))
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_V  0x1
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_S  9
+/* SENS_COCPU_SWD_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_SWD_INT_CLR  (BIT(8))
+#define SENS_COCPU_SWD_INT_CLR_M  (BIT(8))
+#define SENS_COCPU_SWD_INT_CLR_V  0x1
+#define SENS_COCPU_SWD_INT_CLR_S  8
+/* SENS_COCPU_SW_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: cocpu int clear*/
+#define SENS_COCPU_SW_INT_CLR  (BIT(7))
+#define SENS_COCPU_SW_INT_CLR_M  (BIT(7))
+#define SENS_COCPU_SW_INT_CLR_V  0x1
+#define SENS_COCPU_SW_INT_CLR_S  7
+/* SENS_COCPU_START_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_START_INT_CLR  (BIT(6))
+#define SENS_COCPU_START_INT_CLR_M  (BIT(6))
+#define SENS_COCPU_START_INT_CLR_V  0x1
+#define SENS_COCPU_START_INT_CLR_S  6
+/* SENS_COCPU_TSENS_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TSENS_INT_CLR  (BIT(5))
+#define SENS_COCPU_TSENS_INT_CLR_M  (BIT(5))
+#define SENS_COCPU_TSENS_INT_CLR_V  0x1
+#define SENS_COCPU_TSENS_INT_CLR_S  5
+/* SENS_COCPU_SENS2_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_SENS2_INT_CLR  (BIT(4))
+#define SENS_COCPU_SENS2_INT_CLR_M  (BIT(4))
+#define SENS_COCPU_SENS2_INT_CLR_V  0x1
+#define SENS_COCPU_SENS2_INT_CLR_S  4
+/* SENS_COCPU_SENS1_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_SENS1_INT_CLR  (BIT(3))
+#define SENS_COCPU_SENS1_INT_CLR_M  (BIT(3))
+#define SENS_COCPU_SENS1_INT_CLR_V  0x1
+#define SENS_COCPU_SENS1_INT_CLR_S  3
+/* SENS_COCPU_TOUCH_ACTIVE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR  (BIT(2))
+#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_M  (BIT(2))
+#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_V  0x1
+#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_S  2
+/* SENS_COCPU_TOUCH_INACTIVE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR  (BIT(1))
+#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_M  (BIT(1))
+#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_V  0x1
+#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_S  1
+/* SENS_COCPU_TOUCH_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_DONE_INT_CLR  (BIT(0))
+#define SENS_COCPU_TOUCH_DONE_INT_CLR_M  (BIT(0))
+#define SENS_COCPU_TOUCH_DONE_INT_CLR_V  0x1
+#define SENS_COCPU_TOUCH_DONE_INT_CLR_S  0
+
+#define SENS_SAR_COCPU_DEBUG_REG          (DR_REG_SENS_BASE + 0x0138)
+/* SENS_COCPU_MEM_ADDR : RO ;bitpos:[31:19] ;default: 13'd0 ; */
+/*description: cocpu mem address output*/
+#define SENS_COCPU_MEM_ADDR  0x00001FFF
+#define SENS_COCPU_MEM_ADDR_M  ((SENS_COCPU_MEM_ADDR_V)<<(SENS_COCPU_MEM_ADDR_S))
+#define SENS_COCPU_MEM_ADDR_V  0x1FFF
+#define SENS_COCPU_MEM_ADDR_S  19
+/* SENS_COCPU_MEM_WEN : RO ;bitpos:[18:15] ;default: 4'd0 ; */
+/*description: cocpu mem write enable output*/
+#define SENS_COCPU_MEM_WEN  0x0000000F
+#define SENS_COCPU_MEM_WEN_M  ((SENS_COCPU_MEM_WEN_V)<<(SENS_COCPU_MEM_WEN_S))
+#define SENS_COCPU_MEM_WEN_V  0xF
+#define SENS_COCPU_MEM_WEN_S  15
+/* SENS_COCPU_MEM_RDY : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: cocpu mem ready input*/
+#define SENS_COCPU_MEM_RDY  (BIT(14))
+#define SENS_COCPU_MEM_RDY_M  (BIT(14))
+#define SENS_COCPU_MEM_RDY_V  0x1
+#define SENS_COCPU_MEM_RDY_S  14
+/* SENS_COCPU_MEM_VLD : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: cocpu mem valid output*/
+#define SENS_COCPU_MEM_VLD  (BIT(13))
+#define SENS_COCPU_MEM_VLD_M  (BIT(13))
+#define SENS_COCPU_MEM_VLD_V  0x1
+#define SENS_COCPU_MEM_VLD_S  13
+/* SENS_COCPU_PC : RO ;bitpos:[12:0] ;default: 13'd0 ; */
+/*description: cocpu Program counter*/
+#define SENS_COCPU_PC  0x00001FFF
+#define SENS_COCPU_PC_M  ((SENS_COCPU_PC_V)<<(SENS_COCPU_PC_S))
+#define SENS_COCPU_PC_V  0x1FFF
+#define SENS_COCPU_PC_S  0
+
+#define SENS_SAR_HALL_CTRL_REG          (DR_REG_SENS_BASE + 0x013c)
+/* SENS_HALL_PHASE_FORCE : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: 1: HALL PHASE is controlled by SW  0: HALL PHASE is controlled
+ by FSM in ULP-coprocessor*/
+#define SENS_HALL_PHASE_FORCE  (BIT(31))
+#define SENS_HALL_PHASE_FORCE_M  (BIT(31))
+#define SENS_HALL_PHASE_FORCE_V  0x1
+#define SENS_HALL_PHASE_FORCE_S  31
+/* SENS_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Reverse phase of hall sensor*/
+#define SENS_HALL_PHASE  (BIT(30))
+#define SENS_HALL_PHASE_M  (BIT(30))
+#define SENS_HALL_PHASE_V  0x1
+#define SENS_HALL_PHASE_S  30
+/* SENS_XPD_HALL_FORCE : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by
+ FSM in ULP-coprocessor*/
+#define SENS_XPD_HALL_FORCE  (BIT(29))
+#define SENS_XPD_HALL_FORCE_M  (BIT(29))
+#define SENS_XPD_HALL_FORCE_V  0x1
+#define SENS_XPD_HALL_FORCE_S  29
+/* SENS_XPD_HALL : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Power on hall sensor and connect to VP and VN*/
+#define SENS_XPD_HALL  (BIT(28))
+#define SENS_XPD_HALL_M  (BIT(28))
+#define SENS_XPD_HALL_V  0x1
+#define SENS_XPD_HALL_S  28
+
+#define SENS_SAR_NOUSE_REG          (DR_REG_SENS_BASE + 0x0140)
+/* SENS_SAR_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SENS_SAR_NOUSE  0xFFFFFFFF
+#define SENS_SAR_NOUSE_M  ((SENS_SAR_NOUSE_V)<<(SENS_SAR_NOUSE_S))
+#define SENS_SAR_NOUSE_V  0xFFFFFFFF
+#define SENS_SAR_NOUSE_S  0
+
+#define SENS_SAR_PERI_CLK_GATE_CONF_REG          (DR_REG_SENS_BASE + 0x0144)
+/* SENS_IOMUX_CLK_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: */
+#define SENS_IOMUX_CLK_EN  (BIT(31))
+#define SENS_IOMUX_CLK_EN_M  (BIT(31))
+#define SENS_IOMUX_CLK_EN_V  0x1
+#define SENS_IOMUX_CLK_EN_S  31
+/* SENS_CLK_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define SENS_CLK_EN  (BIT(30))
+#define SENS_CLK_EN_M  (BIT(30))
+#define SENS_CLK_EN_V  0x1
+#define SENS_CLK_EN_S  30
+/* SENS_TSENS_CLK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define SENS_TSENS_CLK_EN  (BIT(29))
+#define SENS_TSENS_CLK_EN_M  (BIT(29))
+#define SENS_TSENS_CLK_EN_V  0x1
+#define SENS_TSENS_CLK_EN_S  29
+/* SENS_RTC_I2C_CLK_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define SENS_RTC_I2C_CLK_EN  (BIT(27))
+#define SENS_RTC_I2C_CLK_EN_M  (BIT(27))
+#define SENS_RTC_I2C_CLK_EN_V  0x1
+#define SENS_RTC_I2C_CLK_EN_S  27
+/* SENS_DAC_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SENS_DAC_CLK_EN  (BIT(26))
+#define SENS_DAC_CLK_EN_M  (BIT(26))
+#define SENS_DAC_CLK_EN_V  0x1
+#define SENS_DAC_CLK_EN_S  26
+
+#define SENS_SAR_PERI_RESET_CONF_REG          (DR_REG_SENS_BASE + 0x0148)
+/* SENS_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define SENS_RESET  (BIT(30))
+#define SENS_RESET_M  (BIT(30))
+#define SENS_RESET_V  0x1
+#define SENS_RESET_S  30
+/* SENS_TSENS_RESET : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define SENS_TSENS_RESET  (BIT(29))
+#define SENS_TSENS_RESET_M  (BIT(29))
+#define SENS_TSENS_RESET_V  0x1
+#define SENS_TSENS_RESET_S  29
+#define SENS_FORCE_XPD_SAR_SW_M (BIT1)
+#define SENS_FORCE_XPD_SAR_FSM 0 // Use FSM to control power down
+#define SENS_FORCE_XPD_SAR_PD  2 // Force power down
+#define SENS_FORCE_XPD_SAR_PU  3 // Force power up
+/* SENS_RTC_I2C_RESET : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define SENS_RTC_I2C_RESET  (BIT(27))
+#define SENS_RTC_I2C_RESET_M  (BIT(27))
+#define SENS_RTC_I2C_RESET_V  0x1
+#define SENS_RTC_I2C_RESET_S  27
+/* SENS_DAC_RESET : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SENS_DAC_RESET  (BIT(26))
+#define SENS_DAC_RESET_M  (BIT(26))
+#define SENS_DAC_RESET_V  0x1
+#define SENS_DAC_RESET_S  26
+/* SENS_COCPU_RESET : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_RESET  (BIT(25))
+#define SENS_COCPU_RESET_M  (BIT(25))
+#define SENS_COCPU_RESET_V  0x1
+#define SENS_COCPU_RESET_S  25
+
+#define SENS_SAR_COCPU_INT_ENA_W1TS_REG          (DR_REG_SENS_BASE + 0x014c)
+/* SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS  (BIT(11))
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_M  (BIT(11))
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_V  0x1
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_S  11
+/* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS  (BIT(10))
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_M  (BIT(10))
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V  0x1
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S  10
+/* SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS  (BIT(9))
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_M  (BIT(9))
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_V  0x1
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_S  9
+/* SENS_COCPU_SWD_INT_ENA_W1TS : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_SWD_INT_ENA_W1TS  (BIT(8))
+#define SENS_COCPU_SWD_INT_ENA_W1TS_M  (BIT(8))
+#define SENS_COCPU_SWD_INT_ENA_W1TS_V  0x1
+#define SENS_COCPU_SWD_INT_ENA_W1TS_S  8
+/* SENS_COCPU_SW_INT_ENA_W1TS : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_SW_INT_ENA_W1TS  (BIT(7))
+#define SENS_COCPU_SW_INT_ENA_W1TS_M  (BIT(7))
+#define SENS_COCPU_SW_INT_ENA_W1TS_V  0x1
+#define SENS_COCPU_SW_INT_ENA_W1TS_S  7
+/* SENS_COCPU_START_INT_ENA_W1TS : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_START_INT_ENA_W1TS  (BIT(6))
+#define SENS_COCPU_START_INT_ENA_W1TS_M  (BIT(6))
+#define SENS_COCPU_START_INT_ENA_W1TS_V  0x1
+#define SENS_COCPU_START_INT_ENA_W1TS_S  6
+/* SENS_COCPU_TSENS_INT_ENA_W1TS : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TSENS_INT_ENA_W1TS  (BIT(5))
+#define SENS_COCPU_TSENS_INT_ENA_W1TS_M  (BIT(5))
+#define SENS_COCPU_TSENS_INT_ENA_W1TS_V  0x1
+#define SENS_COCPU_TSENS_INT_ENA_W1TS_S  5
+/* SENS_COCPU_SENS2_INT_ENA_W1TS : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_SENS2_INT_ENA_W1TS  (BIT(4))
+#define SENS_COCPU_SENS2_INT_ENA_W1TS_M  (BIT(4))
+#define SENS_COCPU_SENS2_INT_ENA_W1TS_V  0x1
+#define SENS_COCPU_SENS2_INT_ENA_W1TS_S  4
+/* SENS_COCPU_SENS1_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_SENS1_INT_ENA_W1TS  (BIT(3))
+#define SENS_COCPU_SENS1_INT_ENA_W1TS_M  (BIT(3))
+#define SENS_COCPU_SENS1_INT_ENA_W1TS_V  0x1
+#define SENS_COCPU_SENS1_INT_ENA_W1TS_S  3
+/* SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS  (BIT(2))
+#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_M  (BIT(2))
+#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_V  0x1
+#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_S  2
+/* SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS  (BIT(1))
+#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_M  (BIT(1))
+#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_V  0x1
+#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_S  1
+/* SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS  (BIT(0))
+#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_M  (BIT(0))
+#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_V  0x1
+#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_S  0
+
+#define SENS_SAR_COCPU_INT_ENA_W1TC_REG          (DR_REG_SENS_BASE + 0x0150)
+/* SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC  (BIT(11))
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_M  (BIT(11))
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_V  0x1
+#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_S  11
+/* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC  (BIT(10))
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_M  (BIT(10))
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V  0x1
+#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S  10
+/* SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC  (BIT(9))
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_M  (BIT(9))
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_V  0x1
+#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_S  9
+/* SENS_COCPU_SWD_INT_ENA_W1TC : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_SWD_INT_ENA_W1TC  (BIT(8))
+#define SENS_COCPU_SWD_INT_ENA_W1TC_M  (BIT(8))
+#define SENS_COCPU_SWD_INT_ENA_W1TC_V  0x1
+#define SENS_COCPU_SWD_INT_ENA_W1TC_S  8
+/* SENS_COCPU_SW_INT_ENA_W1TC : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_SW_INT_ENA_W1TC  (BIT(7))
+#define SENS_COCPU_SW_INT_ENA_W1TC_M  (BIT(7))
+#define SENS_COCPU_SW_INT_ENA_W1TC_V  0x1
+#define SENS_COCPU_SW_INT_ENA_W1TC_S  7
+/* SENS_COCPU_START_INT_ENA_W1TC : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_START_INT_ENA_W1TC  (BIT(6))
+#define SENS_COCPU_START_INT_ENA_W1TC_M  (BIT(6))
+#define SENS_COCPU_START_INT_ENA_W1TC_V  0x1
+#define SENS_COCPU_START_INT_ENA_W1TC_S  6
+/* SENS_COCPU_TSENS_INT_ENA_W1TC : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TSENS_INT_ENA_W1TC  (BIT(5))
+#define SENS_COCPU_TSENS_INT_ENA_W1TC_M  (BIT(5))
+#define SENS_COCPU_TSENS_INT_ENA_W1TC_V  0x1
+#define SENS_COCPU_TSENS_INT_ENA_W1TC_S  5
+/* SENS_COCPU_SENS2_INT_ENA_W1TC : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_SENS2_INT_ENA_W1TC  (BIT(4))
+#define SENS_COCPU_SENS2_INT_ENA_W1TC_M  (BIT(4))
+#define SENS_COCPU_SENS2_INT_ENA_W1TC_V  0x1
+#define SENS_COCPU_SENS2_INT_ENA_W1TC_S  4
+/* SENS_COCPU_SENS1_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_SENS1_INT_ENA_W1TC  (BIT(3))
+#define SENS_COCPU_SENS1_INT_ENA_W1TC_M  (BIT(3))
+#define SENS_COCPU_SENS1_INT_ENA_W1TC_V  0x1
+#define SENS_COCPU_SENS1_INT_ENA_W1TC_S  3
+/* SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC  (BIT(2))
+#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_M  (BIT(2))
+#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_V  0x1
+#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_S  2
+/* SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC  (BIT(1))
+#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_M  (BIT(1))
+#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_V  0x1
+#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_S  1
+/* SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC  (BIT(0))
+#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_M  (BIT(0))
+#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_V  0x1
+#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_S  0
+
+#define SENS_SARDATE_REG          (DR_REG_SENS_BASE + 0x0154)
+/* SENS_SAR_DATE : R/W ;bitpos:[27:0] ;default: 28'h1909160 ; */
+/*description: */
+#define SENS_SAR_DATE  0x0FFFFFFF
+#define SENS_SAR_DATE_M  ((SENS_SAR_DATE_V)<<(SENS_SAR_DATE_S))
+#define SENS_SAR_DATE_V  0xFFFFFFF
+#define SENS_SAR_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SENS_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/sens_struct.h b/components/soc/esp32c3/include/soc/sens_struct.h
new file mode 100644
index 0000000000..4a084b9111
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/sens_struct.h
@@ -0,0 +1,504 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SENS_STRUCT_H_
+#define _SOC_SENS_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t sar1_clk_div:    8;                                   /*clock divider*/
+            uint32_t reserved8:      10;
+            uint32_t sar1_clk_gated:  1;
+            uint32_t sar1_sample_num: 8;
+            uint32_t reserved27:      1;
+            uint32_t sar1_data_inv:   1;                                   /*Invert SAR ADC1 data*/
+            uint32_t sar1_int_en:     1;                                   /*enable saradc1 to send out interrupt*/
+            uint32_t reserved30:      2;
+        };
+        uint32_t val;
+    } sar_reader1_ctrl;
+    uint32_t sar_reader1_status;                                           /**/
+    union {
+        struct {
+            uint32_t reserved0:              24;
+            uint32_t force_xpd_amp:           2;
+            uint32_t amp_rst_fb_force:        2;
+            uint32_t amp_short_ref_force:     2;
+            uint32_t amp_short_ref_gnd_force: 2;
+        };
+        uint32_t val;
+    } sar_meas1_ctrl1;
+    union {
+        struct {
+            uint32_t meas1_data_sar:   16;                                 /*SAR ADC1 data*/
+            uint32_t meas1_done_sar:    1;                                 /*SAR ADC1 conversion done indication*/
+            uint32_t meas1_start_sar:   1;                                 /*SAR ADC1 controller (in RTC) starts conversion*/
+            uint32_t meas1_start_force: 1;                                 /*1: SAR ADC1 controller (in RTC) is started by SW*/
+            uint32_t sar1_en_pad:      12;                                 /*SAR ADC1 pad enable bitmap*/
+            uint32_t sar1_en_pad_force: 1;                                 /*1: SAR ADC1 pad enable bitmap is controlled by SW*/
+        };
+        uint32_t val;
+    } sar_meas1_ctrl2;
+    union {
+        struct {
+            uint32_t reserved0:     31;
+            uint32_t sar1_dig_force: 1;                                    /*1: SAR ADC1 controlled by DIG ADC1 CTRL*/
+        };
+        uint32_t val;
+    } sar_meas1_mux;
+    uint32_t sar_atten1;                                                   /*2-bit attenuation for each pad*/
+    union {
+        struct {
+            uint32_t sar_amp_wait1:16;
+            uint32_t sar_amp_wait2:16;
+        };
+        uint32_t val;
+    } sar_amp_ctrl1;
+    union {
+        struct {
+            uint32_t sar1_dac_xpd_fsm_idle:      1;
+            uint32_t xpd_sar_amp_fsm_idle:       1;
+            uint32_t amp_rst_fb_fsm_idle:        1;
+            uint32_t amp_short_ref_fsm_idle:     1;
+            uint32_t amp_short_ref_gnd_fsm_idle: 1;
+            uint32_t xpd_sar_fsm_idle:           1;
+            uint32_t sar_rstb_fsm_idle:          1;
+            uint32_t reserved7:                  9;
+            uint32_t sar_amp_wait3:             16;
+        };
+        uint32_t val;
+    } sar_amp_ctrl2;
+    union {
+        struct {
+            uint32_t sar1_dac_xpd_fsm:      4;
+            uint32_t xpd_sar_amp_fsm:       4;
+            uint32_t amp_rst_fb_fsm:        4;
+            uint32_t amp_short_ref_fsm:     4;
+            uint32_t amp_short_ref_gnd_fsm: 4;
+            uint32_t xpd_sar_fsm:           4;
+            uint32_t sar_rstb_fsm:          4;
+            uint32_t reserved28:            4;
+        };
+        uint32_t val;
+    } sar_amp_ctrl3;
+    union {
+        struct {
+            uint32_t sar2_clk_div:        8;                               /*clock divider*/
+            uint32_t reserved8:           8;
+            uint32_t sar2_wait_arb_cycle: 2;                               /*wait arbit stable after sar_done*/
+            uint32_t sar2_clk_gated:      1;
+            uint32_t sar2_sample_num:     8;
+            uint32_t reserved27:          2;
+            uint32_t sar2_data_inv:       1;                               /*Invert SAR ADC2 data*/
+            uint32_t sar2_int_en:         1;                               /*enable saradc2 to send out interrupt*/
+            uint32_t reserved31:          1;
+        };
+        uint32_t val;
+    } sar_reader2_ctrl;
+    uint32_t sar_reader2_status;                                           /**/
+    union {
+        struct {
+            uint32_t sar2_cntl_state:   3;                                 /*saradc2_cntl_fsm*/
+            uint32_t sar2_pwdet_cal_en: 1;                                 /*rtc control pwdet enable*/
+            uint32_t sar2_pkdet_cal_en: 1;                                 /*rtc control pkdet enable*/
+            uint32_t sar2_en_test:      1;                                 /*SAR2_EN_TEST*/
+            uint32_t sar2_rstb_force:   2;
+            uint32_t sar2_standby_wait: 8;
+            uint32_t sar2_rstb_wait:    8;
+            uint32_t sar2_xpd_wait:     8;
+        };
+        uint32_t val;
+    } sar_meas2_ctrl1;
+    union {
+        struct {
+            uint32_t meas2_data_sar:   16;                                 /*SAR ADC2 data*/
+            uint32_t meas2_done_sar:    1;                                 /*SAR ADC2 conversion done indication*/
+            uint32_t meas2_start_sar:   1;                                 /*SAR ADC2 controller (in RTC) starts conversion*/
+            uint32_t meas2_start_force: 1;                                 /*1: SAR ADC2 controller (in RTC) is started by SW*/
+            uint32_t sar2_en_pad:      12;                                 /*SAR ADC2 pad enable bitmap*/
+            uint32_t sar2_en_pad_force: 1;                                 /*1: SAR ADC2 pad enable bitmap is controlled by SW*/
+        };
+        uint32_t val;
+    } sar_meas2_ctrl2;
+    union {
+        struct {
+            uint32_t reserved0:     28;
+            uint32_t sar2_pwdet_cct: 3;                                    /*SAR2_PWDET_CCT*/
+            uint32_t sar2_rtc_force: 1;                                    /*in sleep  force to use rtc to control ADC*/
+        };
+        uint32_t val;
+    } sar_meas2_mux;
+    uint32_t sar_atten2;                                                   /*2-bit attenuation for each pad*/
+    union {
+        struct {
+            uint32_t reserved0:    29;
+            uint32_t force_xpd_sar: 2;
+            uint32_t sarclk_en:     1;
+        };
+        uint32_t val;
+    } sar_power_xpd_sar;
+    union {
+        struct {
+            uint32_t i2c_slave_addr1:   11;
+            uint32_t i2c_slave_addr0:   11;
+            uint32_t meas_status:        8;
+            uint32_t reserved30:         2;
+        };
+        uint32_t val;
+    } sar_slave_addr1;
+    union {
+        struct {
+            uint32_t i2c_slave_addr3:11;
+            uint32_t i2c_slave_addr2:11;
+            uint32_t reserved22:     10;
+        };
+        uint32_t val;
+    } sar_slave_addr2;
+    union {
+        struct {
+            uint32_t i2c_slave_addr5:11;
+            uint32_t i2c_slave_addr4:11;
+            uint32_t reserved22:     10;
+        };
+        uint32_t val;
+    } sar_slave_addr3;
+    union {
+        struct {
+            uint32_t i2c_slave_addr7:11;
+            uint32_t i2c_slave_addr6:11;
+            uint32_t reserved22:     10;
+        };
+        uint32_t val;
+    } sar_slave_addr4;
+    union {
+        struct {
+            uint32_t tsens_out:            8;                              /*temperature sensor data out*/
+            uint32_t tsens_ready:          1;                              /*indicate temperature sensor out ready*/
+            uint32_t reserved9:            3;
+            uint32_t tsens_int_en:         1;                              /*enable temperature sensor to send out interrupt*/
+            uint32_t tsens_in_inv:         1;                              /*invert temperature sensor data*/
+            uint32_t tsens_clk_div:        8;                              /*temperature sensor clock divider*/
+            uint32_t tsens_power_up:       1;                              /*temperature sensor power up*/
+            uint32_t tsens_power_up_force: 1;                              /*1: dump out & power up controlled by SW*/
+            uint32_t tsens_dump_out:       1;                              /*temperature sensor dump out*/
+            uint32_t reserved25:           7;
+        };
+        uint32_t val;
+    } sar_tctrl;
+    union {
+        struct {
+            uint32_t tsens_xpd_wait: 12;
+            uint32_t tsens_xpd_force: 2;
+            uint32_t tsens_clk_inv:   1;
+            uint32_t reserved15:     17;
+        };
+        uint32_t val;
+    } sar_tctrl2;
+    union {
+        struct {
+            uint32_t sar_i2c_ctrl:       28;                               /*I2C control data*/
+            uint32_t sar_i2c_start:       1;                               /*start I2C*/
+            uint32_t sar_i2c_start_force: 1;                               /*1: I2C started by SW*/
+            uint32_t reserved30:          2;
+        };
+        uint32_t val;
+    } sar_i2c_ctrl;
+    union {
+        struct {
+            uint32_t touch_outen:        15;                               /*touch controller output enable*/
+            uint32_t touch_status_clr:    1;                               /*clear all touch active status*/
+            uint32_t touch_data_sel:      2;                               /*3: smooth data 2: baseline 1 0: raw_data*/
+            uint32_t touch_denoise_end:   1;                               /*touch_denoise_done*/
+            uint32_t touch_unit_end:      1;                               /*touch_unit_done*/
+            uint32_t touch_approach_pad2: 4;                               /*indicate which pad is approach pad2*/
+            uint32_t touch_approach_pad1: 4;                               /*indicate which pad is approach pad1*/
+            uint32_t touch_approach_pad0: 4;                               /*indicate which pad is approach pad0*/
+        };
+        uint32_t val;
+    } sar_touch_conf;
+    union {
+        struct {
+            uint32_t thresh:       22;                                     /*Finger threshold for touch pad 1*/
+            uint32_t reserved22:   10;
+        };
+        uint32_t val;
+    } touch_thresh[14];
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    union {
+        struct {
+            uint32_t touch_pad_active: 15;                                 /*touch active status*/
+            uint32_t touch_channel_clr:15;                                 /*Clear touch channel*/
+            uint32_t reserved30:        1;
+            uint32_t touch_meas_done:   1;
+        };
+        uint32_t val;
+    } sar_touch_chn_st;
+    union {
+        struct {
+            uint32_t touch_denoise_data:22;                                /*the counter for touch pad 0*/
+            uint32_t touch_scan_curr:    4;
+            uint32_t reserved26:         6;
+        };
+        uint32_t val;
+    } sar_touch_status0;
+    union {
+        struct {
+            uint32_t touch_pad1_data:    22;
+            uint32_t reserved22:          7;
+            uint32_t touch_pad_debounce:  3;
+        };
+        uint32_t val;
+    } sar_touch_status[14];
+    union {
+        struct {
+            uint32_t touch_slp_data:    22;
+            uint32_t reserved22:         7;
+            uint32_t touch_slp_debounce: 3;
+        };
+        uint32_t val;
+    } sar_touch_status15;
+    union {
+        struct {
+            uint32_t touch_approach_pad2_cnt: 8;
+            uint32_t touch_approach_pad1_cnt: 8;
+            uint32_t touch_approach_pad0_cnt: 8;
+            uint32_t touch_slp_approach_cnt:  8;
+        };
+        uint32_t val;
+    } sar_touch_status16;
+    union {
+        struct {
+            uint32_t sw_fstep:          16;                                /*frequency step for CW generator*/
+            uint32_t sw_tone_en:         1;                                /*1: enable CW generator*/
+            uint32_t debug_bit_sel:      5;
+            uint32_t dac_dig_force:      1;                                /*1: DAC1 & DAC2 use DMA*/
+            uint32_t dac_clk_force_low:  1;                                /*1: force PDAC_CLK to low*/
+            uint32_t dac_clk_force_high: 1;                                /*1: force PDAC_CLK to high*/
+            uint32_t dac_clk_inv:        1;                                /*1: invert PDAC_CLK*/
+            uint32_t reserved26:         6;
+        };
+        uint32_t val;
+    } sar_dac_ctrl1;
+    union {
+        struct {
+            uint32_t dac_dc1:    8;                                        /*DC offset for DAC1 CW generator*/
+            uint32_t dac_dc2:    8;                                        /*DC offset for DAC2 CW generator*/
+            uint32_t dac_scale1: 2;                                        /*00: no scale*/
+            uint32_t dac_scale2: 2;                                        /*00: no scale*/
+            uint32_t dac_inv1:   2;                                        /*00: do not invert any bits*/
+            uint32_t dac_inv2:   2;                                        /*00: do not invert any bits*/
+            uint32_t dac_cw_en1: 1;                                        /*1: to select CW generator as source to PDAC1_DAC[7:0]*/
+            uint32_t dac_cw_en2: 1;                                        /*1: to select CW generator as source to PDAC2_DAC[7:0]*/
+            uint32_t reserved26: 6;
+        };
+        uint32_t val;
+    } sar_dac_ctrl2;
+    union {
+        struct {
+            uint32_t reserved0:        25;
+            uint32_t dbg_trigger:       1;                                 /*trigger cocpu debug registers*/
+            uint32_t clk_en_st:         1;                                 /*check cocpu whether clk on*/
+            uint32_t reset_n:           1;                                 /*check cocpu whether in reset state*/
+            uint32_t eoi:               1;                                 /*check cocpu whether in interrupt state*/
+            uint32_t trap:              1;                                 /*check cocpu whether in trap state*/
+            uint32_t ebreak:            1;                                 /*check cocpu whether in ebreak*/
+            uint32_t reserved31:        1;
+        };
+        uint32_t val;
+    } sar_cocpu_state;
+    union {
+        struct {
+            uint32_t touch_done:                             1;            /*int from touch done*/
+            uint32_t touch_inactive:                         1;            /*int from touch inactive*/
+            uint32_t touch_active:                           1;            /*int from touch active*/
+            uint32_t saradc1:                                1;            /*int from saradc1*/
+            uint32_t saradc2:                                1;            /*int from saradc2*/
+            uint32_t tsens:                                  1;            /*int from tsens*/
+            uint32_t start:                                  1;            /*int from start*/
+            uint32_t sw:                                     1;            /*int from software*/
+            uint32_t swd:                                    1;            /*int from super watch dog*/
+            uint32_t touch_timeout:                          1;
+            uint32_t touch_approach_loop_done:               1;
+            uint32_t touch_scan_done:                        1;
+            uint32_t reserved12:                            20;
+        };
+        uint32_t val;
+    } sar_cocpu_int_raw;
+    union {
+        struct {
+            uint32_t touch_done:                             1;
+            uint32_t touch_inactive:                         1;
+            uint32_t touch_active:                           1;
+            uint32_t saradc1:                                1;
+            uint32_t saradc2:                                1;
+            uint32_t tsens:                                  1;
+            uint32_t start:                                  1;
+            uint32_t sw:                                     1;            /*cocpu int enable*/
+            uint32_t swd:                                    1;
+            uint32_t touch_timeout:                          1;
+            uint32_t touch_approach_loop_done:               1;
+            uint32_t touch_scan_done:                        1;
+            uint32_t reserved12:                            20;
+        };
+        uint32_t val;
+    } sar_cocpu_int_ena;
+    union {
+        struct {
+            uint32_t touch_done:                            1;
+            uint32_t touch_inactive:                        1;
+            uint32_t touch_active:                          1;
+            uint32_t saradc1:                               1;
+            uint32_t saradc2:                               1;
+            uint32_t tsens:                                 1;
+            uint32_t start:                                 1;
+            uint32_t sw:                                    1;             /*cocpu int status*/
+            uint32_t swd:                                   1;
+            uint32_t touch_timeout:                         1;
+            uint32_t touch_approach_loop_done:              1;
+            uint32_t touch_scan_done:                       1;
+            uint32_t reserved12:                           20;
+        };
+        uint32_t val;
+    } sar_cocpu_int_st;
+    union {
+        struct {
+            uint32_t touch_done:                             1;
+            uint32_t touch_inactive:                         1;
+            uint32_t touch_active:                           1;
+            uint32_t saradc1:                                1;
+            uint32_t saradc2:                                1;
+            uint32_t tsens:                                  1;
+            uint32_t start:                                  1;
+            uint32_t sw:                                     1;            /*cocpu int clear*/
+            uint32_t swd:                                    1;
+            uint32_t touch_timeout:                          1;
+            uint32_t touch_approach_loop_done:               1;
+            uint32_t touch_scan_done:                        1;
+            uint32_t reserved12:                            20;
+        };
+        uint32_t val;
+    } sar_cocpu_int_clr;
+    union {
+        struct {
+            uint32_t pc:            13;                                    /*cocpu Program counter*/
+            uint32_t mem_vld:        1;                                    /*cocpu mem valid output*/
+            uint32_t mem_rdy:        1;                                    /*cocpu mem ready input*/
+            uint32_t mem_wen:        4;                                    /*cocpu mem write enable output*/
+            uint32_t mem_addr:      13;                                    /*cocpu mem address output*/
+        };
+        uint32_t val;
+    } sar_cocpu_debug;
+    union {
+        struct {
+            uint32_t reserved0:       28;
+            uint32_t xpd_hall:         1;                                  /*Power on hall sensor and connect to VP and VN*/
+            uint32_t xpd_hall_force:   1;                                  /*1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor*/
+            uint32_t hall_phase:       1;                                  /*Reverse phase of hall sensor*/
+            uint32_t hall_phase_force: 1;                                  /*1: HALL PHASE is controlled by SW  0: HALL PHASE is controlled by FSM in ULP-coprocessor*/
+        };
+        uint32_t val;
+    } sar_hall_ctrl;
+    uint32_t sar_nouse;                                                    /**/
+    union {
+        struct {
+            uint32_t reserved0:     26;
+            uint32_t dac_clk_en:     1;
+            uint32_t rtc_i2c_clk_en: 1;
+            uint32_t reserved28:     1;
+            uint32_t tsens_clk_en:   1;
+            uint32_t saradc_clk_en:  1;
+            uint32_t iomux_clk_en:   1;
+        };
+        uint32_t val;
+    } sar_peri_clk_gate_conf;
+    union {
+        struct {
+            uint32_t reserved0:    25;
+            uint32_t reset:         1;
+            uint32_t dac_reset:     1;
+            uint32_t rtc_i2c_reset: 1;
+            uint32_t reserved28:    1;
+            uint32_t tsens_reset:   1;
+            uint32_t saradc_reset:  1;
+            uint32_t reserved31:    1;
+        };
+        uint32_t val;
+    } sar_peri_reset_conf;
+    union {
+        struct {
+            uint32_t touch_done_w1ts:                             1;
+            uint32_t touch_inactive_w1ts:                         1;
+            uint32_t touch_active_w1ts:                           1;
+            uint32_t saradc1_w1ts:                                1;
+            uint32_t saradc2_w1ts:                                1;
+            uint32_t tsens_w1ts:                                  1;
+            uint32_t start_w1ts:                                  1;
+            uint32_t sw_w1ts:                                     1;
+            uint32_t swd_w1ts:                                    1;
+            uint32_t touch_timeout_w1ts:                          1;
+            uint32_t touch_approach_loop_done_w1ts:               1;
+            uint32_t touch_scan_done_w1ts:                        1;
+            uint32_t reserved12:                                 20;
+        };
+        uint32_t val;
+    } sar_cocpu_int_ena_w1ts;
+    union {
+        struct {
+            uint32_t touch_done_w1tc:                             1;
+            uint32_t touch_inactive_w1tc:                         1;
+            uint32_t touch_active_w1tc:                           1;
+            uint32_t saradc1_w1tc:                                1;
+            uint32_t saradc2_w1tc:                                1;
+            uint32_t tsens_w1tc:                                  1;
+            uint32_t start_w1tc:                                  1;
+            uint32_t sw_w1tc:                                     1;
+            uint32_t swd_w1tc:                                    1;
+            uint32_t touch_timeout_w1tc:                          1;
+            uint32_t touch_approach_loop_done_w1tc:               1;
+            uint32_t touch_scan_done_w1tc:                        1;
+            uint32_t reserved12:                                 20;
+        };
+        uint32_t val;
+    } sar_cocpu_int_ena_w1tc;
+    union {
+        struct {
+            uint32_t sar_date:  28;
+            uint32_t reserved28: 4;
+        };
+        uint32_t val;
+    } sardate;
+} sens_dev_t;
+extern sens_dev_t SENS;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_SENS_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/sensitive_reg.h b/components/soc/esp32c3/include/soc/sensitive_reg.h
new file mode 100644
index 0000000000..e1ce7d93ef
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/sensitive_reg.h
@@ -0,0 +1,2304 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SENSITIVE_REG_H_
+#define _SOC_SENSITIVE_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define SENSITIVE_ROM_TABLE_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x000)
+/* SENSITIVE_ROM_TABLE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_ROM_TABLE_LOCK  (BIT(0))
+#define SENSITIVE_ROM_TABLE_LOCK_M  (BIT(0))
+#define SENSITIVE_ROM_TABLE_LOCK_V  0x1
+#define SENSITIVE_ROM_TABLE_LOCK_S  0
+
+#define SENSITIVE_ROM_TABLE_REG          (DR_REG_SENSITIVE_BASE + 0x004)
+/* SENSITIVE_ROM_TABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SENSITIVE_ROM_TABLE  0xFFFFFFFF
+#define SENSITIVE_ROM_TABLE_M  ((SENSITIVE_ROM_TABLE_V)<<(SENSITIVE_ROM_TABLE_S))
+#define SENSITIVE_ROM_TABLE_V  0xFFFFFFFF
+#define SENSITIVE_ROM_TABLE_S  0
+
+#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x008)
+/* SENSITIVE_PRIVILEGE_MODE_SEL_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK  (BIT(0))
+#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_M  (BIT(0))
+#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_V  0x1
+#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_S  0
+
+#define SENSITIVE_PRIVILEGE_MODE_SEL_REG          (DR_REG_SENSITIVE_BASE + 0x00C)
+/* SENSITIVE_PRIVILEGE_MODE_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_PRIVILEGE_MODE_SEL  (BIT(0))
+#define SENSITIVE_PRIVILEGE_MODE_SEL_M  (BIT(0))
+#define SENSITIVE_PRIVILEGE_MODE_SEL_V  0x1
+#define SENSITIVE_PRIVILEGE_MODE_SEL_S  0
+
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x010)
+/* SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK  (BIT(0))
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M  (BIT(0))
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V  0x1
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S  0
+
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x014)
+/* SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST  (BIT(0))
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M  (BIT(0))
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V  0x1
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S  0
+
+#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG          (DR_REG_SENSITIVE_BASE + 0x018)
+/* SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK  (BIT(0))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M  (BIT(0))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V  0x1
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S  0
+
+#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG          (DR_REG_SENSITIVE_BASE + 0x01C)
+/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM : R/W ;bitpos:[3:1] ;default: ~3'h0 ; */
+/*description: */
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM  0x00000007
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_M  ((SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V  0x7
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S  1
+/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE : R/W ;bitpos:[0] ;default: ~1'h0 ; */
+/*description: */
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE  (BIT(0))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_M  (BIT(0))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V  0x1
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_S  0
+
+#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG          (DR_REG_SENSITIVE_BASE + 0x020)
+/* SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP  (BIT(3))
+#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_M  (BIT(3))
+#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V  0x1
+#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S  3
+/* SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: */
+#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM  0x00000007
+#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_M  ((SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V  0x7
+#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S  0
+
+#define SENSITIVE_INTERNAL_SRAM_USAGE_4_REG          (DR_REG_SENSITIVE_BASE + 0x024)
+/* SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM  (BIT(0))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_M  (BIT(0))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_V  0x1
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_S  0
+
+#define SENSITIVE_CACHE_TAG_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x028)
+/* SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CACHE_TAG_ACCESS_LOCK  (BIT(0))
+#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M  (BIT(0))
+#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V  0x1
+#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S  0
+
+#define SENSITIVE_CACHE_TAG_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x02C)
+/* SENSITIVE_PRO_D_TAG_WR_ACS : R/W ;bitpos:[3] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_PRO_D_TAG_WR_ACS  (BIT(3))
+#define SENSITIVE_PRO_D_TAG_WR_ACS_M  (BIT(3))
+#define SENSITIVE_PRO_D_TAG_WR_ACS_V  0x1
+#define SENSITIVE_PRO_D_TAG_WR_ACS_S  3
+/* SENSITIVE_PRO_D_TAG_RD_ACS : R/W ;bitpos:[2] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_PRO_D_TAG_RD_ACS  (BIT(2))
+#define SENSITIVE_PRO_D_TAG_RD_ACS_M  (BIT(2))
+#define SENSITIVE_PRO_D_TAG_RD_ACS_V  0x1
+#define SENSITIVE_PRO_D_TAG_RD_ACS_S  2
+/* SENSITIVE_PRO_I_TAG_WR_ACS : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_PRO_I_TAG_WR_ACS  (BIT(1))
+#define SENSITIVE_PRO_I_TAG_WR_ACS_M  (BIT(1))
+#define SENSITIVE_PRO_I_TAG_WR_ACS_V  0x1
+#define SENSITIVE_PRO_I_TAG_WR_ACS_S  1
+/* SENSITIVE_PRO_I_TAG_RD_ACS : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_PRO_I_TAG_RD_ACS  (BIT(0))
+#define SENSITIVE_PRO_I_TAG_RD_ACS_M  (BIT(0))
+#define SENSITIVE_PRO_I_TAG_RD_ACS_V  0x1
+#define SENSITIVE_PRO_I_TAG_RD_ACS_S  0
+
+#define SENSITIVE_CACHE_MMU_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x030)
+/* SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CACHE_MMU_ACCESS_LOCK  (BIT(0))
+#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M  (BIT(0))
+#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V  0x1
+#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S  0
+
+#define SENSITIVE_CACHE_MMU_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x034)
+/* SENSITIVE_PRO_MMU_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define SENSITIVE_PRO_MMU_WR_ACS  (BIT(1))
+#define SENSITIVE_PRO_MMU_WR_ACS_M  (BIT(1))
+#define SENSITIVE_PRO_MMU_WR_ACS_V  0x1
+#define SENSITIVE_PRO_MMU_WR_ACS_S  1
+/* SENSITIVE_PRO_MMU_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SENSITIVE_PRO_MMU_RD_ACS  (BIT(0))
+#define SENSITIVE_PRO_MMU_RD_ACS_M  (BIT(0))
+#define SENSITIVE_PRO_MMU_RD_ACS_V  0x1
+#define SENSITIVE_PRO_MMU_RD_ACS_S  0
+
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x038)
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x03C)
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x040)
+/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x044)
+/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x048)
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x04C)
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x050)
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x054)
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x058)
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x05C)
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x060)
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x064)
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x068)
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x06C)
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x070)
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x074)
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x078)
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x07C)
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x080)
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x084)
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN  (BIT(1))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V  0x1
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S  1
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S  0
+
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x088)
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[26:3] ;default: 24'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR  0x00FFFFFF
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0xFFFFFF
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  3
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[2:1] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD  0x00000003
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  1
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S  0
+
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x08C)
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[4:1] ;default: 4'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN  0x0000000F
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V  0xF
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S  1
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x090)
+/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x094)
+/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR  0x000000FF
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V  0xFF
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S  14
+/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2  0x00000003
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S  4
+/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1  0x00000003
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S  2
+/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0  0x00000003
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x098)
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR  0x000000FF
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V  0xFF
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S  14
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2  0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S  4
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1  0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S  2
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0  0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x09C)
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR  0x000000FF
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V  0xFF
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S  14
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2  0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S  4
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1  0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S  2
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0  0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x0A0)
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR  0x000000FF
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V  0xFF
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S  14
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S  4
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S  2
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x0A4)
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR  0x000000FF
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V  0xFF
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S  14
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S  4
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S  2
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x0A8)
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x0AC)
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S  18
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S  12
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  9
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  6
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  3
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x0B0)
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S  18
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S  12
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  9
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  6
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  3
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x0B4)
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK  (BIT(0))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S  0
+
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x0B8)
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN  (BIT(1))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S  1
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR  (BIT(0))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
+
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x0BC)
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[28:5] ;default: 24'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR  0x00FFFFFF
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0xFFFFFF
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  5
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD  0x00000003
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  3
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE  (BIT(2))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M  (BIT(2))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S  2
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR  (BIT(1))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(1))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  1
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR  (BIT(0))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
+
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x0C0)
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x0C4)
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S  26
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S  24
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x0C8)
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S  0
+
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x0CC)
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN  (BIT(1))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S  1
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
+
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x0D0)
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[27:4] ;default: 24'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR  0x00FFFFFF
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0xFFFFFF
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  4
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD  0x00000003
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  2
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK  (BIT(1))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M  (BIT(1))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S  1
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
+
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x0D4)
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[4:1] ;default: 4'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN  0x0000000F
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V  0xF
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S  1
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x0D8)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x0DC)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S  30
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S  24
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S  18
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S  12
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S  8
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S  2
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x0E0)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S  30
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S  22
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x0E4)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S  22
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x0E8)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S  30
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S  24
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S  22
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S  20
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S  18
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S  12
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S  8
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S  2
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x0EC)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S  30
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S  24
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S  18
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S  12
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S  8
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S  2
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x0F0)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S  30
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S  22
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x0F4)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S  22
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x0F8)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S  30
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S  24
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S  22
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S  20
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S  18
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S  12
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S  8
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S  2
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x0FC)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1  0x000007FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V  0x7FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S  11
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0  0x000007FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V  0x7FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x100)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H  0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S  9
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L  0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H  0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S  3
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L  0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x104)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x108)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S  12
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S  10
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S  8
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S  6
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S  4
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S  2
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x10C)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S  12
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S  10
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S  8
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S  6
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S  4
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S  2
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x110)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_V  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x114)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_V  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x118)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_V  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x11C)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_V  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x120)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_V  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x124)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_V  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x128)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_V  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x12C)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_V  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x130)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x134)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN  (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S  1
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x138)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE  (BIT(5))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M  (BIT(5))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S  5
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[4:2] ;default: 3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE  0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S  2
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0  (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M  (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S  1
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x13C)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR  0xFFFFFFFF
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG          (DR_REG_SENSITIVE_BASE + 0x140)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN  (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S  1
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG          (DR_REG_SENSITIVE_BASE + 0x144)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S  3
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S  1
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG          (DR_REG_SENSITIVE_BASE + 0x148)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR  0xFFFFFFFF
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x14C)
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x150)
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S  30
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S  26
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S  24
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_S  18
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S  16
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S  14
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_S  12
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S  10
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S  8
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S  6
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S  4
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S  2
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x154)
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S  30
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S  28
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S  26
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S  22
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S  16
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S  10
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S  6
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S  4
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x158)
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S  28
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S  26
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S  22
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S  14
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S  10
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S  4
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x15C)
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S  14
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S  12
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S  8
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S  6
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S  4
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S  2
+
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x160)
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_M  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x164)
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN  (BIT(1))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_S  1
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x168)
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE  (BIT(6))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M  (BIT(6))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S  6
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[5:3] ;default: 3'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE  0x00000007
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V  0x7
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S  3
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS : RO ;bitpos:[2:1] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S  1
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x16C)
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR  0xFFFFFFFF
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V  0xFFFFFFFF
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S  0
+
+#define SENSITIVE_CLOCK_GATE_REG          (DR_REG_SENSITIVE_BASE + 0x170)
+/* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SENSITIVE_CLK_EN  (BIT(0))
+#define SENSITIVE_CLK_EN_M  (BIT(0))
+#define SENSITIVE_CLK_EN_V  0x1
+#define SENSITIVE_CLK_EN_S  0
+
+#define SENSITIVE_DATE_REG          (DR_REG_SENSITIVE_BASE + 0xFFC)
+/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2010200 ; */
+/*description: */
+#define SENSITIVE_DATE  0x0FFFFFFF
+#define SENSITIVE_DATE_M  ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S))
+#define SENSITIVE_DATE_V  0xFFFFFFF
+#define SENSITIVE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SENSITIVE_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/sensitive_struct.h b/components/soc/esp32c3/include/soc/sensitive_struct.h
new file mode 100644
index 0000000000..a24ccf6402
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/sensitive_struct.h
@@ -0,0 +1,1912 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SENSITIVE_STRUCT_H_
+#define _SOC_SENSITIVE_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t reg_rom_table_lock            :    1;  /*rom_table_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } rom_table_lock;
+    uint32_t rom_table;
+    union {
+        struct {
+            uint32_t reg_privilege_mode_sel_lock   :    1;  /*privilege_mode_sel_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } privilege_mode_sel_lock;
+    union {
+        struct {
+            uint32_t reg_privilege_mode_sel        :    1;  /*privilege_mode_sel*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } privilege_mode_sel;
+    union {
+        struct {
+            uint32_t reg_apb_peripheral_access_lock:    1;  /*apb_peripheral_access_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } apb_peripheral_access_0;
+    union {
+        struct {
+            uint32_t reg_apb_peripheral_access_split_burst:    1;  /*apb_peripheral_access_split_burst*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } apb_peripheral_access_1;
+    union {
+        struct {
+            uint32_t reg_internal_sram_usage_lock  :    1;  /*internal_sram_usage_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } internal_sram_usage_0;
+    union {
+        struct {
+            uint32_t reg_internal_sram_usage_cpu_cache:    1;  /*internal_sram_usage_cpu_cache*/
+            uint32_t reg_internal_sram_usage_cpu_sram:    3;  /*internal_sram_usage_cpu_sram*/
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } internal_sram_usage_1;
+    union {
+        struct {
+            uint32_t reg_internal_sram_usage_mac_dump_sram:    3;  /*internal_sram_usage_mac_dump_sram*/
+            uint32_t reg_internal_sram_alloc_mac_dump:    1;  /*internal_sram_alloc_mac_dump*/
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } internal_sram_usage_3;
+    union {
+        struct {
+            uint32_t reg_internal_sram_usage_log_sram:    1;  /*internal_sram_usage_log_sram*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } internal_sram_usage_4;
+    union {
+        struct {
+            uint32_t reg_cache_tag_access_lock     :    1;  /*cache_tag_access_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } cache_tag_access_0;
+    union {
+        struct {
+            uint32_t reg_pro_i_tag_rd_acs          :    1;  /*pro_i_tag_rd_acs*/
+            uint32_t reg_pro_i_tag_wr_acs          :    1;  /*pro_i_tag_wr_acs*/
+            uint32_t reg_pro_d_tag_rd_acs          :    1;  /*pro_d_tag_rd_acs*/
+            uint32_t reg_pro_d_tag_wr_acs          :    1;  /*pro_d_tag_wr_acs*/
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } cache_tag_access_1;
+    union {
+        struct {
+            uint32_t reg_cache_mmu_access_lock     :    1;  /*cache_mmu_access_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } cache_mmu_access_0;
+    union {
+        struct {
+            uint32_t reg_pro_mmu_rd_acs            :    1;  /*pro_mmu_rd_acs*/
+            uint32_t reg_pro_mmu_wr_acs            :    1;  /*pro_mmu_wr_acs*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } cache_mmu_access_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_spi2_pms_constrain_lock:    1;  /*dma_apbperi_spi2_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_spi2_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } dma_apbperi_spi2_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_uchi0_pms_constrain_lock:    1;  /*dma_apbperi_uchi0_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_uchi0_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } dma_apbperi_uchi0_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_i2s0_pms_constrain_lock:    1;  /*dma_apbperi_i2s0_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_i2s0_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } dma_apbperi_i2s0_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_mac_pms_constrain_lock:    1;  /*dma_apbperi_mac_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_mac_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } dma_apbperi_mac_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_backup_pms_constrain_lock:    1;  /*dma_apbperi_backup_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_backup_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } dma_apbperi_backup_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_lc_pms_constrain_lock:    1;  /*dma_apbperi_lc_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_lc_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } dma_apbperi_lc_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_aes_pms_constrain_lock:    1;  /*dma_apbperi_aes_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_aes_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } dma_apbperi_aes_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_sha_pms_constrain_lock:    1;  /*dma_apbperi_sha_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_sha_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } dma_apbperi_sha_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_lock:    1;  /*dma_apbperi_adc_dac_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_adc_dac_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } dma_apbperi_adc_dac_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_pms_monitor_lock:    1;  /*dma_apbperi_pms_monitor_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_pms_monitor_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_pms_monitor_violate_clr:    1;  /*dma_apbperi_pms_monitor_violate_clr*/
+            uint32_t reg_dma_apbperi_pms_monitor_violate_en:    1;  /*dma_apbperi_pms_monitor_violate_en*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } dma_apbperi_pms_monitor_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_pms_monitor_violate_intr:    1;  /*dma_apbperi_pms_monitor_violate_intr*/
+            uint32_t reg_dma_apbperi_pms_monitor_violate_status_world:    2;  /*dma_apbperi_pms_monitor_violate_status_world*/
+            uint32_t reg_dma_apbperi_pms_monitor_violate_status_addr:    24;  /*dma_apbperi_pms_monitor_violate_status_addr*/
+            uint32_t reserved27                    :    5;
+        };
+        uint32_t val;
+    } dma_apbperi_pms_monitor_2;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_pms_monitor_violate_status_wr:    1;  /*dma_apbperi_pms_monitor_violate_status_wr*/
+            uint32_t reg_dma_apbperi_pms_monitor_violate_status_byteen:    4;  /*dma_apbperi_pms_monitor_violate_status_byteen*/
+            uint32_t reserved5                     :    27;
+        };
+        uint32_t val;
+    } dma_apbperi_pms_monitor_3;
+    union {
+        struct {
+            uint32_t reg_core_x_iram0_dram0_dma_split_line_constrain_lock:    1;  /*core_x_iram0_dram0_dma_split_line_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_dma_split_line_constrain_0;
+    union {
+        struct {
+            uint32_t reg_core_x_iram0_dram0_dma_sram_category_0:    2;  /*core_x_iram0_dram0_dma_sram_category_0*/
+            uint32_t reg_core_x_iram0_dram0_dma_sram_category_1:    2;  /*core_x_iram0_dram0_dma_sram_category_1*/
+            uint32_t reg_core_x_iram0_dram0_dma_sram_category_2:    2;  /*core_x_iram0_dram0_dma_sram_category_2*/
+            uint32_t reserved6                     :    8;
+            uint32_t reg_core_x_iram0_dram0_dma_sram_splitaddr:    8;  /*core_x_iram0_dram0_dma_sram_splitaddr*/
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_dma_split_line_constrain_1;
+    union {
+        struct {
+            uint32_t reg_core_x_iram0_sram_line_0_category_0:    2;  /*core_x_iram0_sram_line_0_category_0*/
+            uint32_t reg_core_x_iram0_sram_line_0_category_1:    2;  /*core_x_iram0_sram_line_0_category_1*/
+            uint32_t reg_core_x_iram0_sram_line_0_category_2:    2;  /*core_x_iram0_sram_line_0_category_2*/
+            uint32_t reserved6                     :    8;
+            uint32_t reg_core_x_iram0_sram_line_0_splitaddr:    8;  /*core_x_iram0_sram_line_0_splitaddr*/
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_dma_split_line_constrain_2;
+    union {
+        struct {
+            uint32_t reg_core_x_iram0_sram_line_1_category_0:    2;  /*core_x_iram0_sram_line_1_category_0*/
+            uint32_t reg_core_x_iram0_sram_line_1_category_1:    2;  /*core_x_iram0_sram_line_1_category_1*/
+            uint32_t reg_core_x_iram0_sram_line_1_category_2:    2;  /*core_x_iram0_sram_line_1_category_2*/
+            uint32_t reserved6                     :    8;
+            uint32_t reg_core_x_iram0_sram_line_1_splitaddr:    8;  /*core_x_iram0_sram_line_1_splitaddr*/
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_dma_split_line_constrain_3;
+    union {
+        struct {
+            uint32_t reg_core_x_dram0_dma_sram_line_0_category_0:    2;  /*core_x_dram0_dma_sram_line_0_category_0*/
+            uint32_t reg_core_x_dram0_dma_sram_line_0_category_1:    2;  /*core_x_dram0_dma_sram_line_0_category_1*/
+            uint32_t reg_core_x_dram0_dma_sram_line_0_category_2:    2;  /*core_x_dram0_dma_sram_line_0_category_2*/
+            uint32_t reserved6                     :    8;
+            uint32_t reg_core_x_dram0_dma_sram_line_0_splitaddr:    8;  /*core_x_dram0_dma_sram_line_0_splitaddr*/
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_dma_split_line_constrain_4;
+    union {
+        struct {
+            uint32_t reg_core_x_dram0_dma_sram_line_1_category_0:    2;  /*core_x_dram0_dma_sram_line_1_category_0*/
+            uint32_t reg_core_x_dram0_dma_sram_line_1_category_1:    2;  /*core_x_dram0_dma_sram_line_1_category_1*/
+            uint32_t reg_core_x_dram0_dma_sram_line_1_category_2:    2;  /*core_x_dram0_dma_sram_line_1_category_2*/
+            uint32_t reserved6                     :    8;
+            uint32_t reg_core_x_dram0_dma_sram_line_1_splitaddr:    8;  /*core_x_dram0_dma_sram_line_1_splitaddr*/
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_dma_split_line_constrain_5;
+    union {
+        struct {
+            uint32_t reg_core_x_iram0_pms_constrain_lock:    1;  /*core_x_iram0_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_x_iram0_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_0:    3;  /*core_x_iram0_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_1:    3;  /*core_x_iram0_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_2:    3;  /*core_x_iram0_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_3:    3;  /*core_x_iram0_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0:    3;  /*core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0*/
+            uint32_t reserved15                    :    3;
+            uint32_t reg_core_x_iram0_pms_constrain_rom_world_1_pms:    3;  /*core_x_iram0_pms_constrain_rom_world_1_pms*/
+            uint32_t reserved21                    :    11;
+        };
+        uint32_t val;
+    } core_x_iram0_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_0:    3;  /*core_x_iram0_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_1:    3;  /*core_x_iram0_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_2:    3;  /*core_x_iram0_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_3:    3;  /*core_x_iram0_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0:    3;  /*core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0*/
+            uint32_t reserved15                    :    3;
+            uint32_t reg_core_x_iram0_pms_constrain_rom_world_0_pms:    3;  /*core_x_iram0_pms_constrain_rom_world_0_pms*/
+            uint32_t reserved21                    :    11;
+        };
+        uint32_t val;
+    } core_x_iram0_pms_constrain_2;
+    union {
+        struct {
+            uint32_t reg_core_0_iram0_pms_monitor_lock:    1;  /*core_0_iram0_pms_monitor_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_0_iram0_pms_monitor_0;
+    union {
+        struct {
+            uint32_t reg_core_0_iram0_pms_monitor_violate_clr:    1;  /*core_0_iram0_pms_monitor_violate_clr*/
+            uint32_t reg_core_0_iram0_pms_monitor_violate_en:    1;  /*core_0_iram0_pms_monitor_violate_en*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } core_0_iram0_pms_monitor_1;
+    union {
+        struct {
+            uint32_t reg_core_0_iram0_pms_monitor_violate_intr:    1;  /*core_0_iram0_pms_monitor_violate_intr*/
+            uint32_t reg_core_0_iram0_pms_monitor_violate_status_wr:    1;  /*core_0_iram0_pms_monitor_violate_status_wr*/
+            uint32_t reg_core_0_iram0_pms_monitor_violate_status_loadstore:    1;  /*core_0_iram0_pms_monitor_violate_status_loadstore*/
+            uint32_t reg_core_0_iram0_pms_monitor_violate_status_world:    2;  /*core_0_iram0_pms_monitor_violate_status_world*/
+            uint32_t reg_core_0_iram0_pms_monitor_violate_status_addr:    24;  /*core_0_iram0_pms_monitor_violate_status_addr*/
+            uint32_t reserved29                    :    3;
+        };
+        uint32_t val;
+    } core_0_iram0_pms_monitor_2;
+    union {
+        struct {
+            uint32_t reg_core_x_dram0_pms_constrain_lock:    1;  /*core_x_dram0_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_x_dram0_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_0:    2;  /*core_x_dram0_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_1:    2;  /*core_x_dram0_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_2:    2;  /*core_x_dram0_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_3:    2;  /*core_x_dram0_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_0:    2;  /*core_x_dram0_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_1:    2;  /*core_x_dram0_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_2:    2;  /*core_x_dram0_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_3:    2;  /*core_x_dram0_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reg_core_x_dram0_pms_constrain_rom_world_0_pms:    2;  /*core_x_dram0_pms_constrain_rom_world_0_pms*/
+            uint32_t reg_core_x_dram0_pms_constrain_rom_world_1_pms:    2;  /*core_x_dram0_pms_constrain_rom_world_1_pms*/
+            uint32_t reserved28                    :    4;
+        };
+        uint32_t val;
+    } core_x_dram0_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_core_0_dram0_pms_monitor_lock:    1;  /*core_0_dram0_pms_monitor_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_0_dram0_pms_monitor_0;
+    union {
+        struct {
+            uint32_t reg_core_0_dram0_pms_monitor_violate_clr:    1;  /*core_0_dram0_pms_monitor_violate_clr*/
+            uint32_t reg_core_0_dram0_pms_monitor_violate_en:    1;  /*core_0_dram0_pms_monitor_violate_en*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } core_0_dram0_pms_monitor_1;
+    union {
+        struct {
+            uint32_t reg_core_0_dram0_pms_monitor_violate_intr:    1;  /*core_0_dram0_pms_monitor_violate_intr*/
+            uint32_t reg_core_0_dram0_pms_monitor_violate_status_lock:    1;  /*core_0_dram0_pms_monitor_violate_status_lock*/
+            uint32_t reg_core_0_dram0_pms_monitor_violate_status_world:    2;  /*core_0_dram0_pms_monitor_violate_status_world*/
+            uint32_t reg_core_0_dram0_pms_monitor_violate_status_addr:    24;  /*core_0_dram0_pms_monitor_violate_status_addr*/
+            uint32_t reserved28                    :    4;
+        };
+        uint32_t val;
+    } core_0_dram0_pms_monitor_2;
+    union {
+        struct {
+            uint32_t reg_core_0_dram0_pms_monitor_violate_status_wr:    1;  /*core_0_dram0_pms_monitor_violate_status_wr*/
+            uint32_t reg_core_0_dram0_pms_monitor_violate_status_byteen:    4;  /*core_0_dram0_pms_monitor_violate_status_byteen*/
+            uint32_t reserved5                     :    27;
+        };
+        uint32_t val;
+    } core_0_dram0_pms_monitor_3;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_constrain_lock:    1;  /*core_0_pif_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_constrain_world_0_uart:    2;  /*core_0_pif_pms_constrain_world_0_uart*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_g0spi_1:    2;  /*core_0_pif_pms_constrain_world_0_g0spi_1*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_g0spi_0:    2;  /*core_0_pif_pms_constrain_world_0_g0spi_0*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_gpio:    2;  /*core_0_pif_pms_constrain_world_0_gpio*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_fe2:    2;  /*core_0_pif_pms_constrain_world_0_fe2*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_fe:    2;  /*core_0_pif_pms_constrain_world_0_fe*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_timer:    2;  /*core_0_pif_pms_constrain_world_0_timer*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_rtc:    2;  /*core_0_pif_pms_constrain_world_0_rtc*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_io_mux:    2;  /*core_0_pif_pms_constrain_world_0_io_mux*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_wdg:    2;  /*core_0_pif_pms_constrain_world_0_wdg*/
+            uint32_t reserved20                    :    4;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_misc:    2;  /*core_0_pif_pms_constrain_world_0_misc*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_i2c:    2;  /*core_0_pif_pms_constrain_world_0_i2c*/
+            uint32_t reserved28                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_uart1:    2;  /*core_0_pif_pms_constrain_world_0_uart1*/
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_constrain_world_0_bt:    2;  /*core_0_pif_pms_constrain_world_0_bt*/
+            uint32_t reserved2                     :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_i2c_ext0:    2;  /*core_0_pif_pms_constrain_world_0_i2c_ext0*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_uhci0:    2;  /*core_0_pif_pms_constrain_world_0_uhci0*/
+            uint32_t reserved8                     :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_rmt:    2;  /*core_0_pif_pms_constrain_world_0_rmt*/
+            uint32_t reserved12                    :    4;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_ledc:    2;  /*core_0_pif_pms_constrain_world_0_ledc*/
+            uint32_t reserved18                    :    4;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_bb:    2;  /*core_0_pif_pms_constrain_world_0_bb*/
+            uint32_t reserved24                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup:    2;  /*core_0_pif_pms_constrain_world_0_timergroup*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup1:    2;  /*core_0_pif_pms_constrain_world_0_timergroup1*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_systimer:    2;  /*core_0_pif_pms_constrain_world_0_systimer*/
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_2;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_constrain_world_0_spi_2:    2;  /*core_0_pif_pms_constrain_world_0_spi_2*/
+            uint32_t reserved2                     :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_apb_ctrl:    2;  /*core_0_pif_pms_constrain_world_0_apb_ctrl*/
+            uint32_t reserved6                     :    4;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_can:    2;  /*core_0_pif_pms_constrain_world_0_can*/
+            uint32_t reserved12                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_i2s1:    2;  /*core_0_pif_pms_constrain_world_0_i2s1*/
+            uint32_t reserved16                    :    6;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_rwbt:    2;  /*core_0_pif_pms_constrain_world_0_rwbt*/
+            uint32_t reserved24                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_wifimac:    2;  /*core_0_pif_pms_constrain_world_0_wifimac*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_pwr:    2;  /*core_0_pif_pms_constrain_world_0_pwr*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_3;
+    union {
+        struct {
+            uint32_t reserved0                     :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_usb_wrap:    2;  /*core_0_pif_pms_constrain_world_0_usb_wrap*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_crypto_peri:    2;  /*core_0_pif_pms_constrain_world_0_crypto_peri*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_crypto_dma:    2;  /*core_0_pif_pms_constrain_world_0_crypto_dma*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_apb_adc:    2;  /*core_0_pif_pms_constrain_world_0_apb_adc*/
+            uint32_t reserved10                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_bt_pwr:    2;  /*core_0_pif_pms_constrain_world_0_bt_pwr*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_usb_device:    2;  /*core_0_pif_pms_constrain_world_0_usb_device*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_system:    2;  /*core_0_pif_pms_constrain_world_0_system*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_sensitive:    2;  /*core_0_pif_pms_constrain_world_0_sensitive*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_interrupt:    2;  /*core_0_pif_pms_constrain_world_0_interrupt*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_dma_copy:    2;  /*core_0_pif_pms_constrain_world_0_dma_copy*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_cache_config:    2;  /*core_0_pif_pms_constrain_world_0_cache_config*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_ad:    2;  /*core_0_pif_pms_constrain_world_0_ad*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_dio:    2;  /*core_0_pif_pms_constrain_world_0_dio*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_world_controller:    2;  /*core_0_pif_pms_constrain_world_0_world_controller*/
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_4;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_constrain_world_1_uart:    2;  /*core_0_pif_pms_constrain_world_1_uart*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_g0spi_1:    2;  /*core_0_pif_pms_constrain_world_1_g0spi_1*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_g0spi_0:    2;  /*core_0_pif_pms_constrain_world_1_g0spi_0*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_gpio:    2;  /*core_0_pif_pms_constrain_world_1_gpio*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_fe2:    2;  /*core_0_pif_pms_constrain_world_1_fe2*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_fe:    2;  /*core_0_pif_pms_constrain_world_1_fe*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_timer:    2;  /*core_0_pif_pms_constrain_world_1_timer*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_rtc:    2;  /*core_0_pif_pms_constrain_world_1_rtc*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_io_mux:    2;  /*core_0_pif_pms_constrain_world_1_io_mux*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_wdg:    2;  /*core_0_pif_pms_constrain_world_1_wdg*/
+            uint32_t reserved20                    :    4;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_misc:    2;  /*core_0_pif_pms_constrain_world_1_misc*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_i2c:    2;  /*core_0_pif_pms_constrain_world_1_i2c*/
+            uint32_t reserved28                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_uart1:    2;  /*core_0_pif_pms_constrain_world_1_uart1*/
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_5;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_constrain_world_1_bt:    2;  /*core_0_pif_pms_constrain_world_1_bt*/
+            uint32_t reserved2                     :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_i2c_ext0:    2;  /*core_0_pif_pms_constrain_world_1_i2c_ext0*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_uhci0:    2;  /*core_0_pif_pms_constrain_world_1_uhci0*/
+            uint32_t reserved8                     :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_rmt:    2;  /*core_0_pif_pms_constrain_world_1_rmt*/
+            uint32_t reserved12                    :    4;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_ledc:    2;  /*core_0_pif_pms_constrain_world_1_ledc*/
+            uint32_t reserved18                    :    4;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_bb:    2;  /*core_0_pif_pms_constrain_world_1_bb*/
+            uint32_t reserved24                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup:    2;  /*core_0_pif_pms_constrain_world_1_timergroup*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup1:    2;  /*core_0_pif_pms_constrain_world_1_timergroup1*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_systimer:    2;  /*core_0_pif_pms_constrain_world_1_systimer*/
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_6;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_constrain_world_1_spi_2:    2;  /*core_0_pif_pms_constrain_world_1_spi_2*/
+            uint32_t reserved2                     :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_apb_ctrl:    2;  /*core_0_pif_pms_constrain_world_1_apb_ctrl*/
+            uint32_t reserved6                     :    4;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_can:    2;  /*core_0_pif_pms_constrain_world_1_can*/
+            uint32_t reserved12                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_i2s1:    2;  /*core_0_pif_pms_constrain_world_1_i2s1*/
+            uint32_t reserved16                    :    6;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_rwbt:    2;  /*core_0_pif_pms_constrain_world_1_rwbt*/
+            uint32_t reserved24                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_wifimac:    2;  /*core_0_pif_pms_constrain_world_1_wifimac*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_pwr:    2;  /*core_0_pif_pms_constrain_world_1_pwr*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_7;
+    union {
+        struct {
+            uint32_t reserved0                     :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_usb_wrap:    2;  /*core_0_pif_pms_constrain_world_1_usb_wrap*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_crypto_peri:    2;  /*core_0_pif_pms_constrain_world_1_crypto_peri*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_crypto_dma:    2;  /*core_0_pif_pms_constrain_world_1_crypto_dma*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_apb_adc:    2;  /*core_0_pif_pms_constrain_world_1_apb_adc*/
+            uint32_t reserved10                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_bt_pwr:    2;  /*core_0_pif_pms_constrain_world_1_bt_pwr*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_usb_device:    2;  /*core_0_pif_pms_constrain_world_1_usb_device*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_system:    2;  /*core_0_pif_pms_constrain_world_1_system*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_sensitive:    2;  /*core_0_pif_pms_constrain_world_1_sensitive*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_interrupt:    2;  /*core_0_pif_pms_constrain_world_1_interrupt*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_dma_copy:    2;  /*core_0_pif_pms_constrain_world_1_dma_copy*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_cache_config:    2;  /*core_0_pif_pms_constrain_world_1_cache_config*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_ad:    2;  /*core_0_pif_pms_constrain_world_1_ad*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_dio:    2;  /*core_0_pif_pms_constrain_world_1_dio*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_world_controller:    2;  /*core_0_pif_pms_constrain_world_1_world_controller*/
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_8;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_constrain_rtcfast_spltaddr_world_0:    11;  /*core_0_pif_pms_constrain_rtcfast_spltaddr_world_0*/
+            uint32_t reg_core_0_pif_pms_constrain_rtcfast_spltaddr_world_1:    11;  /*core_0_pif_pms_constrain_rtcfast_spltaddr_world_1*/
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_9;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_0_l:    3;  /*core_0_pif_pms_constrain_rtcfast_world_0_l*/
+            uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_0_h:    3;  /*core_0_pif_pms_constrain_rtcfast_world_0_h*/
+            uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_1_l:    3;  /*core_0_pif_pms_constrain_rtcfast_world_1_l*/
+            uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_1_h:    3;  /*core_0_pif_pms_constrain_rtcfast_world_1_h*/
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_10;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_lock :    1;  /*region_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_world_0_area_0:    2;  /*region_pms_constrain_world_0_area_0*/
+            uint32_t reg_region_pms_constrain_world_0_area_1:    2;  /*region_pms_constrain_world_0_area_1*/
+            uint32_t reg_region_pms_constrain_world_0_area_2:    2;  /*region_pms_constrain_world_0_area_2*/
+            uint32_t reg_region_pms_constrain_world_0_area_3:    2;  /*region_pms_constrain_world_0_area_3*/
+            uint32_t reg_region_pms_constrain_world_0_area_4:    2;  /*region_pms_constrain_world_0_area_4*/
+            uint32_t reg_region_pms_constrain_world_0_area_5:    2;  /*region_pms_constrain_world_0_area_5*/
+            uint32_t reg_region_pms_constrain_world_0_area_6:    2;  /*region_pms_constrain_world_0_area_6*/
+            uint32_t reserved14                    :    18;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_world_1_area_0:    2;  /*region_pms_constrain_world_1_area_0*/
+            uint32_t reg_region_pms_constrain_world_1_area_1:    2;  /*region_pms_constrain_world_1_area_1*/
+            uint32_t reg_region_pms_constrain_world_1_area_2:    2;  /*region_pms_constrain_world_1_area_2*/
+            uint32_t reg_region_pms_constrain_world_1_area_3:    2;  /*region_pms_constrain_world_1_area_3*/
+            uint32_t reg_region_pms_constrain_world_1_area_4:    2;  /*region_pms_constrain_world_1_area_4*/
+            uint32_t reg_region_pms_constrain_world_1_area_5:    2;  /*region_pms_constrain_world_1_area_5*/
+            uint32_t reg_region_pms_constrain_world_1_area_6:    2;  /*region_pms_constrain_world_1_area_6*/
+            uint32_t reserved14                    :    18;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_2;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_addr_0:    30;  /*region_pms_constrain_addr_0*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_3;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_addr_1:    30;  /*region_pms_constrain_addr_1*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_4;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_addr_2:    30;  /*region_pms_constrain_addr_2*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_5;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_addr_3:    30;  /*region_pms_constrain_addr_3*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_6;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_addr_4:    30;  /*region_pms_constrain_addr_4*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_7;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_addr_5:    30;  /*region_pms_constrain_addr_5*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_8;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_addr_6:    30;  /*region_pms_constrain_addr_6*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_9;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_addr_7:    30;  /*region_pms_constrain_addr_7*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_10;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_monitor_lock:    1;  /*core_0_pif_pms_monitor_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_0_pif_pms_monitor_0;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_monitor_violate_clr:    1;  /*core_0_pif_pms_monitor_violate_clr*/
+            uint32_t reg_core_0_pif_pms_monitor_violate_en:    1;  /*core_0_pif_pms_monitor_violate_en*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } core_0_pif_pms_monitor_1;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_monitor_violate_intr:    1;  /*core_0_pif_pms_monitor_violate_intr*/
+            uint32_t reg_core_0_pif_pms_monitor_violate_status_hport_0:    1;  /*core_0_pif_pms_monitor_violate_status_hport_0*/
+            uint32_t reg_core_0_pif_pms_monitor_violate_status_hsize:    3;  /*core_0_pif_pms_monitor_violate_status_hsize*/
+            uint32_t reg_core_0_pif_pms_monitor_violate_status_hwrite:    1;  /*core_0_pif_pms_monitor_violate_status_hwrite*/
+            uint32_t reg_core_0_pif_pms_monitor_violate_status_hworld:    2;  /*core_0_pif_pms_monitor_violate_status_hworld*/
+            uint32_t reserved8                     :    24;
+        };
+        uint32_t val;
+    } core_0_pif_pms_monitor_2;
+    uint32_t core_0_pif_pms_monitor_3;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_monitor_nonword_violate_clr:    1;  /*core_0_pif_pms_monitor_nonword_violate_clr*/
+            uint32_t reg_core_0_pif_pms_monitor_nonword_violate_en:    1;  /*core_0_pif_pms_monitor_nonword_violate_en*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } core_0_pif_pms_monitor_4;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_monitor_nonword_violate_intr:    1;  /*core_0_pif_pms_monitor_nonword_violate_intr*/
+            uint32_t reg_core_0_pif_pms_monitor_nonword_violate_status_hsize:    2;  /*core_0_pif_pms_monitor_nonword_violate_status_hsize*/
+            uint32_t reg_core_0_pif_pms_monitor_nonword_violate_status_hworld:    2;  /*core_0_pif_pms_monitor_nonword_violate_status_hworld*/
+            uint32_t reserved5                     :    27;
+        };
+        uint32_t val;
+    } core_0_pif_pms_monitor_5;
+    uint32_t core_0_pif_pms_monitor_6;
+    union {
+        struct {
+            uint32_t reg_backup_bus_pms_constrain_lock:    1;  /*backup_bus_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } backup_bus_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_backup_bus_pms_constrain_uart:    2;  /*backup_bus_pms_constrain_uart*/
+            uint32_t reg_backup_bus_pms_constrain_g0spi_1:    2;  /*backup_bus_pms_constrain_g0spi_1*/
+            uint32_t reg_backup_bus_pms_constrain_g0spi_0:    2;  /*backup_bus_pms_constrain_g0spi_0*/
+            uint32_t reg_backup_bus_pms_constrain_gpio:    2;  /*backup_bus_pms_constrain_gpio*/
+            uint32_t reg_backup_bus_pms_constrain_fe2:    2;  /*backup_bus_pms_constrain_fe2*/
+            uint32_t reg_backup_bus_pms_constrain_fe:    2;  /*backup_bus_pms_constrain_fe*/
+            uint32_t reg_backup_bus_pms_constrain_timer:    2;  /*backup_bus_pms_constrain_timer*/
+            uint32_t reg_backup_bus_pms_constrain_rtc:    2;  /*backup_bus_pms_constrain_rtc*/
+            uint32_t reg_backup_bus_pms_constrain_io_mux:    2;  /*backup_bus_pms_constrain_io_mux*/
+            uint32_t reg_backup_bus_pms_constrain_wdg:    2;  /*backup_bus_pms_constrain_wdg*/
+            uint32_t reserved20                    :    4;
+            uint32_t reg_backup_bus_pms_constrain_misc:    2;  /*backup_bus_pms_constrain_misc*/
+            uint32_t reg_backup_bus_pms_constrain_i2c:    2;  /*backup_bus_pms_constrain_i2c*/
+            uint32_t reserved28                    :    2;
+            uint32_t reg_backup_bus_pms_constrain_uart1:    2;  /*backup_bus_pms_constrain_uart1*/
+        };
+        uint32_t val;
+    } backup_bus_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_backup_bus_pms_constrain_bt:    2;  /*backup_bus_pms_constrain_bt*/
+            uint32_t reserved2                     :    2;
+            uint32_t reg_backup_bus_pms_constrain_i2c_ext0:    2;  /*backup_bus_pms_constrain_i2c_ext0*/
+            uint32_t reg_backup_bus_pms_constrain_uhci0:    2;  /*backup_bus_pms_constrain_uhci0*/
+            uint32_t reserved8                     :    2;
+            uint32_t reg_backup_bus_pms_constrain_rmt:    2;  /*backup_bus_pms_constrain_rmt*/
+            uint32_t reserved12                    :    4;
+            uint32_t reg_backup_bus_pms_constrain_ledc:    2;  /*backup_bus_pms_constrain_ledc*/
+            uint32_t reserved18                    :    4;
+            uint32_t reg_backup_bus_pms_constrain_bb:    2;  /*backup_bus_pms_constrain_bb*/
+            uint32_t reserved24                    :    2;
+            uint32_t reg_backup_bus_pms_constrain_timergroup:    2;  /*backup_bus_pms_constrain_timergroup*/
+            uint32_t reg_backup_bus_pms_constrain_timergroup1:    2;  /*backup_bus_pms_constrain_timergroup1*/
+            uint32_t reg_backup_bus_pms_constrain_systimer:    2;  /*backup_bus_pms_constrain_systimer*/
+        };
+        uint32_t val;
+    } backup_bus_pms_constrain_2;
+    union {
+        struct {
+            uint32_t reg_backup_bus_pms_constrain_spi_2:    2;  /*backup_bus_pms_constrain_spi_2*/
+            uint32_t reserved2                     :    2;
+            uint32_t reg_backup_bus_pms_constrain_apb_ctrl:    2;  /*backup_bus_pms_constrain_apb_ctrl*/
+            uint32_t reserved6                     :    4;
+            uint32_t reg_backup_bus_pms_constrain_can:    2;  /*backup_bus_pms_constrain_can*/
+            uint32_t reserved12                    :    2;
+            uint32_t reg_backup_bus_pms_constrain_i2s1:    2;  /*backup_bus_pms_constrain_i2s1*/
+            uint32_t reserved16                    :    6;
+            uint32_t reg_backup_bus_pms_constrain_rwbt:    2;  /*backup_bus_pms_constrain_rwbt*/
+            uint32_t reserved24                    :    2;
+            uint32_t reg_backup_bus_pms_constrain_wifimac:    2;  /*backup_bus_pms_constrain_wifimac*/
+            uint32_t reg_backup_bus_pms_constrain_pwr:    2;  /*backup_bus_pms_constrain_pwr*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } backup_bus_pms_constrain_3;
+    union {
+        struct {
+            uint32_t reserved0                     :    2;
+            uint32_t reg_backup_bus_pms_constrain_usb_wrap:    2;  /*backup_bus_pms_constrain_usb_wrap*/
+            uint32_t reg_backup_bus_pms_constrain_crypto_peri:    2;  /*backup_bus_pms_constrain_crypto_peri*/
+            uint32_t reg_backup_bus_pms_constrain_crypto_dma:    2;  /*backup_bus_pms_constrain_crypto_dma*/
+            uint32_t reg_backup_bus_pms_constrain_apb_adc:    2;  /*backup_bus_pms_constrain_apb_adc*/
+            uint32_t reserved10                    :    2;
+            uint32_t reg_backup_bus_pms_constrain_bt_pwr:    2;  /*backup_bus_pms_constrain_bt_pwr*/
+            uint32_t reg_backup_bus_pms_constrain_usb_device:    2;  /*backup_bus_pms_constrain_usb_device*/
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } backup_bus_pms_constrain_4;
+    union {
+        struct {
+            uint32_t reg_backup_bus_pms_monitor_lock:    1;  /*backup_bus_pms_monitor_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } backup_bus_pms_monitor_0;
+    union {
+        struct {
+            uint32_t reg_backup_bus_pms_monitor_violate_clr:    1;  /*backup_bus_pms_monitor_violate_clr*/
+            uint32_t reg_backup_bus_pms_monitor_violate_en:    1;  /*backup_bus_pms_monitor_violate_en*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } backup_bus_pms_monitor_1;
+    union {
+        struct {
+            uint32_t reg_backup_bus_pms_monitor_violate_intr:    1;  /*backup_bus_pms_monitor_violate_intr*/
+            uint32_t reg_backup_bus_pms_monitor_violate_status_htrans:    2;  /*backup_bus_pms_monitor_violate_status_htrans*/
+            uint32_t reg_backup_bus_pms_monitor_violate_status_hsize:    3;  /*backup_bus_pms_monitor_violate_status_hsize*/
+            uint32_t reg_backup_bus_pms_monitor_violate_status_hwrite:    1;  /*backup_bus_pms_monitor_violate_status_hwrite*/
+            uint32_t reserved7                     :    25;
+        };
+        uint32_t val;
+    } backup_bus_pms_monitor_2;
+    uint32_t backup_bus_pms_monitor_3;
+    union {
+        struct {
+            uint32_t reg_clk_en                    :    1;  /*clk_en*/
+            uint32_t reserved1                     :    31;
+            uint32_t reservedNone                  :    None;  /*SENSITIVE_CLOCK_GATE_REG_REG*/
+        };
+        uint32_t val;
+    } clock_gate;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    uint32_t reserved_3fc;
+    uint32_t reserved_400;
+    uint32_t reserved_404;
+    uint32_t reserved_408;
+    uint32_t reserved_40c;
+    uint32_t reserved_410;
+    uint32_t reserved_414;
+    uint32_t reserved_418;
+    uint32_t reserved_41c;
+    uint32_t reserved_420;
+    uint32_t reserved_424;
+    uint32_t reserved_428;
+    uint32_t reserved_42c;
+    uint32_t reserved_430;
+    uint32_t reserved_434;
+    uint32_t reserved_438;
+    uint32_t reserved_43c;
+    uint32_t reserved_440;
+    uint32_t reserved_444;
+    uint32_t reserved_448;
+    uint32_t reserved_44c;
+    uint32_t reserved_450;
+    uint32_t reserved_454;
+    uint32_t reserved_458;
+    uint32_t reserved_45c;
+    uint32_t reserved_460;
+    uint32_t reserved_464;
+    uint32_t reserved_468;
+    uint32_t reserved_46c;
+    uint32_t reserved_470;
+    uint32_t reserved_474;
+    uint32_t reserved_478;
+    uint32_t reserved_47c;
+    uint32_t reserved_480;
+    uint32_t reserved_484;
+    uint32_t reserved_488;
+    uint32_t reserved_48c;
+    uint32_t reserved_490;
+    uint32_t reserved_494;
+    uint32_t reserved_498;
+    uint32_t reserved_49c;
+    uint32_t reserved_4a0;
+    uint32_t reserved_4a4;
+    uint32_t reserved_4a8;
+    uint32_t reserved_4ac;
+    uint32_t reserved_4b0;
+    uint32_t reserved_4b4;
+    uint32_t reserved_4b8;
+    uint32_t reserved_4bc;
+    uint32_t reserved_4c0;
+    uint32_t reserved_4c4;
+    uint32_t reserved_4c8;
+    uint32_t reserved_4cc;
+    uint32_t reserved_4d0;
+    uint32_t reserved_4d4;
+    uint32_t reserved_4d8;
+    uint32_t reserved_4dc;
+    uint32_t reserved_4e0;
+    uint32_t reserved_4e4;
+    uint32_t reserved_4e8;
+    uint32_t reserved_4ec;
+    uint32_t reserved_4f0;
+    uint32_t reserved_4f4;
+    uint32_t reserved_4f8;
+    uint32_t reserved_4fc;
+    uint32_t reserved_500;
+    uint32_t reserved_504;
+    uint32_t reserved_508;
+    uint32_t reserved_50c;
+    uint32_t reserved_510;
+    uint32_t reserved_514;
+    uint32_t reserved_518;
+    uint32_t reserved_51c;
+    uint32_t reserved_520;
+    uint32_t reserved_524;
+    uint32_t reserved_528;
+    uint32_t reserved_52c;
+    uint32_t reserved_530;
+    uint32_t reserved_534;
+    uint32_t reserved_538;
+    uint32_t reserved_53c;
+    uint32_t reserved_540;
+    uint32_t reserved_544;
+    uint32_t reserved_548;
+    uint32_t reserved_54c;
+    uint32_t reserved_550;
+    uint32_t reserved_554;
+    uint32_t reserved_558;
+    uint32_t reserved_55c;
+    uint32_t reserved_560;
+    uint32_t reserved_564;
+    uint32_t reserved_568;
+    uint32_t reserved_56c;
+    uint32_t reserved_570;
+    uint32_t reserved_574;
+    uint32_t reserved_578;
+    uint32_t reserved_57c;
+    uint32_t reserved_580;
+    uint32_t reserved_584;
+    uint32_t reserved_588;
+    uint32_t reserved_58c;
+    uint32_t reserved_590;
+    uint32_t reserved_594;
+    uint32_t reserved_598;
+    uint32_t reserved_59c;
+    uint32_t reserved_5a0;
+    uint32_t reserved_5a4;
+    uint32_t reserved_5a8;
+    uint32_t reserved_5ac;
+    uint32_t reserved_5b0;
+    uint32_t reserved_5b4;
+    uint32_t reserved_5b8;
+    uint32_t reserved_5bc;
+    uint32_t reserved_5c0;
+    uint32_t reserved_5c4;
+    uint32_t reserved_5c8;
+    uint32_t reserved_5cc;
+    uint32_t reserved_5d0;
+    uint32_t reserved_5d4;
+    uint32_t reserved_5d8;
+    uint32_t reserved_5dc;
+    uint32_t reserved_5e0;
+    uint32_t reserved_5e4;
+    uint32_t reserved_5e8;
+    uint32_t reserved_5ec;
+    uint32_t reserved_5f0;
+    uint32_t reserved_5f4;
+    uint32_t reserved_5f8;
+    uint32_t reserved_5fc;
+    uint32_t reserved_600;
+    uint32_t reserved_604;
+    uint32_t reserved_608;
+    uint32_t reserved_60c;
+    uint32_t reserved_610;
+    uint32_t reserved_614;
+    uint32_t reserved_618;
+    uint32_t reserved_61c;
+    uint32_t reserved_620;
+    uint32_t reserved_624;
+    uint32_t reserved_628;
+    uint32_t reserved_62c;
+    uint32_t reserved_630;
+    uint32_t reserved_634;
+    uint32_t reserved_638;
+    uint32_t reserved_63c;
+    uint32_t reserved_640;
+    uint32_t reserved_644;
+    uint32_t reserved_648;
+    uint32_t reserved_64c;
+    uint32_t reserved_650;
+    uint32_t reserved_654;
+    uint32_t reserved_658;
+    uint32_t reserved_65c;
+    uint32_t reserved_660;
+    uint32_t reserved_664;
+    uint32_t reserved_668;
+    uint32_t reserved_66c;
+    uint32_t reserved_670;
+    uint32_t reserved_674;
+    uint32_t reserved_678;
+    uint32_t reserved_67c;
+    uint32_t reserved_680;
+    uint32_t reserved_684;
+    uint32_t reserved_688;
+    uint32_t reserved_68c;
+    uint32_t reserved_690;
+    uint32_t reserved_694;
+    uint32_t reserved_698;
+    uint32_t reserved_69c;
+    uint32_t reserved_6a0;
+    uint32_t reserved_6a4;
+    uint32_t reserved_6a8;
+    uint32_t reserved_6ac;
+    uint32_t reserved_6b0;
+    uint32_t reserved_6b4;
+    uint32_t reserved_6b8;
+    uint32_t reserved_6bc;
+    uint32_t reserved_6c0;
+    uint32_t reserved_6c4;
+    uint32_t reserved_6c8;
+    uint32_t reserved_6cc;
+    uint32_t reserved_6d0;
+    uint32_t reserved_6d4;
+    uint32_t reserved_6d8;
+    uint32_t reserved_6dc;
+    uint32_t reserved_6e0;
+    uint32_t reserved_6e4;
+    uint32_t reserved_6e8;
+    uint32_t reserved_6ec;
+    uint32_t reserved_6f0;
+    uint32_t reserved_6f4;
+    uint32_t reserved_6f8;
+    uint32_t reserved_6fc;
+    uint32_t reserved_700;
+    uint32_t reserved_704;
+    uint32_t reserved_708;
+    uint32_t reserved_70c;
+    uint32_t reserved_710;
+    uint32_t reserved_714;
+    uint32_t reserved_718;
+    uint32_t reserved_71c;
+    uint32_t reserved_720;
+    uint32_t reserved_724;
+    uint32_t reserved_728;
+    uint32_t reserved_72c;
+    uint32_t reserved_730;
+    uint32_t reserved_734;
+    uint32_t reserved_738;
+    uint32_t reserved_73c;
+    uint32_t reserved_740;
+    uint32_t reserved_744;
+    uint32_t reserved_748;
+    uint32_t reserved_74c;
+    uint32_t reserved_750;
+    uint32_t reserved_754;
+    uint32_t reserved_758;
+    uint32_t reserved_75c;
+    uint32_t reserved_760;
+    uint32_t reserved_764;
+    uint32_t reserved_768;
+    uint32_t reserved_76c;
+    uint32_t reserved_770;
+    uint32_t reserved_774;
+    uint32_t reserved_778;
+    uint32_t reserved_77c;
+    uint32_t reserved_780;
+    uint32_t reserved_784;
+    uint32_t reserved_788;
+    uint32_t reserved_78c;
+    uint32_t reserved_790;
+    uint32_t reserved_794;
+    uint32_t reserved_798;
+    uint32_t reserved_79c;
+    uint32_t reserved_7a0;
+    uint32_t reserved_7a4;
+    uint32_t reserved_7a8;
+    uint32_t reserved_7ac;
+    uint32_t reserved_7b0;
+    uint32_t reserved_7b4;
+    uint32_t reserved_7b8;
+    uint32_t reserved_7bc;
+    uint32_t reserved_7c0;
+    uint32_t reserved_7c4;
+    uint32_t reserved_7c8;
+    uint32_t reserved_7cc;
+    uint32_t reserved_7d0;
+    uint32_t reserved_7d4;
+    uint32_t reserved_7d8;
+    uint32_t reserved_7dc;
+    uint32_t reserved_7e0;
+    uint32_t reserved_7e4;
+    uint32_t reserved_7e8;
+    uint32_t reserved_7ec;
+    uint32_t reserved_7f0;
+    uint32_t reserved_7f4;
+    uint32_t reserved_7f8;
+    uint32_t reserved_7fc;
+    uint32_t reserved_800;
+    uint32_t reserved_804;
+    uint32_t reserved_808;
+    uint32_t reserved_80c;
+    uint32_t reserved_810;
+    uint32_t reserved_814;
+    uint32_t reserved_818;
+    uint32_t reserved_81c;
+    uint32_t reserved_820;
+    uint32_t reserved_824;
+    uint32_t reserved_828;
+    uint32_t reserved_82c;
+    uint32_t reserved_830;
+    uint32_t reserved_834;
+    uint32_t reserved_838;
+    uint32_t reserved_83c;
+    uint32_t reserved_840;
+    uint32_t reserved_844;
+    uint32_t reserved_848;
+    uint32_t reserved_84c;
+    uint32_t reserved_850;
+    uint32_t reserved_854;
+    uint32_t reserved_858;
+    uint32_t reserved_85c;
+    uint32_t reserved_860;
+    uint32_t reserved_864;
+    uint32_t reserved_868;
+    uint32_t reserved_86c;
+    uint32_t reserved_870;
+    uint32_t reserved_874;
+    uint32_t reserved_878;
+    uint32_t reserved_87c;
+    uint32_t reserved_880;
+    uint32_t reserved_884;
+    uint32_t reserved_888;
+    uint32_t reserved_88c;
+    uint32_t reserved_890;
+    uint32_t reserved_894;
+    uint32_t reserved_898;
+    uint32_t reserved_89c;
+    uint32_t reserved_8a0;
+    uint32_t reserved_8a4;
+    uint32_t reserved_8a8;
+    uint32_t reserved_8ac;
+    uint32_t reserved_8b0;
+    uint32_t reserved_8b4;
+    uint32_t reserved_8b8;
+    uint32_t reserved_8bc;
+    uint32_t reserved_8c0;
+    uint32_t reserved_8c4;
+    uint32_t reserved_8c8;
+    uint32_t reserved_8cc;
+    uint32_t reserved_8d0;
+    uint32_t reserved_8d4;
+    uint32_t reserved_8d8;
+    uint32_t reserved_8dc;
+    uint32_t reserved_8e0;
+    uint32_t reserved_8e4;
+    uint32_t reserved_8e8;
+    uint32_t reserved_8ec;
+    uint32_t reserved_8f0;
+    uint32_t reserved_8f4;
+    uint32_t reserved_8f8;
+    uint32_t reserved_8fc;
+    uint32_t reserved_900;
+    uint32_t reserved_904;
+    uint32_t reserved_908;
+    uint32_t reserved_90c;
+    uint32_t reserved_910;
+    uint32_t reserved_914;
+    uint32_t reserved_918;
+    uint32_t reserved_91c;
+    uint32_t reserved_920;
+    uint32_t reserved_924;
+    uint32_t reserved_928;
+    uint32_t reserved_92c;
+    uint32_t reserved_930;
+    uint32_t reserved_934;
+    uint32_t reserved_938;
+    uint32_t reserved_93c;
+    uint32_t reserved_940;
+    uint32_t reserved_944;
+    uint32_t reserved_948;
+    uint32_t reserved_94c;
+    uint32_t reserved_950;
+    uint32_t reserved_954;
+    uint32_t reserved_958;
+    uint32_t reserved_95c;
+    uint32_t reserved_960;
+    uint32_t reserved_964;
+    uint32_t reserved_968;
+    uint32_t reserved_96c;
+    uint32_t reserved_970;
+    uint32_t reserved_974;
+    uint32_t reserved_978;
+    uint32_t reserved_97c;
+    uint32_t reserved_980;
+    uint32_t reserved_984;
+    uint32_t reserved_988;
+    uint32_t reserved_98c;
+    uint32_t reserved_990;
+    uint32_t reserved_994;
+    uint32_t reserved_998;
+    uint32_t reserved_99c;
+    uint32_t reserved_9a0;
+    uint32_t reserved_9a4;
+    uint32_t reserved_9a8;
+    uint32_t reserved_9ac;
+    uint32_t reserved_9b0;
+    uint32_t reserved_9b4;
+    uint32_t reserved_9b8;
+    uint32_t reserved_9bc;
+    uint32_t reserved_9c0;
+    uint32_t reserved_9c4;
+    uint32_t reserved_9c8;
+    uint32_t reserved_9cc;
+    uint32_t reserved_9d0;
+    uint32_t reserved_9d4;
+    uint32_t reserved_9d8;
+    uint32_t reserved_9dc;
+    uint32_t reserved_9e0;
+    uint32_t reserved_9e4;
+    uint32_t reserved_9e8;
+    uint32_t reserved_9ec;
+    uint32_t reserved_9f0;
+    uint32_t reserved_9f4;
+    uint32_t reserved_9f8;
+    uint32_t reserved_9fc;
+    uint32_t reserved_a00;
+    uint32_t reserved_a04;
+    uint32_t reserved_a08;
+    uint32_t reserved_a0c;
+    uint32_t reserved_a10;
+    uint32_t reserved_a14;
+    uint32_t reserved_a18;
+    uint32_t reserved_a1c;
+    uint32_t reserved_a20;
+    uint32_t reserved_a24;
+    uint32_t reserved_a28;
+    uint32_t reserved_a2c;
+    uint32_t reserved_a30;
+    uint32_t reserved_a34;
+    uint32_t reserved_a38;
+    uint32_t reserved_a3c;
+    uint32_t reserved_a40;
+    uint32_t reserved_a44;
+    uint32_t reserved_a48;
+    uint32_t reserved_a4c;
+    uint32_t reserved_a50;
+    uint32_t reserved_a54;
+    uint32_t reserved_a58;
+    uint32_t reserved_a5c;
+    uint32_t reserved_a60;
+    uint32_t reserved_a64;
+    uint32_t reserved_a68;
+    uint32_t reserved_a6c;
+    uint32_t reserved_a70;
+    uint32_t reserved_a74;
+    uint32_t reserved_a78;
+    uint32_t reserved_a7c;
+    uint32_t reserved_a80;
+    uint32_t reserved_a84;
+    uint32_t reserved_a88;
+    uint32_t reserved_a8c;
+    uint32_t reserved_a90;
+    uint32_t reserved_a94;
+    uint32_t reserved_a98;
+    uint32_t reserved_a9c;
+    uint32_t reserved_aa0;
+    uint32_t reserved_aa4;
+    uint32_t reserved_aa8;
+    uint32_t reserved_aac;
+    uint32_t reserved_ab0;
+    uint32_t reserved_ab4;
+    uint32_t reserved_ab8;
+    uint32_t reserved_abc;
+    uint32_t reserved_ac0;
+    uint32_t reserved_ac4;
+    uint32_t reserved_ac8;
+    uint32_t reserved_acc;
+    uint32_t reserved_ad0;
+    uint32_t reserved_ad4;
+    uint32_t reserved_ad8;
+    uint32_t reserved_adc;
+    uint32_t reserved_ae0;
+    uint32_t reserved_ae4;
+    uint32_t reserved_ae8;
+    uint32_t reserved_aec;
+    uint32_t reserved_af0;
+    uint32_t reserved_af4;
+    uint32_t reserved_af8;
+    uint32_t reserved_afc;
+    uint32_t reserved_b00;
+    uint32_t reserved_b04;
+    uint32_t reserved_b08;
+    uint32_t reserved_b0c;
+    uint32_t reserved_b10;
+    uint32_t reserved_b14;
+    uint32_t reserved_b18;
+    uint32_t reserved_b1c;
+    uint32_t reserved_b20;
+    uint32_t reserved_b24;
+    uint32_t reserved_b28;
+    uint32_t reserved_b2c;
+    uint32_t reserved_b30;
+    uint32_t reserved_b34;
+    uint32_t reserved_b38;
+    uint32_t reserved_b3c;
+    uint32_t reserved_b40;
+    uint32_t reserved_b44;
+    uint32_t reserved_b48;
+    uint32_t reserved_b4c;
+    uint32_t reserved_b50;
+    uint32_t reserved_b54;
+    uint32_t reserved_b58;
+    uint32_t reserved_b5c;
+    uint32_t reserved_b60;
+    uint32_t reserved_b64;
+    uint32_t reserved_b68;
+    uint32_t reserved_b6c;
+    uint32_t reserved_b70;
+    uint32_t reserved_b74;
+    uint32_t reserved_b78;
+    uint32_t reserved_b7c;
+    uint32_t reserved_b80;
+    uint32_t reserved_b84;
+    uint32_t reserved_b88;
+    uint32_t reserved_b8c;
+    uint32_t reserved_b90;
+    uint32_t reserved_b94;
+    uint32_t reserved_b98;
+    uint32_t reserved_b9c;
+    uint32_t reserved_ba0;
+    uint32_t reserved_ba4;
+    uint32_t reserved_ba8;
+    uint32_t reserved_bac;
+    uint32_t reserved_bb0;
+    uint32_t reserved_bb4;
+    uint32_t reserved_bb8;
+    uint32_t reserved_bbc;
+    uint32_t reserved_bc0;
+    uint32_t reserved_bc4;
+    uint32_t reserved_bc8;
+    uint32_t reserved_bcc;
+    uint32_t reserved_bd0;
+    uint32_t reserved_bd4;
+    uint32_t reserved_bd8;
+    uint32_t reserved_bdc;
+    uint32_t reserved_be0;
+    uint32_t reserved_be4;
+    uint32_t reserved_be8;
+    uint32_t reserved_bec;
+    uint32_t reserved_bf0;
+    uint32_t reserved_bf4;
+    uint32_t reserved_bf8;
+    uint32_t reserved_bfc;
+    uint32_t reserved_c00;
+    uint32_t reserved_c04;
+    uint32_t reserved_c08;
+    uint32_t reserved_c0c;
+    uint32_t reserved_c10;
+    uint32_t reserved_c14;
+    uint32_t reserved_c18;
+    uint32_t reserved_c1c;
+    uint32_t reserved_c20;
+    uint32_t reserved_c24;
+    uint32_t reserved_c28;
+    uint32_t reserved_c2c;
+    uint32_t reserved_c30;
+    uint32_t reserved_c34;
+    uint32_t reserved_c38;
+    uint32_t reserved_c3c;
+    uint32_t reserved_c40;
+    uint32_t reserved_c44;
+    uint32_t reserved_c48;
+    uint32_t reserved_c4c;
+    uint32_t reserved_c50;
+    uint32_t reserved_c54;
+    uint32_t reserved_c58;
+    uint32_t reserved_c5c;
+    uint32_t reserved_c60;
+    uint32_t reserved_c64;
+    uint32_t reserved_c68;
+    uint32_t reserved_c6c;
+    uint32_t reserved_c70;
+    uint32_t reserved_c74;
+    uint32_t reserved_c78;
+    uint32_t reserved_c7c;
+    uint32_t reserved_c80;
+    uint32_t reserved_c84;
+    uint32_t reserved_c88;
+    uint32_t reserved_c8c;
+    uint32_t reserved_c90;
+    uint32_t reserved_c94;
+    uint32_t reserved_c98;
+    uint32_t reserved_c9c;
+    uint32_t reserved_ca0;
+    uint32_t reserved_ca4;
+    uint32_t reserved_ca8;
+    uint32_t reserved_cac;
+    uint32_t reserved_cb0;
+    uint32_t reserved_cb4;
+    uint32_t reserved_cb8;
+    uint32_t reserved_cbc;
+    uint32_t reserved_cc0;
+    uint32_t reserved_cc4;
+    uint32_t reserved_cc8;
+    uint32_t reserved_ccc;
+    uint32_t reserved_cd0;
+    uint32_t reserved_cd4;
+    uint32_t reserved_cd8;
+    uint32_t reserved_cdc;
+    uint32_t reserved_ce0;
+    uint32_t reserved_ce4;
+    uint32_t reserved_ce8;
+    uint32_t reserved_cec;
+    uint32_t reserved_cf0;
+    uint32_t reserved_cf4;
+    uint32_t reserved_cf8;
+    uint32_t reserved_cfc;
+    uint32_t reserved_d00;
+    uint32_t reserved_d04;
+    uint32_t reserved_d08;
+    uint32_t reserved_d0c;
+    uint32_t reserved_d10;
+    uint32_t reserved_d14;
+    uint32_t reserved_d18;
+    uint32_t reserved_d1c;
+    uint32_t reserved_d20;
+    uint32_t reserved_d24;
+    uint32_t reserved_d28;
+    uint32_t reserved_d2c;
+    uint32_t reserved_d30;
+    uint32_t reserved_d34;
+    uint32_t reserved_d38;
+    uint32_t reserved_d3c;
+    uint32_t reserved_d40;
+    uint32_t reserved_d44;
+    uint32_t reserved_d48;
+    uint32_t reserved_d4c;
+    uint32_t reserved_d50;
+    uint32_t reserved_d54;
+    uint32_t reserved_d58;
+    uint32_t reserved_d5c;
+    uint32_t reserved_d60;
+    uint32_t reserved_d64;
+    uint32_t reserved_d68;
+    uint32_t reserved_d6c;
+    uint32_t reserved_d70;
+    uint32_t reserved_d74;
+    uint32_t reserved_d78;
+    uint32_t reserved_d7c;
+    uint32_t reserved_d80;
+    uint32_t reserved_d84;
+    uint32_t reserved_d88;
+    uint32_t reserved_d8c;
+    uint32_t reserved_d90;
+    uint32_t reserved_d94;
+    uint32_t reserved_d98;
+    uint32_t reserved_d9c;
+    uint32_t reserved_da0;
+    uint32_t reserved_da4;
+    uint32_t reserved_da8;
+    uint32_t reserved_dac;
+    uint32_t reserved_db0;
+    uint32_t reserved_db4;
+    uint32_t reserved_db8;
+    uint32_t reserved_dbc;
+    uint32_t reserved_dc0;
+    uint32_t reserved_dc4;
+    uint32_t reserved_dc8;
+    uint32_t reserved_dcc;
+    uint32_t reserved_dd0;
+    uint32_t reserved_dd4;
+    uint32_t reserved_dd8;
+    uint32_t reserved_ddc;
+    uint32_t reserved_de0;
+    uint32_t reserved_de4;
+    uint32_t reserved_de8;
+    uint32_t reserved_dec;
+    uint32_t reserved_df0;
+    uint32_t reserved_df4;
+    uint32_t reserved_df8;
+    uint32_t reserved_dfc;
+    uint32_t reserved_e00;
+    uint32_t reserved_e04;
+    uint32_t reserved_e08;
+    uint32_t reserved_e0c;
+    uint32_t reserved_e10;
+    uint32_t reserved_e14;
+    uint32_t reserved_e18;
+    uint32_t reserved_e1c;
+    uint32_t reserved_e20;
+    uint32_t reserved_e24;
+    uint32_t reserved_e28;
+    uint32_t reserved_e2c;
+    uint32_t reserved_e30;
+    uint32_t reserved_e34;
+    uint32_t reserved_e38;
+    uint32_t reserved_e3c;
+    uint32_t reserved_e40;
+    uint32_t reserved_e44;
+    uint32_t reserved_e48;
+    uint32_t reserved_e4c;
+    uint32_t reserved_e50;
+    uint32_t reserved_e54;
+    uint32_t reserved_e58;
+    uint32_t reserved_e5c;
+    uint32_t reserved_e60;
+    uint32_t reserved_e64;
+    uint32_t reserved_e68;
+    uint32_t reserved_e6c;
+    uint32_t reserved_e70;
+    uint32_t reserved_e74;
+    uint32_t reserved_e78;
+    uint32_t reserved_e7c;
+    uint32_t reserved_e80;
+    uint32_t reserved_e84;
+    uint32_t reserved_e88;
+    uint32_t reserved_e8c;
+    uint32_t reserved_e90;
+    uint32_t reserved_e94;
+    uint32_t reserved_e98;
+    uint32_t reserved_e9c;
+    uint32_t reserved_ea0;
+    uint32_t reserved_ea4;
+    uint32_t reserved_ea8;
+    uint32_t reserved_eac;
+    uint32_t reserved_eb0;
+    uint32_t reserved_eb4;
+    uint32_t reserved_eb8;
+    uint32_t reserved_ebc;
+    uint32_t reserved_ec0;
+    uint32_t reserved_ec4;
+    uint32_t reserved_ec8;
+    uint32_t reserved_ecc;
+    uint32_t reserved_ed0;
+    uint32_t reserved_ed4;
+    uint32_t reserved_ed8;
+    uint32_t reserved_edc;
+    uint32_t reserved_ee0;
+    uint32_t reserved_ee4;
+    uint32_t reserved_ee8;
+    uint32_t reserved_eec;
+    uint32_t reserved_ef0;
+    uint32_t reserved_ef4;
+    uint32_t reserved_ef8;
+    uint32_t reserved_efc;
+    uint32_t reserved_f00;
+    uint32_t reserved_f04;
+    uint32_t reserved_f08;
+    uint32_t reserved_f0c;
+    uint32_t reserved_f10;
+    uint32_t reserved_f14;
+    uint32_t reserved_f18;
+    uint32_t reserved_f1c;
+    uint32_t reserved_f20;
+    uint32_t reserved_f24;
+    uint32_t reserved_f28;
+    uint32_t reserved_f2c;
+    uint32_t reserved_f30;
+    uint32_t reserved_f34;
+    uint32_t reserved_f38;
+    uint32_t reserved_f3c;
+    uint32_t reserved_f40;
+    uint32_t reserved_f44;
+    uint32_t reserved_f48;
+    uint32_t reserved_f4c;
+    uint32_t reserved_f50;
+    uint32_t reserved_f54;
+    uint32_t reserved_f58;
+    uint32_t reserved_f5c;
+    uint32_t reserved_f60;
+    uint32_t reserved_f64;
+    uint32_t reserved_f68;
+    uint32_t reserved_f6c;
+    uint32_t reserved_f70;
+    uint32_t reserved_f74;
+    uint32_t reserved_f78;
+    uint32_t reserved_f7c;
+    uint32_t reserved_f80;
+    uint32_t reserved_f84;
+    uint32_t reserved_f88;
+    uint32_t reserved_f8c;
+    uint32_t reserved_f90;
+    uint32_t reserved_f94;
+    uint32_t reserved_f98;
+    uint32_t reserved_f9c;
+    uint32_t reserved_fa0;
+    uint32_t reserved_fa4;
+    uint32_t reserved_fa8;
+    uint32_t reserved_fac;
+    uint32_t reserved_fb0;
+    uint32_t reserved_fb4;
+    uint32_t reserved_fb8;
+    uint32_t reserved_fbc;
+    uint32_t reserved_fc0;
+    uint32_t reserved_fc4;
+    uint32_t reserved_fc8;
+    uint32_t reserved_fcc;
+    uint32_t reserved_fd0;
+    uint32_t reserved_fd4;
+    uint32_t reserved_fd8;
+    uint32_t reserved_fdc;
+    uint32_t reserved_fe0;
+    uint32_t reserved_fe4;
+    uint32_t reserved_fe8;
+    uint32_t reserved_fec;
+    uint32_t reserved_ff0;
+    uint32_t reserved_ff4;
+    uint32_t reserved_ff8;
+    union {
+        struct {
+            uint32_t reg_date                      :    28;  /*reg_date*/
+            uint32_t reserved28                    :    4;
+        };
+        uint32_t val;
+    } date;
+} sensitive_dev_t;
+extern sensitive_dev_t SENSITIVE;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SENSITIVE_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/sha_caps.h b/components/soc/esp32c3/include/soc/sha_caps.h
new file mode 100644
index 0000000000..5b59c7c453
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/sha_caps.h
@@ -0,0 +1,54 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Max amount of bytes in a single DMA operation is 4095,
+   for SHA this means that the biggest safe amount of bytes is
+   31 blocks of 128 bytes = 3968
+*/
+#define SOC_SHA_DMA_MAX_BUFFER_SIZE     (3968)
+#define SOC_SHA_SUPPORT_DMA             (1)
+
+/* ESP32 style SHA engine, where multiple states can be stored in parallel */
+#define SOC_SHA_SUPPORT_PARALLEL_ENG    (0)
+
+/* The SHA engine is able to resume hashing from a user */
+#define SOC_SHA_SUPPORT_RESUME          (1)
+
+/* Has "crypto DMA", which is shared with AES */
+#define SOC_SHA_CRYPTO_DMA              (0)
+
+/* Has a centralized DMA, which is shared with all peripherals */
+#define SOC_SHA_GENERAL_DMA             (1)
+
+/* Supported HW algorithms */
+#define SOC_SHA_SUPPORT_SHA1            (1)
+#define SOC_SHA_SUPPORT_SHA224          (1)
+#define SOC_SHA_SUPPORT_SHA256          (1)
+#define SOC_SHA_SUPPORT_SHA256          (1)
+#define SOC_SHA_SUPPORT_SHA384          (0)
+#define SOC_SHA_SUPPORT_SHA512          (0)
+#define SOC_SHA_SUPPORT_SHA512_224      (0)
+#define SOC_SHA_SUPPORT_SHA512_256      (0)
+#define SOC_SHA_SUPPORT_SHA512_T        (0)
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/include/soc/sigmadelta_caps.h b/components/soc/esp32c3/include/soc/sigmadelta_caps.h
new file mode 100644
index 0000000000..7f2059a150
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/sigmadelta_caps.h
@@ -0,0 +1,25 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SOC_SIGMADELTA_NUM         (1) // 1 sigma-delta peripheral
+#define SOC_SIGMADELTA_CHANNEL_NUM (4) // 4 channels
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h
new file mode 100644
index 0000000000..262726b1dc
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/soc.h
@@ -0,0 +1,340 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#ifndef __ASSEMBLER__
+#include <stdint.h>
+#include "esp_assert.h"
+#include "esp_bit_defs.h"
+#endif
+
+#define PRO_CPU_NUM (0)
+
+#define DR_REG_SYSTEM_BASE                      0x600c0000
+#define DR_REG_SENSITIVE_BASE                   0x600c1000
+#define DR_REG_INTERRUPT_BASE                   0x600c2000
+#define DR_REG_DMA_COPY_BASE                    0x600c3000
+#define DR_REG_EXTMEM_BASE                      0x600c4000
+#define DR_REG_MMU_TABLE                        0x600c5000
+#define DR_REG_AES_BASE                         0x6003a000
+#define DR_REG_SHA_BASE                         0x6003b000
+#define DR_REG_RSA_BASE                         0x6003c000
+#define DR_REG_HMAC_BASE                        0x6003e000
+#define DR_REG_DIGITAL_SIGNATURE_BASE           0x6003d000
+#define DR_REG_GDMA_BASE                        0x6003f000
+#define DR_REG_ASSIST_DEBUG_BASE                0x600ce000
+#define DR_REG_DEDICATED_GPIO_BASE              0x600cf000
+#define DR_REG_WORLD_CNTL_BASE                  0x600d0000
+#define DR_REG_DPORT_END                        0x600d3FFC
+#define DR_REG_UART_BASE                        0x60000000
+#define DR_REG_SPI1_BASE                        0x60002000
+#define DR_REG_SPI0_BASE                        0x60003000
+#define DR_REG_GPIO_BASE                        0x60004000
+#define DR_REG_RTCCNTL_BASE                     0x60008000
+#define DR_REG_IO_MUX_BASE                      0x60009000
+#define DR_REG_RTC_I2C_BASE                     0x6000e000
+#define DR_REG_UART1_BASE                       0x60010000
+#define DR_REG_I2C_EXT_BASE                     0x60013000
+#define DR_REG_UHCI0_BASE                       0x60014000
+#define DR_REG_RMT_BASE                         0x60016000
+#define DR_REG_LEDC_BASE                        0x60019000
+#define DR_REG_EFUSE_BASE                       0x60008800
+#define DR_REG_TIMERGROUP0_BASE                 0x6001F000
+#define DR_REG_TIMERGROUP1_BASE                 0x60020000
+#define DR_REG_SYS_TIMER_BASE                   0x60023000
+#define DR_REG_SPI2_BASE                        0x60024000
+#define DR_REG_SYSCON_BASE                      0x60026000
+#define DR_REG_APB_CTRL_BASE                    0x60026000    /* Old name for SYSCON, to be removed */
+#define DR_REG_TWAI_BASE                        0x6002B000
+#define DR_REG_I2S0_BASE                        0x6002D000
+#define DR_REG_APB_SARADC_BASE                  0x60040000
+#define DR_REG_AES_XTS_BASE                     0x600CC000
+
+#define REG_UHCI_BASE(i)         (DR_REG_UHCI0_BASE - (i) * 0x8000)
+#define REG_UART_BASE( i )  (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
+#define REG_UART_AHB_BASE(i)  (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
+#define UART_FIFO_AHB_REG(i)  (REG_UART_AHB_BASE(i) + 0x0)
+#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000)
+#define REG_TIMG_BASE(i)              (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
+#define REG_SPI_MEM_BASE(i)     (DR_REG_SPI0_BASE - (i) * 0x1000)
+#define REG_I2C_BASE(i)    (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
+
+//Registers Operation {{
+#define ETS_UNCACHED_ADDR(addr) (addr)
+#define ETS_CACHED_ADDR(addr) (addr)
+
+#ifndef __ASSEMBLER__
+#define BIT(nr)                 (1UL << (nr))
+#else
+#define BIT(nr)                 (1 << (nr))
+#endif
+
+#ifndef __ASSEMBLER__
+
+//write value to register
+#define REG_WRITE(_r, _v) ({                                                                                           \
+            (*(volatile uint32_t *)(_r)) = (_v);                                                                       \
+        })
+
+//read value from register
+#define REG_READ(_r) ({                                                                                                \
+            (*(volatile uint32_t *)(_r));                                                                              \
+        })
+
+//get bit or get bits from register
+#define REG_GET_BIT(_r, _b)  ({                                                                                        \
+            (*(volatile uint32_t*)(_r) & (_b));                                                                        \
+        })
+
+//set bit or set bits to register
+#define REG_SET_BIT(_r, _b)  ({                                                                                        \
+            (*(volatile uint32_t*)(_r) |= (_b));                                                                       \
+        })
+
+//clear bit or clear bits of register
+#define REG_CLR_BIT(_r, _b)  ({                                                                                        \
+            (*(volatile uint32_t*)(_r) &= ~(_b));                                                                      \
+        })
+
+//set bits of register controlled by mask
+#define REG_SET_BITS(_r, _b, _m) ({                                                                                    \
+            (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)));                         \
+        })
+
+//get field from register, uses field _S & _V to determine mask
+#define REG_GET_FIELD(_r, _f) ({                                                                                       \
+            ((REG_READ(_r) >> (_f##_S)) & (_f##_V));                                                                   \
+        })
+
+//set field of a register from variable, uses field _S & _V to determine mask
+#define REG_SET_FIELD(_r, _f, _v) ({                                                                                   \
+            (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))));                \
+        })
+
+//get field value from a variable, used when _f is not left shifted by _f##_S
+#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
+
+//get field value from a variable, used when _f is left shifted by _f##_S
+#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
+
+//set field value to a variable, used when _f is not left shifted by _f##_S
+#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
+
+//set field value to a variable, used when _f is left shifted by _f##_S
+#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
+
+//generate a value from a field value, used when _f is not left shifted by _f##_S
+#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
+
+//generate a value from a field value, used when _f is left shifted by _f##_S
+#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
+
+//read value from register
+#define READ_PERI_REG(addr) ({                                                                                         \
+            (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)));                                                         \
+        })
+
+//write value to register
+#define WRITE_PERI_REG(addr, val) ({                                                                                   \
+            (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val);                                       \
+        })
+
+//clear bits of register controlled by mask
+#define CLEAR_PERI_REG_MASK(reg, mask) ({                                                                              \
+            WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))));                                                     \
+        })
+
+//set bits of register controlled by mask
+#define SET_PERI_REG_MASK(reg, mask) ({                                                                                \
+            WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)));                                                        \
+        })
+
+//get bits of register controlled by mask
+#define GET_PERI_REG_MASK(reg, mask) ({                                                                                \
+            (READ_PERI_REG(reg) & (mask));                                                                             \
+        })
+
+//get bits of register controlled by highest bit and lowest bit
+#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({                                                                        \
+            ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1));                                            \
+        })
+
+//set bits of register controlled by mask and shift
+#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({                                                                  \
+            (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ));      \
+        })
+
+//get field of register
+#define GET_PERI_REG_BITS2(reg, mask,shift) ({                                                                         \
+            ((READ_PERI_REG(reg)>>(shift))&(mask));                                                                    \
+        })
+
+#endif /* !__ASSEMBLER__ */
+//}}
+
+//Periheral Clock {{
+#define  APB_CLK_FREQ_ROM                            ( 40*1000000 )
+#define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
+#define  UART_CLK_FREQ_ROM                           ( 40*1000000)
+#define  EFUSE_CLK_FREQ_ROM                          ( 20*1000000)
+#define  CPU_CLK_FREQ                                APB_CLK_FREQ
+#if CONFIG_IDF_ENV_FPGA
+#define  APB_CLK_FREQ                                ( 40*1000000 )
+#else
+#define  APB_CLK_FREQ                                ( 80*1000000 )
+#endif
+#define  REF_CLK_FREQ                                ( 1000000 )
+#define  UART_CLK_FREQ                               APB_CLK_FREQ
+#define  WDT_CLK_FREQ                                APB_CLK_FREQ
+#define  TIMER_CLK_FREQ                              (80000000>>4) //80MHz divided by 16
+#define  SPI_CLK_DIV                                 4
+#define  TICKS_PER_US_ROM                            40              // CPU is 80MHz
+#define  GPIO_MATRIX_DELAY_NS                        0
+//}}
+
+/* Overall memory map */
+#define SOC_DROM_LOW    0x3C000000
+#define SOC_DROM_HIGH   0x3C800000
+#define SOC_IROM_LOW    0x42000000
+#define SOC_IROM_HIGH   0x42800000
+#define SOC_IROM_MASK_LOW  0x40000000
+#define SOC_IROM_MASK_HIGH 0x40060000
+#define SOC_DROM_MASK_LOW 0x3FF00000
+#define SOC_DROM_MASK_HIGH 0x3FF20000
+#define SOC_IRAM_LOW    0x4037C000
+#define SOC_IRAM_HIGH   0x403E0000
+#define SOC_DRAM_LOW    0x3FC80000
+#define SOC_DRAM_HIGH   0x3FCE0000
+#define SOC_RTC_IRAM_LOW  0x50000000 // ESP32-C3 only has RTC slow memory
+#define SOC_RTC_IRAM_HIGH 0x50002000
+#define SOC_RTC_DRAM_LOW  0x50000000
+#define SOC_RTC_DRAM_HIGH 0x50002000
+#define SOC_RTC_DATA_LOW  0x50000000
+#define SOC_RTC_DATA_HIGH 0x50002000
+
+//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
+#define SOC_DIRAM_IRAM_LOW    0x40380000
+#define SOC_DIRAM_IRAM_HIGH   0x403E0000
+#define SOC_DIRAM_DRAM_LOW    0x3FC80000
+#define SOC_DIRAM_DRAM_HIGH   0x3FCE0000
+
+// Region of memory accessible via DMA. See esp_ptr_dma_capable().
+#define SOC_DMA_LOW  0x3FC88000
+#define SOC_DMA_HIGH 0x3FD00000
+
+// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible().
+#define SOC_BYTE_ACCESSIBLE_LOW     0x3FC88000
+#define SOC_BYTE_ACCESSIBLE_HIGH    0x3FD00000
+
+//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
+//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
+#define SOC_MEM_INTERNAL_LOW        0x3FC80000
+#define SOC_MEM_INTERNAL_HIGH       0x3FCE0000
+#define SOC_MEM_INTERNAL_LOW1       0x40370000
+#define SOC_MEM_INTERNAL_HIGH1      0x403E0000
+#define SOC_MEM_INTERNAL_LOW2       0x600FE000
+#define SOC_MEM_INTERNAL_HIGH2      0x60100000
+
+#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
+
+// Region of address space that holds peripherals
+#define SOC_PERIPHERAL_LOW 0x60000000
+#define SOC_PERIPHERAL_HIGH 0x60100000
+
+// Debug region, not used by software
+#define SOC_DEBUG_LOW 0x20000000
+#define SOC_DEBUG_HIGH 0x28000000
+
+// Start (highest address) of ROM boot stack, only relevant during early boot
+#define SOC_ROM_STACK_START         0x3fcebf10
+
+/* Defined for flash mmap */
+#define REGIONS_COUNT                   1
+#define PAGES_PER_REGION                128
+#define IROM0_PAGES_START               (CACHE_IROM_MMU_START / sizeof(uint32_t))
+#define IROM0_PAGES_END                 (CACHE_IROM_MMU_END / sizeof(uint32_t))
+#define DROM0_PAGES_START               (CACHE_DROM_MMU_START / sizeof(uint32_t))
+#define DROM0_PAGES_END                 (CACHE_DROM_MMU_END / sizeof(uint32_t))
+#define INVALID_ENTRY_VAL               MMU_TABLE_INVALID_VAL
+#define MMU_ADDR_MASK                   MMU_ADDRESS_MASK
+#define PAGE_IN_FLASH(page)             (page) //Always in Flash
+#define DPORT_PRO_FLASH_MMU_TABLE       FLASH_MMU_TABLE
+#define VADDR1_START_ADDR               IRAM0_CACHE_ADDRESS_LOW
+#define PRO_IRAM0_FIRST_USABLE_PAGE     IROM0_PAGES_START
+#define VADDR0_START_ADDR               (SOC_DROM_LOW + (DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
+#define VADDR1_FIRST_USABLE_ADDR        SOC_IROM_LOW
+
+//interrupt cpu using table, Please see the core-isa.h
+/*************************************************************************************************************
+ *      Intr num                Level           Type                    PRO CPU usage           APP CPU uasge
+ *      0                       1               extern level            WMAC                    Reserved
+ *      1                       1               extern level            BT/BLE Host HCI DMA     BT/BLE Host HCI DMA
+ *      2                       1               extern level
+ *      3                       1               extern level
+ *      4                       1               extern level            WBB
+ *      5                       1               extern level            BT/BLE Controller       BT/BLE Controller
+ *      6                       1               timer                   FreeRTOS Tick(L1)       FreeRTOS Tick(L1)
+ *      7                       1               software                BT/BLE VHCI             BT/BLE VHCI
+ *      8                       1               extern level            BT/BLE BB(RX/TX)        BT/BLE BB(RX/TX)
+ *      9                       1               extern level
+ *      10                      1               extern edge
+ *      11                      3               profiling
+ *      12                      1               extern level
+ *      13                      1               extern level
+ *      14                      7               nmi                     Reserved                Reserved
+ *      15                      3               timer                   FreeRTOS Tick(L3)       FreeRTOS Tick(L3)
+ *      16                      5               timer
+ *      17                      1               extern level
+ *      18                      1               extern level
+ *      19                      2               extern level
+ *      20                      2               extern level
+ *      21                      2               extern level
+ *      22                      3               extern edge
+ *      23                      3               extern level
+ *      24                      4               extern level            TG1_WDT
+ *      25                      4               extern level            CACHEERR
+ *      26                      5               extern level
+ *      27                      3               extern level            Reserved                Reserved
+ *      28                      4               extern edge             DPORT ACCESS            DPORT ACCESS
+ *      29                      3               software                Reserved                Reserved
+ *      30                      4               extern edge             Reserved                Reserved
+ *      31                      5               extern level
+ *************************************************************************************************************
+ */
+
+//CPU0 Interrupt number reserved, not touch this.
+#define ETS_WMAC_INUM                           1
+//#define ETS_BT_HOST_INUM                      1
+#define ETS_WBB_INUM                            4
+#define ETS_SYSTICK_INUM                        9
+#define ETS_TG0_T1_INUM                         10 /* use edge interrupt */
+#define ETS_CPU_INTR0_INUM                      12 /* used as freertos soft intr */
+#define ETS_FRC1_INUM                           22
+#define ETS_T1_WDT_INUM                         24
+#define ETS_CACHEERR_INUM                       25
+#define ETS_DPORT_INUM                          28
+
+//CPU0 Interrupt number used in ROM, should be cancelled in SDK
+#define ETS_SLC_INUM                            1
+#define ETS_UART0_INUM                          5
+#define ETS_UART1_INUM                          5
+#define ETS_SPI2_INUM                           1
+//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here.
+#define ETS_GPIO_INUM       4
+
+//Other interrupt number should be managed by the user
+
+//Invalid interrupt for number interrupt matrix
+#define ETS_INVALID_INUM                        0
diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h
new file mode 100644
index 0000000000..b511f946ce
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/soc_caps.h
@@ -0,0 +1,45 @@
+// The long term plan is to have a single soc_caps.h for each peripheral.
+// During the refactoring and multichip support development process, we
+// seperate these information into periph_caps.h for each peripheral and
+// include them here.
+
+#pragma once
+
+#define SOC_CPU_CORES_NUM 1
+#define SOC_GDMA_SUPPORTED 1
+
+// Attention: These fixed DMA channels are temporarily workaround before we have a centralized DMA controller API to help alloc the channel dynamically
+// Remove them when GDMA driver API is ready
+#define SOC_GDMA_M2M_DMA_CHANNEL    (0)
+#define SOC_GDMA_SHA_DMA_CHANNEL    (1)
+#define SOC_GDMA_SPI2_DMA_CHANNEL   (2)
+
+//NOTE: The CHx number should be consistent with the selected DMA channel above
+#define SOC_GDMA_SPI2_INTR_SOURCE   ETS_DMA_CH2_INTR_SOURCE
+//On C3, there is only 1 GPSPI controller (GPSPI2)
+#define SOC_GDMA_SPI3_DMA_CHANNEL   SOC_GDMA_SPI2_DMA_CHANNEL
+
+#include "rmt_caps.h"
+#include "adc_caps.h"
+#include "dac_caps.h"
+#include "i2c_caps.h"
+#include "mpu_caps.h"
+#include "rsa_caps.h"
+#include "sigmadelta_caps.h"
+#include "systimer_caps.h"
+#include "uart_caps.h"
+#include "brownout_caps.h"
+#include "gdma_caps.h"
+#include "i2s_caps.h"
+#include "rtc_io_caps.h"
+#include "soc_caps.h"
+#include "timer_group_caps.h"
+#include "cpu_caps.h"
+#include "gpio_caps.h"
+#include "ledc_caps.h"
+#include "rmt_caps.h"
+#include "sha_caps.h"
+#include "spi_caps.h"
+
+/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
+#define SOC_TOUCH_SENSOR_NUM            (0)    /*! No touch sensors on ESP32-C3 */
diff --git a/components/soc/esp32c3/include/soc/soc_pins.h b/components/soc/esp32c3/include/soc/soc_pins.h
new file mode 100644
index 0000000000..fccf303153
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/soc_pins.h
@@ -0,0 +1,24 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+ * Pin definition header file. The long term plan is to have a single soc_pins.h for all
+ * peripherals. Now we temporarily separate these information into periph_pins/channels.h for each
+ * peripheral and include them here to avoid developing conflicts in those header files.
+ */
+
+#pragma once
+
+#include "soc/gpio_pins.h"
+#include "soc/spi_pins.h"
diff --git a/components/soc/esp32c3/include/soc/spi_caps.h b/components/soc/esp32c3/include/soc/spi_caps.h
new file mode 100644
index 0000000000..c3578456d8
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/spi_caps.h
@@ -0,0 +1,38 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#define SOC_SPI_PERIPH_NUM      4
+#define SOC_SPI_DMA_CHAN_NUM    3
+#define SOC_SPI_PERIPH_CS_NUM(i)    3
+
+#define SOC_SPI_MAXIMUM_BUFFER_SIZE     72
+
+//#define SOC_SPI_SUPPORT_AS_CS         //don't support to toggle the CS while the clock toggles
+#define SOC_SPI_SUPPORT_DDRCLK              1
+#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS     1
+#define SOC_SPI_SUPPORT_CD_SIG              1
+#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS    1
+#define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
+
+// Peripheral supports DIO, DOUT, QIO, or QOUT
+#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id)          ((host_id) != 2)
+
+// Peripheral supports output given level during its "dummy phase"
+#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT              1
+
+#define SOC_MEMSPI_IS_INDEPENDENT 1
+
+#define SOC_SPI_MAX_PRE_DIVIDER 16
diff --git a/components/soc/esp32c3/include/soc/spi_mem_reg.h b/components/soc/esp32c3/include/soc/spi_mem_reg.h
new file mode 100644
index 0000000000..fcf3e29248
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/spi_mem_reg.h
@@ -0,0 +1,1220 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SPI_MEM_REG_H_
+#define _SOC_SPI_MEM_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x000)
+/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Read flash enable. Read flash operation will be triggered when
+ the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+#define SPI_MEM_FLASH_READ  (BIT(31))
+#define SPI_MEM_FLASH_READ_M  (BIT(31))
+#define SPI_MEM_FLASH_READ_V  0x1
+#define SPI_MEM_FLASH_READ_S  31
+/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Write flash enable.  Write enable command will be sent when the
+ bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+#define SPI_MEM_FLASH_WREN  (BIT(30))
+#define SPI_MEM_FLASH_WREN_M  (BIT(30))
+#define SPI_MEM_FLASH_WREN_V  0x1
+#define SPI_MEM_FLASH_WREN_S  30
+/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Write flash disable. Write disable command will be sent when
+ the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+#define SPI_MEM_FLASH_WRDI  (BIT(29))
+#define SPI_MEM_FLASH_WRDI_M  (BIT(29))
+#define SPI_MEM_FLASH_WRDI_V  0x1
+#define SPI_MEM_FLASH_WRDI_S  29
+/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Read JEDEC ID . Read ID command will be sent when the bit is
+ set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+#define SPI_MEM_FLASH_RDID  (BIT(28))
+#define SPI_MEM_FLASH_RDID_M  (BIT(28))
+#define SPI_MEM_FLASH_RDID_V  0x1
+#define SPI_MEM_FLASH_RDID_S  28
+/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Read status register-1.  Read status operation will be triggered
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_RDSR  (BIT(27))
+#define SPI_MEM_FLASH_RDSR_M  (BIT(27))
+#define SPI_MEM_FLASH_RDSR_V  0x1
+#define SPI_MEM_FLASH_RDSR_S  27
+/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Write status register enable.   Write status operation  will
+ be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_WRSR  (BIT(26))
+#define SPI_MEM_FLASH_WRSR_M  (BIT(26))
+#define SPI_MEM_FLASH_WRSR_V  0x1
+#define SPI_MEM_FLASH_WRSR_S  26
+/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Page program enable(1 byte ~256 bytes data to be programmed).
+ Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
+#define SPI_MEM_FLASH_PP  (BIT(25))
+#define SPI_MEM_FLASH_PP_M  (BIT(25))
+#define SPI_MEM_FLASH_PP_V  0x1
+#define SPI_MEM_FLASH_PP_S  25
+/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Sector erase enable(4KB). Sector erase operation will be triggered
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_SE  (BIT(24))
+#define SPI_MEM_FLASH_SE_M  (BIT(24))
+#define SPI_MEM_FLASH_SE_V  0x1
+#define SPI_MEM_FLASH_SE_S  24
+/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Block erase enable(32KB) .  Block erase operation will be triggered
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_BE  (BIT(23))
+#define SPI_MEM_FLASH_BE_M  (BIT(23))
+#define SPI_MEM_FLASH_BE_V  0x1
+#define SPI_MEM_FLASH_BE_S  23
+/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Chip erase enable. Chip erase operation will be triggered when
+ the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_CE  (BIT(22))
+#define SPI_MEM_FLASH_CE_M  (BIT(22))
+#define SPI_MEM_FLASH_CE_V  0x1
+#define SPI_MEM_FLASH_CE_S  22
+/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Drive Flash into power down.  An operation will be triggered
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_DP  (BIT(21))
+#define SPI_MEM_FLASH_DP_M  (BIT(21))
+#define SPI_MEM_FLASH_DP_V  0x1
+#define SPI_MEM_FLASH_DP_S  21
+/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
+/*description: This bit combined with reg_resandres bit releases Flash from
+ the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_RES  (BIT(20))
+#define SPI_MEM_FLASH_RES_M  (BIT(20))
+#define SPI_MEM_FLASH_RES_V  0x1
+#define SPI_MEM_FLASH_RES_S  20
+/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Drive Flash into high performance mode.  The bit will be cleared
+ once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_HPM  (BIT(19))
+#define SPI_MEM_FLASH_HPM_M  (BIT(19))
+#define SPI_MEM_FLASH_HPM_V  0x1
+#define SPI_MEM_FLASH_HPM_S  19
+/* SPI_MEM_USR : R/W/SC ;bitpos:[18] ;default: 1'b0 ; */
+/*description: User define command enable.  An operation will be triggered when
+ the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_USR  (BIT(18))
+#define SPI_MEM_USR_M  (BIT(18))
+#define SPI_MEM_USR_V  0x1
+#define SPI_MEM_USR_S  18
+/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */
+/*description: In user mode  it is set to indicate that program/erase operation
+ will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_PE  (BIT(17))
+#define SPI_MEM_FLASH_PE_M  (BIT(17))
+#define SPI_MEM_FLASH_PE_V  0x1
+#define SPI_MEM_FLASH_PE_S  17
+/* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: The current status of SPI1 slave FSM: mspi_st. 0: idle state
+  1: preparation state  2: send command state  3: send address state  4: wait state  5: read data state  6:write data state  7: done state  8: read data end state.*/
+#define SPI_MEM_SLV_ST  0x0000000F
+#define SPI_MEM_SLV_ST_M  ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S))
+#define SPI_MEM_SLV_ST_V  0xF
+#define SPI_MEM_SLV_ST_S  4
+/* SPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: The current status of SPI1 master FSM.*/
+#define SPI_MEM_MST_ST  0x0000000F
+#define SPI_MEM_MST_ST_M  ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S))
+#define SPI_MEM_MST_ST_V  0xF
+#define SPI_MEM_MST_ST_S  0
+
+#define SPI_MEM_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x004)
+/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: In user mode  it is the memory address. other then the bit0-bit23
+ is the memory address  the bit24-bit31 are the byte length of a transfer.*/
+#define SPI_MEM_USR_ADDR_VALUE  0xFFFFFFFF
+#define SPI_MEM_USR_ADDR_VALUE_M  ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S))
+#define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFF
+#define SPI_MEM_USR_ADDR_VALUE_S  0
+
+#define SPI_MEM_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x008)
+/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply
+ 4 signals. 1: enable 0: disable.*/
+#define SPI_MEM_FREAD_QIO  (BIT(24))
+#define SPI_MEM_FREAD_QIO_M  (BIT(24))
+#define SPI_MEM_FREAD_QIO_V  0x1
+#define SPI_MEM_FREAD_QIO_S  24
+/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply
+ 2 signals. 1: enable 0: disable.*/
+#define SPI_MEM_FREAD_DIO  (BIT(23))
+#define SPI_MEM_FREAD_DIO_M  (BIT(23))
+#define SPI_MEM_FREAD_DIO_V  0x1
+#define SPI_MEM_FREAD_DIO_S  23
+/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: two bytes data will be written to status register when it is
+ set. 1: enable 0: disable.*/
+#define SPI_MEM_WRSR_2B  (BIT(22))
+#define SPI_MEM_WRSR_2B_M  (BIT(22))
+#define SPI_MEM_WRSR_2B_V  0x1
+#define SPI_MEM_WRSR_2B_S  22
+/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: Write protect signal output when SPI is idle.  1: output high  0: output low.*/
+#define SPI_MEM_WP_REG  (BIT(21))
+#define SPI_MEM_WP_REG_M  (BIT(21))
+#define SPI_MEM_WP_REG_V  0x1
+#define SPI_MEM_WP_REG_S  21
+/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
+#define SPI_MEM_FREAD_QUAD  (BIT(20))
+#define SPI_MEM_FREAD_QUAD_M  (BIT(20))
+#define SPI_MEM_FREAD_QUAD_V  0x1
+#define SPI_MEM_FREAD_QUAD_S  20
+/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: The bit is used to set MOSI line polarity  1: high 0  low*/
+#define SPI_MEM_D_POL  (BIT(19))
+#define SPI_MEM_D_POL_M  (BIT(19))
+#define SPI_MEM_D_POL_V  0x1
+#define SPI_MEM_D_POL_S  19
+/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: The bit is used to set MISO line polarity  1: high 0  low*/
+#define SPI_MEM_Q_POL  (BIT(18))
+#define SPI_MEM_Q_POL_M  (BIT(18))
+#define SPI_MEM_Q_POL_V  0x1
+#define SPI_MEM_Q_POL_S  18
+/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: The Device ID is read out to SPI_MEM_RD_STATUS register   this
+ bit combine with spi_mem_flash_res bit. 1: enable 0: disable.*/
+#define SPI_MEM_RESANDRES  (BIT(15))
+#define SPI_MEM_RESANDRES_M  (BIT(15))
+#define SPI_MEM_RESANDRES_V  0x1
+#define SPI_MEM_RESANDRES_S  15
+/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the read operations  read-data phase apply 2 signals. 1: enable 0: disable.*/
+#define SPI_MEM_FREAD_DUAL  (BIT(14))
+#define SPI_MEM_FREAD_DUAL_M  (BIT(14))
+#define SPI_MEM_FREAD_DUAL_V  0x1
+#define SPI_MEM_FREAD_DUAL_S  14
+/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This bit enable the bits: spi_mem_fread_qio  spi_mem_fread_dio
+  spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/
+#define SPI_MEM_FASTRD_MODE  (BIT(13))
+#define SPI_MEM_FASTRD_MODE_M  (BIT(13))
+#define SPI_MEM_FASTRD_MODE_V  0x1
+#define SPI_MEM_FASTRD_MODE_S  13
+/* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: For SPI1   enable crc32 when writing encrypted data to flash.
+ 1: enable 0:disable*/
+#define SPI_MEM_TX_CRC_EN  (BIT(11))
+#define SPI_MEM_TX_CRC_EN_M  (BIT(11))
+#define SPI_MEM_TX_CRC_EN_V  0x1
+#define SPI_MEM_TX_CRC_EN_S  11
+/* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: For SPI1   initialize crc32 module before writing encrypted data
+ to flash. Active low.*/
+#define SPI_MEM_FCS_CRC_EN  (BIT(10))
+#define SPI_MEM_FCS_CRC_EN_M  (BIT(10))
+#define SPI_MEM_FCS_CRC_EN_V  0x1
+#define SPI_MEM_FCS_CRC_EN_S  10
+/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Apply 4 signals during command phase 1:enable 0: disable*/
+#define SPI_MEM_FCMD_QUAD  (BIT(8))
+#define SPI_MEM_FCMD_QUAD_M  (BIT(8))
+#define SPI_MEM_FCMD_QUAD_V  0x1
+#define SPI_MEM_FCMD_QUAD_S  8
+/* SPI_MEM_FCMD_DUAL : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Apply 2 signals during command phase 1:enable 0: disable*/
+#define SPI_MEM_FCMD_DUAL  (BIT(7))
+#define SPI_MEM_FCMD_DUAL_M  (BIT(7))
+#define SPI_MEM_FCMD_DUAL_V  0x1
+#define SPI_MEM_FCMD_DUAL_S  7
+/* SPI_MEM_FDUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: In the dummy phase the signal level of spi is output by the spi controller.*/
+#define SPI_MEM_FDUMMY_OUT  (BIT(3))
+#define SPI_MEM_FDUMMY_OUT_M  (BIT(3))
+#define SPI_MEM_FDUMMY_OUT_V  0x1
+#define SPI_MEM_FDUMMY_OUT_S  3
+
+#define SPI_MEM_CTRL1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x00C)
+/* SPI_MEM_RXFIFO_WFULL_ERR : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 1: SPI0 RX FIFO write full error  Cache/EDMA do not read all
+ the data out. 0: Not error.*/
+#define SPI_MEM_RXFIFO_WFULL_ERR  (BIT(31))
+#define SPI_MEM_RXFIFO_WFULL_ERR_M  (BIT(31))
+#define SPI_MEM_RXFIFO_WFULL_ERR_V  0x1
+#define SPI_MEM_RXFIFO_WFULL_ERR_S  31
+/* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
+/*description: SPI0 RX FIFO reset signal.*/
+#define SPI_MEM_RXFIFO_RST  (BIT(30))
+#define SPI_MEM_RXFIFO_RST_M  (BIT(30))
+#define SPI_MEM_RXFIFO_RST_V  0x1
+#define SPI_MEM_RXFIFO_RST_S  30
+/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */
+/*description: After RES/DP/HPM command is sent  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0]
+ * 512) SPI_CLK cycles.*/
+#define SPI_MEM_CS_HOLD_DLY_RES  0x000003FF
+#define SPI_MEM_CS_HOLD_DLY_RES_M  ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S))
+#define SPI_MEM_CS_HOLD_DLY_RES_V  0x3FF
+#define SPI_MEM_CS_HOLD_DLY_RES_S  2
+/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1:
+ SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
+#define SPI_MEM_CLK_MODE  0x00000003
+#define SPI_MEM_CLK_MODE_M  ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
+#define SPI_MEM_CLK_MODE_V  0x3
+#define SPI_MEM_CLK_MODE_S  0
+
+#define SPI_MEM_CTRL2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x010)
+/* SPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The FSM will be reset.*/
+#define SPI_MEM_SYNC_RESET  (BIT(31))
+#define SPI_MEM_SYNC_RESET_M  (BIT(31))
+#define SPI_MEM_SYNC_RESET_V  0x1
+#define SPI_MEM_SYNC_RESET_S  31
+/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
+/*description: These bits are used to set the minimum CS high time tSHSL between
+ SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
+#define SPI_MEM_CS_HOLD_DELAY  0x0000003F
+#define SPI_MEM_CS_HOLD_DELAY_M  ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S))
+#define SPI_MEM_CS_HOLD_DELAY_V  0x3F
+#define SPI_MEM_CS_HOLD_DELAY_S  25
+/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
+/*description: Spi cs signal is delayed to inactive by spi clock this bits are
+ combined with spi_mem_cs_hold bit.*/
+#define SPI_MEM_CS_HOLD_TIME  0x0000001F
+#define SPI_MEM_CS_HOLD_TIME_M  ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S))
+#define SPI_MEM_CS_HOLD_TIME_V  0x1F
+#define SPI_MEM_CS_HOLD_TIME_S  5
+/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
+/*description: (cycles-1) of prepare phase by spi clock this bits are combined
+ with spi_mem_cs_setup bit.*/
+#define SPI_MEM_CS_SETUP_TIME  0x0000001F
+#define SPI_MEM_CS_SETUP_TIME_M  ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S))
+#define SPI_MEM_CS_SETUP_TIME_V  0x1F
+#define SPI_MEM_CS_SETUP_TIME_S  0
+
+#define SPI_MEM_CLOCK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x014)
+/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Set this bit in 1-division mode.reserved for spi1*/
+#define SPI_MEM_CLK_EQU_SYSCLK  (BIT(31))
+#define SPI_MEM_CLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_MEM_CLK_EQU_SYSCLK_V  0x1
+#define SPI_MEM_CLK_EQU_SYSCLK_S  31
+/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
+/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk
+ frequency is system/(spi_mem_clkcnt_N+1)*/
+#define SPI_MEM_CLKCNT_N  0x000000FF
+#define SPI_MEM_CLKCNT_N_M  ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S))
+#define SPI_MEM_CLKCNT_N_V  0xFF
+#define SPI_MEM_CLKCNT_N_S  16
+/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
+#define SPI_MEM_CLKCNT_H  0x000000FF
+#define SPI_MEM_CLKCNT_H_M  ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S))
+#define SPI_MEM_CLKCNT_H_V  0xFF
+#define SPI_MEM_CLKCNT_H_S  8
+/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
+/*description: In the master mode it must be equal to spi_mem_clkcnt_N.*/
+#define SPI_MEM_CLKCNT_L  0x000000FF
+#define SPI_MEM_CLKCNT_L_M  ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S))
+#define SPI_MEM_CLKCNT_L_V  0xFF
+#define SPI_MEM_CLKCNT_L_S  0
+
+#define SPI_MEM_USER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x018)
+/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: This bit enable the command phase of an operation.*/
+#define SPI_MEM_USR_COMMAND  (BIT(31))
+#define SPI_MEM_USR_COMMAND_M  (BIT(31))
+#define SPI_MEM_USR_COMMAND_V  0x1
+#define SPI_MEM_USR_COMMAND_S  31
+/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: This bit enable the address phase of an operation.*/
+#define SPI_MEM_USR_ADDR  (BIT(30))
+#define SPI_MEM_USR_ADDR_M  (BIT(30))
+#define SPI_MEM_USR_ADDR_V  0x1
+#define SPI_MEM_USR_ADDR_S  30
+/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: This bit enable the dummy phase of an operation.*/
+#define SPI_MEM_USR_DUMMY  (BIT(29))
+#define SPI_MEM_USR_DUMMY_M  (BIT(29))
+#define SPI_MEM_USR_DUMMY_V  0x1
+#define SPI_MEM_USR_DUMMY_S  29
+/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: This bit enable the read-data phase of an operation.*/
+#define SPI_MEM_USR_MISO  (BIT(28))
+#define SPI_MEM_USR_MISO_M  (BIT(28))
+#define SPI_MEM_USR_MISO_V  0x1
+#define SPI_MEM_USR_MISO_S  28
+/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: This bit enable the write-data phase of an operation.*/
+#define SPI_MEM_USR_MOSI  (BIT(27))
+#define SPI_MEM_USR_MOSI_M  (BIT(27))
+#define SPI_MEM_USR_MOSI_V  0x1
+#define SPI_MEM_USR_MOSI_S  27
+/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: spi clock is disable in dummy phase when the bit is enable.*/
+#define SPI_MEM_USR_DUMMY_IDLE  (BIT(26))
+#define SPI_MEM_USR_DUMMY_IDLE_M  (BIT(26))
+#define SPI_MEM_USR_DUMMY_IDLE_V  0x1
+#define SPI_MEM_USR_DUMMY_IDLE_S  26
+/* SPI_MEM_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
+ 1: enable 0: disable.*/
+#define SPI_MEM_USR_MOSI_HIGHPART  (BIT(25))
+#define SPI_MEM_USR_MOSI_HIGHPART_M  (BIT(25))
+#define SPI_MEM_USR_MOSI_HIGHPART_V  0x1
+#define SPI_MEM_USR_MOSI_HIGHPART_S  25
+/* SPI_MEM_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
+ 1: enable 0: disable.*/
+#define SPI_MEM_USR_MISO_HIGHPART  (BIT(24))
+#define SPI_MEM_USR_MISO_HIGHPART_M  (BIT(24))
+#define SPI_MEM_USR_MISO_HIGHPART_V  0x1
+#define SPI_MEM_USR_MISO_HIGHPART_S  24
+/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: In the write operations address phase and read-data phase apply 4 signals.*/
+#define SPI_MEM_FWRITE_QIO  (BIT(15))
+#define SPI_MEM_FWRITE_QIO_M  (BIT(15))
+#define SPI_MEM_FWRITE_QIO_V  0x1
+#define SPI_MEM_FWRITE_QIO_S  15
+/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the write operations address phase and read-data phase apply 2 signals.*/
+#define SPI_MEM_FWRITE_DIO  (BIT(14))
+#define SPI_MEM_FWRITE_DIO_M  (BIT(14))
+#define SPI_MEM_FWRITE_DIO_V  0x1
+#define SPI_MEM_FWRITE_DIO_S  14
+/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 4 signals*/
+#define SPI_MEM_FWRITE_QUAD  (BIT(13))
+#define SPI_MEM_FWRITE_QUAD_M  (BIT(13))
+#define SPI_MEM_FWRITE_QUAD_V  0x1
+#define SPI_MEM_FWRITE_QUAD_S  13
+/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 2 signals*/
+#define SPI_MEM_FWRITE_DUAL  (BIT(12))
+#define SPI_MEM_FWRITE_DUAL_M  (BIT(12))
+#define SPI_MEM_FWRITE_DUAL_V  0x1
+#define SPI_MEM_FWRITE_DUAL_S  12
+/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: the bit combined with spi_mem_mosi_delay_mode bits to set mosi
+ signal delay mode.*/
+#define SPI_MEM_CK_OUT_EDGE  (BIT(9))
+#define SPI_MEM_CK_OUT_EDGE_M  (BIT(9))
+#define SPI_MEM_CK_OUT_EDGE_V  0x1
+#define SPI_MEM_CK_OUT_EDGE_S  9
+/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.*/
+#define SPI_MEM_CS_SETUP  (BIT(7))
+#define SPI_MEM_CS_SETUP_M  (BIT(7))
+#define SPI_MEM_CS_SETUP_V  0x1
+#define SPI_MEM_CS_SETUP_S  7
+/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable.*/
+#define SPI_MEM_CS_HOLD  (BIT(6))
+#define SPI_MEM_CS_HOLD_M  (BIT(6))
+#define SPI_MEM_CS_HOLD_V  0x1
+#define SPI_MEM_CS_HOLD_S  6
+
+#define SPI_MEM_USER1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x01C)
+/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
+/*description: The length in bits of address phase. The register value shall be (bit_num-1).*/
+#define SPI_MEM_USR_ADDR_BITLEN  0x0000003F
+#define SPI_MEM_USR_ADDR_BITLEN_M  ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S))
+#define SPI_MEM_USR_ADDR_BITLEN_V  0x3F
+#define SPI_MEM_USR_ADDR_BITLEN_S  26
+/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
+/*description: The length in spi_mem_clk cycles of dummy phase. The register
+ value shall be (cycle_num-1).*/
+#define SPI_MEM_USR_DUMMY_CYCLELEN  0x0000003F
+#define SPI_MEM_USR_DUMMY_CYCLELEN_M  ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
+#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
+
+#define SPI_MEM_USER2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x020)
+/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
+/*description: The length in bits of command phase. The register value shall be (bit_num-1)*/
+#define SPI_MEM_USR_COMMAND_BITLEN  0x0000000F
+#define SPI_MEM_USR_COMMAND_BITLEN_M  ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S))
+#define SPI_MEM_USR_COMMAND_BITLEN_V  0xF
+#define SPI_MEM_USR_COMMAND_BITLEN_S  28
+/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value of  command.*/
+#define SPI_MEM_USR_COMMAND_VALUE  0x0000FFFF
+#define SPI_MEM_USR_COMMAND_VALUE_M  ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S))
+#define SPI_MEM_USR_COMMAND_VALUE_V  0xFFFF
+#define SPI_MEM_USR_COMMAND_VALUE_S  0
+
+#define SPI_MEM_MOSI_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x024)
+/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The length in bits of write-data. The register value shall be (bit_num-1).*/
+#define SPI_MEM_USR_MOSI_DBITLEN  0x000003FF
+#define SPI_MEM_USR_MOSI_DBITLEN_M  ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
+#define SPI_MEM_USR_MOSI_DBITLEN_V  0x3FF
+#define SPI_MEM_USR_MOSI_DBITLEN_S  0
+
+#define SPI_MEM_MISO_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x028)
+/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The length in bits of  read-data. The register value shall be (bit_num-1).*/
+#define SPI_MEM_USR_MISO_DBITLEN  0x000003FF
+#define SPI_MEM_USR_MISO_DBITLEN_M  ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S))
+#define SPI_MEM_USR_MISO_DBITLEN_V  0x3FF
+#define SPI_MEM_USR_MISO_DBITLEN_S  0
+
+#define SPI_MEM_RD_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x02C)
+/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
+/*description: Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode
+ bit.*/
+#define SPI_MEM_WB_MODE  0x000000FF
+#define SPI_MEM_WB_MODE_M  ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S))
+#define SPI_MEM_WB_MODE_V  0xFF
+#define SPI_MEM_WB_MODE_S  16
+/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
+#define SPI_MEM_STATUS  0x0000FFFF
+#define SPI_MEM_STATUS_M  ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
+#define SPI_MEM_STATUS_V  0xFFFF
+#define SPI_MEM_STATUS_S  0
+
+#define SPI_MEM_MISC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x034)
+/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: spi cs line keep low when the bit is set.*/
+#define SPI_MEM_CS_KEEP_ACTIVE  (BIT(10))
+#define SPI_MEM_CS_KEEP_ACTIVE_M  (BIT(10))
+#define SPI_MEM_CS_KEEP_ACTIVE_V  0x1
+#define SPI_MEM_CS_KEEP_ACTIVE_S  10
+/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 1: spi clk line is high when idle     0: spi clk line is low when idle*/
+#define SPI_MEM_CK_IDLE_EDGE  (BIT(9))
+#define SPI_MEM_CK_IDLE_EDGE_M  (BIT(9))
+#define SPI_MEM_CK_IDLE_EDGE_V  0x1
+#define SPI_MEM_CK_IDLE_EDGE_S  9
+/* SPI_MEM_SLV_ST_TRANS_END_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt of spi0_slv_st controlled
+ transmitting is done.*/
+#define SPI_MEM_SLV_ST_TRANS_END_INT_ENA  (BIT(6))
+#define SPI_MEM_SLV_ST_TRANS_END_INT_ENA_M  (BIT(6))
+#define SPI_MEM_SLV_ST_TRANS_END_INT_ENA_V  0x1
+#define SPI_MEM_SLV_ST_TRANS_END_INT_ENA_S  6
+/* SPI_MEM_SLV_ST_TRANS_END : R/W/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the  spi0_slv_st controlled transmitting is done.*/
+#define SPI_MEM_SLV_ST_TRANS_END  (BIT(5))
+#define SPI_MEM_SLV_ST_TRANS_END_M  (BIT(5))
+#define SPI_MEM_SLV_ST_TRANS_END_V  0x1
+#define SPI_MEM_SLV_ST_TRANS_END_S  5
+/* SPI_MEM_CSPI_ST_TRANS_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt of SPI0 cspi_st controlled
+ transmitting is done.*/
+#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA  (BIT(4))
+#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_M  (BIT(4))
+#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_V  0x1
+#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_S  4
+/* SPI_MEM_CSPI_ST_TRANS_END : R/W/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the SPI0 cspi_st controlled transmitting is done.*/
+#define SPI_MEM_CSPI_ST_TRANS_END  (BIT(3))
+#define SPI_MEM_CSPI_ST_TRANS_END_M  (BIT(3))
+#define SPI_MEM_CSPI_ST_TRANS_END_V  0x1
+#define SPI_MEM_CSPI_ST_TRANS_END_S  3
+/* SPI_MEM_TRANS_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt of SPI0 em_st controlled
+ transmitting is done.*/
+#define SPI_MEM_TRANS_END_INT_ENA  (BIT(2))
+#define SPI_MEM_TRANS_END_INT_ENA_M  (BIT(2))
+#define SPI_MEM_TRANS_END_INT_ENA_V  0x1
+#define SPI_MEM_TRANS_END_INT_ENA_S  2
+/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: SPI_CS1 pin enable  1: disable SPI_CS1  0: SPI_CS1 pin is active
+ to select SPI device  such as flash  external RAM and so on.*/
+#define SPI_MEM_CS1_DIS  (BIT(1))
+#define SPI_MEM_CS1_DIS_M  (BIT(1))
+#define SPI_MEM_CS1_DIS_V  0x1
+#define SPI_MEM_CS1_DIS_S  1
+/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: SPI_CS0 pin enable  1: disable SPI_CS0  0: SPI_CS0 pin is active
+ to select SPI device  such as flash  external RAM and so on.*/
+#define SPI_MEM_CS0_DIS  (BIT(0))
+#define SPI_MEM_CS0_DIS_M  (BIT(0))
+#define SPI_MEM_CS0_DIS_V  0x1
+#define SPI_MEM_CS0_DIS_S  0
+
+#define SPI_MEM_TX_CRC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x038)
+/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: For SPI1  the value of crc32.*/
+#define SPI_MEM_TX_CRC_DATA  0xFFFFFFFF
+#define SPI_MEM_TX_CRC_DATA_M  ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S))
+#define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFF
+#define SPI_MEM_TX_CRC_DATA_S  0
+
+#define SPI_MEM_CACHE_FCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x03C)
+/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: For SPI1  address phase apply 4 signals. 1: enable 0: disable.
+  The bit is the same with spi_mem_fread_qio.*/
+#define SPI_MEM_FADDR_QUAD  (BIT(8))
+#define SPI_MEM_FADDR_QUAD_M  (BIT(8))
+#define SPI_MEM_FADDR_QUAD_V  0x1
+#define SPI_MEM_FADDR_QUAD_S  8
+/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: For SPI1  dout phase apply 4 signals. 1: enable 0: disable.
+ The bit is the same with spi_mem_fread_qio.*/
+#define SPI_MEM_FDOUT_QUAD  (BIT(7))
+#define SPI_MEM_FDOUT_QUAD_M  (BIT(7))
+#define SPI_MEM_FDOUT_QUAD_V  0x1
+#define SPI_MEM_FDOUT_QUAD_S  7
+/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: For SPI1  din phase apply 4 signals. 1: enable 0: disable.  The
+ bit is the same with spi_mem_fread_qio.*/
+#define SPI_MEM_FDIN_QUAD  (BIT(6))
+#define SPI_MEM_FDIN_QUAD_M  (BIT(6))
+#define SPI_MEM_FDIN_QUAD_V  0x1
+#define SPI_MEM_FDIN_QUAD_S  6
+/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: For SPI1  address phase apply 2 signals. 1: enable 0: disable.
+  The bit is the same with spi_mem_fread_dio.*/
+#define SPI_MEM_FADDR_DUAL  (BIT(5))
+#define SPI_MEM_FADDR_DUAL_M  (BIT(5))
+#define SPI_MEM_FADDR_DUAL_V  0x1
+#define SPI_MEM_FADDR_DUAL_S  5
+/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: For SPI1  dout phase apply 2 signals. 1: enable 0: disable. The
+ bit is the same with spi_mem_fread_dio.*/
+#define SPI_MEM_FDOUT_DUAL  (BIT(4))
+#define SPI_MEM_FDOUT_DUAL_M  (BIT(4))
+#define SPI_MEM_FDOUT_DUAL_V  0x1
+#define SPI_MEM_FDOUT_DUAL_S  4
+/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: For SPI1  din phase apply 2 signals. 1: enable 0: disable. The
+ bit is the same with spi_mem_fread_dio.*/
+#define SPI_MEM_FDIN_DUAL  (BIT(3))
+#define SPI_MEM_FDIN_DUAL_M  (BIT(3))
+#define SPI_MEM_FDIN_DUAL_V  0x1
+#define SPI_MEM_FDIN_DUAL_S  3
+/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: For SPI0   cache  read flash for user define command  1: enable  0:disable.*/
+#define SPI_MEM_CACHE_FLASH_USR_CMD  (BIT(2))
+#define SPI_MEM_CACHE_FLASH_USR_CMD_M  (BIT(2))
+#define SPI_MEM_CACHE_FLASH_USR_CMD_V  0x1
+#define SPI_MEM_CACHE_FLASH_USR_CMD_S  2
+/* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0   cache  read flash with 4 bytes address  1: enable  0:disable.*/
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE  (BIT(1))
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M  (BIT(1))
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V  0x1
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S  1
+/* SPI_MEM_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0  Cache access enable  1: enable  0:disable.*/
+#define SPI_MEM_CACHE_REQ_EN  (BIT(0))
+#define SPI_MEM_CACHE_REQ_EN_M  (BIT(0))
+#define SPI_MEM_CACHE_REQ_EN_V  0x1
+#define SPI_MEM_CACHE_REQ_EN_S  0
+
+#define SPI_MEM_FSM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x054)
+/* SPI_MEM_CSPI_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */
+/*description: The lock delay time of SPI0/1 arbiter by cspi_st  after PER is sent by SPI1.*/
+#define SPI_MEM_CSPI_LOCK_DELAY_TIME  0x0000001F
+#define SPI_MEM_CSPI_LOCK_DELAY_TIME_M  ((SPI_MEM_CSPI_LOCK_DELAY_TIME_V)<<(SPI_MEM_CSPI_LOCK_DELAY_TIME_S))
+#define SPI_MEM_CSPI_LOCK_DELAY_TIME_V  0x1F
+#define SPI_MEM_CSPI_LOCK_DELAY_TIME_S  7
+/* SPI_MEM_EM_ST : RO ;bitpos:[6:4] ;default: 3'h0 ; */
+/*description: The current status of SPI0 master FSM: cspi_st. 0: idle state
+  1:EM_CACHE_GRANT   2: program/erase suspend state  3: SPI0 read data state  4: wait cache/EDMA sent data is stored in SPI0 TX FIFO  5: SPI0 write data state.*/
+#define SPI_MEM_EM_ST  0x00000007
+#define SPI_MEM_EM_ST_M  ((SPI_MEM_EM_ST_V)<<(SPI_MEM_EM_ST_S))
+#define SPI_MEM_EM_ST_V  0x7
+#define SPI_MEM_EM_ST_S  4
+/* SPI_MEM_CSPI_ST : RO ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: The current status of SPI0 slave FSM: cspi_st. 0: idle state
+  1: preparation state  2: send command state  3: send address state  4: wait state  5: read data state  6:write data state  7: done state  8: read data end state.*/
+#define SPI_MEM_CSPI_ST  0x0000000F
+#define SPI_MEM_CSPI_ST_M  ((SPI_MEM_CSPI_ST_V)<<(SPI_MEM_CSPI_ST_S))
+#define SPI_MEM_CSPI_ST_V  0xF
+#define SPI_MEM_CSPI_ST_S  0
+
+#define SPI_MEM_W0_REG(i)          (REG_SPI_MEM_BASE(i) + 0x058)
+/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF0  0xFFFFFFFF
+#define SPI_MEM_BUF0_M  ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S))
+#define SPI_MEM_BUF0_V  0xFFFFFFFF
+#define SPI_MEM_BUF0_S  0
+
+#define SPI_MEM_W1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x05C)
+/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF1  0xFFFFFFFF
+#define SPI_MEM_BUF1_M  ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S))
+#define SPI_MEM_BUF1_V  0xFFFFFFFF
+#define SPI_MEM_BUF1_S  0
+
+#define SPI_MEM_W2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x060)
+/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF2  0xFFFFFFFF
+#define SPI_MEM_BUF2_M  ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S))
+#define SPI_MEM_BUF2_V  0xFFFFFFFF
+#define SPI_MEM_BUF2_S  0
+
+#define SPI_MEM_W3_REG(i)          (REG_SPI_MEM_BASE(i) + 0x064)
+/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF3  0xFFFFFFFF
+#define SPI_MEM_BUF3_M  ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S))
+#define SPI_MEM_BUF3_V  0xFFFFFFFF
+#define SPI_MEM_BUF3_S  0
+
+#define SPI_MEM_W4_REG(i)          (REG_SPI_MEM_BASE(i) + 0x068)
+/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF4  0xFFFFFFFF
+#define SPI_MEM_BUF4_M  ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S))
+#define SPI_MEM_BUF4_V  0xFFFFFFFF
+#define SPI_MEM_BUF4_S  0
+
+#define SPI_MEM_W5_REG(i)          (REG_SPI_MEM_BASE(i) + 0x06C)
+/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF5  0xFFFFFFFF
+#define SPI_MEM_BUF5_M  ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S))
+#define SPI_MEM_BUF5_V  0xFFFFFFFF
+#define SPI_MEM_BUF5_S  0
+
+#define SPI_MEM_W6_REG(i)          (REG_SPI_MEM_BASE(i) + 0x070)
+/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF6  0xFFFFFFFF
+#define SPI_MEM_BUF6_M  ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S))
+#define SPI_MEM_BUF6_V  0xFFFFFFFF
+#define SPI_MEM_BUF6_S  0
+
+#define SPI_MEM_W7_REG(i)          (REG_SPI_MEM_BASE(i) + 0x074)
+/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF7  0xFFFFFFFF
+#define SPI_MEM_BUF7_M  ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S))
+#define SPI_MEM_BUF7_V  0xFFFFFFFF
+#define SPI_MEM_BUF7_S  0
+
+#define SPI_MEM_W8_REG(i)          (REG_SPI_MEM_BASE(i) + 0x078)
+/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF8  0xFFFFFFFF
+#define SPI_MEM_BUF8_M  ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S))
+#define SPI_MEM_BUF8_V  0xFFFFFFFF
+#define SPI_MEM_BUF8_S  0
+
+#define SPI_MEM_W9_REG(i)          (REG_SPI_MEM_BASE(i) + 0x07C)
+/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF9  0xFFFFFFFF
+#define SPI_MEM_BUF9_M  ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S))
+#define SPI_MEM_BUF9_V  0xFFFFFFFF
+#define SPI_MEM_BUF9_S  0
+
+#define SPI_MEM_W10_REG(i)          (REG_SPI_MEM_BASE(i) + 0x080)
+/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF10  0xFFFFFFFF
+#define SPI_MEM_BUF10_M  ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S))
+#define SPI_MEM_BUF10_V  0xFFFFFFFF
+#define SPI_MEM_BUF10_S  0
+
+#define SPI_MEM_W11_REG(i)          (REG_SPI_MEM_BASE(i) + 0x084)
+/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF11  0xFFFFFFFF
+#define SPI_MEM_BUF11_M  ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S))
+#define SPI_MEM_BUF11_V  0xFFFFFFFF
+#define SPI_MEM_BUF11_S  0
+
+#define SPI_MEM_W12_REG(i)          (REG_SPI_MEM_BASE(i) + 0x088)
+/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF12  0xFFFFFFFF
+#define SPI_MEM_BUF12_M  ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S))
+#define SPI_MEM_BUF12_V  0xFFFFFFFF
+#define SPI_MEM_BUF12_S  0
+
+#define SPI_MEM_W13_REG(i)          (REG_SPI_MEM_BASE(i) + 0x08C)
+/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF13  0xFFFFFFFF
+#define SPI_MEM_BUF13_M  ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S))
+#define SPI_MEM_BUF13_V  0xFFFFFFFF
+#define SPI_MEM_BUF13_S  0
+
+#define SPI_MEM_W14_REG(i)          (REG_SPI_MEM_BASE(i) + 0x090)
+/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF14  0xFFFFFFFF
+#define SPI_MEM_BUF14_M  ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S))
+#define SPI_MEM_BUF14_V  0xFFFFFFFF
+#define SPI_MEM_BUF14_S  0
+
+#define SPI_MEM_W15_REG(i)          (REG_SPI_MEM_BASE(i) + 0x094)
+/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF15  0xFFFFFFFF
+#define SPI_MEM_BUF15_M  ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S))
+#define SPI_MEM_BUF15_V  0xFFFFFFFF
+#define SPI_MEM_BUF15_S  0
+
+#define SPI_MEM_FLASH_WAITI_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x098)
+/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
+/*description: The dummy cycle length when wait flash idle(RDSR).*/
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN  0x0000003F
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S))
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
+/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[9:2] ;default: 8'h05 ; */
+/*description: The command to wait flash idle(RDSR).*/
+#define SPI_MEM_WAITI_CMD  0x000000FF
+#define SPI_MEM_WAITI_CMD_M  ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S))
+#define SPI_MEM_WAITI_CMD_V  0xFF
+#define SPI_MEM_WAITI_CMD_S  2
+/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The dummy phase enable when wait flash idle (RDSR)*/
+#define SPI_MEM_WAITI_DUMMY  (BIT(1))
+#define SPI_MEM_WAITI_DUMMY_M  (BIT(1))
+#define SPI_MEM_WAITI_DUMMY_V  0x1
+#define SPI_MEM_WAITI_DUMMY_S  1
+
+#define SPI_MEM_FLASH_SUS_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x09C)
+/* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */
+/*description: When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0]
+ times  it will be treated as check pass.*/
+#define SPI_MEM_SUS_TIMEOUT_CNT  0x0000007F
+#define SPI_MEM_SUS_TIMEOUT_CNT_M  ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S))
+#define SPI_MEM_SUS_TIMEOUT_CNT_V  0x7F
+#define SPI_MEM_SUS_TIMEOUT_CNT_S  25
+/* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure
+ the suspend status of flash. 0: Only need to check WIP is 0.*/
+#define SPI_MEM_PES_END_EN  (BIT(24))
+#define SPI_MEM_PES_END_EN_M  (BIT(24))
+#define SPI_MEM_PES_END_EN_V  0x1
+#define SPI_MEM_PES_END_EN_S  24
+/* SPI_MEM_PER_END_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure
+ the resume status of flash. 0: Only need to check WIP is 0.*/
+#define SPI_MEM_PER_END_EN  (BIT(23))
+#define SPI_MEM_PER_END_EN_M  (BIT(23))
+#define SPI_MEM_PER_END_EN_V  0x1
+#define SPI_MEM_PER_END_EN_S  23
+/* SPI_MEM_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit.
+ 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit*/
+#define SPI_MEM_FMEM_RD_SUS_2B  (BIT(22))
+#define SPI_MEM_FMEM_RD_SUS_2B_M  (BIT(22))
+#define SPI_MEM_FMEM_RD_SUS_2B_V  0x1
+#define SPI_MEM_FMEM_RD_SUS_2B_S  22
+/* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */
+/*description: The mask value when check SUS/SUS1/SUS2 status bit. If the read
+ status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out  status_in[15:0] is valid when two bytes of data are read out)  SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
+#define SPI_MEM_PESR_END_MSK  0x0000FFFF
+#define SPI_MEM_PESR_END_MSK_M  ((SPI_MEM_PESR_END_MSK_V)<<(SPI_MEM_PESR_END_MSK_S))
+#define SPI_MEM_PESR_END_MSK_V  0xFFFF
+#define SPI_MEM_PESR_END_MSK_S  6
+/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable Auto-suspending function.*/
+#define SPI_MEM_FLASH_PES_EN  (BIT(5))
+#define SPI_MEM_FLASH_PES_EN_M  (BIT(5))
+#define SPI_MEM_FLASH_PES_EN_V  0x1
+#define SPI_MEM_FLASH_PES_EN_S  5
+/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to enable PES transfer trigger PES transfer option.
+ If this bit is 0  application should send PER after PES is done.*/
+#define SPI_MEM_PES_PER_EN  (BIT(4))
+#define SPI_MEM_PES_PER_EN_M  (BIT(4))
+#define SPI_MEM_PES_PER_EN_V  0x1
+#define SPI_MEM_PES_PER_EN_S  4
+/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0]
+ * 4) SPI_CLK cycles after program erase suspend.*/
+#define SPI_MEM_FLASH_PES_WAIT_EN  (BIT(3))
+#define SPI_MEM_FLASH_PES_WAIT_EN_M  (BIT(3))
+#define SPI_MEM_FLASH_PES_WAIT_EN_V  0x1
+#define SPI_MEM_FLASH_PES_WAIT_EN_S  3
+/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0]
+ * 4) SPI_CLK cycles after program erase resume.*/
+#define SPI_MEM_FLASH_PER_WAIT_EN  (BIT(2))
+#define SPI_MEM_FLASH_PER_WAIT_EN_M  (BIT(2))
+#define SPI_MEM_FLASH_PER_WAIT_EN_V  0x1
+#define SPI_MEM_FLASH_PER_WAIT_EN_S  2
+/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
+/*description: program erase suspend bit  program erase suspend operation will
+ be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_PES  (BIT(1))
+#define SPI_MEM_FLASH_PES_M  (BIT(1))
+#define SPI_MEM_FLASH_PES_V  0x1
+#define SPI_MEM_FLASH_PES_S  1
+/* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
+/*description: program erase resume bit  program erase suspend operation will
+ be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_PER  (BIT(0))
+#define SPI_MEM_FLASH_PER_M  (BIT(0))
+#define SPI_MEM_FLASH_PER_V  0x1
+#define SPI_MEM_FLASH_PER_S  0
+
+#define SPI_MEM_FLASH_SUS_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0A0)
+/* SPI_MEM_WAIT_PESR_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h05 ; */
+/*description: Flash SUS/SUS1/SUS2 status bit read command. The command should
+ be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
+#define SPI_MEM_WAIT_PESR_COMMAND  0x0000FFFF
+#define SPI_MEM_WAIT_PESR_COMMAND_M  ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S))
+#define SPI_MEM_WAIT_PESR_COMMAND_V  0xFFFF
+#define SPI_MEM_WAIT_PESR_COMMAND_S  16
+/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[15:8] ;default: 8'h75 ; */
+/*description: Program/Erase suspend command.*/
+#define SPI_MEM_FLASH_PES_COMMAND  0x000000FF
+#define SPI_MEM_FLASH_PES_COMMAND_M  ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S))
+#define SPI_MEM_FLASH_PES_COMMAND_V  0xFF
+#define SPI_MEM_FLASH_PES_COMMAND_S  8
+/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[7:0] ;default: 8'h7a ; */
+/*description: Program/Erase resume command.*/
+#define SPI_MEM_FLASH_PER_COMMAND  0x000000FF
+#define SPI_MEM_FLASH_PER_COMMAND_M  ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S))
+#define SPI_MEM_FLASH_PER_COMMAND_V  0xFF
+#define SPI_MEM_FLASH_PER_COMMAND_S  0
+
+#define SPI_MEM_SUS_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0A4)
+/* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/
+#define SPI_MEM_SPI0_LOCK_EN  (BIT(7))
+#define SPI_MEM_SPI0_LOCK_EN_M  (BIT(7))
+#define SPI_MEM_SPI0_LOCK_EN_V  0x1
+#define SPI_MEM_SPI0_LOCK_EN_S  7
+/* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0]
+ * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
+#define SPI_MEM_FLASH_PES_DLY_128  (BIT(6))
+#define SPI_MEM_FLASH_PES_DLY_128_M  (BIT(6))
+#define SPI_MEM_FLASH_PES_DLY_128_V  0x1
+#define SPI_MEM_FLASH_PES_DLY_128_S  6
+/* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0]
+ * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
+#define SPI_MEM_FLASH_PER_DLY_128  (BIT(5))
+#define SPI_MEM_FLASH_PER_DLY_128_M  (BIT(5))
+#define SPI_MEM_FLASH_PER_DLY_128_V  0x1
+#define SPI_MEM_FLASH_PER_DLY_128_S  5
+/* SPI_MEM_FLASH_DP_DLY_128 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK
+ cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
+#define SPI_MEM_FLASH_DP_DLY_128  (BIT(4))
+#define SPI_MEM_FLASH_DP_DLY_128_M  (BIT(4))
+#define SPI_MEM_FLASH_DP_DLY_128_V  0x1
+#define SPI_MEM_FLASH_DP_DLY_128_S  4
+/* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK
+ cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
+#define SPI_MEM_FLASH_RES_DLY_128  (BIT(3))
+#define SPI_MEM_FLASH_RES_DLY_128_M  (BIT(3))
+#define SPI_MEM_FLASH_RES_DLY_128_V  0x1
+#define SPI_MEM_FLASH_RES_DLY_128_S  3
+/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK
+ cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
+#define SPI_MEM_FLASH_HPM_DLY_128  (BIT(2))
+#define SPI_MEM_FLASH_HPM_DLY_128_M  (BIT(2))
+#define SPI_MEM_FLASH_HPM_DLY_128_V  0x1
+#define SPI_MEM_FLASH_HPM_DLY_128_S  2
+/* SPI_MEM_WAIT_PESR_CMD_2B : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2
+ bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/
+#define SPI_MEM_WAIT_PESR_CMD_2B  (BIT(1))
+#define SPI_MEM_WAIT_PESR_CMD_2B_M  (BIT(1))
+#define SPI_MEM_WAIT_PESR_CMD_2B_V  0x1
+#define SPI_MEM_WAIT_PESR_CMD_2B_S  1
+/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The status of flash suspend  only used in SPI1.*/
+#define SPI_MEM_FLASH_SUS  (BIT(0))
+#define SPI_MEM_FLASH_SUS_M  (BIT(0))
+#define SPI_MEM_FLASH_SUS_V  0x1
+#define SPI_MEM_FLASH_SUS_S  0
+
+#define SPI_MEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0A8)
+/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
+/*description: add extra dummy spi clock cycle length for spi clock calibration.*/
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN  0x00000007
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x7
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
+/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable timing auto-calibration for all reading operations.*/
+#define SPI_MEM_TIMING_CALI  (BIT(1))
+#define SPI_MEM_TIMING_CALI_M  (BIT(1))
+#define SPI_MEM_TIMING_CALI_V  0x1
+#define SPI_MEM_TIMING_CALI_S  1
+/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to enable timing adjust clock for all reading operations.*/
+#define SPI_MEM_TIMING_CLK_ENA  (BIT(0))
+#define SPI_MEM_TIMING_CLK_ENA_M  (BIT(0))
+#define SPI_MEM_TIMING_CLK_ENA_V  0x1
+#define SPI_MEM_TIMING_CLK_ENA_S  0
+
+#define SPI_MEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0AC)
+/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+#define SPI_MEM_DIN3_MODE  0x00000003
+#define SPI_MEM_DIN3_MODE_M  ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S))
+#define SPI_MEM_DIN3_MODE_V  0x3
+#define SPI_MEM_DIN3_MODE_S  6
+/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+#define SPI_MEM_DIN2_MODE  0x00000003
+#define SPI_MEM_DIN2_MODE_M  ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S))
+#define SPI_MEM_DIN2_MODE_V  0x3
+#define SPI_MEM_DIN2_MODE_S  4
+/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+#define SPI_MEM_DIN1_MODE  0x00000003
+#define SPI_MEM_DIN1_MODE_M  ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S))
+#define SPI_MEM_DIN1_MODE_V  0x3
+#define SPI_MEM_DIN1_MODE_S  2
+/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+#define SPI_MEM_DIN0_MODE  0x00000003
+#define SPI_MEM_DIN0_MODE_M  ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S))
+#define SPI_MEM_DIN0_MODE_V  0x3
+#define SPI_MEM_DIN0_MODE_S  0
+
+#define SPI_MEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0B0)
+/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_MEM_DIN3_NUM  0x00000003
+#define SPI_MEM_DIN3_NUM_M  ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S))
+#define SPI_MEM_DIN3_NUM_V  0x3
+#define SPI_MEM_DIN3_NUM_S  6
+/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_MEM_DIN2_NUM  0x00000003
+#define SPI_MEM_DIN2_NUM_M  ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S))
+#define SPI_MEM_DIN2_NUM_V  0x3
+#define SPI_MEM_DIN2_NUM_S  4
+/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_MEM_DIN1_NUM  0x00000003
+#define SPI_MEM_DIN1_NUM_M  ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S))
+#define SPI_MEM_DIN1_NUM_V  0x3
+#define SPI_MEM_DIN1_NUM_S  2
+/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_MEM_DIN0_NUM  0x00000003
+#define SPI_MEM_DIN0_NUM_M  ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S))
+#define SPI_MEM_DIN0_NUM_V  0x3
+#define SPI_MEM_DIN0_NUM_S  0
+
+#define SPI_MEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0B4)
+/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+#define SPI_MEM_DOUT3_MODE  (BIT(3))
+#define SPI_MEM_DOUT3_MODE_M  (BIT(3))
+#define SPI_MEM_DOUT3_MODE_V  0x1
+#define SPI_MEM_DOUT3_MODE_S  3
+/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+#define SPI_MEM_DOUT2_MODE  (BIT(2))
+#define SPI_MEM_DOUT2_MODE_M  (BIT(2))
+#define SPI_MEM_DOUT2_MODE_V  0x1
+#define SPI_MEM_DOUT2_MODE_S  2
+/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+#define SPI_MEM_DOUT1_MODE  (BIT(1))
+#define SPI_MEM_DOUT1_MODE_M  (BIT(1))
+#define SPI_MEM_DOUT1_MODE_V  0x1
+#define SPI_MEM_DOUT1_MODE_S  1
+/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+#define SPI_MEM_DOUT0_MODE  (BIT(0))
+#define SPI_MEM_DOUT0_MODE_M  (BIT(0))
+#define SPI_MEM_DOUT0_MODE_V  0x1
+#define SPI_MEM_DOUT0_MODE_S  0
+
+#define SPI_MEM_INT_ENA_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0C0)
+/* SPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+#define SPI_MEM_MST_ST_END_INT_ENA  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ENA_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ENA_V  0x1
+#define SPI_MEM_MST_ST_END_INT_ENA_S  4
+/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+#define SPI_MEM_SLV_ST_END_INT_ENA  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ENA_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ENA_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_ENA_S  3
+/* SPI_MEM_WPE_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
+#define SPI_MEM_WPE_END_INT_ENA  (BIT(2))
+#define SPI_MEM_WPE_END_INT_ENA_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_ENA_V  0x1
+#define SPI_MEM_WPE_END_INT_ENA_S  2
+/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PES_END_INT interrupt.*/
+#define SPI_MEM_PES_END_INT_ENA  (BIT(1))
+#define SPI_MEM_PES_END_INT_ENA_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_ENA_V  0x1
+#define SPI_MEM_PES_END_INT_ENA_S  1
+/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PER_END_INT interrupt.*/
+#define SPI_MEM_PER_END_INT_ENA  (BIT(0))
+#define SPI_MEM_PER_END_INT_ENA_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_ENA_V  0x1
+#define SPI_MEM_PER_END_INT_ENA_S  0
+
+#define SPI_MEM_INT_CLR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0C4)
+/* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+#define SPI_MEM_MST_ST_END_INT_CLR  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_CLR_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_CLR_V  0x1
+#define SPI_MEM_MST_ST_END_INT_CLR_S  4
+/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+#define SPI_MEM_SLV_ST_END_INT_CLR  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_CLR_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_CLR_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_CLR_S  3
+/* SPI_MEM_WPE_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
+#define SPI_MEM_WPE_END_INT_CLR  (BIT(2))
+#define SPI_MEM_WPE_END_INT_CLR_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_CLR_V  0x1
+#define SPI_MEM_WPE_END_INT_CLR_S  2
+/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PES_END_INT interrupt.*/
+#define SPI_MEM_PES_END_INT_CLR  (BIT(1))
+#define SPI_MEM_PES_END_INT_CLR_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_CLR_V  0x1
+#define SPI_MEM_PES_END_INT_CLR_S  1
+/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PER_END_INT interrupt.*/
+#define SPI_MEM_PER_END_INT_CLR  (BIT(0))
+#define SPI_MEM_PER_END_INT_CLR_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_CLR_V  0x1
+#define SPI_MEM_PER_END_INT_CLR_S  0
+
+#define SPI_MEM_INT_RAW_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0C8)
+/* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered
+ when spi1_mst_st is changed from non idle state to idle state. 0: Others.*/
+#define SPI_MEM_MST_ST_END_INT_RAW  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_RAW_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_RAW_V  0x1
+#define SPI_MEM_MST_ST_END_INT_RAW_S  4
+/* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered
+ when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
+#define SPI_MEM_SLV_ST_END_INT_RAW  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_RAW_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_RAW_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_RAW_S  3
+/* SPI_MEM_WPE_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when
+ WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
+#define SPI_MEM_WPE_END_INT_RAW  (BIT(2))
+#define SPI_MEM_WPE_END_INT_RAW_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_RAW_V  0x1
+#define SPI_MEM_WPE_END_INT_RAW_S  2
+/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when
+ Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.*/
+#define SPI_MEM_PES_END_INT_RAW  (BIT(1))
+#define SPI_MEM_PES_END_INT_RAW_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_RAW_V  0x1
+#define SPI_MEM_PES_END_INT_RAW_S  1
+/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when
+ Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.*/
+#define SPI_MEM_PER_END_INT_RAW  (BIT(0))
+#define SPI_MEM_PER_END_INT_RAW_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_RAW_V  0x1
+#define SPI_MEM_PER_END_INT_RAW_S  0
+
+#define SPI_MEM_INT_ST_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0CC)
+/* SPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+#define SPI_MEM_MST_ST_END_INT_ST  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ST_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ST_V  0x1
+#define SPI_MEM_MST_ST_END_INT_ST_S  4
+/* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+#define SPI_MEM_SLV_ST_END_INT_ST  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ST_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ST_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_ST_S  3
+/* SPI_MEM_WPE_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_WPE_END_INT interrupt.*/
+#define SPI_MEM_WPE_END_INT_ST  (BIT(2))
+#define SPI_MEM_WPE_END_INT_ST_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_ST_V  0x1
+#define SPI_MEM_WPE_END_INT_ST_S  2
+/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PES_END_INT interrupt.*/
+#define SPI_MEM_PES_END_INT_ST  (BIT(1))
+#define SPI_MEM_PES_END_INT_ST_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_ST_V  0x1
+#define SPI_MEM_PES_END_INT_ST_S  1
+/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PER_END_INT interrupt.*/
+#define SPI_MEM_PER_END_INT_ST  (BIT(0))
+#define SPI_MEM_PER_END_INT_ST_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_ST_V  0x1
+#define SPI_MEM_PER_END_INT_ST_S  0
+
+#define SPI_MEM_CLOCK_GATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0DC)
+/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Register clock gate enable signal. 1: Enable. 0: Disable.*/
+#define SPI_MEM_CLK_EN  (BIT(0))
+#define SPI_MEM_CLK_EN_M  (BIT(0))
+#define SPI_MEM_CLK_EN_V  0x1
+#define SPI_MEM_CLK_EN_S  0
+
+#define SPI_MEM_CORE_CLK_SEL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0E0)
+/* SPI_MEM_SPI01_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: When the digital system clock selects PLL clock and the frequency
+ of PLL clock is 480MHz  the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz  the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/
+#define SPI_MEM_SPI01_CLK_SEL  0x00000003
+#define SPI_MEM_SPI01_CLK_SEL_M  ((SPI_MEM_SPI01_CLK_SEL_V)<<(SPI_MEM_SPI01_CLK_SEL_S))
+#define SPI_MEM_SPI01_CLK_SEL_V  0x3
+#define SPI_MEM_SPI01_CLK_SEL_S  0
+
+#define SPI_MEM_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3FC)
+/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007170 ; */
+/*description: Version control register*/
+#define SPI_MEM_DATE  0x0FFFFFFF
+#define SPI_MEM_DATE_M  ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S))
+#define SPI_MEM_DATE_V  0xFFFFFFF
+#define SPI_MEM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SPI_MEM_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/spi_mem_struct.h b/components/soc/esp32c3/include/soc/spi_mem_struct.h
new file mode 100644
index 0000000000..e0f62b0d15
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/spi_mem_struct.h
@@ -0,0 +1,569 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SPI_MEM_STRUCT_H_
+#define _SOC_SPI_MEM_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t mst_st:         4;                 /*The current status of SPI1 master FSM.*/
+            uint32_t st:             4;                 /*The current status of SPI1 slave FSM: mspi_st. 0: idle state  1: preparation state  2: send command state  3: send address state  4: wait state  5: read data state  6:write data state  7: done state  8: read data end state.*/
+            uint32_t reserved8:      9;                 /*reserved*/
+            uint32_t flash_pe:       1;                 /*In user mode  it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t usr:            1;                 /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_hpm:      1;                 /*Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_res:      1;                 /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_dp:       1;                 /*Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_ce:       1;                 /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_be:       1;                 /*Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_se:       1;                 /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_pp:       1;                 /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
+            uint32_t flash_wrsr:     1;                 /*Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_rdsr:     1;                 /*Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_rdid:     1;                 /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+            uint32_t flash_wrdi:     1;                 /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+            uint32_t flash_wren:     1;                 /*Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+            uint32_t flash_read:     1;                 /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+        };
+        uint32_t val;
+    } cmd;
+    uint32_t addr;                                      /*SPI1 address register*/
+    union {
+        struct {
+            uint32_t reserved0:       3;                /*reserved*/
+            uint32_t fdummy_out:      1;                /*In the dummy phase the signal level of spi is output by the spi controller.*/
+            uint32_t reserved4:       3;                /*reserved*/
+            uint32_t fcmd_dual:       1;                /*Apply 2 signals during command phase 1:enable 0: disable*/
+            uint32_t fcmd_quad:       1;                /*Apply 4 signals during command phase 1:enable 0: disable*/
+            uint32_t reserved9:       1;                /*reserved*/
+            uint32_t fcs_crc_en:      1;                /*For SPI1   initialize crc32 module before writing encrypted data to flash. Active low.*/
+            uint32_t tx_crc_en:       1;                /*For SPI1   enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
+            uint32_t reserved12:      1;                /*reserved*/
+            uint32_t fastrd_mode:     1;                /*This bit enable the bits: spi_mem_fread_qio  spi_mem_fread_dio  spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/
+            uint32_t fread_dual:      1;                /*In the read operations  read-data phase apply 2 signals. 1: enable 0: disable.*/
+            uint32_t resandres:       1;                /*The Device ID is read out to SPI_MEM_RD_STATUS register   this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.*/
+            uint32_t reserved16:      2;                /*reserved*/
+            uint32_t q_pol:           1;                /*The bit is used to set MISO line polarity  1: high 0  low*/
+            uint32_t d_pol:           1;                /*The bit is used to set MOSI line polarity  1: high 0  low*/
+            uint32_t fread_quad:      1;                /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
+            uint32_t wp:              1;                /*Write protect signal output when SPI is idle.  1: output high  0: output low.*/
+            uint32_t wrsr_2b:         1;                /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/
+            uint32_t fread_dio:       1;                /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/
+            uint32_t fread_qio:       1;                /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/
+            uint32_t reserved25:      7;                /*reserved*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t clk_mode:            2;            /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
+            uint32_t cs_hold_dly_res:    10;            /*After RES/DP/HPM command is sent  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
+            uint32_t reserved2:           18;               /*reserved*/
+            uint32_t rxfifo_rst:       1;               /*SPI0 RX FIFO reset signal.*/
+            uint32_t rxfifo_wfull_err: 1;               /*1: SPI0 RX FIFO write full error  Cache/EDMA do not read all the data out. 0: Not error.*/
+        };
+        uint32_t val;
+    } ctrl1;
+    union {
+        struct {
+            uint32_t cs_setup_time: 5;                  /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
+            uint32_t cs_hold_time:  5;                  /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
+            uint32_t reserved10:       15;                  /*reserved*/
+            uint32_t cs_hold_delay: 6;                  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
+            uint32_t sync_reset:    1;                  /*The FSM will be reset.*/
+        };
+        uint32_t val;
+    } ctrl2;
+    union {
+        struct {
+            uint32_t clkcnt_l:       8;                 /*In the master mode it must be equal to spi_mem_clkcnt_N.*/
+            uint32_t clkcnt_h:       8;                 /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
+            uint32_t clkcnt_n:       8;                 /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
+            uint32_t reserved24:         7;                 /*reserved*/
+            uint32_t clk_equ_sysclk: 1;                 /*Set this bit in 1-division mode.*/
+        };
+        uint32_t val;
+    } clock;
+    union {
+        struct {
+            uint32_t reserved0:          6;                 /*reserved*/
+            uint32_t cs_hold:        1;                 /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable.*/
+            uint32_t cs_setup:       1;                 /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.*/
+            uint32_t reserved8:          1;                 /*reserved*/
+            uint32_t ck_out_edge:       1;          /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.*/
+            uint32_t reserved10:            2;          /*reserved*/
+            uint32_t fwrite_dual:       1;          /*In the write operations read-data phase apply 2 signals*/
+            uint32_t fwrite_quad:       1;          /*In the write operations read-data phase apply 4 signals*/
+            uint32_t fwrite_dio:        1;          /*In the write operations address phase and read-data phase apply 2 signals.*/
+            uint32_t fwrite_qio:        1;          /*In the write operations address phase and read-data phase apply 4 signals.*/
+            uint32_t reserved16:            8;          /*reserved*/
+            uint32_t usr_miso_highpart: 1;          /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/
+            uint32_t usr_mosi_highpart: 1;          /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/
+            uint32_t usr_dummy_idle:    1;          /*SPI clock is disable in dummy phase when the bit is enable.*/
+            uint32_t usr_mosi:          1;          /*This bit enable the write-data phase of an operation.*/
+            uint32_t usr_miso:          1;          /*This bit enable the read-data phase of an operation.*/
+            uint32_t usr_dummy:         1;          /*This bit enable the dummy phase of an operation.*/
+            uint32_t usr_addr:          1;          /*This bit enable the address phase of an operation.*/
+            uint32_t usr_command:       1;          /*This bit enable the command phase of an operation.*/
+        };
+        uint32_t val;
+    } user;
+    union {
+        struct {
+            uint32_t usr_dummy_cyclelen:     6;         /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
+            uint32_t reserved6:             20;         /*reserved*/
+            uint32_t usr_addr_bitlen:        6;         /*The length in bits of address phase. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } user1;
+    union {
+        struct {
+            uint32_t usr_command_value:     16;         /*The value of  command.*/
+            uint32_t reserved16:            12;         /*reserved*/
+            uint32_t usr_command_bitlen:     4;         /*The length in bits of command phase. The register value shall be (bit_num-1)*/
+        };
+        uint32_t val;
+    } user2;
+    union {
+        struct {
+            uint32_t usr_mosi_bit_len:    10;           /*The length in bits of write-data. The register value shall be (bit_num-1).*/
+            uint32_t reserved10:          22;           /*reserved*/
+        };
+        uint32_t val;
+    } mosi_dlen;
+    union {
+        struct {
+            uint32_t usr_miso_bit_len:    10;           /*The length in bits of  read-data. The register value shall be (bit_num-1).*/
+            uint32_t reserved10:          22;           /*reserved*/
+        };
+        uint32_t val;
+    } miso_dlen;
+    union {
+        struct {
+            uint32_t status:     16;                    /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
+            uint32_t wb_mode:     8;                    /*Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
+            uint32_t reserved24:  8;                    /*reserved*/
+        };
+        uint32_t val;
+    } rd_status;
+    uint32_t reserved_30;
+    union {
+        struct {
+            uint32_t cs0_dis:            1;             /*SPI_CS0 pin enable  1: disable SPI_CS0  0: SPI_CS0 pin is active to select SPI device  such as flash  external RAM and so on.*/
+            uint32_t cs1_dis:            1;             /*SPI_CS1 pin enable  1: disable SPI_CS1  0: SPI_CS1 pin is active to select SPI device  such as flash  external RAM and so on.*/
+            uint32_t reserved2:          1;             /*reserved*/
+            uint32_t mst_st_trans_end:         1;       /*The bit is used to indicate the  spi0_mst_st controlled transmitting is done.*/
+            uint32_t mst_st_trans_end_en:      1;       /*The bit is used to enable the interrupt of  spi0_mst_st controlled transmitting is done.*/
+            uint32_t st_trans_end:             1;       /*The bit is used to indicate the  spi0_slv_st controlled transmitting is done.*/
+            uint32_t st_trans_end_en:          1;       /*The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.*/
+            uint32_t reserved7:                    2;       /*reserved*/
+            uint32_t ck_idle_edge:       1;             /*1: spi clk line is high when idle     0: spi clk line is low when idle*/
+            uint32_t cs_keep_active:     1;             /*spi cs line keep low when the bit is set.*/
+            uint32_t reserved11:                  21;       /*reserved*/
+        };
+        uint32_t val;
+    } misc;
+    uint32_t tx_crc;                                    /*SPI1 TX CRC data register.*/
+    union {
+        struct {
+            uint32_t req_en:               1;           /*For SPI0  Cache access enable  1: enable  0:disable.*/
+            uint32_t usr_addr_4byte:           1;       /*For SPI1   cache  read flash with 4 bytes address  1: enable  0:disable.*/
+            uint32_t flash_usr_cmd:        1;           /*For SPI0   cache  read flash for user define command  1: enable  0:disable.*/
+            uint32_t fdin_dual:                1;       /*For SPI1  din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
+            uint32_t fdout_dual:               1;       /*For SPI1  dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
+            uint32_t faddr_dual:               1;       /*For SPI1  address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.*/
+            uint32_t fdin_quad:                1;       /*For SPI1  din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t fdout_quad:               1;       /*For SPI1  dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t faddr_quad:               1;       /*For SPI1  address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t reserved9:               23;       /*reserved*/
+        };
+        uint32_t val;
+    } cache_fctrl;
+    uint32_t reserved_40;
+    uint32_t reserved_44;
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    union {
+        struct {
+            uint32_t spi0_st:              4;           /*The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state  1: preparation state  2: send command state  3: send address state  4: wait state  5: read data state  6:write data state  7: done state  8: read data end state.*/
+            uint32_t spi0_mst_st:          3;           /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state  1:EM_CACHE_GRANT   2: program/erase suspend state  3: SPI0 read data state  4: wait cache/EDMA sent data is stored in SPI0 TX FIFO  5: SPI0 write data state.*/
+            uint32_t cspi_lock_delay_time: 5;           /*The lock delay time of SPI0/1 arbiter by spi0_slv_st  after PER is sent by SPI1.*/
+            uint32_t reserved12:              20;           /*reserved*/
+        };
+        uint32_t val;
+    } fsm;
+    uint32_t data_buf[16];
+    union {
+        struct {
+            uint32_t reserved0:                1;       /*reserved*/
+            uint32_t waiti_dummy:              1;       /*The dummy phase enable when wait flash idle (RDSR)*/
+            uint32_t waiti_cmd:                8;       /*The command to wait flash idle(RDSR).*/
+            uint32_t waiti_dummy_cyclelen:     6;       /*The dummy cycle length when wait flash idle(RDSR).*/
+            uint32_t reserved16:              16;       /*reserved*/
+        };
+        uint32_t val;
+    } flash_waiti_ctrl;
+    union {
+        struct {
+            uint32_t flash_per:             1;          /*program erase resume bit  program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_pes:             1;          /*program erase suspend bit  program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_per_wait_en:     1;          /*Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after program erase suspend.*/
+            uint32_t flash_pes_wait_en:     1;          /*Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after program erase suspend.*/
+            uint32_t pes_per_en:            1;          /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0  application should send PER after PES is done.*/
+            uint32_t flash_pes_en:          1;          /*Set this bit to enable Auto-suspending function.*/
+            uint32_t pesr_end_msk:         16;          /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out  status_in[15:0] is valid when two bytes of data are read out)  SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
+            uint32_t frd_sus_2b:            1;          /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit*/
+            uint32_t per_end_en:            1;          /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/
+            uint32_t pes_end_en:            1;          /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/
+            uint32_t sus_timeout_cnt:       7;          /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times  it will be treated as check pass.*/
+        };
+        uint32_t val;
+    } flash_sus_ctrl;
+    union {
+        struct {
+            uint32_t flash_per_command:     8;          /*Program/Erase resume command.*/
+            uint32_t flash_pes_command:     8;          /*Program/Erase suspend command.*/
+            uint32_t wait_pesr_command:    16;          /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
+        };
+        uint32_t val;
+    } flash_sus_cmd;
+    union {
+        struct {
+            uint32_t flash_sus:     1;                  /*The status of flash suspend  only used in SPI1.*/
+            uint32_t reserved1:    31;                  /*reserved*/
+        };
+        uint32_t val;
+    } sus_status;
+    union {
+        struct {
+            uint32_t timing_clk_ena:       1;           /*The bit is used to enable timing adjust clock for all reading operations.*/
+            uint32_t timing_cali:              1;       /*The bit is used to enable timing auto-calibration for all reading operations.*/
+            uint32_t extra_dummy_cyclelen:     3;       /*add extra dummy spi clock cycle length for spi clock calibration.*/
+            uint32_t reserved5:               27;           /*reserved*/
+        };
+        uint32_t val;
+    } timing_cali;
+    union {
+        struct {
+            uint32_t din0_mode: 2;                      /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+            uint32_t din1_mode: 2;                      /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+            uint32_t din2_mode: 2;                      /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+            uint32_t din3_mode: 2;                      /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+            uint32_t reserved8:    24;                      /*reserved*/
+        };
+        uint32_t val;
+    } din_mode;
+    union {
+        struct {
+            uint32_t din0_num: 2;                       /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t din1_num: 2;                       /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t din2_num: 2;                       /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t din3_num: 2;                       /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t reserved8:   24;                       /*reserved*/
+        };
+        uint32_t val;
+    } din_num;
+    union {
+        struct {
+            uint32_t dout0_mode: 1;                     /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+            uint32_t dout1_mode: 1;                     /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+            uint32_t dout2_mode: 1;                     /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+            uint32_t dout3_mode: 1;                     /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+            uint32_t reserved4:     28;                     /*reserved*/
+        };
+        uint32_t val;
+    } dout_mode;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    union {
+        struct {
+            uint32_t per_end_int_ena:        1;         /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end_int_ena:        1;         /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end_int_ena:        1;         /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t st_end_int_ena:         1;         /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end_int_ena:     1;         /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t reserved5:             27;         /*reserved*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t per_end:                1;         /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end:                1;         /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end:                1;         /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t st_end:                 1;         /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end:             1;         /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t reserved5:             27;         /*reserved*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t per_end:                1;         /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.*/
+            uint32_t pes_end:                1;         /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.*/
+            uint32_t wpe_end:                1;         /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
+            uint32_t st_end:                 1;         /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
+            uint32_t mst_st_end:             1;         /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.*/
+            uint32_t reserved5:             27;         /*reserved*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t per_end:               1;          /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end:               1;          /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end:               1;          /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t st_end:                1;          /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end:            1;          /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t reserved5:            27;          /*reserved*/
+        };
+        uint32_t val;
+    } int_st;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    union {
+        struct {
+            uint32_t clk_en:     1;                     /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
+            uint32_t reserved1: 31;                         /*reserved*/
+        };
+        uint32_t val;
+    } clock_gate;
+    union {
+        struct {
+            uint32_t spi01_clk_sel: 2;                  /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz  the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz  the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/
+            uint32_t reserved2:        30;                  /*reserved*/
+        };
+        uint32_t val;
+    } core_clk_sel;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    union {
+        struct {
+            uint32_t date:      28;                     /*Version control register*/
+            uint32_t reserved28: 4;                     /*reserved*/
+        };
+        uint32_t val;
+    } date;
+} spi_mem_dev_t;
+extern spi_mem_dev_t SPIMEM0;
+extern spi_mem_dev_t SPIMEM1;
+
+_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "spi_mem_dev_t size error!");
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_SPI_MEM_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/spi_pins.h b/components/soc/esp32c3/include/soc/spi_pins.h
new file mode 100644
index 0000000000..b958be57cb
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/spi_pins.h
@@ -0,0 +1,39 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_SPI_PINS_H_
+#define _SOC_SPI_PINS_H_
+
+#define SPI_FUNC_NUM            0
+#define SPI_IOMUX_PIN_NUM_HD    12
+#define SPI_IOMUX_PIN_NUM_CS    14
+#define SPI_IOMUX_PIN_NUM_MOSI  16
+#define SPI_IOMUX_PIN_NUM_CLK   15
+#define SPI_IOMUX_PIN_NUM_MISO  17
+#define SPI_IOMUX_PIN_NUM_WP    13
+//TODO: add the next slot
+
+#define FSPI_FUNC_NUM           2
+#define FSPI_IOMUX_PIN_NUM_MISO 2
+#define FSPI_IOMUX_PIN_NUM_HD   4
+#define FSPI_IOMUX_PIN_NUM_WP   5
+#define FSPI_IOMUX_PIN_NUM_CLK  6
+#define FSPI_IOMUX_PIN_NUM_MOSI 7
+#define FSPI_IOMUX_PIN_NUM_CS   10
+
+//TODO: add the next slot
+
+//HSPI and VSPI have no iomux pins
+
+#endif
diff --git a/components/soc/esp32c3/include/soc/spi_reg.h b/components/soc/esp32c3/include/soc/spi_reg.h
new file mode 100644
index 0000000000..a08cb24f3c
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/spi_reg.h
@@ -0,0 +1,1443 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SPI_REG_H_
+#define _SOC_SPI_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+#define SPI_CMD_REG(i)          (REG_SPI_BASE(i) + 0x0)
+/* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
+/*description: User define command enable.  An operation will be triggered when the bit is set.
+ The bit will be cleared once the operation done.1: enable 0: disable. Can not b
+e changed by CONF_buf..*/
+#define SPI_USR    (BIT(24))
+#define SPI_USR_M  (BIT(24))
+#define SPI_USR_V  0x1
+#define SPI_USR_S  24
+/* SPI_UPDATE : WT ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Set this bit to synchronize SPI registers from APB clock domain into SPI module
+clock domain, which is only used in SPI master mode..*/
+#define SPI_UPDATE    (BIT(23))
+#define SPI_UPDATE_M  (BIT(23))
+#define SPI_UPDATE_V  0x1
+#define SPI_UPDATE_S  23
+/* SPI_CONF_BITLEN : R/W ;bitpos:[17:0] ;default: 18'd0 ; */
+/*description: Define the APB cycles of  SPI_CONF state. Can be configured in CONF state..*/
+#define SPI_CONF_BITLEN    0x0003FFFF
+#define SPI_CONF_BITLEN_M  ((SPI_CONF_BITLEN_V)<<(SPI_CONF_BITLEN_S))
+#define SPI_CONF_BITLEN_V  0x3FFFF
+#define SPI_CONF_BITLEN_S  0
+
+#define SPI_ADDR_REG(i)          (REG_SPI_BASE(i) + 0x4)
+/* SPI_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: Address to slave. Can be configured in CONF state..*/
+#define SPI_USR_ADDR_VALUE    0xFFFFFFFF
+#define SPI_USR_ADDR_VALUE_M  ((SPI_USR_ADDR_VALUE_V)<<(SPI_USR_ADDR_VALUE_S))
+#define SPI_USR_ADDR_VALUE_V  0xFFFFFFFF
+#define SPI_USR_ADDR_VALUE_S  0
+
+#define SPI_CTRL_REG(i)          (REG_SPI_BASE(i) + 0x8)
+/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be con
+figured in CONF state..*/
+#define SPI_WR_BIT_ORDER    (BIT(26))
+#define SPI_WR_BIT_ORDER_M  (BIT(26))
+#define SPI_WR_BIT_ORDER_V  0x1
+#define SPI_WR_BIT_ORDER_S  26
+/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF s
+tate..*/
+#define SPI_RD_BIT_ORDER    (BIT(25))
+#define SPI_RD_BIT_ORDER_M  (BIT(25))
+#define SPI_RD_BIT_ORDER_V  0x1
+#define SPI_RD_BIT_ORDER_S  25
+/* SPI_WP_POL : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low.  C
+an be configured in CONF state..*/
+#define SPI_WP_POL    (BIT(21))
+#define SPI_WP_POL_M  (BIT(21))
+#define SPI_WP_POL_V  0x1
+#define SPI_WP_POL_S  21
+/* SPI_HOLD_POL : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be co
+nfigured in CONF state..*/
+#define SPI_HOLD_POL    (BIT(20))
+#define SPI_HOLD_POL_M  (BIT(20))
+#define SPI_HOLD_POL_V  0x1
+#define SPI_HOLD_POL_S  20
+/* SPI_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
+CONF state..*/
+#define SPI_D_POL    (BIT(19))
+#define SPI_D_POL_M  (BIT(19))
+#define SPI_D_POL_V  0x1
+#define SPI_D_POL_S  19
+/* SPI_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
+CONF state..*/
+#define SPI_Q_POL    (BIT(18))
+#define SPI_Q_POL_M  (BIT(18))
+#define SPI_Q_POL_V  0x1
+#define SPI_Q_POL_S  18
+/* SPI_FREAD_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  C
+an be configured in CONF state..*/
+#define SPI_FREAD_QUAD    (BIT(15))
+#define SPI_FREAD_QUAD_M  (BIT(15))
+#define SPI_FREAD_QUAD_V  0x1
+#define SPI_FREAD_QUAD_S  15
+/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. C
+an be configured in CONF state..*/
+#define SPI_FREAD_DUAL    (BIT(14))
+#define SPI_FREAD_DUAL_M  (BIT(14))
+#define SPI_FREAD_DUAL_V  0x1
+#define SPI_FREAD_DUAL_S  14
+/* SPI_FCMD_QUAD : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Apply 4 signals during command phase 1:enable 0: disable. Can be configured in C
+ONF state..*/
+#define SPI_FCMD_QUAD    (BIT(9))
+#define SPI_FCMD_QUAD_M  (BIT(9))
+#define SPI_FCMD_QUAD_V  0x1
+#define SPI_FCMD_QUAD_S  9
+/* SPI_FCMD_DUAL : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Apply 2 signals during command phase 1:enable 0: disable. Can be configured in C
+ONF state..*/
+#define SPI_FCMD_DUAL    (BIT(8))
+#define SPI_FCMD_DUAL_M  (BIT(8))
+#define SPI_FCMD_DUAL_V  0x1
+#define SPI_FCMD_DUAL_S  8
+/* SPI_FADDR_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ state..*/
+#define SPI_FADDR_QUAD    (BIT(6))
+#define SPI_FADDR_QUAD_M  (BIT(6))
+#define SPI_FADDR_QUAD_V  0x1
+#define SPI_FADDR_QUAD_S  6
+/* SPI_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ state..*/
+#define SPI_FADDR_DUAL    (BIT(5))
+#define SPI_FADDR_DUAL_M  (BIT(5))
+#define SPI_FADDR_DUAL_V  0x1
+#define SPI_FADDR_DUAL_S  5
+/* SPI_DUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: In the dummy phase the signal level of spi is output by the spi controller. Can
+be configured in CONF state..*/
+#define SPI_DUMMY_OUT    (BIT(3))
+#define SPI_DUMMY_OUT_M  (BIT(3))
+#define SPI_DUMMY_OUT_V  0x1
+#define SPI_DUMMY_OUT_S  3
+
+#define SPI_CLOCK_REG(i)          (REG_SPI_BASE(i) + 0xC)
+/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from syst
+em clock. Can be configured in CONF state..*/
+#define SPI_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_CLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_CLK_EQU_SYSCLK_V  0x1
+#define SPI_CLK_EQU_SYSCLK_S  31
+/* SPI_CLKDIV_PRE : R/W ;bitpos:[21:18] ;default: 4'b0 ; */
+/*description: In the master mode it is pre-divider of spi_clk.  Can be configured in CONF stat
+e..*/
+#define SPI_CLKDIV_PRE    0x0000000F
+#define SPI_CLKDIV_PRE_M  ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S))
+#define SPI_CLKDIV_PRE_V  0xF
+#define SPI_CLKDIV_PRE_S  18
+/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */
+/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/
+(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state..*/
+#define SPI_CLKCNT_N    0x0000003F
+#define SPI_CLKCNT_N_M  ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S))
+#define SPI_CLKCNT_N_V  0x3F
+#define SPI_CLKCNT_N_S  12
+/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */
+/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
+must be 0. Can be configured in CONF state..*/
+#define SPI_CLKCNT_H    0x0000003F
+#define SPI_CLKCNT_H_M  ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S))
+#define SPI_CLKCNT_H_V  0x3F
+#define SPI_CLKCNT_H_S  6
+/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
+/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must b
+e 0. Can be configured in CONF state..*/
+#define SPI_CLKCNT_L    0x0000003F
+#define SPI_CLKCNT_L_M  ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S))
+#define SPI_CLKCNT_L_V  0x3F
+#define SPI_CLKCNT_L_S  0
+
+#define SPI_USER_REG(i)          (REG_SPI_BASE(i) + 0x10)
+/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: This bit enable the command phase of an operation. Can be configured in CONF sta
+te..*/
+#define SPI_USR_COMMAND    (BIT(31))
+#define SPI_USR_COMMAND_M  (BIT(31))
+#define SPI_USR_COMMAND_V  0x1
+#define SPI_USR_COMMAND_S  31
+/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: This bit enable the address phase of an operation. Can be configured in CONF sta
+te..*/
+#define SPI_USR_ADDR    (BIT(30))
+#define SPI_USR_ADDR_M  (BIT(30))
+#define SPI_USR_ADDR_V  0x1
+#define SPI_USR_ADDR_S  30
+/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: This bit enable the dummy phase of an operation. Can be configured in CONF state
+..*/
+#define SPI_USR_DUMMY    (BIT(29))
+#define SPI_USR_DUMMY_M  (BIT(29))
+#define SPI_USR_DUMMY_V  0x1
+#define SPI_USR_DUMMY_S  29
+/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: This bit enable the read-data phase of an operation. Can be configured in CONF s
+tate..*/
+#define SPI_USR_MISO    (BIT(28))
+#define SPI_USR_MISO_M  (BIT(28))
+#define SPI_USR_MISO_V  0x1
+#define SPI_USR_MISO_S  28
+/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: This bit enable the write-data phase of an operation. Can be configured in CONF
+state..*/
+#define SPI_USR_MOSI    (BIT(27))
+#define SPI_USR_MOSI_M  (BIT(27))
+#define SPI_USR_MOSI_V  0x1
+#define SPI_USR_MOSI_S  27
+/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: spi clock is disable in dummy phase when the bit is enable. Can be configured in
+ CONF state..*/
+#define SPI_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_USR_DUMMY_IDLE_M  (BIT(26))
+#define SPI_USR_DUMMY_IDLE_V  0x1
+#define SPI_USR_DUMMY_IDLE_S  26
+/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enabl
+e 0: disable.  Can be configured in CONF state..*/
+#define SPI_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI_USR_MOSI_HIGHPART_M  (BIT(25))
+#define SPI_USR_MOSI_HIGHPART_V  0x1
+#define SPI_USR_MOSI_HIGHPART_S  25
+/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
+ 0: disable. Can be configured in CONF state..*/
+#define SPI_USR_MISO_HIGHPART    (BIT(24))
+#define SPI_USR_MISO_HIGHPART_M  (BIT(24))
+#define SPI_USR_MISO_HIGHPART_V  0x1
+#define SPI_USR_MISO_HIGHPART_S  24
+/* SPI_SIO : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set the bit to enable 3-line half duplex communication mosi and miso signals sha
+re the same pin. 1: enable 0: disable. Can be configured in CONF state..*/
+#define SPI_SIO    (BIT(17))
+#define SPI_SIO_M  (BIT(17))
+#define SPI_SIO_V  0x1
+#define SPI_SIO_S  17
+/* SPI_USR_CONF_NXT : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
+will continue. 0: The seg-trans will end after the current SPI seg-trans or this
+ is not seg-trans mode. Can be configured in CONF state..*/
+#define SPI_USR_CONF_NXT    (BIT(15))
+#define SPI_USR_CONF_NXT_M  (BIT(15))
+#define SPI_USR_CONF_NXT_V  0x1
+#define SPI_USR_CONF_NXT_S  15
+/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 4 signals. Can be configured in CO
+NF state..*/
+#define SPI_FWRITE_QUAD    (BIT(13))
+#define SPI_FWRITE_QUAD_M  (BIT(13))
+#define SPI_FWRITE_QUAD_V  0x1
+#define SPI_FWRITE_QUAD_S  13
+/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 2 signals. Can be configured in CO
+NF state..*/
+#define SPI_FWRITE_DUAL    (BIT(12))
+#define SPI_FWRITE_DUAL_M  (BIT(12))
+#define SPI_FWRITE_DUAL_V  0x1
+#define SPI_FWRITE_DUAL_S  12
+/* SPI_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Ca
+n be configured in CONF state..*/
+#define SPI_CK_OUT_EDGE    (BIT(9))
+#define SPI_CK_OUT_EDGE_M  (BIT(9))
+#define SPI_CK_OUT_EDGE_V  0x1
+#define SPI_CK_OUT_EDGE_S  9
+/* SPI_RSCK_I_EDGE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck
+= !spi_ck_i. 1:rsck = spi_ck_i..*/
+#define SPI_RSCK_I_EDGE    (BIT(8))
+#define SPI_RSCK_I_EDGE_M  (BIT(8))
+#define SPI_RSCK_I_EDGE_V  0x1
+#define SPI_RSCK_I_EDGE_S  8
+/* SPI_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be co
+nfigured in CONF state..*/
+#define SPI_CS_SETUP    (BIT(7))
+#define SPI_CS_SETUP_M  (BIT(7))
+#define SPI_CS_SETUP_V  0x1
+#define SPI_CS_SETUP_S  7
+/* SPI_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be config
+ured in CONF state..*/
+#define SPI_CS_HOLD    (BIT(6))
+#define SPI_CS_HOLD_M  (BIT(6))
+#define SPI_CS_HOLD_V  0x1
+#define SPI_CS_HOLD_S  6
+/* SPI_TSCK_I_EDGE : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck
+= spi_ck_i. 1:tsck = !spi_ck_i..*/
+#define SPI_TSCK_I_EDGE    (BIT(5))
+#define SPI_TSCK_I_EDGE_M  (BIT(5))
+#define SPI_TSCK_I_EDGE_V  0x1
+#define SPI_TSCK_I_EDGE_S  5
+/* SPI_QPI_MODE : R/W/SS/SC ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others
+. Can be configured in CONF state..*/
+#define SPI_QPI_MODE    (BIT(3))
+#define SPI_QPI_MODE_M  (BIT(3))
+#define SPI_QPI_MODE_V  0x1
+#define SPI_QPI_MODE_S  3
+/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set the bit to enable full duplex communication. 1: enable 0: disable. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUTDIN    (BIT(0))
+#define SPI_DOUTDIN_M  (BIT(0))
+#define SPI_DOUTDIN_V  0x1
+#define SPI_DOUTDIN_S  0
+
+#define SPI_USER1_REG(i)          (REG_SPI_BASE(i) + 0x14)
+/* SPI_USR_ADDR_BITLEN : R/W ;bitpos:[31:27] ;default: 5'd23 ; */
+/*description: The length in bits of address phase. The register value shall be (bit_num-1). Ca
+n be configured in CONF state..*/
+#define SPI_USR_ADDR_BITLEN    0x0000001F
+#define SPI_USR_ADDR_BITLEN_M  ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S))
+#define SPI_USR_ADDR_BITLEN_V  0x1F
+#define SPI_USR_ADDR_BITLEN_S  27
+/* SPI_CS_HOLD_TIME : R/W ;bitpos:[26:22] ;default: 5'h1 ; */
+/*description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
+ Can be configured in CONF state..*/
+#define SPI_CS_HOLD_TIME    0x0000001F
+#define SPI_CS_HOLD_TIME_M  ((SPI_CS_HOLD_TIME_V)<<(SPI_CS_HOLD_TIME_S))
+#define SPI_CS_HOLD_TIME_V  0x1F
+#define SPI_CS_HOLD_TIME_S  22
+/* SPI_CS_SETUP_TIME : R/W ;bitpos:[21:17] ;default: 5'b0 ; */
+/*description: (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setu
+p bit. Can be configured in CONF state..*/
+#define SPI_CS_SETUP_TIME    0x0000001F
+#define SPI_CS_SETUP_TIME_M  ((SPI_CS_SETUP_TIME_V)<<(SPI_CS_SETUP_TIME_S))
+#define SPI_CS_SETUP_TIME_V  0x1F
+#define SPI_CS_SETUP_TIME_S  17
+/* SPI_MST_WFULL_ERR_END_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
+ FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid
+ in GP-SPI master FD/HD-mode..*/
+#define SPI_MST_WFULL_ERR_END_EN    (BIT(16))
+#define SPI_MST_WFULL_ERR_END_EN_M  (BIT(16))
+#define SPI_MST_WFULL_ERR_END_EN_V  0x1
+#define SPI_MST_WFULL_ERR_END_EN_S  16
+/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */
+/*description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_
+num-1). Can be configured in CONF state..*/
+#define SPI_USR_DUMMY_CYCLELEN    0x000000FF
+#define SPI_USR_DUMMY_CYCLELEN_M  ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S))
+#define SPI_USR_DUMMY_CYCLELEN_V  0xFF
+#define SPI_USR_DUMMY_CYCLELEN_S  0
+
+#define SPI_USER2_REG(i)          (REG_SPI_BASE(i) + 0x18)
+/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
+/*description: The length in bits of command phase. The register value shall be (bit_num-1). Ca
+n be configured in CONF state..*/
+#define SPI_USR_COMMAND_BITLEN    0x0000000F
+#define SPI_USR_COMMAND_BITLEN_M  ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S))
+#define SPI_USR_COMMAND_BITLEN_V  0xF
+#define SPI_USR_COMMAND_BITLEN_S  28
+/* SPI_MST_REMPTY_ERR_END_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */
+/*description: 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI m
+aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty erro
+r is valid in GP-SPI master FD/HD-mode..*/
+#define SPI_MST_REMPTY_ERR_END_EN    (BIT(27))
+#define SPI_MST_REMPTY_ERR_END_EN_M  (BIT(27))
+#define SPI_MST_REMPTY_ERR_END_EN_V  0x1
+#define SPI_MST_REMPTY_ERR_END_EN_S  27
+/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value of  command. Can be configured in CONF state..*/
+#define SPI_USR_COMMAND_VALUE    0x0000FFFF
+#define SPI_USR_COMMAND_VALUE_M  ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S))
+#define SPI_USR_COMMAND_VALUE_V  0xFFFF
+#define SPI_USR_COMMAND_VALUE_S  0
+
+#define SPI_MS_DLEN_REG(i)          (REG_SPI_BASE(i) + 0x1C)
+/* SPI_MS_DATA_BITLEN : R/W ;bitpos:[17:0] ;default: 18'b0 ; */
+/*description: The value of these bits is the configured SPI transmission data bit length in ma
+ster mode DMA controlled transfer or CPU controlled transfer. The value is also
+the configured bit length in slave mode DMA RX controlled transfer. The register
+ value shall be (bit_num-1). Can be configured in CONF state..*/
+#define SPI_MS_DATA_BITLEN    0x0003FFFF
+#define SPI_MS_DATA_BITLEN_M  ((SPI_MS_DATA_BITLEN_V)<<(SPI_MS_DATA_BITLEN_S))
+#define SPI_MS_DATA_BITLEN_V  0x3FFFF
+#define SPI_MS_DATA_BITLEN_S  0
+
+#define SPI_MISC_REG(i)          (REG_SPI_BASE(i) + 0x20)
+/* SPI_QUAD_DIN_PIN_SWAP : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 1:  spi quad input swap enable  0:  spi quad input swap disable. Can be configur
+ed in CONF state..*/
+#define SPI_QUAD_DIN_PIN_SWAP    (BIT(31))
+#define SPI_QUAD_DIN_PIN_SWAP_M  (BIT(31))
+#define SPI_QUAD_DIN_PIN_SWAP_V  0x1
+#define SPI_QUAD_DIN_PIN_SWAP_S  31
+/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: spi cs line keep low when the bit is set. Can be configured in CONF state..*/
+#define SPI_CS_KEEP_ACTIVE    (BIT(30))
+#define SPI_CS_KEEP_ACTIVE_M  (BIT(30))
+#define SPI_CS_KEEP_ACTIVE_V  0x1
+#define SPI_CS_KEEP_ACTIVE_S  30
+/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: 1: spi clk line is high when idle     0: spi clk line is low when idle. Can be c
+onfigured in CONF state..*/
+#define SPI_CK_IDLE_EDGE    (BIT(29))
+#define SPI_CK_IDLE_EDGE_M  (BIT(29))
+#define SPI_CK_IDLE_EDGE_V  0x1
+#define SPI_CK_IDLE_EDGE_S  29
+/* SPI_SLAVE_CS_POL : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
+CONF state..*/
+#define SPI_SLAVE_CS_POL    (BIT(23))
+#define SPI_SLAVE_CS_POL_M  (BIT(23))
+#define SPI_SLAVE_CS_POL_V  0x1
+#define SPI_SLAVE_CS_POL_S  23
+/* SPI_MASTER_CS_POL : R/W ;bitpos:[12:7] ;default: 6'b0 ; */
+/*description: In the master mode the bits are the polarity of spi cs line, the value is equiva
+lent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state..*/
+#define SPI_MASTER_CS_POL    0x0000003F
+#define SPI_MASTER_CS_POL_M  ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S))
+#define SPI_MASTER_CS_POL_V  0x3F
+#define SPI_MASTER_CS_POL_S  7
+/* SPI_CK_DIS : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: 1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state..*/
+#define SPI_CK_DIS    (BIT(6))
+#define SPI_CK_DIS_M  (BIT(6))
+#define SPI_CK_DIS_V  0x1
+#define SPI_CK_DIS_S  6
+/* SPI_CS5_DIS : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS5_DIS    (BIT(5))
+#define SPI_CS5_DIS_M  (BIT(5))
+#define SPI_CS5_DIS_V  0x1
+#define SPI_CS5_DIS_S  5
+/* SPI_CS4_DIS : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS4_DIS    (BIT(4))
+#define SPI_CS4_DIS_M  (BIT(4))
+#define SPI_CS4_DIS_V  0x1
+#define SPI_CS4_DIS_S  4
+/* SPI_CS3_DIS : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS3_DIS    (BIT(3))
+#define SPI_CS3_DIS_M  (BIT(3))
+#define SPI_CS3_DIS_V  0x1
+#define SPI_CS3_DIS_S  3
+/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS2_DIS    (BIT(2))
+#define SPI_CS2_DIS_M  (BIT(2))
+#define SPI_CS2_DIS_V  0x1
+#define SPI_CS2_DIS_S  2
+/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS1_DIS    (BIT(1))
+#define SPI_CS1_DIS_M  (BIT(1))
+#define SPI_CS1_DIS_V  0x1
+#define SPI_CS1_DIS_S  1
+/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS0_DIS    (BIT(0))
+#define SPI_CS0_DIS_M  (BIT(0))
+#define SPI_CS0_DIS_V  0x1
+#define SPI_CS0_DIS_S  0
+
+#define SPI_DIN_MODE_REG(i)          (REG_SPI_BASE(i) + 0x24)
+/* SPI_TIMING_HCLK_ACTIVE : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: 1:enable hclk in SPI input timing module.  0: disable it. Can be configured in C
+ONF state..*/
+#define SPI_TIMING_HCLK_ACTIVE    (BIT(16))
+#define SPI_TIMING_HCLK_ACTIVE_M  (BIT(16))
+#define SPI_TIMING_HCLK_ACTIVE_V  0x1
+#define SPI_TIMING_HCLK_ACTIVE_S  16
+/* SPI_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN3_MODE    0x00000003
+#define SPI_DIN3_MODE_M  ((SPI_DIN3_MODE_V)<<(SPI_DIN3_MODE_S))
+#define SPI_DIN3_MODE_V  0x3
+#define SPI_DIN3_MODE_S  6
+/* SPI_DIN2_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN2_MODE    0x00000003
+#define SPI_DIN2_MODE_M  ((SPI_DIN2_MODE_V)<<(SPI_DIN2_MODE_S))
+#define SPI_DIN2_MODE_V  0x3
+#define SPI_DIN2_MODE_S  4
+/* SPI_DIN1_MODE : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN1_MODE    0x00000003
+#define SPI_DIN1_MODE_M  ((SPI_DIN1_MODE_V)<<(SPI_DIN1_MODE_S))
+#define SPI_DIN1_MODE_V  0x3
+#define SPI_DIN1_MODE_S  2
+/* SPI_DIN0_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN0_MODE    0x00000003
+#define SPI_DIN0_MODE_M  ((SPI_DIN0_MODE_V)<<(SPI_DIN0_MODE_S))
+#define SPI_DIN0_MODE_V  0x3
+#define SPI_DIN0_MODE_S  0
+
+#define SPI_DIN_NUM_REG(i)          (REG_SPI_BASE(i) + 0x28)
+/* SPI_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN3_NUM    0x00000003
+#define SPI_DIN3_NUM_M  ((SPI_DIN3_NUM_V)<<(SPI_DIN3_NUM_S))
+#define SPI_DIN3_NUM_V  0x3
+#define SPI_DIN3_NUM_S  6
+/* SPI_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN2_NUM    0x00000003
+#define SPI_DIN2_NUM_M  ((SPI_DIN2_NUM_V)<<(SPI_DIN2_NUM_S))
+#define SPI_DIN2_NUM_V  0x3
+#define SPI_DIN2_NUM_S  4
+/* SPI_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN1_NUM    0x00000003
+#define SPI_DIN1_NUM_M  ((SPI_DIN1_NUM_V)<<(SPI_DIN1_NUM_S))
+#define SPI_DIN1_NUM_V  0x3
+#define SPI_DIN1_NUM_S  2
+/* SPI_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN0_NUM    0x00000003
+#define SPI_DIN0_NUM_M  ((SPI_DIN0_NUM_V)<<(SPI_DIN0_NUM_S))
+#define SPI_DIN0_NUM_V  0x3
+#define SPI_DIN0_NUM_S  0
+
+#define SPI_DOUT_MODE_REG(i)          (REG_SPI_BASE(i) + 0x2C)
+/* SPI_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT3_MODE    (BIT(3))
+#define SPI_DOUT3_MODE_M  (BIT(3))
+#define SPI_DOUT3_MODE_V  0x1
+#define SPI_DOUT3_MODE_S  3
+/* SPI_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT2_MODE    (BIT(2))
+#define SPI_DOUT2_MODE_M  (BIT(2))
+#define SPI_DOUT2_MODE_V  0x1
+#define SPI_DOUT2_MODE_S  2
+/* SPI_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT1_MODE    (BIT(1))
+#define SPI_DOUT1_MODE_M  (BIT(1))
+#define SPI_DOUT1_MODE_V  0x1
+#define SPI_DOUT1_MODE_S  1
+/* SPI_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT0_MODE    (BIT(0))
+#define SPI_DOUT0_MODE_M  (BIT(0))
+#define SPI_DOUT0_MODE_V  0x1
+#define SPI_DOUT0_MODE_S  0
+
+#define SPI_DMA_CONF_REG(i)          (REG_SPI_BASE(i) + 0x30)
+/* SPI_DMA_AFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave
+DMA controlled mode transfer..*/
+#define SPI_DMA_AFIFO_RST    (BIT(31))
+#define SPI_DMA_AFIFO_RST_M  (BIT(31))
+#define SPI_DMA_AFIFO_RST_V  0x1
+#define SPI_DMA_AFIFO_RST_S  31
+/* SPI_BUF_AFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
+ controlled mode transfer and master mode transfer..*/
+#define SPI_BUF_AFIFO_RST    (BIT(30))
+#define SPI_BUF_AFIFO_RST_M  (BIT(30))
+#define SPI_BUF_AFIFO_RST_V  0x1
+#define SPI_BUF_AFIFO_RST_S  30
+/* SPI_RX_AFIFO_RST : WT ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
+slave mode transfer..*/
+#define SPI_RX_AFIFO_RST    (BIT(29))
+#define SPI_RX_AFIFO_RST_M  (BIT(29))
+#define SPI_RX_AFIFO_RST_V  0x1
+#define SPI_RX_AFIFO_RST_S  29
+/* SPI_DMA_TX_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI DMA controlled send data mode..*/
+#define SPI_DMA_TX_ENA    (BIT(28))
+#define SPI_DMA_TX_ENA_M  (BIT(28))
+#define SPI_DMA_TX_ENA_V  0x1
+#define SPI_DMA_TX_ENA_S  28
+/* SPI_DMA_RX_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: Set this bit to enable SPI DMA controlled receive data mode..*/
+#define SPI_DMA_RX_ENA    (BIT(27))
+#define SPI_DMA_RX_ENA_M  (BIT(27))
+#define SPI_DMA_RX_ENA_V  0x1
+#define SPI_DMA_RX_ENA_S  27
+/* SPI_RX_EOF_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal t
+o the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_d
+ma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_don
+e in seg-trans..*/
+#define SPI_RX_EOF_EN    (BIT(21))
+#define SPI_RX_EOF_EN_M  (BIT(21))
+#define SPI_RX_EOF_EN_V  0x1
+#define SPI_RX_EOF_EN_S  21
+/* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_e
+mpty_vld is cleared by spi_trans_done..*/
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN    (BIT(20))
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M  (BIT(20))
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V  0x1
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S  20
+/* SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full
+_vld is cleared by spi_trans_done..*/
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN    (BIT(19))
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M  (BIT(19))
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V  0x1
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S  19
+/* SPI_DMA_SLV_SEG_TRANS_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable..*/
+#define SPI_DMA_SLV_SEG_TRANS_EN    (BIT(18))
+#define SPI_DMA_SLV_SEG_TRANS_EN_M  (BIT(18))
+#define SPI_DMA_SLV_SEG_TRANS_EN_V  0x1
+#define SPI_DMA_SLV_SEG_TRANS_EN_S  18
+
+#define SPI_DMA_INT_ENA_REG(i)          (REG_SPI_BASE(i) + 0x34)
+/* SPI_APP1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_APP1_INT interrupt..*/
+#define SPI_APP1_INT_ENA    (BIT(20))
+#define SPI_APP1_INT_ENA_M  (BIT(20))
+#define SPI_APP1_INT_ENA_V  0x1
+#define SPI_APP1_INT_ENA_S  20
+/* SPI_APP2_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_APP2_INT interrupt..*/
+#define SPI_APP2_INT_ENA    (BIT(19))
+#define SPI_APP2_INT_ENA_M  (BIT(19))
+#define SPI_APP2_INT_ENA_V  0x1
+#define SPI_APP2_INT_ENA_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S  17
+/* SPI_SLV_CMD_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt..*/
+#define SPI_SLV_CMD_ERR_INT_ENA    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ENA_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ENA_V  0x1
+#define SPI_SLV_CMD_ERR_INT_ENA_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S  15
+/* SPI_SEG_MAGIC_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
+#define SPI_SEG_MAGIC_ERR_INT_ENA    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ENA_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ENA_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_ENA_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S  13
+/* SPI_TRANS_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_TRANS_DONE_INT interrupt..*/
+#define SPI_TRANS_DONE_INT_ENA    (BIT(12))
+#define SPI_TRANS_DONE_INT_ENA_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_ENA_V  0x1
+#define SPI_TRANS_DONE_INT_ENA_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_WR_BUF_DONE_INT_ENA    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_RD_BUF_DONE_INT_ENA    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_WR_DMA_DONE_INT_ENA    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_RD_DMA_DONE_INT_ENA    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_S  8
+/* SPI_SLV_CMDA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMDA interrupt..*/
+#define SPI_SLV_CMDA_INT_ENA    (BIT(7))
+#define SPI_SLV_CMDA_INT_ENA_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_ENA_V  0x1
+#define SPI_SLV_CMDA_INT_ENA_S  7
+/* SPI_SLV_CMD9_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMD9 interrupt..*/
+#define SPI_SLV_CMD9_INT_ENA    (BIT(6))
+#define SPI_SLV_CMD9_INT_ENA_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_ENA_V  0x1
+#define SPI_SLV_CMD9_INT_ENA_S  6
+/* SPI_SLV_CMD8_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMD8 interrupt..*/
+#define SPI_SLV_CMD8_INT_ENA    (BIT(5))
+#define SPI_SLV_CMD8_INT_ENA_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_ENA_V  0x1
+#define SPI_SLV_CMD8_INT_ENA_S  5
+/* SPI_SLV_CMD7_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMD7 interrupt..*/
+#define SPI_SLV_CMD7_INT_ENA    (BIT(4))
+#define SPI_SLV_CMD7_INT_ENA_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_ENA_V  0x1
+#define SPI_SLV_CMD7_INT_ENA_S  4
+/* SPI_SLV_EN_QPI_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave En_QPI interrupt..*/
+#define SPI_SLV_EN_QPI_INT_ENA    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ENA_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ENA_V  0x1
+#define SPI_SLV_EN_QPI_INT_ENA_S  3
+/* SPI_SLV_EX_QPI_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave Ex_QPI interrupt..*/
+#define SPI_SLV_EX_QPI_INT_ENA    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ENA_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ENA_V  0x1
+#define SPI_SLV_EX_QPI_INT_ENA_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S  0
+
+#define SPI_DMA_INT_CLR_REG(i)          (REG_SPI_BASE(i) + 0x38)
+/* SPI_APP1_INT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_APP1_INT interrupt..*/
+#define SPI_APP1_INT_CLR    (BIT(20))
+#define SPI_APP1_INT_CLR_M  (BIT(20))
+#define SPI_APP1_INT_CLR_V  0x1
+#define SPI_APP1_INT_CLR_S  20
+/* SPI_APP2_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_APP2_INT interrupt..*/
+#define SPI_APP2_INT_CLR    (BIT(19))
+#define SPI_APP2_INT_CLR_M  (BIT(19))
+#define SPI_APP2_INT_CLR_V  0x1
+#define SPI_APP2_INT_CLR_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S  17
+/* SPI_SLV_CMD_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt..*/
+#define SPI_SLV_CMD_ERR_INT_CLR    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_CLR_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_CLR_V  0x1
+#define SPI_SLV_CMD_ERR_INT_CLR_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S  15
+/* SPI_SEG_MAGIC_ERR_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
+#define SPI_SEG_MAGIC_ERR_INT_CLR    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_CLR_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_CLR_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_CLR_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S  13
+/* SPI_TRANS_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_TRANS_DONE_INT interrupt..*/
+#define SPI_TRANS_DONE_INT_CLR    (BIT(12))
+#define SPI_TRANS_DONE_INT_CLR_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_CLR_V  0x1
+#define SPI_TRANS_DONE_INT_CLR_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_WR_BUF_DONE_INT_CLR    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_RD_BUF_DONE_INT_CLR    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_WR_DMA_DONE_INT_CLR    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_RD_DMA_DONE_INT_CLR    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_S  8
+/* SPI_SLV_CMDA_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMDA interrupt..*/
+#define SPI_SLV_CMDA_INT_CLR    (BIT(7))
+#define SPI_SLV_CMDA_INT_CLR_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_CLR_V  0x1
+#define SPI_SLV_CMDA_INT_CLR_S  7
+/* SPI_SLV_CMD9_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMD9 interrupt..*/
+#define SPI_SLV_CMD9_INT_CLR    (BIT(6))
+#define SPI_SLV_CMD9_INT_CLR_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_CLR_V  0x1
+#define SPI_SLV_CMD9_INT_CLR_S  6
+/* SPI_SLV_CMD8_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMD8 interrupt..*/
+#define SPI_SLV_CMD8_INT_CLR    (BIT(5))
+#define SPI_SLV_CMD8_INT_CLR_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_CLR_V  0x1
+#define SPI_SLV_CMD8_INT_CLR_S  5
+/* SPI_SLV_CMD7_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMD7 interrupt..*/
+#define SPI_SLV_CMD7_INT_CLR    (BIT(4))
+#define SPI_SLV_CMD7_INT_CLR_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_CLR_V  0x1
+#define SPI_SLV_CMD7_INT_CLR_S  4
+/* SPI_SLV_EN_QPI_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave En_QPI interrupt..*/
+#define SPI_SLV_EN_QPI_INT_CLR    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_CLR_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_CLR_V  0x1
+#define SPI_SLV_EN_QPI_INT_CLR_S  3
+/* SPI_SLV_EX_QPI_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave Ex_QPI interrupt..*/
+#define SPI_SLV_EX_QPI_INT_CLR    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_CLR_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_CLR_V  0x1
+#define SPI_SLV_EX_QPI_INT_CLR_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S  0
+
+#define SPI_DMA_INT_RAW_REG(i)          (REG_SPI_BASE(i) + 0x3C)
+/* SPI_APP1_INT_RAW : R/W/WTC ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_APP1_INT interrupt. The value is only controlled by applicat
+ion..*/
+#define SPI_APP1_INT_RAW    (BIT(20))
+#define SPI_APP1_INT_RAW_M  (BIT(20))
+#define SPI_APP1_INT_RAW_V  0x1
+#define SPI_APP1_INT_RAW_S  20
+/* SPI_APP2_INT_RAW : R/W/WTC ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_APP2_INT interrupt. The value is only controlled by applicat
+ion..*/
+#define SPI_APP2_INT_RAW    (BIT(19))
+#define SPI_APP2_INT_RAW_M  (BIT(19))
+#define SPI_APP2_INT_RAW_V  0x1
+#define SPI_APP2_INT_RAW_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
+AFIFO read-empty error when SPI outputs data in master mode. 0: Others..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
+ write-full error when SPI inputs data in master mode. 0: Others..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S  17
+/* SPI_SLV_CMD_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
+ current SPI slave HD mode transmission is not supported. 0: Others..*/
+#define SPI_SLV_CMD_ERR_INT_RAW    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_RAW_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_RAW_V  0x1
+#define SPI_SLV_CMD_ERR_INT_RAW_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data addres
+s of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission
+ is bigger than 63. 0: Others..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S  15
+/* SPI_SEG_MAGIC_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buff
+er is error in the DMA seg-conf-trans. 0: others..*/
+#define SPI_SEG_MAGIC_ERR_INT_RAW    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_RAW_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_RAW_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_RAW_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-du
+plex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And da
+ta has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is
+not ended or not occurred. .*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S  13
+/* SPI_TRANS_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
+ ended. 0: others..*/
+#define SPI_TRANS_DONE_INT_RAW    (BIT(12))
+#define SPI_TRANS_DONE_INT_RAW_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_RAW_V  0x1
+#define SPI_TRANS_DONE_INT_RAW_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_WR_BUF_DONE_INT_RAW    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_RD_BUF_DONE_INT_RAW    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_WR_DMA_DONE_INT_RAW    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_RD_DMA_DONE_INT_RAW    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_S  8
+/* SPI_SLV_CMDA_INT_RAW : R/W/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMDA_INT_RAW    (BIT(7))
+#define SPI_SLV_CMDA_INT_RAW_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_RAW_V  0x1
+#define SPI_SLV_CMDA_INT_RAW_S  7
+/* SPI_SLV_CMD9_INT_RAW : R/W/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMD9_INT_RAW    (BIT(6))
+#define SPI_SLV_CMD9_INT_RAW_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_RAW_V  0x1
+#define SPI_SLV_CMD9_INT_RAW_S  6
+/* SPI_SLV_CMD8_INT_RAW : R/W/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMD8_INT_RAW    (BIT(5))
+#define SPI_SLV_CMD8_INT_RAW_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_RAW_V  0x1
+#define SPI_SLV_CMD8_INT_RAW_S  5
+/* SPI_SLV_CMD7_INT_RAW : R/W/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMD7_INT_RAW    (BIT(4))
+#define SPI_SLV_CMD7_INT_RAW_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_RAW_V  0x1
+#define SPI_SLV_CMD7_INT_RAW_S  4
+/* SPI_SLV_EN_QPI_INT_RAW : R/W/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmissio
+n is ended. 0: Others..*/
+#define SPI_SLV_EN_QPI_INT_RAW    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_RAW_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_RAW_V  0x1
+#define SPI_SLV_EN_QPI_INT_RAW_S  3
+/* SPI_SLV_EX_QPI_INT_RAW : R/W/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmissio
+n is ended. 0: Others..*/
+#define SPI_SLV_EX_QPI_INT_RAW    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_RAW_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_RAW_V  0x1
+#define SPI_SLV_EX_QPI_INT_RAW_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
+ master mode and send out all 0 in slave mode.  0: Others.  .*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose
+the receive data.  0: Others.  .*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S  0
+
+#define SPI_DMA_INT_ST_REG(i)          (REG_SPI_BASE(i) + 0x40)
+/* SPI_APP1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The status bit for SPI_APP1_INT interrupt..*/
+#define SPI_APP1_INT_ST    (BIT(20))
+#define SPI_APP1_INT_ST_M  (BIT(20))
+#define SPI_APP1_INT_ST_V  0x1
+#define SPI_APP1_INT_ST_S  20
+/* SPI_APP2_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The status bit for SPI_APP2_INT interrupt..*/
+#define SPI_APP2_INT_ST    (BIT(19))
+#define SPI_APP2_INT_ST_M  (BIT(19))
+#define SPI_APP2_INT_ST_V  0x1
+#define SPI_APP2_INT_ST_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S  17
+/* SPI_SLV_CMD_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_CMD_ERR_INT interrupt..*/
+#define SPI_SLV_CMD_ERR_INT_ST    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ST_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ST_V  0x1
+#define SPI_SLV_CMD_ERR_INT_ST_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S  15
+/* SPI_SEG_MAGIC_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
+#define SPI_SEG_MAGIC_ERR_INT_ST    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ST_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ST_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_ST_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S  13
+/* SPI_TRANS_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The status bit for SPI_TRANS_DONE_INT interrupt..*/
+#define SPI_TRANS_DONE_INT_ST    (BIT(12))
+#define SPI_TRANS_DONE_INT_ST_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_ST_V  0x1
+#define SPI_TRANS_DONE_INT_ST_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_WR_BUF_DONE_INT_ST    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ST_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ST_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_ST_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_RD_BUF_DONE_INT_ST    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ST_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ST_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_ST_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_WR_DMA_DONE_INT_ST    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ST_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ST_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_ST_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_RD_DMA_DONE_INT_ST    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ST_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ST_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_ST_S  8
+/* SPI_SLV_CMDA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMDA interrupt..*/
+#define SPI_SLV_CMDA_INT_ST    (BIT(7))
+#define SPI_SLV_CMDA_INT_ST_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_ST_V  0x1
+#define SPI_SLV_CMDA_INT_ST_S  7
+/* SPI_SLV_CMD9_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMD9 interrupt..*/
+#define SPI_SLV_CMD9_INT_ST    (BIT(6))
+#define SPI_SLV_CMD9_INT_ST_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_ST_V  0x1
+#define SPI_SLV_CMD9_INT_ST_S  6
+/* SPI_SLV_CMD8_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMD8 interrupt..*/
+#define SPI_SLV_CMD8_INT_ST    (BIT(5))
+#define SPI_SLV_CMD8_INT_ST_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_ST_V  0x1
+#define SPI_SLV_CMD8_INT_ST_S  5
+/* SPI_SLV_CMD7_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMD7 interrupt..*/
+#define SPI_SLV_CMD7_INT_ST    (BIT(4))
+#define SPI_SLV_CMD7_INT_ST_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_ST_V  0x1
+#define SPI_SLV_CMD7_INT_ST_S  4
+/* SPI_SLV_EN_QPI_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave En_QPI interrupt..*/
+#define SPI_SLV_EN_QPI_INT_ST    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ST_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ST_V  0x1
+#define SPI_SLV_EN_QPI_INT_ST_S  3
+/* SPI_SLV_EX_QPI_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave Ex_QPI interrupt..*/
+#define SPI_SLV_EX_QPI_INT_ST    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ST_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ST_V  0x1
+#define SPI_SLV_EX_QPI_INT_ST_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S  0
+
+#define SPI_W0_REG(i)          (REG_SPI_BASE(i) + 0x98)
+/* SPI_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF0    0xFFFFFFFF
+#define SPI_BUF0_M  ((SPI_BUF0_V)<<(SPI_BUF0_S))
+#define SPI_BUF0_V  0xFFFFFFFF
+#define SPI_BUF0_S  0
+
+#define SPI_W1_REG(i)          (REG_SPI_BASE(i) + 0x9C)
+/* SPI_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF1    0xFFFFFFFF
+#define SPI_BUF1_M  ((SPI_BUF1_V)<<(SPI_BUF1_S))
+#define SPI_BUF1_V  0xFFFFFFFF
+#define SPI_BUF1_S  0
+
+#define SPI_W2_REG(i)          (REG_SPI_BASE(i) + 0xA0)
+/* SPI_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF2    0xFFFFFFFF
+#define SPI_BUF2_M  ((SPI_BUF2_V)<<(SPI_BUF2_S))
+#define SPI_BUF2_V  0xFFFFFFFF
+#define SPI_BUF2_S  0
+
+#define SPI_W3_REG(i)          (REG_SPI_BASE(i) + 0xA4)
+/* SPI_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF3    0xFFFFFFFF
+#define SPI_BUF3_M  ((SPI_BUF3_V)<<(SPI_BUF3_S))
+#define SPI_BUF3_V  0xFFFFFFFF
+#define SPI_BUF3_S  0
+
+#define SPI_W4_REG(i)          (REG_SPI_BASE(i) + 0xA8)
+/* SPI_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF4    0xFFFFFFFF
+#define SPI_BUF4_M  ((SPI_BUF4_V)<<(SPI_BUF4_S))
+#define SPI_BUF4_V  0xFFFFFFFF
+#define SPI_BUF4_S  0
+
+#define SPI_W5_REG(i)          (REG_SPI_BASE(i) + 0xAC)
+/* SPI_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF5    0xFFFFFFFF
+#define SPI_BUF5_M  ((SPI_BUF5_V)<<(SPI_BUF5_S))
+#define SPI_BUF5_V  0xFFFFFFFF
+#define SPI_BUF5_S  0
+
+#define SPI_W6_REG(i)          (REG_SPI_BASE(i) + 0xB0)
+/* SPI_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF6    0xFFFFFFFF
+#define SPI_BUF6_M  ((SPI_BUF6_V)<<(SPI_BUF6_S))
+#define SPI_BUF6_V  0xFFFFFFFF
+#define SPI_BUF6_S  0
+
+#define SPI_W7_REG(i)          (REG_SPI_BASE(i) + 0xB4)
+/* SPI_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF7    0xFFFFFFFF
+#define SPI_BUF7_M  ((SPI_BUF7_V)<<(SPI_BUF7_S))
+#define SPI_BUF7_V  0xFFFFFFFF
+#define SPI_BUF7_S  0
+
+#define SPI_W8_REG(i)          (REG_SPI_BASE(i) + 0xB8)
+/* SPI_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF8    0xFFFFFFFF
+#define SPI_BUF8_M  ((SPI_BUF8_V)<<(SPI_BUF8_S))
+#define SPI_BUF8_V  0xFFFFFFFF
+#define SPI_BUF8_S  0
+
+#define SPI_W9_REG(i)          (REG_SPI_BASE(i) + 0xBC)
+/* SPI_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF9    0xFFFFFFFF
+#define SPI_BUF9_M  ((SPI_BUF9_V)<<(SPI_BUF9_S))
+#define SPI_BUF9_V  0xFFFFFFFF
+#define SPI_BUF9_S  0
+
+#define SPI_W10_REG(i)          (REG_SPI_BASE(i) + 0xC0)
+/* SPI_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF10    0xFFFFFFFF
+#define SPI_BUF10_M  ((SPI_BUF10_V)<<(SPI_BUF10_S))
+#define SPI_BUF10_V  0xFFFFFFFF
+#define SPI_BUF10_S  0
+
+#define SPI_W11_REG(i)          (REG_SPI_BASE(i) + 0xC4)
+/* SPI_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF11    0xFFFFFFFF
+#define SPI_BUF11_M  ((SPI_BUF11_V)<<(SPI_BUF11_S))
+#define SPI_BUF11_V  0xFFFFFFFF
+#define SPI_BUF11_S  0
+
+#define SPI_W12_REG(i)          (REG_SPI_BASE(i) + 0xC8)
+/* SPI_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF12    0xFFFFFFFF
+#define SPI_BUF12_M  ((SPI_BUF12_V)<<(SPI_BUF12_S))
+#define SPI_BUF12_V  0xFFFFFFFF
+#define SPI_BUF12_S  0
+
+#define SPI_W13_REG(i)          (REG_SPI_BASE(i) + 0xCC)
+/* SPI_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF13    0xFFFFFFFF
+#define SPI_BUF13_M  ((SPI_BUF13_V)<<(SPI_BUF13_S))
+#define SPI_BUF13_V  0xFFFFFFFF
+#define SPI_BUF13_S  0
+
+#define SPI_W14_REG(i)          (REG_SPI_BASE(i) + 0xD0)
+/* SPI_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF14    0xFFFFFFFF
+#define SPI_BUF14_M  ((SPI_BUF14_V)<<(SPI_BUF14_S))
+#define SPI_BUF14_V  0xFFFFFFFF
+#define SPI_BUF14_S  0
+
+#define SPI_W15_REG(i)          (REG_SPI_BASE(i) + 0xD4)
+/* SPI_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF15    0xFFFFFFFF
+#define SPI_BUF15_M  ((SPI_BUF15_V)<<(SPI_BUF15_S))
+#define SPI_BUF15_V  0xFFFFFFFF
+#define SPI_BUF15_S  0
+
+#define SPI_SLAVE_REG(i)          (REG_SPI_BASE(i) + 0xE0)
+/* SPI_USR_CONF : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-tra
+ns will start. 0: This is not seg-trans mode..*/
+#define SPI_USR_CONF    (BIT(28))
+#define SPI_USR_CONF_M  (BIT(28))
+#define SPI_USR_CONF_V  0x1
+#define SPI_USR_CONF_S  28
+/* SPI_SOFT_RESET : WT ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Software reset enable, reset the spi clock line cs line and data lines. Can be c
+onfigured in CONF state..*/
+#define SPI_SOFT_RESET    (BIT(27))
+#define SPI_SOFT_RESET_M  (BIT(27))
+#define SPI_SOFT_RESET_V  0x1
+#define SPI_SOFT_RESET_S  27
+/* SPI_SLAVE_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set SPI work mode. 1: slave mode 0: master mode..*/
+#define SPI_SLAVE_MODE    (BIT(26))
+#define SPI_SLAVE_MODE_M  (BIT(26))
+#define SPI_SLAVE_MODE_V  0x1
+#define SPI_SLAVE_MODE_S  26
+/* SPI_DMA_SEG_MAGIC_VALUE : R/W ;bitpos:[25:22] ;default: 4'd10 ; */
+/*description: The magic value of BM table in master DMA seg-trans..*/
+#define SPI_DMA_SEG_MAGIC_VALUE    0x0000000F
+#define SPI_DMA_SEG_MAGIC_VALUE_M  ((SPI_DMA_SEG_MAGIC_VALUE_V)<<(SPI_DMA_SEG_MAGIC_VALUE_S))
+#define SPI_DMA_SEG_MAGIC_VALUE_V  0xF
+#define SPI_DMA_SEG_MAGIC_VALUE_S  22
+/* SPI_SLV_WRBUF_BITLEN_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng
+th in CPU controlled mode(Wr_BUF). 0: others.*/
+#define SPI_SLV_WRBUF_BITLEN_EN    (BIT(11))
+#define SPI_SLV_WRBUF_BITLEN_EN_M  (BIT(11))
+#define SPI_SLV_WRBUF_BITLEN_EN_V  0x1
+#define SPI_SLV_WRBUF_BITLEN_EN_S  11
+/* SPI_SLV_RDBUF_BITLEN_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i
+n CPU controlled mode(Rd_BUF). 0: others.*/
+#define SPI_SLV_RDBUF_BITLEN_EN    (BIT(10))
+#define SPI_SLV_RDBUF_BITLEN_EN_M  (BIT(10))
+#define SPI_SLV_RDBUF_BITLEN_EN_V  0x1
+#define SPI_SLV_RDBUF_BITLEN_EN_S  10
+/* SPI_SLV_WRDMA_BITLEN_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng
+th in DMA controlled mode(Wr_DMA). 0: others.*/
+#define SPI_SLV_WRDMA_BITLEN_EN    (BIT(9))
+#define SPI_SLV_WRDMA_BITLEN_EN_M  (BIT(9))
+#define SPI_SLV_WRDMA_BITLEN_EN_V  0x1
+#define SPI_SLV_WRDMA_BITLEN_EN_S  9
+/* SPI_SLV_RDDMA_BITLEN_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i
+n DMA controlled mode(Rd_DMA). 0: others.*/
+#define SPI_SLV_RDDMA_BITLEN_EN    (BIT(8))
+#define SPI_SLV_RDDMA_BITLEN_EN_M  (BIT(8))
+#define SPI_SLV_RDDMA_BITLEN_EN_V  0x1
+#define SPI_SLV_RDDMA_BITLEN_EN_S  8
+/* SPI_RSCK_DATA_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: It saves half a cycle when tsck is the same as rsck. 1: output data at rsck pose
+dge   0: output data at tsck posedge .*/
+#define SPI_RSCK_DATA_OUT    (BIT(3))
+#define SPI_RSCK_DATA_OUT_M  (BIT(3))
+#define SPI_RSCK_DATA_OUT_V  0x1
+#define SPI_RSCK_DATA_OUT_S  3
+/* SPI_CLK_MODE_13 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].
+ 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]..*/
+#define SPI_CLK_MODE_13    (BIT(2))
+#define SPI_CLK_MODE_13_M  (BIT(2))
+#define SPI_CLK_MODE_13_V  0x1
+#define SPI_CLK_MODE_13_S  2
+/* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
+d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
+ve 3: SPI clock is alwasy on. Can be configured in CONF state..*/
+#define SPI_CLK_MODE    0x00000003
+#define SPI_CLK_MODE_M  ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S))
+#define SPI_CLK_MODE_V  0x3
+#define SPI_CLK_MODE_S  0
+
+#define SPI_SLAVE1_REG(i)          (REG_SPI_BASE(i) + 0xE4)
+/* SPI_SLV_LAST_ADDR : R/W/SS ;bitpos:[31:26] ;default: 6'd0 ; */
+/*description: In the slave mode it is the value of address..*/
+#define SPI_SLV_LAST_ADDR    0x0000003F
+#define SPI_SLV_LAST_ADDR_M  ((SPI_SLV_LAST_ADDR_V)<<(SPI_SLV_LAST_ADDR_S))
+#define SPI_SLV_LAST_ADDR_V  0x3F
+#define SPI_SLV_LAST_ADDR_S  26
+/* SPI_SLV_LAST_COMMAND : R/W/SS ;bitpos:[25:18] ;default: 8'b0 ; */
+/*description: In the slave mode it is the value of command..*/
+#define SPI_SLV_LAST_COMMAND    0x000000FF
+#define SPI_SLV_LAST_COMMAND_M  ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S))
+#define SPI_SLV_LAST_COMMAND_V  0xFF
+#define SPI_SLV_LAST_COMMAND_S  18
+/* SPI_SLV_DATA_BITLEN : R/W/SS ;bitpos:[17:0] ;default: 18'd0 ; */
+/*description: The transferred data bit length in SPI slave FD and HD mode. .*/
+#define SPI_SLV_DATA_BITLEN    0x0003FFFF
+#define SPI_SLV_DATA_BITLEN_M  ((SPI_SLV_DATA_BITLEN_V)<<(SPI_SLV_DATA_BITLEN_S))
+#define SPI_SLV_DATA_BITLEN_V  0x3FFFF
+#define SPI_SLV_DATA_BITLEN_S  0
+
+#define SPI_CLK_GATE_REG(i)          (REG_SPI_BASE(i) + 0xE8)
+/* SPI_MST_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80
+M. 0: XTAL CLK..*/
+#define SPI_MST_CLK_SEL    (BIT(2))
+#define SPI_MST_CLK_SEL_M  (BIT(2))
+#define SPI_MST_CLK_SEL_V  0x1
+#define SPI_MST_CLK_SEL_S  2
+/* SPI_MST_CLK_ACTIVE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to power on the SPI module clock..*/
+#define SPI_MST_CLK_ACTIVE    (BIT(1))
+#define SPI_MST_CLK_ACTIVE_M  (BIT(1))
+#define SPI_MST_CLK_ACTIVE_V  0x1
+#define SPI_MST_CLK_ACTIVE_S  1
+/* SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable clk gate.*/
+#define SPI_CLK_EN    (BIT(0))
+#define SPI_CLK_EN_M  (BIT(0))
+#define SPI_CLK_EN_V  0x1
+#define SPI_CLK_EN_S  0
+
+#define SPI_DATE_REG(i)          (REG_SPI_BASE(i) + 0xF0)
+/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007220 ; */
+/*description: SPI register version..*/
+#define SPI_DATE    0x0FFFFFFF
+#define SPI_DATE_M  ((SPI_DATE_V)<<(SPI_DATE_S))
+#define SPI_DATE_V  0xFFFFFFF
+#define SPI_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SPI_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/spi_struct.h b/components/soc/esp32c3/include/soc/spi_struct.h
new file mode 100644
index 0000000000..24844d58ba
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/spi_struct.h
@@ -0,0 +1,382 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SPI_STRUCT_H_
+#define _SOC_SPI_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t conf_bitlen                   :    18;  /*Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.*/
+            uint32_t reserved18                    :    5;  /*reserved*/
+            uint32_t update                        :    1;  /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.*/
+            uint32_t usr                           :    1;  /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/
+            uint32_t reserved25                    :    7;  /*reserved*/
+        };
+        uint32_t val;
+    } cmd;
+    uint32_t addr;
+    union {
+        struct {
+            uint32_t reserved0                     :    3;  /*reserved*/
+            uint32_t dummy_out                     :    1;  /*In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.*/
+            uint32_t reserved4                     :    1;  /*reserved*/
+            uint32_t faddr_dual                    :    1;  /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t faddr_quad                    :    1;  /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t reserved7                     :    1;  /*reserved*/
+            uint32_t fcmd_dual                     :    1;  /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t fcmd_quad                     :    1;  /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t reserved10                    :    4;  /*reserved*/
+            uint32_t fread_dual                    :    1;  /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t fread_quad                    :    1;  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.*/
+            uint32_t reserved16                    :    1;  /*reserved*/
+            uint32_t reserved17                    :    1;  /*reserved*/
+            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.*/
+            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/
+            uint32_t hold_pol                      :    1;  /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
+            uint32_t wp_pol                        :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.*/
+            uint32_t reserved22                    :    3;  /*reserved*/
+            uint32_t rd_bit_order                  :    1;  /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
+            uint32_t wr_bit_order                  :    1;  /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
+            uint32_t reserved27                    :    5;  /*reserved*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t clkcnt_l                      :    6;  /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/
+            uint32_t clkcnt_h                      :    6;  /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/
+            uint32_t clkcnt_n                      :    6;  /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/
+            uint32_t clkdiv_pre                    :    4;  /*In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.*/
+            uint32_t reserved22                    :    9;  /*reserved*/
+            uint32_t clk_equ_sysclk                :    1;  /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } clock;
+    union {
+        struct {
+            uint32_t doutdin                       :    1;  /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t reserved1                     :    2;  /*reserved*/
+            uint32_t qpi_mode                      :    1;  /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/
+            uint32_t reserved4                     :    1;  /*reserved*/
+            uint32_t tsck_i_edge                   :    1;  /*In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
+            uint32_t cs_hold                       :    1;  /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t cs_setup                      :    1;  /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t rsck_i_edge                   :    1;  /*In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/
+            uint32_t ck_out_edge                   :    1;  /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/
+            uint32_t reserved10                    :    2;  /*reserved*/
+            uint32_t fwrite_dual                   :    1;  /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/
+            uint32_t fwrite_quad                   :    1;  /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/
+            uint32_t reserved14                    :    1;  /*reserved*/
+            uint32_t usr_conf_nxt                  :    1;  /*1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/
+            uint32_t reserved16                    :    1;  /*reserved*/
+            uint32_t sio                           :    1;  /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t reserved18                    :    6;  /*reserved*/
+            uint32_t usr_miso_highpart             :    1;  /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t usr_mosi_highpart             :    1;  /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.*/
+            uint32_t usr_dummy_idle                :    1;  /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/
+            uint32_t usr_mosi                      :    1;  /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_miso                      :    1;  /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_dummy                     :    1;  /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_addr                      :    1;  /*This bit enable the address phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_command                   :    1;  /*This bit enable the command phase of an operation. Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } user;
+    union {
+        struct {
+            uint32_t usr_dummy_cyclelen            :    8;  /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/
+            uint32_t reserved8                     :    8;  /*reserved*/
+            uint32_t mst_wfull_err_end_en          :    1;  /*1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.*/
+            uint32_t cs_setup_time                 :    5;  /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/
+            uint32_t cs_hold_time                  :    5;  /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/
+            uint32_t usr_addr_bitlen               :    5;  /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } user1;
+    union {
+        struct {
+            uint32_t usr_command_value             :    16;  /*The value of  command. Can be configured in CONF state.*/
+            uint32_t reserved16                    :    11;  /*reserved*/
+            uint32_t mst_rempty_err_end_en         :    1;  /*1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.*/
+            uint32_t usr_command_bitlen            :    4;  /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } user2;
+    union {
+        struct {
+            uint32_t ms_data_bitlen                :    18;  /*The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/
+            uint32_t reserved18                    :    14;  /*reserved*/
+        };
+        uint32_t val;
+    } ms_dlen;
+    union {
+        struct {
+            uint32_t cs0_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs1_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs2_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs3_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs4_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs5_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t ck_dis                        :    1;  /*1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.*/
+            uint32_t master_cs_pol                 :    6;  /*In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/
+            uint32_t reserved13                    :    10;  /*reserved*/
+            uint32_t slave_cs_pol                  :    1;  /*spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.*/
+            uint32_t reserved24                    :    5;  /*reserved*/
+            uint32_t ck_idle_edge                  :    1;  /*1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.*/
+            uint32_t cs_keep_active                :    1;  /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/
+            uint32_t quad_din_pin_swap             :    1;  /*1:  spi quad input swap enable  0:  spi quad input swap disable. Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } misc;
+    union {
+        struct {
+            uint32_t din0_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din1_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din2_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din3_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t reserved8                     :    8;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t timing_hclk_active            :    1;  /*1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.*/
+            uint32_t reserved17                    :    15;  /*reserved*/
+        };
+        uint32_t val;
+    } din_mode;
+    union {
+        struct {
+            uint32_t din0_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din1_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din2_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din3_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t reserved8                     :    24;  /*reserved*/
+        };
+        uint32_t val;
+    } din_num;
+    union {
+        struct {
+            uint32_t dout0_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout1_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout2_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout3_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t reserved4                     :    28;  /*reserved*/
+        };
+        uint32_t val;
+    } dout_mode;
+    union {
+        struct {
+            uint32_t reserved0                     :    18;  /*reserved*/
+            uint32_t dma_seg_trans_en              :    1;  /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/
+            uint32_t rx_seg_trans_clr_en           :    1;  /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/
+            uint32_t tx_seg_trans_clr_en           :    1;  /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/
+            uint32_t rx_eof_en                     :    1;  /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/
+            uint32_t reserved22                    :    5;  /*reserved*/
+            uint32_t dma_rx_ena                    :    1;  /*Set this bit to enable SPI DMA controlled receive data mode.*/
+            uint32_t dma_tx_ena                    :    1;  /*Set this bit to enable SPI DMA controlled send data mode.*/
+            uint32_t rx_afifo_rst                  :    1;  /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/
+            uint32_t buf_afifo_rst                 :    1;  /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/
+            uint32_t dma_afifo_rst                 :    1;  /*Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.*/
+        };
+        uint32_t val;
+    } dma_conf;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
+            uint32_t outfifo_empty_err             :    1;  /*The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
+            uint32_t ex_qpi                        :    1;  /*The enable bit for SPI slave Ex_QPI interrupt.*/
+            uint32_t en_qpi                        :    1;  /*The enable bit for SPI slave En_QPI interrupt.*/
+            uint32_t cmd7                          :    1;  /*The enable bit for SPI slave CMD7 interrupt.*/
+            uint32_t cmd8                          :    1;  /*The enable bit for SPI slave CMD8 interrupt.*/
+            uint32_t cmd9                          :    1;  /*The enable bit for SPI slave CMD9 interrupt.*/
+            uint32_t cmda                          :    1;  /*The enable bit for SPI slave CMDA interrupt.*/
+            uint32_t rd_dma_done                   :    1;  /*The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
+            uint32_t wr_dma_done                   :    1;  /*The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
+            uint32_t rd_buf_done                   :    1;  /*The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
+            uint32_t wr_buf_done                   :    1;  /*The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
+            uint32_t trans_done                    :    1;  /*The enable bit for SPI_TRANS_DONE_INT interrupt.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
+            uint32_t seg_magic_err                 :    1;  /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
+            uint32_t buf_addr_err                  :    1;  /*The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
+            uint32_t cmd_err                       :    1;  /*The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
+            uint32_t app2                          :    1;  /*The enable bit for SPI_APP2_INT interrupt.*/
+            uint32_t app1                          :    1;  /*The enable bit for SPI_APP1_INT interrupt.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_ena;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
+            uint32_t outfifo_empty_err             :    1;  /*The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
+            uint32_t ex_qpi                        :    1;  /*The clear bit for SPI slave Ex_QPI interrupt.*/
+            uint32_t en_qpi                        :    1;  /*The clear bit for SPI slave En_QPI interrupt.*/
+            uint32_t cmd7                          :    1;  /*The clear bit for SPI slave CMD7 interrupt.*/
+            uint32_t cmd8                          :    1;  /*The clear bit for SPI slave CMD8 interrupt.*/
+            uint32_t cmd9                          :    1;  /*The clear bit for SPI slave CMD9 interrupt.*/
+            uint32_t cmda                          :    1;  /*The clear bit for SPI slave CMDA interrupt.*/
+            uint32_t rd_dma_done                   :    1;  /*The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
+            uint32_t wr_dma_done                   :    1;  /*The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
+            uint32_t rd_buf_done                   :    1;  /*The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
+            uint32_t wr_buf_done                   :    1;  /*The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
+            uint32_t trans_done                    :    1;  /*The clear bit for SPI_TRANS_DONE_INT interrupt.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
+            uint32_t seg_magic_err                 :    1;  /*The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
+            uint32_t buf_addr_err                  :    1;  /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
+            uint32_t cmd_err                       :    1;  /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
+            uint32_t app2                          :    1;  /*The clear bit for SPI_APP2_INT interrupt.*/
+            uint32_t app1                          :    1;  /*The clear bit for SPI_APP1_INT interrupt.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_clr;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.  */
+            uint32_t outfifo_empty_err             :    1;  /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.  */
+            uint32_t ex_qpi                        :    1;  /*The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/
+            uint32_t en_qpi                        :    1;  /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/
+            uint32_t cmd7                          :    1;  /*The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.*/
+            uint32_t cmd8                          :    1;  /*The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.*/
+            uint32_t cmd9                          :    1;  /*The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.*/
+            uint32_t cmda                          :    1;  /*The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.*/
+            uint32_t rd_dma_done                   :    1;  /*The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.*/
+            uint32_t wr_dma_done                   :    1;  /*The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/
+            uint32_t rd_buf_done                   :    1;  /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.*/
+            uint32_t wr_buf_done                   :    1;  /*The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.*/
+            uint32_t trans_done                    :    1;  /*The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred. */
+            uint32_t seg_magic_err                 :    1;  /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/
+            uint32_t buf_addr_err                  :    1;  /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/
+            uint32_t cmd_err                       :    1;  /*The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.*/
+            uint32_t app2                          :    1;  /*The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.*/
+            uint32_t app1                          :    1;  /*The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_raw;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
+            uint32_t outfifo_empty_err             :    1;  /*The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
+            uint32_t ex_qpi                        :    1;  /*The status bit for SPI slave Ex_QPI interrupt.*/
+            uint32_t en_qpi                        :    1;  /*The status bit for SPI slave En_QPI interrupt.*/
+            uint32_t cmd7                          :    1;  /*The status bit for SPI slave CMD7 interrupt.*/
+            uint32_t cmd8                          :    1;  /*The status bit for SPI slave CMD8 interrupt.*/
+            uint32_t cmd9                          :    1;  /*The status bit for SPI slave CMD9 interrupt.*/
+            uint32_t cmda                          :    1;  /*The status bit for SPI slave CMDA interrupt.*/
+            uint32_t rd_dma_done                   :    1;  /*The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
+            uint32_t wr_dma_done                   :    1;  /*The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
+            uint32_t rd_buf_done                   :    1;  /*The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
+            uint32_t wr_buf_done                   :    1;  /*The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
+            uint32_t trans_done                    :    1;  /*The status bit for SPI_TRANS_DONE_INT interrupt.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
+            uint32_t seg_magic_err                 :    1;  /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
+            uint32_t buf_addr_err                  :    1;  /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
+            uint32_t cmd_err                       :    1;  /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
+            uint32_t app2                          :    1;  /*The status bit for SPI_APP2_INT interrupt.*/
+            uint32_t app1                          :    1;  /*The status bit for SPI_APP1_INT interrupt.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_st;
+    uint32_t reserved_44;
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    uint32_t reserved_54;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t data_buf[16];
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    union {
+        struct {
+            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/
+            uint32_t clk_mode_13                   :    1;  /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/
+            uint32_t rsck_data_out                 :    1;  /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge */
+            uint32_t reserved4                     :    4;  /*reserved*/
+            uint32_t rddma_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/
+            uint32_t wrdma_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/
+            uint32_t rdbuf_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/
+            uint32_t wrbuf_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/
+            uint32_t reserved12                    :    10;  /*reserved*/
+            uint32_t dma_seg_magic_value           :    4;  /*The magic value of BM table in master DMA seg-trans.*/
+            uint32_t slave_mode                    :    1;  /*Set SPI work mode. 1: slave mode 0: master mode.*/
+            uint32_t soft_reset                    :    1;  /*Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.*/
+            uint32_t usr_conf                      :    1;  /*1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.*/
+            uint32_t reserved29                    :    3;  /*reserved*/
+        };
+        uint32_t val;
+    } slave;
+    union {
+        struct {
+            uint32_t data_bitlen                   :    18;  /*The transferred data bit length in SPI slave FD and HD mode. */
+            uint32_t last_command                  :    8;  /*In the slave mode it is the value of command.*/
+            uint32_t last_addr                     :    6;  /*In the slave mode it is the value of address.*/
+        };
+        uint32_t val;
+    } slave1;
+    union {
+        struct {
+            uint32_t clk_en                        :    1;  /*Set this bit to enable clk gate*/
+            uint32_t mst_clk_active                :    1;  /*Set this bit to power on the SPI module clock.*/
+            uint32_t mst_clk_sel                   :    1;  /*This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } clk_gate;
+    uint32_t reserved_ec;
+    union {
+        struct {
+            uint32_t date                          :    28;  /*SPI register version.*/
+            uint32_t reserved28                    :    4;  /*reserved*/
+        };
+        uint32_t val;
+    } date;
+} spi_dev_t;
+
+extern spi_dev_t GPSPI2;
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SPI_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/syscon_reg.h b/components/soc/esp32c3/include/soc/syscon_reg.h
new file mode 100644
index 0000000000..e7b437d24a
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/syscon_reg.h
@@ -0,0 +1,625 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SYSCON_REG_H_
+#define _SOC_SYSCON_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define SYSCON_SYSCLK_CONF_REG          (DR_REG_SYSCON_BASE + 0x000)
+/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_RST_TICK_CNT  (BIT(12))
+#define SYSCON_RST_TICK_CNT_M  (BIT(12))
+#define SYSCON_RST_TICK_CNT_V  0x1
+#define SYSCON_RST_TICK_CNT_S  12
+/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_CLK_EN  (BIT(11))
+#define SYSCON_CLK_EN_M  (BIT(11))
+#define SYSCON_CLK_EN_V  0x1
+#define SYSCON_CLK_EN_S  11
+/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_CLK_320M_EN  (BIT(10))
+#define SYSCON_CLK_320M_EN_M  (BIT(10))
+#define SYSCON_CLK_320M_EN_V  0x1
+#define SYSCON_CLK_320M_EN_S  10
+/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
+/*description: */
+#define SYSCON_PRE_DIV_CNT  0x000003FF
+#define SYSCON_PRE_DIV_CNT_M  ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
+#define SYSCON_PRE_DIV_CNT_V  0x3FF
+#define SYSCON_PRE_DIV_CNT_S  0
+
+#define SYSCON_TICK_CONF_REG          (DR_REG_SYSCON_BASE + 0x004)
+/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: */
+#define SYSCON_TICK_ENABLE  (BIT(16))
+#define SYSCON_TICK_ENABLE_M  (BIT(16))
+#define SYSCON_TICK_ENABLE_V  0x1
+#define SYSCON_TICK_ENABLE_S  16
+/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
+/*description: */
+#define SYSCON_CK8M_TICK_NUM  0x000000FF
+#define SYSCON_CK8M_TICK_NUM_M  ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S))
+#define SYSCON_CK8M_TICK_NUM_V  0xFF
+#define SYSCON_CK8M_TICK_NUM_S  8
+/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
+/*description: */
+#define SYSCON_XTAL_TICK_NUM  0x000000FF
+#define SYSCON_XTAL_TICK_NUM_M  ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S))
+#define SYSCON_XTAL_TICK_NUM_V  0xFF
+#define SYSCON_XTAL_TICK_NUM_S  0
+
+#define SYSCON_CLK_OUT_EN_REG          (DR_REG_SYSCON_BASE + 0x008)
+/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK_XTAL_OEN  (BIT(10))
+#define SYSCON_CLK_XTAL_OEN_M  (BIT(10))
+#define SYSCON_CLK_XTAL_OEN_V  0x1
+#define SYSCON_CLK_XTAL_OEN_S  10
+/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK40X_BB_OEN  (BIT(9))
+#define SYSCON_CLK40X_BB_OEN_M  (BIT(9))
+#define SYSCON_CLK40X_BB_OEN_V  0x1
+#define SYSCON_CLK40X_BB_OEN_S  9
+/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK_DAC_CPU_OEN  (BIT(8))
+#define SYSCON_CLK_DAC_CPU_OEN_M  (BIT(8))
+#define SYSCON_CLK_DAC_CPU_OEN_V  0x1
+#define SYSCON_CLK_DAC_CPU_OEN_S  8
+/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK_ADC_INF_OEN  (BIT(7))
+#define SYSCON_CLK_ADC_INF_OEN_M  (BIT(7))
+#define SYSCON_CLK_ADC_INF_OEN_V  0x1
+#define SYSCON_CLK_ADC_INF_OEN_S  7
+/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK_320M_OEN  (BIT(6))
+#define SYSCON_CLK_320M_OEN_M  (BIT(6))
+#define SYSCON_CLK_320M_OEN_V  0x1
+#define SYSCON_CLK_320M_OEN_S  6
+/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK160_OEN  (BIT(5))
+#define SYSCON_CLK160_OEN_M  (BIT(5))
+#define SYSCON_CLK160_OEN_V  0x1
+#define SYSCON_CLK160_OEN_S  5
+/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK80_OEN  (BIT(4))
+#define SYSCON_CLK80_OEN_M  (BIT(4))
+#define SYSCON_CLK80_OEN_V  0x1
+#define SYSCON_CLK80_OEN_S  4
+/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK_BB_OEN  (BIT(3))
+#define SYSCON_CLK_BB_OEN_M  (BIT(3))
+#define SYSCON_CLK_BB_OEN_V  0x1
+#define SYSCON_CLK_BB_OEN_S  3
+/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK44_OEN  (BIT(2))
+#define SYSCON_CLK44_OEN_M  (BIT(2))
+#define SYSCON_CLK44_OEN_V  0x1
+#define SYSCON_CLK44_OEN_S  2
+/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK22_OEN  (BIT(1))
+#define SYSCON_CLK22_OEN_M  (BIT(1))
+#define SYSCON_CLK22_OEN_V  0x1
+#define SYSCON_CLK22_OEN_S  1
+/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK20_OEN  (BIT(0))
+#define SYSCON_CLK20_OEN_M  (BIT(0))
+#define SYSCON_CLK20_OEN_V  0x1
+#define SYSCON_CLK20_OEN_S  0
+
+#define SYSCON_WIFI_BB_CFG_REG          (DR_REG_SYSCON_BASE + 0x00C)
+/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSCON_WIFI_BB_CFG  0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_M  ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S))
+#define SYSCON_WIFI_BB_CFG_V  0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_S  0
+
+#define SYSCON_WIFI_BB_CFG_2_REG          (DR_REG_SYSCON_BASE + 0x010)
+/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSCON_WIFI_BB_CFG_2  0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_2_M  ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S))
+#define SYSCON_WIFI_BB_CFG_2_V  0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_2_S  0
+
+#define SYSCON_WIFI_CLK_EN_REG          (DR_REG_SYSCON_BASE + 0x014)
+/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
+/*description: */
+#define SYSCON_WIFI_CLK_EN  0xFFFFFFFF
+#define SYSCON_WIFI_CLK_EN_M  ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S))
+#define SYSCON_WIFI_CLK_EN_V  0xFFFFFFFF
+#define SYSCON_WIFI_CLK_EN_S  0
+
+#define SYSCON_WIFI_RST_EN_REG          (DR_REG_SYSCON_BASE + 0x018)
+/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSCON_WIFI_RST  0xFFFFFFFF
+#define SYSCON_WIFI_RST_M  ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S))
+#define SYSCON_WIFI_RST_V  0xFFFFFFFF
+#define SYSCON_WIFI_RST_S  0
+
+#define SYSTEM_WIFI_CLK_EN_REG          SYSCON_WIFI_CLK_EN_REG
+/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
+/*description: */
+#define SYSTEM_WIFI_CLK_EN  0xFFFFFFFF
+#define SYSTEM_WIFI_CLK_EN_M  ((SYSTEM_WIFI_CLK_EN_V)<<(SYSTEM_WIFI_CLK_EN_S))
+#define SYSTEM_WIFI_CLK_EN_V  0xFFFFFFFF
+#define SYSTEM_WIFI_CLK_EN_S  0
+
+/* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15, 19, 20, 21
+   Bit15 not included here because of the bit now can't be cleared */
+#define SYSTEM_WIFI_CLK_WIFI_EN  0x003807cf
+#define SYSTEM_WIFI_CLK_WIFI_EN_M  ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S))
+#define SYSTEM_WIFI_CLK_WIFI_EN_V  0x7cf
+#define SYSTEM_WIFI_CLK_WIFI_EN_S  0
+/* Mask for all Bluetooth clock bits - 11, 16, 17 */
+#define SYSTEM_WIFI_CLK_BT_EN  0x61
+#define SYSTEM_WIFI_CLK_BT_EN_M  ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S))
+#define SYSTEM_WIFI_CLK_BT_EN_V  0x61
+#define SYSTEM_WIFI_CLK_BT_EN_S  11
+/* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */
+#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9
+
+/* Digital team to check */
+//bluetooth baseband bit11
+#define SYSTEM_BT_BASEBAND_EN  BIT(11)
+//bluetooth LC bit16 and bit17
+#define SYSTEM_BT_LC_EN  (BIT(16)|BIT(17))
+
+/* Remaining single bit clock masks */
+#define SYSTEM_WIFI_CLK_SDIOSLAVE_EN  BIT(4)
+#define SYSTEM_WIFI_CLK_UNUSED_BIT5  BIT(5)
+#define SYSTEM_WIFI_CLK_UNUSED_BIT12  BIT(12)
+#define SYSTEM_WIFI_CLK_EMAC_EN  BIT(14)
+#define SYSTEM_WIFI_CLK_RNG_EN  BIT(15)
+
+#define SYSTEM_CORE_RST_EN_REG        SYSTEM_WIFI_RST_EN_REG
+#define SYSTEM_WIFI_RST_EN_REG        SYSCON_WIFI_RST_EN_REG
+/* SYSTEM_WIFI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSTEM_RW_BTLP_RST (BIT(10))
+#define SYSTEM_RW_BTMAC_RST (BIT(9))
+#define SYSTEM_MACPWR_RST (BIT(8))
+#define SYSTEM_SDIO_RST (BIT(5))
+#define SYSTEM_BTMAC_RST (BIT(4))
+#define SYSTEM_BT_RST (BIT(3))
+#define SYSTEM_MAC_RST (BIT(2))
+#define SYSTEM_FE_RST (BIT(1))
+#define SYSTEM_BB_RST (BIT(0))
+
+#define SYSCON_HOST_INF_SEL_REG          (DR_REG_SYSCON_BASE + 0x01C)
+/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define SYSCON_PERI_IO_SWAP  0x000000FF
+#define SYSCON_PERI_IO_SWAP_M  ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S))
+#define SYSCON_PERI_IO_SWAP_V  0xFF
+#define SYSCON_PERI_IO_SWAP_S  0
+
+#define SYSCON_EXT_MEM_PMS_LOCK_REG          (DR_REG_SYSCON_BASE + 0x020)
+/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_EXT_MEM_PMS_LOCK  (BIT(0))
+#define SYSCON_EXT_MEM_PMS_LOCK_M  (BIT(0))
+#define SYSCON_EXT_MEM_PMS_LOCK_V  0x1
+#define SYSCON_EXT_MEM_PMS_LOCK_S  0
+
+#define SYSCON_FLASH_ACE0_ATTR_REG          (DR_REG_SYSCON_BASE + 0x028)
+/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: */
+#define SYSCON_FLASH_ACE0_ATTR  0x00000003
+#define SYSCON_FLASH_ACE0_ATTR_M  ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S))
+#define SYSCON_FLASH_ACE0_ATTR_V  0x3
+#define SYSCON_FLASH_ACE0_ATTR_S  0
+
+#define SYSCON_FLASH_ACE1_ATTR_REG          (DR_REG_SYSCON_BASE + 0x02C)
+/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: */
+#define SYSCON_FLASH_ACE1_ATTR  0x00000003
+#define SYSCON_FLASH_ACE1_ATTR_M  ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S))
+#define SYSCON_FLASH_ACE1_ATTR_V  0x3
+#define SYSCON_FLASH_ACE1_ATTR_S  0
+
+#define SYSCON_FLASH_ACE2_ATTR_REG          (DR_REG_SYSCON_BASE + 0x030)
+/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: */
+#define SYSCON_FLASH_ACE2_ATTR  0x00000003
+#define SYSCON_FLASH_ACE2_ATTR_M  ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S))
+#define SYSCON_FLASH_ACE2_ATTR_V  0x3
+#define SYSCON_FLASH_ACE2_ATTR_S  0
+
+#define SYSCON_FLASH_ACE3_ATTR_REG          (DR_REG_SYSCON_BASE + 0x034)
+/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: */
+#define SYSCON_FLASH_ACE3_ATTR  0x00000003
+#define SYSCON_FLASH_ACE3_ATTR_M  ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S))
+#define SYSCON_FLASH_ACE3_ATTR_V  0x3
+#define SYSCON_FLASH_ACE3_ATTR_S  0
+
+#define SYSCON_FLASH_ACE0_ADDR_REG          (DR_REG_SYSCON_BASE + 0x038)
+/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSCON_FLASH_ACE0_ADDR_S  0xFFFFFFFF
+#define SYSCON_FLASH_ACE0_ADDR_S_M  ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S))
+#define SYSCON_FLASH_ACE0_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE0_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE1_ADDR_REG          (DR_REG_SYSCON_BASE + 0x03C)
+/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */
+/*description: */
+#define SYSCON_FLASH_ACE1_ADDR_S  0xFFFFFFFF
+#define SYSCON_FLASH_ACE1_ADDR_S_M  ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S))
+#define SYSCON_FLASH_ACE1_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE1_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE2_ADDR_REG          (DR_REG_SYSCON_BASE + 0x040)
+/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */
+/*description: */
+#define SYSCON_FLASH_ACE2_ADDR_S  0xFFFFFFFF
+#define SYSCON_FLASH_ACE2_ADDR_S_M  ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S))
+#define SYSCON_FLASH_ACE2_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE2_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE3_ADDR_REG          (DR_REG_SYSCON_BASE + 0x044)
+/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hC00000 ; */
+/*description: */
+#define SYSCON_FLASH_ACE3_ADDR_S  0xFFFFFFFF
+#define SYSCON_FLASH_ACE3_ADDR_S_M  ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S))
+#define SYSCON_FLASH_ACE3_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE3_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE0_SIZE_REG          (DR_REG_SYSCON_BASE + 0x048)
+/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: */
+#define SYSCON_FLASH_ACE0_SIZE  0x00001FFF
+#define SYSCON_FLASH_ACE0_SIZE_M  ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S))
+#define SYSCON_FLASH_ACE0_SIZE_V  0x1FFF
+#define SYSCON_FLASH_ACE0_SIZE_S  0
+
+#define SYSCON_FLASH_ACE1_SIZE_REG          (DR_REG_SYSCON_BASE + 0x04C)
+/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: */
+#define SYSCON_FLASH_ACE1_SIZE  0x00001FFF
+#define SYSCON_FLASH_ACE1_SIZE_M  ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S))
+#define SYSCON_FLASH_ACE1_SIZE_V  0x1FFF
+#define SYSCON_FLASH_ACE1_SIZE_S  0
+
+#define SYSCON_FLASH_ACE2_SIZE_REG          (DR_REG_SYSCON_BASE + 0x050)
+/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: */
+#define SYSCON_FLASH_ACE2_SIZE  0x00001FFF
+#define SYSCON_FLASH_ACE2_SIZE_M  ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S))
+#define SYSCON_FLASH_ACE2_SIZE_V  0x1FFF
+#define SYSCON_FLASH_ACE2_SIZE_S  0
+
+#define SYSCON_FLASH_ACE3_SIZE_REG          (DR_REG_SYSCON_BASE + 0x054)
+/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: */
+#define SYSCON_FLASH_ACE3_SIZE  0x00001FFF
+#define SYSCON_FLASH_ACE3_SIZE_M  ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S))
+#define SYSCON_FLASH_ACE3_SIZE_V  0x1FFF
+#define SYSCON_FLASH_ACE3_SIZE_S  0
+
+#define SYSCON_SPI_MEM_PMS_CTRL_REG          (DR_REG_SYSCON_BASE + 0x088)
+/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
+/*description: */
+#define SYSCON_SPI_MEM_REJECT_CDE  0x0000001F
+#define SYSCON_SPI_MEM_REJECT_CDE_M  ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S))
+#define SYSCON_SPI_MEM_REJECT_CDE_V  0x1F
+#define SYSCON_SPI_MEM_REJECT_CDE_S  2
+/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_SPI_MEM_REJECT_CLR  (BIT(1))
+#define SYSCON_SPI_MEM_REJECT_CLR_M  (BIT(1))
+#define SYSCON_SPI_MEM_REJECT_CLR_V  0x1
+#define SYSCON_SPI_MEM_REJECT_CLR_S  1
+/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_SPI_MEM_REJECT_INT  (BIT(0))
+#define SYSCON_SPI_MEM_REJECT_INT_M  (BIT(0))
+#define SYSCON_SPI_MEM_REJECT_INT_V  0x1
+#define SYSCON_SPI_MEM_REJECT_INT_S  0
+
+#define SYSCON_SPI_MEM_REJECT_ADDR_REG          (DR_REG_SYSCON_BASE + 0x08C)
+/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSCON_SPI_MEM_REJECT_ADDR  0xFFFFFFFF
+#define SYSCON_SPI_MEM_REJECT_ADDR_M  ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S))
+#define SYSCON_SPI_MEM_REJECT_ADDR_V  0xFFFFFFFF
+#define SYSCON_SPI_MEM_REJECT_ADDR_S  0
+
+#define SYSCON_SDIO_CTRL_REG          (DR_REG_SYSCON_BASE + 0x090)
+/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define SYSCON_SDIO_WIN_ACCESS_EN  (BIT(0))
+#define SYSCON_SDIO_WIN_ACCESS_EN_M  (BIT(0))
+#define SYSCON_SDIO_WIN_ACCESS_EN_V  0x1
+#define SYSCON_SDIO_WIN_ACCESS_EN_S  0
+
+#define SYSCON_REDCY_SIG0_REG          (DR_REG_SYSCON_BASE + 0x094)
+/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define SYSCON_REDCY_ANDOR  (BIT(31))
+#define SYSCON_REDCY_ANDOR_M  (BIT(31))
+#define SYSCON_REDCY_ANDOR_V  0x1
+#define SYSCON_REDCY_ANDOR_S  31
+/* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: */
+#define SYSCON_REDCY_SIG0  0x7FFFFFFF
+#define SYSCON_REDCY_SIG0_M  ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S))
+#define SYSCON_REDCY_SIG0_V  0x7FFFFFFF
+#define SYSCON_REDCY_SIG0_S  0
+
+#define SYSCON_REDCY_SIG1_REG          (DR_REG_SYSCON_BASE + 0x098)
+/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define SYSCON_REDCY_NANDOR  (BIT(31))
+#define SYSCON_REDCY_NANDOR_M  (BIT(31))
+#define SYSCON_REDCY_NANDOR_V  0x1
+#define SYSCON_REDCY_NANDOR_S  31
+/* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: */
+#define SYSCON_REDCY_SIG1  0x7FFFFFFF
+#define SYSCON_REDCY_SIG1_M  ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S))
+#define SYSCON_REDCY_SIG1_V  0x7FFFFFFF
+#define SYSCON_REDCY_SIG1_S  0
+
+#define SYSCON_FRONT_END_MEM_PD_REG          (DR_REG_SYSCON_BASE + 0x09C)
+/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_DC_MEM_FORCE_PD  (BIT(5))
+#define SYSCON_DC_MEM_FORCE_PD_M  (BIT(5))
+#define SYSCON_DC_MEM_FORCE_PD_V  0x1
+#define SYSCON_DC_MEM_FORCE_PD_S  5
+/* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_DC_MEM_FORCE_PU  (BIT(4))
+#define SYSCON_DC_MEM_FORCE_PU_M  (BIT(4))
+#define SYSCON_DC_MEM_FORCE_PU_V  0x1
+#define SYSCON_DC_MEM_FORCE_PU_S  4
+/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_PBUS_MEM_FORCE_PD  (BIT(3))
+#define SYSCON_PBUS_MEM_FORCE_PD_M  (BIT(3))
+#define SYSCON_PBUS_MEM_FORCE_PD_V  0x1
+#define SYSCON_PBUS_MEM_FORCE_PD_S  3
+/* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_PBUS_MEM_FORCE_PU  (BIT(2))
+#define SYSCON_PBUS_MEM_FORCE_PU_M  (BIT(2))
+#define SYSCON_PBUS_MEM_FORCE_PU_V  0x1
+#define SYSCON_PBUS_MEM_FORCE_PU_S  2
+/* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_AGC_MEM_FORCE_PD  (BIT(1))
+#define SYSCON_AGC_MEM_FORCE_PD_M  (BIT(1))
+#define SYSCON_AGC_MEM_FORCE_PD_V  0x1
+#define SYSCON_AGC_MEM_FORCE_PD_S  1
+/* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_AGC_MEM_FORCE_PU  (BIT(0))
+#define SYSCON_AGC_MEM_FORCE_PU_M  (BIT(0))
+#define SYSCON_AGC_MEM_FORCE_PU_V  0x1
+#define SYSCON_AGC_MEM_FORCE_PU_S  0
+
+#define SYSCON_RETENTION_CTRL_REG          (DR_REG_SYSCON_BASE + 0x0A0)
+/* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_NOBYPASS_CPU_ISO_RST  (BIT(27))
+#define SYSCON_NOBYPASS_CPU_ISO_RST_M  (BIT(27))
+#define SYSCON_NOBYPASS_CPU_ISO_RST_V  0x1
+#define SYSCON_NOBYPASS_CPU_ISO_RST_S  27
+/* SYSCON_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
+/*description: */
+#define SYSCON_RETENTION_LINK_ADDR  0x07FFFFFF
+#define SYSCON_RETENTION_LINK_ADDR_M  ((SYSCON_RETENTION_LINK_ADDR_V)<<(SYSCON_RETENTION_LINK_ADDR_S))
+#define SYSCON_RETENTION_LINK_ADDR_V  0x7FFFFFF
+#define SYSCON_RETENTION_LINK_ADDR_S  0
+
+#define SYSCON_CLKGATE_FORCE_ON_REG          (DR_REG_SYSCON_BASE + 0x0A4)
+/* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
+/*description: */
+#define SYSCON_SRAM_CLKGATE_FORCE_ON  0x0000000F
+#define SYSCON_SRAM_CLKGATE_FORCE_ON_M  ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S))
+#define SYSCON_SRAM_CLKGATE_FORCE_ON_V  0xF
+#define SYSCON_SRAM_CLKGATE_FORCE_ON_S  2
+/* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SYSCON_ROM_CLKGATE_FORCE_ON  0x00000003
+#define SYSCON_ROM_CLKGATE_FORCE_ON_M  ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S))
+#define SYSCON_ROM_CLKGATE_FORCE_ON_V  0x3
+#define SYSCON_ROM_CLKGATE_FORCE_ON_S  0
+
+#define SYSCON_MEM_POWER_DOWN_REG          (DR_REG_SYSCON_BASE + 0x0A8)
+/* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[5:2] ;default: 4'b0 ; */
+/*description: */
+#define SYSCON_SRAM_POWER_DOWN  0x0000000F
+#define SYSCON_SRAM_POWER_DOWN_M  ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S))
+#define SYSCON_SRAM_POWER_DOWN_V  0xF
+#define SYSCON_SRAM_POWER_DOWN_S  2
+/* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define SYSCON_ROM_POWER_DOWN  0x00000003
+#define SYSCON_ROM_POWER_DOWN_M  ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S))
+#define SYSCON_ROM_POWER_DOWN_V  0x3
+#define SYSCON_ROM_POWER_DOWN_S  0
+
+#define SYSCON_MEM_POWER_UP_REG          (DR_REG_SYSCON_BASE + 0x0AC)
+/* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
+/*description: */
+#define SYSCON_SRAM_POWER_UP  0x0000000F
+#define SYSCON_SRAM_POWER_UP_M  ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S))
+#define SYSCON_SRAM_POWER_UP_V  0xF
+#define SYSCON_SRAM_POWER_UP_S  2
+/* SYSCON_ROM_POWER_UP : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SYSCON_ROM_POWER_UP  0x00000003
+#define SYSCON_ROM_POWER_UP_M  ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S))
+#define SYSCON_ROM_POWER_UP_V  0x3
+#define SYSCON_ROM_POWER_UP_S  0
+
+#define SYSCON_RND_DATA_REG          (DR_REG_SYSCON_BASE + 0x0B0)
+/* SYSCON_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SYSCON_RND_DATA  0xFFFFFFFF
+#define SYSCON_RND_DATA_M  ((SYSCON_RND_DATA_V)<<(SYSCON_RND_DATA_S))
+#define SYSCON_RND_DATA_V  0xFFFFFFFF
+#define SYSCON_RND_DATA_S  0
+
+#define SYSCON_PERI_BACKUP_CONFIG_REG          (DR_REG_SYSCON_BASE + 0x0B4)
+/* SYSCON_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_ENA  (BIT(31))
+#define SYSCON_PERI_BACKUP_ENA_M  (BIT(31))
+#define SYSCON_PERI_BACKUP_ENA_V  0x1
+#define SYSCON_PERI_BACKUP_ENA_S  31
+/* SYSCON_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_TO_MEM  (BIT(30))
+#define SYSCON_PERI_BACKUP_TO_MEM_M  (BIT(30))
+#define SYSCON_PERI_BACKUP_TO_MEM_V  0x1
+#define SYSCON_PERI_BACKUP_TO_MEM_S  30
+/* SYSCON_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_START  (BIT(29))
+#define SYSCON_PERI_BACKUP_START_M  (BIT(29))
+#define SYSCON_PERI_BACKUP_START_V  0x1
+#define SYSCON_PERI_BACKUP_START_S  29
+/* SYSCON_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_SIZE  0x000003FF
+#define SYSCON_PERI_BACKUP_SIZE_M  ((SYSCON_PERI_BACKUP_SIZE_V)<<(SYSCON_PERI_BACKUP_SIZE_S))
+#define SYSCON_PERI_BACKUP_SIZE_V  0x3FF
+#define SYSCON_PERI_BACKUP_SIZE_S  19
+/* SYSCON_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_TOUT_THRES  0x000003FF
+#define SYSCON_PERI_BACKUP_TOUT_THRES_M  ((SYSCON_PERI_BACKUP_TOUT_THRES_V)<<(SYSCON_PERI_BACKUP_TOUT_THRES_S))
+#define SYSCON_PERI_BACKUP_TOUT_THRES_V  0x3FF
+#define SYSCON_PERI_BACKUP_TOUT_THRES_S  9
+/* SYSCON_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_BURST_LIMIT  0x0000001F
+#define SYSCON_PERI_BACKUP_BURST_LIMIT_M  ((SYSCON_PERI_BACKUP_BURST_LIMIT_V)<<(SYSCON_PERI_BACKUP_BURST_LIMIT_S))
+#define SYSCON_PERI_BACKUP_BURST_LIMIT_V  0x1F
+#define SYSCON_PERI_BACKUP_BURST_LIMIT_S  4
+/* SYSCON_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_FLOW_ERR  0x00000003
+#define SYSCON_PERI_BACKUP_FLOW_ERR_M  ((SYSCON_PERI_BACKUP_FLOW_ERR_V)<<(SYSCON_PERI_BACKUP_FLOW_ERR_S))
+#define SYSCON_PERI_BACKUP_FLOW_ERR_V  0x3
+#define SYSCON_PERI_BACKUP_FLOW_ERR_S  1
+
+#define SYSCON_PERI_BACKUP_APB_ADDR_REG          (DR_REG_SYSCON_BASE + 0x0B8)
+/* SYSCON_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: */
+#define SYSCON_BACKUP_APB_START_ADDR  0xFFFFFFFF
+#define SYSCON_BACKUP_APB_START_ADDR_M  ((SYSCON_BACKUP_APB_START_ADDR_V)<<(SYSCON_BACKUP_APB_START_ADDR_S))
+#define SYSCON_BACKUP_APB_START_ADDR_V  0xFFFFFFFF
+#define SYSCON_BACKUP_APB_START_ADDR_S  0
+
+#define SYSCON_PERI_BACKUP_MEM_ADDR_REG          (DR_REG_SYSCON_BASE + 0x0BC)
+/* SYSCON_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: */
+#define SYSCON_BACKUP_MEM_START_ADDR  0xFFFFFFFF
+#define SYSCON_BACKUP_MEM_START_ADDR_M  ((SYSCON_BACKUP_MEM_START_ADDR_V)<<(SYSCON_BACKUP_MEM_START_ADDR_S))
+#define SYSCON_BACKUP_MEM_START_ADDR_V  0xFFFFFFFF
+#define SYSCON_BACKUP_MEM_START_ADDR_S  0
+
+#define SYSCON_PERI_BACKUP_INT_RAW_REG          (DR_REG_SYSCON_BASE + 0x0C0)
+/* SYSCON_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW_M  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW_V  0x1
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW_S  1
+/* SYSCON_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW_M  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW_V  0x1
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW_S  0
+
+#define SYSCON_PERI_BACKUP_INT_ST_REG          (DR_REG_SYSCON_BASE + 0x0C4)
+/* SYSCON_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_ERR_INT_ST  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_ST_M  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_ST_V  0x1
+#define SYSCON_PERI_BACKUP_ERR_INT_ST_S  1
+/* SYSCON_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_DONE_INT_ST  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_ST_M  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_ST_V  0x1
+#define SYSCON_PERI_BACKUP_DONE_INT_ST_S  0
+
+#define SYSCON_PERI_BACKUP_INT_ENA_REG          (DR_REG_SYSCON_BASE + 0x0C8)
+/* SYSCON_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA_M  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA_V  0x1
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA_S  1
+/* SYSCON_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA_M  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA_V  0x1
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA_S  0
+
+#define SYSCON_PERI_BACKUP_INT_CLR_REG          (DR_REG_SYSCON_BASE + 0x0D0)
+/* SYSCON_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR_M  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR_V  0x1
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR_S  1
+/* SYSCON_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR_M  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR_V  0x1
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR_S  0
+
+#define SYSCON_DATE_REG          (DR_REG_SYSCON_BASE + 0x3FC)
+/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007210 ; */
+/*description: Version control*/
+#define SYSCON_DATE  0xFFFFFFFF
+#define SYSCON_DATE_M  ((SYSCON_DATE_V)<<(SYSCON_DATE_S))
+#define SYSCON_DATE_V  0xFFFFFFFF
+#define SYSCON_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SYSCON_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/syscon_struct.h b/components/soc/esp32c3/include/soc/syscon_struct.h
new file mode 100644
index 0000000000..2a9485aa87
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/syscon_struct.h
@@ -0,0 +1,482 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SYSCON_STRUCT_H_
+#define _SOC_SYSCON_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t apb_ctrl_pre_div_cnt: 10;
+            uint32_t apb_ctrl_clk_320m_en:  1;
+            uint32_t clk_en:                1;
+            uint32_t apb_ctrl_rst_tick_cnt: 1;
+            uint32_t reserved13:           19;
+        };
+        uint32_t val;
+    } apb_ctrl_sysclk_conf;
+    union {
+        struct {
+            uint32_t apb_ctrl_xtal_tick_num: 8;
+            uint32_t apb_ctrl_ck8m_tick_num: 8;
+            uint32_t apb_ctrl_tick_enable:   1;
+            uint32_t reserved17:            15;
+        };
+        uint32_t val;
+    } apb_ctrl_tick_conf;
+    union {
+        struct {
+            uint32_t clk20_oen:       1;
+            uint32_t clk22_oen:       1;
+            uint32_t clk44_oen:       1;
+            uint32_t clk_bb_oen:      1;
+            uint32_t clk80_oen:       1;
+            uint32_t clk160_oen:      1;
+            uint32_t clk_320m_oen:    1;
+            uint32_t clk_adc_inf_oen: 1;
+            uint32_t clk_dac_cpu_oen: 1;
+            uint32_t clk40x_bb_oen:   1;
+            uint32_t clk_xtal_oen:    1;
+            uint32_t reserved11:     21;
+        };
+        uint32_t val;
+    } apb_ctrl_clk_out_en;
+    uint32_t wifi_bb_cfg;                               /**/
+    uint32_t wifi_bb_cfg_2;                             /**/
+    uint32_t wifi_clk_en;                               /**/
+    uint32_t wifi_rst_en;                               /**/
+    union {
+        struct {
+            uint32_t peri_io_swap: 8;
+            uint32_t reserved8:   24;
+        };
+        uint32_t val;
+    } host_inf_sel;
+    union {
+        struct {
+            uint32_t ext_mem_pms_lock: 1;
+            uint32_t reserved1:       31;
+        };
+        uint32_t val;
+    } ext_mem_pms_lock;
+    uint32_t reserved_24;
+    union {
+        struct {
+            uint32_t flash_ace0_attr: 2;
+            uint32_t reserved2:      30;
+        };
+        uint32_t val;
+    } flash_ace0_attr;
+    union {
+        struct {
+            uint32_t flash_ace1_attr: 2;
+            uint32_t reserved2:      30;
+        };
+        uint32_t val;
+    } flash_ace1_attr;
+    union {
+        struct {
+            uint32_t flash_ace2_attr: 2;
+            uint32_t reserved2:      30;
+        };
+        uint32_t val;
+    } flash_ace2_attr;
+    union {
+        struct {
+            uint32_t flash_ace3_attr: 2;
+            uint32_t reserved2:      30;
+        };
+        uint32_t val;
+    } flash_ace3_attr;
+    uint32_t flash_ace0_addr;                           /**/
+    uint32_t flash_ace1_addr;                           /**/
+    uint32_t flash_ace2_addr;                           /**/
+    uint32_t flash_ace3_addr;                           /**/
+    union {
+        struct {
+            uint32_t flash_ace0_size:13;
+            uint32_t reserved13:     19;
+        };
+        uint32_t val;
+    } flash_ace0_size;
+    union {
+        struct {
+            uint32_t flash_ace1_size:13;
+            uint32_t reserved13:     19;
+        };
+        uint32_t val;
+    } flash_ace1_size;
+    union {
+        struct {
+            uint32_t flash_ace2_size:13;
+            uint32_t reserved13:     19;
+        };
+        uint32_t val;
+    } flash_ace2_size;
+    union {
+        struct {
+            uint32_t flash_ace3_size:13;
+            uint32_t reserved13:     19;
+        };
+        uint32_t val;
+    } flash_ace3_size;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    union {
+        struct {
+            uint32_t spi_mem_reject_int: 1;
+            uint32_t spi_mem_reject_clr: 1;
+            uint32_t spi_mem_reject_cde: 5;
+            uint32_t reserved7:         25;
+        };
+        uint32_t val;
+    } spi_mem_pms_ctrl;
+    uint32_t spi_mem_reject_addr;                       /**/
+    union {
+        struct {
+            uint32_t sdio_win_access_en: 1;
+            uint32_t reserved1:         31;
+        };
+        uint32_t val;
+    } apb_ctrl_sdio_ctrl;
+    union {
+        struct {
+            uint32_t redcy_sig0: 31;
+            uint32_t redcy_andor: 1;
+        };
+        uint32_t val;
+    } redcy_sig0;
+    union {
+        struct {
+            uint32_t redcy_sig1:  31;
+            uint32_t redcy_nandor: 1;
+        };
+        uint32_t val;
+    } redcy_sig1;
+    union {
+        struct {
+            uint32_t agc_mem_force_pu:  1;
+            uint32_t agc_mem_force_pd:  1;
+            uint32_t pbus_mem_force_pu: 1;
+            uint32_t pbus_mem_force_pd: 1;
+            uint32_t dc_mem_force_pu:   1;
+            uint32_t dc_mem_force_pd:   1;
+            uint32_t reserved6:        26;
+        };
+        uint32_t val;
+    } front_end_mem_pd;
+    union {
+        struct {
+            uint32_t retention_link_addr: 27;
+            uint32_t nobypass_cpu_iso_rst: 1;
+            uint32_t reserved28:           4;
+        };
+        uint32_t val;
+    } retention_ctrl;
+    union {
+        struct {
+            uint32_t rom_clkgate_force_on:  2;
+            uint32_t sram_clkgate_force_on: 4;
+            uint32_t reserved6:            26;
+        };
+        uint32_t val;
+    } clkgate_force_on;
+    union {
+        struct {
+            uint32_t rom_power_down:  2;
+            uint32_t sram_power_down: 4;
+            uint32_t reserved6:      26;
+        };
+        uint32_t val;
+    } mem_power_down;
+    union {
+        struct {
+            uint32_t rom_power_up:  2;
+            uint32_t sram_power_up: 4;
+            uint32_t reserved6:    26;
+        };
+        uint32_t val;
+    } mem_power_up;
+    uint32_t rnd_data;                                  /**/
+    union {
+        struct {
+            uint32_t reserved0:               1;
+            uint32_t peri_backup_flow_err:    2;
+            uint32_t reserved3:               1;
+            uint32_t peri_backup_burst_limit: 5;
+            uint32_t peri_backup_tout_thres: 10;
+            uint32_t peri_backup_size:       10;
+            uint32_t peri_backup_start:       1;
+            uint32_t peri_backup_to_mem:      1;
+            uint32_t peri_backup_ena:         1;
+        };
+        uint32_t val;
+    } peri_backup_config;
+    uint32_t peri_backup_apb_addr;                      /**/
+    uint32_t peri_backup_mem_addr;                      /**/
+    union {
+        struct {
+            uint32_t peri_backup_done:         1;
+            uint32_t peri_backup_err:          1;
+            uint32_t reserved2:               30;
+        };
+        uint32_t val;
+    } peri_backup_int_raw;
+    union {
+        struct {
+            uint32_t peri_backup_done:        1;
+            uint32_t peri_backup_err:         1;
+            uint32_t reserved2:              30;
+        };
+        uint32_t val;
+    } peri_backup_int_st;
+    union {
+        struct {
+            uint32_t peri_backup_done:         1;
+            uint32_t peri_backup_err:          1;
+            uint32_t reserved2:               30;
+        };
+        uint32_t val;
+    } peri_backup_int_ena;
+    uint32_t reserved_cc;
+    union {
+        struct {
+            uint32_t peri_backup_done:         1;
+            uint32_t peri_backup_err:          1;
+            uint32_t reserved2:               30;
+        };
+        uint32_t val;
+    } peri_backup_int_clr;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    uint32_t apb_ctrl_date;                             /*Version control*/
+} syscon_dev_t;
+extern syscon_dev_t SYSCON;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_SYSCON_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/system_reg.h b/components/soc/esp32c3/include/soc/system_reg.h
new file mode 100644
index 0000000000..3a67cb4606
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/system_reg.h
@@ -0,0 +1,1050 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SYSTEM_REG_H_
+#define _SOC_SYSTEM_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define SYSTEM_CPU_PERI_CLK_EN_REG          (DR_REG_SYSTEM_BASE + 0x000)
+/* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CLK_EN_DEDICATED_GPIO  (BIT(7))
+#define SYSTEM_CLK_EN_DEDICATED_GPIO_M  (BIT(7))
+#define SYSTEM_CLK_EN_DEDICATED_GPIO_V  0x1
+#define SYSTEM_CLK_EN_DEDICATED_GPIO_S  7
+/* SYSTEM_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CLK_EN_ASSIST_DEBUG  (BIT(6))
+#define SYSTEM_CLK_EN_ASSIST_DEBUG_M  (BIT(6))
+#define SYSTEM_CLK_EN_ASSIST_DEBUG_V  0x1
+#define SYSTEM_CLK_EN_ASSIST_DEBUG_S  6
+
+#define SYSTEM_CPU_PERI_RST_EN_REG          (DR_REG_SYSTEM_BASE + 0x004)
+/* SYSTEM_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_RST_EN_DEDICATED_GPIO  (BIT(7))
+#define SYSTEM_RST_EN_DEDICATED_GPIO_M  (BIT(7))
+#define SYSTEM_RST_EN_DEDICATED_GPIO_V  0x1
+#define SYSTEM_RST_EN_DEDICATED_GPIO_S  7
+/* SYSTEM_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_RST_EN_ASSIST_DEBUG  (BIT(6))
+#define SYSTEM_RST_EN_ASSIST_DEBUG_M  (BIT(6))
+#define SYSTEM_RST_EN_ASSIST_DEBUG_V  0x1
+#define SYSTEM_RST_EN_ASSIST_DEBUG_S  6
+
+#define SYSTEM_CPU_PER_CONF_REG          (DR_REG_SYSTEM_BASE + 0x008)
+/* SYSTEM_CPU_WAITI_DELAY_NUM : R/W ;bitpos:[7:4] ;default: 4'h0 ; */
+/*description: */
+#define SYSTEM_CPU_WAITI_DELAY_NUM  0x0000000F
+#define SYSTEM_CPU_WAITI_DELAY_NUM_M  ((SYSTEM_CPU_WAITI_DELAY_NUM_V)<<(SYSTEM_CPU_WAITI_DELAY_NUM_S))
+#define SYSTEM_CPU_WAITI_DELAY_NUM_V  0xF
+#define SYSTEM_CPU_WAITI_DELAY_NUM_S  4
+/* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON  (BIT(3))
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M  (BIT(3))
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V  0x1
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S  3
+/* SYSTEM_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_PLL_FREQ_SEL  (BIT(2))
+#define SYSTEM_PLL_FREQ_SEL_M  (BIT(2))
+#define SYSTEM_PLL_FREQ_SEL_V  0x1
+#define SYSTEM_PLL_FREQ_SEL_S  2
+/* SYSTEM_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define SYSTEM_CPUPERIOD_SEL  0x00000003
+#define SYSTEM_CPUPERIOD_SEL_M  ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S))
+#define SYSTEM_CPUPERIOD_SEL_V  0x3
+#define SYSTEM_CPUPERIOD_SEL_S  0
+
+#define SYSTEM_MEM_PD_MASK_REG          (DR_REG_SYSTEM_BASE + 0x00C)
+/* SYSTEM_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_LSLP_MEM_PD_MASK  (BIT(0))
+#define SYSTEM_LSLP_MEM_PD_MASK_M  (BIT(0))
+#define SYSTEM_LSLP_MEM_PD_MASK_V  0x1
+#define SYSTEM_LSLP_MEM_PD_MASK_S  0
+
+#define SYSTEM_PERIP_CLK_EN0_REG          (DR_REG_SYSTEM_BASE + 0x010)
+/* SYSTEM_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */
+/*description: */
+#define SYSTEM_SPI4_CLK_EN  (BIT(31))
+#define SYSTEM_SPI4_CLK_EN_M  (BIT(31))
+#define SYSTEM_SPI4_CLK_EN_V  0x1
+#define SYSTEM_SPI4_CLK_EN_S  31
+/* SYSTEM_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_ADC2_ARB_CLK_EN  (BIT(30))
+#define SYSTEM_ADC2_ARB_CLK_EN_M  (BIT(30))
+#define SYSTEM_ADC2_ARB_CLK_EN_V  0x1
+#define SYSTEM_ADC2_ARB_CLK_EN_S  30
+/* SYSTEM_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_SYSTIMER_CLK_EN  (BIT(29))
+#define SYSTEM_SYSTIMER_CLK_EN_M  (BIT(29))
+#define SYSTEM_SYSTIMER_CLK_EN_V  0x1
+#define SYSTEM_SYSTIMER_CLK_EN_S  29
+/* SYSTEM_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_APB_SARADC_CLK_EN  (BIT(28))
+#define SYSTEM_APB_SARADC_CLK_EN_M  (BIT(28))
+#define SYSTEM_APB_SARADC_CLK_EN_V  0x1
+#define SYSTEM_APB_SARADC_CLK_EN_S  28
+/* SYSTEM_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_SPI3_DMA_CLK_EN  (BIT(27))
+#define SYSTEM_SPI3_DMA_CLK_EN_M  (BIT(27))
+#define SYSTEM_SPI3_DMA_CLK_EN_V  0x1
+#define SYSTEM_SPI3_DMA_CLK_EN_S  27
+/* SYSTEM_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PWM3_CLK_EN  (BIT(26))
+#define SYSTEM_PWM3_CLK_EN_M  (BIT(26))
+#define SYSTEM_PWM3_CLK_EN_V  0x1
+#define SYSTEM_PWM3_CLK_EN_S  26
+/* SYSTEM_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PWM2_CLK_EN  (BIT(25))
+#define SYSTEM_PWM2_CLK_EN_M  (BIT(25))
+#define SYSTEM_PWM2_CLK_EN_V  0x1
+#define SYSTEM_PWM2_CLK_EN_S  25
+/* SYSTEM_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_UART_MEM_CLK_EN  (BIT(24))
+#define SYSTEM_UART_MEM_CLK_EN_M  (BIT(24))
+#define SYSTEM_UART_MEM_CLK_EN_V  0x1
+#define SYSTEM_UART_MEM_CLK_EN_S  24
+/* SYSTEM_USB_DEVICE_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_USB_DEVICE_CLK_EN  (BIT(23))
+#define SYSTEM_USB_DEVICE_CLK_EN_M  (BIT(23))
+#define SYSTEM_USB_DEVICE_CLK_EN_V  0x1
+#define SYSTEM_USB_DEVICE_CLK_EN_S  23
+/* SYSTEM_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_SPI2_DMA_CLK_EN  (BIT(22))
+#define SYSTEM_SPI2_DMA_CLK_EN_M  (BIT(22))
+#define SYSTEM_SPI2_DMA_CLK_EN_V  0x1
+#define SYSTEM_SPI2_DMA_CLK_EN_S  22
+/* SYSTEM_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_I2S1_CLK_EN  (BIT(21))
+#define SYSTEM_I2S1_CLK_EN_M  (BIT(21))
+#define SYSTEM_I2S1_CLK_EN_V  0x1
+#define SYSTEM_I2S1_CLK_EN_S  21
+/* SYSTEM_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PWM1_CLK_EN  (BIT(20))
+#define SYSTEM_PWM1_CLK_EN_M  (BIT(20))
+#define SYSTEM_PWM1_CLK_EN_V  0x1
+#define SYSTEM_PWM1_CLK_EN_S  20
+/* SYSTEM_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_TWAI_CLK_EN  (BIT(19))
+#define SYSTEM_TWAI_CLK_EN_M  (BIT(19))
+#define SYSTEM_TWAI_CLK_EN_V  0x1
+#define SYSTEM_TWAI_CLK_EN_S  19
+/* SYSTEM_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_I2C_EXT1_CLK_EN  (BIT(18))
+#define SYSTEM_I2C_EXT1_CLK_EN_M  (BIT(18))
+#define SYSTEM_I2C_EXT1_CLK_EN_V  0x1
+#define SYSTEM_I2C_EXT1_CLK_EN_S  18
+/* SYSTEM_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PWM0_CLK_EN  (BIT(17))
+#define SYSTEM_PWM0_CLK_EN_M  (BIT(17))
+#define SYSTEM_PWM0_CLK_EN_V  0x1
+#define SYSTEM_PWM0_CLK_EN_S  17
+/* SYSTEM_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_SPI3_CLK_EN  (BIT(16))
+#define SYSTEM_SPI3_CLK_EN_M  (BIT(16))
+#define SYSTEM_SPI3_CLK_EN_V  0x1
+#define SYSTEM_SPI3_CLK_EN_S  16
+/* SYSTEM_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_TIMERGROUP1_CLK_EN  (BIT(15))
+#define SYSTEM_TIMERGROUP1_CLK_EN_M  (BIT(15))
+#define SYSTEM_TIMERGROUP1_CLK_EN_V  0x1
+#define SYSTEM_TIMERGROUP1_CLK_EN_S  15
+/* SYSTEM_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_EFUSE_CLK_EN  (BIT(14))
+#define SYSTEM_EFUSE_CLK_EN_M  (BIT(14))
+#define SYSTEM_EFUSE_CLK_EN_V  0x1
+#define SYSTEM_EFUSE_CLK_EN_S  14
+/* SYSTEM_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_TIMERGROUP_CLK_EN  (BIT(13))
+#define SYSTEM_TIMERGROUP_CLK_EN_M  (BIT(13))
+#define SYSTEM_TIMERGROUP_CLK_EN_V  0x1
+#define SYSTEM_TIMERGROUP_CLK_EN_S  13
+/* SYSTEM_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_UHCI1_CLK_EN  (BIT(12))
+#define SYSTEM_UHCI1_CLK_EN_M  (BIT(12))
+#define SYSTEM_UHCI1_CLK_EN_V  0x1
+#define SYSTEM_UHCI1_CLK_EN_S  12
+/* SYSTEM_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_LEDC_CLK_EN  (BIT(11))
+#define SYSTEM_LEDC_CLK_EN_M  (BIT(11))
+#define SYSTEM_LEDC_CLK_EN_V  0x1
+#define SYSTEM_LEDC_CLK_EN_S  11
+/* SYSTEM_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PCNT_CLK_EN  (BIT(10))
+#define SYSTEM_PCNT_CLK_EN_M  (BIT(10))
+#define SYSTEM_PCNT_CLK_EN_V  0x1
+#define SYSTEM_PCNT_CLK_EN_S  10
+/* SYSTEM_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_RMT_CLK_EN  (BIT(9))
+#define SYSTEM_RMT_CLK_EN_M  (BIT(9))
+#define SYSTEM_RMT_CLK_EN_V  0x1
+#define SYSTEM_RMT_CLK_EN_S  9
+/* SYSTEM_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_UHCI0_CLK_EN  (BIT(8))
+#define SYSTEM_UHCI0_CLK_EN_M  (BIT(8))
+#define SYSTEM_UHCI0_CLK_EN_V  0x1
+#define SYSTEM_UHCI0_CLK_EN_S  8
+/* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_I2C_EXT0_CLK_EN  (BIT(7))
+#define SYSTEM_I2C_EXT0_CLK_EN_M  (BIT(7))
+#define SYSTEM_I2C_EXT0_CLK_EN_V  0x1
+#define SYSTEM_I2C_EXT0_CLK_EN_S  7
+/* SYSTEM_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_SPI2_CLK_EN  (BIT(6))
+#define SYSTEM_SPI2_CLK_EN_M  (BIT(6))
+#define SYSTEM_SPI2_CLK_EN_V  0x1
+#define SYSTEM_SPI2_CLK_EN_S  6
+/* SYSTEM_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_UART1_CLK_EN  (BIT(5))
+#define SYSTEM_UART1_CLK_EN_M  (BIT(5))
+#define SYSTEM_UART1_CLK_EN_V  0x1
+#define SYSTEM_UART1_CLK_EN_S  5
+/* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_I2S0_CLK_EN  (BIT(4))
+#define SYSTEM_I2S0_CLK_EN_M  (BIT(4))
+#define SYSTEM_I2S0_CLK_EN_V  0x1
+#define SYSTEM_I2S0_CLK_EN_S  4
+/* SYSTEM_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_WDG_CLK_EN  (BIT(3))
+#define SYSTEM_WDG_CLK_EN_M  (BIT(3))
+#define SYSTEM_WDG_CLK_EN_V  0x1
+#define SYSTEM_WDG_CLK_EN_S  3
+/* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_UART_CLK_EN  (BIT(2))
+#define SYSTEM_UART_CLK_EN_M  (BIT(2))
+#define SYSTEM_UART_CLK_EN_V  0x1
+#define SYSTEM_UART_CLK_EN_S  2
+/* SYSTEM_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_SPI01_CLK_EN  (BIT(1))
+#define SYSTEM_SPI01_CLK_EN_M  (BIT(1))
+#define SYSTEM_SPI01_CLK_EN_V  0x1
+#define SYSTEM_SPI01_CLK_EN_S  1
+/* SYSTEM_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_TIMERS_CLK_EN  (BIT(0))
+#define SYSTEM_TIMERS_CLK_EN_M  (BIT(0))
+#define SYSTEM_TIMERS_CLK_EN_V  0x1
+#define SYSTEM_TIMERS_CLK_EN_S  0
+
+#define SYSTEM_PERIP_CLK_EN1_REG          (DR_REG_SYSTEM_BASE + 0x014)
+/* SYSTEM_TSENS_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_TSENS_CLK_EN  (BIT(10))
+#define SYSTEM_TSENS_CLK_EN_M  (BIT(10))
+#define SYSTEM_TSENS_CLK_EN_V  0x1
+#define SYSTEM_TSENS_CLK_EN_S  10
+/* SYSTEM_UART2_CLK_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_UART2_CLK_EN  (BIT(9))
+#define SYSTEM_UART2_CLK_EN_M  (BIT(9))
+#define SYSTEM_UART2_CLK_EN_V  0x1
+#define SYSTEM_UART2_CLK_EN_S  9
+/* SYSTEM_LCD_CAM_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_LCD_CAM_CLK_EN  (BIT(8))
+#define SYSTEM_LCD_CAM_CLK_EN_M  (BIT(8))
+#define SYSTEM_LCD_CAM_CLK_EN_V  0x1
+#define SYSTEM_LCD_CAM_CLK_EN_S  8
+/* SYSTEM_SDIO_HOST_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_SDIO_HOST_CLK_EN  (BIT(7))
+#define SYSTEM_SDIO_HOST_CLK_EN_M  (BIT(7))
+#define SYSTEM_SDIO_HOST_CLK_EN_V  0x1
+#define SYSTEM_SDIO_HOST_CLK_EN_S  7
+/* SYSTEM_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_DMA_CLK_EN  (BIT(6))
+#define SYSTEM_DMA_CLK_EN_M  (BIT(6))
+#define SYSTEM_DMA_CLK_EN_V  0x1
+#define SYSTEM_DMA_CLK_EN_S  6
+/* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CRYPTO_HMAC_CLK_EN  (BIT(5))
+#define SYSTEM_CRYPTO_HMAC_CLK_EN_M  (BIT(5))
+#define SYSTEM_CRYPTO_HMAC_CLK_EN_V  0x1
+#define SYSTEM_CRYPTO_HMAC_CLK_EN_S  5
+/* SYSTEM_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CRYPTO_DS_CLK_EN  (BIT(4))
+#define SYSTEM_CRYPTO_DS_CLK_EN_M  (BIT(4))
+#define SYSTEM_CRYPTO_DS_CLK_EN_V  0x1
+#define SYSTEM_CRYPTO_DS_CLK_EN_S  4
+/* SYSTEM_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CRYPTO_RSA_CLK_EN  (BIT(3))
+#define SYSTEM_CRYPTO_RSA_CLK_EN_M  (BIT(3))
+#define SYSTEM_CRYPTO_RSA_CLK_EN_V  0x1
+#define SYSTEM_CRYPTO_RSA_CLK_EN_S  3
+/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CRYPTO_SHA_CLK_EN  (BIT(2))
+#define SYSTEM_CRYPTO_SHA_CLK_EN_M  (BIT(2))
+#define SYSTEM_CRYPTO_SHA_CLK_EN_V  0x1
+#define SYSTEM_CRYPTO_SHA_CLK_EN_S  2
+/* SYSTEM_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CRYPTO_AES_CLK_EN  (BIT(1))
+#define SYSTEM_CRYPTO_AES_CLK_EN_M  (BIT(1))
+#define SYSTEM_CRYPTO_AES_CLK_EN_V  0x1
+#define SYSTEM_CRYPTO_AES_CLK_EN_S  1
+
+#define SYSTEM_PERIP_RST_EN0_REG          (DR_REG_SYSTEM_BASE + 0x018)
+/* SYSTEM_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define SYSTEM_SPI4_RST  (BIT(31))
+#define SYSTEM_SPI4_RST_M  (BIT(31))
+#define SYSTEM_SPI4_RST_V  0x1
+#define SYSTEM_SPI4_RST_S  31
+/* SYSTEM_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_ADC2_ARB_RST  (BIT(30))
+#define SYSTEM_ADC2_ARB_RST_M  (BIT(30))
+#define SYSTEM_ADC2_ARB_RST_V  0x1
+#define SYSTEM_ADC2_ARB_RST_S  30
+/* SYSTEM_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_SYSTIMER_RST  (BIT(29))
+#define SYSTEM_SYSTIMER_RST_M  (BIT(29))
+#define SYSTEM_SYSTIMER_RST_V  0x1
+#define SYSTEM_SYSTIMER_RST_S  29
+/* SYSTEM_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_APB_SARADC_RST  (BIT(28))
+#define SYSTEM_APB_SARADC_RST_M  (BIT(28))
+#define SYSTEM_APB_SARADC_RST_V  0x1
+#define SYSTEM_APB_SARADC_RST_S  28
+/* SYSTEM_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_SPI3_DMA_RST  (BIT(27))
+#define SYSTEM_SPI3_DMA_RST_M  (BIT(27))
+#define SYSTEM_SPI3_DMA_RST_V  0x1
+#define SYSTEM_SPI3_DMA_RST_S  27
+/* SYSTEM_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PWM3_RST  (BIT(26))
+#define SYSTEM_PWM3_RST_M  (BIT(26))
+#define SYSTEM_PWM3_RST_V  0x1
+#define SYSTEM_PWM3_RST_S  26
+/* SYSTEM_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PWM2_RST  (BIT(25))
+#define SYSTEM_PWM2_RST_M  (BIT(25))
+#define SYSTEM_PWM2_RST_V  0x1
+#define SYSTEM_PWM2_RST_S  25
+/* SYSTEM_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_UART_MEM_RST  (BIT(24))
+#define SYSTEM_UART_MEM_RST_M  (BIT(24))
+#define SYSTEM_UART_MEM_RST_V  0x1
+#define SYSTEM_UART_MEM_RST_S  24
+/* SYSTEM_USB_DEVICE_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_USB_DEVICE_RST  (BIT(23))
+#define SYSTEM_USB_DEVICE_RST_M  (BIT(23))
+#define SYSTEM_USB_DEVICE_RST_V  0x1
+#define SYSTEM_USB_DEVICE_RST_S  23
+/* SYSTEM_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_SPI2_DMA_RST  (BIT(22))
+#define SYSTEM_SPI2_DMA_RST_M  (BIT(22))
+#define SYSTEM_SPI2_DMA_RST_V  0x1
+#define SYSTEM_SPI2_DMA_RST_S  22
+/* SYSTEM_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_I2S1_RST  (BIT(21))
+#define SYSTEM_I2S1_RST_M  (BIT(21))
+#define SYSTEM_I2S1_RST_V  0x1
+#define SYSTEM_I2S1_RST_S  21
+/* SYSTEM_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PWM1_RST  (BIT(20))
+#define SYSTEM_PWM1_RST_M  (BIT(20))
+#define SYSTEM_PWM1_RST_V  0x1
+#define SYSTEM_PWM1_RST_S  20
+/* SYSTEM_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_TWAI_RST  (BIT(19))
+#define SYSTEM_TWAI_RST_M  (BIT(19))
+#define SYSTEM_TWAI_RST_V  0x1
+#define SYSTEM_TWAI_RST_S  19
+/* SYSTEM_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_I2C_EXT1_RST  (BIT(18))
+#define SYSTEM_I2C_EXT1_RST_M  (BIT(18))
+#define SYSTEM_I2C_EXT1_RST_V  0x1
+#define SYSTEM_I2C_EXT1_RST_S  18
+/* SYSTEM_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PWM0_RST  (BIT(17))
+#define SYSTEM_PWM0_RST_M  (BIT(17))
+#define SYSTEM_PWM0_RST_V  0x1
+#define SYSTEM_PWM0_RST_S  17
+/* SYSTEM_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_SPI3_RST  (BIT(16))
+#define SYSTEM_SPI3_RST_M  (BIT(16))
+#define SYSTEM_SPI3_RST_V  0x1
+#define SYSTEM_SPI3_RST_S  16
+/* SYSTEM_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_TIMERGROUP1_RST  (BIT(15))
+#define SYSTEM_TIMERGROUP1_RST_M  (BIT(15))
+#define SYSTEM_TIMERGROUP1_RST_V  0x1
+#define SYSTEM_TIMERGROUP1_RST_S  15
+/* SYSTEM_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_EFUSE_RST  (BIT(14))
+#define SYSTEM_EFUSE_RST_M  (BIT(14))
+#define SYSTEM_EFUSE_RST_V  0x1
+#define SYSTEM_EFUSE_RST_S  14
+/* SYSTEM_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_TIMERGROUP_RST  (BIT(13))
+#define SYSTEM_TIMERGROUP_RST_M  (BIT(13))
+#define SYSTEM_TIMERGROUP_RST_V  0x1
+#define SYSTEM_TIMERGROUP_RST_S  13
+/* SYSTEM_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_UHCI1_RST  (BIT(12))
+#define SYSTEM_UHCI1_RST_M  (BIT(12))
+#define SYSTEM_UHCI1_RST_V  0x1
+#define SYSTEM_UHCI1_RST_S  12
+/* SYSTEM_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_LEDC_RST  (BIT(11))
+#define SYSTEM_LEDC_RST_M  (BIT(11))
+#define SYSTEM_LEDC_RST_V  0x1
+#define SYSTEM_LEDC_RST_S  11
+/* SYSTEM_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PCNT_RST  (BIT(10))
+#define SYSTEM_PCNT_RST_M  (BIT(10))
+#define SYSTEM_PCNT_RST_V  0x1
+#define SYSTEM_PCNT_RST_S  10
+/* SYSTEM_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_RMT_RST  (BIT(9))
+#define SYSTEM_RMT_RST_M  (BIT(9))
+#define SYSTEM_RMT_RST_V  0x1
+#define SYSTEM_RMT_RST_S  9
+/* SYSTEM_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_UHCI0_RST  (BIT(8))
+#define SYSTEM_UHCI0_RST_M  (BIT(8))
+#define SYSTEM_UHCI0_RST_V  0x1
+#define SYSTEM_UHCI0_RST_S  8
+/* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_I2C_EXT0_RST  (BIT(7))
+#define SYSTEM_I2C_EXT0_RST_M  (BIT(7))
+#define SYSTEM_I2C_EXT0_RST_V  0x1
+#define SYSTEM_I2C_EXT0_RST_S  7
+/* SYSTEM_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_SPI2_RST  (BIT(6))
+#define SYSTEM_SPI2_RST_M  (BIT(6))
+#define SYSTEM_SPI2_RST_V  0x1
+#define SYSTEM_SPI2_RST_S  6
+/* SYSTEM_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_UART1_RST  (BIT(5))
+#define SYSTEM_UART1_RST_M  (BIT(5))
+#define SYSTEM_UART1_RST_V  0x1
+#define SYSTEM_UART1_RST_S  5
+/* SYSTEM_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_I2S0_RST  (BIT(4))
+#define SYSTEM_I2S0_RST_M  (BIT(4))
+#define SYSTEM_I2S0_RST_V  0x1
+#define SYSTEM_I2S0_RST_S  4
+/* SYSTEM_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_WDG_RST  (BIT(3))
+#define SYSTEM_WDG_RST_M  (BIT(3))
+#define SYSTEM_WDG_RST_V  0x1
+#define SYSTEM_WDG_RST_S  3
+/* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_UART_RST  (BIT(2))
+#define SYSTEM_UART_RST_M  (BIT(2))
+#define SYSTEM_UART_RST_V  0x1
+#define SYSTEM_UART_RST_S  2
+/* SYSTEM_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_SPI01_RST  (BIT(1))
+#define SYSTEM_SPI01_RST_M  (BIT(1))
+#define SYSTEM_SPI01_RST_V  0x1
+#define SYSTEM_SPI01_RST_S  1
+/* SYSTEM_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_TIMERS_RST  (BIT(0))
+#define SYSTEM_TIMERS_RST_M  (BIT(0))
+#define SYSTEM_TIMERS_RST_V  0x1
+#define SYSTEM_TIMERS_RST_S  0
+
+#define SYSTEM_PERIP_RST_EN1_REG          (DR_REG_SYSTEM_BASE + 0x01C)
+/* SYSTEM_TSENS_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_TSENS_RST  (BIT(10))
+#define SYSTEM_TSENS_RST_M  (BIT(10))
+#define SYSTEM_TSENS_RST_V  0x1
+#define SYSTEM_TSENS_RST_S  10
+/* SYSTEM_UART2_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_UART2_RST  (BIT(9))
+#define SYSTEM_UART2_RST_M  (BIT(9))
+#define SYSTEM_UART2_RST_V  0x1
+#define SYSTEM_UART2_RST_S  9
+/* SYSTEM_LCD_CAM_RST : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_LCD_CAM_RST  (BIT(8))
+#define SYSTEM_LCD_CAM_RST_M  (BIT(8))
+#define SYSTEM_LCD_CAM_RST_V  0x1
+#define SYSTEM_LCD_CAM_RST_S  8
+/* SYSTEM_SDIO_HOST_RST : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_SDIO_HOST_RST  (BIT(7))
+#define SYSTEM_SDIO_HOST_RST_M  (BIT(7))
+#define SYSTEM_SDIO_HOST_RST_V  0x1
+#define SYSTEM_SDIO_HOST_RST_S  7
+/* SYSTEM_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_DMA_RST  (BIT(6))
+#define SYSTEM_DMA_RST_M  (BIT(6))
+#define SYSTEM_DMA_RST_V  0x1
+#define SYSTEM_DMA_RST_S  6
+/* SYSTEM_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_CRYPTO_HMAC_RST  (BIT(5))
+#define SYSTEM_CRYPTO_HMAC_RST_M  (BIT(5))
+#define SYSTEM_CRYPTO_HMAC_RST_V  0x1
+#define SYSTEM_CRYPTO_HMAC_RST_S  5
+/* SYSTEM_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_CRYPTO_DS_RST  (BIT(4))
+#define SYSTEM_CRYPTO_DS_RST_M  (BIT(4))
+#define SYSTEM_CRYPTO_DS_RST_V  0x1
+#define SYSTEM_CRYPTO_DS_RST_S  4
+/* SYSTEM_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_CRYPTO_RSA_RST  (BIT(3))
+#define SYSTEM_CRYPTO_RSA_RST_M  (BIT(3))
+#define SYSTEM_CRYPTO_RSA_RST_V  0x1
+#define SYSTEM_CRYPTO_RSA_RST_S  3
+/* SYSTEM_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_CRYPTO_SHA_RST  (BIT(2))
+#define SYSTEM_CRYPTO_SHA_RST_M  (BIT(2))
+#define SYSTEM_CRYPTO_SHA_RST_V  0x1
+#define SYSTEM_CRYPTO_SHA_RST_S  2
+/* SYSTEM_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_CRYPTO_AES_RST  (BIT(1))
+#define SYSTEM_CRYPTO_AES_RST_M  (BIT(1))
+#define SYSTEM_CRYPTO_AES_RST_V  0x1
+#define SYSTEM_CRYPTO_AES_RST_S  1
+
+#define SYSTEM_BT_LPCK_DIV_INT_REG          (DR_REG_SYSTEM_BASE + 0x020)
+/* SYSTEM_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */
+/*description: */
+#define SYSTEM_BT_LPCK_DIV_NUM  0x00000FFF
+#define SYSTEM_BT_LPCK_DIV_NUM_M  ((SYSTEM_BT_LPCK_DIV_NUM_V)<<(SYSTEM_BT_LPCK_DIV_NUM_S))
+#define SYSTEM_BT_LPCK_DIV_NUM_V  0xFFF
+#define SYSTEM_BT_LPCK_DIV_NUM_S  0
+
+#define SYSTEM_BT_LPCK_DIV_FRAC_REG          (DR_REG_SYSTEM_BASE + 0x024)
+/* SYSTEM_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_LPCLK_RTC_EN  (BIT(28))
+#define SYSTEM_LPCLK_RTC_EN_M  (BIT(28))
+#define SYSTEM_LPCLK_RTC_EN_V  0x1
+#define SYSTEM_LPCLK_RTC_EN_S  28
+/* SYSTEM_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_LPCLK_SEL_XTAL32K  (BIT(27))
+#define SYSTEM_LPCLK_SEL_XTAL32K_M  (BIT(27))
+#define SYSTEM_LPCLK_SEL_XTAL32K_V  0x1
+#define SYSTEM_LPCLK_SEL_XTAL32K_S  27
+/* SYSTEM_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_LPCLK_SEL_XTAL  (BIT(26))
+#define SYSTEM_LPCLK_SEL_XTAL_M  (BIT(26))
+#define SYSTEM_LPCLK_SEL_XTAL_V  0x1
+#define SYSTEM_LPCLK_SEL_XTAL_S  26
+/* SYSTEM_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_LPCLK_SEL_8M  (BIT(25))
+#define SYSTEM_LPCLK_SEL_8M_M  (BIT(25))
+#define SYSTEM_LPCLK_SEL_8M_V  0x1
+#define SYSTEM_LPCLK_SEL_8M_S  25
+/* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_LPCLK_SEL_RTC_SLOW  (BIT(24))
+#define SYSTEM_LPCLK_SEL_RTC_SLOW_M  (BIT(24))
+#define SYSTEM_LPCLK_SEL_RTC_SLOW_V  0x1
+#define SYSTEM_LPCLK_SEL_RTC_SLOW_S  24
+/* SYSTEM_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */
+/*description: */
+#define SYSTEM_BT_LPCK_DIV_A  0x00000FFF
+#define SYSTEM_BT_LPCK_DIV_A_M  ((SYSTEM_BT_LPCK_DIV_A_V)<<(SYSTEM_BT_LPCK_DIV_A_S))
+#define SYSTEM_BT_LPCK_DIV_A_V  0xFFF
+#define SYSTEM_BT_LPCK_DIV_A_S  12
+/* SYSTEM_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */
+/*description: */
+#define SYSTEM_BT_LPCK_DIV_B  0x00000FFF
+#define SYSTEM_BT_LPCK_DIV_B_M  ((SYSTEM_BT_LPCK_DIV_B_V)<<(SYSTEM_BT_LPCK_DIV_B_S))
+#define SYSTEM_BT_LPCK_DIV_B_V  0xFFF
+#define SYSTEM_BT_LPCK_DIV_B_S  0
+
+#define SYSTEM_CPU_INTR_FROM_CPU_0_REG          (DR_REG_SYSTEM_BASE + 0x028)
+/* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CPU_INTR_FROM_CPU_0  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_0_M  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_0_V  0x1
+#define SYSTEM_CPU_INTR_FROM_CPU_0_S  0
+
+#define SYSTEM_CPU_INTR_FROM_CPU_1_REG          (DR_REG_SYSTEM_BASE + 0x02C)
+/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CPU_INTR_FROM_CPU_1  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_1_M  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_1_V  0x1
+#define SYSTEM_CPU_INTR_FROM_CPU_1_S  0
+
+#define SYSTEM_CPU_INTR_FROM_CPU_2_REG          (DR_REG_SYSTEM_BASE + 0x030)
+/* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CPU_INTR_FROM_CPU_2  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_2_M  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_2_V  0x1
+#define SYSTEM_CPU_INTR_FROM_CPU_2_S  0
+
+#define SYSTEM_CPU_INTR_FROM_CPU_3_REG          (DR_REG_SYSTEM_BASE + 0x034)
+/* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CPU_INTR_FROM_CPU_3  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_3_M  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_3_V  0x1
+#define SYSTEM_CPU_INTR_FROM_CPU_3_S  0
+
+#define SYSTEM_RSA_PD_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x038)
+/* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_RSA_MEM_FORCE_PD  (BIT(2))
+#define SYSTEM_RSA_MEM_FORCE_PD_M  (BIT(2))
+#define SYSTEM_RSA_MEM_FORCE_PD_V  0x1
+#define SYSTEM_RSA_MEM_FORCE_PD_S  2
+/* SYSTEM_RSA_MEM_FORCE_PU : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_RSA_MEM_FORCE_PU  (BIT(1))
+#define SYSTEM_RSA_MEM_FORCE_PU_M  (BIT(1))
+#define SYSTEM_RSA_MEM_FORCE_PU_V  0x1
+#define SYSTEM_RSA_MEM_FORCE_PU_S  1
+/* SYSTEM_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_RSA_MEM_PD  (BIT(0))
+#define SYSTEM_RSA_MEM_PD_M  (BIT(0))
+#define SYSTEM_RSA_MEM_PD_V  0x1
+#define SYSTEM_RSA_MEM_PD_S  0
+
+#define SYSTEM_EDMA_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x03C)
+/* SYSTEM_EDMA_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_EDMA_RESET  (BIT(1))
+#define SYSTEM_EDMA_RESET_M  (BIT(1))
+#define SYSTEM_EDMA_RESET_V  0x1
+#define SYSTEM_EDMA_RESET_S  1
+/* SYSTEM_EDMA_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_EDMA_CLK_ON  (BIT(0))
+#define SYSTEM_EDMA_CLK_ON_M  (BIT(0))
+#define SYSTEM_EDMA_CLK_ON_V  0x1
+#define SYSTEM_EDMA_CLK_ON_S  0
+
+#define SYSTEM_CACHE_CONTROL_REG          (DR_REG_SYSTEM_BASE + 0x040)
+/* SYSTEM_DCACHE_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_DCACHE_RESET  (BIT(3))
+#define SYSTEM_DCACHE_RESET_M  (BIT(3))
+#define SYSTEM_DCACHE_RESET_V  0x1
+#define SYSTEM_DCACHE_RESET_S  3
+/* SYSTEM_DCACHE_CLK_ON : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_DCACHE_CLK_ON  (BIT(2))
+#define SYSTEM_DCACHE_CLK_ON_M  (BIT(2))
+#define SYSTEM_DCACHE_CLK_ON_V  0x1
+#define SYSTEM_DCACHE_CLK_ON_S  2
+/* SYSTEM_ICACHE_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_ICACHE_RESET  (BIT(1))
+#define SYSTEM_ICACHE_RESET_M  (BIT(1))
+#define SYSTEM_ICACHE_RESET_V  0x1
+#define SYSTEM_ICACHE_RESET_S  1
+/* SYSTEM_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_ICACHE_CLK_ON  (BIT(0))
+#define SYSTEM_ICACHE_CLK_ON_M  (BIT(0))
+#define SYSTEM_ICACHE_CLK_ON_V  0x1
+#define SYSTEM_ICACHE_CLK_ON_S  0
+
+#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG          (DR_REG_SYSTEM_BASE + 0x044)
+/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT  (BIT(3))
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M  (BIT(3))
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V  0x1
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S  3
+/* SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT  (BIT(2))
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M  (BIT(2))
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V  0x1
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S  2
+/* SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT  (BIT(1))
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M  (BIT(1))
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V  0x1
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S  1
+/* SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT  (BIT(0))
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M  (BIT(0))
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V  0x1
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S  0
+
+#define SYSTEM_RTC_FASTMEM_CONFIG_REG          (DR_REG_SYSTEM_BASE + 0x048)
+/* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_RTC_MEM_CRC_FINISH  (BIT(31))
+#define SYSTEM_RTC_MEM_CRC_FINISH_M  (BIT(31))
+#define SYSTEM_RTC_MEM_CRC_FINISH_V  0x1
+#define SYSTEM_RTC_MEM_CRC_FINISH_S  31
+/* SYSTEM_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */
+/*description: */
+#define SYSTEM_RTC_MEM_CRC_LEN  0x000007FF
+#define SYSTEM_RTC_MEM_CRC_LEN_M  ((SYSTEM_RTC_MEM_CRC_LEN_V)<<(SYSTEM_RTC_MEM_CRC_LEN_S))
+#define SYSTEM_RTC_MEM_CRC_LEN_V  0x7FF
+#define SYSTEM_RTC_MEM_CRC_LEN_S  20
+/* SYSTEM_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */
+/*description: */
+#define SYSTEM_RTC_MEM_CRC_ADDR  0x000007FF
+#define SYSTEM_RTC_MEM_CRC_ADDR_M  ((SYSTEM_RTC_MEM_CRC_ADDR_V)<<(SYSTEM_RTC_MEM_CRC_ADDR_S))
+#define SYSTEM_RTC_MEM_CRC_ADDR_V  0x7FF
+#define SYSTEM_RTC_MEM_CRC_ADDR_S  9
+/* SYSTEM_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_RTC_MEM_CRC_START  (BIT(8))
+#define SYSTEM_RTC_MEM_CRC_START_M  (BIT(8))
+#define SYSTEM_RTC_MEM_CRC_START_V  0x1
+#define SYSTEM_RTC_MEM_CRC_START_S  8
+
+#define SYSTEM_RTC_FASTMEM_CRC_REG          (DR_REG_SYSTEM_BASE + 0x04C)
+/* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SYSTEM_RTC_MEM_CRC_RES  0xFFFFFFFF
+#define SYSTEM_RTC_MEM_CRC_RES_M  ((SYSTEM_RTC_MEM_CRC_RES_V)<<(SYSTEM_RTC_MEM_CRC_RES_S))
+#define SYSTEM_RTC_MEM_CRC_RES_V  0xFFFFFFFF
+#define SYSTEM_RTC_MEM_CRC_RES_S  0
+
+#define SYSTEM_REDUNDANT_ECO_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x050)
+/* SYSTEM_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_REDUNDANT_ECO_RESULT  (BIT(1))
+#define SYSTEM_REDUNDANT_ECO_RESULT_M  (BIT(1))
+#define SYSTEM_REDUNDANT_ECO_RESULT_V  0x1
+#define SYSTEM_REDUNDANT_ECO_RESULT_S  1
+/* SYSTEM_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_REDUNDANT_ECO_DRIVE  (BIT(0))
+#define SYSTEM_REDUNDANT_ECO_DRIVE_M  (BIT(0))
+#define SYSTEM_REDUNDANT_ECO_DRIVE_V  0x1
+#define SYSTEM_REDUNDANT_ECO_DRIVE_S  0
+
+#define SYSTEM_CLOCK_GATE_REG          (DR_REG_SYSTEM_BASE + 0x054)
+/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_CLK_EN  (BIT(0))
+#define SYSTEM_CLK_EN_M  (BIT(0))
+#define SYSTEM_CLK_EN_V  0x1
+#define SYSTEM_CLK_EN_S  0
+
+#define SYSTEM_SYSCLK_CONF_REG          (DR_REG_SYSTEM_BASE + 0x058)
+/* SYSTEM_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */
+/*description: */
+#define SYSTEM_CLK_DIV_EN  (BIT(19))
+#define SYSTEM_CLK_DIV_EN_M  (BIT(19))
+#define SYSTEM_CLK_DIV_EN_V  0x1
+#define SYSTEM_CLK_DIV_EN_S  19
+/* SYSTEM_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */
+/*description: */
+#define SYSTEM_CLK_XTAL_FREQ  0x0000007F
+#define SYSTEM_CLK_XTAL_FREQ_M  ((SYSTEM_CLK_XTAL_FREQ_V)<<(SYSTEM_CLK_XTAL_FREQ_S))
+#define SYSTEM_CLK_XTAL_FREQ_V  0x7F
+#define SYSTEM_CLK_XTAL_FREQ_S  12
+/* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: */
+#define SYSTEM_SOC_CLK_SEL  0x00000003
+#define SYSTEM_SOC_CLK_SEL_M  ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S))
+#define SYSTEM_SOC_CLK_SEL_V  0x3
+#define SYSTEM_SOC_CLK_SEL_S  10
+/* SYSTEM_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
+/*description: */
+#define SYSTEM_PRE_DIV_CNT  0x000003FF
+#define SYSTEM_PRE_DIV_CNT_M  ((SYSTEM_PRE_DIV_CNT_V)<<(SYSTEM_PRE_DIV_CNT_S))
+#define SYSTEM_PRE_DIV_CNT_V  0x3FF
+#define SYSTEM_PRE_DIV_CNT_S  0
+
+#define SYSTEM_MEM_PVT_REG          (DR_REG_SYSTEM_BASE + 0x05C)
+/* SYSTEM_MEM_VT_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: */
+#define SYSTEM_MEM_VT_SEL  0x00000003
+#define SYSTEM_MEM_VT_SEL_M  ((SYSTEM_MEM_VT_SEL_V)<<(SYSTEM_MEM_VT_SEL_S))
+#define SYSTEM_MEM_VT_SEL_V  0x3
+#define SYSTEM_MEM_VT_SEL_S  22
+/* SYSTEM_MEM_TIMING_ERR_CNT : RO ;bitpos:[21:6] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_MEM_TIMING_ERR_CNT  0x0000FFFF
+#define SYSTEM_MEM_TIMING_ERR_CNT_M  ((SYSTEM_MEM_TIMING_ERR_CNT_V)<<(SYSTEM_MEM_TIMING_ERR_CNT_S))
+#define SYSTEM_MEM_TIMING_ERR_CNT_V  0xFFFF
+#define SYSTEM_MEM_TIMING_ERR_CNT_S  6
+/* SYSTEM_MEM_PVT_MONITOR_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_MEM_PVT_MONITOR_EN  (BIT(5))
+#define SYSTEM_MEM_PVT_MONITOR_EN_M  (BIT(5))
+#define SYSTEM_MEM_PVT_MONITOR_EN_V  0x1
+#define SYSTEM_MEM_PVT_MONITOR_EN_S  5
+/* SYSTEM_MEM_ERR_CNT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_MEM_ERR_CNT_CLR  (BIT(4))
+#define SYSTEM_MEM_ERR_CNT_CLR_M  (BIT(4))
+#define SYSTEM_MEM_ERR_CNT_CLR_V  0x1
+#define SYSTEM_MEM_ERR_CNT_CLR_S  4
+/* SYSTEM_MEM_PATH_LEN : R/W ;bitpos:[3:0] ;default: 4'h3 ; */
+/*description: */
+#define SYSTEM_MEM_PATH_LEN  0x0000000F
+#define SYSTEM_MEM_PATH_LEN_M  ((SYSTEM_MEM_PATH_LEN_V)<<(SYSTEM_MEM_PATH_LEN_S))
+#define SYSTEM_MEM_PATH_LEN_V  0xF
+#define SYSTEM_MEM_PATH_LEN_S  0
+
+#define SYSTEM_COMB_PVT_LVT_CONF_REG          (DR_REG_SYSTEM_BASE + 0x060)
+/* SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_COMB_PVT_MONITOR_EN_LVT  (BIT(6))
+#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_M  (BIT(6))
+#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_V  0x1
+#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_S  6
+/* SYSTEM_COMB_ERR_CNT_CLR_LVT : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_COMB_ERR_CNT_CLR_LVT  (BIT(5))
+#define SYSTEM_COMB_ERR_CNT_CLR_LVT_M  (BIT(5))
+#define SYSTEM_COMB_ERR_CNT_CLR_LVT_V  0x1
+#define SYSTEM_COMB_ERR_CNT_CLR_LVT_S  5
+/* SYSTEM_COMB_PATH_LEN_LVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */
+/*description: */
+#define SYSTEM_COMB_PATH_LEN_LVT  0x0000001F
+#define SYSTEM_COMB_PATH_LEN_LVT_M  ((SYSTEM_COMB_PATH_LEN_LVT_V)<<(SYSTEM_COMB_PATH_LEN_LVT_S))
+#define SYSTEM_COMB_PATH_LEN_LVT_V  0x1F
+#define SYSTEM_COMB_PATH_LEN_LVT_S  0
+
+#define SYSTEM_COMB_PVT_NVT_CONF_REG          (DR_REG_SYSTEM_BASE + 0x064)
+/* SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_COMB_PVT_MONITOR_EN_NVT  (BIT(6))
+#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_M  (BIT(6))
+#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_V  0x1
+#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_S  6
+/* SYSTEM_COMB_ERR_CNT_CLR_NVT : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_COMB_ERR_CNT_CLR_NVT  (BIT(5))
+#define SYSTEM_COMB_ERR_CNT_CLR_NVT_M  (BIT(5))
+#define SYSTEM_COMB_ERR_CNT_CLR_NVT_V  0x1
+#define SYSTEM_COMB_ERR_CNT_CLR_NVT_S  5
+/* SYSTEM_COMB_PATH_LEN_NVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */
+/*description: */
+#define SYSTEM_COMB_PATH_LEN_NVT  0x0000001F
+#define SYSTEM_COMB_PATH_LEN_NVT_M  ((SYSTEM_COMB_PATH_LEN_NVT_V)<<(SYSTEM_COMB_PATH_LEN_NVT_S))
+#define SYSTEM_COMB_PATH_LEN_NVT_V  0x1F
+#define SYSTEM_COMB_PATH_LEN_NVT_S  0
+
+#define SYSTEM_COMB_PVT_HVT_CONF_REG          (DR_REG_SYSTEM_BASE + 0x068)
+/* SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_COMB_PVT_MONITOR_EN_HVT  (BIT(6))
+#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M  (BIT(6))
+#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V  0x1
+#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S  6
+/* SYSTEM_COMB_ERR_CNT_CLR_HVT : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_COMB_ERR_CNT_CLR_HVT  (BIT(5))
+#define SYSTEM_COMB_ERR_CNT_CLR_HVT_M  (BIT(5))
+#define SYSTEM_COMB_ERR_CNT_CLR_HVT_V  0x1
+#define SYSTEM_COMB_ERR_CNT_CLR_HVT_S  5
+/* SYSTEM_COMB_PATH_LEN_HVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */
+/*description: */
+#define SYSTEM_COMB_PATH_LEN_HVT  0x0000001F
+#define SYSTEM_COMB_PATH_LEN_HVT_M  ((SYSTEM_COMB_PATH_LEN_HVT_V)<<(SYSTEM_COMB_PATH_LEN_HVT_S))
+#define SYSTEM_COMB_PATH_LEN_HVT_V  0x1F
+#define SYSTEM_COMB_PATH_LEN_HVT_S  0
+
+#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG          (DR_REG_SYSTEM_BASE + 0x06C)
+/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S  0
+
+#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG          (DR_REG_SYSTEM_BASE + 0x070)
+/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S  0
+
+#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG          (DR_REG_SYSTEM_BASE + 0x074)
+/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S  0
+
+#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG          (DR_REG_SYSTEM_BASE + 0x078)
+/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S  0
+
+#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG          (DR_REG_SYSTEM_BASE + 0x07C)
+/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S  0
+
+#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG          (DR_REG_SYSTEM_BASE + 0x080)
+/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S  0
+
+#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG          (DR_REG_SYSTEM_BASE + 0x084)
+/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S  0
+
+#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG          (DR_REG_SYSTEM_BASE + 0x088)
+/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S  0
+
+#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG          (DR_REG_SYSTEM_BASE + 0x08C)
+/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S  0
+
+#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG          (DR_REG_SYSTEM_BASE + 0x090)
+/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S  0
+
+#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG          (DR_REG_SYSTEM_BASE + 0x094)
+/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S  0
+
+#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG          (DR_REG_SYSTEM_BASE + 0x098)
+/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S  0
+
+#define SYSTEM_DATE_REG          (DR_REG_SYSTEM_BASE + 0xFFC)
+/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007150 ; */
+/*description: */
+#define SYSTEM_DATE  0x0FFFFFFF
+#define SYSTEM_DATE_M  ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S))
+#define SYSTEM_DATE_V  0xFFFFFFF
+#define SYSTEM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SYSTEM_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/system_struct.h b/components/soc/esp32c3/include/soc/system_struct.h
new file mode 100644
index 0000000000..f07fab0aff
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/system_struct.h
@@ -0,0 +1,1412 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SYSTEM_STRUCT_H_
+#define _SOC_SYSTEM_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t reserved0                     :    6;  /*reserved*/
+            uint32_t reg_clk_en_assist_debug       :    1;  /*reg_clk_en_assist_debug*/
+            uint32_t reg_clk_en_dedicated_gpio     :    1;  /*reg_clk_en_dedicated_gpio*/
+            uint32_t reserved8                     :    24;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_peri_clk_en;
+    union {
+        struct {
+            uint32_t reserved0                     :    6;  /*reserved*/
+            uint32_t reg_rst_en_assist_debug       :    1;  /*reg_rst_en_assist_debug*/
+            uint32_t reg_rst_en_dedicated_gpio     :    1;  /*reg_rst_en_dedicated_gpio*/
+            uint32_t reserved8                     :    24;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_peri_rst_en;
+    union {
+        struct {
+            uint32_t reg_cpuperiod_sel             :    2;  /*reg_cpuperiod_sel*/
+            uint32_t reg_pll_freq_sel              :    1;  /*reg_pll_freq_sel*/
+            uint32_t reg_cpu_wait_mode_force_on    :    1;  /*reg_cpu_wait_mode_force_on*/
+            uint32_t reg_cpu_waiti_delay_num       :    4;  /*reg_cpu_waiti_delay_num*/
+            uint32_t reserved8                     :    24;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_per_conf;
+    union {
+        struct {
+            uint32_t reg_lslp_mem_pd_mask          :    1;  /*reg_lslp_mem_pd_mask*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } mem_pd_mask;
+    union {
+        struct {
+            uint32_t reg_timers_clk_en             :    1;  /*reg_timers_clk_en*/
+            uint32_t reg_spi01_clk_en              :    1;  /*reg_spi01_clk_en*/
+            uint32_t reg_uart_clk_en               :    1;  /*reg_uart_clk_en*/
+            uint32_t reg_wdg_clk_en                :    1;  /*reg_wdg_clk_en*/
+            uint32_t reg_i2s0_clk_en               :    1;  /*reg_i2s0_clk_en*/
+            uint32_t reg_uart1_clk_en              :    1;  /*reg_uart1_clk_en*/
+            uint32_t reg_spi2_clk_en               :    1;  /*reg_spi2_clk_en*/
+            uint32_t reg_i2c_ext0_clk_en           :    1;  /*reg_i2c_ext0_clk_en*/
+            uint32_t reg_uhci0_clk_en              :    1;  /*reg_uhci0_clk_en*/
+            uint32_t reg_rmt_clk_en                :    1;  /*reg_rmt_clk_en*/
+            uint32_t reg_pcnt_clk_en               :    1;  /*reg_pcnt_clk_en*/
+            uint32_t reg_ledc_clk_en               :    1;  /*reg_ledc_clk_en*/
+            uint32_t reg_uhci1_clk_en              :    1;  /*reg_uhci1_clk_en*/
+            uint32_t reg_timergroup_clk_en         :    1;  /*reg_timergroup_clk_en*/
+            uint32_t reg_efuse_clk_en              :    1;  /*reg_efuse_clk_en*/
+            uint32_t reg_timergroup1_clk_en        :    1;  /*reg_timergroup1_clk_en*/
+            uint32_t reg_spi3_clk_en               :    1;  /*reg_spi3_clk_en*/
+            uint32_t reg_pwm0_clk_en               :    1;  /*reg_pwm0_clk_en*/
+            uint32_t reg_i2c_ext1_clk_en           :    1;  /*reg_i2c_ext1_clk_en*/
+            uint32_t reg_can_clk_en                :    1;  /*reg_can_clk_en*/
+            uint32_t reg_pwm1_clk_en               :    1;  /*reg_pwm1_clk_en*/
+            uint32_t reg_i2s1_clk_en               :    1;  /*reg_i2s1_clk_en*/
+            uint32_t reg_spi2_dma_clk_en           :    1;  /*reg_spi2_dma_clk_en*/
+            uint32_t reg_usb_device_clk_en         :    1;  /*reg_usb_device_clk_en*/
+            uint32_t reg_uart_mem_clk_en           :    1;  /*reg_uart_mem_clk_en*/
+            uint32_t reg_pwm2_clk_en               :    1;  /*reg_pwm2_clk_en*/
+            uint32_t reg_pwm3_clk_en               :    1;  /*reg_pwm3_clk_en*/
+            uint32_t reg_spi3_dma_clk_en           :    1;  /*reg_spi3_dma_clk_en*/
+            uint32_t reg_apb_saradc_clk_en         :    1;  /*reg_apb_saradc_clk_en*/
+            uint32_t reg_systimer_clk_en           :    1;  /*reg_systimer_clk_en*/
+            uint32_t reg_adc2_arb_clk_en           :    1;  /*reg_adc2_arb_clk_en*/
+            uint32_t reg_spi4_clk_en               :    1;  /*reg_spi4_clk_en*/
+        };
+        uint32_t val;
+    } perip_clk_en0;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;  /*peripheral reset register*/
+            uint32_t reg_crypto_aes_clk_en         :    1;  /*reg_crypto_aes_clk_en*/
+            uint32_t reg_crypto_sha_clk_en         :    1;  /*reg_crypto_sha_clk_en*/
+            uint32_t reg_crypto_rsa_clk_en         :    1;  /*reg_crypto_rsa_clk_en*/
+            uint32_t reg_crypto_ds_clk_en          :    1;  /*reg_crypto_ds_clk_en*/
+            uint32_t reg_crypto_hmac_clk_en        :    1;  /*reg_crypto_hmac_clk_en*/
+            uint32_t reg_dma_clk_en                :    1;  /*reg_dma_clk_en*/
+            uint32_t reg_sdio_host_clk_en          :    1;  /*reg_sdio_host_clk_en*/
+            uint32_t reg_lcd_cam_clk_en            :    1;  /*reg_lcd_cam_clk_en*/
+            uint32_t reg_uart2_clk_en              :    1;  /*reg_uart2_clk_en*/
+            uint32_t reg_tsens_clk_en              :    1;  /*reg_tsens_clk_en*/
+            uint32_t reserved11                    :    21;  /*reserved*/
+        };
+        uint32_t val;
+    } perip_clk_en1;
+    union {
+        struct {
+            uint32_t reg_timers_rst                :    1;  /*reg_timers_rst*/
+            uint32_t reg_spi01_rst                 :    1;  /*reg_spi01_rst*/
+            uint32_t reg_uart_rst                  :    1;  /*reg_uart_rst*/
+            uint32_t reg_wdg_rst                   :    1;  /*reg_wdg_rst*/
+            uint32_t reg_i2s0_rst                  :    1;  /*reg_i2s0_rst*/
+            uint32_t reg_uart1_rst                 :    1;  /*reg_uart1_rst*/
+            uint32_t reg_spi2_rst                  :    1;  /*reg_spi2_rst*/
+            uint32_t reg_i2c_ext0_rst              :    1;  /*reg_i2c_ext0_rst*/
+            uint32_t reg_uhci0_rst                 :    1;  /*reg_uhci0_rst*/
+            uint32_t reg_rmt_rst                   :    1;  /*reg_rmt_rst*/
+            uint32_t reg_pcnt_rst                  :    1;  /*reg_pcnt_rst*/
+            uint32_t reg_ledc_rst                  :    1;  /*reg_ledc_rst*/
+            uint32_t reg_uhci1_rst                 :    1;  /*reg_uhci1_rst*/
+            uint32_t reg_timergroup_rst            :    1;  /*reg_timergroup_rst*/
+            uint32_t reg_efuse_rst                 :    1;  /*reg_efuse_rst*/
+            uint32_t reg_timergroup1_rst           :    1;  /*reg_timergroup1_rst*/
+            uint32_t reg_spi3_rst                  :    1;  /*reg_spi3_rst*/
+            uint32_t reg_pwm0_rst                  :    1;  /*reg_pwm0_rst*/
+            uint32_t reg_i2c_ext1_rst              :    1;  /*reg_i2c_ext1_rst*/
+            uint32_t reg_can_rst                   :    1;  /*reg_can_rst*/
+            uint32_t reg_pwm1_rst                  :    1;  /*reg_pwm1_rst*/
+            uint32_t reg_i2s1_rst                  :    1;  /*reg_i2s1_rst*/
+            uint32_t reg_spi2_dma_rst              :    1;  /*reg_spi2_dma_rst*/
+            uint32_t reg_usb_device_rst            :    1;  /*reg_usb_device_rst*/
+            uint32_t reg_uart_mem_rst              :    1;  /*reg_uart_mem_rst*/
+            uint32_t reg_pwm2_rst                  :    1;  /*reg_pwm2_rst*/
+            uint32_t reg_pwm3_rst                  :    1;  /*reg_pwm3_rst*/
+            uint32_t reg_spi3_dma_rst              :    1;  /*reg_spi3_dma_rst*/
+            uint32_t reg_apb_saradc_rst            :    1;  /*reg_apb_saradc_rst*/
+            uint32_t reg_systimer_rst              :    1;  /*reg_systimer_rst*/
+            uint32_t reg_adc2_arb_rst              :    1;  /*reg_adc2_arb_rst*/
+            uint32_t reg_spi4_rst                  :    1;  /*reg_spi4_rst*/
+        };
+        uint32_t val;
+    } perip_rst_en0;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;  /*reserved*/
+            uint32_t reg_crypto_aes_rst            :    1;  /*reg_crypto_aes_rst*/
+            uint32_t reg_crypto_sha_rst            :    1;  /*reg_crypto_sha_rst*/
+            uint32_t reg_crypto_rsa_rst            :    1;  /*reg_crypto_rsa_rst*/
+            uint32_t reg_crypto_ds_rst             :    1;  /*reg_crypto_ds_rst*/
+            uint32_t reg_crypto_hmac_rst           :    1;  /*reg_crypto_hmac_rst*/
+            uint32_t reg_dma_rst                   :    1;  /*reg_dma_rst*/
+            uint32_t reg_sdio_host_rst             :    1;  /*reg_sdio_host_rst*/
+            uint32_t reg_lcd_cam_rst               :    1;  /*reg_lcd_cam_rst*/
+            uint32_t reg_uart2_rst                 :    1;  /*reg_uart2_rst*/
+            uint32_t reg_tsens_rst                 :    1;  /*reg_tsens_rst*/
+            uint32_t reserved11                    :    21;  /*reserved*/
+        };
+        uint32_t val;
+    } perip_rst_en1;
+    union {
+        struct {
+            uint32_t reg_bt_lpck_div_num           :    12;  /*reg_bt_lpck_div_num*/
+            uint32_t reserved12                    :    20;  /*reserved*/
+        };
+        uint32_t val;
+    } bt_lpck_div_int;
+    union {
+        struct {
+            uint32_t reg_bt_lpck_div_b             :    12;  /*reg_bt_lpck_div_b*/
+            uint32_t reg_bt_lpck_div_a             :    12;  /*reg_bt_lpck_div_a*/
+            uint32_t reg_lpclk_sel_rtc_slow        :    1;  /*reg_lpclk_sel_rtc_slow*/
+            uint32_t reg_lpclk_sel_8m              :    1;  /*reg_lpclk_sel_8m*/
+            uint32_t reg_lpclk_sel_xtal            :    1;  /*reg_lpclk_sel_xtal*/
+            uint32_t reg_lpclk_sel_xtal32k         :    1;  /*reg_lpclk_sel_xtal32k*/
+            uint32_t reg_lpclk_rtc_en              :    1;  /*reg_lpclk_rtc_en*/
+            uint32_t reserved29                    :    3;  /*reserved*/
+        };
+        uint32_t val;
+    } bt_lpck_div_frac;
+    union {
+        struct {
+            uint32_t reg_cpu_intr_from_cpu_0       :    1;  /*reg_cpu_intr_from_cpu_0*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_intr_from_cpu_0;
+    union {
+        struct {
+            uint32_t reg_cpu_intr_from_cpu_1       :    1;  /*reg_cpu_intr_from_cpu_1*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_intr_from_cpu_1;
+    union {
+        struct {
+            uint32_t reg_cpu_intr_from_cpu_2       :    1;  /*reg_cpu_intr_from_cpu_2*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_intr_from_cpu_2;
+    union {
+        struct {
+            uint32_t reg_cpu_intr_from_cpu_3       :    1;  /*reg_cpu_intr_from_cpu_3*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_intr_from_cpu_3;
+    union {
+        struct {
+            uint32_t reg_rsa_mem_pd                :    1;  /*reg_rsa_mem_pd*/
+            uint32_t reg_rsa_mem_force_pu          :    1;  /*reg_rsa_mem_force_pu*/
+            uint32_t reg_rsa_mem_force_pd          :    1;  /*reg_rsa_mem_force_pd*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } rsa_pd_ctrl;
+    union {
+        struct {
+            uint32_t reg_edma_clk_on               :    1;  /*reg_edma_clk_on*/
+            uint32_t reg_edma_reset                :    1;  /*reg_edma_reset*/
+            uint32_t reserved2                     :    30;  /*reserved*/
+        };
+        uint32_t val;
+    } edma_ctrl;
+    union {
+        struct {
+            uint32_t reg_icache_clk_on             :    1;  /*reg_icache_clk_on*/
+            uint32_t reg_icache_reset              :    1;  /*reg_icache_reset*/
+            uint32_t reg_dcache_clk_on             :    1;  /*reg_dcache_clk_on*/
+            uint32_t reg_dcache_reset              :    1;  /*reg_dcache_reset*/
+            uint32_t reserved4                     :    28;  /*reserved*/
+        };
+        uint32_t val;
+    } cache_control;
+    union {
+        struct {
+            uint32_t reg_enable_spi_manual_encrypt :    1;  /*reg_enable_spi_manual_encrypt*/
+            uint32_t reg_enable_download_db_encrypt:    1;  /*reg_enable_download_db_encrypt*/
+            uint32_t reg_enable_download_g0cb_decrypt:    1;  /*reg_enable_download_g0cb_decrypt*/
+            uint32_t reg_enable_download_manual_encrypt:    1;  /*reg_enable_download_manual_encrypt*/
+            uint32_t reserved4                     :    28;  /*reserved*/
+        };
+        uint32_t val;
+    } external_device_encrypt_decrypt_control;
+    union {
+        struct {
+            uint32_t reserved0                     :    8;  /*fast memory crc register*/
+            uint32_t reg_rtc_mem_crc_start         :    1;  /*reg_rtc_mem_crc_start*/
+            uint32_t reg_rtc_mem_crc_addr          :    11;  /*reg_rtc_mem_crc_addr*/
+            uint32_t reg_rtc_mem_crc_len           :    11;  /*reg_rtc_mem_crc_len*/
+            uint32_t reg_rtc_mem_crc_finish        :    1;  /*reg_rtc_mem_crc_finish*/
+        };
+        uint32_t val;
+    } rtc_fastmem_config;
+    uint32_t rtc_fastmem_crc;
+    union {
+        struct {
+            uint32_t reg_redundant_eco_drive       :    1;  /*reg_redundant_eco_drive*/
+            uint32_t reg_redundant_eco_result      :    1;  /*reg_redundant_eco_result*/
+            uint32_t reserved2                     :    30;  /*reserved*/
+        };
+        uint32_t val;
+    } redundant_eco_ctrl;
+    union {
+        struct {
+            uint32_t reg_clk_en                    :    1;  /*reg_clk_en*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } clock_gate;
+    union {
+        struct {
+            uint32_t reg_pre_div_cnt               :    10;  /*reg_pre_div_cnt*/
+            uint32_t reg_soc_clk_sel               :    2;  /*reg_soc_clk_sel*/
+            uint32_t reg_clk_xtal_freq             :    7;  /*reg_clk_xtal_freq*/
+            uint32_t reg_clk_div_en                :    1;  /*reg_clk_div_en*/
+            uint32_t reserved20                    :    12;  /*reserved*/
+        };
+        uint32_t val;
+    } sysclk_conf;
+    union {
+        struct {
+            uint32_t reg_mem_path_len              :    4;  /*reg_mem_path_len*/
+            uint32_t reg_mem_err_cnt_clr           :    1;  /*reg_mem_err_cnt_clr*/
+            uint32_t reg_mem_pvt_monitor_en        :    1;  /*reg_mem_pvt_monitor_en*/
+            uint32_t reg_mem_timing_err_cnt        :    16;  /*reg_mem_timing_err_cnt*/
+            uint32_t reg_mem_vt_sel                :    2;  /*reg_mem_vt_sel*/
+            uint32_t reserved24                    :    8;  /*reserved*/
+        };
+        uint32_t val;
+    } mem_pvt;
+    union {
+        struct {
+            uint32_t reg_comb_path_len_lvt         :    5;  /*reg_comb_path_len_lvt*/
+            uint32_t reg_comb_err_cnt_clr_lvt      :    1;  /*reg_comb_err_cnt_clr_lvt*/
+            uint32_t reg_comb_pvt_monitor_en_lvt   :    1;  /*reg_comb_pvt_monitor_en_lvt*/
+            uint32_t reserved7                     :    18;  /*reserved*/
+            uint32_t reserved25                    :    7;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_lvt_conf;
+    union {
+        struct {
+            uint32_t reg_comb_path_len_nvt         :    5;  /*reg_comb_path_len_nvt*/
+            uint32_t reg_comb_err_cnt_clr_nvt      :    1;  /*reg_comb_err_cnt_clr_nvt*/
+            uint32_t reg_comb_pvt_monitor_en_nvt   :    1;  /*reg_comb_pvt_monitor_en_nvt*/
+            uint32_t reserved7                     :    18;  /*reserved*/
+            uint32_t reserved25                    :    7;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_nvt_conf;
+    union {
+        struct {
+            uint32_t reg_comb_path_len_hvt         :    5;  /*reg_comb_path_len_hvt*/
+            uint32_t reg_comb_err_cnt_clr_hvt      :    1;  /*reg_comb_err_cnt_clr_hvt*/
+            uint32_t reg_comb_pvt_monitor_en_hvt   :    1;  /*reg_comb_pvt_monitor_en_hvt*/
+            uint32_t reserved7                     :    18;  /*reserved*/
+            uint32_t reserved25                    :    7;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_hvt_conf;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_lvt_site0:    16;  /*reg_comb_timing_err_cnt_lvt_site0*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_lvt_site0;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_nvt_site0:    16;  /*reg_comb_timing_err_cnt_nvt_site0*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_nvt_site0;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_hvt_site0:    16;  /*reg_comb_timing_err_cnt_hvt_site0*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_hvt_site0;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_lvt_site1:    16;  /*reg_comb_timing_err_cnt_lvt_site1*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_lvt_site1;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_nvt_site1:    16;  /*reg_comb_timing_err_cnt_nvt_site1*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_nvt_site1;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_hvt_site1:    16;  /*reg_comb_timing_err_cnt_hvt_site1*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_hvt_site1;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_lvt_site2:    16;  /*reg_comb_timing_err_cnt_lvt_site2*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_lvt_site2;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_nvt_site2:    16;  /*reg_comb_timing_err_cnt_nvt_site2*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_nvt_site2;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_hvt_site2:    16;  /*reg_comb_timing_err_cnt_hvt_site2*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_hvt_site2;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_lvt_site3:    16;  /*reg_comb_timing_err_cnt_lvt_site3*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_lvt_site3;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_nvt_site3:    16;  /*reg_comb_timing_err_cnt_nvt_site3*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_nvt_site3;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_hvt_site3:    16;  /*reg_comb_timing_err_cnt_hvt_site3*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_hvt_site3;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    uint32_t reserved_3fc;
+    uint32_t reserved_400;
+    uint32_t reserved_404;
+    uint32_t reserved_408;
+    uint32_t reserved_40c;
+    uint32_t reserved_410;
+    uint32_t reserved_414;
+    uint32_t reserved_418;
+    uint32_t reserved_41c;
+    uint32_t reserved_420;
+    uint32_t reserved_424;
+    uint32_t reserved_428;
+    uint32_t reserved_42c;
+    uint32_t reserved_430;
+    uint32_t reserved_434;
+    uint32_t reserved_438;
+    uint32_t reserved_43c;
+    uint32_t reserved_440;
+    uint32_t reserved_444;
+    uint32_t reserved_448;
+    uint32_t reserved_44c;
+    uint32_t reserved_450;
+    uint32_t reserved_454;
+    uint32_t reserved_458;
+    uint32_t reserved_45c;
+    uint32_t reserved_460;
+    uint32_t reserved_464;
+    uint32_t reserved_468;
+    uint32_t reserved_46c;
+    uint32_t reserved_470;
+    uint32_t reserved_474;
+    uint32_t reserved_478;
+    uint32_t reserved_47c;
+    uint32_t reserved_480;
+    uint32_t reserved_484;
+    uint32_t reserved_488;
+    uint32_t reserved_48c;
+    uint32_t reserved_490;
+    uint32_t reserved_494;
+    uint32_t reserved_498;
+    uint32_t reserved_49c;
+    uint32_t reserved_4a0;
+    uint32_t reserved_4a4;
+    uint32_t reserved_4a8;
+    uint32_t reserved_4ac;
+    uint32_t reserved_4b0;
+    uint32_t reserved_4b4;
+    uint32_t reserved_4b8;
+    uint32_t reserved_4bc;
+    uint32_t reserved_4c0;
+    uint32_t reserved_4c4;
+    uint32_t reserved_4c8;
+    uint32_t reserved_4cc;
+    uint32_t reserved_4d0;
+    uint32_t reserved_4d4;
+    uint32_t reserved_4d8;
+    uint32_t reserved_4dc;
+    uint32_t reserved_4e0;
+    uint32_t reserved_4e4;
+    uint32_t reserved_4e8;
+    uint32_t reserved_4ec;
+    uint32_t reserved_4f0;
+    uint32_t reserved_4f4;
+    uint32_t reserved_4f8;
+    uint32_t reserved_4fc;
+    uint32_t reserved_500;
+    uint32_t reserved_504;
+    uint32_t reserved_508;
+    uint32_t reserved_50c;
+    uint32_t reserved_510;
+    uint32_t reserved_514;
+    uint32_t reserved_518;
+    uint32_t reserved_51c;
+    uint32_t reserved_520;
+    uint32_t reserved_524;
+    uint32_t reserved_528;
+    uint32_t reserved_52c;
+    uint32_t reserved_530;
+    uint32_t reserved_534;
+    uint32_t reserved_538;
+    uint32_t reserved_53c;
+    uint32_t reserved_540;
+    uint32_t reserved_544;
+    uint32_t reserved_548;
+    uint32_t reserved_54c;
+    uint32_t reserved_550;
+    uint32_t reserved_554;
+    uint32_t reserved_558;
+    uint32_t reserved_55c;
+    uint32_t reserved_560;
+    uint32_t reserved_564;
+    uint32_t reserved_568;
+    uint32_t reserved_56c;
+    uint32_t reserved_570;
+    uint32_t reserved_574;
+    uint32_t reserved_578;
+    uint32_t reserved_57c;
+    uint32_t reserved_580;
+    uint32_t reserved_584;
+    uint32_t reserved_588;
+    uint32_t reserved_58c;
+    uint32_t reserved_590;
+    uint32_t reserved_594;
+    uint32_t reserved_598;
+    uint32_t reserved_59c;
+    uint32_t reserved_5a0;
+    uint32_t reserved_5a4;
+    uint32_t reserved_5a8;
+    uint32_t reserved_5ac;
+    uint32_t reserved_5b0;
+    uint32_t reserved_5b4;
+    uint32_t reserved_5b8;
+    uint32_t reserved_5bc;
+    uint32_t reserved_5c0;
+    uint32_t reserved_5c4;
+    uint32_t reserved_5c8;
+    uint32_t reserved_5cc;
+    uint32_t reserved_5d0;
+    uint32_t reserved_5d4;
+    uint32_t reserved_5d8;
+    uint32_t reserved_5dc;
+    uint32_t reserved_5e0;
+    uint32_t reserved_5e4;
+    uint32_t reserved_5e8;
+    uint32_t reserved_5ec;
+    uint32_t reserved_5f0;
+    uint32_t reserved_5f4;
+    uint32_t reserved_5f8;
+    uint32_t reserved_5fc;
+    uint32_t reserved_600;
+    uint32_t reserved_604;
+    uint32_t reserved_608;
+    uint32_t reserved_60c;
+    uint32_t reserved_610;
+    uint32_t reserved_614;
+    uint32_t reserved_618;
+    uint32_t reserved_61c;
+    uint32_t reserved_620;
+    uint32_t reserved_624;
+    uint32_t reserved_628;
+    uint32_t reserved_62c;
+    uint32_t reserved_630;
+    uint32_t reserved_634;
+    uint32_t reserved_638;
+    uint32_t reserved_63c;
+    uint32_t reserved_640;
+    uint32_t reserved_644;
+    uint32_t reserved_648;
+    uint32_t reserved_64c;
+    uint32_t reserved_650;
+    uint32_t reserved_654;
+    uint32_t reserved_658;
+    uint32_t reserved_65c;
+    uint32_t reserved_660;
+    uint32_t reserved_664;
+    uint32_t reserved_668;
+    uint32_t reserved_66c;
+    uint32_t reserved_670;
+    uint32_t reserved_674;
+    uint32_t reserved_678;
+    uint32_t reserved_67c;
+    uint32_t reserved_680;
+    uint32_t reserved_684;
+    uint32_t reserved_688;
+    uint32_t reserved_68c;
+    uint32_t reserved_690;
+    uint32_t reserved_694;
+    uint32_t reserved_698;
+    uint32_t reserved_69c;
+    uint32_t reserved_6a0;
+    uint32_t reserved_6a4;
+    uint32_t reserved_6a8;
+    uint32_t reserved_6ac;
+    uint32_t reserved_6b0;
+    uint32_t reserved_6b4;
+    uint32_t reserved_6b8;
+    uint32_t reserved_6bc;
+    uint32_t reserved_6c0;
+    uint32_t reserved_6c4;
+    uint32_t reserved_6c8;
+    uint32_t reserved_6cc;
+    uint32_t reserved_6d0;
+    uint32_t reserved_6d4;
+    uint32_t reserved_6d8;
+    uint32_t reserved_6dc;
+    uint32_t reserved_6e0;
+    uint32_t reserved_6e4;
+    uint32_t reserved_6e8;
+    uint32_t reserved_6ec;
+    uint32_t reserved_6f0;
+    uint32_t reserved_6f4;
+    uint32_t reserved_6f8;
+    uint32_t reserved_6fc;
+    uint32_t reserved_700;
+    uint32_t reserved_704;
+    uint32_t reserved_708;
+    uint32_t reserved_70c;
+    uint32_t reserved_710;
+    uint32_t reserved_714;
+    uint32_t reserved_718;
+    uint32_t reserved_71c;
+    uint32_t reserved_720;
+    uint32_t reserved_724;
+    uint32_t reserved_728;
+    uint32_t reserved_72c;
+    uint32_t reserved_730;
+    uint32_t reserved_734;
+    uint32_t reserved_738;
+    uint32_t reserved_73c;
+    uint32_t reserved_740;
+    uint32_t reserved_744;
+    uint32_t reserved_748;
+    uint32_t reserved_74c;
+    uint32_t reserved_750;
+    uint32_t reserved_754;
+    uint32_t reserved_758;
+    uint32_t reserved_75c;
+    uint32_t reserved_760;
+    uint32_t reserved_764;
+    uint32_t reserved_768;
+    uint32_t reserved_76c;
+    uint32_t reserved_770;
+    uint32_t reserved_774;
+    uint32_t reserved_778;
+    uint32_t reserved_77c;
+    uint32_t reserved_780;
+    uint32_t reserved_784;
+    uint32_t reserved_788;
+    uint32_t reserved_78c;
+    uint32_t reserved_790;
+    uint32_t reserved_794;
+    uint32_t reserved_798;
+    uint32_t reserved_79c;
+    uint32_t reserved_7a0;
+    uint32_t reserved_7a4;
+    uint32_t reserved_7a8;
+    uint32_t reserved_7ac;
+    uint32_t reserved_7b0;
+    uint32_t reserved_7b4;
+    uint32_t reserved_7b8;
+    uint32_t reserved_7bc;
+    uint32_t reserved_7c0;
+    uint32_t reserved_7c4;
+    uint32_t reserved_7c8;
+    uint32_t reserved_7cc;
+    uint32_t reserved_7d0;
+    uint32_t reserved_7d4;
+    uint32_t reserved_7d8;
+    uint32_t reserved_7dc;
+    uint32_t reserved_7e0;
+    uint32_t reserved_7e4;
+    uint32_t reserved_7e8;
+    uint32_t reserved_7ec;
+    uint32_t reserved_7f0;
+    uint32_t reserved_7f4;
+    uint32_t reserved_7f8;
+    uint32_t reserved_7fc;
+    uint32_t reserved_800;
+    uint32_t reserved_804;
+    uint32_t reserved_808;
+    uint32_t reserved_80c;
+    uint32_t reserved_810;
+    uint32_t reserved_814;
+    uint32_t reserved_818;
+    uint32_t reserved_81c;
+    uint32_t reserved_820;
+    uint32_t reserved_824;
+    uint32_t reserved_828;
+    uint32_t reserved_82c;
+    uint32_t reserved_830;
+    uint32_t reserved_834;
+    uint32_t reserved_838;
+    uint32_t reserved_83c;
+    uint32_t reserved_840;
+    uint32_t reserved_844;
+    uint32_t reserved_848;
+    uint32_t reserved_84c;
+    uint32_t reserved_850;
+    uint32_t reserved_854;
+    uint32_t reserved_858;
+    uint32_t reserved_85c;
+    uint32_t reserved_860;
+    uint32_t reserved_864;
+    uint32_t reserved_868;
+    uint32_t reserved_86c;
+    uint32_t reserved_870;
+    uint32_t reserved_874;
+    uint32_t reserved_878;
+    uint32_t reserved_87c;
+    uint32_t reserved_880;
+    uint32_t reserved_884;
+    uint32_t reserved_888;
+    uint32_t reserved_88c;
+    uint32_t reserved_890;
+    uint32_t reserved_894;
+    uint32_t reserved_898;
+    uint32_t reserved_89c;
+    uint32_t reserved_8a0;
+    uint32_t reserved_8a4;
+    uint32_t reserved_8a8;
+    uint32_t reserved_8ac;
+    uint32_t reserved_8b0;
+    uint32_t reserved_8b4;
+    uint32_t reserved_8b8;
+    uint32_t reserved_8bc;
+    uint32_t reserved_8c0;
+    uint32_t reserved_8c4;
+    uint32_t reserved_8c8;
+    uint32_t reserved_8cc;
+    uint32_t reserved_8d0;
+    uint32_t reserved_8d4;
+    uint32_t reserved_8d8;
+    uint32_t reserved_8dc;
+    uint32_t reserved_8e0;
+    uint32_t reserved_8e4;
+    uint32_t reserved_8e8;
+    uint32_t reserved_8ec;
+    uint32_t reserved_8f0;
+    uint32_t reserved_8f4;
+    uint32_t reserved_8f8;
+    uint32_t reserved_8fc;
+    uint32_t reserved_900;
+    uint32_t reserved_904;
+    uint32_t reserved_908;
+    uint32_t reserved_90c;
+    uint32_t reserved_910;
+    uint32_t reserved_914;
+    uint32_t reserved_918;
+    uint32_t reserved_91c;
+    uint32_t reserved_920;
+    uint32_t reserved_924;
+    uint32_t reserved_928;
+    uint32_t reserved_92c;
+    uint32_t reserved_930;
+    uint32_t reserved_934;
+    uint32_t reserved_938;
+    uint32_t reserved_93c;
+    uint32_t reserved_940;
+    uint32_t reserved_944;
+    uint32_t reserved_948;
+    uint32_t reserved_94c;
+    uint32_t reserved_950;
+    uint32_t reserved_954;
+    uint32_t reserved_958;
+    uint32_t reserved_95c;
+    uint32_t reserved_960;
+    uint32_t reserved_964;
+    uint32_t reserved_968;
+    uint32_t reserved_96c;
+    uint32_t reserved_970;
+    uint32_t reserved_974;
+    uint32_t reserved_978;
+    uint32_t reserved_97c;
+    uint32_t reserved_980;
+    uint32_t reserved_984;
+    uint32_t reserved_988;
+    uint32_t reserved_98c;
+    uint32_t reserved_990;
+    uint32_t reserved_994;
+    uint32_t reserved_998;
+    uint32_t reserved_99c;
+    uint32_t reserved_9a0;
+    uint32_t reserved_9a4;
+    uint32_t reserved_9a8;
+    uint32_t reserved_9ac;
+    uint32_t reserved_9b0;
+    uint32_t reserved_9b4;
+    uint32_t reserved_9b8;
+    uint32_t reserved_9bc;
+    uint32_t reserved_9c0;
+    uint32_t reserved_9c4;
+    uint32_t reserved_9c8;
+    uint32_t reserved_9cc;
+    uint32_t reserved_9d0;
+    uint32_t reserved_9d4;
+    uint32_t reserved_9d8;
+    uint32_t reserved_9dc;
+    uint32_t reserved_9e0;
+    uint32_t reserved_9e4;
+    uint32_t reserved_9e8;
+    uint32_t reserved_9ec;
+    uint32_t reserved_9f0;
+    uint32_t reserved_9f4;
+    uint32_t reserved_9f8;
+    uint32_t reserved_9fc;
+    uint32_t reserved_a00;
+    uint32_t reserved_a04;
+    uint32_t reserved_a08;
+    uint32_t reserved_a0c;
+    uint32_t reserved_a10;
+    uint32_t reserved_a14;
+    uint32_t reserved_a18;
+    uint32_t reserved_a1c;
+    uint32_t reserved_a20;
+    uint32_t reserved_a24;
+    uint32_t reserved_a28;
+    uint32_t reserved_a2c;
+    uint32_t reserved_a30;
+    uint32_t reserved_a34;
+    uint32_t reserved_a38;
+    uint32_t reserved_a3c;
+    uint32_t reserved_a40;
+    uint32_t reserved_a44;
+    uint32_t reserved_a48;
+    uint32_t reserved_a4c;
+    uint32_t reserved_a50;
+    uint32_t reserved_a54;
+    uint32_t reserved_a58;
+    uint32_t reserved_a5c;
+    uint32_t reserved_a60;
+    uint32_t reserved_a64;
+    uint32_t reserved_a68;
+    uint32_t reserved_a6c;
+    uint32_t reserved_a70;
+    uint32_t reserved_a74;
+    uint32_t reserved_a78;
+    uint32_t reserved_a7c;
+    uint32_t reserved_a80;
+    uint32_t reserved_a84;
+    uint32_t reserved_a88;
+    uint32_t reserved_a8c;
+    uint32_t reserved_a90;
+    uint32_t reserved_a94;
+    uint32_t reserved_a98;
+    uint32_t reserved_a9c;
+    uint32_t reserved_aa0;
+    uint32_t reserved_aa4;
+    uint32_t reserved_aa8;
+    uint32_t reserved_aac;
+    uint32_t reserved_ab0;
+    uint32_t reserved_ab4;
+    uint32_t reserved_ab8;
+    uint32_t reserved_abc;
+    uint32_t reserved_ac0;
+    uint32_t reserved_ac4;
+    uint32_t reserved_ac8;
+    uint32_t reserved_acc;
+    uint32_t reserved_ad0;
+    uint32_t reserved_ad4;
+    uint32_t reserved_ad8;
+    uint32_t reserved_adc;
+    uint32_t reserved_ae0;
+    uint32_t reserved_ae4;
+    uint32_t reserved_ae8;
+    uint32_t reserved_aec;
+    uint32_t reserved_af0;
+    uint32_t reserved_af4;
+    uint32_t reserved_af8;
+    uint32_t reserved_afc;
+    uint32_t reserved_b00;
+    uint32_t reserved_b04;
+    uint32_t reserved_b08;
+    uint32_t reserved_b0c;
+    uint32_t reserved_b10;
+    uint32_t reserved_b14;
+    uint32_t reserved_b18;
+    uint32_t reserved_b1c;
+    uint32_t reserved_b20;
+    uint32_t reserved_b24;
+    uint32_t reserved_b28;
+    uint32_t reserved_b2c;
+    uint32_t reserved_b30;
+    uint32_t reserved_b34;
+    uint32_t reserved_b38;
+    uint32_t reserved_b3c;
+    uint32_t reserved_b40;
+    uint32_t reserved_b44;
+    uint32_t reserved_b48;
+    uint32_t reserved_b4c;
+    uint32_t reserved_b50;
+    uint32_t reserved_b54;
+    uint32_t reserved_b58;
+    uint32_t reserved_b5c;
+    uint32_t reserved_b60;
+    uint32_t reserved_b64;
+    uint32_t reserved_b68;
+    uint32_t reserved_b6c;
+    uint32_t reserved_b70;
+    uint32_t reserved_b74;
+    uint32_t reserved_b78;
+    uint32_t reserved_b7c;
+    uint32_t reserved_b80;
+    uint32_t reserved_b84;
+    uint32_t reserved_b88;
+    uint32_t reserved_b8c;
+    uint32_t reserved_b90;
+    uint32_t reserved_b94;
+    uint32_t reserved_b98;
+    uint32_t reserved_b9c;
+    uint32_t reserved_ba0;
+    uint32_t reserved_ba4;
+    uint32_t reserved_ba8;
+    uint32_t reserved_bac;
+    uint32_t reserved_bb0;
+    uint32_t reserved_bb4;
+    uint32_t reserved_bb8;
+    uint32_t reserved_bbc;
+    uint32_t reserved_bc0;
+    uint32_t reserved_bc4;
+    uint32_t reserved_bc8;
+    uint32_t reserved_bcc;
+    uint32_t reserved_bd0;
+    uint32_t reserved_bd4;
+    uint32_t reserved_bd8;
+    uint32_t reserved_bdc;
+    uint32_t reserved_be0;
+    uint32_t reserved_be4;
+    uint32_t reserved_be8;
+    uint32_t reserved_bec;
+    uint32_t reserved_bf0;
+    uint32_t reserved_bf4;
+    uint32_t reserved_bf8;
+    uint32_t reserved_bfc;
+    uint32_t reserved_c00;
+    uint32_t reserved_c04;
+    uint32_t reserved_c08;
+    uint32_t reserved_c0c;
+    uint32_t reserved_c10;
+    uint32_t reserved_c14;
+    uint32_t reserved_c18;
+    uint32_t reserved_c1c;
+    uint32_t reserved_c20;
+    uint32_t reserved_c24;
+    uint32_t reserved_c28;
+    uint32_t reserved_c2c;
+    uint32_t reserved_c30;
+    uint32_t reserved_c34;
+    uint32_t reserved_c38;
+    uint32_t reserved_c3c;
+    uint32_t reserved_c40;
+    uint32_t reserved_c44;
+    uint32_t reserved_c48;
+    uint32_t reserved_c4c;
+    uint32_t reserved_c50;
+    uint32_t reserved_c54;
+    uint32_t reserved_c58;
+    uint32_t reserved_c5c;
+    uint32_t reserved_c60;
+    uint32_t reserved_c64;
+    uint32_t reserved_c68;
+    uint32_t reserved_c6c;
+    uint32_t reserved_c70;
+    uint32_t reserved_c74;
+    uint32_t reserved_c78;
+    uint32_t reserved_c7c;
+    uint32_t reserved_c80;
+    uint32_t reserved_c84;
+    uint32_t reserved_c88;
+    uint32_t reserved_c8c;
+    uint32_t reserved_c90;
+    uint32_t reserved_c94;
+    uint32_t reserved_c98;
+    uint32_t reserved_c9c;
+    uint32_t reserved_ca0;
+    uint32_t reserved_ca4;
+    uint32_t reserved_ca8;
+    uint32_t reserved_cac;
+    uint32_t reserved_cb0;
+    uint32_t reserved_cb4;
+    uint32_t reserved_cb8;
+    uint32_t reserved_cbc;
+    uint32_t reserved_cc0;
+    uint32_t reserved_cc4;
+    uint32_t reserved_cc8;
+    uint32_t reserved_ccc;
+    uint32_t reserved_cd0;
+    uint32_t reserved_cd4;
+    uint32_t reserved_cd8;
+    uint32_t reserved_cdc;
+    uint32_t reserved_ce0;
+    uint32_t reserved_ce4;
+    uint32_t reserved_ce8;
+    uint32_t reserved_cec;
+    uint32_t reserved_cf0;
+    uint32_t reserved_cf4;
+    uint32_t reserved_cf8;
+    uint32_t reserved_cfc;
+    uint32_t reserved_d00;
+    uint32_t reserved_d04;
+    uint32_t reserved_d08;
+    uint32_t reserved_d0c;
+    uint32_t reserved_d10;
+    uint32_t reserved_d14;
+    uint32_t reserved_d18;
+    uint32_t reserved_d1c;
+    uint32_t reserved_d20;
+    uint32_t reserved_d24;
+    uint32_t reserved_d28;
+    uint32_t reserved_d2c;
+    uint32_t reserved_d30;
+    uint32_t reserved_d34;
+    uint32_t reserved_d38;
+    uint32_t reserved_d3c;
+    uint32_t reserved_d40;
+    uint32_t reserved_d44;
+    uint32_t reserved_d48;
+    uint32_t reserved_d4c;
+    uint32_t reserved_d50;
+    uint32_t reserved_d54;
+    uint32_t reserved_d58;
+    uint32_t reserved_d5c;
+    uint32_t reserved_d60;
+    uint32_t reserved_d64;
+    uint32_t reserved_d68;
+    uint32_t reserved_d6c;
+    uint32_t reserved_d70;
+    uint32_t reserved_d74;
+    uint32_t reserved_d78;
+    uint32_t reserved_d7c;
+    uint32_t reserved_d80;
+    uint32_t reserved_d84;
+    uint32_t reserved_d88;
+    uint32_t reserved_d8c;
+    uint32_t reserved_d90;
+    uint32_t reserved_d94;
+    uint32_t reserved_d98;
+    uint32_t reserved_d9c;
+    uint32_t reserved_da0;
+    uint32_t reserved_da4;
+    uint32_t reserved_da8;
+    uint32_t reserved_dac;
+    uint32_t reserved_db0;
+    uint32_t reserved_db4;
+    uint32_t reserved_db8;
+    uint32_t reserved_dbc;
+    uint32_t reserved_dc0;
+    uint32_t reserved_dc4;
+    uint32_t reserved_dc8;
+    uint32_t reserved_dcc;
+    uint32_t reserved_dd0;
+    uint32_t reserved_dd4;
+    uint32_t reserved_dd8;
+    uint32_t reserved_ddc;
+    uint32_t reserved_de0;
+    uint32_t reserved_de4;
+    uint32_t reserved_de8;
+    uint32_t reserved_dec;
+    uint32_t reserved_df0;
+    uint32_t reserved_df4;
+    uint32_t reserved_df8;
+    uint32_t reserved_dfc;
+    uint32_t reserved_e00;
+    uint32_t reserved_e04;
+    uint32_t reserved_e08;
+    uint32_t reserved_e0c;
+    uint32_t reserved_e10;
+    uint32_t reserved_e14;
+    uint32_t reserved_e18;
+    uint32_t reserved_e1c;
+    uint32_t reserved_e20;
+    uint32_t reserved_e24;
+    uint32_t reserved_e28;
+    uint32_t reserved_e2c;
+    uint32_t reserved_e30;
+    uint32_t reserved_e34;
+    uint32_t reserved_e38;
+    uint32_t reserved_e3c;
+    uint32_t reserved_e40;
+    uint32_t reserved_e44;
+    uint32_t reserved_e48;
+    uint32_t reserved_e4c;
+    uint32_t reserved_e50;
+    uint32_t reserved_e54;
+    uint32_t reserved_e58;
+    uint32_t reserved_e5c;
+    uint32_t reserved_e60;
+    uint32_t reserved_e64;
+    uint32_t reserved_e68;
+    uint32_t reserved_e6c;
+    uint32_t reserved_e70;
+    uint32_t reserved_e74;
+    uint32_t reserved_e78;
+    uint32_t reserved_e7c;
+    uint32_t reserved_e80;
+    uint32_t reserved_e84;
+    uint32_t reserved_e88;
+    uint32_t reserved_e8c;
+    uint32_t reserved_e90;
+    uint32_t reserved_e94;
+    uint32_t reserved_e98;
+    uint32_t reserved_e9c;
+    uint32_t reserved_ea0;
+    uint32_t reserved_ea4;
+    uint32_t reserved_ea8;
+    uint32_t reserved_eac;
+    uint32_t reserved_eb0;
+    uint32_t reserved_eb4;
+    uint32_t reserved_eb8;
+    uint32_t reserved_ebc;
+    uint32_t reserved_ec0;
+    uint32_t reserved_ec4;
+    uint32_t reserved_ec8;
+    uint32_t reserved_ecc;
+    uint32_t reserved_ed0;
+    uint32_t reserved_ed4;
+    uint32_t reserved_ed8;
+    uint32_t reserved_edc;
+    uint32_t reserved_ee0;
+    uint32_t reserved_ee4;
+    uint32_t reserved_ee8;
+    uint32_t reserved_eec;
+    uint32_t reserved_ef0;
+    uint32_t reserved_ef4;
+    uint32_t reserved_ef8;
+    uint32_t reserved_efc;
+    uint32_t reserved_f00;
+    uint32_t reserved_f04;
+    uint32_t reserved_f08;
+    uint32_t reserved_f0c;
+    uint32_t reserved_f10;
+    uint32_t reserved_f14;
+    uint32_t reserved_f18;
+    uint32_t reserved_f1c;
+    uint32_t reserved_f20;
+    uint32_t reserved_f24;
+    uint32_t reserved_f28;
+    uint32_t reserved_f2c;
+    uint32_t reserved_f30;
+    uint32_t reserved_f34;
+    uint32_t reserved_f38;
+    uint32_t reserved_f3c;
+    uint32_t reserved_f40;
+    uint32_t reserved_f44;
+    uint32_t reserved_f48;
+    uint32_t reserved_f4c;
+    uint32_t reserved_f50;
+    uint32_t reserved_f54;
+    uint32_t reserved_f58;
+    uint32_t reserved_f5c;
+    uint32_t reserved_f60;
+    uint32_t reserved_f64;
+    uint32_t reserved_f68;
+    uint32_t reserved_f6c;
+    uint32_t reserved_f70;
+    uint32_t reserved_f74;
+    uint32_t reserved_f78;
+    uint32_t reserved_f7c;
+    uint32_t reserved_f80;
+    uint32_t reserved_f84;
+    uint32_t reserved_f88;
+    uint32_t reserved_f8c;
+    uint32_t reserved_f90;
+    uint32_t reserved_f94;
+    uint32_t reserved_f98;
+    uint32_t reserved_f9c;
+    uint32_t reserved_fa0;
+    uint32_t reserved_fa4;
+    uint32_t reserved_fa8;
+    uint32_t reserved_fac;
+    uint32_t reserved_fb0;
+    uint32_t reserved_fb4;
+    uint32_t reserved_fb8;
+    uint32_t reserved_fbc;
+    uint32_t reserved_fc0;
+    uint32_t reserved_fc4;
+    uint32_t reserved_fc8;
+    uint32_t reserved_fcc;
+    uint32_t reserved_fd0;
+    uint32_t reserved_fd4;
+    uint32_t reserved_fd8;
+    uint32_t reserved_fdc;
+    uint32_t reserved_fe0;
+    uint32_t reserved_fe4;
+    uint32_t reserved_fe8;
+    uint32_t reserved_fec;
+    uint32_t reserved_ff0;
+    uint32_t reserved_ff4;
+    uint32_t reserved_ff8;
+    union {
+        struct {
+            uint32_t reg_system_reg_date           :    28;  /*reg_system_reg_date*/
+            uint32_t reserved28                    :    4;  /*reserved*/
+        };
+        uint32_t val;
+    } date;
+} system_dev_t;
+extern system_dev_t SYSTEM;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SYSTEM_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/systimer_caps.h b/components/soc/esp32c3/include/soc/systimer_caps.h
new file mode 100644
index 0000000000..feda097f45
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/systimer_caps.h
@@ -0,0 +1,24 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#define SOC_SYSTIMER_COUNTER_NUM (2)   // Number of counter units
+#define SOC_SYSTIMER_ALARM_NUM (3)     // Number of alarm units
+
+#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part
+#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part
+
+#define SOC_SYSTIMER_FIXED_TICKS_US (16)  // If defined, number of ticks per microsecond is fixed
+#define SOC_SYSTIMER_INT_LEVEL      (1)   // Systimer peripheral uses level interrupt
diff --git a/components/soc/esp32c3/include/soc/systimer_reg.h b/components/soc/esp32c3/include/soc/systimer_reg.h
new file mode 100644
index 0000000000..cb6ebe6a43
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/systimer_reg.h
@@ -0,0 +1,424 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SYS_TIMER_REG_H_
+#define _SOC_SYS_TIMER_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define SYS_TIMER_SYSTIMER_CONF_REG          (DR_REG_SYS_TIMER_BASE + 0x0000)
+/* SYS_TIMER_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: register file clk gating*/
+#define SYS_TIMER_CLK_EN  (BIT(31))
+#define SYS_TIMER_CLK_EN_M  (BIT(31))
+#define SYS_TIMER_CLK_EN_V  0x1
+#define SYS_TIMER_CLK_EN_S  31
+/* SYS_TIMER_TIMER_UNIT0_WORK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: timer unit0 work enable*/
+#define SYS_TIMER_TIMER_UNIT0_WORK_EN  (BIT(30))
+#define SYS_TIMER_TIMER_UNIT0_WORK_EN_M  (BIT(30))
+#define SYS_TIMER_TIMER_UNIT0_WORK_EN_V  0x1
+#define SYS_TIMER_TIMER_UNIT0_WORK_EN_S  30
+/* SYS_TIMER_TIMER_UNIT1_WORK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: timer unit1 work enable*/
+#define SYS_TIMER_TIMER_UNIT1_WORK_EN  (BIT(29))
+#define SYS_TIMER_TIMER_UNIT1_WORK_EN_M  (BIT(29))
+#define SYS_TIMER_TIMER_UNIT1_WORK_EN_V  0x1
+#define SYS_TIMER_TIMER_UNIT1_WORK_EN_S  29
+/* SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: If timer unit0 is stalled when core0 stalled*/
+#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN  (BIT(28))
+#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_M  (BIT(28))
+#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_V  0x1
+#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_S  28
+/* SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: If timer unit0 is stalled when core1 stalled*/
+#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN  (BIT(27))
+#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_M  (BIT(27))
+#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_V  0x1
+#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_S  27
+/* SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W ;bitpos:[26] ;default: 1'b1 ; */
+/*description: If timer unit1 is stalled when core0 stalled*/
+#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN  (BIT(26))
+#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_M  (BIT(26))
+#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_V  0x1
+#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_S  26
+/* SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: If timer unit1 is stalled when core1 stalled*/
+#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN  (BIT(25))
+#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_M  (BIT(25))
+#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_V  0x1
+#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_S  25
+/* SYS_TIMER_TARGET0_WORK_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: target0 work enable*/
+#define SYS_TIMER_TARGET0_WORK_EN  (BIT(24))
+#define SYS_TIMER_TARGET0_WORK_EN_M  (BIT(24))
+#define SYS_TIMER_TARGET0_WORK_EN_V  0x1
+#define SYS_TIMER_TARGET0_WORK_EN_S  24
+/* SYS_TIMER_TARGET1_WORK_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: target1 work enable*/
+#define SYS_TIMER_TARGET1_WORK_EN  (BIT(23))
+#define SYS_TIMER_TARGET1_WORK_EN_M  (BIT(23))
+#define SYS_TIMER_TARGET1_WORK_EN_V  0x1
+#define SYS_TIMER_TARGET1_WORK_EN_S  23
+/* SYS_TIMER_TARGET2_WORK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: target2 work enable*/
+#define SYS_TIMER_TARGET2_WORK_EN  (BIT(22))
+#define SYS_TIMER_TARGET2_WORK_EN_M  (BIT(22))
+#define SYS_TIMER_TARGET2_WORK_EN_V  0x1
+#define SYS_TIMER_TARGET2_WORK_EN_S  22
+/* SYS_TIMER_SYSTIMER_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: systimer clock force on*/
+#define SYS_TIMER_SYSTIMER_CLK_FO  (BIT(0))
+#define SYS_TIMER_SYSTIMER_CLK_FO_M  (BIT(0))
+#define SYS_TIMER_SYSTIMER_CLK_FO_V  0x1
+#define SYS_TIMER_SYSTIMER_CLK_FO_S  0
+
+#define SYS_TIMER_SYSTIMER_UNIT0_OP_REG          (DR_REG_SYS_TIMER_BASE + 0x0004)
+/* SYS_TIMER_TIMER_UNIT0_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */
+/*description: update timer_unit0*/
+#define SYS_TIMER_TIMER_UNIT0_UPDATE  (BIT(30))
+#define SYS_TIMER_TIMER_UNIT0_UPDATE_M  (BIT(30))
+#define SYS_TIMER_TIMER_UNIT0_UPDATE_V  0x1
+#define SYS_TIMER_TIMER_UNIT0_UPDATE_S  30
+/* SYS_TIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID  (BIT(29))
+#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_M  (BIT(29))
+#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_V  0x1
+#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_S  29
+
+#define SYS_TIMER_SYSTIMER_UNIT1_OP_REG          (DR_REG_SYS_TIMER_BASE + 0x0008)
+/* SYS_TIMER_TIMER_UNIT1_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */
+/*description: update timer unit1*/
+#define SYS_TIMER_TIMER_UNIT1_UPDATE  (BIT(30))
+#define SYS_TIMER_TIMER_UNIT1_UPDATE_M  (BIT(30))
+#define SYS_TIMER_TIMER_UNIT1_UPDATE_V  0x1
+#define SYS_TIMER_TIMER_UNIT1_UPDATE_S  30
+/* SYS_TIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
+/*description: timer value is sync and valid*/
+#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID  (BIT(29))
+#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_M  (BIT(29))
+#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_V  0x1
+#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_S  29
+
+#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG          (DR_REG_SYS_TIMER_BASE + 0x000C)
+/* SYS_TIMER_TIMER_UNIT0_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
+/*description: timer unit0 load high 32 bit*/
+#define SYS_TIMER_TIMER_UNIT0_LOAD_HI  0x000FFFFF
+#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_M  ((SYS_TIMER_TIMER_UNIT0_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_HI_S))
+#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_V  0xFFFFF
+#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_S  0
+
+#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG          (DR_REG_SYS_TIMER_BASE + 0x0010)
+/* SYS_TIMER_TIMER_UNIT0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: timer unit0 load low 32 bit*/
+#define SYS_TIMER_TIMER_UNIT0_LOAD_LO  0xFFFFFFFF
+#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_M  ((SYS_TIMER_TIMER_UNIT0_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_LO_S))
+#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_V  0xFFFFFFFF
+#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_S  0
+
+#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_HI_REG          (DR_REG_SYS_TIMER_BASE + 0x0014)
+/* SYS_TIMER_TIMER_UNIT1_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
+/*description: timer unit1 load high 32 bit*/
+#define SYS_TIMER_TIMER_UNIT1_LOAD_HI  0x000FFFFF
+#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_M  ((SYS_TIMER_TIMER_UNIT1_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_HI_S))
+#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_V  0xFFFFF
+#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_S  0
+
+#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_LO_REG          (DR_REG_SYS_TIMER_BASE + 0x0018)
+/* SYS_TIMER_TIMER_UNIT1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: timer unit1 load low 32 bit*/
+#define SYS_TIMER_TIMER_UNIT1_LOAD_LO  0xFFFFFFFF
+#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_M  ((SYS_TIMER_TIMER_UNIT1_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_LO_S))
+#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_V  0xFFFFFFFF
+#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_S  0
+
+#define SYS_TIMER_SYSTIMER_TARGET0_HI_REG          (DR_REG_SYS_TIMER_BASE + 0x001C)
+/* SYS_TIMER_TIMER_TARGET0_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
+/*description: timer taget0 high 32 bit*/
+#define SYS_TIMER_TIMER_TARGET0_HI  0x000FFFFF
+#define SYS_TIMER_TIMER_TARGET0_HI_M  ((SYS_TIMER_TIMER_TARGET0_HI_V)<<(SYS_TIMER_TIMER_TARGET0_HI_S))
+#define SYS_TIMER_TIMER_TARGET0_HI_V  0xFFFFF
+#define SYS_TIMER_TIMER_TARGET0_HI_S  0
+
+#define SYS_TIMER_SYSTIMER_TARGET0_LO_REG          (DR_REG_SYS_TIMER_BASE + 0x0020)
+/* SYS_TIMER_TIMER_TARGET0_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: timer taget0 low 32 bit*/
+#define SYS_TIMER_TIMER_TARGET0_LO  0xFFFFFFFF
+#define SYS_TIMER_TIMER_TARGET0_LO_M  ((SYS_TIMER_TIMER_TARGET0_LO_V)<<(SYS_TIMER_TIMER_TARGET0_LO_S))
+#define SYS_TIMER_TIMER_TARGET0_LO_V  0xFFFFFFFF
+#define SYS_TIMER_TIMER_TARGET0_LO_S  0
+
+#define SYS_TIMER_SYSTIMER_TARGET1_HI_REG          (DR_REG_SYS_TIMER_BASE + 0x0024)
+/* SYS_TIMER_TIMER_TARGET1_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
+/*description: timer taget1 high 32 bit*/
+#define SYS_TIMER_TIMER_TARGET1_HI  0x000FFFFF
+#define SYS_TIMER_TIMER_TARGET1_HI_M  ((SYS_TIMER_TIMER_TARGET1_HI_V)<<(SYS_TIMER_TIMER_TARGET1_HI_S))
+#define SYS_TIMER_TIMER_TARGET1_HI_V  0xFFFFF
+#define SYS_TIMER_TIMER_TARGET1_HI_S  0
+
+#define SYS_TIMER_SYSTIMER_TARGET1_LO_REG          (DR_REG_SYS_TIMER_BASE + 0x0028)
+/* SYS_TIMER_TIMER_TARGET1_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: timer taget1 low 32 bit*/
+#define SYS_TIMER_TIMER_TARGET1_LO  0xFFFFFFFF
+#define SYS_TIMER_TIMER_TARGET1_LO_M  ((SYS_TIMER_TIMER_TARGET1_LO_V)<<(SYS_TIMER_TIMER_TARGET1_LO_S))
+#define SYS_TIMER_TIMER_TARGET1_LO_V  0xFFFFFFFF
+#define SYS_TIMER_TIMER_TARGET1_LO_S  0
+
+#define SYS_TIMER_SYSTIMER_TARGET2_HI_REG          (DR_REG_SYS_TIMER_BASE + 0x002C)
+/* SYS_TIMER_TIMER_TARGET2_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
+/*description: timer taget2 high 32 bit*/
+#define SYS_TIMER_TIMER_TARGET2_HI  0x000FFFFF
+#define SYS_TIMER_TIMER_TARGET2_HI_M  ((SYS_TIMER_TIMER_TARGET2_HI_V)<<(SYS_TIMER_TIMER_TARGET2_HI_S))
+#define SYS_TIMER_TIMER_TARGET2_HI_V  0xFFFFF
+#define SYS_TIMER_TIMER_TARGET2_HI_S  0
+
+#define SYS_TIMER_SYSTIMER_TARGET2_LO_REG          (DR_REG_SYS_TIMER_BASE + 0x0030)
+/* SYS_TIMER_TIMER_TARGET2_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: timer taget2 low 32 bit*/
+#define SYS_TIMER_TIMER_TARGET2_LO  0xFFFFFFFF
+#define SYS_TIMER_TIMER_TARGET2_LO_M  ((SYS_TIMER_TIMER_TARGET2_LO_V)<<(SYS_TIMER_TIMER_TARGET2_LO_S))
+#define SYS_TIMER_TIMER_TARGET2_LO_V  0xFFFFFFFF
+#define SYS_TIMER_TIMER_TARGET2_LO_S  0
+
+#define SYS_TIMER_SYSTIMER_TARGET0_CONF_REG          (DR_REG_SYS_TIMER_BASE + 0x0034)
+/* SYS_TIMER_TARGET0_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: select which unit to compare*/
+#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL  (BIT(31))
+#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_M  (BIT(31))
+#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_V  0x1
+#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_S  31
+/* SYS_TIMER_TARGET0_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set target0 to period mode*/
+#define SYS_TIMER_TARGET0_PERIOD_MODE  (BIT(30))
+#define SYS_TIMER_TARGET0_PERIOD_MODE_M  (BIT(30))
+#define SYS_TIMER_TARGET0_PERIOD_MODE_V  0x1
+#define SYS_TIMER_TARGET0_PERIOD_MODE_S  30
+/* SYS_TIMER_TARGET0_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: target0 period*/
+#define SYS_TIMER_TARGET0_PERIOD  0x03FFFFFF
+#define SYS_TIMER_TARGET0_PERIOD_M  ((SYS_TIMER_TARGET0_PERIOD_V)<<(SYS_TIMER_TARGET0_PERIOD_S))
+#define SYS_TIMER_TARGET0_PERIOD_V  0x3FFFFFF
+#define SYS_TIMER_TARGET0_PERIOD_S  0
+
+#define SYS_TIMER_SYSTIMER_TARGET1_CONF_REG          (DR_REG_SYS_TIMER_BASE + 0x0038)
+/* SYS_TIMER_TARGET1_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: select which unit to compare*/
+#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL  (BIT(31))
+#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_M  (BIT(31))
+#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_V  0x1
+#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_S  31
+/* SYS_TIMER_TARGET1_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set target1 to period mode*/
+#define SYS_TIMER_TARGET1_PERIOD_MODE  (BIT(30))
+#define SYS_TIMER_TARGET1_PERIOD_MODE_M  (BIT(30))
+#define SYS_TIMER_TARGET1_PERIOD_MODE_V  0x1
+#define SYS_TIMER_TARGET1_PERIOD_MODE_S  30
+/* SYS_TIMER_TARGET1_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: target1 period*/
+#define SYS_TIMER_TARGET1_PERIOD  0x03FFFFFF
+#define SYS_TIMER_TARGET1_PERIOD_M  ((SYS_TIMER_TARGET1_PERIOD_V)<<(SYS_TIMER_TARGET1_PERIOD_S))
+#define SYS_TIMER_TARGET1_PERIOD_V  0x3FFFFFF
+#define SYS_TIMER_TARGET1_PERIOD_S  0
+
+#define SYS_TIMER_SYSTIMER_TARGET2_CONF_REG          (DR_REG_SYS_TIMER_BASE + 0x003C)
+/* SYS_TIMER_TARGET2_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: select which unit to compare*/
+#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL  (BIT(31))
+#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_M  (BIT(31))
+#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_V  0x1
+#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_S  31
+/* SYS_TIMER_TARGET2_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set target2 to period mode*/
+#define SYS_TIMER_TARGET2_PERIOD_MODE  (BIT(30))
+#define SYS_TIMER_TARGET2_PERIOD_MODE_M  (BIT(30))
+#define SYS_TIMER_TARGET2_PERIOD_MODE_V  0x1
+#define SYS_TIMER_TARGET2_PERIOD_MODE_S  30
+/* SYS_TIMER_TARGET2_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: target2 period*/
+#define SYS_TIMER_TARGET2_PERIOD  0x03FFFFFF
+#define SYS_TIMER_TARGET2_PERIOD_M  ((SYS_TIMER_TARGET2_PERIOD_V)<<(SYS_TIMER_TARGET2_PERIOD_S))
+#define SYS_TIMER_TARGET2_PERIOD_V  0x3FFFFFF
+#define SYS_TIMER_TARGET2_PERIOD_S  0
+
+#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG          (DR_REG_SYS_TIMER_BASE + 0x0040)
+/* SYS_TIMER_TIMER_UNIT0_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */
+/*description: timer read value high 32bit*/
+#define SYS_TIMER_TIMER_UNIT0_VALUE_HI  0x000FFFFF
+#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_M  ((SYS_TIMER_TIMER_UNIT0_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_HI_S))
+#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_V  0xFFFFF
+#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_S  0
+
+#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_LO_REG          (DR_REG_SYS_TIMER_BASE + 0x0044)
+/* SYS_TIMER_TIMER_UNIT0_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: timer read value low 32bit*/
+#define SYS_TIMER_TIMER_UNIT0_VALUE_LO  0xFFFFFFFF
+#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_M  ((SYS_TIMER_TIMER_UNIT0_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_LO_S))
+#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_V  0xFFFFFFFF
+#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_S  0
+
+#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_HI_REG          (DR_REG_SYS_TIMER_BASE + 0x0048)
+/* SYS_TIMER_TIMER_UNIT1_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */
+/*description: timer read value high 32bit*/
+#define SYS_TIMER_TIMER_UNIT1_VALUE_HI  0x000FFFFF
+#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_M  ((SYS_TIMER_TIMER_UNIT1_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_HI_S))
+#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_V  0xFFFFF
+#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_S  0
+
+#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_LO_REG          (DR_REG_SYS_TIMER_BASE + 0x004C)
+/* SYS_TIMER_TIMER_UNIT1_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: timer read value low 32bit*/
+#define SYS_TIMER_TIMER_UNIT1_VALUE_LO  0xFFFFFFFF
+#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_M  ((SYS_TIMER_TIMER_UNIT1_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_LO_S))
+#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_V  0xFFFFFFFF
+#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_S  0
+
+#define SYS_TIMER_SYSTIMER_COMP0_LOAD_REG          (DR_REG_SYS_TIMER_BASE + 0x0050)
+/* SYS_TIMER_TIMER_COMP0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: timer comp0 load value*/
+#define SYS_TIMER_TIMER_COMP0_LOAD  (BIT(0))
+#define SYS_TIMER_TIMER_COMP0_LOAD_M  (BIT(0))
+#define SYS_TIMER_TIMER_COMP0_LOAD_V  0x1
+#define SYS_TIMER_TIMER_COMP0_LOAD_S  0
+
+#define SYS_TIMER_SYSTIMER_COMP1_LOAD_REG          (DR_REG_SYS_TIMER_BASE + 0x0054)
+/* SYS_TIMER_TIMER_COMP1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: timer comp1 load value*/
+#define SYS_TIMER_TIMER_COMP1_LOAD  (BIT(0))
+#define SYS_TIMER_TIMER_COMP1_LOAD_M  (BIT(0))
+#define SYS_TIMER_TIMER_COMP1_LOAD_V  0x1
+#define SYS_TIMER_TIMER_COMP1_LOAD_S  0
+
+#define SYS_TIMER_SYSTIMER_COMP2_LOAD_REG          (DR_REG_SYS_TIMER_BASE + 0x0058)
+/* SYS_TIMER_TIMER_COMP2_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: timer comp2 load value*/
+#define SYS_TIMER_TIMER_COMP2_LOAD  (BIT(0))
+#define SYS_TIMER_TIMER_COMP2_LOAD_M  (BIT(0))
+#define SYS_TIMER_TIMER_COMP2_LOAD_V  0x1
+#define SYS_TIMER_TIMER_COMP2_LOAD_S  0
+
+#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_REG          (DR_REG_SYS_TIMER_BASE + 0x005C)
+/* SYS_TIMER_TIMER_UNIT0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: timer unit0 load value*/
+#define SYS_TIMER_TIMER_UNIT0_LOAD  (BIT(0))
+#define SYS_TIMER_TIMER_UNIT0_LOAD_M  (BIT(0))
+#define SYS_TIMER_TIMER_UNIT0_LOAD_V  0x1
+#define SYS_TIMER_TIMER_UNIT0_LOAD_S  0
+
+#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_REG          (DR_REG_SYS_TIMER_BASE + 0x0060)
+/* SYS_TIMER_TIMER_UNIT1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: timer unit1 load value*/
+#define SYS_TIMER_TIMER_UNIT1_LOAD  (BIT(0))
+#define SYS_TIMER_TIMER_UNIT1_LOAD_M  (BIT(0))
+#define SYS_TIMER_TIMER_UNIT1_LOAD_V  0x1
+#define SYS_TIMER_TIMER_UNIT1_LOAD_S  0
+
+#define SYS_TIMER_SYSTIMER_INT_ENA_REG          (DR_REG_SYS_TIMER_BASE + 0x0064)
+/* SYS_TIMER_TARGET2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: interupt2 enable*/
+#define SYS_TIMER_TARGET2_INT_ENA  (BIT(2))
+#define SYS_TIMER_TARGET2_INT_ENA_M  (BIT(2))
+#define SYS_TIMER_TARGET2_INT_ENA_V  0x1
+#define SYS_TIMER_TARGET2_INT_ENA_S  2
+/* SYS_TIMER_TARGET1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: interupt1 enable*/
+#define SYS_TIMER_TARGET1_INT_ENA  (BIT(1))
+#define SYS_TIMER_TARGET1_INT_ENA_M  (BIT(1))
+#define SYS_TIMER_TARGET1_INT_ENA_V  0x1
+#define SYS_TIMER_TARGET1_INT_ENA_S  1
+/* SYS_TIMER_TARGET0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: interupt0 enable*/
+#define SYS_TIMER_TARGET0_INT_ENA  (BIT(0))
+#define SYS_TIMER_TARGET0_INT_ENA_M  (BIT(0))
+#define SYS_TIMER_TARGET0_INT_ENA_V  0x1
+#define SYS_TIMER_TARGET0_INT_ENA_S  0
+
+#define SYS_TIMER_SYSTIMER_INT_RAW_REG          (DR_REG_SYS_TIMER_BASE + 0x0068)
+/* SYS_TIMER_TARGET2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: interupt2 raw*/
+#define SYS_TIMER_TARGET2_INT_RAW  (BIT(2))
+#define SYS_TIMER_TARGET2_INT_RAW_M  (BIT(2))
+#define SYS_TIMER_TARGET2_INT_RAW_V  0x1
+#define SYS_TIMER_TARGET2_INT_RAW_S  2
+/* SYS_TIMER_TARGET1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: interupt1 raw*/
+#define SYS_TIMER_TARGET1_INT_RAW  (BIT(1))
+#define SYS_TIMER_TARGET1_INT_RAW_M  (BIT(1))
+#define SYS_TIMER_TARGET1_INT_RAW_V  0x1
+#define SYS_TIMER_TARGET1_INT_RAW_S  1
+/* SYS_TIMER_TARGET0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: interupt0 raw*/
+#define SYS_TIMER_TARGET0_INT_RAW  (BIT(0))
+#define SYS_TIMER_TARGET0_INT_RAW_M  (BIT(0))
+#define SYS_TIMER_TARGET0_INT_RAW_V  0x1
+#define SYS_TIMER_TARGET0_INT_RAW_S  0
+
+#define SYS_TIMER_SYSTIMER_INT_CLR_REG          (DR_REG_SYS_TIMER_BASE + 0x006c)
+/* SYS_TIMER_TARGET2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: interupt2 clear*/
+#define SYS_TIMER_TARGET2_INT_CLR  (BIT(2))
+#define SYS_TIMER_TARGET2_INT_CLR_M  (BIT(2))
+#define SYS_TIMER_TARGET2_INT_CLR_V  0x1
+#define SYS_TIMER_TARGET2_INT_CLR_S  2
+/* SYS_TIMER_TARGET1_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: interupt1 clear*/
+#define SYS_TIMER_TARGET1_INT_CLR  (BIT(1))
+#define SYS_TIMER_TARGET1_INT_CLR_M  (BIT(1))
+#define SYS_TIMER_TARGET1_INT_CLR_V  0x1
+#define SYS_TIMER_TARGET1_INT_CLR_S  1
+/* SYS_TIMER_TARGET0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: interupt0 clear*/
+#define SYS_TIMER_TARGET0_INT_CLR  (BIT(0))
+#define SYS_TIMER_TARGET0_INT_CLR_M  (BIT(0))
+#define SYS_TIMER_TARGET0_INT_CLR_V  0x1
+#define SYS_TIMER_TARGET0_INT_CLR_S  0
+
+#define SYS_TIMER_SYSTIMER_INT_ST_REG          (DR_REG_SYS_TIMER_BASE + 0x0070)
+/* SYS_TIMER_TARGET2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SYS_TIMER_TARGET2_INT_ST  (BIT(2))
+#define SYS_TIMER_TARGET2_INT_ST_M  (BIT(2))
+#define SYS_TIMER_TARGET2_INT_ST_V  0x1
+#define SYS_TIMER_TARGET2_INT_ST_S  2
+/* SYS_TIMER_TARGET1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYS_TIMER_TARGET1_INT_ST  (BIT(1))
+#define SYS_TIMER_TARGET1_INT_ST_M  (BIT(1))
+#define SYS_TIMER_TARGET1_INT_ST_V  0x1
+#define SYS_TIMER_TARGET1_INT_ST_S  1
+/* SYS_TIMER_TARGET0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYS_TIMER_TARGET0_INT_ST  (BIT(0))
+#define SYS_TIMER_TARGET0_INT_ST_M  (BIT(0))
+#define SYS_TIMER_TARGET0_INT_ST_V  0x1
+#define SYS_TIMER_TARGET0_INT_ST_S  0
+
+#define SYS_TIMER_SYSTIMER_DATE_REG          (DR_REG_SYS_TIMER_BASE + 0x00fc)
+/* SYS_TIMER_DATE : R/W ;bitpos:[31:0] ;default: 28'h2006171 ; */
+/*description: */
+#define SYS_TIMER_DATE  0xFFFFFFFF
+#define SYS_TIMER_DATE_M  ((SYS_TIMER_DATE_V)<<(SYS_TIMER_DATE_S))
+#define SYS_TIMER_DATE_V  0xFFFFFFFF
+#define SYS_TIMER_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SYS_TIMER_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/systimer_struct.h b/components/soc/esp32c3/include/soc/systimer_struct.h
new file mode 100644
index 0000000000..b029eca80b
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/systimer_struct.h
@@ -0,0 +1,251 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SYS_TIMER_STRUCT_H_
+#define _SOC_SYS_TIMER_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t systimer_clk_fo:            1;       /*systimer clock force on*/
+            uint32_t reserved1:                 21;
+            uint32_t target2_work_en:            1;       /*target2 work enable*/
+            uint32_t target1_work_en:            1;       /*target1 work enable*/
+            uint32_t target0_work_en:            1;       /*target0 work enable*/
+            uint32_t timer_unit1_core1_stall_en: 1;       /*If timer unit1 is stalled when core1 stalled*/
+            uint32_t timer_unit1_core0_stall_en: 1;       /*If timer unit1 is stalled when core0 stalled*/
+            uint32_t timer_unit0_core1_stall_en: 1;       /*If timer unit0 is stalled when core1 stalled*/
+            uint32_t timer_unit0_core0_stall_en: 1;       /*If timer unit0 is stalled when core0 stalled*/
+            uint32_t timer_unit1_work_en:        1;       /*timer unit1 work enable*/
+            uint32_t timer_unit0_work_en:        1;       /*timer unit0 work enable*/
+            uint32_t clk_en:                     1;       /*register file clk gating*/
+        };
+        uint32_t val;
+    } systimer_conf;
+    union {
+        struct {
+            uint32_t reserved0:              29;
+            uint32_t timer_unit0_value_valid: 1;
+            uint32_t timer_unit0_update:      1;          /*update timer_unit0*/
+            uint32_t reserved31:              1;
+        };
+        uint32_t val;
+    } systimer_unit0_op;
+    union {
+        struct {
+            uint32_t reserved0:              29;
+            uint32_t timer_unit1_value_valid: 1;          /*timer value is sync and valid*/
+            uint32_t timer_unit1_update:      1;          /*update timer unit1*/
+            uint32_t reserved31:              1;
+        };
+        uint32_t val;
+    } systimer_unit1_op;
+    union {
+        struct {
+            uint32_t timer_unit0_load_hi:20;              /*timer unit0 load high 32 bit*/
+            uint32_t reserved20:         12;
+        };
+        uint32_t val;
+    } systimer_unit0_load_hi;
+    uint32_t systimer_unit0_load_lo;                      /**/
+    union {
+        struct {
+            uint32_t timer_unit1_load_hi:20;              /*timer unit1 load high 32 bit*/
+            uint32_t reserved20:         12;
+        };
+        uint32_t val;
+    } systimer_unit1_load_hi;
+    uint32_t systimer_unit1_load_lo;                      /**/
+    union {
+        struct {
+            uint32_t timer_target0_hi:20;                 /*timer taget0 high 32 bit*/
+            uint32_t reserved20:      12;
+        };
+        uint32_t val;
+    } systimer_target0_hi;
+    uint32_t systimer_target0_lo;                         /**/
+    union {
+        struct {
+            uint32_t timer_target1_hi:20;                 /*timer taget1 high 32 bit*/
+            uint32_t reserved20:      12;
+        };
+        uint32_t val;
+    } systimer_target1_hi;
+    uint32_t systimer_target1_lo;                         /**/
+    union {
+        struct {
+            uint32_t timer_target2_hi:20;                 /*timer taget2 high 32 bit*/
+            uint32_t reserved20:      12;
+        };
+        uint32_t val;
+    } systimer_target2_hi;
+    uint32_t systimer_target2_lo;                         /**/
+    union {
+        struct {
+            uint32_t target0_period:        26;           /*target0 period*/
+            uint32_t reserved26:             4;
+            uint32_t target0_period_mode:    1;           /*Set target0 to period mode*/
+            uint32_t target0_timer_unit_sel: 1;           /*select which unit to compare*/
+        };
+        uint32_t val;
+    } systimer_target0_conf;
+    union {
+        struct {
+            uint32_t target1_period:        26;           /*target1 period*/
+            uint32_t reserved26:             4;
+            uint32_t target1_period_mode:    1;           /*Set target1 to period mode*/
+            uint32_t target1_timer_unit_sel: 1;           /*select which unit to compare*/
+        };
+        uint32_t val;
+    } systimer_target1_conf;
+    union {
+        struct {
+            uint32_t target2_period:        26;           /*target2 period*/
+            uint32_t reserved26:             4;
+            uint32_t target2_period_mode:    1;           /*Set target2 to period mode*/
+            uint32_t target2_timer_unit_sel: 1;           /*select which unit to compare*/
+        };
+        uint32_t val;
+    } systimer_target2_conf;
+    union {
+        struct {
+            uint32_t timer_unit0_value_hi:20;             /*timer read value high 32bit*/
+            uint32_t reserved20:          12;
+        };
+        uint32_t val;
+    } systimer_unit0_value_hi;
+    uint32_t systimer_unit0_value_lo;                     /**/
+    union {
+        struct {
+            uint32_t timer_unit1_value_hi:20;             /*timer read value high 32bit*/
+            uint32_t reserved20:          12;
+        };
+        uint32_t val;
+    } systimer_unit1_value_hi;
+    uint32_t systimer_unit1_value_lo;                     /**/
+    union {
+        struct {
+            uint32_t timer_comp0_load: 1;                 /*timer comp0 load value*/
+            uint32_t reserved1:       31;
+        };
+        uint32_t val;
+    } systimer_comp0_load;
+    union {
+        struct {
+            uint32_t timer_comp1_load: 1;                 /*timer comp1 load value*/
+            uint32_t reserved1:       31;
+        };
+        uint32_t val;
+    } systimer_comp1_load;
+    union {
+        struct {
+            uint32_t timer_comp2_load: 1;                 /*timer comp2 load value*/
+            uint32_t reserved1:       31;
+        };
+        uint32_t val;
+    } systimer_comp2_load;
+    union {
+        struct {
+            uint32_t timer_unit0_load: 1;                 /*timer unit0 load value*/
+            uint32_t reserved1:       31;
+        };
+        uint32_t val;
+    } systimer_unit0_load;
+    union {
+        struct {
+            uint32_t timer_unit1_load: 1;                 /*timer unit1 load value*/
+            uint32_t reserved1:       31;
+        };
+        uint32_t val;
+    } systimer_unit1_load;
+    union {
+        struct {
+            uint32_t target0:         1;                  /*interupt0 enable*/
+            uint32_t target1:         1;                  /*interupt1 enable*/
+            uint32_t target2:         1;                  /*interupt2 enable*/
+            uint32_t reserved3:      29;
+        };
+        uint32_t val;
+    } systimer_int_ena;
+    union {
+        struct {
+            uint32_t target0:         1;                  /*interupt0 raw*/
+            uint32_t target1:         1;                  /*interupt1 raw*/
+            uint32_t target2:         1;                  /*interupt2 raw*/
+            uint32_t reserved3:      29;
+        };
+        uint32_t val;
+    } systimer_int_raw;
+    union {
+        struct {
+            uint32_t target0:         1;                  /*interupt0 clear*/
+            uint32_t target1:         1;                  /*interupt1 clear*/
+            uint32_t target2:         1;                  /*interupt2 clear*/
+            uint32_t reserved3:      29;
+        };
+        uint32_t val;
+    } systimer_int_clr;
+    union {
+        struct {
+            uint32_t target0:        1;
+            uint32_t target1:        1;
+            uint32_t target2:        1;
+            uint32_t reserved3:     29;
+        };
+        uint32_t val;
+    } systimer_int_st;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t systimer_date;                               /**/
+} sys_timer_dev_t;
+extern sys_timer_dev_t SYS_TIMER;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_SYS_TIMER_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/timer_group_caps.h b/components/soc/esp32c3/include/soc/timer_group_caps.h
new file mode 100644
index 0000000000..b827b0005e
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/timer_group_caps.h
@@ -0,0 +1,24 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
+#define SOC_TIMER_GROUP_XTAL_MHZ (40)
+#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH  (54)
+#define SOC_TIMER_GROUP_PRESCALE_BIT_WIDTH (16)
+#define SOC_TIMER_GROUPS (2)
+#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1)
+#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
+#define SOC_TIMER_GROUP_LAYOUT {1,1}
diff --git a/components/soc/esp32c3/include/soc/timer_group_reg.h b/components/soc/esp32c3/include/soc/timer_group_reg.h
new file mode 100644
index 0000000000..05ae6fb42e
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/timer_group_reg.h
@@ -0,0 +1,441 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_TIMG_REG_H_
+#define _SOC_TIMG_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
+#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
+
+/* Possible values for TIMG_WDT_STGx */
+#define TIMG_WDT_STG_SEL_OFF 0
+#define TIMG_WDT_STG_SEL_INT 1
+#define TIMG_WDT_STG_SEL_RESET_CPU 2
+#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
+
+#define TIMG_WDT_RESET_LENGTH_100_NS 0
+#define TIMG_WDT_RESET_LENGTH_200_NS 1
+#define TIMG_WDT_RESET_LENGTH_300_NS 2
+#define TIMG_WDT_RESET_LENGTH_400_NS 3
+#define TIMG_WDT_RESET_LENGTH_500_NS 4
+#define TIMG_WDT_RESET_LENGTH_800_NS 5
+#define TIMG_WDT_RESET_LENGTH_1600_NS 6
+#define TIMG_WDT_RESET_LENGTH_3200_NS 7
+
+#define TIMG_T0CONFIG_REG(i)          (REG_TIMG_BASE(i) + 0x0000)
+/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T0_EN  (BIT(31))
+#define TIMG_T0_EN_M  (BIT(31))
+#define TIMG_T0_EN_V  0x1
+#define TIMG_T0_EN_S  31
+/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
+/*description: */
+#define TIMG_T0_INCREASE  (BIT(30))
+#define TIMG_T0_INCREASE_M  (BIT(30))
+#define TIMG_T0_INCREASE_V  0x1
+#define TIMG_T0_INCREASE_S  30
+/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
+/*description: */
+#define TIMG_T0_AUTORELOAD  (BIT(29))
+#define TIMG_T0_AUTORELOAD_M  (BIT(29))
+#define TIMG_T0_AUTORELOAD_V  0x1
+#define TIMG_T0_AUTORELOAD_S  29
+/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
+/*description: */
+#define TIMG_T0_DIVIDER  0x0000FFFF
+#define TIMG_T0_DIVIDER_M  ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S))
+#define TIMG_T0_DIVIDER_V  0xFFFF
+#define TIMG_T0_DIVIDER_S  13
+/* TIMG_T0_DIVCNT_RST : WT ;bitpos:[12] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T0_DIVCNT_RST  (BIT(12))
+#define TIMG_T0_DIVCNT_RST_M  (BIT(12))
+#define TIMG_T0_DIVCNT_RST_V  0x1
+#define TIMG_T0_DIVCNT_RST_S  12
+/* TIMG_T0_ALARM_EN : R/W/SC ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T0_ALARM_EN  (BIT(10))
+#define TIMG_T0_ALARM_EN_M  (BIT(10))
+#define TIMG_T0_ALARM_EN_V  0x1
+#define TIMG_T0_ALARM_EN_S  10
+/* TIMG_T0_USE_XTAL : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: */
+#define TIMG_T0_USE_XTAL  (BIT(9))
+#define TIMG_T0_USE_XTAL_M  (BIT(9))
+#define TIMG_T0_USE_XTAL_V  0x1
+#define TIMG_T0_USE_XTAL_S  9
+
+#define TIMG_T0LO_REG(i)          (REG_TIMG_BASE(i) + 0x0004)
+/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_T0_LO  0xFFFFFFFF
+#define TIMG_T0_LO_M  ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S))
+#define TIMG_T0_LO_V  0xFFFFFFFF
+#define TIMG_T0_LO_S  0
+
+#define TIMG_T0HI_REG(i)          (REG_TIMG_BASE(i) + 0x0008)
+/* TIMG_T0_HI : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define TIMG_T0_HI  0x003FFFFF
+#define TIMG_T0_HI_M  ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S))
+#define TIMG_T0_HI_V  0x3FFFFF
+#define TIMG_T0_HI_S  0
+
+#define TIMG_T0UPDATE_REG(i)          (REG_TIMG_BASE(i) + 0x000c)
+/* TIMG_T0_UPDATE : R/W/SC ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T0_UPDATE  (BIT(31))
+#define TIMG_T0_UPDATE_M  (BIT(31))
+#define TIMG_T0_UPDATE_V  0x1
+#define TIMG_T0_UPDATE_S  31
+
+#define TIMG_T0ALARMLO_REG(i)          (REG_TIMG_BASE(i) + 0x0010)
+/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_T0_ALARM_LO  0xFFFFFFFF
+#define TIMG_T0_ALARM_LO_M  ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S))
+#define TIMG_T0_ALARM_LO_V  0xFFFFFFFF
+#define TIMG_T0_ALARM_LO_S  0
+
+#define TIMG_T0ALARMHI_REG(i)          (REG_TIMG_BASE(i) + 0x0014)
+/* TIMG_T0_ALARM_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define TIMG_T0_ALARM_HI  0x003FFFFF
+#define TIMG_T0_ALARM_HI_M  ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S))
+#define TIMG_T0_ALARM_HI_V  0x3FFFFF
+#define TIMG_T0_ALARM_HI_S  0
+
+#define TIMG_T0LOADLO_REG(i)          (REG_TIMG_BASE(i) + 0x0018)
+/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_T0_LOAD_LO  0xFFFFFFFF
+#define TIMG_T0_LOAD_LO_M  ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S))
+#define TIMG_T0_LOAD_LO_V  0xFFFFFFFF
+#define TIMG_T0_LOAD_LO_S  0
+
+#define TIMG_T0LOADHI_REG(i)          (REG_TIMG_BASE(i) + 0x001c)
+/* TIMG_T0_LOAD_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define TIMG_T0_LOAD_HI  0x003FFFFF
+#define TIMG_T0_LOAD_HI_M  ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S))
+#define TIMG_T0_LOAD_HI_V  0x3FFFFF
+#define TIMG_T0_LOAD_HI_S  0
+
+#define TIMG_T0LOAD_REG(i)          (REG_TIMG_BASE(i) + 0x0020)
+/* TIMG_T0_LOAD : WT ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_T0_LOAD  0xFFFFFFFF
+#define TIMG_T0_LOAD_M  ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S))
+#define TIMG_T0_LOAD_V  0xFFFFFFFF
+#define TIMG_T0_LOAD_S  0
+
+#define TIMG_WDTCONFIG0_REG(i)          (REG_TIMG_BASE(i) + 0x0048)
+/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_WDT_EN  (BIT(31))
+#define TIMG_WDT_EN_M  (BIT(31))
+#define TIMG_WDT_EN_V  0x1
+#define TIMG_WDT_EN_S  31
+/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 2'd0 ; */
+/*description: */
+#define TIMG_WDT_STG0  0x00000003
+#define TIMG_WDT_STG0_M  ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S))
+#define TIMG_WDT_STG0_V  0x3
+#define TIMG_WDT_STG0_S  29
+/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
+/*description: */
+#define TIMG_WDT_STG1  0x00000003
+#define TIMG_WDT_STG1_M  ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S))
+#define TIMG_WDT_STG1_V  0x3
+#define TIMG_WDT_STG1_S  27
+/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 2'd0 ; */
+/*description: */
+#define TIMG_WDT_STG2  0x00000003
+#define TIMG_WDT_STG2_M  ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S))
+#define TIMG_WDT_STG2_V  0x3
+#define TIMG_WDT_STG2_S  25
+/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 2'd0 ; */
+/*description: */
+#define TIMG_WDT_STG3  0x00000003
+#define TIMG_WDT_STG3_M  ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S))
+#define TIMG_WDT_STG3_V  0x3
+#define TIMG_WDT_STG3_S  23
+/* TIMG_WDT_CONF_UPDATE_EN : WT ;bitpos:[22] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_WDT_CONF_UPDATE_EN  (BIT(22))
+#define TIMG_WDT_CONF_UPDATE_EN_M  (BIT(22))
+#define TIMG_WDT_CONF_UPDATE_EN_V  0x1
+#define TIMG_WDT_CONF_UPDATE_EN_S  22
+/* TIMG_WDT_USE_XTAL : R/W ;bitpos:[21] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_WDT_USE_XTAL  (BIT(21))
+#define TIMG_WDT_USE_XTAL_M  (BIT(21))
+#define TIMG_WDT_USE_XTAL_V  0x1
+#define TIMG_WDT_USE_XTAL_S  21
+/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */
+/*description: */
+#define TIMG_WDT_CPU_RESET_LENGTH  0x00000007
+#define TIMG_WDT_CPU_RESET_LENGTH_M  ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S))
+#define TIMG_WDT_CPU_RESET_LENGTH_V  0x7
+#define TIMG_WDT_CPU_RESET_LENGTH_S  18
+/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */
+/*description: */
+#define TIMG_WDT_SYS_RESET_LENGTH  0x00000007
+#define TIMG_WDT_SYS_RESET_LENGTH_M  ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S))
+#define TIMG_WDT_SYS_RESET_LENGTH_V  0x7
+#define TIMG_WDT_SYS_RESET_LENGTH_S  15
+/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
+/*description: */
+#define TIMG_WDT_FLASHBOOT_MOD_EN  (BIT(14))
+#define TIMG_WDT_FLASHBOOT_MOD_EN_M  (BIT(14))
+#define TIMG_WDT_FLASHBOOT_MOD_EN_V  0x1
+#define TIMG_WDT_FLASHBOOT_MOD_EN_S  14
+/* TIMG_WDT_PROCPU_RESET_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: */
+#define TIMG_WDT_PROCPU_RESET_EN  (BIT(13))
+#define TIMG_WDT_PROCPU_RESET_EN_M  (BIT(13))
+#define TIMG_WDT_PROCPU_RESET_EN_V  0x1
+#define TIMG_WDT_PROCPU_RESET_EN_S  13
+/* TIMG_WDT_APPCPU_RESET_EN : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: */
+#define TIMG_WDT_APPCPU_RESET_EN  (BIT(12))
+#define TIMG_WDT_APPCPU_RESET_EN_M  (BIT(12))
+#define TIMG_WDT_APPCPU_RESET_EN_V  0x1
+#define TIMG_WDT_APPCPU_RESET_EN_S  12
+
+#define TIMG_WDTCONFIG1_REG(i)          (REG_TIMG_BASE(i) + 0x004c)
+/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */
+/*description: */
+#define TIMG_WDT_CLK_PRESCALE  0x0000FFFF
+#define TIMG_WDT_CLK_PRESCALE_M  ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S))
+#define TIMG_WDT_CLK_PRESCALE_V  0xFFFF
+#define TIMG_WDT_CLK_PRESCALE_S  16
+/* TIMG_WDT_DIVCNT_RST : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define TIMG_WDT_DIVCNT_RST  (BIT(0))
+#define TIMG_WDT_DIVCNT_RST_M  (BIT(0))
+#define TIMG_WDT_DIVCNT_RST_V  0x1
+#define TIMG_WDT_DIVCNT_RST_S  0
+
+#define TIMG_WDTCONFIG2_REG(i)          (REG_TIMG_BASE(i) + 0x0050)
+/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */
+/*description: */
+#define TIMG_WDT_STG0_HOLD  0xFFFFFFFF
+#define TIMG_WDT_STG0_HOLD_M  ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S))
+#define TIMG_WDT_STG0_HOLD_V  0xFFFFFFFF
+#define TIMG_WDT_STG0_HOLD_S  0
+
+#define TIMG_WDTCONFIG3_REG(i)          (REG_TIMG_BASE(i) + 0x0054)
+/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */
+/*description: */
+#define TIMG_WDT_STG1_HOLD  0xFFFFFFFF
+#define TIMG_WDT_STG1_HOLD_M  ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S))
+#define TIMG_WDT_STG1_HOLD_V  0xFFFFFFFF
+#define TIMG_WDT_STG1_HOLD_S  0
+
+#define TIMG_WDTCONFIG4_REG(i)          (REG_TIMG_BASE(i) + 0x0058)
+/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
+/*description: */
+#define TIMG_WDT_STG2_HOLD  0xFFFFFFFF
+#define TIMG_WDT_STG2_HOLD_M  ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S))
+#define TIMG_WDT_STG2_HOLD_V  0xFFFFFFFF
+#define TIMG_WDT_STG2_HOLD_S  0
+
+#define TIMG_WDTCONFIG5_REG(i)          (REG_TIMG_BASE(i) + 0x005c)
+/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
+/*description: */
+#define TIMG_WDT_STG3_HOLD  0xFFFFFFFF
+#define TIMG_WDT_STG3_HOLD_M  ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S))
+#define TIMG_WDT_STG3_HOLD_V  0xFFFFFFFF
+#define TIMG_WDT_STG3_HOLD_S  0
+
+#define TIMG_WDTFEED_REG(i)          (REG_TIMG_BASE(i) + 0x0060)
+/* TIMG_WDT_FEED : WT ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_WDT_FEED  0xFFFFFFFF
+#define TIMG_WDT_FEED_M  ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S))
+#define TIMG_WDT_FEED_V  0xFFFFFFFF
+#define TIMG_WDT_FEED_S  0
+
+#define TIMG_WDTWPROTECT_REG(i)          (REG_TIMG_BASE(i) + 0x0064)
+/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
+/*description: */
+#define TIMG_WDT_WKEY  0xFFFFFFFF
+#define TIMG_WDT_WKEY_M  ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S))
+#define TIMG_WDT_WKEY_V  0xFFFFFFFF
+#define TIMG_WDT_WKEY_S  0
+
+#define TIMG_RTCCALICFG_REG(i)          (REG_TIMG_BASE(i) + 0x0068)
+/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_RTC_CALI_START  (BIT(31))
+#define TIMG_RTC_CALI_START_M  (BIT(31))
+#define TIMG_RTC_CALI_START_V  0x1
+#define TIMG_RTC_CALI_START_S  31
+/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */
+/*description: */
+#define TIMG_RTC_CALI_MAX  0x00007FFF
+#define TIMG_RTC_CALI_MAX_M  ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S))
+#define TIMG_RTC_CALI_MAX_V  0x7FFF
+#define TIMG_RTC_CALI_MAX_S  16
+/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_RTC_CALI_RDY  (BIT(15))
+#define TIMG_RTC_CALI_RDY_M  (BIT(15))
+#define TIMG_RTC_CALI_RDY_V  0x1
+#define TIMG_RTC_CALI_RDY_S  15
+/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */
+/*description: */
+#define TIMG_RTC_CALI_CLK_SEL  0x00000003
+#define TIMG_RTC_CALI_CLK_SEL_M  ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S))
+#define TIMG_RTC_CALI_CLK_SEL_V  0x3
+#define TIMG_RTC_CALI_CLK_SEL_S  13
+/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */
+/*description: */
+#define TIMG_RTC_CALI_START_CYCLING  (BIT(12))
+#define TIMG_RTC_CALI_START_CYCLING_M  (BIT(12))
+#define TIMG_RTC_CALI_START_CYCLING_V  0x1
+#define TIMG_RTC_CALI_START_CYCLING_S  12
+
+#define TIMG_RTCCALICFG1_REG(i)          (REG_TIMG_BASE(i) + 0x006c)
+/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */
+/*description: */
+#define TIMG_RTC_CALI_VALUE  0x01FFFFFF
+#define TIMG_RTC_CALI_VALUE_M  ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S))
+#define TIMG_RTC_CALI_VALUE_V  0x1FFFFFF
+#define TIMG_RTC_CALI_VALUE_S  7
+/* TIMG_RTC_CALI_CYCLING_DATA_VLD : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD  (BIT(0))
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M  (BIT(0))
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V  0x1
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S  0
+
+#define TIMG_INT_ENA_TIMERS_REG(i)          (REG_TIMG_BASE(i) + 0x0070)
+/* TIMG_WDT_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_WDT_INT_ENA  (BIT(1))
+#define TIMG_WDT_INT_ENA_M  (BIT(1))
+#define TIMG_WDT_INT_ENA_V  0x1
+#define TIMG_WDT_INT_ENA_S  1
+/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T0_INT_ENA  (BIT(0))
+#define TIMG_T0_INT_ENA_M  (BIT(0))
+#define TIMG_T0_INT_ENA_V  0x1
+#define TIMG_T0_INT_ENA_S  0
+
+#define TIMG_INT_RAW_TIMERS_REG(i)          (REG_TIMG_BASE(i) + 0x0074)
+/* TIMG_WDT_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_WDT_INT_RAW  (BIT(1))
+#define TIMG_WDT_INT_RAW_M  (BIT(1))
+#define TIMG_WDT_INT_RAW_V  0x1
+#define TIMG_WDT_INT_RAW_S  1
+/* TIMG_T0_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T0_INT_RAW  (BIT(0))
+#define TIMG_T0_INT_RAW_M  (BIT(0))
+#define TIMG_T0_INT_RAW_V  0x1
+#define TIMG_T0_INT_RAW_S  0
+
+#define TIMG_INT_ST_TIMERS_REG(i)          (REG_TIMG_BASE(i) + 0x0078)
+/* TIMG_WDT_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_WDT_INT_ST  (BIT(1))
+#define TIMG_WDT_INT_ST_M  (BIT(1))
+#define TIMG_WDT_INT_ST_V  0x1
+#define TIMG_WDT_INT_ST_S  1
+/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T0_INT_ST  (BIT(0))
+#define TIMG_T0_INT_ST_M  (BIT(0))
+#define TIMG_T0_INT_ST_V  0x1
+#define TIMG_T0_INT_ST_S  0
+
+#define TIMG_INT_CLR_TIMERS_REG(i)          (REG_TIMG_BASE(i) + 0x007c)
+/* TIMG_WDT_INT_CLR : WT ;bitpos:[1] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_WDT_INT_CLR  (BIT(1))
+#define TIMG_WDT_INT_CLR_M  (BIT(1))
+#define TIMG_WDT_INT_CLR_V  0x1
+#define TIMG_WDT_INT_CLR_S  1
+/* TIMG_T0_INT_CLR : WT ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T0_INT_CLR  (BIT(0))
+#define TIMG_T0_INT_CLR_M  (BIT(0))
+#define TIMG_T0_INT_CLR_V  0x1
+#define TIMG_T0_INT_CLR_S  0
+
+#define TIMG_RTCCALICFG2_REG(i)          (REG_TIMG_BASE(i) + 0x0080)
+/* TIMG_RTC_CALI_TIMEOUT_THRES : R/W ;bitpos:[31:7] ;default: 25'h1ffffff ; */
+/*description: timeout if cali value counts over threshold*/
+#define TIMG_RTC_CALI_TIMEOUT_THRES  0x01FFFFFF
+#define TIMG_RTC_CALI_TIMEOUT_THRES_M  ((TIMG_RTC_CALI_TIMEOUT_THRES_V)<<(TIMG_RTC_CALI_TIMEOUT_THRES_S))
+#define TIMG_RTC_CALI_TIMEOUT_THRES_V  0x1FFFFFF
+#define TIMG_RTC_CALI_TIMEOUT_THRES_S  7
+/* TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W ;bitpos:[6:3] ;default: 4'd3 ; */
+/*description: Cycles that release calibration timeout reset*/
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT  0x0000000F
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M  ((TIMG_RTC_CALI_TIMEOUT_RST_CNT_V)<<(TIMG_RTC_CALI_TIMEOUT_RST_CNT_S))
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V  0xF
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S  3
+/* TIMG_RTC_CALI_TIMEOUT : RO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: timeout indicator*/
+#define TIMG_RTC_CALI_TIMEOUT  (BIT(0))
+#define TIMG_RTC_CALI_TIMEOUT_M  (BIT(0))
+#define TIMG_RTC_CALI_TIMEOUT_V  0x1
+#define TIMG_RTC_CALI_TIMEOUT_S  0
+
+#define TIMG_NTIMERS_DATE_REG(i)          (REG_TIMG_BASE(i) + 0x00f8)
+/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006191 ; */
+/*description: */
+#define TIMG_NTIMERS_DATE  0x0FFFFFFF
+#define TIMG_NTIMERS_DATE_M  ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S))
+#define TIMG_NTIMERS_DATE_V  0xFFFFFFF
+#define TIMG_NTIMERS_DATE_S  0
+
+#define TIMG_CLK_REG(i)          (REG_TIMG_BASE(i) + 0x00fc)
+/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_CLK_EN  (BIT(31))
+#define TIMG_CLK_EN_M  (BIT(31))
+#define TIMG_CLK_EN_V  0x1
+#define TIMG_CLK_EN_S  31
+/* TIMG_TIMER_CLK_IS_ACTIVE : R/W ;bitpos:[30] ;default: 1'h1 ; */
+/*description: */
+#define TIMG_TIMER_CLK_IS_ACTIVE  (BIT(30))
+#define TIMG_TIMER_CLK_IS_ACTIVE_M  (BIT(30))
+#define TIMG_TIMER_CLK_IS_ACTIVE_V  0x1
+#define TIMG_TIMER_CLK_IS_ACTIVE_S  30
+/* TIMG_WDT_CLK_IS_ACTIVE : R/W ;bitpos:[29] ;default: 1'h1 ; */
+/*description: */
+#define TIMG_WDT_CLK_IS_ACTIVE  (BIT(29))
+#define TIMG_WDT_CLK_IS_ACTIVE_M  (BIT(29))
+#define TIMG_WDT_CLK_IS_ACTIVE_V  0x1
+#define TIMG_WDT_CLK_IS_ACTIVE_S  29
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_TIMG_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/timer_group_struct.h b/components/soc/esp32c3/include/soc/timer_group_struct.h
new file mode 100644
index 0000000000..e69f1fe777
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/timer_group_struct.h
@@ -0,0 +1,222 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_TIMG_STRUCT_H_
+#define _SOC_TIMG_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    struct {
+        union {
+            struct {
+                uint32_t reserved0:     9;
+                uint32_t use_xtal:      1;
+                uint32_t alarm_en:      1;
+                uint32_t reserved11:    1;
+                uint32_t divcnt_rst:    1;
+                uint32_t divider:      16;
+                uint32_t autoreload:    1;
+                uint32_t increase:      1;
+                uint32_t enable:        1;
+            };
+            uint32_t val;
+        } config;
+        uint32_t cnt_low;                                      /**/
+        union {
+            struct {
+                uint32_t hi:        22;
+                uint32_t reserved22:10;
+            };
+            uint32_t val;
+        } cnt_high;
+        union {
+            struct {
+                uint32_t reserved0: 31;
+                uint32_t update:     1;
+            };
+            uint32_t val;
+        } update;
+        uint32_t alarm_low;                                 /**/
+        union {
+            struct {
+                uint32_t alarm_hi:   22;
+                uint32_t reserved22: 10;
+            };
+            uint32_t val;
+        } alarm_high;
+        uint32_t load_low;                                  /**/
+        union {
+            struct {
+                uint32_t load_hi:   22;
+                uint32_t reserved22:10;
+            };
+            uint32_t val;
+        } load_high;
+        uint32_t reload;                                    /**/
+    } hw_timer[1];
+    uint32_t reserved_24;
+    uint32_t reserved_28;
+    uint32_t reserved_2c;
+    uint32_t reserved_30;
+    uint32_t reserved_34;
+    uint32_t reserved_38;
+    uint32_t reserved_3c;
+    uint32_t reserved_40;
+    uint32_t reserved_44;
+    union {
+        struct {
+            uint32_t reserved0:           12;
+            uint32_t appcpu_reset_en:      1;
+            uint32_t procpu_reset_en:      1;
+            uint32_t flashboot_mod_en:     1;
+            uint32_t sys_reset_length:     3;
+            uint32_t cpu_reset_length:     3;
+            uint32_t use_xtal:             1;
+            uint32_t conf_update_en:       1;
+            uint32_t stg3:                 2;
+            uint32_t stg2:                 2;
+            uint32_t stg1:                 2;
+            uint32_t stg0:                 2;
+            uint32_t en:                   1;
+        };
+        uint32_t val;
+    } wdt_config0;
+    union {
+        struct {
+            uint32_t divcnt_rst:       1;
+            uint32_t reserved1:       15;
+            uint32_t clk_prescale:    16;
+        };
+        uint32_t val;
+    } wdt_config1;
+    uint32_t wdt_config2;                                /**/
+    uint32_t wdt_config3;                                /**/
+    uint32_t wdt_config4;                                /**/
+    uint32_t wdt_config5;                                /**/
+    uint32_t wdt_feed;                                   /**/
+    uint32_t wdt_wprotect;                               /**/
+    union {
+        struct {
+            uint32_t reserved0:             12;
+            uint32_t start_cycling:          1;
+            uint32_t clk_sel:                2;
+            uint32_t rdy:                    1;
+            uint32_t max:                   15;
+            uint32_t start:                  1;
+        };
+        uint32_t val;
+    } rtc_cali_cfg;
+    union {
+        struct {
+            uint32_t cycling_data_vld:          1;
+            uint32_t reserved1:                 6;
+            uint32_t value:                    25;
+        };
+        uint32_t val;
+    } rtc_cali_cfg1;
+    union {
+        struct {
+            uint32_t t0:          1;
+            uint32_t wdt:         1;
+            uint32_t reserved2:  30;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t t0:          1;
+            uint32_t wdt:         1;
+            uint32_t reserved2:  30;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t t0:         1;
+            uint32_t wdt:        1;
+            uint32_t reserved2: 30;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t t0:          1;
+            uint32_t wdt:         1;
+            uint32_t reserved2:  30;
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t timeout:                  1;       /*timeout indicator*/
+            uint32_t reserved1:                2;
+            uint32_t timeout_rst_cnt:          4;       /*Cycles that release calibration timeout reset*/
+            uint32_t timeout_thres:           25;       /*timeout if cali value counts over threshold*/
+        };
+        uint32_t val;
+    } rtc_cali_cfg2;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    union {
+        struct {
+            uint32_t date:        28;
+            uint32_t reserved28:   4;
+        };
+        uint32_t val;
+    } timg_date;
+    union {
+        struct {
+            uint32_t reserved0:          29;
+            uint32_t clk_is_active:       1;
+            uint32_t timer_clk_is_active: 1;
+            uint32_t en:                  1;
+        };
+        uint32_t val;
+    } clk;
+} timg_dev_t;
+extern timg_dev_t TIMERG0;
+extern timg_dev_t TIMERG1;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_TIMG_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/uart_caps.h b/components/soc/esp32c3/include/soc/uart_caps.h
new file mode 100644
index 0000000000..ebd3252b7b
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/uart_caps.h
@@ -0,0 +1,30 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SOC_UART_FIFO_LEN          (128)      /*!< The UART hardware FIFO length */
+#define SOC_UART_BITRATE_MAX       (5000000)  /*!< Max bit rate supported by UART */
+
+// ESP32-C3 have 2 UART
+#define SOC_UART_NUM           (2)
+#define SOC_UART_MIN_WAKEUP_THRESH (2)
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/include/soc/uart_channel.h b/components/soc/esp32c3/include/soc/uart_channel.h
new file mode 100644
index 0000000000..855728262e
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/uart_channel.h
@@ -0,0 +1,61 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_UART_CHANNEL_H
+#define _SOC_UART_CHANNEL_H
+
+//UART channels
+#define UART_GPIO1_DIRECT_CHANNEL       UART_NUM_0
+#define UART_NUM_0_TXD_DIRECT_GPIO_NUM  1
+#define UART_GPIO3_DIRECT_CHANNEL       UART_NUM_0
+#define UART_NUM_0_RXD_DIRECT_GPIO_NUM  3
+#define UART_GPIO19_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_CTS_DIRECT_GPIO_NUM  19
+#define UART_GPIO22_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_RTS_DIRECT_GPIO_NUM  22
+
+#define UART_TXD_GPIO1_DIRECT_CHANNEL   UART_GPIO1_DIRECT_CHANNEL
+#define UART_RXD_GPIO3_DIRECT_CHANNEL   UART_GPIO3_DIRECT_CHANNEL
+#define UART_CTS_GPIO19_DIRECT_CHANNEL  UART_GPIO19_DIRECT_CHANNEL
+#define UART_RTS_GPIO22_DIRECT_CHANNEL  UART_GPIO22_DIRECT_CHANNEL
+
+#define UART_GPIO10_DIRECT_CHANNEL      UART_NUM_1
+#define UART_NUM_1_TXD_DIRECT_GPIO_NUM  10
+#define UART_GPIO9_DIRECT_CHANNEL       UART_NUM_1
+#define UART_NUM_1_RXD_DIRECT_GPIO_NUM  9
+#define UART_GPIO6_DIRECT_CHANNEL       UART_NUM_1
+#define UART_NUM_1_CTS_DIRECT_GPIO_NUM  6
+#define UART_GPIO11_DIRECT_CHANNEL      UART_NUM_1
+#define UART_NUM_1_RTS_DIRECT_GPIO_NUM  11
+
+#define UART_TXD_GPIO10_DIRECT_CHANNEL  UART_GPIO10_DIRECT_CHANNEL
+#define UART_RXD_GPIO9_DIRECT_CHANNEL   UART_GPIO9_DIRECT_CHANNEL
+#define UART_CTS_GPIO6_DIRECT_CHANNEL   UART_GPIO6_DIRECT_CHANNEL
+#define UART_RTS_GPIO11_DIRECT_CHANNEL  UART_GPIO11_DIRECT_CHANNEL
+
+#define UART_GPIO17_DIRECT_CHANNEL      UART_NUM_2
+#define UART_NUM_2_TXD_DIRECT_GPIO_NUM  17
+#define UART_GPIO16_DIRECT_CHANNEL      UART_NUM_2
+#define UART_NUM_2_RXD_DIRECT_GPIO_NUM  16
+#define UART_GPIO8_DIRECT_CHANNEL       UART_NUM_2
+#define UART_NUM_2_CTS_DIRECT_GPIO_NUM  8
+#define UART_GPIO7_DIRECT_CHANNEL       UART_NUM_2
+#define UART_NUM_2_RTS_DIRECT_GPIO_NUM  7
+
+#define UART_TXD_GPIO17_DIRECT_CHANNEL  UART_GPIO17_DIRECT_CHANNEL
+#define UART_RXD_GPIO16_DIRECT_CHANNEL  UART_GPIO16_DIRECT_CHANNEL
+#define UART_CTS_GPIO8_DIRECT_CHANNEL   UART_GPIO8_DIRECT_CHANNEL
+#define UART_RTS_GPIO7_DIRECT_CHANNEL   UART_GPIO7_DIRECT_CHANNEL
+
+#endif
diff --git a/components/soc/esp32c3/include/soc/uart_reg.h b/components/soc/esp32c3/include/soc/uart_reg.h
new file mode 100644
index 0000000000..a0d6c72735
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/uart_reg.h
@@ -0,0 +1,1258 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_UART_REG_H_
+#define _SOC_UART_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define UART_FIFO_REG(i)          (REG_UART_BASE(i) + 0x0)
+/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: UART $n accesses FIFO via this register.*/
+#define UART_RXFIFO_RD_BYTE  0x000000FF
+#define UART_RXFIFO_RD_BYTE_M  ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S))
+#define UART_RXFIFO_RD_BYTE_V  0xFF
+#define UART_RXFIFO_RD_BYTE_S  0
+
+#define UART_INT_RAW_REG(i)          (REG_UART_BASE(i) + 0x4)
+/* UART_WAKEUP_INT_RAW : R/WTC/SS ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when input rxd edge
+ changes more times than what reg_active_threshold specifies in light sleeping mode.*/
+#define UART_WAKEUP_INT_RAW  (BIT(19))
+#define UART_WAKEUP_INT_RAW_M  (BIT(19))
+#define UART_WAKEUP_INT_RAW_V  0x1
+#define UART_WAKEUP_INT_RAW_S  19
+/* UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ the configured at_cmd char.*/
+#define UART_AT_CMD_CHAR_DET_INT_RAW  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
+/* UART_RS485_CLASH_INT_RAW : R/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when detects a clash
+ between transmitter and receiver in rs485 mode.*/
+#define UART_RS485_CLASH_INT_RAW  (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_M  (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_V  0x1
+#define UART_RS485_CLASH_INT_RAW_S  17
+/* UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ a data frame error from the echo of transmitter in rs485 mode.*/
+#define UART_RS485_FRM_ERR_INT_RAW  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_V  0x1
+#define UART_RS485_FRM_ERR_INT_RAW_S  16
+/* UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ a parity error from the echo of transmitter in rs485 mode.*/
+#define UART_RS485_PARITY_ERR_INT_RAW  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_V  0x1
+#define UART_RS485_PARITY_ERR_INT_RAW_S  15
+/* UART_TX_DONE_INT_RAW : R/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when transmitter has
+ send out all data in FIFO.*/
+#define UART_TX_DONE_INT_RAW  (BIT(14))
+#define UART_TX_DONE_INT_RAW_M  (BIT(14))
+#define UART_TX_DONE_INT_RAW_V  0x1
+#define UART_TX_DONE_INT_RAW_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when transmitter has
+ kept the shortest duration after sending the  last data.*/
+#define UART_TX_BRK_IDLE_DONE_INT_RAW  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
+/* UART_TX_BRK_DONE_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when transmitter completes
+  sending  NULL characters  after all data in Tx-FIFO are sent.*/
+#define UART_TX_BRK_DONE_INT_RAW  (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_V  0x1
+#define UART_TX_BRK_DONE_INT_RAW_S  12
+/* UART_GLITCH_DET_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ a glitch in the middle of a start bit.*/
+#define UART_GLITCH_DET_INT_RAW  (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_M  (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_V  0x1
+#define UART_GLITCH_DET_INT_RAW_S  11
+/* UART_SW_XOFF_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver receives
+ Xoff char when uart_sw_flow_con_en is set to 1.*/
+#define UART_SW_XOFF_INT_RAW  (BIT(10))
+#define UART_SW_XOFF_INT_RAW_M  (BIT(10))
+#define UART_SW_XOFF_INT_RAW_V  0x1
+#define UART_SW_XOFF_INT_RAW_S  10
+/* UART_SW_XON_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver recevies
+ Xon char when uart_sw_flow_con_en is set to 1.*/
+#define UART_SW_XON_INT_RAW  (BIT(9))
+#define UART_SW_XON_INT_RAW_M  (BIT(9))
+#define UART_SW_XON_INT_RAW_V  0x1
+#define UART_SW_XON_INT_RAW_S  9
+/* UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver takes
+ more time than rx_tout_thrhd to receive a byte.*/
+#define UART_RXFIFO_TOUT_INT_RAW  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_V  0x1
+#define UART_RXFIFO_TOUT_INT_RAW_S  8
+/* UART_BRK_DET_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ a 0 after the stop bit.*/
+#define UART_BRK_DET_INT_RAW  (BIT(7))
+#define UART_BRK_DET_INT_RAW_M  (BIT(7))
+#define UART_BRK_DET_INT_RAW_V  0x1
+#define UART_BRK_DET_INT_RAW_S  7
+/* UART_CTS_CHG_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ the edge change of CTSn signal.*/
+#define UART_CTS_CHG_INT_RAW  (BIT(6))
+#define UART_CTS_CHG_INT_RAW_M  (BIT(6))
+#define UART_CTS_CHG_INT_RAW_V  0x1
+#define UART_CTS_CHG_INT_RAW_S  6
+/* UART_DSR_CHG_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ the edge change of DSRn signal.*/
+#define UART_DSR_CHG_INT_RAW  (BIT(5))
+#define UART_DSR_CHG_INT_RAW_M  (BIT(5))
+#define UART_DSR_CHG_INT_RAW_V  0x1
+#define UART_DSR_CHG_INT_RAW_S  5
+/* UART_RXFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver receives
+ more data than the FIFO can store.*/
+#define UART_RXFIFO_OVF_INT_RAW  (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_V  0x1
+#define UART_RXFIFO_OVF_INT_RAW_S  4
+/* UART_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ a data frame error .*/
+#define UART_FRM_ERR_INT_RAW  (BIT(3))
+#define UART_FRM_ERR_INT_RAW_M  (BIT(3))
+#define UART_FRM_ERR_INT_RAW_V  0x1
+#define UART_FRM_ERR_INT_RAW_S  3
+/* UART_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ a parity error in the data.*/
+#define UART_PARITY_ERR_INT_RAW  (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_M  (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_V  0x1
+#define UART_PARITY_ERR_INT_RAW_S  2
+/* UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b1 ; */
+/*description: This interrupt raw bit turns to high level when the amount of
+ data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .*/
+#define UART_TXFIFO_EMPTY_INT_RAW  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_V  0x1
+#define UART_TXFIFO_EMPTY_INT_RAW_S  1
+/* UART_RXFIFO_FULL_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver receives
+ more data than what rxfifo_full_thrhd specifies.*/
+#define UART_RXFIFO_FULL_INT_RAW  (BIT(0))
+#define UART_RXFIFO_FULL_INT_RAW_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_RAW_V  0x1
+#define UART_RXFIFO_FULL_INT_RAW_S  0
+
+#define UART_INT_ST_REG(i)          (REG_UART_BASE(i) + 0x8)
+/* UART_WAKEUP_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena
+ is set to 1.*/
+#define UART_WAKEUP_INT_ST  (BIT(19))
+#define UART_WAKEUP_INT_ST_M  (BIT(19))
+#define UART_WAKEUP_INT_ST_V  0x1
+#define UART_WAKEUP_INT_ST_S  19
+/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena
+ is set to 1.*/
+#define UART_AT_CMD_CHAR_DET_INT_ST  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
+/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena
+ is set to 1.*/
+#define UART_RS485_CLASH_INT_ST  (BIT(17))
+#define UART_RS485_CLASH_INT_ST_M  (BIT(17))
+#define UART_RS485_CLASH_INT_ST_V  0x1
+#define UART_RS485_CLASH_INT_ST_S  17
+/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena
+ is set to 1.*/
+#define UART_RS485_FRM_ERR_INT_ST  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_V  0x1
+#define UART_RS485_FRM_ERR_INT_ST_S  16
+/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena
+ is set to 1.*/
+#define UART_RS485_PARITY_ERR_INT_ST  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_V  0x1
+#define UART_RS485_PARITY_ERR_INT_ST_S  15
+/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
+#define UART_TX_DONE_INT_ST  (BIT(14))
+#define UART_TX_DONE_INT_ST_M  (BIT(14))
+#define UART_TX_DONE_INT_ST_V  0x1
+#define UART_TX_DONE_INT_ST_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+ is set to 1.*/
+#define UART_TX_BRK_IDLE_DONE_INT_ST  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
+/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena
+ is set to 1.*/
+#define UART_TX_BRK_DONE_INT_ST  (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_V  0x1
+#define UART_TX_BRK_DONE_INT_ST_S  12
+/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena
+ is set to 1.*/
+#define UART_GLITCH_DET_INT_ST  (BIT(11))
+#define UART_GLITCH_DET_INT_ST_M  (BIT(11))
+#define UART_GLITCH_DET_INT_ST_V  0x1
+#define UART_GLITCH_DET_INT_ST_S  11
+/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
+#define UART_SW_XOFF_INT_ST  (BIT(10))
+#define UART_SW_XOFF_INT_ST_M  (BIT(10))
+#define UART_SW_XOFF_INT_ST_V  0x1
+#define UART_SW_XOFF_INT_ST_S  10
+/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
+#define UART_SW_XON_INT_ST  (BIT(9))
+#define UART_SW_XON_INT_ST_M  (BIT(9))
+#define UART_SW_XON_INT_ST_V  0x1
+#define UART_SW_XON_INT_ST_S  9
+/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena
+ is set to 1.*/
+#define UART_RXFIFO_TOUT_INT_ST  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_V  0x1
+#define UART_RXFIFO_TOUT_INT_ST_S  8
+/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
+#define UART_BRK_DET_INT_ST  (BIT(7))
+#define UART_BRK_DET_INT_ST_M  (BIT(7))
+#define UART_BRK_DET_INT_ST_V  0x1
+#define UART_BRK_DET_INT_ST_S  7
+/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
+#define UART_CTS_CHG_INT_ST  (BIT(6))
+#define UART_CTS_CHG_INT_ST_M  (BIT(6))
+#define UART_CTS_CHG_INT_ST_V  0x1
+#define UART_CTS_CHG_INT_ST_S  6
+/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
+#define UART_DSR_CHG_INT_ST  (BIT(5))
+#define UART_DSR_CHG_INT_ST_M  (BIT(5))
+#define UART_DSR_CHG_INT_ST_V  0x1
+#define UART_DSR_CHG_INT_ST_S  5
+/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena
+ is set to 1.*/
+#define UART_RXFIFO_OVF_INT_ST  (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_V  0x1
+#define UART_RXFIFO_OVF_INT_ST_S  4
+/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/
+#define UART_FRM_ERR_INT_ST  (BIT(3))
+#define UART_FRM_ERR_INT_ST_M  (BIT(3))
+#define UART_FRM_ERR_INT_ST_V  0x1
+#define UART_FRM_ERR_INT_ST_S  3
+/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena
+ is set to 1.*/
+#define UART_PARITY_ERR_INT_ST  (BIT(2))
+#define UART_PARITY_ERR_INT_ST_M  (BIT(2))
+#define UART_PARITY_ERR_INT_ST_V  0x1
+#define UART_PARITY_ERR_INT_ST_S  2
+/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena
+ is set to 1.*/
+#define UART_TXFIFO_EMPTY_INT_ST  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_V  0x1
+#define UART_TXFIFO_EMPTY_INT_ST_S  1
+/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena
+ is set to 1.*/
+#define UART_RXFIFO_FULL_INT_ST  (BIT(0))
+#define UART_RXFIFO_FULL_INT_ST_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_ST_V  0x1
+#define UART_RXFIFO_FULL_INT_ST_S  0
+
+#define UART_INT_ENA_REG(i)          (REG_UART_BASE(i) + 0xC)
+/* UART_WAKEUP_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the enable bit for uart_wakeup_int_st register.*/
+#define UART_WAKEUP_INT_ENA  (BIT(19))
+#define UART_WAKEUP_INT_ENA_M  (BIT(19))
+#define UART_WAKEUP_INT_ENA_V  0x1
+#define UART_WAKEUP_INT_ENA_S  19
+/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This is the enable bit for at_cmd_char_det_int_st register.*/
+#define UART_AT_CMD_CHAR_DET_INT_ENA  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
+/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This is the enable bit for rs485_clash_int_st register.*/
+#define UART_RS485_CLASH_INT_ENA  (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_M  (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_V  0x1
+#define UART_RS485_CLASH_INT_ENA_S  17
+/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This is the enable bit for rs485_parity_err_int_st register.*/
+#define UART_RS485_FRM_ERR_INT_ENA  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_V  0x1
+#define UART_RS485_FRM_ERR_INT_ENA_S  16
+/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for rs485_parity_err_int_st register.*/
+#define UART_RS485_PARITY_ERR_INT_ENA  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_V  0x1
+#define UART_RS485_PARITY_ERR_INT_ENA_S  15
+/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for tx_done_int_st register.*/
+#define UART_TX_DONE_INT_ENA  (BIT(14))
+#define UART_TX_DONE_INT_ENA_M  (BIT(14))
+#define UART_TX_DONE_INT_ENA_V  0x1
+#define UART_TX_DONE_INT_ENA_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: This is the enable bit for tx_brk_idle_done_int_st register.*/
+#define UART_TX_BRK_IDLE_DONE_INT_ENA  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
+/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: This is the enable bit for tx_brk_done_int_st register.*/
+#define UART_TX_BRK_DONE_INT_ENA  (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_V  0x1
+#define UART_TX_BRK_DONE_INT_ENA_S  12
+/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: This is the enable bit for glitch_det_int_st register.*/
+#define UART_GLITCH_DET_INT_ENA  (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_M  (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_V  0x1
+#define UART_GLITCH_DET_INT_ENA_S  11
+/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This is the enable bit for sw_xoff_int_st register.*/
+#define UART_SW_XOFF_INT_ENA  (BIT(10))
+#define UART_SW_XOFF_INT_ENA_M  (BIT(10))
+#define UART_SW_XOFF_INT_ENA_V  0x1
+#define UART_SW_XOFF_INT_ENA_S  10
+/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: This is the enable bit for sw_xon_int_st register.*/
+#define UART_SW_XON_INT_ENA  (BIT(9))
+#define UART_SW_XON_INT_ENA_M  (BIT(9))
+#define UART_SW_XON_INT_ENA_V  0x1
+#define UART_SW_XON_INT_ENA_S  9
+/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: This is the enable bit for rxfifo_tout_int_st register.*/
+#define UART_RXFIFO_TOUT_INT_ENA  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_V  0x1
+#define UART_RXFIFO_TOUT_INT_ENA_S  8
+/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the enable bit for brk_det_int_st register.*/
+#define UART_BRK_DET_INT_ENA  (BIT(7))
+#define UART_BRK_DET_INT_ENA_M  (BIT(7))
+#define UART_BRK_DET_INT_ENA_V  0x1
+#define UART_BRK_DET_INT_ENA_S  7
+/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This is the enable bit for cts_chg_int_st register.*/
+#define UART_CTS_CHG_INT_ENA  (BIT(6))
+#define UART_CTS_CHG_INT_ENA_M  (BIT(6))
+#define UART_CTS_CHG_INT_ENA_V  0x1
+#define UART_CTS_CHG_INT_ENA_S  6
+/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This is the enable bit for dsr_chg_int_st register.*/
+#define UART_DSR_CHG_INT_ENA  (BIT(5))
+#define UART_DSR_CHG_INT_ENA_M  (BIT(5))
+#define UART_DSR_CHG_INT_ENA_V  0x1
+#define UART_DSR_CHG_INT_ENA_S  5
+/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This is the enable bit for rxfifo_ovf_int_st register.*/
+#define UART_RXFIFO_OVF_INT_ENA  (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_V  0x1
+#define UART_RXFIFO_OVF_INT_ENA_S  4
+/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This is the enable bit for frm_err_int_st register.*/
+#define UART_FRM_ERR_INT_ENA  (BIT(3))
+#define UART_FRM_ERR_INT_ENA_M  (BIT(3))
+#define UART_FRM_ERR_INT_ENA_V  0x1
+#define UART_FRM_ERR_INT_ENA_S  3
+/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the enable bit for parity_err_int_st register.*/
+#define UART_PARITY_ERR_INT_ENA  (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_M  (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_V  0x1
+#define UART_PARITY_ERR_INT_ENA_S  2
+/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: This is the enable bit for txfifo_empty_int_st register.*/
+#define UART_TXFIFO_EMPTY_INT_ENA  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_V  0x1
+#define UART_TXFIFO_EMPTY_INT_ENA_S  1
+/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This is the enable bit for rxfifo_full_int_st register.*/
+#define UART_RXFIFO_FULL_INT_ENA  (BIT(0))
+#define UART_RXFIFO_FULL_INT_ENA_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_ENA_V  0x1
+#define UART_RXFIFO_FULL_INT_ENA_S  0
+
+#define UART_INT_CLR_REG(i)          (REG_UART_BASE(i) + 0x10)
+/* UART_WAKEUP_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Set this bit to clear the uart_wakeup_int_raw interrupt.*/
+#define UART_WAKEUP_INT_CLR  (BIT(19))
+#define UART_WAKEUP_INT_CLR_M  (BIT(19))
+#define UART_WAKEUP_INT_CLR_V  0x1
+#define UART_WAKEUP_INT_CLR_S  19
+/* UART_AT_CMD_CHAR_DET_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
+#define UART_AT_CMD_CHAR_DET_INT_CLR  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
+/* UART_RS485_CLASH_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rs485_clash_int_raw interrupt.*/
+#define UART_RS485_CLASH_INT_CLR  (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_M  (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_V  0x1
+#define UART_RS485_CLASH_INT_CLR_S  17
+/* UART_RS485_FRM_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
+#define UART_RS485_FRM_ERR_INT_CLR  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_V  0x1
+#define UART_RS485_FRM_ERR_INT_CLR_S  16
+/* UART_RS485_PARITY_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
+#define UART_RS485_PARITY_ERR_INT_CLR  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_V  0x1
+#define UART_RS485_PARITY_ERR_INT_CLR_S  15
+/* UART_TX_DONE_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to clear the tx_done_int_raw interrupt.*/
+#define UART_TX_DONE_INT_CLR  (BIT(14))
+#define UART_TX_DONE_INT_CLR_M  (BIT(14))
+#define UART_TX_DONE_INT_CLR_V  0x1
+#define UART_TX_DONE_INT_CLR_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
+#define UART_TX_BRK_IDLE_DONE_INT_CLR  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
+/* UART_TX_BRK_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to clear the tx_brk_done_int_raw interrupt..*/
+#define UART_TX_BRK_DONE_INT_CLR  (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_V  0x1
+#define UART_TX_BRK_DONE_INT_CLR_S  12
+/* UART_GLITCH_DET_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to clear the glitch_det_int_raw interrupt.*/
+#define UART_GLITCH_DET_INT_CLR  (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_M  (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_V  0x1
+#define UART_GLITCH_DET_INT_CLR_S  11
+/* UART_SW_XOFF_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to clear the sw_xoff_int_raw interrupt.*/
+#define UART_SW_XOFF_INT_CLR  (BIT(10))
+#define UART_SW_XOFF_INT_CLR_M  (BIT(10))
+#define UART_SW_XOFF_INT_CLR_V  0x1
+#define UART_SW_XOFF_INT_CLR_S  10
+/* UART_SW_XON_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/
+#define UART_SW_XON_INT_CLR  (BIT(9))
+#define UART_SW_XON_INT_CLR_M  (BIT(9))
+#define UART_SW_XON_INT_CLR_V  0x1
+#define UART_SW_XON_INT_CLR_S  9
+/* UART_RXFIFO_TOUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
+#define UART_RXFIFO_TOUT_INT_CLR  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_V  0x1
+#define UART_RXFIFO_TOUT_INT_CLR_S  8
+/* UART_BRK_DET_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to clear the brk_det_int_raw interrupt.*/
+#define UART_BRK_DET_INT_CLR  (BIT(7))
+#define UART_BRK_DET_INT_CLR_M  (BIT(7))
+#define UART_BRK_DET_INT_CLR_V  0x1
+#define UART_BRK_DET_INT_CLR_S  7
+/* UART_CTS_CHG_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to clear the cts_chg_int_raw interrupt.*/
+#define UART_CTS_CHG_INT_CLR  (BIT(6))
+#define UART_CTS_CHG_INT_CLR_M  (BIT(6))
+#define UART_CTS_CHG_INT_CLR_V  0x1
+#define UART_CTS_CHG_INT_CLR_S  6
+/* UART_DSR_CHG_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to clear the dsr_chg_int_raw interrupt.*/
+#define UART_DSR_CHG_INT_CLR  (BIT(5))
+#define UART_DSR_CHG_INT_CLR_M  (BIT(5))
+#define UART_DSR_CHG_INT_CLR_V  0x1
+#define UART_DSR_CHG_INT_CLR_S  5
+/* UART_RXFIFO_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
+#define UART_RXFIFO_OVF_INT_CLR  (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_V  0x1
+#define UART_RXFIFO_OVF_INT_CLR_S  4
+/* UART_FRM_ERR_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear frm_err_int_raw interrupt.*/
+#define UART_FRM_ERR_INT_CLR  (BIT(3))
+#define UART_FRM_ERR_INT_CLR_M  (BIT(3))
+#define UART_FRM_ERR_INT_CLR_V  0x1
+#define UART_FRM_ERR_INT_CLR_S  3
+/* UART_PARITY_ERR_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear parity_err_int_raw interrupt.*/
+#define UART_PARITY_ERR_INT_CLR  (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_M  (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_V  0x1
+#define UART_PARITY_ERR_INT_CLR_S  2
+/* UART_TXFIFO_EMPTY_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear txfifo_empty_int_raw interrupt.*/
+#define UART_TXFIFO_EMPTY_INT_CLR  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_V  0x1
+#define UART_TXFIFO_EMPTY_INT_CLR_S  1
+/* UART_RXFIFO_FULL_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rxfifo_full_int_raw interrupt.*/
+#define UART_RXFIFO_FULL_INT_CLR  (BIT(0))
+#define UART_RXFIFO_FULL_INT_CLR_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_CLR_V  0x1
+#define UART_RXFIFO_FULL_INT_CLR_S  0
+
+#define UART_CLKDIV_REG(i)          (REG_UART_BASE(i) + 0x14)
+/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */
+/*description: The decimal part of the frequency divider factor.*/
+#define UART_CLKDIV_FRAG  0x0000000F
+#define UART_CLKDIV_FRAG_M  ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S))
+#define UART_CLKDIV_FRAG_V  0xF
+#define UART_CLKDIV_FRAG_S  20
+/* UART_CLKDIV : R/W ;bitpos:[11:0] ;default: 12'h2B6 ; */
+/*description: The integral part of the frequency divider factor.*/
+#define UART_CLKDIV  0x00000FFF
+#define UART_CLKDIV_M  ((UART_CLKDIV_V)<<(UART_CLKDIV_S))
+#define UART_CLKDIV_V  0xFFF
+#define UART_CLKDIV_S  0
+
+#define UART_RX_FILT_REG(i)          (REG_UART_BASE(i) + 0x18)
+/* UART_GLITCH_FILT_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to enable Rx signal filter.*/
+#define UART_GLITCH_FILT_EN  (BIT(8))
+#define UART_GLITCH_FILT_EN_M  (BIT(8))
+#define UART_GLITCH_FILT_EN_V  0x1
+#define UART_GLITCH_FILT_EN_S  8
+/* UART_GLITCH_FILT : R/W ;bitpos:[7:0] ;default: 8'h8 ; */
+/*description: when input pulse width is lower than this value  the pulse is ignored.*/
+#define UART_GLITCH_FILT  0x000000FF
+#define UART_GLITCH_FILT_M  ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S))
+#define UART_GLITCH_FILT_V  0xFF
+#define UART_GLITCH_FILT_S  0
+
+#define UART_STATUS_REG(i)          (REG_UART_BASE(i) + 0x1C)
+/* UART_TXD : RO ;bitpos:[31] ;default: 1'h1 ; */
+/*description: This bit represents the  level of the internal uart txd signal.*/
+#define UART_TXD  (BIT(31))
+#define UART_TXD_M  (BIT(31))
+#define UART_TXD_V  0x1
+#define UART_TXD_S  31
+/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This bit represents the level of the internal uart rts signal.*/
+#define UART_RTSN  (BIT(30))
+#define UART_RTSN_M  (BIT(30))
+#define UART_RTSN_V  0x1
+#define UART_RTSN_S  30
+/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit represents the level of the internal uart dtr signal.*/
+#define UART_DTRN  (BIT(29))
+#define UART_DTRN_M  (BIT(29))
+#define UART_DTRN_V  0x1
+#define UART_DTRN_S  29
+/* UART_TXFIFO_CNT : RO ;bitpos:[25:16] ;default: 10'b0 ; */
+/*description: Stores the byte number of data in Tx-FIFO.*/
+#define UART_TXFIFO_CNT  0x000003FF
+#define UART_TXFIFO_CNT_M  ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S))
+#define UART_TXFIFO_CNT_V  0x3FF
+#define UART_TXFIFO_CNT_S  16
+/* UART_RXD : RO ;bitpos:[15] ;default: 1'b1 ; */
+/*description: This register represent the  level value of the internal uart rxd signal.*/
+#define UART_RXD  (BIT(15))
+#define UART_RXD_M  (BIT(15))
+#define UART_RXD_V  0x1
+#define UART_RXD_S  15
+/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b1 ; */
+/*description: This register represent the level value of the internal uart cts signal.*/
+#define UART_CTSN  (BIT(14))
+#define UART_CTSN_M  (BIT(14))
+#define UART_CTSN_V  0x1
+#define UART_CTSN_S  14
+/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The register represent the level value of the internal uart dsr signal.*/
+#define UART_DSRN  (BIT(13))
+#define UART_DSRN_M  (BIT(13))
+#define UART_DSRN_V  0x1
+#define UART_DSRN_S  13
+/* UART_RXFIFO_CNT : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: Stores the byte number of valid data in Rx-FIFO.*/
+#define UART_RXFIFO_CNT  0x000003FF
+#define UART_RXFIFO_CNT_M  ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S))
+#define UART_RXFIFO_CNT_V  0x3FF
+#define UART_RXFIFO_CNT_S  0
+
+#define UART_CONF0_REG(i)          (REG_UART_BASE(i) + 0x20)
+/* UART_MEM_CLK_EN : R/W ;bitpos:[28] ;default: 1'h1 ; */
+/*description: UART memory clock gate enable signal.*/
+#define UART_MEM_CLK_EN  (BIT(28))
+#define UART_MEM_CLK_EN_M  (BIT(28))
+#define UART_MEM_CLK_EN_V  0x1
+#define UART_MEM_CLK_EN_S  28
+/* UART_AUTOBAUD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: This is the enable bit for detecting baudrate.*/
+#define UART_AUTOBAUD_EN  (BIT(27))
+#define UART_AUTOBAUD_EN_M  (BIT(27))
+#define UART_AUTOBAUD_EN_V  0x1
+#define UART_AUTOBAUD_EN_S  27
+/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: 1'h1: Receiver stops storing data into FIFO when data is wrong.
+ 1'h0: Receiver stores the data even if the  received data is wrong.*/
+#define UART_ERR_WR_MASK  (BIT(26))
+#define UART_ERR_WR_MASK_M  (BIT(26))
+#define UART_ERR_WR_MASK_V  0x1
+#define UART_ERR_WR_MASK_S  26
+/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */
+/*description: 1'h1: Force clock on for register. 1'h0: Support clock only when
+ application writes registers.*/
+#define UART_CLK_EN  (BIT(25))
+#define UART_CLK_EN_M  (BIT(25))
+#define UART_CLK_EN_V  0x1
+#define UART_CLK_EN_S  25
+/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart dtr signal.*/
+#define UART_DTR_INV  (BIT(24))
+#define UART_DTR_INV_M  (BIT(24))
+#define UART_DTR_INV_V  0x1
+#define UART_DTR_INV_S  24
+/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart rts signal.*/
+#define UART_RTS_INV  (BIT(23))
+#define UART_RTS_INV_M  (BIT(23))
+#define UART_RTS_INV_V  0x1
+#define UART_RTS_INV_S  23
+/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart txd signal.*/
+#define UART_TXD_INV  (BIT(22))
+#define UART_TXD_INV_M  (BIT(22))
+#define UART_TXD_INV_V  0x1
+#define UART_TXD_INV_S  22
+/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart dsr signal.*/
+#define UART_DSR_INV  (BIT(21))
+#define UART_DSR_INV_M  (BIT(21))
+#define UART_DSR_INV_V  0x1
+#define UART_DSR_INV_S  21
+/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart cts signal.*/
+#define UART_CTS_INV  (BIT(20))
+#define UART_CTS_INV_M  (BIT(20))
+#define UART_CTS_INV_V  0x1
+#define UART_CTS_INV_S  20
+/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart rxd signal.*/
+#define UART_RXD_INV  (BIT(19))
+#define UART_RXD_INV_M  (BIT(19))
+#define UART_RXD_INV_V  0x1
+#define UART_RXD_INV_S  19
+/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */
+/*description: Set this bit to reset the uart transmit-FIFO.*/
+#define UART_TXFIFO_RST  (BIT(18))
+#define UART_TXFIFO_RST_M  (BIT(18))
+#define UART_TXFIFO_RST_V  0x1
+#define UART_TXFIFO_RST_S  18
+/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: Set this bit to reset the uart receive-FIFO.*/
+#define UART_RXFIFO_RST  (BIT(17))
+#define UART_RXFIFO_RST_M  (BIT(17))
+#define UART_RXFIFO_RST_V  0x1
+#define UART_RXFIFO_RST_S  17
+/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: Set this bit to enable IrDA protocol.*/
+#define UART_IRDA_EN  (BIT(16))
+#define UART_IRDA_EN_M  (BIT(16))
+#define UART_IRDA_EN_V  0x1
+#define UART_IRDA_EN_S  16
+/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to enable flow control function for transmitter.*/
+#define UART_TX_FLOW_EN  (BIT(15))
+#define UART_TX_FLOW_EN_M  (BIT(15))
+#define UART_TX_FLOW_EN_V  0x1
+#define UART_TX_FLOW_EN_S  15
+/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to enable uart loopback test mode.*/
+#define UART_LOOPBACK  (BIT(14))
+#define UART_LOOPBACK_M  (BIT(14))
+#define UART_LOOPBACK_V  0x1
+#define UART_LOOPBACK_S  14
+/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to invert the level of IrDA receiver.*/
+#define UART_IRDA_RX_INV  (BIT(13))
+#define UART_IRDA_RX_INV_M  (BIT(13))
+#define UART_IRDA_RX_INV_V  0x1
+#define UART_IRDA_RX_INV_S  13
+/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to invert the level of  IrDA transmitter.*/
+#define UART_IRDA_TX_INV  (BIT(12))
+#define UART_IRDA_TX_INV_M  (BIT(12))
+#define UART_IRDA_TX_INV_V  0x1
+#define UART_IRDA_TX_INV_S  12
+/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit.
+ 1'h0: Set IrDA transmitter's 11th bit to 0.*/
+#define UART_IRDA_WCTL  (BIT(11))
+#define UART_IRDA_WCTL_M  (BIT(11))
+#define UART_IRDA_WCTL_V  0x1
+#define UART_IRDA_WCTL_S  11
+/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This is the start enable bit for IrDA transmitter.*/
+#define UART_IRDA_TX_EN  (BIT(10))
+#define UART_IRDA_TX_EN_M  (BIT(10))
+#define UART_IRDA_TX_EN_V  0x1
+#define UART_IRDA_TX_EN_S  10
+/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to enable IrDA loopback mode.*/
+#define UART_IRDA_DPLX  (BIT(9))
+#define UART_IRDA_DPLX_M  (BIT(9))
+#define UART_IRDA_DPLX_V  0x1
+#define UART_IRDA_DPLX_S  9
+/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to enbale transmitter to  send NULL when the process
+ of sending data is done.*/
+#define UART_TXD_BRK  (BIT(8))
+#define UART_TXD_BRK_M  (BIT(8))
+#define UART_TXD_BRK_V  0x1
+#define UART_TXD_BRK_S  8
+/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This register is used to configure the software dtr signal which
+ is used in software flow control.*/
+#define UART_SW_DTR  (BIT(7))
+#define UART_SW_DTR_M  (BIT(7))
+#define UART_SW_DTR_V  0x1
+#define UART_SW_DTR_S  7
+/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This register is used to configure the software rts signal which
+ is used in software flow control.*/
+#define UART_SW_RTS  (BIT(6))
+#define UART_SW_RTS_M  (BIT(6))
+#define UART_SW_RTS_V  0x1
+#define UART_SW_RTS_S  6
+/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */
+/*description: This register is used to set the length of  stop bit.*/
+#define UART_STOP_BIT_NUM  0x00000003
+#define UART_STOP_BIT_NUM_M  ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S))
+#define UART_STOP_BIT_NUM_V  0x3
+#define UART_STOP_BIT_NUM_S  4
+/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */
+/*description: This register is used to set the length of data.*/
+#define UART_BIT_NUM  0x00000003
+#define UART_BIT_NUM_M  ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S))
+#define UART_BIT_NUM_V  0x3
+#define UART_BIT_NUM_S  2
+/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to enable uart parity check.*/
+#define UART_PARITY_EN  (BIT(1))
+#define UART_PARITY_EN_M  (BIT(1))
+#define UART_PARITY_EN_V  0x1
+#define UART_PARITY_EN_S  1
+/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This register is used to configure the parity check mode.*/
+#define UART_PARITY  (BIT(0))
+#define UART_PARITY_M  (BIT(0))
+#define UART_PARITY_V  0x1
+#define UART_PARITY_S  0
+
+#define UART_CONF1_REG(i)          (REG_UART_BASE(i) + 0x24)
+/* UART_RX_TOUT_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: This is the enble bit for uart receiver's timeout function.*/
+#define UART_RX_TOUT_EN  (BIT(21))
+#define UART_RX_TOUT_EN_M  (BIT(21))
+#define UART_RX_TOUT_EN_V  0x1
+#define UART_RX_TOUT_EN_S  21
+/* UART_RX_FLOW_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: This is the flow enable bit for UART receiver.*/
+#define UART_RX_FLOW_EN  (BIT(20))
+#define UART_RX_FLOW_EN_M  (BIT(20))
+#define UART_RX_FLOW_EN_V  0x1
+#define UART_RX_FLOW_EN_S  20
+/* UART_RX_TOUT_FLOW_DIS : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Set this bit to stop accumulating idle_cnt when hardware flow control works.*/
+#define UART_RX_TOUT_FLOW_DIS  (BIT(19))
+#define UART_RX_TOUT_FLOW_DIS_M  (BIT(19))
+#define UART_RX_TOUT_FLOW_DIS_V  0x1
+#define UART_RX_TOUT_FLOW_DIS_S  19
+/* UART_DIS_RX_DAT_OVF : R/W ;bitpos:[18] ;default: 1'h0 ; */
+/*description: Disable UART Rx data overflow detect.*/
+#define UART_DIS_RX_DAT_OVF  (BIT(18))
+#define UART_DIS_RX_DAT_OVF_M  (BIT(18))
+#define UART_DIS_RX_DAT_OVF_V  0x1
+#define UART_DIS_RX_DAT_OVF_S  18
+/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[17:9] ;default: 9'h60 ; */
+/*description: It will produce txfifo_empty_int interrupt when the data amount
+ in Tx-FIFO is less than this register value.*/
+#define UART_TXFIFO_EMPTY_THRHD  0x000001FF
+#define UART_TXFIFO_EMPTY_THRHD_M  ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S))
+#define UART_TXFIFO_EMPTY_THRHD_V  0x1FF
+#define UART_TXFIFO_EMPTY_THRHD_S  9
+/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[8:0] ;default: 9'h60 ; */
+/*description: It will produce rxfifo_full_int interrupt when receiver receives
+ more data than this register value.*/
+#define UART_RXFIFO_FULL_THRHD  0x000001FF
+#define UART_RXFIFO_FULL_THRHD_M  ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S))
+#define UART_RXFIFO_FULL_THRHD_V  0x1FF
+#define UART_RXFIFO_FULL_THRHD_S  0
+
+#define UART_LOWPULSE_REG(i)          (REG_UART_BASE(i) + 0x28)
+/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */
+/*description: This register stores the value of the minimum duration time of
+ the low level pulse. It is used in baud rate-detect process.*/
+#define UART_LOWPULSE_MIN_CNT  0x00000FFF
+#define UART_LOWPULSE_MIN_CNT_M  ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S))
+#define UART_LOWPULSE_MIN_CNT_V  0xFFF
+#define UART_LOWPULSE_MIN_CNT_S  0
+
+#define UART_HIGHPULSE_REG(i)          (REG_UART_BASE(i) + 0x2C)
+/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */
+/*description: This register stores  the value of the maxinum duration time
+ for the high level pulse. It is used in baud rate-detect process.*/
+#define UART_HIGHPULSE_MIN_CNT  0x00000FFF
+#define UART_HIGHPULSE_MIN_CNT_M  ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))
+#define UART_HIGHPULSE_MIN_CNT_V  0xFFF
+#define UART_HIGHPULSE_MIN_CNT_S  0
+
+#define UART_RXD_CNT_REG(i)          (REG_UART_BASE(i) + 0x30)
+/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register stores the count of rxd edge change. It is used
+ in baud rate-detect process.*/
+#define UART_RXD_EDGE_CNT  0x000003FF
+#define UART_RXD_EDGE_CNT_M  ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S))
+#define UART_RXD_EDGE_CNT_V  0x3FF
+#define UART_RXD_EDGE_CNT_S  0
+
+#define UART_FLOW_CONF_REG(i)          (REG_UART_BASE(i) + 0x34)
+/* UART_SEND_XOFF : R/W/SS/SC ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to send Xoff char. It is cleared by hardware automatically.*/
+#define UART_SEND_XOFF  (BIT(5))
+#define UART_SEND_XOFF_M  (BIT(5))
+#define UART_SEND_XOFF_V  0x1
+#define UART_SEND_XOFF_S  5
+/* UART_SEND_XON : R/W/SS/SC ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to send Xon char. It is cleared by hardware automatically.*/
+#define UART_SEND_XON  (BIT(4))
+#define UART_SEND_XON_M  (BIT(4))
+#define UART_SEND_XON_V  0x1
+#define UART_SEND_XON_S  4
+/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to stop the  transmitter from sending data.*/
+#define UART_FORCE_XOFF  (BIT(3))
+#define UART_FORCE_XOFF_M  (BIT(3))
+#define UART_FORCE_XOFF_V  0x1
+#define UART_FORCE_XOFF_S  3
+/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to enable the transmitter to go on sending data.*/
+#define UART_FORCE_XON  (BIT(2))
+#define UART_FORCE_XON_M  (BIT(2))
+#define UART_FORCE_XON_V  0x1
+#define UART_FORCE_XON_S  2
+/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to remove flow control char from the received data.*/
+#define UART_XONOFF_DEL  (BIT(1))
+#define UART_XONOFF_DEL_M  (BIT(1))
+#define UART_XONOFF_DEL_V  0x1
+#define UART_XONOFF_DEL_S  1
+/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable software flow control. It is used with
+ register sw_xon or sw_xoff.*/
+#define UART_SW_FLOW_CON_EN  (BIT(0))
+#define UART_SW_FLOW_CON_EN_M  (BIT(0))
+#define UART_SW_FLOW_CON_EN_V  0x1
+#define UART_SW_FLOW_CON_EN_S  0
+
+#define UART_SLEEP_CONF_REG(i)          (REG_UART_BASE(i) + 0x38)
+/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */
+/*description: The uart is activated from light sleeping mode when the input
+ rxd edge changes more times than this register value.*/
+#define UART_ACTIVE_THRESHOLD  0x000003FF
+#define UART_ACTIVE_THRESHOLD_M  ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S))
+#define UART_ACTIVE_THRESHOLD_V  0x3FF
+#define UART_ACTIVE_THRESHOLD_S  0
+
+#define UART_SWFC_CONF0_REG(i)          (REG_UART_BASE(i) + 0x3C)
+/* UART_XOFF_CHAR : R/W ;bitpos:[16:9] ;default: 8'h13 ; */
+/*description: This register stores the Xoff flow control char.*/
+#define UART_XOFF_CHAR  0x000000FF
+#define UART_XOFF_CHAR_M  ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S))
+#define UART_XOFF_CHAR_V  0xFF
+#define UART_XOFF_CHAR_S  9
+/* UART_XOFF_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'he0 ; */
+/*description: When the data amount in Rx-FIFO is more than this register value
+ with uart_sw_flow_con_en set to 1  it will send a Xoff char.*/
+#define UART_XOFF_THRESHOLD  0x000001FF
+#define UART_XOFF_THRESHOLD_M  ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S))
+#define UART_XOFF_THRESHOLD_V  0x1FF
+#define UART_XOFF_THRESHOLD_S  0
+
+#define UART_SWFC_CONF1_REG(i)          (REG_UART_BASE(i) + 0x40)
+/* UART_XON_CHAR : R/W ;bitpos:[16:9] ;default: 8'h11 ; */
+/*description: This register stores the Xon flow control char.*/
+#define UART_XON_CHAR  0x000000FF
+#define UART_XON_CHAR_M  ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S))
+#define UART_XON_CHAR_V  0xFF
+#define UART_XON_CHAR_S  9
+/* UART_XON_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: When the data amount in Rx-FIFO is less than this register value
+ with uart_sw_flow_con_en set to 1  it will send a Xon char.*/
+#define UART_XON_THRESHOLD  0x000001FF
+#define UART_XON_THRESHOLD_M  ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S))
+#define UART_XON_THRESHOLD_V  0x1FF
+#define UART_XON_THRESHOLD_S  0
+
+#define UART_TXBRK_CONF_REG(i)          (REG_UART_BASE(i) + 0x44)
+/* UART_TX_BRK_NUM : R/W ;bitpos:[7:0] ;default: 8'ha ; */
+/*description: This register is used to configure the number of 0 to be sent
+ after the process of sending data is done. It is active when txd_brk is set to 1.*/
+#define UART_TX_BRK_NUM  0x000000FF
+#define UART_TX_BRK_NUM_M  ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S))
+#define UART_TX_BRK_NUM_V  0xFF
+#define UART_TX_BRK_NUM_S  0
+
+#define UART_IDLE_CONF_REG(i)          (REG_UART_BASE(i) + 0x48)
+/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */
+/*description: This register is used to configure the duration time between transfers.*/
+#define UART_TX_IDLE_NUM  0x000003FF
+#define UART_TX_IDLE_NUM_M  ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S))
+#define UART_TX_IDLE_NUM_V  0x3FF
+#define UART_TX_IDLE_NUM_S  10
+/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */
+/*description: It will produce frame end signal when receiver takes more time
+ to receive one byte data than this register value.*/
+#define UART_RX_IDLE_THRHD  0x000003FF
+#define UART_RX_IDLE_THRHD_M  ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S))
+#define UART_RX_IDLE_THRHD_V  0x3FF
+#define UART_RX_IDLE_THRHD_S  0
+
+#define UART_RS485_CONF_REG(i)          (REG_UART_BASE(i) + 0x4c)
+/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */
+/*description: This register is used to delay the transmitter's internal data signal.*/
+#define UART_RS485_TX_DLY_NUM  0x0000000F
+#define UART_RS485_TX_DLY_NUM_M  ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S))
+#define UART_RS485_TX_DLY_NUM_V  0xF
+#define UART_RS485_TX_DLY_NUM_S  6
+/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This register is used to delay the receiver's internal data signal.*/
+#define UART_RS485_RX_DLY_NUM  (BIT(5))
+#define UART_RS485_RX_DLY_NUM_M  (BIT(5))
+#define UART_RS485_RX_DLY_NUM_V  0x1
+#define UART_RS485_RX_DLY_NUM_S  5
+/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.*/
+#define UART_RS485RXBY_TX_EN  (BIT(4))
+#define UART_RS485RXBY_TX_EN_M  (BIT(4))
+#define UART_RS485RXBY_TX_EN_V  0x1
+#define UART_RS485RXBY_TX_EN_S  4
+/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to enable receiver could receive data when the transmitter
+ is transmitting data in rs485 mode.*/
+#define UART_RS485TX_RX_EN  (BIT(3))
+#define UART_RS485TX_RX_EN_M  (BIT(3))
+#define UART_RS485TX_RX_EN_V  0x1
+#define UART_RS485TX_RX_EN_S  3
+/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to delay the stop bit by 1 bit.*/
+#define UART_DL1_EN  (BIT(2))
+#define UART_DL1_EN_M  (BIT(2))
+#define UART_DL1_EN_V  0x1
+#define UART_DL1_EN_S  2
+/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to delay the stop bit by 1 bit.*/
+#define UART_DL0_EN  (BIT(1))
+#define UART_DL0_EN_M  (BIT(1))
+#define UART_DL0_EN_V  0x1
+#define UART_DL0_EN_S  1
+/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to choose the rs485 mode.*/
+#define UART_RS485_EN  (BIT(0))
+#define UART_RS485_EN_M  (BIT(0))
+#define UART_RS485_EN_V  0x1
+#define UART_RS485_EN_S  0
+
+#define UART_AT_CMD_PRECNT_REG(i)          (REG_UART_BASE(i) + 0x50)
+/* UART_PRE_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */
+/*description: This register is used to configure the idle duration time before
+ the first at_cmd is received by receiver.*/
+#define UART_PRE_IDLE_NUM  0x0000FFFF
+#define UART_PRE_IDLE_NUM_M  ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S))
+#define UART_PRE_IDLE_NUM_V  0xFFFF
+#define UART_PRE_IDLE_NUM_S  0
+
+#define UART_AT_CMD_POSTCNT_REG(i)          (REG_UART_BASE(i) + 0x54)
+/* UART_POST_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */
+/*description: This register is used to configure the duration time between
+ the last at_cmd and the next data.*/
+#define UART_POST_IDLE_NUM  0x0000FFFF
+#define UART_POST_IDLE_NUM_M  ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S))
+#define UART_POST_IDLE_NUM_V  0xFFFF
+#define UART_POST_IDLE_NUM_S  0
+
+#define UART_AT_CMD_GAPTOUT_REG(i)          (REG_UART_BASE(i) + 0x58)
+/* UART_RX_GAP_TOUT : R/W ;bitpos:[15:0] ;default: 16'd11 ; */
+/*description: This register is used to configure the duration time between the at_cmd chars.*/
+#define UART_RX_GAP_TOUT  0x0000FFFF
+#define UART_RX_GAP_TOUT_M  ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S))
+#define UART_RX_GAP_TOUT_V  0xFFFF
+#define UART_RX_GAP_TOUT_S  0
+
+#define UART_AT_CMD_CHAR_REG(i)          (REG_UART_BASE(i) + 0x5c)
+/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */
+/*description: This register is used to configure the num of continuous at_cmd
+ chars received by receiver.*/
+#define UART_CHAR_NUM  0x000000FF
+#define UART_CHAR_NUM_M  ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S))
+#define UART_CHAR_NUM_V  0xFF
+#define UART_CHAR_NUM_S  8
+/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */
+/*description: This register is used to configure the content of at_cmd char.*/
+#define UART_AT_CMD_CHAR  0x000000FF
+#define UART_AT_CMD_CHAR_M  ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S))
+#define UART_AT_CMD_CHAR_V  0xFF
+#define UART_AT_CMD_CHAR_S  0
+
+#define UART_MEM_CONF_REG(i)          (REG_UART_BASE(i) + 0x60)
+/* UART_MEM_FORCE_PU : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to force power up UART memory.*/
+#define UART_MEM_FORCE_PU  (BIT(27))
+#define UART_MEM_FORCE_PU_M  (BIT(27))
+#define UART_MEM_FORCE_PU_V  0x1
+#define UART_MEM_FORCE_PU_S  27
+/* UART_MEM_FORCE_PD : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to force power down UART memory.*/
+#define UART_MEM_FORCE_PD  (BIT(26))
+#define UART_MEM_FORCE_PD_M  (BIT(26))
+#define UART_MEM_FORCE_PD_V  0x1
+#define UART_MEM_FORCE_PD_S  26
+/* UART_RX_TOUT_THRHD : R/W ;bitpos:[25:16] ;default: 10'ha ; */
+/*description: This register is used to configure the threshold time that receiver
+ takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.*/
+#define UART_RX_TOUT_THRHD  0x000003FF
+#define UART_RX_TOUT_THRHD_M  ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S))
+#define UART_RX_TOUT_THRHD_V  0x3FF
+#define UART_RX_TOUT_THRHD_S  16
+/* UART_RX_FLOW_THRHD : R/W ;bitpos:[15:7] ;default: 9'h0 ; */
+/*description: This register is used to configure the maximum amount of data
+ that can be received  when hardware flow control works.*/
+#define UART_RX_FLOW_THRHD  0x000001FF
+#define UART_RX_FLOW_THRHD_M  ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S))
+#define UART_RX_FLOW_THRHD_V  0x1FF
+#define UART_RX_FLOW_THRHD_S  7
+/* UART_TX_SIZE : R/W ;bitpos:[6:4] ;default: 3'h1 ; */
+/*description: This register is used to configure the amount of mem allocated
+ for transmit-FIFO. The default number is 128 bytes.*/
+#define UART_TX_SIZE  0x00000007
+#define UART_TX_SIZE_M  ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S))
+#define UART_TX_SIZE_V  0x7
+#define UART_TX_SIZE_S  4
+/* UART_RX_SIZE : R/W ;bitpos:[3:1] ;default: 3'b1 ; */
+/*description: This register is used to configure the amount of mem allocated
+ for receive-FIFO. The default number is 128 bytes.*/
+#define UART_RX_SIZE  0x00000007
+#define UART_RX_SIZE_M  ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S))
+#define UART_RX_SIZE_V  0x7
+#define UART_RX_SIZE_S  1
+
+#define UART_MEM_TX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x64)
+/* UART_TX_RADDR : RO ;bitpos:[20:11] ;default: 10'h0 ; */
+/*description: This register stores the offset address in Tx-FIFO when Tx-FSM
+ reads data via Tx-FIFO_Ctrl.*/
+#define UART_TX_RADDR  0x000003FF
+#define UART_TX_RADDR_M  ((UART_TX_RADDR_V)<<(UART_TX_RADDR_S))
+#define UART_TX_RADDR_V  0x3FF
+#define UART_TX_RADDR_S  11
+/* UART_APB_TX_WADDR : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register stores the offset address in Tx-FIFO when software
+ writes Tx-FIFO via APB.*/
+#define UART_APB_TX_WADDR  0x000003FF
+#define UART_APB_TX_WADDR_M  ((UART_APB_TX_WADDR_V)<<(UART_APB_TX_WADDR_S))
+#define UART_APB_TX_WADDR_V  0x3FF
+#define UART_APB_TX_WADDR_S  0
+
+#define UART_MEM_RX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x68)
+/* UART_RX_WADDR : RO ;bitpos:[20:11] ;default: 10'h100 ; */
+/*description: This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl
+ writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.*/
+#define UART_RX_WADDR  0x000003FF
+#define UART_RX_WADDR_M  ((UART_RX_WADDR_V)<<(UART_RX_WADDR_S))
+#define UART_RX_WADDR_V  0x3FF
+#define UART_RX_WADDR_S  11
+/* UART_APB_RX_RADDR : RO ;bitpos:[9:0] ;default: 10'h100 ; */
+/*description: This register stores the offset address in RX-FIFO when software
+ reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.*/
+#define UART_APB_RX_RADDR  0x000003FF
+#define UART_APB_RX_RADDR_M  ((UART_APB_RX_RADDR_V)<<(UART_APB_RX_RADDR_S))
+#define UART_APB_RX_RADDR_V  0x3FF
+#define UART_APB_RX_RADDR_S  0
+
+#define UART_FSM_STATUS_REG(i)          (REG_UART_BASE(i) + 0x6c)
+/* UART_ST_UTX_OUT : RO ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: This is the status register of transmitter.*/
+#define UART_ST_UTX_OUT  0x0000000F
+#define UART_ST_UTX_OUT_M  ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S))
+#define UART_ST_UTX_OUT_V  0xF
+#define UART_ST_UTX_OUT_S  4
+/* UART_ST_URX_OUT : RO ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: This is the status register of receiver.*/
+#define UART_ST_URX_OUT  0x0000000F
+#define UART_ST_URX_OUT_M  ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S))
+#define UART_ST_URX_OUT_V  0xF
+#define UART_ST_URX_OUT_S  0
+
+#define UART_POSPULSE_REG(i)          (REG_UART_BASE(i) + 0x70)
+/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */
+/*description: This register stores the minimal input clock count between two
+ positive edges. It is used in boudrate-detect process.*/
+#define UART_POSEDGE_MIN_CNT  0x00000FFF
+#define UART_POSEDGE_MIN_CNT_M  ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S))
+#define UART_POSEDGE_MIN_CNT_V  0xFFF
+#define UART_POSEDGE_MIN_CNT_S  0
+
+#define UART_NEGPULSE_REG(i)          (REG_UART_BASE(i) + 0x74)
+/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */
+/*description: This register stores the minimal input clock count between two
+ negative edges. It is used in boudrate-detect process.*/
+#define UART_NEGEDGE_MIN_CNT  0x00000FFF
+#define UART_NEGEDGE_MIN_CNT_M  ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S))
+#define UART_NEGEDGE_MIN_CNT_V  0xFFF
+#define UART_NEGEDGE_MIN_CNT_S  0
+
+#define UART_CLK_CONF_REG(i)          (REG_UART_BASE(i) + 0x78)
+/* UART_RX_RST_CORE : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Write 1 then write 0 to this bit  reset UART Rx.*/
+#define UART_RX_RST_CORE  (BIT(27))
+#define UART_RX_RST_CORE_M  (BIT(27))
+#define UART_RX_RST_CORE_V  0x1
+#define UART_RX_RST_CORE_S  27
+/* UART_TX_RST_CORE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Write 1 then write 0 to this bit  reset UART Tx.*/
+#define UART_TX_RST_CORE  (BIT(26))
+#define UART_TX_RST_CORE_M  (BIT(26))
+#define UART_TX_RST_CORE_V  0x1
+#define UART_TX_RST_CORE_S  26
+/* UART_RX_SCLK_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: Set this bit to enable UART Rx clock.*/
+#define UART_RX_SCLK_EN  (BIT(25))
+#define UART_RX_SCLK_EN_M  (BIT(25))
+#define UART_RX_SCLK_EN_V  0x1
+#define UART_RX_SCLK_EN_S  25
+/* UART_TX_SCLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: Set this bit to enable UART Tx clock.*/
+#define UART_TX_SCLK_EN  (BIT(24))
+#define UART_TX_SCLK_EN_M  (BIT(24))
+#define UART_TX_SCLK_EN_V  0x1
+#define UART_TX_SCLK_EN_S  24
+/* UART_RST_CORE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Write 1 then write 0 to this bit  reset UART Tx/Rx.*/
+#define UART_RST_CORE  (BIT(23))
+#define UART_RST_CORE_M  (BIT(23))
+#define UART_RST_CORE_V  0x1
+#define UART_RST_CORE_S  23
+/* UART_SCLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: Set this bit to enable UART Tx/Rx clock.*/
+#define UART_SCLK_EN  (BIT(22))
+#define UART_SCLK_EN_M  (BIT(22))
+#define UART_SCLK_EN_V  0x1
+#define UART_SCLK_EN_S  22
+/* UART_SCLK_SEL : R/W ;bitpos:[21:20] ;default: 2'd3 ; */
+/*description: UART clock source select. 1: 80Mhz  2: 8Mhz  3: XTAL.*/
+#define UART_SCLK_SEL  0x00000003
+#define UART_SCLK_SEL_M  ((UART_SCLK_SEL_V)<<(UART_SCLK_SEL_S))
+#define UART_SCLK_SEL_V  0x3
+#define UART_SCLK_SEL_S  20
+/* UART_SCLK_DIV_NUM : R/W ;bitpos:[19:12] ;default: 8'h1 ; */
+/*description: The integral part of the frequency divider factor.*/
+#define UART_SCLK_DIV_NUM  0x000000FF
+#define UART_SCLK_DIV_NUM_M  ((UART_SCLK_DIV_NUM_V)<<(UART_SCLK_DIV_NUM_S))
+#define UART_SCLK_DIV_NUM_V  0xFF
+#define UART_SCLK_DIV_NUM_S  12
+/* UART_SCLK_DIV_A : R/W ;bitpos:[11:6] ;default: 6'h0 ; */
+/*description: The numerator of the frequency divider factor.*/
+#define UART_SCLK_DIV_A  0x0000003F
+#define UART_SCLK_DIV_A_M  ((UART_SCLK_DIV_A_V)<<(UART_SCLK_DIV_A_S))
+#define UART_SCLK_DIV_A_V  0x3F
+#define UART_SCLK_DIV_A_S  6
+/* UART_SCLK_DIV_B : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: The  denominator of the frequency divider factor.*/
+#define UART_SCLK_DIV_B  0x0000003F
+#define UART_SCLK_DIV_B_M  ((UART_SCLK_DIV_B_V)<<(UART_SCLK_DIV_B_S))
+#define UART_SCLK_DIV_B_V  0x3F
+#define UART_SCLK_DIV_B_S  0
+
+#define UART_DATE_REG(i)          (REG_UART_BASE(i) + 0x7c)
+/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h2008270 ; */
+/*description: This is the version register.*/
+#define UART_DATE  0xFFFFFFFF
+#define UART_DATE_M  ((UART_DATE_V)<<(UART_DATE_S))
+#define UART_DATE_V  0xFFFFFFFF
+#define UART_DATE_S  0
+
+#define UART_ID_REG(i)          (REG_UART_BASE(i) + 0x80)
+/* UART_UPDATE : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Software write 1 would synchronize registers into UART Core clock
+ domain and would be cleared by hardware after synchronization is done.*/
+#define UART_UPDATE  (BIT(31))
+#define UART_UPDATE_M  (BIT(31))
+#define UART_UPDATE_V  0x1
+#define UART_UPDATE_S  31
+/* UART_HIGH_SPEED : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This bit used to select synchronize mode. 1: Registers are auto
+ synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers  software needs to write 1 to UART_REG_UPDATE to synchronize registers.*/
+#define UART_HIGH_SPEED  (BIT(30))
+#define UART_HIGH_SPEED_M  (BIT(30))
+#define UART_HIGH_SPEED_V  0x1
+#define UART_HIGH_SPEED_S  30
+/* UART_ID : R/W ;bitpos:[29:0] ;default: 30'h0500 ; */
+/*description: This register is used to configure the uart_id.*/
+#define UART_ID  0x3FFFFFFF
+#define UART_ID_M  ((UART_ID_V)<<(UART_ID_S))
+#define UART_ID_V  0x3FFFFFFF
+#define UART_ID_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_UART_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/uart_struct.h b/components/soc/esp32c3/include/soc/uart_struct.h
new file mode 100644
index 0000000000..ad9ca42ff7
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/uart_struct.h
@@ -0,0 +1,406 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_UART_STRUCT_H_
+#define _SOC_UART_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t rw_byte;                 /*a*/
+        };
+        uint32_t val;
+    } ahb_fifo;
+    union {
+        struct {
+            uint32_t rxfifo_full:              1;       /*This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.*/
+            uint32_t txfifo_empty:             1;       /*This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .*/
+            uint32_t parity_err:               1;       /*This interrupt raw bit turns to high level when receiver detects a parity error in the data.*/
+            uint32_t frm_err:                  1;       /*This interrupt raw bit turns to high level when receiver detects a data frame error .*/
+            uint32_t rxfifo_ovf:               1;       /*This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.*/
+            uint32_t dsr_chg:                  1;       /*This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.*/
+            uint32_t cts_chg:                  1;       /*This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.*/
+            uint32_t brk_det:                  1;       /*This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.*/
+            uint32_t rxfifo_tout:              1;       /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
+            uint32_t sw_xon:                   1;       /*This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.*/
+            uint32_t sw_xoff:                  1;       /*This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.*/
+            uint32_t glitch_det:               1;       /*This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.*/
+            uint32_t tx_brk_done:              1;       /*This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters  after all data in Tx-FIFO are sent.*/
+            uint32_t tx_brk_idle_done:         1;       /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.*/
+            uint32_t tx_done:                  1;       /*This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.*/
+            uint32_t rs485_parity_err:         1;       /*This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.*/
+            uint32_t rs485_frm_err:            1;       /*This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.*/
+            uint32_t rs485_clash:              1;       /*This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.*/
+            uint32_t at_cmd_char_det:          1;       /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.*/
+            uint32_t wakeup:                   1;       /*This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.*/
+            uint32_t reserved20:              12;       /*Reserved*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t rxfifo_full:             1;        /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/
+            uint32_t txfifo_empty:            1;        /*This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.*/
+            uint32_t parity_err:              1;        /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/
+            uint32_t frm_err:                 1;        /*This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/
+            uint32_t rxfifo_ovf:              1;        /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
+            uint32_t dsr_chg:                 1;        /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
+            uint32_t cts_chg:                 1;        /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
+            uint32_t brk_det:                 1;        /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
+            uint32_t rxfifo_tout:             1;        /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/
+            uint32_t sw_xon:                  1;        /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
+            uint32_t sw_xoff:                 1;        /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
+            uint32_t glitch_det:              1;        /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
+            uint32_t tx_brk_done:             1;        /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
+            uint32_t tx_brk_idle_done:        1;        /*This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
+            uint32_t tx_done:                 1;        /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
+            uint32_t rs485_parity_err:        1;        /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/
+            uint32_t rs485_frm_err:           1;        /*This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/
+            uint32_t rs485_clash:             1;        /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/
+            uint32_t at_cmd_char_det:         1;        /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
+            uint32_t wakeup:                  1;        /*This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.*/
+            uint32_t reserved20:             12;        /*Reserved*/
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t rxfifo_full:              1;       /*This is the enable bit for rxfifo_full_int_st register.*/
+            uint32_t txfifo_empty:             1;       /*This is the enable bit for txfifo_empty_int_st register.*/
+            uint32_t parity_err:               1;       /*This is the enable bit for parity_err_int_st register.*/
+            uint32_t frm_err:                  1;       /*This is the enable bit for frm_err_int_st register.*/
+            uint32_t rxfifo_ovf:               1;       /*This is the enable bit for rxfifo_ovf_int_st register.*/
+            uint32_t dsr_chg:                  1;       /*This is the enable bit for dsr_chg_int_st register.*/
+            uint32_t cts_chg:                  1;       /*This is the enable bit for cts_chg_int_st register.*/
+            uint32_t brk_det:                  1;       /*This is the enable bit for brk_det_int_st register.*/
+            uint32_t rxfifo_tout:              1;       /*This is the enable bit for rxfifo_tout_int_st register.*/
+            uint32_t sw_xon:                   1;       /*This is the enable bit for sw_xon_int_st register.*/
+            uint32_t sw_xoff:                  1;       /*This is the enable bit for sw_xoff_int_st register.*/
+            uint32_t glitch_det:               1;       /*This is the enable bit for glitch_det_int_st register.*/
+            uint32_t tx_brk_done:              1;       /*This is the enable bit for tx_brk_done_int_st register.*/
+            uint32_t tx_brk_idle_done:         1;       /*This is the enable bit for tx_brk_idle_done_int_st register.*/
+            uint32_t tx_done:                  1;       /*This is the enable bit for tx_done_int_st register.*/
+            uint32_t rs485_parity_err:         1;       /*This is the enable bit for rs485_parity_err_int_st register.*/
+            uint32_t rs485_frm_err:            1;       /*This is the enable bit for rs485_parity_err_int_st register.*/
+            uint32_t rs485_clash:              1;       /*This is the enable bit for rs485_clash_int_st register.*/
+            uint32_t at_cmd_char_det:          1;       /*This is the enable bit for at_cmd_char_det_int_st register.*/
+            uint32_t wakeup:                   1;       /*This is the enable bit for uart_wakeup_int_st register.*/
+            uint32_t reserved20:              12;       /*Reserved*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t rxfifo_full:              1;       /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/
+            uint32_t txfifo_empty:             1;       /*Set this bit to clear txfifo_empty_int_raw interrupt.*/
+            uint32_t parity_err:               1;       /*Set this bit to clear parity_err_int_raw interrupt.*/
+            uint32_t frm_err:                  1;       /*Set this bit to clear frm_err_int_raw interrupt.*/
+            uint32_t rxfifo_ovf:               1;       /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
+            uint32_t dsr_chg:                  1;       /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
+            uint32_t cts_chg:                  1;       /*Set this bit to clear the cts_chg_int_raw interrupt.*/
+            uint32_t brk_det:                  1;       /*Set this bit to clear the brk_det_int_raw interrupt.*/
+            uint32_t rxfifo_tout:              1;       /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
+            uint32_t sw_xon:                   1;       /*Set this bit to clear the sw_xon_int_raw interrupt.*/
+            uint32_t sw_xoff:                  1;       /*Set this bit to clear the sw_xoff_int_raw interrupt.*/
+            uint32_t glitch_det:               1;       /*Set this bit to clear the glitch_det_int_raw interrupt.*/
+            uint32_t tx_brk_done:              1;       /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/
+            uint32_t tx_brk_idle_done:         1;       /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
+            uint32_t tx_done:                  1;       /*Set this bit to clear the tx_done_int_raw interrupt.*/
+            uint32_t rs485_parity_err:         1;       /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
+            uint32_t rs485_frm_err:            1;       /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
+            uint32_t rs485_clash:              1;       /*Set this bit to clear the rs485_clash_int_raw interrupt.*/
+            uint32_t at_cmd_char_det:          1;       /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
+            uint32_t wakeup:                   1;       /*Set this bit to clear the uart_wakeup_int_raw interrupt.*/
+            uint32_t reserved20:              12;       /*Reserved*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t div_int:    12;                    /*The integral part of the frequency divider factor.*/
+            uint32_t reserved12:  8;
+            uint32_t div_frag:    4;                    /*The decimal part of the frequency divider factor.*/
+            uint32_t reserved24:  8;                    /*Reserved*/
+        };
+        uint32_t val;
+    } clk_div;
+    union {
+        struct {
+            uint32_t glitch_filt:    8;                 /*when input pulse width is lower than this value  the pulse is ignored.*/
+            uint32_t glitch_filt_en: 1;                 /*Set this bit to enable Rx signal filter.*/
+            uint32_t reserved9:     23;
+        };
+        uint32_t val;
+    } rx_filt;
+    union {
+        struct {
+            uint32_t rxfifo_cnt:10;                     /*Stores the byte number of valid data in Rx-FIFO.*/
+            uint32_t reserved10: 3;
+            uint32_t dsrn:       1;                     /*The register represent the level value of the internal uart dsr signal.*/
+            uint32_t ctsn:       1;                     /*This register represent the level value of the internal uart cts signal.*/
+            uint32_t rxd:        1;                     /*This register represent the  level value of the internal uart rxd signal.*/
+            uint32_t txfifo_cnt:10;                     /*Stores the byte number of data in Tx-FIFO.*/
+            uint32_t reserved26: 3;                     /*Reserved*/
+            uint32_t dtrn:       1;                     /*This bit represents the level of the internal uart dtr signal.*/
+            uint32_t rtsn:       1;                     /*This bit represents the level of the internal uart rts signal.*/
+            uint32_t txd:        1;                     /*This bit represents the  level of the internal uart txd signal.*/
+        };
+        uint32_t val;
+    } status;
+    union {
+        struct {
+            uint32_t parity:       1;                   /*This register is used to configure the parity check mode.*/
+            uint32_t parity_en:    1;                   /*Set this bit to enable uart parity check.*/
+            uint32_t bit_num:      2;                   /*This register is used to set the length of data.*/
+            uint32_t stop_bit_num: 2;                   /*This register is used to set the length of  stop bit.*/
+            uint32_t sw_rts:       1;                   /*This register is used to configure the software rts signal which is used in software flow control.*/
+            uint32_t sw_dtr:       1;                   /*This register is used to configure the software dtr signal which is used in software flow control.*/
+            uint32_t txd_brk:      1;                   /*Set this bit to enbale transmitter to  send NULL when the process of sending data is done.*/
+            uint32_t irda_dplx:    1;                   /*Set this bit to enable IrDA loopback mode.*/
+            uint32_t irda_tx_en:   1;                   /*This is the start enable bit for IrDA transmitter.*/
+            uint32_t irda_wctl:    1;                   /*1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.*/
+            uint32_t irda_tx_inv:  1;                   /*Set this bit to invert the level of  IrDA transmitter.*/
+            uint32_t irda_rx_inv:  1;                   /*Set this bit to invert the level of IrDA receiver.*/
+            uint32_t loopback:     1;                   /*Set this bit to enable uart loopback test mode.*/
+            uint32_t tx_flow_en:   1;                   /*Set this bit to enable flow control function for transmitter.*/
+            uint32_t irda_en:      1;                   /*Set this bit to enable IrDA protocol.*/
+            uint32_t rxfifo_rst:   1;                   /*Set this bit to reset the uart receive-FIFO.*/
+            uint32_t txfifo_rst:   1;                   /*Set this bit to reset the uart transmit-FIFO.*/
+            uint32_t rxd_inv:      1;                   /*Set this bit to inverse the level value of uart rxd signal.*/
+            uint32_t cts_inv:      1;                   /*Set this bit to inverse the level value of uart cts signal.*/
+            uint32_t dsr_inv:      1;                   /*Set this bit to inverse the level value of uart dsr signal.*/
+            uint32_t txd_inv:      1;                   /*Set this bit to inverse the level value of uart txd signal.*/
+            uint32_t rts_inv:      1;                   /*Set this bit to inverse the level value of uart rts signal.*/
+            uint32_t dtr_inv:      1;                   /*Set this bit to inverse the level value of uart dtr signal.*/
+            uint32_t clk_en:       1;                   /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
+            uint32_t err_wr_mask:  1;                   /*1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.*/
+            uint32_t autobaud_en:  1;                   /*This is the enable bit for detecting baudrate.*/
+            uint32_t mem_clk_en:   1;                   /*UART memory clock gate enable signal.*/
+            uint32_t reserved29:   3;
+        };
+        uint32_t val;
+    } conf0;
+    union {
+        struct {
+            uint32_t rxfifo_full_thrhd:  9;             /*It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.*/
+            uint32_t txfifo_empty_thrhd: 9;             /*It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.*/
+            uint32_t dis_rx_dat_ovf:     1;             /*Disable UART Rx data overflow detect.*/
+            uint32_t rx_tout_flow_dis:   1;             /*Set this bit to stop accumulating idle_cnt when hardware flow control works.*/
+            uint32_t rx_flow_en:         1;             /*This is the flow enable bit for UART receiver.*/
+            uint32_t rx_tout_en:         1;             /*This is the enble bit for uart receiver's timeout function.*/
+            uint32_t reserved22:        10;
+        };
+        uint32_t val;
+    } conf1;
+    union {
+        struct {
+            uint32_t min_cnt:         12;               /*This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.*/
+            uint32_t reserved12:      20;               /*Reserved*/
+        };
+        uint32_t val;
+    } lowpulse;
+    union {
+        struct {
+            uint32_t min_cnt:          12;              /*This register stores  the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.*/
+            uint32_t reserved12:       20;              /*Reserved*/
+        };
+        uint32_t val;
+    } highpulse;
+    union {
+        struct {
+            uint32_t edge_cnt:    10;                   /*This register stores the count of rxd edge change. It is used in baud rate-detect process.*/
+            uint32_t reserved10:  22;                   /*Reserved*/
+        };
+        uint32_t val;
+    } rxd_cnt;
+    union {
+        struct {
+            uint32_t sw_flow_con_en: 1;                 /*Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.*/
+            uint32_t xonoff_del:     1;                 /*Set this bit to remove flow control char from the received data.*/
+            uint32_t force_xon:      1;                 /*Set this bit to enable the transmitter to go on sending data.*/
+            uint32_t force_xoff:     1;                 /*Set this bit to stop the  transmitter from sending data.*/
+            uint32_t send_xon:       1;                 /*Set this bit to send Xon char. It is cleared by hardware automatically.*/
+            uint32_t send_xoff:      1;                 /*Set this bit to send Xoff char. It is cleared by hardware automatically.*/
+            uint32_t reserved6:     26;                 /*Reserved*/
+        };
+        uint32_t val;
+    } flow_conf;
+    union {
+        struct {
+            uint32_t active_threshold:10;               /*The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.*/
+            uint32_t reserved10:      22;               /*Reserved*/
+        };
+        uint32_t val;
+    } sleep_conf;
+    union {
+        struct {
+            uint32_t xoff_threshold: 9;                 /*When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1  it will send a Xoff char.*/
+            uint32_t xoff_char:      8;                 /*This register stores the Xoff flow control char.*/
+            uint32_t reserved17:    15;                 /*Reserved*/
+        };
+        uint32_t val;
+    } swfc_conf0;
+    union {
+        struct {
+            uint32_t xon_threshold: 9;                  /*When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1  it will send a Xon char.*/
+            uint32_t xon_char:      8;                  /*This register stores the Xon flow control char.*/
+            uint32_t reserved17:   15;                  /*Reserved*/
+        };
+        uint32_t val;
+    } swfc_conf1;
+    union {
+        struct {
+            uint32_t tx_brk_num: 8;                     /*This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.*/
+            uint32_t reserved8: 24;
+        };
+        uint32_t val;
+    } txbrk_conf;
+    union {
+        struct {
+            uint32_t rx_idle_thrhd:10;                  /*It will produce frame end signal when receiver takes more time to receive one byte data than this register value.*/
+            uint32_t tx_idle_num:  10;                  /*This register is used to configure the duration time between transfers.*/
+            uint32_t reserved20:   12;                  /*Reserved*/
+        };
+        uint32_t val;
+    } idle_conf;
+    union {
+        struct {
+            uint32_t en:               1;               /*Set this bit to choose the rs485 mode.*/
+            uint32_t dl0_en:           1;               /*Set this bit to delay the stop bit by 1 bit.*/
+            uint32_t dl1_en:           1;               /*Set this bit to delay the stop bit by 1 bit.*/
+            uint32_t tx_rx_en:         1;               /*Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.*/
+            uint32_t rx_busy_tx_en:    1;               /*1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.*/
+            uint32_t rx_dly_num:       1;               /*This register is used to delay the receiver's internal data signal.*/
+            uint32_t tx_dly_num:       4;               /*This register is used to delay the transmitter's internal data signal.*/
+            uint32_t reserved10:      22;               /*Reserved*/
+        };
+        uint32_t val;
+    } rs485_conf;
+    union {
+        struct {
+            uint32_t pre_idle_num:16;                   /*This register is used to configure the idle duration time before the first at_cmd is received by receiver.*/
+            uint32_t reserved16:  16;                   /*Reserved*/
+        };
+        uint32_t val;
+    } at_cmd_precnt;
+    union {
+        struct {
+            uint32_t post_idle_num:16;                  /*This register is used to configure the duration time between the last at_cmd and the next data.*/
+            uint32_t reserved16:   16;                  /*Reserved*/
+        };
+        uint32_t val;
+    } at_cmd_postcnt;
+    union {
+        struct {
+            uint32_t rx_gap_tout:16;                    /*This register is used to configure the duration time between the at_cmd chars.*/
+            uint32_t reserved16: 16;                    /*Reserved*/
+        };
+        uint32_t val;
+    } at_cmd_gaptout;
+    union {
+        struct {
+            uint32_t data:        8;                    /*This register is used to configure the content of at_cmd char.*/
+            uint32_t char_num:    8;                    /*This register is used to configure the num of continuous at_cmd chars received by receiver.*/
+            uint32_t reserved16: 16;                    /*Reserved*/
+        };
+        uint32_t val;
+    } at_cmd_char;
+    union {
+        struct {
+            uint32_t reserved0:     1;
+            uint32_t rx_size:       3;                  /*This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.*/
+            uint32_t tx_size:       3;                  /*This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.*/
+            uint32_t rx_flow_thrhd: 9;                  /*This register is used to configure the maximum amount of data that can be received  when hardware flow control works.*/
+            uint32_t rx_tout_thrhd:10;                  /*This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.*/
+            uint32_t force_pd:      1;                  /*Set this bit to force power down UART memory.*/
+            uint32_t force_pu:      1;                  /*Set this bit to force power up UART memory.*/
+            uint32_t reserved28:    4;
+        };
+        uint32_t val;
+    } mem_conf;
+    union {
+        struct {
+            uint32_t apb_tx_waddr:10;                   /*This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.*/
+            uint32_t reserved10:   1;                   /*Reserved*/
+            uint32_t tx_raddr:    10;                   /*This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.*/
+            uint32_t reserved21:  11;                   /*Reserved*/
+        };
+        uint32_t val;
+    } mem_tx_status;
+    union {
+        struct {
+            uint32_t apb_rx_raddr:10;                   /*This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.*/
+            uint32_t reserved10:   1;                   /*Reserved*/
+            uint32_t rx_waddr:    10;                   /*This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.*/
+            uint32_t reserved21:  11;                   /*Reserved*/
+        };
+        uint32_t val;
+    } mem_rx_status;
+    union {
+        struct {
+            uint32_t st_urx_out: 4;                     /*This is the status register of receiver.*/
+            uint32_t st_utx_out: 4;                     /*This is the status register of transmitter.*/
+            uint32_t reserved8: 24;                     /*Reserved*/
+        };
+        uint32_t val;
+    } fsm_status;
+    union {
+        struct {
+            uint32_t min_cnt:        12;                /*This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.*/
+            uint32_t reserved12:     20;                /*Reserved*/
+        };
+        uint32_t val;
+    } pospulse;
+    union {
+        struct {
+            uint32_t min_cnt:        12;                /*This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.*/
+            uint32_t reserved12:     20;                /*Reserved*/
+        };
+        uint32_t val;
+    } negpulse;
+    union {
+        struct {
+            uint32_t sclk_div_b:   6;                   /*The  denominator of the frequency divider factor.*/
+            uint32_t sclk_div_a:   6;                   /*The numerator of the frequency divider factor.*/
+            uint32_t sclk_div_num: 8;                   /*The integral part of the frequency divider factor.*/
+            uint32_t sclk_sel:     2;                   /*UART clock source select. 1: 80Mhz  2: 8Mhz  3: XTAL.*/
+            uint32_t sclk_en:      1;                   /*Set this bit to enable UART Tx/Rx clock.*/
+            uint32_t rst_core:     1;                   /*Write 1 then write 0 to this bit  reset UART Tx/Rx.*/
+            uint32_t tx_sclk_en:   1;                   /*Set this bit to enable UART Tx clock.*/
+            uint32_t rx_sclk_en:   1;                   /*Set this bit to enable UART Rx clock.*/
+            uint32_t tx_rst_core:  1;                   /*Write 1 then write 0 to this bit  reset UART Tx.*/
+            uint32_t rx_rst_core:  1;                   /*Write 1 then write 0 to this bit  reset UART Rx.*/
+            uint32_t reserved28:   4;
+        };
+        uint32_t val;
+    } clk_conf;
+    uint32_t date;                                      /*UART Version register*/
+    union {
+        struct {
+            uint32_t id                            :    30;  /*This register is used to configure the uart_id.*/
+            uint32_t high_speed                    :    1;  /*This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. */
+            uint32_t update                        :    1;  /*Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.*/
+        };
+        uint32_t val;
+    } id;
+} uart_dev_t;
+extern uart_dev_t UART0;
+extern uart_dev_t UART1;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_UART_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/uhci_reg.h b/components/soc/esp32c3/include/soc/uhci_reg.h
new file mode 100644
index 0000000000..3a41dedb80
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/uhci_reg.h
@@ -0,0 +1,748 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_UHCI_REG_H_
+#define _SOC_UHCI_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define UHCI_CONF0_REG(i)          (REG_UHCI_BASE(i) + 0x0)
+/* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: If this bit is set to 1  UHCI will end payload receive process
+ when NULL frame is received by UART.*/
+#define UHCI_UART_RX_BRK_EOF_EN  (BIT(12))
+#define UHCI_UART_RX_BRK_EOF_EN_M  (BIT(12))
+#define UHCI_UART_RX_BRK_EOF_EN_V  0x1
+#define UHCI_UART_RX_BRK_EOF_EN_S  12
+/* UHCI_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: 1'b1: Force clock on for register. 1'b0: Support clock only when
+ application writes registers.*/
+#define UHCI_CLK_EN  (BIT(11))
+#define UHCI_CLK_EN_M  (BIT(11))
+#define UHCI_CLK_EN_V  0x1
+#define UHCI_CLK_EN_S  11
+/* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: Set this bit to enable data integrity checking by appending a
+ 16 bit CCITT-CRC to end of the payload.*/
+#define UHCI_ENCODE_CRC_EN  (BIT(10))
+#define UHCI_ENCODE_CRC_EN_M  (BIT(10))
+#define UHCI_ENCODE_CRC_EN_V  0x1
+#define UHCI_ENCODE_CRC_EN_S  10
+/* UHCI_LEN_EOF_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: If this bit is set to 1  UHCI decoder receiving payload data
+ is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0  UHCI decoder receiving payload data is end when 0xc0 is received.*/
+#define UHCI_LEN_EOF_EN  (BIT(9))
+#define UHCI_LEN_EOF_EN_M  (BIT(9))
+#define UHCI_LEN_EOF_EN_V  0x1
+#define UHCI_LEN_EOF_EN_S  9
+/* UHCI_UART_IDLE_EOF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: If this bit is set to 1  UHCI will end the payload receiving
+ process when UART has been in idle state.*/
+#define UHCI_UART_IDLE_EOF_EN  (BIT(8))
+#define UHCI_UART_IDLE_EOF_EN_M  (BIT(8))
+#define UHCI_UART_IDLE_EOF_EN_V  0x1
+#define UHCI_UART_IDLE_EOF_EN_S  8
+/* UHCI_CRC_REC_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: Set this bit to enable UHCI to receive the 16 bit CRC.*/
+#define UHCI_CRC_REC_EN  (BIT(7))
+#define UHCI_CRC_REC_EN_M  (BIT(7))
+#define UHCI_CRC_REC_EN_V  0x1
+#define UHCI_CRC_REC_EN_S  7
+/* UHCI_HEAD_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: Set this bit to encode the data packet with a formatting header.*/
+#define UHCI_HEAD_EN  (BIT(6))
+#define UHCI_HEAD_EN_M  (BIT(6))
+#define UHCI_HEAD_EN_V  0x1
+#define UHCI_HEAD_EN_S  6
+/* UHCI_SEPER_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: Set this bit to separate the data frame using a special char.*/
+#define UHCI_SEPER_EN  (BIT(5))
+#define UHCI_SEPER_EN_M  (BIT(5))
+#define UHCI_SEPER_EN_V  0x1
+#define UHCI_SEPER_EN_S  5
+/* UHCI_UART1_CE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to link up HCI and UART1.*/
+#define UHCI_UART1_CE  (BIT(3))
+#define UHCI_UART1_CE_M  (BIT(3))
+#define UHCI_UART1_CE_V  0x1
+#define UHCI_UART1_CE_S  3
+/* UHCI_UART0_CE : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to link up HCI and UART0.*/
+#define UHCI_UART0_CE  (BIT(2))
+#define UHCI_UART0_CE_M  (BIT(2))
+#define UHCI_UART0_CE_V  0x1
+#define UHCI_UART0_CE_S  2
+/* UHCI_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Write 1  then write 0 to this bit to reset encode state machine.*/
+#define UHCI_RX_RST  (BIT(1))
+#define UHCI_RX_RST_M  (BIT(1))
+#define UHCI_RX_RST_V  0x1
+#define UHCI_RX_RST_S  1
+/* UHCI_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Write 1  then write 0 to this bit to reset decode state machine.*/
+#define UHCI_TX_RST  (BIT(0))
+#define UHCI_TX_RST_M  (BIT(0))
+#define UHCI_TX_RST_V  0x1
+#define UHCI_TX_RST_S  0
+
+#define UHCI_INT_RAW_REG(i)          (REG_UHCI_BASE(i) + 0x4)
+/* UHCI_APP_CTRL1_INT_RAW : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Soft control int raw bit.*/
+#define UHCI_APP_CTRL1_INT_RAW  (BIT(8))
+#define UHCI_APP_CTRL1_INT_RAW_M  (BIT(8))
+#define UHCI_APP_CTRL1_INT_RAW_V  0x1
+#define UHCI_APP_CTRL1_INT_RAW_S  8
+/* UHCI_APP_CTRL0_INT_RAW : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Soft control int raw bit.*/
+#define UHCI_APP_CTRL0_INT_RAW  (BIT(7))
+#define UHCI_APP_CTRL0_INT_RAW_M  (BIT(7))
+#define UHCI_APP_CTRL0_INT_RAW_V  0x1
+#define UHCI_APP_CTRL0_INT_RAW_S  7
+/* UHCI_OUTLINK_EOF_ERR_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This is the interrupt raw bit. Triggered when there are some
+ errors in EOF in the*/
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW_M  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW_V  0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW_S  6
+/* UHCI_SEND_A_Q_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SEND_A_Q_INT_RAW  (BIT(5))
+#define UHCI_SEND_A_Q_INT_RAW_M  (BIT(5))
+#define UHCI_SEND_A_Q_INT_RAW_V  0x1
+#define UHCI_SEND_A_Q_INT_RAW_S  5
+/* UHCI_SEND_S_Q_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SEND_S_Q_INT_RAW  (BIT(4))
+#define UHCI_SEND_S_Q_INT_RAW_M  (BIT(4))
+#define UHCI_SEND_S_Q_INT_RAW_V  0x1
+#define UHCI_SEND_S_Q_INT_RAW_S  4
+/* UHCI_TX_HUNG_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_HUNG_INT_RAW  (BIT(3))
+#define UHCI_TX_HUNG_INT_RAW_M  (BIT(3))
+#define UHCI_TX_HUNG_INT_RAW_V  0x1
+#define UHCI_TX_HUNG_INT_RAW_S  3
+/* UHCI_RX_HUNG_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_HUNG_INT_RAW  (BIT(2))
+#define UHCI_RX_HUNG_INT_RAW_M  (BIT(2))
+#define UHCI_RX_HUNG_INT_RAW_V  0x1
+#define UHCI_RX_HUNG_INT_RAW_S  2
+/* UHCI_TX_START_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_START_INT_RAW  (BIT(1))
+#define UHCI_TX_START_INT_RAW_M  (BIT(1))
+#define UHCI_TX_START_INT_RAW_V  0x1
+#define UHCI_TX_START_INT_RAW_S  1
+/* UHCI_RX_START_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_START_INT_RAW  (BIT(0))
+#define UHCI_RX_START_INT_RAW_M  (BIT(0))
+#define UHCI_RX_START_INT_RAW_V  0x1
+#define UHCI_RX_START_INT_RAW_S  0
+
+#define UHCI_INT_ST_REG(i)          (REG_UHCI_BASE(i) + 0x8)
+/* UHCI_APP_CTRL1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_APP_CTRL1_INT_ST  (BIT(8))
+#define UHCI_APP_CTRL1_INT_ST_M  (BIT(8))
+#define UHCI_APP_CTRL1_INT_ST_V  0x1
+#define UHCI_APP_CTRL1_INT_ST_S  8
+/* UHCI_APP_CTRL0_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_APP_CTRL0_INT_ST  (BIT(7))
+#define UHCI_APP_CTRL0_INT_ST_M  (BIT(7))
+#define UHCI_APP_CTRL0_INT_ST_V  0x1
+#define UHCI_APP_CTRL0_INT_ST_S  7
+/* UHCI_OUTLINK_EOF_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_OUTLINK_EOF_ERR_INT_ST  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_M  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_V  0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_S  6
+/* UHCI_SEND_A_Q_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SEND_A_Q_INT_ST  (BIT(5))
+#define UHCI_SEND_A_Q_INT_ST_M  (BIT(5))
+#define UHCI_SEND_A_Q_INT_ST_V  0x1
+#define UHCI_SEND_A_Q_INT_ST_S  5
+/* UHCI_SEND_S_Q_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SEND_S_Q_INT_ST  (BIT(4))
+#define UHCI_SEND_S_Q_INT_ST_M  (BIT(4))
+#define UHCI_SEND_S_Q_INT_ST_V  0x1
+#define UHCI_SEND_S_Q_INT_ST_S  4
+/* UHCI_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_HUNG_INT_ST  (BIT(3))
+#define UHCI_TX_HUNG_INT_ST_M  (BIT(3))
+#define UHCI_TX_HUNG_INT_ST_V  0x1
+#define UHCI_TX_HUNG_INT_ST_S  3
+/* UHCI_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_HUNG_INT_ST  (BIT(2))
+#define UHCI_RX_HUNG_INT_ST_M  (BIT(2))
+#define UHCI_RX_HUNG_INT_ST_V  0x1
+#define UHCI_RX_HUNG_INT_ST_S  2
+/* UHCI_TX_START_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_START_INT_ST  (BIT(1))
+#define UHCI_TX_START_INT_ST_M  (BIT(1))
+#define UHCI_TX_START_INT_ST_V  0x1
+#define UHCI_TX_START_INT_ST_S  1
+/* UHCI_RX_START_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_START_INT_ST  (BIT(0))
+#define UHCI_RX_START_INT_ST_M  (BIT(0))
+#define UHCI_RX_START_INT_ST_V  0x1
+#define UHCI_RX_START_INT_ST_S  0
+
+#define UHCI_INT_ENA_REG(i)          (REG_UHCI_BASE(i) + 0xC)
+/* UHCI_APP_CTRL1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_APP_CTRL1_INT_ENA  (BIT(8))
+#define UHCI_APP_CTRL1_INT_ENA_M  (BIT(8))
+#define UHCI_APP_CTRL1_INT_ENA_V  0x1
+#define UHCI_APP_CTRL1_INT_ENA_S  8
+/* UHCI_APP_CTRL0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_APP_CTRL0_INT_ENA  (BIT(7))
+#define UHCI_APP_CTRL0_INT_ENA_M  (BIT(7))
+#define UHCI_APP_CTRL0_INT_ENA_V  0x1
+#define UHCI_APP_CTRL0_INT_ENA_S  7
+/* UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V  0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S  6
+/* UHCI_SEND_A_Q_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SEND_A_Q_INT_ENA  (BIT(5))
+#define UHCI_SEND_A_Q_INT_ENA_M  (BIT(5))
+#define UHCI_SEND_A_Q_INT_ENA_V  0x1
+#define UHCI_SEND_A_Q_INT_ENA_S  5
+/* UHCI_SEND_S_Q_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SEND_S_Q_INT_ENA  (BIT(4))
+#define UHCI_SEND_S_Q_INT_ENA_M  (BIT(4))
+#define UHCI_SEND_S_Q_INT_ENA_V  0x1
+#define UHCI_SEND_S_Q_INT_ENA_S  4
+/* UHCI_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_HUNG_INT_ENA  (BIT(3))
+#define UHCI_TX_HUNG_INT_ENA_M  (BIT(3))
+#define UHCI_TX_HUNG_INT_ENA_V  0x1
+#define UHCI_TX_HUNG_INT_ENA_S  3
+/* UHCI_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_HUNG_INT_ENA  (BIT(2))
+#define UHCI_RX_HUNG_INT_ENA_M  (BIT(2))
+#define UHCI_RX_HUNG_INT_ENA_V  0x1
+#define UHCI_RX_HUNG_INT_ENA_S  2
+/* UHCI_TX_START_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_START_INT_ENA  (BIT(1))
+#define UHCI_TX_START_INT_ENA_M  (BIT(1))
+#define UHCI_TX_START_INT_ENA_V  0x1
+#define UHCI_TX_START_INT_ENA_S  1
+/* UHCI_RX_START_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_START_INT_ENA  (BIT(0))
+#define UHCI_RX_START_INT_ENA_M  (BIT(0))
+#define UHCI_RX_START_INT_ENA_V  0x1
+#define UHCI_RX_START_INT_ENA_S  0
+
+#define UHCI_INT_CLR_REG(i)          (REG_UHCI_BASE(i) + 0x10)
+/* UHCI_APP_CTRL1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_APP_CTRL1_INT_CLR  (BIT(8))
+#define UHCI_APP_CTRL1_INT_CLR_M  (BIT(8))
+#define UHCI_APP_CTRL1_INT_CLR_V  0x1
+#define UHCI_APP_CTRL1_INT_CLR_S  8
+/* UHCI_APP_CTRL0_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_APP_CTRL0_INT_CLR  (BIT(7))
+#define UHCI_APP_CTRL0_INT_CLR_M  (BIT(7))
+#define UHCI_APP_CTRL0_INT_CLR_V  0x1
+#define UHCI_APP_CTRL0_INT_CLR_S  7
+/* UHCI_OUTLINK_EOF_ERR_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V  0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S  6
+/* UHCI_SEND_A_Q_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SEND_A_Q_INT_CLR  (BIT(5))
+#define UHCI_SEND_A_Q_INT_CLR_M  (BIT(5))
+#define UHCI_SEND_A_Q_INT_CLR_V  0x1
+#define UHCI_SEND_A_Q_INT_CLR_S  5
+/* UHCI_SEND_S_Q_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SEND_S_Q_INT_CLR  (BIT(4))
+#define UHCI_SEND_S_Q_INT_CLR_M  (BIT(4))
+#define UHCI_SEND_S_Q_INT_CLR_V  0x1
+#define UHCI_SEND_S_Q_INT_CLR_S  4
+/* UHCI_TX_HUNG_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_HUNG_INT_CLR  (BIT(3))
+#define UHCI_TX_HUNG_INT_CLR_M  (BIT(3))
+#define UHCI_TX_HUNG_INT_CLR_V  0x1
+#define UHCI_TX_HUNG_INT_CLR_S  3
+/* UHCI_RX_HUNG_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_HUNG_INT_CLR  (BIT(2))
+#define UHCI_RX_HUNG_INT_CLR_M  (BIT(2))
+#define UHCI_RX_HUNG_INT_CLR_V  0x1
+#define UHCI_RX_HUNG_INT_CLR_S  2
+/* UHCI_TX_START_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_START_INT_CLR  (BIT(1))
+#define UHCI_TX_START_INT_CLR_M  (BIT(1))
+#define UHCI_TX_START_INT_CLR_V  0x1
+#define UHCI_TX_START_INT_CLR_S  1
+/* UHCI_RX_START_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_START_INT_CLR  (BIT(0))
+#define UHCI_RX_START_INT_CLR_M  (BIT(0))
+#define UHCI_RX_START_INT_CLR_V  0x1
+#define UHCI_RX_START_INT_CLR_S  0
+
+#define UHCI_CONF1_REG(i)          (REG_UHCI_BASE(i) + 0x14)
+/* UHCI_SW_START : R/W/SC ;bitpos:[8] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SW_START  (BIT(8))
+#define UHCI_SW_START_M  (BIT(8))
+#define UHCI_SW_START_V  0x1
+#define UHCI_SW_START_S  8
+/* UHCI_WAIT_SW_START : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_WAIT_SW_START  (BIT(7))
+#define UHCI_WAIT_SW_START_M  (BIT(7))
+#define UHCI_WAIT_SW_START_V  0x1
+#define UHCI_WAIT_SW_START_S  7
+/* UHCI_TX_ACK_NUM_RE : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_TX_ACK_NUM_RE  (BIT(5))
+#define UHCI_TX_ACK_NUM_RE_M  (BIT(5))
+#define UHCI_TX_ACK_NUM_RE_V  0x1
+#define UHCI_TX_ACK_NUM_RE_S  5
+/* UHCI_TX_CHECK_SUM_RE : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_TX_CHECK_SUM_RE  (BIT(4))
+#define UHCI_TX_CHECK_SUM_RE_M  (BIT(4))
+#define UHCI_TX_CHECK_SUM_RE_V  0x1
+#define UHCI_TX_CHECK_SUM_RE_S  4
+/* UHCI_SAVE_HEAD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SAVE_HEAD  (BIT(3))
+#define UHCI_SAVE_HEAD_M  (BIT(3))
+#define UHCI_SAVE_HEAD_V  0x1
+#define UHCI_SAVE_HEAD_S  3
+/* UHCI_CRC_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_CRC_DISABLE  (BIT(2))
+#define UHCI_CRC_DISABLE_M  (BIT(2))
+#define UHCI_CRC_DISABLE_V  0x1
+#define UHCI_CRC_DISABLE_S  2
+/* UHCI_CHECK_SEQ_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_CHECK_SEQ_EN  (BIT(1))
+#define UHCI_CHECK_SEQ_EN_M  (BIT(1))
+#define UHCI_CHECK_SEQ_EN_V  0x1
+#define UHCI_CHECK_SEQ_EN_S  1
+/* UHCI_CHECK_SUM_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_CHECK_SUM_EN  (BIT(0))
+#define UHCI_CHECK_SUM_EN_M  (BIT(0))
+#define UHCI_CHECK_SUM_EN_V  0x1
+#define UHCI_CHECK_SUM_EN_S  0
+
+#define UHCI_STATE0_REG(i)          (REG_UHCI_BASE(i) + 0x18)
+/* UHCI_DECODE_STATE : RO ;bitpos:[5:3] ;default: 3'b0 ; */
+/*description: a*/
+#define UHCI_DECODE_STATE  0x00000007
+#define UHCI_DECODE_STATE_M  ((UHCI_DECODE_STATE_V)<<(UHCI_DECODE_STATE_S))
+#define UHCI_DECODE_STATE_V  0x7
+#define UHCI_DECODE_STATE_S  3
+/* UHCI_RX_ERR_CAUSE : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: a*/
+#define UHCI_RX_ERR_CAUSE  0x00000007
+#define UHCI_RX_ERR_CAUSE_M  ((UHCI_RX_ERR_CAUSE_V)<<(UHCI_RX_ERR_CAUSE_S))
+#define UHCI_RX_ERR_CAUSE_V  0x7
+#define UHCI_RX_ERR_CAUSE_S  0
+
+#define UHCI_STATE1_REG(i)          (REG_UHCI_BASE(i) + 0x1C)
+/* UHCI_ENCODE_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: a*/
+#define UHCI_ENCODE_STATE  0x00000007
+#define UHCI_ENCODE_STATE_M  ((UHCI_ENCODE_STATE_V)<<(UHCI_ENCODE_STATE_S))
+#define UHCI_ENCODE_STATE_V  0x7
+#define UHCI_ENCODE_STATE_S  0
+
+#define UHCI_ESCAPE_CONF_REG(i)          (REG_UHCI_BASE(i) + 0x20)
+/* UHCI_RX_13_ESC_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_13_ESC_EN  (BIT(7))
+#define UHCI_RX_13_ESC_EN_M  (BIT(7))
+#define UHCI_RX_13_ESC_EN_V  0x1
+#define UHCI_RX_13_ESC_EN_S  7
+/* UHCI_RX_11_ESC_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_11_ESC_EN  (BIT(6))
+#define UHCI_RX_11_ESC_EN_M  (BIT(6))
+#define UHCI_RX_11_ESC_EN_V  0x1
+#define UHCI_RX_11_ESC_EN_S  6
+/* UHCI_RX_DB_ESC_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_RX_DB_ESC_EN  (BIT(5))
+#define UHCI_RX_DB_ESC_EN_M  (BIT(5))
+#define UHCI_RX_DB_ESC_EN_V  0x1
+#define UHCI_RX_DB_ESC_EN_S  5
+/* UHCI_RX_C0_ESC_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_RX_C0_ESC_EN  (BIT(4))
+#define UHCI_RX_C0_ESC_EN_M  (BIT(4))
+#define UHCI_RX_C0_ESC_EN_V  0x1
+#define UHCI_RX_C0_ESC_EN_S  4
+/* UHCI_TX_13_ESC_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_13_ESC_EN  (BIT(3))
+#define UHCI_TX_13_ESC_EN_M  (BIT(3))
+#define UHCI_TX_13_ESC_EN_V  0x1
+#define UHCI_TX_13_ESC_EN_S  3
+/* UHCI_TX_11_ESC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_11_ESC_EN  (BIT(2))
+#define UHCI_TX_11_ESC_EN_M  (BIT(2))
+#define UHCI_TX_11_ESC_EN_V  0x1
+#define UHCI_TX_11_ESC_EN_S  2
+/* UHCI_TX_DB_ESC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_TX_DB_ESC_EN  (BIT(1))
+#define UHCI_TX_DB_ESC_EN_M  (BIT(1))
+#define UHCI_TX_DB_ESC_EN_V  0x1
+#define UHCI_TX_DB_ESC_EN_S  1
+/* UHCI_TX_C0_ESC_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_TX_C0_ESC_EN  (BIT(0))
+#define UHCI_TX_C0_ESC_EN_M  (BIT(0))
+#define UHCI_TX_C0_ESC_EN_V  0x1
+#define UHCI_TX_C0_ESC_EN_S  0
+
+#define UHCI_HUNG_CONF_REG(i)          (REG_UHCI_BASE(i) + 0x24)
+/* UHCI_RXFIFO_TIMEOUT_ENA : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_RXFIFO_TIMEOUT_ENA  (BIT(23))
+#define UHCI_RXFIFO_TIMEOUT_ENA_M  (BIT(23))
+#define UHCI_RXFIFO_TIMEOUT_ENA_V  0x1
+#define UHCI_RXFIFO_TIMEOUT_ENA_S  23
+/* UHCI_RXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: a*/
+#define UHCI_RXFIFO_TIMEOUT_SHIFT  0x00000007
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_M  ((UHCI_RXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_RXFIFO_TIMEOUT_SHIFT_S))
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_V  0x7
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_S  20
+/* UHCI_RXFIFO_TIMEOUT : R/W ;bitpos:[19:12] ;default: 8'h10 ; */
+/*description: a*/
+#define UHCI_RXFIFO_TIMEOUT  0x000000FF
+#define UHCI_RXFIFO_TIMEOUT_M  ((UHCI_RXFIFO_TIMEOUT_V)<<(UHCI_RXFIFO_TIMEOUT_S))
+#define UHCI_RXFIFO_TIMEOUT_V  0xFF
+#define UHCI_RXFIFO_TIMEOUT_S  12
+/* UHCI_TXFIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_TXFIFO_TIMEOUT_ENA  (BIT(11))
+#define UHCI_TXFIFO_TIMEOUT_ENA_M  (BIT(11))
+#define UHCI_TXFIFO_TIMEOUT_ENA_V  0x1
+#define UHCI_TXFIFO_TIMEOUT_ENA_S  11
+/* UHCI_TXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
+/*description: a*/
+#define UHCI_TXFIFO_TIMEOUT_SHIFT  0x00000007
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_M  ((UHCI_TXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_TXFIFO_TIMEOUT_SHIFT_S))
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_V  0x7
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_S  8
+/* UHCI_TXFIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
+/*description: a*/
+#define UHCI_TXFIFO_TIMEOUT  0x000000FF
+#define UHCI_TXFIFO_TIMEOUT_M  ((UHCI_TXFIFO_TIMEOUT_V)<<(UHCI_TXFIFO_TIMEOUT_S))
+#define UHCI_TXFIFO_TIMEOUT_V  0xFF
+#define UHCI_TXFIFO_TIMEOUT_S  0
+
+#define UHCI_ACK_NUM_REG(i)          (REG_UHCI_BASE(i) + 0x28)
+/* UHCI_ACK_NUM_LOAD : WT ;bitpos:[3] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_ACK_NUM_LOAD  (BIT(3))
+#define UHCI_ACK_NUM_LOAD_M  (BIT(3))
+#define UHCI_ACK_NUM_LOAD_V  0x1
+#define UHCI_ACK_NUM_LOAD_S  3
+/* UHCI_ACK_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: */
+#define UHCI_ACK_NUM  0x00000007
+#define UHCI_ACK_NUM_M  ((UHCI_ACK_NUM_V)<<(UHCI_ACK_NUM_S))
+#define UHCI_ACK_NUM_V  0x7
+#define UHCI_ACK_NUM_S  0
+
+#define UHCI_RX_HEAD_REG(i)          (REG_UHCI_BASE(i) + 0x2C)
+/* UHCI_RX_HEAD : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_RX_HEAD  0xFFFFFFFF
+#define UHCI_RX_HEAD_M  ((UHCI_RX_HEAD_V)<<(UHCI_RX_HEAD_S))
+#define UHCI_RX_HEAD_V  0xFFFFFFFF
+#define UHCI_RX_HEAD_S  0
+
+#define UHCI_QUICK_SENT_REG(i)          (REG_UHCI_BASE(i) + 0x30)
+/* UHCI_ALWAYS_SEND_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_ALWAYS_SEND_EN  (BIT(7))
+#define UHCI_ALWAYS_SEND_EN_M  (BIT(7))
+#define UHCI_ALWAYS_SEND_EN_V  0x1
+#define UHCI_ALWAYS_SEND_EN_S  7
+/* UHCI_ALWAYS_SEND_NUM : R/W ;bitpos:[6:4] ;default: 3'h0 ; */
+/*description: a*/
+#define UHCI_ALWAYS_SEND_NUM  0x00000007
+#define UHCI_ALWAYS_SEND_NUM_M  ((UHCI_ALWAYS_SEND_NUM_V)<<(UHCI_ALWAYS_SEND_NUM_S))
+#define UHCI_ALWAYS_SEND_NUM_V  0x7
+#define UHCI_ALWAYS_SEND_NUM_S  4
+/* UHCI_SINGLE_SEND_EN : R/W/SC ;bitpos:[3] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SINGLE_SEND_EN  (BIT(3))
+#define UHCI_SINGLE_SEND_EN_M  (BIT(3))
+#define UHCI_SINGLE_SEND_EN_V  0x1
+#define UHCI_SINGLE_SEND_EN_S  3
+/* UHCI_SINGLE_SEND_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: a*/
+#define UHCI_SINGLE_SEND_NUM  0x00000007
+#define UHCI_SINGLE_SEND_NUM_M  ((UHCI_SINGLE_SEND_NUM_V)<<(UHCI_SINGLE_SEND_NUM_S))
+#define UHCI_SINGLE_SEND_NUM_V  0x7
+#define UHCI_SINGLE_SEND_NUM_S  0
+
+#define UHCI_Q0_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x34)
+/* UHCI_SEND_Q0_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q0_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD0_M  ((UHCI_SEND_Q0_WORD0_V)<<(UHCI_SEND_Q0_WORD0_S))
+#define UHCI_SEND_Q0_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD0_S  0
+
+#define UHCI_Q0_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x38)
+/* UHCI_SEND_Q0_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q0_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD1_M  ((UHCI_SEND_Q0_WORD1_V)<<(UHCI_SEND_Q0_WORD1_S))
+#define UHCI_SEND_Q0_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD1_S  0
+
+#define UHCI_Q1_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x3C)
+/* UHCI_SEND_Q1_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q1_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD0_M  ((UHCI_SEND_Q1_WORD0_V)<<(UHCI_SEND_Q1_WORD0_S))
+#define UHCI_SEND_Q1_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD0_S  0
+
+#define UHCI_Q1_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x40)
+/* UHCI_SEND_Q1_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q1_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD1_M  ((UHCI_SEND_Q1_WORD1_V)<<(UHCI_SEND_Q1_WORD1_S))
+#define UHCI_SEND_Q1_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD1_S  0
+
+#define UHCI_Q2_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x44)
+/* UHCI_SEND_Q2_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q2_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD0_M  ((UHCI_SEND_Q2_WORD0_V)<<(UHCI_SEND_Q2_WORD0_S))
+#define UHCI_SEND_Q2_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD0_S  0
+
+#define UHCI_Q2_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x48)
+/* UHCI_SEND_Q2_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q2_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD1_M  ((UHCI_SEND_Q2_WORD1_V)<<(UHCI_SEND_Q2_WORD1_S))
+#define UHCI_SEND_Q2_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD1_S  0
+
+#define UHCI_Q3_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x4C)
+/* UHCI_SEND_Q3_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q3_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD0_M  ((UHCI_SEND_Q3_WORD0_V)<<(UHCI_SEND_Q3_WORD0_S))
+#define UHCI_SEND_Q3_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD0_S  0
+
+#define UHCI_Q3_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x50)
+/* UHCI_SEND_Q3_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q3_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD1_M  ((UHCI_SEND_Q3_WORD1_V)<<(UHCI_SEND_Q3_WORD1_S))
+#define UHCI_SEND_Q3_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD1_S  0
+
+#define UHCI_Q4_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x54)
+/* UHCI_SEND_Q4_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q4_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD0_M  ((UHCI_SEND_Q4_WORD0_V)<<(UHCI_SEND_Q4_WORD0_S))
+#define UHCI_SEND_Q4_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD0_S  0
+
+#define UHCI_Q4_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x58)
+/* UHCI_SEND_Q4_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q4_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD1_M  ((UHCI_SEND_Q4_WORD1_V)<<(UHCI_SEND_Q4_WORD1_S))
+#define UHCI_SEND_Q4_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD1_S  0
+
+#define UHCI_Q5_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x5C)
+/* UHCI_SEND_Q5_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q5_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD0_M  ((UHCI_SEND_Q5_WORD0_V)<<(UHCI_SEND_Q5_WORD0_S))
+#define UHCI_SEND_Q5_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD0_S  0
+
+#define UHCI_Q5_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x60)
+/* UHCI_SEND_Q5_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q5_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD1_M  ((UHCI_SEND_Q5_WORD1_V)<<(UHCI_SEND_Q5_WORD1_S))
+#define UHCI_SEND_Q5_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD1_S  0
+
+#define UHCI_Q6_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x64)
+/* UHCI_SEND_Q6_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q6_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD0_M  ((UHCI_SEND_Q6_WORD0_V)<<(UHCI_SEND_Q6_WORD0_S))
+#define UHCI_SEND_Q6_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD0_S  0
+
+#define UHCI_Q6_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x68)
+/* UHCI_SEND_Q6_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q6_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD1_M  ((UHCI_SEND_Q6_WORD1_V)<<(UHCI_SEND_Q6_WORD1_S))
+#define UHCI_SEND_Q6_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD1_S  0
+
+#define UHCI_ESC_CONF0_REG(i)          (REG_UHCI_BASE(i) + 0x6C)
+/* UHCI_SEPER_ESC_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdc ; */
+/*description: a*/
+#define UHCI_SEPER_ESC_CHAR1  0x000000FF
+#define UHCI_SEPER_ESC_CHAR1_M  ((UHCI_SEPER_ESC_CHAR1_V)<<(UHCI_SEPER_ESC_CHAR1_S))
+#define UHCI_SEPER_ESC_CHAR1_V  0xFF
+#define UHCI_SEPER_ESC_CHAR1_S  16
+/* UHCI_SEPER_ESC_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: a*/
+#define UHCI_SEPER_ESC_CHAR0  0x000000FF
+#define UHCI_SEPER_ESC_CHAR0_M  ((UHCI_SEPER_ESC_CHAR0_V)<<(UHCI_SEPER_ESC_CHAR0_S))
+#define UHCI_SEPER_ESC_CHAR0_V  0xFF
+#define UHCI_SEPER_ESC_CHAR0_S  8
+/* UHCI_SEPER_CHAR : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */
+/*description: a*/
+#define UHCI_SEPER_CHAR  0x000000FF
+#define UHCI_SEPER_CHAR_M  ((UHCI_SEPER_CHAR_V)<<(UHCI_SEPER_CHAR_S))
+#define UHCI_SEPER_CHAR_V  0xFF
+#define UHCI_SEPER_CHAR_S  0
+
+#define UHCI_ESC_CONF1_REG(i)          (REG_UHCI_BASE(i) + 0x70)
+/* UHCI_ESC_SEQ0_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdd ; */
+/*description: a*/
+#define UHCI_ESC_SEQ0_CHAR1  0x000000FF
+#define UHCI_ESC_SEQ0_CHAR1_M  ((UHCI_ESC_SEQ0_CHAR1_V)<<(UHCI_ESC_SEQ0_CHAR1_S))
+#define UHCI_ESC_SEQ0_CHAR1_V  0xFF
+#define UHCI_ESC_SEQ0_CHAR1_S  16
+/* UHCI_ESC_SEQ0_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: a*/
+#define UHCI_ESC_SEQ0_CHAR0  0x000000FF
+#define UHCI_ESC_SEQ0_CHAR0_M  ((UHCI_ESC_SEQ0_CHAR0_V)<<(UHCI_ESC_SEQ0_CHAR0_S))
+#define UHCI_ESC_SEQ0_CHAR0_V  0xFF
+#define UHCI_ESC_SEQ0_CHAR0_S  8
+/* UHCI_ESC_SEQ0 : R/W ;bitpos:[7:0] ;default: 8'hdb ; */
+/*description: a*/
+#define UHCI_ESC_SEQ0  0x000000FF
+#define UHCI_ESC_SEQ0_M  ((UHCI_ESC_SEQ0_V)<<(UHCI_ESC_SEQ0_S))
+#define UHCI_ESC_SEQ0_V  0xFF
+#define UHCI_ESC_SEQ0_S  0
+
+#define UHCI_ESC_CONF2_REG(i)          (REG_UHCI_BASE(i) + 0x74)
+/* UHCI_ESC_SEQ1_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hde ; */
+/*description: a*/
+#define UHCI_ESC_SEQ1_CHAR1  0x000000FF
+#define UHCI_ESC_SEQ1_CHAR1_M  ((UHCI_ESC_SEQ1_CHAR1_V)<<(UHCI_ESC_SEQ1_CHAR1_S))
+#define UHCI_ESC_SEQ1_CHAR1_V  0xFF
+#define UHCI_ESC_SEQ1_CHAR1_S  16
+/* UHCI_ESC_SEQ1_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: a*/
+#define UHCI_ESC_SEQ1_CHAR0  0x000000FF
+#define UHCI_ESC_SEQ1_CHAR0_M  ((UHCI_ESC_SEQ1_CHAR0_V)<<(UHCI_ESC_SEQ1_CHAR0_S))
+#define UHCI_ESC_SEQ1_CHAR0_V  0xFF
+#define UHCI_ESC_SEQ1_CHAR0_S  8
+/* UHCI_ESC_SEQ1 : R/W ;bitpos:[7:0] ;default: 8'h11 ; */
+/*description: a*/
+#define UHCI_ESC_SEQ1  0x000000FF
+#define UHCI_ESC_SEQ1_M  ((UHCI_ESC_SEQ1_V)<<(UHCI_ESC_SEQ1_S))
+#define UHCI_ESC_SEQ1_V  0xFF
+#define UHCI_ESC_SEQ1_S  0
+
+#define UHCI_ESC_CONF3_REG(i)          (REG_UHCI_BASE(i) + 0x78)
+/* UHCI_ESC_SEQ2_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdf ; */
+/*description: a*/
+#define UHCI_ESC_SEQ2_CHAR1  0x000000FF
+#define UHCI_ESC_SEQ2_CHAR1_M  ((UHCI_ESC_SEQ2_CHAR1_V)<<(UHCI_ESC_SEQ2_CHAR1_S))
+#define UHCI_ESC_SEQ2_CHAR1_V  0xFF
+#define UHCI_ESC_SEQ2_CHAR1_S  16
+/* UHCI_ESC_SEQ2_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: a*/
+#define UHCI_ESC_SEQ2_CHAR0  0x000000FF
+#define UHCI_ESC_SEQ2_CHAR0_M  ((UHCI_ESC_SEQ2_CHAR0_V)<<(UHCI_ESC_SEQ2_CHAR0_S))
+#define UHCI_ESC_SEQ2_CHAR0_V  0xFF
+#define UHCI_ESC_SEQ2_CHAR0_S  8
+/* UHCI_ESC_SEQ2 : R/W ;bitpos:[7:0] ;default: 8'h13 ; */
+/*description: a*/
+#define UHCI_ESC_SEQ2  0x000000FF
+#define UHCI_ESC_SEQ2_M  ((UHCI_ESC_SEQ2_V)<<(UHCI_ESC_SEQ2_S))
+#define UHCI_ESC_SEQ2_V  0xFF
+#define UHCI_ESC_SEQ2_S  0
+
+#define UHCI_PKT_THRES_REG(i)          (REG_UHCI_BASE(i) + 0x7C)
+/* UHCI_PKT_THRS : R/W ;bitpos:[12:0] ;default: 13'h80 ; */
+/*description: a*/
+#define UHCI_PKT_THRS  0x00001FFF
+#define UHCI_PKT_THRS_M  ((UHCI_PKT_THRS_V)<<(UHCI_PKT_THRS_S))
+#define UHCI_PKT_THRS_V  0x1FFF
+#define UHCI_PKT_THRS_S  0
+
+#define UHCI_DATE_REG(i)          (REG_UHCI_BASE(i) + 0x80)
+/* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007170 ; */
+/*description: a*/
+#define UHCI_DATE  0xFFFFFFFF
+#define UHCI_DATE_M  ((UHCI_DATE_V)<<(UHCI_DATE_S))
+#define UHCI_DATE_V  0xFFFFFFFF
+#define UHCI_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_UHCI_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/uhci_struct.h b/components/soc/esp32c3/include/soc/uhci_struct.h
new file mode 100644
index 0000000000..a89c4d0126
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/uhci_struct.h
@@ -0,0 +1,230 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_UHCI_STRUCT_H_
+#define _SOC_UHCI_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t tx_rst:             1;            /*Write 1  then write 0 to this bit to reset decode state machine.*/
+            uint32_t rx_rst:             1;            /*Write 1  then write 0 to this bit to reset encode state machine.*/
+            uint32_t uart0_ce:           1;            /*Set this bit to link up HCI and UART0.*/
+            uint32_t uart1_ce:           1;            /*Set this bit to link up HCI and UART1.*/
+            uint32_t reserved4:          1;
+            uint32_t seper_en:           1;            /*Set this bit to separate the data frame using a special char.*/
+            uint32_t head_en:            1;            /*Set this bit to encode the data packet with a formatting header.*/
+            uint32_t crc_rec_en:         1;            /*Set this bit to enable UHCI to receive the 16 bit CRC.*/
+            uint32_t uart_idle_eof_en:   1;            /*If this bit is set to 1  UHCI will end the payload receiving process when UART has been in idle state.*/
+            uint32_t len_eof_en:         1;            /*If this bit is set to 1  UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0  UHCI decoder receiving payload data is end when 0xc0 is received.*/
+            uint32_t encode_crc_en:      1;            /*Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.*/
+            uint32_t clk_en:             1;            /*1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers.*/
+            uint32_t uart_rx_brk_eof_en: 1;            /*If this bit is set to 1  UHCI will end payload receive process when NULL frame is received by UART.*/
+            uint32_t reserved13:        19;
+        };
+        uint32_t val;
+    } conf0;
+    union {
+        struct {
+            uint32_t rx_start:                1;       /*a*/
+            uint32_t tx_start:                1;       /*a*/
+            uint32_t rx_hung:                 1;       /*a*/
+            uint32_t tx_hung:                 1;       /*a*/
+            uint32_t send_s_q:                1;       /*a*/
+            uint32_t send_a_q:                1;       /*a*/
+            uint32_t outlink_eof_err:         1;       /*This is the interrupt raw bit. Triggered when there are some errors in EOF in the*/
+            uint32_t app_ctrl0:               1;       /*Soft control int raw bit.*/
+            uint32_t app_ctrl1:               1;       /*Soft control int raw bit.*/
+            uint32_t reserved9:              23;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t rx_start:               1;        /*a*/
+            uint32_t tx_start:               1;        /*a*/
+            uint32_t rx_hung:                1;        /*a*/
+            uint32_t tx_hung:                1;        /*a*/
+            uint32_t send_s_q:               1;        /*a*/
+            uint32_t send_a_q:               1;        /*a*/
+            uint32_t outlink_eof_err:        1;        /*a*/
+            uint32_t app_ctrl0:              1;        /*a*/
+            uint32_t app_ctrl1:              1;        /*a*/
+            uint32_t reserved9:             23;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t rx_start:                1;       /*a*/
+            uint32_t tx_start:                1;       /*a*/
+            uint32_t rx_hung:                 1;       /*a*/
+            uint32_t tx_hung:                 1;       /*a*/
+            uint32_t send_s_q:                1;       /*a*/
+            uint32_t send_a_q:                1;       /*a*/
+            uint32_t outlink_eof_err:         1;       /*a*/
+            uint32_t app_ctrl0:               1;       /*a*/
+            uint32_t app_ctrl1:               1;       /*a*/
+            uint32_t reserved9:              23;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t rx_start:                1;       /*a*/
+            uint32_t tx_start:                1;       /*a*/
+            uint32_t rx_hung:                 1;       /*a*/
+            uint32_t tx_hung:                 1;       /*a*/
+            uint32_t send_s_q:                1;       /*a*/
+            uint32_t send_a_q:                1;       /*a*/
+            uint32_t outlink_eof_err:         1;       /*a*/
+            uint32_t app_ctrl0:               1;       /*a*/
+            uint32_t app_ctrl1:               1;       /*a*/
+            uint32_t reserved9:              23;
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t check_sum_en:    1;               /*a*/
+            uint32_t check_seq_en:    1;               /*a*/
+            uint32_t crc_disable:     1;               /*a*/
+            uint32_t save_head:       1;               /*a*/
+            uint32_t tx_check_sum_re: 1;               /*a*/
+            uint32_t tx_ack_num_re:   1;               /*a*/
+            uint32_t reserved6:       1;
+            uint32_t wait_sw_start:   1;               /*a*/
+            uint32_t sw_start:        1;               /*a*/
+            uint32_t reserved9:      12;
+            uint32_t reserved21:     11;
+        };
+        uint32_t val;
+    } conf1;
+    union {
+        struct {
+            uint32_t rx_err_cause: 3;                  /*a*/
+            uint32_t decode_state: 3;                  /*a*/
+            uint32_t reserved6:   26;
+        };
+        uint32_t val;
+    } state0;
+    union {
+        struct {
+            uint32_t encode_state: 3;                  /*a*/
+            uint32_t reserved3:   29;
+        };
+        uint32_t val;
+    } state1;
+    union {
+        struct {
+            uint32_t tx_c0_esc_en: 1;                  /*a*/
+            uint32_t tx_db_esc_en: 1;                  /*a*/
+            uint32_t tx_11_esc_en: 1;                  /*a*/
+            uint32_t tx_13_esc_en: 1;                  /*a*/
+            uint32_t rx_c0_esc_en: 1;                  /*a*/
+            uint32_t rx_db_esc_en: 1;                  /*a*/
+            uint32_t rx_11_esc_en: 1;                  /*a*/
+            uint32_t rx_13_esc_en: 1;                  /*a*/
+            uint32_t reserved8:   24;
+        };
+        uint32_t val;
+    } escape_conf;
+    union {
+        struct {
+            uint32_t txfifo_timeout:       8;          /*a*/
+            uint32_t txfifo_timeout_shift: 3;          /*a*/
+            uint32_t txfifo_timeout_ena:   1;          /*a*/
+            uint32_t rxfifo_timeout:       8;          /*a*/
+            uint32_t rxfifo_timeout_shift: 3;          /*a*/
+            uint32_t rxfifo_timeout_ena:   1;          /*a*/
+            uint32_t reserved24:           8;
+        };
+        uint32_t val;
+    } hung_conf;
+    union {
+        struct {
+            uint32_t ack_num:      3;
+            uint32_t ack_num_load: 1;                  /*a*/
+            uint32_t reserved4:   28;
+        };
+        uint32_t val;
+    } ack_num;
+    uint32_t rx_head;                                  /*a*/
+    union {
+        struct {
+            uint32_t single_send_num: 3;               /*a*/
+            uint32_t single_send_en:  1;               /*a*/
+            uint32_t always_send_num: 3;               /*a*/
+            uint32_t always_send_en:  1;               /*a*/
+            uint32_t reserved8:      24;
+        };
+        uint32_t val;
+    } quick_sent;
+    struct {
+        uint32_t w_data[2];                                 /*a*/
+    } q_data[7];
+    union {
+        struct {
+            uint32_t seper_char:      8;               /*a*/
+            uint32_t seper_esc_char0: 8;               /*a*/
+            uint32_t seper_esc_char1: 8;               /*a*/
+            uint32_t reserved24:      8;               /*a*/
+        };
+        uint32_t val;
+    } esc_conf0;
+    union {
+        struct {
+            uint32_t seq0:           8;                /*a*/
+            uint32_t seq0_char0:     8;                /*a*/
+            uint32_t seq0_char1:     8;                /*a*/
+            uint32_t reserved24:     8;
+        };
+        uint32_t val;
+    } esc_conf1;
+    union {
+        struct {
+            uint32_t seq1:           8;                /*a*/
+            uint32_t seq1_char0:     8;                /*a*/
+            uint32_t seq1_char1:     8;                /*a*/
+            uint32_t reserved24:     8;
+        };
+        uint32_t val;
+    } esc_conf2;
+    union {
+        struct {
+            uint32_t seq2:           8;                /*a*/
+            uint32_t seq2_char0:     8;                /*a*/
+            uint32_t seq2_char1:     8;                /*a*/
+            uint32_t reserved24:     8;
+        };
+        uint32_t val;
+    } esc_conf3;
+    union {
+        struct {
+            uint32_t thrs:      13;                    /*a*/
+            uint32_t reserved13:19;
+        };
+        uint32_t val;
+    } pkt_thres;
+    uint32_t date;                                     /*a*/
+} uhci_dev_t;
+extern uhci_dev_t UHCI0;
+extern uhci_dev_t UHCI1;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_UHCI_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/wdev_reg.h b/components/soc/esp32c3/include/soc/wdev_reg.h
new file mode 100644
index 0000000000..6992254b26
--- /dev/null
+++ b/components/soc/esp32c3/include/soc/wdev_reg.h
@@ -0,0 +1,20 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include "soc.h"
+
+/* Hardware random number generator register */
+#define WDEV_RND_REG 0x600260b0
diff --git a/components/soc/esp32c3/interrupts.c b/components/soc/esp32c3/interrupts.c
new file mode 100644
index 0000000000..93790cc60c
--- /dev/null
+++ b/components/soc/esp32c3/interrupts.c
@@ -0,0 +1,80 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "soc/interrupts.h"
+
+const char *const esp_isr_names[ETS_MAX_INTR_SOURCE] = {
+    [0] = "WIFI_MAC",
+    [1] = "WIFI_NMI",
+    [2] = "WIFI_PWR",
+    [3] = "WIFI_BB",
+    [4] = "BT_MAC",
+    [5] = "BT_BB",
+    [6] = "BT_BB_NMI",
+    [7] = "RWBT",
+    [8] = "RWBLE",
+    [9] = "RWBT_NMI",
+    [10] = "RWBLE_NMI",
+    [11] = "I2C",
+    [12] = "SLC0",
+    [13] = "SLC1",
+    [14] = "APB_CTRL",
+    [15] = "UHCI0",
+    [16] = "GPIO",
+    [17] = "GPIO_NMI",
+    [18] = "SPI1",
+    [19] = "SPI2",
+    [20] = "I2S1",
+    [21] = "UART0",
+    [22] = "UART1",
+    [23] = "LEDC",
+    [24] = "EFUSE",
+    [25] = "CAN",
+    [26] = "USB",
+    [27] = "RTC_CORE",
+    [28] = "RMT",
+    [29] = "I2C_EXT0",
+    [30] = "TIMER1",
+    [31] = "TIMER2",
+    [32] = "TG0_T0_LEVEL",
+    [33] = "TG0_WDT_LEVEL",
+    [34] = "TG1_T0_LEVEL",
+    [35] = "TG1_WDT_LEVEL",
+    [36] = "CACHE_IA",
+    [37] = "SYSTIMER_TARGET0_EDGE",
+    [38] = "SYSTIMER_TARGET1_EDGE",
+    [39] = "SYSTIMER_TARGET2_EDGE",
+    [40] = "SPI_MEM_REJECT_CACHE",
+    [41] = "ICACHE_PRELOAD0",
+    [42] = "ICACHE_SYNC0",
+    [43] = "APB_ADC",
+    [44] = "DMA_CH0",
+    [45] = "DMA_CH1",
+    [46] = "DMA_CH2",
+    [47] = "RSA",
+    [48] = "AES",
+    [49] = "SHA",
+    [50] = "ETS_FROM_CPU_INTR0",
+    [51] = "ETS_FROM_CPU_INTR1",
+    [52] = "ETS_FROM_CPU_INTR2",
+    [53] = "ETS_FROM_CPU_INTR3",
+    [54] = "ETS_ASSIST_DEBUG",
+    [55] = "ETS_DMA_APBPERI_PMS",
+    [56] = "ETS_CORE0_IRAM0_PMS",
+    [57] = "ETS_CORE0_DRAM0_PMS",
+    [58] = "ETS_CORE0_PIF_PMS",
+    [59] = "ETS_CORE0_PIF_PMS_SIZE",
+    [60] = "ETS_BAK_PMS_VIOLATE",
+    [61] = "ETS_CACHE_CORE0_ACS",
+};
diff --git a/components/soc/esp32c3/ledc_periph.c b/components/soc/esp32c3/ledc_periph.c
new file mode 100644
index 0000000000..13f87e5c86
--- /dev/null
+++ b/components/soc/esp32c3/ledc_periph.c
@@ -0,0 +1,25 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "soc/ledc_periph.h"
+#include "soc/gpio_sig_map.h"
+
+/*
+ Bunch of constants for every LEDC peripheral: GPIO signals
+*/
+const ledc_signal_conn_t ledc_periph_signal[1] = {
+	{
+        .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
+	}
+};
diff --git a/components/soc/esp32c3/rmt_periph.c b/components/soc/esp32c3/rmt_periph.c
new file mode 100644
index 0000000000..1556cf92f4
--- /dev/null
+++ b/components/soc/esp32c3/rmt_periph.c
@@ -0,0 +1,39 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "soc/rmt_periph.h"
+#include "soc/gpio_sig_map.h"
+
+const rmt_signal_conn_t rmt_periph_signals = {
+    .module = PERIPH_RMT_MODULE,
+    .irq = ETS_RMT_INTR_SOURCE,
+    .channels = {
+        [0] = {
+            .tx_sig = RMT_SIG_OUT0_IDX,
+            .rx_sig = -1
+        },
+        [1] = {
+            .tx_sig = RMT_SIG_OUT1_IDX,
+            .rx_sig = -1
+        },
+        [2] = {
+            .tx_sig = -1,
+            .rx_sig = RMT_SIG_IN0_IDX
+        },
+        [3] = {
+            .tx_sig = -1,
+            .rx_sig = RMT_SIG_IN1_IDX
+        },
+    }
+};
diff --git a/components/soc/esp32c3/sigmadelta_periph.c b/components/soc/esp32c3/sigmadelta_periph.c
new file mode 100644
index 0000000000..5c4c8169cb
--- /dev/null
+++ b/components/soc/esp32c3/sigmadelta_periph.c
@@ -0,0 +1,33 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "soc/sigmadelta_periph.h"
+#include "soc/gpio_sig_map.h"
+
+const sigma_delta_signal_conn_t sigma_delta_periph_signals = {
+    .channels = {
+        [0] = {
+            GPIO_SD0_OUT_IDX
+        },
+        [1] = {
+            GPIO_SD1_OUT_IDX
+        },
+        [2] = {
+            GPIO_SD2_OUT_IDX
+        },
+        [3] = {
+            GPIO_SD3_OUT_IDX
+        }
+    }
+};
diff --git a/components/soc/esp32c3/spi_periph.c b/components/soc/esp32c3/spi_periph.c
new file mode 100644
index 0000000000..1d1b41df8f
--- /dev/null
+++ b/components/soc/esp32c3/spi_periph.c
@@ -0,0 +1,71 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "soc/spi_periph.h"
+#include "stddef.h"
+
+/*
+ Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
+    {
+        .spiclk_out = SPICLK_OUT_MUX_IDX,
+        .spiclk_in = 0,/* SPI clock is not an input signal*/
+        .spid_out = SPID_OUT_IDX,
+        .spiq_out = SPIQ_OUT_IDX,
+        .spiwp_out = SPIWP_OUT_IDX,
+        .spihd_out = SPIHD_OUT_IDX,
+        .spid_in = SPID_IN_IDX,
+        .spiq_in = SPIQ_IN_IDX,
+        .spiwp_in = SPIWP_IN_IDX,
+        .spihd_in = SPIHD_IN_IDX,
+        .spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */
+        .spics_in = 0,/* SPI cs is not an input signal*/
+        .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
+        .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
+        .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
+        .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
+        .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
+        .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
+        .irq = ETS_SPI1_INTR_SOURCE,
+        .irq_dma = -1,
+        .module = PERIPH_SPI_MODULE,
+        .hw = (spi_dev_t *) &SPIMEM1,
+        .func = SPI_FUNC_NUM,
+    }, {
+        .spiclk_out = FSPICLK_OUT_IDX,
+        .spiclk_in = FSPICLK_IN_IDX,
+        .spid_out = FSPID_OUT_IDX,
+        .spiq_out = FSPIQ_OUT_IDX,
+        .spiwp_out = FSPIWP_OUT_IDX,
+        .spihd_out = FSPIHD_OUT_IDX,
+        .spid_in = FSPID_IN_IDX,
+        .spiq_in = FSPIQ_IN_IDX,
+        .spiwp_in = FSPIWP_IN_IDX,
+        .spihd_in = FSPIHD_IN_IDX,
+        .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX},
+        .spics_in = FSPICS0_IN_IDX,
+        .spiclk_iomux_pin = FSPI_IOMUX_PIN_NUM_CLK,
+        .spid_iomux_pin = FSPI_IOMUX_PIN_NUM_MOSI,
+        .spiq_iomux_pin = FSPI_IOMUX_PIN_NUM_MISO,
+        .spiwp_iomux_pin = FSPI_IOMUX_PIN_NUM_WP,
+        .spihd_iomux_pin = FSPI_IOMUX_PIN_NUM_HD,
+        .spics0_iomux_pin = FSPI_IOMUX_PIN_NUM_CS,
+        .irq = ETS_SPI2_INTR_SOURCE,
+        .irq_dma = SOC_GDMA_SPI2_INTR_SOURCE,
+        .module = PERIPH_SPI2_MODULE,
+        .hw = &GPSPI2,
+        .func = FSPI_FUNC_NUM,
+    }
+};
diff --git a/components/soc/esp32c3/timer_periph.c b/components/soc/esp32c3/timer_periph.c
new file mode 100644
index 0000000000..661f19514b
--- /dev/null
+++ b/components/soc/esp32c3/timer_periph.c
@@ -0,0 +1,28 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "soc/timer_periph.h"
+
+const timer_group_signal_conn_t timer_group_periph_signals = {
+    .groups = {
+        [0] = {
+            .module = PERIPH_TIMG0_MODULE,
+            .t0_irq_id = ETS_TG0_T0_LEVEL_INTR_SOURCE
+        },
+        [1] = {
+            .module = PERIPH_TIMG1_MODULE,
+            .t0_irq_id = ETS_TG1_T0_LEVEL_INTR_SOURCE,
+        }
+    }
+};
diff --git a/components/soc/esp32c3/uart_periph.c b/components/soc/esp32c3/uart_periph.c
new file mode 100644
index 0000000000..999eb69fd8
--- /dev/null
+++ b/components/soc/esp32c3/uart_periph.c
@@ -0,0 +1,37 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "soc/uart_periph.h"
+
+/*
+ Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
+    {
+        .tx_sig = U0TXD_OUT_IDX,
+        .rx_sig = U0RXD_IN_IDX,
+        .rts_sig = U0RTS_OUT_IDX,
+        .cts_sig = U0CTS_IN_IDX,
+        .irq = ETS_UART0_INTR_SOURCE,
+        .module = PERIPH_UART0_MODULE,
+    },
+    {
+        .tx_sig = U1TXD_OUT_IDX,
+        .rx_sig = U1RXD_IN_IDX,
+        .rts_sig = U1RTS_OUT_IDX,
+        .cts_sig = U1CTS_IN_IDX,
+        .irq = ETS_UART1_INTR_SOURCE,
+        .module = PERIPH_UART1_MODULE,
+    }
+};
diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h
index a25f4c75a8..7dfacf528f 100644
--- a/components/soc/esp32s2/include/soc/soc_caps.h
+++ b/components/soc/esp32s2/include/soc/soc_caps.h
@@ -37,16 +37,18 @@
 #pragma once
 
 /*-------------------------- COMMON CAPS ---------------------------------------*/
-#define SOC_TWAI_SUPPORTED 1
-#define SOC_CP_DMA_SUPPORTED 1
-#define SOC_CPU_CORES_NUM 1
-#define SOC_DEDICATED_GPIO_SUPPORTED 1
-#define SOC_SUPPORTS_SECURE_DL_MODE 1
-#define SOC_RISCV_COPROC_SUPPORTED 1
-#define SOC_USB_SUPPORTED 1
-#define SOC_PCNT_SUPPORTED 1
+#define SOC_TWAI_SUPPORTED              1
+#define SOC_CP_DMA_SUPPORTED            1
+#define SOC_CPU_CORES_NUM               1
+#define SOC_DEDICATED_GPIO_SUPPORTED    1
+#define SOC_SUPPORTS_SECURE_DL_MODE     1
+#define SOC_RISCV_COPROC_SUPPORTED      1
+#define SOC_USB_SUPPORTED               1
+#define SOC_PCNT_SUPPORTED              1
+#define SOC_ULP_SUPPORTED               1
+#define SOC_RTC_SLOW_MEM_SUPPORTED      1
 
-#define SOC_CACHE_SUPPORT_WRAP    1
+#define SOC_CACHE_SUPPORT_WRAP          1
 
 /*-------------------------- ADC CAPS ----------------------------------------*/
 #define SOC_ADC_PERIPH_NUM              (2)
@@ -161,6 +163,10 @@
 
 /*-------------------------- RTCIO CAPS --------------------------------------*/
 #define SOC_RTCIO_PIN_COUNT   22
+#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
+#define SOC_RTCIO_HOLD_SUPPORTED 1
+#define SOC_RTCIO_WAKE_SUPPORTED 1
+
 
 /*-------------------------- SIGMA DELTA CAPS --------------------------------*/
 #define SOC_SIGMADELTA_NUM            1
@@ -172,6 +178,7 @@
 #define SOC_SPI_PERIPH_CS_NUM(i)    (((i)==0)? 2: (((i)==1)? 6: 3))
 
 #define SOC_SPI_MAXIMUM_BUFFER_SIZE     72
+#define SOC_SPI_MAX_PRE_DIVIDER         8192
 
 //#define SOC_SPI_SUPPORT_AS_CS         //don't support to toggle the CS while the clock toggles
 #define SOC_SPI_SUPPORT_DDRCLK              1
@@ -226,6 +233,9 @@
 #define SOC_UART_FIFO_LEN           (128)       /*!< The UART hardware FIFO length */
 #define SOC_UART_BITRATE_MAX        (5000000)   /*!< Max bit rate supported by UART */
 
+/*-------------------------- SPIRAM CAPS -------------------------------------*/
+#define SOC_SPIRAM_SUPPORTED    1
+
 /*-------------------------- USB CAPS ----------------------------------------*/
 #define SOC_USB_PERIPH_NUM 1
 
diff --git a/components/soc/esp32s3/include/soc/gdma_caps.h b/components/soc/esp32s3/include/soc/gdma_caps.h
index ee3311610e..807de4e34f 100644
--- a/components/soc/esp32s3/include/soc/gdma_caps.h
+++ b/components/soc/esp32s3/include/soc/gdma_caps.h
@@ -16,3 +16,4 @@
 
 #define SOC_GDMA_CHANNELS_NUM (5)       /*!< GDMA has 5 TX and 5 RX  channels in ESP32-S3 */
 #define SOC_GDMA_L2_FIFO_BASE_SIZE (16) /*!< GDMA L2 FIFO basic size is 16 Bytes */
+#define SOC_GDMA_SUPPORT_EXTMEM (1)
diff --git a/components/soc/esp32s3/include/soc/ledc_caps.h b/components/soc/esp32s3/include/soc/ledc_caps.h
index 7feddd2c04..5f7a49704c 100644
--- a/components/soc/esp32s3/include/soc/ledc_caps.h
+++ b/components/soc/esp32s3/include/soc/ledc_caps.h
@@ -18,6 +18,8 @@ extern "C" {
 #endif
 
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK  (1)
+#define SOC_LEDC_CHANNEL_NUM 8
+#define SOC_LEDC_TIMER_BIT_WIDE_NUM  (14)
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h
index b8e5a242c2..7cf5d63445 100644
--- a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h
+++ b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h
@@ -21,6 +21,8 @@ extern "C" {
 
 /* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
 #define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
+/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */
+#define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A
 
 /* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
 #define RTC_WDT_RESET_LENGTH_100_NS    0
diff --git a/components/soc/esp32s3/include/soc/rtc_io_caps.h b/components/soc/esp32s3/include/soc/rtc_io_caps.h
index ec1aeb428f..2127adac62 100644
--- a/components/soc/esp32s3/include/soc/rtc_io_caps.h
+++ b/components/soc/esp32s3/include/soc/rtc_io_caps.h
@@ -16,3 +16,6 @@
 
 #define SOC_RTCIO_PIN_COUNT   22
 #define RTCIO_LL_PIN_FUNC     0
+#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
+#define SOC_RTCIO_HOLD_SUPPORTED 1
+#define SOC_RTCIO_WAKE_SUPPORTED 1
diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h
index 7f70afb676..2a1d68caa9 100644
--- a/components/soc/esp32s3/include/soc/soc_caps.h
+++ b/components/soc/esp32s3/include/soc/soc_caps.h
@@ -10,8 +10,10 @@
 #define SOC_TWAI_SUPPORTED              1
 #define SOC_GDMA_SUPPORTED              1
 #define SOC_DEDICATED_GPIO_SUPPORTED    1
-#define SOC_CACHE_SUPPORT_WRAP          1
 #define SOC_CPU_CORES_NUM               2
+#define SOC_CACHE_SUPPORT_WRAP          1
+#define SOC_ULP_SUPPORTED               1
+#define SOC_RTC_SLOW_MEM_SUPPORTED      1
 
 /*-------------------------- ADC CAPS ----------------------------------------*/
 #include "adc_caps.h"
@@ -73,6 +75,9 @@
 /*-------------------------- SPI CAPS ----------------------------------------*/
 #include "spi_caps.h"
 
+/*-------------------------- SPIRAM CAPS ----------------------------------------*/
+#define SOC_SPIRAM_SUPPORTED            1
+
 /*-------------------------- SYS TIMER CAPS ----------------------------------*/
 #include "systimer_caps.h"
 
@@ -83,6 +88,7 @@
 #define SOC_TIMER_GROUPS                   (2)
 #define SOC_TIMER_GROUP_TIMERS_PER_GROUP   (2)
 #define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP)
+#define SOC_TIMER_GROUP_LAYOUT             {2,2}
 
 /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
 #include "touch_sensor_caps.h"
diff --git a/components/soc/esp32s3/include/soc/spi_caps.h b/components/soc/esp32s3/include/soc/spi_caps.h
index 1f0fc055cd..3976153e1e 100644
--- a/components/soc/esp32s3/include/soc/spi_caps.h
+++ b/components/soc/esp32s3/include/soc/spi_caps.h
@@ -34,3 +34,5 @@
 #define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT         1
 
 #define SOC_MEMSPI_IS_INDEPENDENT 1
+
+#define SOC_SPI_MAX_PRE_DIVIDER 8192
diff --git a/components/soc/include/soc/adc_periph.h b/components/soc/include/soc/adc_periph.h
index 09ec3d8168..9cb75283eb 100644
--- a/components/soc/include/soc/adc_periph.h
+++ b/components/soc/include/soc/adc_periph.h
@@ -15,10 +15,13 @@
 #pragma once
 
 #include "soc/soc.h"
+#include "soc/soc_caps.h"
 #include "soc/syscon_struct.h"
 #include "soc/sens_reg.h"
 #include "soc/sens_struct.h"
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
 #include "soc/rtc_io_struct.h"
+#endif
 #include "soc/rtc_cntl_struct.h"
 #include "soc/adc_channel.h"
 #include "soc/soc_caps.h"
diff --git a/components/soc/include/soc/hwcrypto_periph.h b/components/soc/include/soc/hwcrypto_periph.h
index 6cabdd38ab..3c517879b1 100644
--- a/components/soc/include/soc/hwcrypto_periph.h
+++ b/components/soc/include/soc/hwcrypto_periph.h
@@ -13,5 +13,13 @@
 // limitations under the License.
 
 #pragma once
+
+#include "sdkconfig.h"
+
+#if CONFIG_IDF_TARGET_ESP32
+/* included here for ESP-IDF v4.x compatibility */
 #include "soc/dport_reg.h"
+#include "soc/dport_access.h"
+#endif
+
 #include "soc/hwcrypto_reg.h"
diff --git a/components/soc/include/soc/lldesc.h b/components/soc/include/soc/lldesc.h
index a991a95d17..31e02125c4 100644
--- a/components/soc/include/soc/lldesc.h
+++ b/components/soc/include/soc/lldesc.h
@@ -22,6 +22,8 @@
 #include "esp32s2/rom/lldesc.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rom/lldesc.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/lldesc.h"
 #endif
 
 //the size field has 12 bits, but 0 not for 4096.
diff --git a/components/soc/include/soc/rtc_io_periph.h b/components/soc/include/soc/rtc_io_periph.h
index 8f36889131..570f103244 100644
--- a/components/soc/include/soc/rtc_io_periph.h
+++ b/components/soc/include/soc/rtc_io_periph.h
@@ -17,9 +17,15 @@
 #include "soc/soc.h"
 //include soc related (generated) definitions
 #include "soc/soc_caps.h"
+
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
+
 #include "soc/rtc_io_channel.h"
 #include "soc/rtc_io_reg.h"
 #include "soc/rtc_io_struct.h"
+
+#endif
+
 #include "soc/rtc_cntl_reg.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/sens_struct.h"
@@ -29,6 +35,8 @@ extern "C"
 {
 #endif
 
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
+
 /**
  * @brief Pin function information for a single RTCIO pad's.
  *
@@ -102,7 +110,9 @@ typedef struct {
  */
 extern const rtc_gpio_desc_t rtc_gpio_desc[GPIO_PIN_COUNT];
 
-#endif // CONFIG_IDF_TARGET_ESP32
+#endif // CONFIG_RTCIO_SUPPORT_RTC_GPIO_DESC
+
+#endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/include/soc/rtc_periph.h b/components/soc/include/soc/rtc_periph.h
index 121dc597d9..433f5cc42e 100644
--- a/components/soc/include/soc/rtc_periph.h
+++ b/components/soc/include/soc/rtc_periph.h
@@ -15,6 +15,7 @@
 #pragma once
 #include <stdint.h>
 #include "rtc_io_periph.h"
+#include "soc/rtc_cntl_reg.h"
 #include "soc/soc_caps.h"
 
 #ifdef __cplusplus
diff --git a/components/soc/include/soc/soc_memory_layout.h b/components/soc/include/soc/soc_memory_layout.h
index 781cf74892..615304d31b 100644
--- a/components/soc/include/soc/soc_memory_layout.h
+++ b/components/soc/include/soc/soc_memory_layout.h
@@ -18,6 +18,7 @@
 #include <stdbool.h>
 
 #include "soc/soc.h"
+#include "soc/soc_caps.h"
 #include "sdkconfig.h"
 #include "esp_attr.h"
 
@@ -207,7 +208,11 @@ inline static bool IRAM_ATTR esp_ptr_internal(const void *p) {
 
 
 inline static bool IRAM_ATTR esp_ptr_external_ram(const void *p) {
+#if SOC_SPIRAM_SUPPORTED
     return ((intptr_t)p >= SOC_EXTRAM_DATA_LOW && (intptr_t)p < SOC_EXTRAM_DATA_HIGH);
+#else
+    return false; // SoC has no external RAM
+#endif
 }
 
 inline static bool IRAM_ATTR esp_ptr_in_iram(const void *p) {
diff --git a/components/soc/include/soc/touch_sensor_periph.h b/components/soc/include/soc/touch_sensor_periph.h
index 08317a3696..e38b18b059 100644
--- a/components/soc/include/soc/touch_sensor_periph.h
+++ b/components/soc/include/soc/touch_sensor_periph.h
@@ -20,7 +20,9 @@
 #include "soc/rtc_cntl_struct.h"
 #include "soc/sens_reg.h"
 #include "soc/sens_struct.h"
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
 #include "soc/rtc_io_struct.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {