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feat(sd): supported UHS-I SDR104 200MHz speed

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This commit is contained in:
armando
2025-05-13 10:49:29 +08:00
parent 0944a2a68a
commit c2b8ea07d0
10 changed files with 244 additions and 62 deletions
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1
components/esp_driver_sdspi/include/driver/sdspi_host.h
View File

@@ -60,6 +60,7 @@ typedef int sdspi_dev_handle_t;
.get_real_freq = &sdspi_host_get_real_freq, \ .get_real_freq = &sdspi_host_get_real_freq, \
.input_delay_phase = SDMMC_DELAY_PHASE_0, \ .input_delay_phase = SDMMC_DELAY_PHASE_0, \
.set_input_delay = NULL, \ .set_input_delay = NULL, \
.set_input_delayline = NULL, \
.dma_aligned_buffer = NULL, \ .dma_aligned_buffer = NULL, \
.pwr_ctrl_handle = NULL, \ .pwr_ctrl_handle = NULL, \
.get_dma_info = NULL, \ .get_dma_info = NULL, \

119
components/hal/esp32p4/include/hal/sdmmc_ll.h
View File

@@ -87,16 +87,46 @@ extern "C" {
* SDMMC capabilities * SDMMC capabilities
*/ */
#define SDMMC_LL_SLOT_SUPPORT_GPIO_MATRIX(SLOT_ID) ((SLOT_ID == 0) ? 0 : 1) #define SDMMC_LL_SLOT_SUPPORT_GPIO_MATRIX(SLOT_ID) ((SLOT_ID == 0) ? 0 : 1)
#define SDMMC_LL_IOMUX_FUNC 0
#define SDMMC_LL_HOST_CTLR_NUMS 1U
#define SDMMC_LL_DELAY_MAX_NUMS_LS 4
#define SDMMC_LL_DELAY_PHASE_SUPPORTED 1
#define SDMMC_LL_IOMUX_FUNC 0 /**
* SDMMC delay phase
*/
typedef enum { typedef enum {
SDMMC_LL_DELAY_PHASE_0, SDMMC_LL_DELAY_PHASE_0,
SDMMC_LL_DELAY_PHASE_1, SDMMC_LL_DELAY_PHASE_1,
SDMMC_LL_DELAY_PHASE_2, SDMMC_LL_DELAY_PHASE_2,
SDMMC_LL_DELAY_PHASE_3, SDMMC_LL_DELAY_PHASE_3,
SDMMC_LL_DELAY_PHASE_4,
SDMMC_LL_DELAY_PHASE_5,
SDMMC_LL_DELAY_PHASE_6,
SDMMC_LL_DELAY_PHASE_7,
} sdmmc_ll_delay_phase_t; } sdmmc_ll_delay_phase_t;
/**
* SDMMC delayline
*/
typedef enum {
SDMMC_LL_DELAY_LINE_0,
SDMMC_LL_DELAY_LINE_1,
SDMMC_LL_DELAY_LINE_2,
SDMMC_LL_DELAY_LINE_3,
SDMMC_LL_DELAY_LINE_4,
SDMMC_LL_DELAY_LINE_5,
SDMMC_LL_DELAY_LINE_6,
SDMMC_LL_DELAY_LINE_7,
} sdmmc_ll_delay_line_t;
/**
* SDMMC speed mode
*/
typedef enum {
SDMMC_LL_SPEED_MODE_LS,
SDMMC_LL_SPEED_MODE_HS,
} sdmmc_ll_speed_mode_t;
/*--------------------------------------------------------------- /*---------------------------------------------------------------
Clock & Reset Clock & Reset
@@ -274,32 +304,85 @@ static inline void sdmmc_ll_init_phase_delay(sdmmc_dev_t *hw)
#define sdmmc_ll_init_phase_delay(...) (void)__DECLARE_RCC_ATOMIC_ENV; sdmmc_ll_init_phase_delay(__VA_ARGS__) #define sdmmc_ll_init_phase_delay(...) (void)__DECLARE_RCC_ATOMIC_ENV; sdmmc_ll_init_phase_delay(__VA_ARGS__)
/** /**
* @brief Set SDMMC din delay * @brief Set SDMMC din delay phase
* *
* @param hw hardware instance address * @param hw hardware instance address
* @param phase delay phase * @param phase delay phase
* @param mode speed mode
*/ */
static inline void sdmmc_ll_set_din_delay(sdmmc_dev_t *hw, sdmmc_ll_delay_phase_t phase) static inline void sdmmc_ll_set_din_delay_phase(sdmmc_dev_t *hw, sdmmc_ll_delay_phase_t phase, sdmmc_ll_speed_mode_t mode)
{ {
switch (phase) { if (mode == SDMMC_LL_SPEED_MODE_LS) {
case SDMMC_LL_DELAY_PHASE_1: switch (phase) {
HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x1; case SDMMC_LL_DELAY_PHASE_1:
break; HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x1;
case SDMMC_LL_DELAY_PHASE_2: break;
HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x2; case SDMMC_LL_DELAY_PHASE_2:
break; HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x2;
case SDMMC_LL_DELAY_PHASE_3: break;
HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x3; case SDMMC_LL_DELAY_PHASE_3:
break; HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x3;
default: break;
HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x0; default:
break; HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_sam_clk_edge_sel = 0x0;
break;
}
} else {
SDMMC.dll_clk_conf.dll_cclk_in_sam_phase = (phase << 3);
} }
} }
/// use a macro to wrap the function, force the caller to use it in a critical section /// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define sdmmc_ll_set_din_delay(...) (void)__DECLARE_RCC_ATOMIC_ENV; sdmmc_ll_set_din_delay(__VA_ARGS__) #define sdmmc_ll_set_din_delay_phase(...) (void)__DECLARE_RCC_ATOMIC_ENV; sdmmc_ll_set_din_delay_phase(__VA_ARGS__)
/**
* @brief Set SDMMC dout delay phase
*
* @param hw hardware instance address
* @param phase delay phase
* @param mode speed mode
*/
static inline void sdmmc_ll_set_dout_delay_phase(sdmmc_dev_t *hw, sdmmc_ll_delay_phase_t phase, sdmmc_ll_speed_mode_t mode)
{
if (mode == SDMMC_LL_SPEED_MODE_HS) {
SDMMC.dll_clk_conf.dll_cclk_in_drv_phase = (phase << 3);
}
}
/**
* @brief Set SDMMC din delay line
*
* @param hw hardware instance address
* @param phase delay line
* @param mode speed mode
*/
static inline void sdmmc_ll_set_din_delay_line(sdmmc_dev_t *hw, sdmmc_ll_delay_line_t phase, sdmmc_ll_speed_mode_t mode)
{
SDMMC.dll_clk_conf.dll_cclk_in_sam_phase &= ~0x7;
if (mode == SDMMC_LL_SPEED_MODE_HS) {
SDMMC.dll_clk_conf.dll_cclk_in_sam_phase |= phase;
} else {
HAL_ASSERT(false);
}
}
/**
* @brief Set SDMMC dout delay line
*
* @param hw hardware instance address
* @param phase delay line
* @param mode speed mode
*/
static inline void sdmmc_ll_set_dout_delay_line(sdmmc_dev_t *hw, sdmmc_ll_delay_line_t phase, sdmmc_ll_speed_mode_t mode)
{
SDMMC.dll_clk_conf.dll_cclk_in_drv_phase &= ~0x7;
if (mode == SDMMC_LL_SPEED_MODE_HS) {
SDMMC.dll_clk_conf.dll_cclk_in_drv_phase |= phase;
} else {
HAL_ASSERT(false);
}
}
/** /**
* @brief Enable card clock * @brief Enable card clock

34
components/hal/esp32s3/include/hal/sdmmc_ll.h
View File

@@ -84,9 +84,14 @@ extern "C" {
* SDMMC capabilities * SDMMC capabilities
*/ */
#define SDMMC_LL_SLOT_SUPPORT_GPIO_MATRIX(SLOT_ID) 1 #define SDMMC_LL_SLOT_SUPPORT_GPIO_MATRIX(SLOT_ID) 1
#define SDMMC_LL_IOMUX_FUNC -1
#define SDMMC_LL_HOST_CTLR_NUMS 1U
#define SDMMC_LL_DELAY_MAX_NUMS_LS 4
#define SDMMC_LL_DELAY_PHASE_SUPPORTED 1
#define SDMMC_LL_IOMUX_FUNC -1 /**
* SDMMC delay phase
*/
typedef enum { typedef enum {
SDMMC_LL_DELAY_PHASE_0, SDMMC_LL_DELAY_PHASE_0,
SDMMC_LL_DELAY_PHASE_1, SDMMC_LL_DELAY_PHASE_1,
@@ -94,6 +99,13 @@ typedef enum {
SDMMC_LL_DELAY_PHASE_3, SDMMC_LL_DELAY_PHASE_3,
} sdmmc_ll_delay_phase_t; } sdmmc_ll_delay_phase_t;
/**
* SDMMC speed mode
*/
typedef enum {
SDMMC_LL_SPEED_MODE_LS,
SDMMC_LL_SPEED_MODE_HS,
} sdmmc_ll_speed_mode_t;
/*--------------------------------------------------------------- /*---------------------------------------------------------------
Clock & Reset Clock & Reset
@@ -220,13 +232,15 @@ static inline void sdmmc_ll_init_phase_delay(sdmmc_dev_t *hw)
} }
/** /**
* @brief Set SDMMC din delay * @brief Set SDMMC din delay phase
* *
* @param hw hardware instance address * @param hw hardware instance address
* @param phase delay phase * @param phase delay phase
* @param mode speed mode
*/ */
static inline void sdmmc_ll_set_din_delay(sdmmc_dev_t *hw, sdmmc_ll_delay_phase_t phase) static inline void sdmmc_ll_set_din_delay_phase(sdmmc_dev_t *hw, sdmmc_ll_delay_phase_t phase, sdmmc_ll_speed_mode_t mode)
{ {
(void)mode;
switch (phase) { switch (phase) {
case SDMMC_LL_DELAY_PHASE_1: case SDMMC_LL_DELAY_PHASE_1:
hw->clock.phase_din = 0x1; hw->clock.phase_din = 0x1;
@@ -243,6 +257,18 @@ static inline void sdmmc_ll_set_din_delay(sdmmc_dev_t *hw, sdmmc_ll_delay_phase_
} }
} }
/**
* @brief Set SDMMC dout delay phase
*
* @param hw hardware instance address
* @param phase delay phase
* @param mode speed mode
*/
static inline void sdmmc_ll_set_dout_delay_phase(sdmmc_dev_t *hw, sdmmc_ll_delay_phase_t phase, sdmmc_ll_speed_mode_t mode)
{
//for compatibility
}
/** /**
* @brief Enable card clock * @brief Enable card clock
* *

39
components/hal/include/hal/sd_types.h
View File

@@ -36,6 +36,45 @@ typedef enum {
SD_SAMPLING_MODE_SDR, ///< Single data rate mode SD_SAMPLING_MODE_SDR, ///< Single data rate mode
SD_SAMPLING_MODE_DDR, ///< Double data rate mode SD_SAMPLING_MODE_DDR, ///< Double data rate mode
} sd_sampling_mode_t; } sd_sampling_mode_t;
/**
* @brief SD/MMC Host clock timing delay phases
*
* This will only take effect when the host works in
* - SDMMC_FREQ_HIGHSPEED
* - SDMMC_FREQ_52M
* - SDR50
* - DDR50
* - SDR104
* Driver will print out how long the delay is, in picosecond (ps).
*/
typedef enum {
SDMMC_DELAY_PHASE_0, /*!< Delay phase 0 */
SDMMC_DELAY_PHASE_1, /*!< Delay phase 1 */
SDMMC_DELAY_PHASE_2, /*!< Delay phase 2 */
SDMMC_DELAY_PHASE_3, /*!< Delay phase 3 */
SDMMC_DELAY_PHASE_4, /*!< Delay phase 4 */
SDMMC_DELAY_PHASE_5, /*!< Delay phase 5 */
SDMMC_DELAY_PHASE_6, /*!< Delay phase 6 */
SDMMC_DELAY_PHASE_7, /*!< Delay phase 7 */
SDMMC_DELAY_PHASE_AUTO, /*!< Auto detect phase, only valid for UHS-I modes */
} sdmmc_delay_phase_t;
/**
* @brief SD/MMC Host clock timing delay lines
*/
typedef enum {
SDMMC_DELAY_LINE_0, /*!< Delay line 0 */
SDMMC_DELAY_LINE_1, /*!< Delay line 1 */
SDMMC_DELAY_LINE_2, /*!< Delay line 2 */
SDMMC_DELAY_LINE_3, /*!< Delay line 3 */
SDMMC_DELAY_LINE_4, /*!< Delay line 4 */
SDMMC_DELAY_LINE_5, /*!< Delay line 5 */
SDMMC_DELAY_LINE_6, /*!< Delay line 6 */
SDMMC_DELAY_LINE_7, /*!< Delay line 7 */
SDMMC_DELAY_LINE_AUTO, /*!< Auto detect line */
} sdmmc_delay_line_t;
#if SOC_SDMMC_DATA_WIDTH_MAX #if SOC_SDMMC_DATA_WIDTH_MAX
#define SDMMC_DATA_SIG_NUM SOC_SDMMC_DATA_WIDTH_MAX ///< Number of data signals #define SDMMC_DATA_SIG_NUM SOC_SDMMC_DATA_WIDTH_MAX ///< Number of data signals
#else #else

10
components/sdmmc/include/esp_private/sdmmc_common.h
View File

@@ -62,7 +62,13 @@ extern "C" {
#define SDMMC_MMC_TRIM_ARG 1 #define SDMMC_MMC_TRIM_ARG 1
#define SDMMC_MMC_DISCARD_ARG 3 #define SDMMC_MMC_DISCARD_ARG 3
#define SDMMC_FREQ_SDR104 208000 /*!< MMC 208MHz speed */ /**
* Delay mode
*/
typedef enum {
SDMMC_DELAY_MODE_PHASE,
SDMMC_DELAY_MODE_LINE,
} sdmmc_delay_mode_t;
/* Functions to send individual commands */ /* Functions to send individual commands */
esp_err_t sdmmc_send_cmd(sdmmc_card_t* card, sdmmc_command_t* cmd); esp_err_t sdmmc_send_cmd(sdmmc_card_t* card, sdmmc_command_t* cmd);
@@ -97,7 +103,7 @@ esp_err_t sdmmc_read_sectors_dma(sdmmc_card_t* card, void* dst,
uint32_t sdmmc_get_erase_timeout_ms(const sdmmc_card_t* card, int arg, size_t erase_size_kb); uint32_t sdmmc_get_erase_timeout_ms(const sdmmc_card_t* card, int arg, size_t erase_size_kb);
esp_err_t sdmmc_select_driver_strength(sdmmc_card_t *card, sdmmc_driver_strength_t driver_strength); esp_err_t sdmmc_select_driver_strength(sdmmc_card_t *card, sdmmc_driver_strength_t driver_strength);
esp_err_t sdmmc_select_current_limit(sdmmc_card_t *card, sdmmc_current_limit_t current_limit); esp_err_t sdmmc_select_current_limit(sdmmc_card_t *card, sdmmc_current_limit_t current_limit);
esp_err_t sdmmc_do_timing_tuning(sdmmc_card_t *card); esp_err_t sdmmc_do_timing_tuning(sdmmc_card_t *card, sdmmc_delay_mode_t delay_mode);
/* SD specific */ /* SD specific */
esp_err_t sdmmc_check_scr(sdmmc_card_t* card); esp_err_t sdmmc_check_scr(sdmmc_card_t* card);

22
components/sdmmc/include/sd_protocol_types.h
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@@ -3,7 +3,7 @@
* *
* SPDX-License-Identifier: ISC * SPDX-License-Identifier: ISC
* *
* SPDX-FileContributor: 2016-2024 Espressif Systems (Shanghai) CO LTD * SPDX-FileContributor: 2016-2025 Espressif Systems (Shanghai) CO LTD
*/ */
/* /*
* Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
@@ -154,24 +154,6 @@ typedef struct {
void* volt_switch_cb_arg; /*!< argument to be passed to the CMD11 callback */ void* volt_switch_cb_arg; /*!< argument to be passed to the CMD11 callback */
} sdmmc_command_t; } sdmmc_command_t;
/**
* SD/MMC Host clock timing delay phases
*
* This will only take effect when the host works in
* - SDMMC_FREQ_HIGHSPEED
* - SDMMC_FREQ_52M
* - SDR50
* - DDR50
* Driver will print out how long the delay is, in picosecond (ps).
*/
typedef enum {
SDMMC_DELAY_PHASE_0, /*!< Delay phase 0 */
SDMMC_DELAY_PHASE_1, /*!< Delay phase 1 */
SDMMC_DELAY_PHASE_2, /*!< Delay phase 2 */
SDMMC_DELAY_PHASE_3, /*!< Delay phase 3 */
SDMMC_DELAY_PHASE_AUTO, /*!< Auto detect phase, only valid for UHS-I mode */
} sdmmc_delay_phase_t;
/** /**
* @brief SD/MMC Driver Strength * @brief SD/MMC Driver Strength
*/ */
@@ -220,6 +202,7 @@ typedef struct {
#define SDMMC_FREQ_26M 26000 /*!< MMC 26MHz speed */ #define SDMMC_FREQ_26M 26000 /*!< MMC 26MHz speed */
#define SDMMC_FREQ_DDR50 50000 /*!< MMC 50MHz speed */ #define SDMMC_FREQ_DDR50 50000 /*!< MMC 50MHz speed */
#define SDMMC_FREQ_SDR50 100000 /*!< MMC 100MHz speed */ #define SDMMC_FREQ_SDR50 100000 /*!< MMC 100MHz speed */
#define SDMMC_FREQ_SDR104 200000 /*!< MMC 200MHz speed */
float io_voltage; /*!< I/O voltage used by the controller (voltage switching is not supported) */ float io_voltage; /*!< I/O voltage used by the controller (voltage switching is not supported) */
sdmmc_driver_strength_t driver_strength; /*!< Driver Strength */ sdmmc_driver_strength_t driver_strength; /*!< Driver Strength */
sdmmc_current_limit_t current_limit; /*!< Current Limit */ sdmmc_current_limit_t current_limit; /*!< Current Limit */
@@ -240,6 +223,7 @@ typedef struct {
esp_err_t (*get_real_freq)(int slot, int* real_freq); /*!< Host function to provide real working freq, based on SDMMC controller setup */ esp_err_t (*get_real_freq)(int slot, int* real_freq); /*!< Host function to provide real working freq, based on SDMMC controller setup */
sdmmc_delay_phase_t input_delay_phase; /*!< input delay phase, this will only take into effect when the host works in SDMMC_FREQ_HIGHSPEED or SDMMC_FREQ_52M. Driver will print out how long the delay is*/ sdmmc_delay_phase_t input_delay_phase; /*!< input delay phase, this will only take into effect when the host works in SDMMC_FREQ_HIGHSPEED or SDMMC_FREQ_52M. Driver will print out how long the delay is*/
esp_err_t (*set_input_delay)(int slot, sdmmc_delay_phase_t delay_phase); /*!< set input delay phase */ esp_err_t (*set_input_delay)(int slot, sdmmc_delay_phase_t delay_phase); /*!< set input delay phase */
esp_err_t (*set_input_delayline)(int slot, sdmmc_delay_line_t delay_line); /*!< set input delay line */
void* dma_aligned_buffer; /*!< Leave it NULL. Reserved for cache aligned buffers for SDIO mode */ void* dma_aligned_buffer; /*!< Leave it NULL. Reserved for cache aligned buffers for SDIO mode */
sd_pwr_ctrl_handle_t pwr_ctrl_handle; /*!< Power control handle */ sd_pwr_ctrl_handle_t pwr_ctrl_handle; /*!< Power control handle */
esp_err_t (*get_dma_info)(int slot, esp_dma_mem_info_t *dma_mem_info); /*!< host function to dma memory information*/ esp_err_t (*get_dma_info)(int slot, esp_dma_mem_info_t *dma_mem_info); /*!< host function to dma memory information*/

7
components/sdmmc/sdmmc_common.c
View File

@@ -206,7 +206,12 @@ esp_err_t sdmmc_init_sd_current_limit(sdmmc_card_t *card)
esp_err_t sdmmc_init_sd_timing_tuning(sdmmc_card_t *card) esp_err_t sdmmc_init_sd_timing_tuning(sdmmc_card_t *card)
{ {
return sdmmc_do_timing_tuning(card); ESP_RETURN_ON_ERROR(sdmmc_do_timing_tuning(card, SDMMC_DELAY_MODE_PHASE), TAG, "failed to do phase timing tuning");
if (card->host.max_freq_khz == SDMMC_FREQ_SDR104) {
ESP_RETURN_ON_ERROR(sdmmc_do_timing_tuning(card, SDMMC_DELAY_MODE_LINE), TAG, "failed to do delayline timing tuning");
}
return ESP_OK;
} }
esp_err_t sdmmc_init_host_bus_width(sdmmc_card_t* card) esp_err_t sdmmc_init_host_bus_width(sdmmc_card_t* card)

65
components/sdmmc/sdmmc_sd.c
View File

@@ -21,6 +21,8 @@
#include "esp_cache.h" #include "esp_cache.h"
#include "esp_private/sdmmc_common.h" #include "esp_private/sdmmc_common.h"
#define SDMMC_DELAY_NUMS_MAX 10
static const char* TAG = "sdmmc_sd"; static const char* TAG = "sdmmc_sd";
esp_err_t sdmmc_init_sd_if_cond(sdmmc_card_t* card) esp_err_t sdmmc_init_sd_if_cond(sdmmc_card_t* card)
@@ -332,7 +334,7 @@ static const uint8_t s_tuning_block_pattern[] = {
* Find consecutive successful sampling points. * Find consecutive successful sampling points.
* e.g. array: {1, 1, 0, 0, 1, 1, 1, 0} * e.g. array: {1, 1, 0, 0, 1, 1, 1, 0}
* out_length: 3 * out_length: 3
* outout_end_index: 6 * out_end_index: 6
*/ */
static void find_max_consecutive_success_points(int *array, size_t size, size_t *out_length, uint32_t *out_end_index) static void find_max_consecutive_success_points(int *array, size_t size, size_t *out_length, uint32_t *out_end_index)
{ {
@@ -354,8 +356,17 @@ static void find_max_consecutive_success_points(int *array, size_t size, size_t
i++; i++;
} }
*out_length = match_num > max ? match_num : max; /**
*out_end_index = match_num == size ? size : end; * this is to deal with the case when the last points are consecutive 1, e.g.
* {1, 0, 0, 1, 1, 1, 1, 1, 1}
*/
if (match_num > max) {
max = match_num;
end = i - 1;
}
*out_length = max;
*out_end_index = end;
} }
static esp_err_t read_tuning_block(sdmmc_card_t *card) static esp_err_t read_tuning_block(sdmmc_card_t *card)
@@ -415,44 +426,64 @@ static esp_err_t read_tuning_block(sdmmc_card_t *card)
return success ? ESP_OK : ESP_FAIL; return success ? ESP_OK : ESP_FAIL;
} }
esp_err_t sdmmc_do_timing_tuning(sdmmc_card_t *card) esp_err_t sdmmc_do_timing_tuning(sdmmc_card_t *card, sdmmc_delay_mode_t delay_mode)
{ {
esp_err_t ret = ESP_FAIL; esp_err_t ret = ESP_FAIL;
ESP_RETURN_ON_FALSE(!host_is_spi(card), ESP_ERR_NOT_SUPPORTED, TAG, "sdspi not supported timing tuning"); ESP_RETURN_ON_FALSE(!host_is_spi(card), ESP_ERR_NOT_SUPPORTED, TAG, "sdspi not supported timing tuning");
ESP_RETURN_ON_FALSE(card->host.set_input_delay, ESP_ERR_NOT_SUPPORTED, TAG, "input phase delay feature isn't supported"); if (delay_mode == SDMMC_DELAY_MODE_PHASE) {
ESP_RETURN_ON_FALSE(card->host.set_input_delay, ESP_ERR_NOT_SUPPORTED, TAG, "phase delay feature isn't supported");
} else {
ESP_RETURN_ON_FALSE(card->host.set_input_delayline, ESP_ERR_NOT_SUPPORTED, TAG, "line delay feature isn't supported");
}
int results[SDMMC_DELAY_PHASE_AUTO] = {}; int results[SDMMC_DELAY_NUMS_MAX] = {};
int start_delay_item = (delay_mode == SDMMC_DELAY_MODE_PHASE) ? SDMMC_DELAY_PHASE_0 : SDMMC_DELAY_LINE_0;
int slot = card->host.slot; int slot = card->host.slot;
for (int i = SDMMC_DELAY_PHASE_0; i < SDMMC_DELAY_PHASE_AUTO; i++) { int delay_total_nums = 4;
ESP_RETURN_ON_ERROR((*card->host.set_input_delay)(slot, i), TAG, "failed to set input delay"); if (delay_mode == SDMMC_DELAY_MODE_PHASE) {
if (card->host.max_freq_khz == SDMMC_FREQ_SDR104) {
delay_total_nums = SDMMC_DELAY_PHASE_AUTO;
}
} else {
delay_total_nums = SDMMC_DELAY_LINE_AUTO;
}
for (int i = start_delay_item; i < delay_total_nums; i++) {
if (delay_mode == SDMMC_DELAY_MODE_PHASE) {
ESP_RETURN_ON_ERROR((*card->host.set_input_delay)(slot, i), TAG, "failed to set delay phase");
} else {
ESP_RETURN_ON_ERROR((*card->host.set_input_delayline)(slot, i), TAG, "failed to set delay line");
}
ret = read_tuning_block(card); ret = read_tuning_block(card);
if (ret == ESP_OK) { if (ret == ESP_OK) {
results[i] += 1; results[i] += 1;
} }
} }
for (int i = 0; i < 4; i++) { for (int i = 0; i < delay_total_nums; i++) {
ESP_LOGV(TAG, "results[%d]: %d", i, results[i]); ESP_LOGV(TAG, "results[%d]: %d", i, results[i]);
} }
size_t consecutive_len = 0; size_t consecutive_len = 0;
uint32_t end = 0; uint32_t end = 0;
find_max_consecutive_success_points(results, SDMMC_DELAY_PHASE_AUTO, &consecutive_len, &end); find_max_consecutive_success_points(results, delay_total_nums, &consecutive_len, &end);
sdmmc_delay_phase_t proper_delay_phase = SDMMC_DELAY_PHASE_AUTO; int proper_delay_id = SDMMC_DELAY_PHASE_AUTO;
if (consecutive_len == 1) { if (consecutive_len == 1) {
proper_delay_phase = end; proper_delay_id = end;
} else if (consecutive_len <= SDMMC_DELAY_PHASE_AUTO) { } else if (consecutive_len <= SDMMC_DELAY_PHASE_AUTO) {
proper_delay_phase = end / 2; proper_delay_id = end - (consecutive_len / 2);
} else { } else {
assert(false && "exceeds max tuning point"); assert(false && "exceeds max tuning point");
} }
ESP_LOGV(TAG, "%s: proper_delay_phase: %d\n", __func__, proper_delay_phase); ESP_LOGI(TAG, "%s: proper delay phase/line id: %d", __func__, proper_delay_id);
if (proper_delay_phase != SDMMC_DELAY_PHASE_AUTO) { if (proper_delay_id != SDMMC_DELAY_PHASE_AUTO) {
ESP_RETURN_ON_ERROR((*card->host.set_input_delay)(slot, proper_delay_phase), TAG, "failed to set input delay"); if (delay_mode == SDMMC_DELAY_MODE_PHASE) {
ESP_RETURN_ON_ERROR((*card->host.set_input_delay)(slot, proper_delay_id), TAG, "failed to set delay phase");
} else {
ESP_RETURN_ON_ERROR((*card->host.set_input_delayline)(slot, proper_delay_id), TAG, "failed to set delay line");
}
} }
return ESP_OK; return ESP_OK;

3
examples/storage/sd_card/sdmmc/main/Kconfig.projbuild
View File

@@ -42,6 +42,9 @@ menu "SD/MMC Example Configuration"
config EXAMPLE_SDMMC_SPEED_UHS_I_DDR50 config EXAMPLE_SDMMC_SPEED_UHS_I_DDR50
bool "UHS-I DDR50 (50 MHz, 50 MB/s)" bool "UHS-I DDR50 (50 MHz, 50 MB/s)"
depends on SOC_SDMMC_UHS_I_SUPPORTED depends on SOC_SDMMC_UHS_I_SUPPORTED
config EXAMPLE_SDMMC_SPEED_UHS_I_SDR104
bool "UHS-I SDR104 (200 MHz, 100 MB/s)"
depends on SOC_SDMMC_UHS_I_SUPPORTED
endchoice endchoice
if SOC_SDMMC_USE_GPIO_MATRIX if SOC_SDMMC_USE_GPIO_MATRIX

6
examples/storage/sd_card/sdmmc/main/sd_card_example_main.c
View File

@@ -24,7 +24,7 @@
static const char *TAG = "example"; static const char *TAG = "example";
#define MOUNT_POINT "/sdcard" #define MOUNT_POINT "/sdcard"
#define EXAMPLE_IS_UHS1 (CONFIG_EXAMPLE_SDMMC_SPEED_UHS_I_SDR50 || CONFIG_EXAMPLE_SDMMC_SPEED_UHS_I_DDR50) #define EXAMPLE_IS_UHS1 (CONFIG_EXAMPLE_SDMMC_SPEED_UHS_I_SDR50 || CONFIG_EXAMPLE_SDMMC_SPEED_UHS_I_DDR50 || CONFIG_EXAMPLE_SDMMC_SPEED_UHS_I_SDR104)
#ifdef CONFIG_EXAMPLE_DEBUG_PIN_CONNECTIONS #ifdef CONFIG_EXAMPLE_DEBUG_PIN_CONNECTIONS
const char* names[] = {"CLK", "CMD", "D0", "D1", "D2", "D3"}; const char* names[] = {"CLK", "CMD", "D0", "D1", "D2", "D3"};
@@ -138,6 +138,10 @@ void app_main(void)
#elif CONFIG_EXAMPLE_SDMMC_SPEED_UHS_I_DDR50 #elif CONFIG_EXAMPLE_SDMMC_SPEED_UHS_I_DDR50
host.slot = SDMMC_HOST_SLOT_0; host.slot = SDMMC_HOST_SLOT_0;
host.max_freq_khz = SDMMC_FREQ_DDR50; host.max_freq_khz = SDMMC_FREQ_DDR50;
#elif CONFIG_EXAMPLE_SDMMC_SPEED_UHS_I_SDR104
host.slot = SDMMC_HOST_SLOT_0;
host.max_freq_khz = SDMMC_FREQ_SDR104;
host.flags &= ~SDMMC_HOST_FLAG_DDR;
#endif #endif
// For SoCs where the SD power can be supplied both via an internal or external (e.g. on-board LDO) power supply. // For SoCs where the SD power can be supplied both via an internal or external (e.g. on-board LDO) power supply.