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mspi: make cpu clock source switch safe
For some of the MSPI high frequency setting (e.g. 80M DDR mode Flash or PSRAM), timing tuning is required. Certain delays will be added to the MSPI RX direction. When system clock switches down, the delays should be cleared. When system clock switches up, the delays should be restored.
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@@ -17,6 +17,7 @@
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#include "soc/soc.h"
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#if CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/spi_timing_config.h"
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#include "esp32s3/rom/cache.h"
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#endif
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#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(*(arr)))
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@@ -377,6 +378,7 @@ void spi_timing_psram_tuning(void)
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}
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#endif //SPI_TIMING_PSRAM_NEEDS_TUNING
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/*------------------------------------------------------------------------------
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* APIs to make SPI0 (and SPI1) FLASH work for high/low freq
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*----------------------------------------------------------------------------*/
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@@ -460,9 +462,33 @@ void spi_timing_enter_mspi_high_speed_mode(bool control_spi1)
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#endif
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}
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/**
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* Should be only used by SPI1 Flash driver to know the necessary timing registers
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*/
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void spi_timing_change_speed_mode_cache_safe(bool switch_down)
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{
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Cache_Freeze_ICache_Enable(1);
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Cache_Freeze_DCache_Enable(1);
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if (switch_down) {
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//enter MSPI low speed mode, extra delays should be removed
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spi_timing_enter_mspi_low_speed_mode(false);
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} else {
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//enter MSPI high speed mode, extra delays should be considered
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spi_timing_enter_mspi_high_speed_mode(false);
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}
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Cache_Freeze_DCache_Disable();
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Cache_Freeze_ICache_Disable();
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}
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/*------------------------------------------------------------------------------
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* APIs to inform SPI1 Flash driver of necessary timing configurations
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*----------------------------------------------------------------------------*/
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bool spi_timing_is_tuned(void)
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{
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#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
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return true;
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#else
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return false;
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#endif
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}
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#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
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void spi_timing_get_flash_timing_param(spi_flash_hal_timing_config_t *out_timing_config)
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{
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