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soc: update iram/dram addr range in ext_mem_defs.h

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IRAM0/DRAM0 addr range update, on s3, c3, c2, h4, c6:

IRAM0_ADDRESS_LOW ~ IRAM0_ADDRESS_HIGH
DRAM0_ADDRESS_LOW ~ DRAM0_ADDRESS_HIGH

now are for the real IRAM0 and DRAM0
This commit is contained in:
Armando
2022-11-22 12:02:24 +08:00
parent ad52655558
commit c3682bf0a4
5 changed files with 30 additions and 32 deletions
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16
components/soc/esp32c6/include/soc/ext_mem_defs.h
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@@ -13,16 +13,14 @@
extern "C" {
#endif
/*IRAM0 is connected with Cache IBUS0*/
#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
#define IRAM0_CACHE_ADDRESS_HIGH(page_size) (IRAM0_CACHE_ADDRESS_LOW + ((page_size) * 256))
#define IRAM0_ADDRESS_LOW 0x40000000
#define IRAM0_ADDRESS_HIGH(page_size) IRAM0_CACHE_ADDRESS_HIGH(page_size)
#define IRAM0_ADDRESS_LOW 0x40800000
#define IRAM0_ADDRESS_HIGH 0x40880000
#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
#define IRAM0_CACHE_ADDRESS_HIGH(page_size) (IRAM0_CACHE_ADDRESS_LOW + ((page_size) * 256))
/*DRAM0 is connected with Cache DBUS0*/
#define DRAM0_ADDRESS_LOW 0x42000000
#define DRAM0_ADDRESS_HIGH 0x43000000
#define DRAM0_CACHE_ADDRESS_LOW IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range
#define DRAM0_ADDRESS_LOW IRAM0_ADDRESS_LOW //I/D share the same vaddr range
#define DRAM0_ADDRESS_HIGH IRAM0_ADDRESS_HIGH //I/D share the same vaddr range
#define DRAM0_CACHE_ADDRESS_LOW IRAM0_CACHE_ADDRESS_LOW //I/D share the same vaddr range
#define DRAM0_CACHE_ADDRESS_HIGH(page_size) IRAM0_CACHE_ADDRESS_HIGH(page_size) //I/D share the same vaddr range
#define DRAM0_CACHE_OPERATION_HIGH(page_size) DRAM0_CACHE_ADDRESS_HIGH(page_size)
#define ESP_CACHE_TEMP_ADDR 0x42000000