From 0c817d92385911d2c9ee79245b5bfa0034c5b7ca Mon Sep 17 00:00:00 2001 From: hongshuqing Date: Thu, 8 Aug 2024 17:25:39 +0800 Subject: [PATCH 1/2] fix(bootloader): update random disable api for ESP32-C5 --- components/bootloader_support/src/bootloader_random_esp32c5.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/components/bootloader_support/src/bootloader_random_esp32c5.c b/components/bootloader_support/src/bootloader_random_esp32c5.c index c2b93bacfe..6541b8deb0 100644 --- a/components/bootloader_support/src/bootloader_random_esp32c5.c +++ b/components/bootloader_support/src/bootloader_random_esp32c5.c @@ -94,9 +94,6 @@ void bootloader_random_disable(void) REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_EN_TOUT_ADDR, 0); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_EN_TOUT_ADDR, 0); - // Revert PMU_RF_PWC_REG to it's initial value - CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB); - // disable ADC_CTRL_CLK (SAR ADC function clock) REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000); From f38f77a7fc3af411e6adf0754e770fa028ffddeb Mon Sep 17 00:00:00 2001 From: Mahavir Jain Date: Mon, 12 Aug 2024 08:26:05 +0530 Subject: [PATCH 2/2] fix(rng): avoid clearing `PMU_PERIF_I2C_RSTB` in random disable API for C6 This configuration bit is required for ADC operation as well and hence should not be cleared in the RNG API sequence. Ideally, the ADC driver should take care of initializing this bit but still the RNG layer change is required because of interleaved API usage scenario described in following linked issue. Closes https://github.com/espressif/esp-idf/issues/14124 Closes https://github.com/espressif/esp-idf/issues/14280 --- components/bootloader_support/src/bootloader_random_esp32c6.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/components/bootloader_support/src/bootloader_random_esp32c6.c b/components/bootloader_support/src/bootloader_random_esp32c6.c index 0efd9d4c08..fec85a6a40 100644 --- a/components/bootloader_support/src/bootloader_random_esp32c6.c +++ b/components/bootloader_support/src/bootloader_random_esp32c6.c @@ -88,9 +88,6 @@ void bootloader_random_disable(void) REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0); REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0); - // Revert PMU_RF_PWC_REG to it's initial value - CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB); - // disable ADC_CTRL_CLK (SAR ADC function clock) REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);