From 0722386585b88f1d780097c8b5dec63470d09146 Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Fri, 12 May 2023 18:32:24 +0800 Subject: [PATCH 1/2] esp-system: fixed int WDT reset reason being reported as task WDT on C2 --- components/esp_system/port/soc/esp32c2/reset_reason.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_system/port/soc/esp32c2/reset_reason.c b/components/esp_system/port/soc/esp32c2/reset_reason.c index 29099e24f8..494707fb0f 100644 --- a/components/esp_system/port/soc/esp32c2/reset_reason.c +++ b/components/esp_system/port/soc/esp32c2/reset_reason.c @@ -34,7 +34,7 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason, return ESP_RST_DEEPSLEEP; case RESET_REASON_CORE_MWDT0: - return ESP_RST_TASK_WDT; + return ESP_RST_INT_WDT; case RESET_REASON_CORE_RTC_WDT: case RESET_REASON_SYS_RTC_WDT: From 3720ea91c3512befe1450b3cecc357f107e0a685 Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Fri, 12 May 2023 19:00:27 +0800 Subject: [PATCH 2/2] ci: re-enable reset reason tests for all targets except H2. --- .../esp_system/test/test_reset_reason.c | 39 ++++++++++++++++--- 1 file changed, 33 insertions(+), 6 deletions(-) diff --git a/components/esp_system/test/test_reset_reason.c b/components/esp_system/test/test_reset_reason.c index 984d790059..fe40062cc4 100644 --- a/components/esp_system/test/test_reset_reason.c +++ b/components/esp_system/test/test_reset_reason.c @@ -13,6 +13,9 @@ #define CHECK_VALUE 0x89abcdef +#if CONFIG_SOC_RTC_FAST_MEM_SUPPORTED || CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED +#define CHECK_RTC_MEM 1 +#endif //CONFIG_SOC_RTC_FAST_MEM_SUPPORTED || CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED #if CONFIG_IDF_TARGET_ESP32 #define DEEPSLEEP "DEEPSLEEP_RESET" @@ -38,7 +41,7 @@ #define BROWNOUT "BROWN_OUT_RST" #define STORE_ERROR "StoreProhibited" -#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 #define DEEPSLEEP "DSLEEP" #define LOAD_STORE_ERROR "Store access fault" #define RESET "RTC_SW_CPU_RST" @@ -47,6 +50,15 @@ #define RTC_WDT "RTCWDT_RTC_RST" #define BROWNOUT "BROWNOUT_RST" #define STORE_ERROR LOAD_STORE_ERROR +#elif CONFIG_IDF_TARGET_ESP32C2 +#define DEEPSLEEP "DSLEEP" +#define LOAD_STORE_ERROR "Store access fault" +#define RESET "RTC_SW_CPU_RST" +#define INT_WDT_PANIC "Interrupt wdt timeout on CPU0" +#define INT_WDT "TG0WDT_SYS_RST" +#define RTC_WDT "RTCWDT_RTC_RST" +#define BROWNOUT "BROWNOUT_RST" +#define STORE_ERROR LOAD_STORE_ERROR #endif // CONFIG_IDF_TARGET_ESP32 @@ -60,9 +72,9 @@ TEST_CASE("reset reason ESP_RST_POWERON", "[reset][ignore]") } -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) -//IDF-5059 static __NOINIT_ATTR uint32_t s_noinit_val; + +#if CHECK_RTC_MEM static RTC_NOINIT_ATTR uint32_t s_rtc_noinit_val; static RTC_DATA_ATTR uint32_t s_rtc_data_val; static RTC_BSS_ATTR uint32_t s_rtc_bss_val; @@ -73,10 +85,12 @@ static RTC_BSS_ATTR uint32_t s_rtc_bss_val; static RTC_RODATA_ATTR uint32_t s_rtc_rodata_val = CHECK_VALUE; static RTC_FAST_ATTR uint32_t s_rtc_force_fast_val; static RTC_SLOW_ATTR uint32_t s_rtc_force_slow_val; +#endif //CHECK_RTC_MEM static void setup_values(void) { s_noinit_val = CHECK_VALUE; +#if CHECK_RTC_MEM s_rtc_noinit_val = CHECK_VALUE; s_rtc_data_val = CHECK_VALUE; s_rtc_bss_val = CHECK_VALUE; @@ -84,9 +98,9 @@ static void setup_values(void) "s_rtc_rodata_val should already be set up"); s_rtc_force_fast_val = CHECK_VALUE; s_rtc_force_slow_val = CHECK_VALUE; +#endif //CHECK_RTC_MEM } -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) static void do_deep_sleep(void) { setup_values(); @@ -98,18 +112,20 @@ static void check_reset_reason_deep_sleep(void) { TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason()); +#if CHECK_RTC_MEM TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_noinit_val); TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_data_val); TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_bss_val); TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_rodata_val); TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_force_fast_val); TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_force_slow_val); +#endif //CHECK_RTC_MEM + } TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_DEEPSLEEP", "[reset_reason][reset="DEEPSLEEP"]", do_deep_sleep, check_reset_reason_deep_sleep); -#endif // TEMPORARY_DISABLED_FOR_TARGETS static void do_exception(void) { @@ -128,12 +144,14 @@ static void check_reset_reason_panic(void) TEST_ASSERT_EQUAL(ESP_RST_PANIC, esp_reset_reason()); TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_noinit_val); +#if CHECK_RTC_MEM TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_noinit_val); TEST_ASSERT_EQUAL_HEX32(0, s_rtc_data_val); TEST_ASSERT_EQUAL_HEX32(0, s_rtc_bss_val); TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_rodata_val); TEST_ASSERT_EQUAL_HEX32(0, s_rtc_force_fast_val); TEST_ASSERT_EQUAL_HEX32(0, s_rtc_force_slow_val); +#endif //CHECK_RTC_MEM } TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_PANIC after exception", "[reset_reason][reset="LOAD_STORE_ERROR","RESET"]", @@ -164,12 +182,14 @@ static void check_reset_reason_sw(void) TEST_ASSERT_EQUAL(ESP_RST_SW, esp_reset_reason()); TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_noinit_val); +#if CHECK_RTC_MEM TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_noinit_val); TEST_ASSERT_EQUAL_HEX32(0, s_rtc_data_val); TEST_ASSERT_EQUAL_HEX32(0, s_rtc_bss_val); TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_rodata_val); TEST_ASSERT_EQUAL_HEX32(0, s_rtc_force_fast_val); TEST_ASSERT_EQUAL_HEX32(0, s_rtc_force_slow_val); +#endif //CHECK_RTC_MEM } TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_SW after restart", "[reset_reason][reset="RESET"]", @@ -209,7 +229,9 @@ static void do_int_wdt_hw(void) static void check_reset_reason_int_wdt(void) { TEST_ASSERT_EQUAL(ESP_RST_INT_WDT, esp_reset_reason()); +#if CHECK_RTC_MEM TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_noinit_val); +#endif //CHECK_RTC_MEM } TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_INT_WDT after interrupt watchdog (panic)", @@ -240,12 +262,14 @@ static void check_reset_reason_task_wdt(void) TEST_ASSERT_EQUAL(ESP_RST_TASK_WDT, esp_reset_reason()); TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_noinit_val); +#if CHECK_RTC_MEM TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_noinit_val); TEST_ASSERT_EQUAL_HEX32(0, s_rtc_data_val); TEST_ASSERT_EQUAL_HEX32(0, s_rtc_bss_val); TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_rodata_val); TEST_ASSERT_EQUAL_HEX32(0, s_rtc_force_fast_val); TEST_ASSERT_EQUAL_HEX32(0, s_rtc_force_slow_val); +#endif //CHECK_RTC_MEM } TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_TASK_WDT after task watchdog", @@ -271,7 +295,9 @@ static void do_rtc_wdt(void) static void check_reset_reason_any_wdt(void) { TEST_ASSERT_EQUAL(ESP_RST_WDT, esp_reset_reason()); +#if CHECK_RTC_MEM TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_noinit_val); +#endif //CHECK_RTC_MEM } TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_WDT after RTC watchdog", @@ -292,12 +318,14 @@ static void check_reset_reason_brownout(void) TEST_ASSERT_EQUAL(ESP_RST_BROWNOUT, esp_reset_reason()); TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_noinit_val); +#if CHECK_RTC_MEM TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_noinit_val); TEST_ASSERT_EQUAL_HEX32(0, s_rtc_data_val); TEST_ASSERT_EQUAL_HEX32(0, s_rtc_bss_val); TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_rodata_val); TEST_ASSERT_EQUAL_HEX32(0, s_rtc_force_fast_val); TEST_ASSERT_EQUAL_HEX32(0, s_rtc_force_slow_val); +#endif //CHECK_RTC_MEM } TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_BROWNOUT after brownout event", @@ -305,7 +333,6 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_BROWNOUT after brownout event", do_brownout, check_reset_reason_brownout); -#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2) #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY