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Merge branch 'fix/esp32s3_ununsed_dcache_as_dram_v5.1' into 'release/v5.1'

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esp_hw_support: Update the memory ptr location/property checks to include the unused DCACHE added to DRAM (v5.1)

See merge request espressif/esp-idf!23303
This commit is contained in:
Mahavir Jain
2023-04-27 22:09:55 +08:00
parent 1a03cb02c2 16f3317496
commit c49dce48eb
3 changed files with 32 additions and 2 deletions
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9
components/esp_hw_support/esp_memory_utils.c
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@ -42,6 +42,15 @@ bool esp_ptr_byte_accessible(const void *p)
#endif #endif
#if CONFIG_SPIRAM #if CONFIG_SPIRAM
r |= esp_psram_check_ptr_addr(p); r |= esp_psram_check_ptr_addr(p);
#endif
#if CONFIG_ESP32S3_DATA_CACHE_16KB
/* For ESP32-S3, when the DCACHE size is set to 16 kB, the unused 48 kB is
* added to the heap in 2 blocks of 32 kB (from 0x3FCF0000) and 16 kB
* (from 0x3C000000 (SOC_DROM_LOW) - 0x3C004000).
* Though this memory lies in the external memory vaddr, it is no different
* from the internal RAM in terms of hardware attributes. It is a part of
* the internal RAM when added to the heap and is byte-accessible .*/
r |= (ip >= SOC_DROM_LOW && ip < (SOC_DROM_LOW + 0x4000));
#endif #endif
return r; return r;
} }

23
components/esp_hw_support/include/esp_memory_utils.h
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@ -256,6 +256,17 @@ inline static bool esp_ptr_internal(const void *p) {
* additional check is required */ * additional check is required */
r |= ((intptr_t)p >= SOC_RTC_DRAM_LOW && (intptr_t)p < SOC_RTC_DRAM_HIGH); r |= ((intptr_t)p >= SOC_RTC_DRAM_LOW && (intptr_t)p < SOC_RTC_DRAM_HIGH);
#endif #endif
#if CONFIG_ESP32S3_DATA_CACHE_16KB
/* For ESP32-S3, when the DCACHE size is set to 16 kB, the unused 48 kB is
* added to the heap in 2 blocks of 32 kB (from 0x3FCF0000) and 16 kB
* (from 0x3C000000 (SOC_DROM_LOW) - 0x3C004000).
* Though this memory lies in the external memory vaddr, it is no different
* from the internal RAM in terms of hardware attributes and it is a part of
* the internal RAM when added to the heap.*/
r |= ((intptr_t)p >= SOC_DROM_LOW && (intptr_t)p < (SOC_DROM_LOW + 0x4000));
#endif
return r; return r;
} }
@ -277,7 +288,17 @@ bool esp_ptr_external_ram(const void *p);
*/ */
__attribute__((always_inline)) __attribute__((always_inline))
inline static bool esp_ptr_in_drom(const void *p) { inline static bool esp_ptr_in_drom(const void *p) {
return ((intptr_t)p >= SOC_DROM_LOW && (intptr_t)p < SOC_DROM_HIGH); uint32_t drom_start_addr = SOC_DROM_LOW;
#if CONFIG_ESP32S3_DATA_CACHE_16KB
/* For ESP32-S3, when the DCACHE size is set to 16 kB, the unused 48 kB is
* added to the heap in 2 blocks of 32 kB (from 0x3FCF0000) and 16 kB
* (from 0x3C000000 (SOC_DROM_LOW) - 0x3C004000).
* The drom_start_addr has to be moved by 0x4000 (16kB) to accomodate
* this addition. */
drom_start_addr += 0x4000;
#endif
return ((intptr_t)p >= drom_start_addr && (intptr_t)p < SOC_DROM_HIGH);
} }
/** /**

2
components/soc/esp32s3/include/soc/soc.h
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@ -218,7 +218,7 @@
//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs //Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
//(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). //(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
#define SOC_MEM_INTERNAL_LOW 0x3FC88000 #define SOC_MEM_INTERNAL_LOW 0x3FC88000
#define SOC_MEM_INTERNAL_HIGH 0x403E2000 #define SOC_MEM_INTERNAL_HIGH 0x403E0000
// Start (highest address) of ROM boot stack, only relevant during early boot // Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x3fceb710 #define SOC_ROM_STACK_START 0x3fceb710