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change(driver): reformat driver component with astyle_py

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This commit is contained in:
morris
2024-02-23 17:28:52 +08:00
parent 603bc0536c
commit c65fbbdf71
43 changed files with 704 additions and 749 deletions
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1
components/driver/deprecated/adc1_private.h
View File

@@ -12,7 +12,6 @@ extern "C" {
#include "esp_err.h"
/**
* @brief For I2S dma to claim the usage of ADC1.
*

4
components/driver/deprecated/adc_dma_legacy.c
View File

@@ -285,7 +285,7 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config)
dma_chan = s_adc_digi_ctx->spi_dma_ctx->rx_dma_chan.chan_id;
ret = esp_intr_alloc(spicommon_irqdma_source_for_host(s_adc_digi_ctx->spi_host), 0, adc_dma_intr_handler,
(void *)s_adc_digi_ctx, &s_adc_digi_ctx->intr_hdl);
(void *)s_adc_digi_ctx, &s_adc_digi_ctx->intr_hdl);
if (ret != ESP_OK) {
goto cleanup;
}
@@ -300,7 +300,7 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config)
s_adc_digi_ctx->i2s_host = I2S_NUM_0;
ret = esp_intr_alloc(i2s_periph_signal[s_adc_digi_ctx->i2s_host].irq, 0, adc_dma_intr_handler,
(void *)s_adc_digi_ctx, &s_adc_digi_ctx->intr_hdl);
(void *)s_adc_digi_ctx, &s_adc_digi_ctx->intr_hdl);
if (ret != ESP_OK) {
goto cleanup;
}

31
components/driver/deprecated/adc_i2s_deprecated.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -50,7 +50,6 @@ extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate posi
esp_pm_lock_handle_t adc_digi_arbiter_lock = NULL;
#endif //CONFIG_PM_ENABLE
#if CONFIG_IDF_TARGET_ESP32
/*---------------------------------------------------------------
ESP32 Depricated ADC APIs and functions
@@ -149,20 +148,20 @@ static void adc_digi_controller_reg_set(const adc_digi_config_t *cfg)
{
/* On ESP32, only support ADC1 */
switch (cfg->conv_mode) {
case ADC_CONV_SINGLE_UNIT_1:
adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_ONLY_ADC1);
break;
case ADC_CONV_SINGLE_UNIT_2:
adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_ONLY_ADC2);
break;
case ADC_CONV_BOTH_UNIT:
adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_BOTH_UNIT);
break;
case ADC_CONV_ALTER_UNIT:
adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_ALTER_UNIT);
break;
default:
abort();
case ADC_CONV_SINGLE_UNIT_1:
adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_ONLY_ADC1);
break;
case ADC_CONV_SINGLE_UNIT_2:
adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_ONLY_ADC2);
break;
case ADC_CONV_BOTH_UNIT:
adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_BOTH_UNIT);
break;
case ADC_CONV_ALTER_UNIT:
adc_ll_digi_set_convert_mode(ADC_LL_DIGI_CONV_ALTER_UNIT);
break;
default:
abort();
}
if (cfg->conv_mode & ADC_CONV_SINGLE_UNIT_1) {

109
components/driver/deprecated/adc_legacy.c
View File

@@ -39,7 +39,6 @@
#include "esp_efuse_rtc_calib.h"
#endif
static const char *ADC_TAG = "ADC";
#define ADC_GET_IO_NUM(periph, channel) (adc_channel_io_map[periph][channel])
@@ -78,7 +77,6 @@ static _lock_t adc1_dma_lock;
#define SARADC1_RELEASE() _lock_release( &adc1_dma_lock )
#endif
/*
In ADC2, there're two locks used for different cases:
1. lock shared with app and Wi-Fi:
@@ -218,21 +216,21 @@ esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t width_bit)
if ((uint32_t)width_bit == (uint32_t)ADC_BITWIDTH_DEFAULT) {
bitwidth = SOC_ADC_RTC_MAX_BITWIDTH;
} else {
switch(width_bit) {
case ADC_WIDTH_BIT_9:
bitwidth = ADC_BITWIDTH_9;
break;
case ADC_WIDTH_BIT_10:
bitwidth = ADC_BITWIDTH_10;
break;
case ADC_WIDTH_BIT_11:
bitwidth = ADC_BITWIDTH_11;
break;
case ADC_WIDTH_BIT_12:
bitwidth = ADC_BITWIDTH_12;
break;
default:
return ESP_ERR_INVALID_ARG;
switch (width_bit) {
case ADC_WIDTH_BIT_9:
bitwidth = ADC_BITWIDTH_9;
break;
case ADC_WIDTH_BIT_10:
bitwidth = ADC_BITWIDTH_10;
break;
case ADC_WIDTH_BIT_11:
bitwidth = ADC_BITWIDTH_11;
break;
case ADC_WIDTH_BIT_12:
bitwidth = ADC_BITWIDTH_12;
break;
default:
return ESP_ERR_INVALID_ARG;
}
}
#elif CONFIG_IDF_TARGET_ESP32S2
@@ -307,21 +305,21 @@ esp_err_t adc1_config_width(adc_bits_width_t width_bit)
if ((uint32_t)width_bit == (uint32_t)ADC_BITWIDTH_DEFAULT) {
bitwidth = SOC_ADC_RTC_MAX_BITWIDTH;
} else {
switch(width_bit) {
case ADC_WIDTH_BIT_9:
bitwidth = ADC_BITWIDTH_9;
break;
case ADC_WIDTH_BIT_10:
bitwidth = ADC_BITWIDTH_10;
break;
case ADC_WIDTH_BIT_11:
bitwidth = ADC_BITWIDTH_11;
break;
case ADC_WIDTH_BIT_12:
bitwidth = ADC_BITWIDTH_12;
break;
default:
return ESP_ERR_INVALID_ARG;
switch (width_bit) {
case ADC_WIDTH_BIT_9:
bitwidth = ADC_BITWIDTH_9;
break;
case ADC_WIDTH_BIT_10:
bitwidth = ADC_BITWIDTH_10;
break;
case ADC_WIDTH_BIT_11:
bitwidth = ADC_BITWIDTH_11;
break;
case ADC_WIDTH_BIT_12:
bitwidth = ADC_BITWIDTH_12;
break;
default:
return ESP_ERR_INVALID_ARG;
}
}
#elif CONFIG_IDF_TARGET_ESP32S2
@@ -342,7 +340,7 @@ esp_err_t adc1_dma_mode_acquire(void)
/* Use locks to avoid digtal and RTC controller conflicts.
for adc1, block until acquire the lock. */
SARADC1_ACQUIRE();
ESP_LOGD( ADC_TAG, "dma mode takes adc1 lock." );
ESP_LOGD(ADC_TAG, "dma mode takes adc1 lock.");
sar_periph_ctrl_adc_continuous_power_acquire();
@@ -484,19 +482,19 @@ static inline void adc2_init(void)
#endif //CONFIG_IDF_TARGET_ESP32S2
}
static inline void adc2_dac_disable( adc2_channel_t channel)
static inline void adc2_dac_disable(adc2_channel_t channel)
{
#if SOC_DAC_SUPPORTED
#ifdef CONFIG_IDF_TARGET_ESP32
if ( channel == ADC2_CHANNEL_8 ) { // the same as DAC channel 0
if (channel == ADC2_CHANNEL_8) { // the same as DAC channel 0
dac_ll_power_down(DAC_CHAN_0);
} else if ( channel == ADC2_CHANNEL_9 ) {
} else if (channel == ADC2_CHANNEL_9) {
dac_ll_power_down(DAC_CHAN_1);
}
#else
if ( channel == ADC2_CHANNEL_6 ) { // the same as DAC channel 0
if (channel == ADC2_CHANNEL_6) { // the same as DAC channel 0
dac_ll_power_down(DAC_CHAN_0);
} else if ( channel == ADC2_CHANNEL_7 ) {
} else if (channel == ADC2_CHANNEL_7) {
dac_ll_power_down(DAC_CHAN_1);
}
#endif
@@ -522,21 +520,21 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
if ((uint32_t)width_bit == (uint32_t)ADC_BITWIDTH_DEFAULT) {
bitwidth = SOC_ADC_RTC_MAX_BITWIDTH;
} else {
switch(width_bit) {
case ADC_WIDTH_BIT_9:
bitwidth = ADC_BITWIDTH_9;
break;
case ADC_WIDTH_BIT_10:
bitwidth = ADC_BITWIDTH_10;
break;
case ADC_WIDTH_BIT_11:
bitwidth = ADC_BITWIDTH_11;
break;
case ADC_WIDTH_BIT_12:
bitwidth = ADC_BITWIDTH_12;
break;
default:
return ESP_ERR_INVALID_ARG;
switch (width_bit) {
case ADC_WIDTH_BIT_9:
bitwidth = ADC_BITWIDTH_9;
break;
case ADC_WIDTH_BIT_10:
bitwidth = ADC_BITWIDTH_10;
break;
case ADC_WIDTH_BIT_11:
bitwidth = ADC_BITWIDTH_11;
break;
case ADC_WIDTH_BIT_12:
bitwidth = ADC_BITWIDTH_12;
break;
default:
return ESP_ERR_INVALID_ARG;
}
}
#elif CONFIG_IDF_TARGET_ESP32S2
@@ -650,7 +648,6 @@ esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio)
#endif //SOC_ADC_RTC_CTRL_SUPPORTED
#endif //#if (SOC_ADC_PERIPH_NUM >= 2)
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
/*---------------------------------------------------------------
Legacy ADC Single Read Mode
@@ -667,7 +664,6 @@ static adc_atten_t s_atten1_single[ADC1_CHANNEL_MAX]; //Array saving attenuat
static adc_atten_t s_atten2_single[ADC2_CHANNEL_MAX]; //Array saving attenuate of each channel of ADC2, used by single read API
#endif
static int8_t adc_digi_get_io_num(adc_unit_t adc_unit, uint8_t adc_channel)
{
assert(adc_unit < SOC_ADC_PERIPH_NUM);
@@ -860,7 +856,6 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
#endif //#if (SOC_ADC_PERIPH_NUM >= 2)
#endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
static void adc_hal_onetime_start(adc_unit_t adc_n, uint32_t clk_src_freq_hz)
{
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
@@ -876,7 +871,7 @@ static void adc_hal_onetime_start(adc_unit_t adc_n, uint32_t clk_src_freq_hz)
//3 ADC digital controller clock cycle
delay = delay * 3;
//This coefficient (8) is got from test, and verified from DT. When digi_clk is not smaller than ``APB_CLK_FREQ/8``, no delay is needed.
if (digi_clk >= APB_CLK_FREQ/8) {
if (digi_clk >= APB_CLK_FREQ / 8) {
delay = 0;
}

1
components/driver/deprecated/dac_common_legacy.c
View File

@@ -4,7 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include "esp_check.h"
#include "freertos/FreeRTOS.h"

1
components/driver/deprecated/driver/adc.h
View File

@@ -278,7 +278,6 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio);
#endif //#if (SOC_ADC_PERIPH_NUM >= 2)
/*---------------------------------------------------------------
ADC DMA Read Setting
---------------------------------------------------------------*/

1
components/driver/deprecated/driver/i2s.h
View File

@@ -378,7 +378,6 @@ esp_err_t i2s_adc_disable(i2s_port_t i2s_num);
esp_err_t i2s_set_dac_mode(i2s_dac_mode_t dac_mode);
#endif //SOC_I2S_SUPPORTS_DAC
#ifdef __cplusplus
}
#endif

1
components/driver/deprecated/driver/i2s_types_legacy.h
View File

@@ -207,7 +207,6 @@ typedef struct {
} i2s_pdm_tx_upsample_cfg_t;
#endif
/**
* @brief I2S driver configuration parameters
*

2
components/driver/deprecated/driver/mcpwm.h
View File

@@ -64,7 +64,7 @@ esp_err_t mcpwm_set_pin(mcpwm_unit_t mcpwm_num, const mcpwm_pin_config_t *mcpwm_
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t mcpwm_init( mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpwm_config_t *mcpwm_conf);
esp_err_t mcpwm_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpwm_config_t *mcpwm_conf);
/**
* @brief Set resolution of the MCPWM group

2
components/driver/deprecated/driver/rmt_types_legacy.h
View File

@@ -15,7 +15,6 @@
extern "C" {
#endif
#define RMT_CHANNEL_FLAGS_AWARE_DFS (1 << 0) /*!< Channel can work during APB clock scaling */
#define RMT_CHANNEL_FLAGS_INVERT_SIG (1 << 1) /*!< Invert RMT signal */
@@ -39,7 +38,6 @@ typedef struct {
};
} rmt_item32_t;
#if SOC_RMT_SUPPORTED
/**
* @brief RMT hardware memory layout

1
components/driver/deprecated/driver/temp_sensor_types_legacy.h
View File

@@ -23,7 +23,6 @@ typedef enum {
TSENS_DAC_DEFAULT = TSENS_DAC_L2,
} temp_sensor_dac_offset_t;
/**
* @brief Configuration for temperature sensor reading
*/

1
components/driver/deprecated/driver/timer.h
View File

@@ -359,7 +359,6 @@ void timer_group_set_alarm_value_in_isr(timer_group_t group_num, timer_idx_t tim
*/
void timer_group_set_counter_enable_in_isr(timer_group_t group_num, timer_idx_t timer_num, timer_start_t counter_en);
/** @brief Get interrupt status, just used in ISR
*
* @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1

1
components/driver/deprecated/esp32/dac_legacy.c
View File

@@ -4,7 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "freertos/FreeRTOS.h"
#include "hal/dac_ll.h"
#include "esp_err.h"

1
components/driver/deprecated/esp32s2/dac_legacy.c
View File

@@ -4,7 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"

43
components/driver/deprecated/i2s_legacy.c
View File

@@ -202,7 +202,7 @@ static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_e
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_RX_Q_OVF;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
xQueueSendFromISR(p_i2s->i2s_queue, (void *)&i2s_event, &tmp);
need_awoke |= tmp;
}
}
@@ -210,7 +210,7 @@ static bool IRAM_ATTR i2s_dma_rx_callback(gdma_channel_handle_t dma_chan, gdma_e
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_RX_DONE;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
xQueueSendFromISR(p_i2s->i2s_queue, (void *)&i2s_event, &tmp);
need_awoke |= tmp;
}
}
@@ -234,7 +234,7 @@ static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_e
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_TX_Q_OVF;
i2s_event.size = p_i2s->tx->buf_size;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
xQueueSendFromISR(p_i2s->i2s_queue, (void *)&i2s_event, &tmp);
need_awoke |= tmp;
}
}
@@ -249,7 +249,7 @@ static bool IRAM_ATTR i2s_dma_tx_callback(gdma_channel_handle_t dma_chan, gdma_e
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_TX_DONE;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
xQueueSendFromISR(p_i2s->i2s_queue, (void *)&i2s_event, &tmp);
need_awoke |= tmp;
}
}
@@ -279,7 +279,7 @@ static void IRAM_ATTR i2s_intr_handler_default(void *arg)
xQueueReceiveFromISR(p_i2s->i2s_queue, &dummy, &tmp);
need_awoke |= tmp;
}
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
xQueueSendFromISR(p_i2s->i2s_queue, (void *)&i2s_event, &tmp);
need_awoke |= tmp;
}
}
@@ -293,7 +293,7 @@ static void IRAM_ATTR i2s_intr_handler_default(void *arg)
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_TX_Q_OVF;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
xQueueSendFromISR(p_i2s->i2s_queue, (void *)&i2s_event, &tmp);
need_awoke |= tmp;
}
}
@@ -307,7 +307,7 @@ static void IRAM_ATTR i2s_intr_handler_default(void *arg)
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_TX_DONE;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
xQueueSendFromISR(p_i2s->i2s_queue, (void *)&i2s_event, &tmp);
need_awoke |= tmp;
}
}
@@ -321,7 +321,7 @@ static void IRAM_ATTR i2s_intr_handler_default(void *arg)
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_RX_Q_OVF;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
xQueueSendFromISR(p_i2s->i2s_queue, (void *)&i2s_event, &tmp);
need_awoke |= tmp;
}
}
@@ -329,7 +329,7 @@ static void IRAM_ATTR i2s_intr_handler_default(void *arg)
need_awoke |= tmp;
if (p_i2s->i2s_queue) {
i2s_event.type = I2S_EVENT_RX_DONE;
xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp);
xQueueSendFromISR(p_i2s->i2s_queue, (void *)&i2s_event, &tmp);
need_awoke |= tmp;
}
}
@@ -360,7 +360,7 @@ static esp_err_t i2s_dma_intr_init(i2s_port_t i2s_num, int intr_flag)
/* Set GDMA config */
gdma_channel_alloc_config_t dma_cfg = {};
if ( p_i2s[i2s_num]->dir & I2S_DIR_TX) {
if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
dma_cfg.direction = GDMA_CHANNEL_DIRECTION_TX;
/* Register a new GDMA tx channel */
ESP_RETURN_ON_ERROR(gdma_new_channel(&dma_cfg, &p_i2s[i2s_num]->tx_dma_chan), TAG, "Register tx dma channel error");
@@ -369,7 +369,7 @@ static esp_err_t i2s_dma_intr_init(i2s_port_t i2s_num, int intr_flag)
/* Set callback function for GDMA, the interrupt is triggered by GDMA, then the GDMA ISR will call the callback function */
gdma_register_tx_event_callbacks(p_i2s[i2s_num]->tx_dma_chan, &cb, p_i2s[i2s_num]);
}
if ( p_i2s[i2s_num]->dir & I2S_DIR_RX) {
if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
dma_cfg.direction = GDMA_CHANNEL_DIRECTION_RX;
/* Register a new GDMA rx channel */
ESP_RETURN_ON_ERROR(gdma_new_channel(&dma_cfg, &p_i2s[i2s_num]->rx_dma_chan), TAG, "Register rx dma channel error");
@@ -693,7 +693,7 @@ err:
/*-------------------------------------------------------------
I2S clock operation
-------------------------------------------------------------*/
// [clk_tree] TODO: replace the following switch table by clk_tree API
// [clk_tree] TODO: replace the following switch table by clk_tree API
static uint32_t i2s_config_source_clock(i2s_port_t i2s_num, bool use_apll, uint32_t mclk)
{
#if SOC_I2S_SUPPORTS_APLL
@@ -844,7 +844,6 @@ static esp_err_t i2s_calculate_common_clock(int i2s_num, i2s_hal_clock_info_t *c
return ESP_OK;
}
static esp_err_t i2s_calculate_clock(i2s_port_t i2s_num, i2s_hal_clock_info_t *clk_info)
{
/* Calculate clock for ADC/DAC mode */
@@ -996,7 +995,6 @@ static esp_err_t i2s_check_cfg_validity(i2s_port_t i2s_num, const i2s_config_t *
ESP_RETURN_ON_FALSE((cfg->dma_desc_num >= 2 && cfg->dma_desc_num <= 128), ESP_ERR_INVALID_ARG, TAG, "I2S buffer count less than 128 and more than 2");
ESP_RETURN_ON_FALSE((cfg->dma_frame_num >= 8 && cfg->dma_frame_num <= 1024), ESP_ERR_INVALID_ARG, TAG, "I2S buffer length at most 1024 and more than 8");
#if SOC_I2S_SUPPORTS_PDM_TX || SOC_I2S_SUPPORTS_PDM_RX
/* Check PDM mode */
if (cfg->mode & I2S_MODE_PDM) {
@@ -1041,22 +1039,22 @@ static void i2s_set_slot_legacy(i2s_port_t i2s_num)
}
if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_STD) {
if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
i2s_hal_std_set_tx_slot(&(p_i2s[i2s_num]->hal), is_tx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg) );
i2s_hal_std_set_tx_slot(&(p_i2s[i2s_num]->hal), is_tx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg));
}
if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
i2s_hal_std_set_rx_slot(&(p_i2s[i2s_num]->hal), is_rx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg) );
i2s_hal_std_set_rx_slot(&(p_i2s[i2s_num]->hal), is_rx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg));
}
}
#if SOC_I2S_SUPPORTS_PDM
else if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_PDM) {
#if SOC_I2S_SUPPORTS_PDM_TX
if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
i2s_hal_pdm_set_tx_slot(&(p_i2s[i2s_num]->hal), is_tx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg) );
i2s_hal_pdm_set_tx_slot(&(p_i2s[i2s_num]->hal), is_tx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg));
}
#endif
#if SOC_I2S_SUPPORTS_PDM_RX
if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
i2s_hal_pdm_set_rx_slot(&(p_i2s[i2s_num]->hal), is_rx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg) );
i2s_hal_pdm_set_rx_slot(&(p_i2s[i2s_num]->hal), is_rx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg));
}
#endif
}
@@ -1064,10 +1062,10 @@ static void i2s_set_slot_legacy(i2s_port_t i2s_num)
#if SOC_I2S_SUPPORTS_TDM
else if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_TDM) {
if (p_i2s[i2s_num]->dir & I2S_DIR_TX) {
i2s_hal_tdm_set_tx_slot(&(p_i2s[i2s_num]->hal), is_tx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg) );
i2s_hal_tdm_set_tx_slot(&(p_i2s[i2s_num]->hal), is_tx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg));
}
if (p_i2s[i2s_num]->dir & I2S_DIR_RX) {
i2s_hal_tdm_set_rx_slot(&(p_i2s[i2s_num]->hal), is_rx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg) );
i2s_hal_tdm_set_rx_slot(&(p_i2s[i2s_num]->hal), is_rx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_num]->slot_cfg));
}
}
#endif
@@ -1324,7 +1322,7 @@ static void i2s_mode_identify(i2s_port_t i2s_num, const i2s_config_t *i2s_config
#if SOC_I2S_SUPPORTS_ADC_DAC
if ((i2s_config->mode & I2S_MODE_DAC_BUILT_IN) ||
(i2s_config->mode & I2S_MODE_ADC_BUILT_IN)) {
(i2s_config->mode & I2S_MODE_ADC_BUILT_IN)) {
p_i2s[i2s_num]->mode = (i2s_comm_mode_t)I2S_COMM_MODE_ADC_DAC;
}
#endif // SOC_I2S_SUPPORTS_ADC_DAC
@@ -1337,7 +1335,7 @@ static esp_err_t i2s_config_transfer(i2s_port_t i2s_num, const i2s_config_t *i2s
/* Convert legacy configuration into general part of slot and clock configuration */
p_i2s[i2s_num]->slot_cfg.data_bit_width = i2s_config->bits_per_sample;
p_i2s[i2s_num]->slot_cfg.slot_bit_width = (int)i2s_config->bits_per_chan < (int)i2s_config->bits_per_sample ?
i2s_config->bits_per_sample : i2s_config->bits_per_chan;
i2s_config->bits_per_sample : i2s_config->bits_per_chan;
p_i2s[i2s_num]->slot_cfg.slot_mode = i2s_config->channel_format < I2S_CHANNEL_FMT_ONLY_RIGHT ?
I2S_SLOT_MODE_STEREO : I2S_SLOT_MODE_MONO;
@@ -1637,7 +1635,6 @@ esp_err_t i2s_driver_uninstall(i2s_port_t i2s_num)
return ESP_OK;
}
esp_err_t i2s_driver_install(i2s_port_t i2s_num, const i2s_config_t *i2s_config, int queue_size, void *i2s_queue)
{
#if CONFIG_I2S_ENABLE_DEBUG_LOG

1
components/driver/deprecated/pcnt_legacy.c
View File

@@ -37,7 +37,6 @@
#define PCNT_RCC_ATOMIC()
#endif
static const char *TAG = "pcnt(legacy)";
#define PCNT_CHECK(a, str, ret_val) ESP_RETURN_ON_FALSE(a, ret_val, TAG, "%s", str)

2
components/driver/deprecated/rmt_legacy.c
View File

@@ -1011,7 +1011,7 @@ esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr
}
#if CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH
if (intr_alloc_flags & ESP_INTR_FLAG_IRAM ) {
if (intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
ESP_LOGE(TAG, "ringbuf ISR functions in flash, but used in IRAM interrupt");
return ESP_ERR_INVALID_ARG;
}

2
components/driver/deprecated/timer_legacy.c
View File

@@ -85,7 +85,7 @@ esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_
// get clock source frequency
uint32_t counter_src_hz = 0;
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)p_timer_obj[group_num][timer_num]->clk_src,
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &counter_src_hz),
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &counter_src_hz),
TIMER_TAG, "get clock source frequency failed");
*time = (double)timer_val * div / counter_src_hz;
return ESP_OK;