diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt
index 290dce049f..991522eb4c 100644
--- a/components/esp_rom/CMakeLists.txt
+++ b/components/esp_rom/CMakeLists.txt
@@ -26,6 +26,10 @@ if(CONFIG_IDF_TARGET_ARCH_XTENSA)
     list(APPEND sources "patches/esp_rom_longjmp.S")
 endif()
 
+if(target STREQUAL "esp32s2" OR target STREQUAL "esp32s3")
+    list(APPEND sources "patches/esp_rom_cache.c")
+endif()
+
 idf_component_register(SRCS ${sources}
                        INCLUDE_DIRS ${include_dirs}
                        PRIV_REQUIRES ${private_required_comp})
diff --git a/components/esp_rom/esp32s2/esp_rom_caps.h b/components/esp_rom/esp32s2/esp_rom_caps.h
index 1032eef93a..5667e51788 100644
--- a/components/esp_rom/esp32s2/esp_rom_caps.h
+++ b/components/esp_rom/esp32s2/esp_rom_caps.h
@@ -8,3 +8,4 @@
 
 #define ESP_ROM_HAS_CRC_LE            (1) // ROM CRC library supports Little Endian
 #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND    (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing
+#define ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG   (1) // ROM api Cache_Count_Flash_Pages will return unexpected value
diff --git a/components/esp_rom/esp32s2/ld/esp32s2.rom.ld b/components/esp_rom/esp32s2/ld/esp32s2.rom.ld
index 20a6d3c2a9..2256bc2b32 100644
--- a/components/esp_rom/esp32s2/ld/esp32s2.rom.ld
+++ b/components/esp_rom/esp32s2/ld/esp32s2.rom.ld
@@ -17,7 +17,7 @@ PROVIDE ( Cache_Clean_All = 0x40018438 );
 PROVIDE ( Cache_Clean_Items = 0x40018250 );
 PROVIDE ( Cache_Config_DCache_Autoload = 0x40018794 );
 PROVIDE ( Cache_Config_ICache_Autoload = 0x40018664 );
-PROVIDE ( Cache_Count_Flash_Pages = 0x40018f70 );
+PROVIDE ( rom_Cache_Count_Flash_Pages = 0x40018f70 );
 PROVIDE ( Cache_Dbus_MMU_Set = 0x40018eb0 );
 PROVIDE ( Cache_DCache_Preload_Done = 0x40018630 );
 PROVIDE ( Cache_Disable_DCache = 0x40018c68 );
diff --git a/components/esp_rom/esp32s3/esp_rom_caps.h b/components/esp_rom/esp32s3/esp_rom_caps.h
index 2b2c337079..8c814c713a 100644
--- a/components/esp_rom/esp32s3/esp_rom_caps.h
+++ b/components/esp_rom/esp32s3/esp_rom_caps.h
@@ -23,3 +23,5 @@
 #define ESP_ROM_HAS_ERASE_0_REGION_BUG      (1) // ROM has esp_flash_erase_region(size=0) bug
 #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND    (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing
 #define ESP_ROM_HAS_ETS_PRINTF_BUG          (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register
+#define ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG   (1) // ROM api Cache_Count_Flash_Pages will return unexpected value
+#define ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG (1) // ROM api Cache_Suspend_I/DCache and Cache_Freeze_I/DCache_Enable does not waiti
diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld
index 372fd9ddeb..741f72090c 100644
--- a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld
+++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld
@@ -420,15 +420,15 @@ PROVIDE( Cache_Disable_ICache = 0x4000186c );
 PROVIDE( Cache_Enable_ICache = 0x40001878 );
 PROVIDE( Cache_Disable_DCache = 0x40001884 );
 PROVIDE( Cache_Enable_DCache = 0x40001890 );
-PROVIDE( Cache_Suspend_ICache = 0x4000189c );
+PROVIDE( rom_Cache_Suspend_ICache = 0x4000189c );
 PROVIDE( Cache_Resume_ICache = 0x400018a8 );
-PROVIDE( Cache_Suspend_DCache = 0x400018b4 );
+PROVIDE( rom_Cache_Suspend_DCache = 0x400018b4 );
 PROVIDE( Cache_Resume_DCache = 0x400018c0 );
 PROVIDE( Cache_Occupy_Items = 0x400018cc );
 PROVIDE( Cache_Occupy_Addr = 0x400018d8 );
-PROVIDE( Cache_Freeze_ICache_Enable = 0x400018e4 );
+PROVIDE( rom_Cache_Freeze_ICache_Enable = 0x400018e4 );
 PROVIDE( Cache_Freeze_ICache_Disable = 0x400018f0 );
-PROVIDE( Cache_Freeze_DCache_Enable = 0x400018fc );
+PROVIDE( rom_Cache_Freeze_DCache_Enable = 0x400018fc );
 PROVIDE( Cache_Freeze_DCache_Disable = 0x40001908 );
 PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40001914 );
 PROVIDE( flash2spiram_instruction_offset = 0x40001920 );
@@ -444,7 +444,7 @@ PROVIDE( Cache_Occupy_DCache_MEMORY = 0x4000198c );
 PROVIDE( Cache_MMU_Init = 0x40001998 );
 PROVIDE( Cache_Ibus_MMU_Set = 0x400019a4 );
 PROVIDE( Cache_Dbus_MMU_Set = 0x400019b0 );
-PROVIDE( Cache_Count_Flash_Pages = 0x400019bc );
+PROVIDE( rom_Cache_Count_Flash_Pages = 0x400019bc );
 PROVIDE( Cache_Flash_To_SPIRAM_Copy = 0x400019c8 );
 PROVIDE( Cache_Travel_Tag_Memory = 0x400019d4 );
 PROVIDE( Cache_Travel_Tag_Memory2 = 0x400019e0 );
diff --git a/components/esp_rom/patches/esp_rom_cache.c b/components/esp_rom/patches/esp_rom_cache.c
new file mode 100644
index 0000000000..038d695e98
--- /dev/null
+++ b/components/esp_rom/patches/esp_rom_cache.c
@@ -0,0 +1,86 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "sdkconfig.h"
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
+#include <stdint.h>
+#include "esp_attr.h"
+#include "esp_rom_caps.h"
+#include "soc/extmem_reg.h"
+#if CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/cache.h"
+#endif
+
+// this api is renamed for patch
+extern uint32_t rom_Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped);
+IRAM_ATTR uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped)
+{
+    uint32_t page0_before_count = *page0_mapped;
+    uint32_t flash_pages = 0;
+    flash_pages = rom_Cache_Count_Flash_Pages(bus, page0_mapped);
+
+/* No page mapped to page0, in this condition, the rom api will return
+ * unexpected value + 1.
+ */
+    if (page0_before_count == *page0_mapped) {
+        flash_pages--;
+    }
+    return flash_pages;
+}
+extern uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped);
+
+#if ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG
+IRAM_ATTR static inline void Cache_Wait_Idle(int icache)
+{
+    if (icache) {
+        while (REG_GET_FIELD(EXTMEM_CACHE_STATE_REG, EXTMEM_ICACHE_STATE) != 1) {
+            ;
+        }
+    } else {
+        while (REG_GET_FIELD(EXTMEM_CACHE_STATE_REG, EXTMEM_DCACHE_STATE) != 1) {
+            ;
+        }
+    }
+}
+// renamed for patch
+extern uint32_t rom_Cache_Suspend_ICache(void);
+IRAM_ATTR uint32_t Cache_Suspend_ICache(void)
+{
+    uint32_t ret = rom_Cache_Suspend_ICache();
+    Cache_Wait_Idle(1);
+    return ret;
+}
+extern uint32_t Cache_Suspend_ICache(void);
+
+// renamed for patch
+extern uint32_t rom_Cache_Suspend_DCache(void);
+IRAM_ATTR uint32_t Cache_Suspend_DCache(void)
+{
+    uint32_t ret = rom_Cache_Suspend_DCache();
+    Cache_Wait_Idle(0);
+    return ret;
+}
+extern uint32_t Cache_Suspend_DCache(void);
+
+// renamed for patch
+extern void rom_Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode);
+IRAM_ATTR void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode)
+{
+    rom_Cache_Freeze_ICache_Enable(mode);
+    Cache_Wait_Idle(1);
+}
+extern void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode);
+
+// renamed for patch
+extern void rom_Cache_Freeze_DCache_Enable(cache_freeze_mode_t mode);
+IRAM_ATTR void Cache_Freeze_DCache_Enable(cache_freeze_mode_t mode)
+{
+    rom_Cache_Freeze_DCache_Enable(mode);
+    Cache_Wait_Idle(0);
+}
+extern void Cache_Freeze_DCache_Enable(cache_freeze_mode_t mode);
+#endif
+#endif