diff --git a/components/esp_coex/include/private/esp_coexist_internal.h b/components/esp_coex/include/private/esp_coexist_internal.h
index 5eac40b708..6e3799487f 100644
--- a/components/esp_coex/include/private/esp_coexist_internal.h
+++ b/components/esp_coex/include/private/esp_coexist_internal.h
@@ -396,6 +396,15 @@ int coex_schm_flexible_period_set(uint8_t period);
 uint8_t coex_schm_flexible_period_get(void);
 #endif
 
+/**
+ * @brief     Get coexistence scheme phase by phase index.
+ *
+ * @param     phase_idx    Coexistence phase index
+ *
+ * @return    Coexistence scheme phase
+ */
+void * coex_schm_get_phase_by_idx(int phase_idx);
+
 /**
   * @brief     Check the MD5 values of the coexistence adapter header files in IDF and WiFi library
   *
diff --git a/components/esp_coex/lib b/components/esp_coex/lib
index 61b07d1707..0b15dd89a6 160000
--- a/components/esp_coex/lib
+++ b/components/esp_coex/lib
@@ -1 +1 @@
-Subproject commit 61b07d1707b5aa18c0184899a8e45acf06c94912
+Subproject commit 0b15dd89a6be4fb6e7c64cfcacde612a3b8f4043
diff --git a/components/esp_hw_support/include/esp_private/esp_pmu.h b/components/esp_hw_support/include/esp_private/esp_pmu.h
index c530a85fb6..43c06781e0 100644
--- a/components/esp_hw_support/include/esp_private/esp_pmu.h
+++ b/components/esp_hw_support/include/esp_private/esp_pmu.h
@@ -12,6 +12,7 @@
 #include <stdlib.h>
 
 #include "soc/soc_caps.h"
+#include "soc/clk_tree_defs.h"
 
 #if SOC_PMU_SUPPORTED
 #include "hal/pmu_hal.h"
@@ -225,18 +226,20 @@ uint32_t pmu_sleep_calculate_hp_hw_wait_time(uint32_t pd_flags, uint32_t slowclk
  * @brief Calculate the hardware time overhead during sleep to compensate for sleep time
  *
  * @param pd_flags flags indicates the power domain that will be powered down
+ * @param slowclk_src slow clock source of pmu
  * @param slowclk_period re-calibrated slow clock period
  * @param fastclk_period re-calibrated fast clock period
  *
  * @return hardware time overhead in us
  */
-uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period);
+uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period);
 
 /**
  * @brief Get default sleep configuration
  * @param config pmu_sleep_config instance
  * @param pd_flags flags indicates the power domain that will be powered down
  * @param adjustment total software and hardware time overhead
+ * @param slowclk_src slow clock source of pmu
  * @param slowclk_period re-calibrated slow clock period in microseconds,
  *                       Q13.19 fixed point format
  * @param fastclk_period re-calibrated fast clock period in microseconds,
@@ -245,7 +248,7 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_pe
 
  * @return hardware time overhead in us
  */
-const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, uint32_t pd_flags, uint32_t adjustment, uint32_t slowclk_period, uint32_t fastclk_period, bool dslp);
+const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, uint32_t pd_flags, uint32_t adjustment, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period, bool dslp);
 
 /**
  * @brief Prepare the chip to enter sleep mode
diff --git a/components/esp_hw_support/port/esp32/include/soc/rtc.h b/components/esp_hw_support/port/esp32/include/soc/rtc.h
index 69b152143f..234783e9a6 100644
--- a/components/esp_hw_support/port/esp32/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32/include/soc/rtc.h
@@ -478,6 +478,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 /**
  * @brief sleep configuration for rtc_sleep_init function
  */
diff --git a/components/esp_hw_support/port/esp32/rtc_time.c b/components/esp_hw_support/port/esp32/rtc_time.c
index 447c109ec8..03695fc93c 100644
--- a/components/esp_hw_support/port/esp32/rtc_time.c
+++ b/components/esp_hw_support/port/esp32/rtc_time.c
@@ -191,6 +191,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)
diff --git a/components/esp_hw_support/port/esp32c2/include/soc/rtc.h b/components/esp_hw_support/port/esp32c2/include/soc/rtc.h
index 0cc79431c0..0269caa4e0 100644
--- a/components/esp_hw_support/port/esp32c2/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32c2/include/soc/rtc.h
@@ -508,6 +508,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 /**
  * @brief Power down flags for rtc_sleep_pd function
  */
diff --git a/components/esp_hw_support/port/esp32c2/rtc_time.c b/components/esp_hw_support/port/esp32c2/rtc_time.c
index 5c7470dad4..d724df17a1 100644
--- a/components/esp_hw_support/port/esp32c2/rtc_time.c
+++ b/components/esp_hw_support/port/esp32c2/rtc_time.c
@@ -191,6 +191,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)
diff --git a/components/esp_hw_support/port/esp32c3/include/soc/rtc.h b/components/esp_hw_support/port/esp32c3/include/soc/rtc.h
index c160b128f4..bb60f57d5a 100644
--- a/components/esp_hw_support/port/esp32c3/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32c3/include/soc/rtc.h
@@ -536,6 +536,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 /**
  * @brief Power down flags for rtc_sleep_pd function
  */
diff --git a/components/esp_hw_support/port/esp32c3/rtc_time.c b/components/esp_hw_support/port/esp32c3/rtc_time.c
index bf1aa97259..783aa93ffb 100644
--- a/components/esp_hw_support/port/esp32c3/rtc_time.c
+++ b/components/esp_hw_support/port/esp32c3/rtc_time.c
@@ -194,6 +194,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)
diff --git a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h
index a4e00edfdf..a111c411db 100644
--- a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h
@@ -469,6 +469,14 @@ typedef soc_xtal_freq_t rtc_xtal_freq_t;
 #define RTC_XTAL_FREQ_40M SOC_XTAL_FREQ_40M                 //!< 40 MHz XTAL
 #define RTC_XTAL_FREQ_48M SOC_XTAL_FREQ_48M                 //!< 48 MHz XTAL
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_hw_support/port/esp32c5/pmu_sleep.c b/components/esp_hw_support/port/esp32c5/pmu_sleep.c
index 7b6cce7293..d5d99498e1 100644
--- a/components/esp_hw_support/port/esp32c5/pmu_sleep.c
+++ b/components/esp_hw_support/port/esp32c5/pmu_sleep.c
@@ -50,7 +50,7 @@ void pmu_sleep_disable_regdma_backup(void)
     }
 }
 
-uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period)
+uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period)
 {
     const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
 
@@ -89,8 +89,20 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_pe
      *                     |                           wake-up delay                          |
      */
 #if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
+    int min_slp_time_adjustment_us = 0;
+#if SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED
+    if (slowclk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
+        const uint32_t slowclk_period_fixed = rtc_clk_freq_to_period(SOC_CLK_RC_SLOW_FREQ_APPROX);
+        const int min_slp_cycle_fixed = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period_fixed);
+        const int min_slp_cycle_calib = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
+        const int min_slp_cycle_diff = (min_slp_cycle_calib > min_slp_cycle_fixed) ? \
+                       (min_slp_cycle_calib - min_slp_cycle_fixed) : (min_slp_cycle_fixed - min_slp_cycle_calib);
+        const int min_slp_time_diff = rtc_time_slowclk_to_us(min_slp_cycle_diff, slowclk_period_fixed);
+        min_slp_time_adjustment_us = (min_slp_cycle_calib > min_slp_cycle_fixed) ? min_slp_time_diff : -min_slp_time_diff;
+    }
+#endif
     const int rf_on_protect_time_us = mc->hp.regdma_rf_on_work_time_us;
-    const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us + mc->hp.clock_domain_sync_time_us;
+    const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us + mc->hp.clock_domain_sync_time_us + min_slp_time_adjustment_us;
 #else
     const int rf_on_protect_time_us = 0;
     const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us;
@@ -105,24 +117,31 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
         pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
         const uint32_t pd_flags,
         const uint32_t adjustment,
+        soc_rtc_slow_clk_src_t slowclk_src,
         const uint32_t slowclk_period,
         const uint32_t fastclk_period
     )
 {
     const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
 
-    param->hp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
+#if (SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED && SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP)
+    const uint32_t slowclk_period_fixed = (slowclk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? rtc_clk_freq_to_period(SOC_CLK_RC_SLOW_FREQ_APPROX) : slowclk_period;
+#else
+    const uint32_t slowclk_period_fixed = slowclk_period;
+#endif
+
+    param->hp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period_fixed);
     param->hp_sys.analog_wait_target_cycle        = rtc_time_us_to_fastclk(mc->hp.analog_wait_time_us, fastclk_period);
     param->hp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_supply_wait_time_us, fastclk_period);
     param->hp_sys.digital_power_up_wait_cycle     = rtc_time_us_to_fastclk(mc->hp.power_up_wait_time_us, fastclk_period);
     param->hp_sys.pll_stable_wait_cycle           = rtc_time_us_to_fastclk(mc->hp.pll_wait_stable_time_us, fastclk_period);
 
-    const int hw_wait_time_us = pmu_sleep_calculate_hw_wait_time(pd_flags, slowclk_period, fastclk_period);
+    const int hw_wait_time_us = pmu_sleep_calculate_hw_wait_time(pd_flags, slowclk_src, slowclk_period, fastclk_period);
     const int modem_state_skip_time_us = mc->hp.regdma_m2a_work_time_us + mc->hp.system_dfs_up_work_time_us + mc->lp.min_slp_time_us;
     const int modem_wakeup_wait_time_us = adjustment - hw_wait_time_us + modem_state_skip_time_us + mc->hp.regdma_rf_on_work_time_us;
     param->hp_sys.modem_wakeup_wait_cycle         = rtc_time_us_to_fastclk(modem_wakeup_wait_time_us, fastclk_period);
 
-    param->lp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period);
+    param->lp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period_fixed);
     param->lp_sys.analog_wait_target_cycle        = rtc_time_us_to_slowclk(mc->lp.analog_wait_time_us, slowclk_period);
     param->lp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_supply_wait_time_us, fastclk_period);
     param->lp_sys.digital_power_up_wait_cycle     = rtc_time_us_to_fastclk(mc->lp.power_up_wait_time_us, fastclk_period);
@@ -139,6 +158,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
         pmu_sleep_config_t *config,
         uint32_t pd_flags,
         uint32_t adjustment,
+        soc_rtc_slow_clk_src_t slowclk_src,
         uint32_t slowclk_period,
         uint32_t fastclk_period,
         bool dslp
@@ -154,7 +174,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
     config->power = power_default;
 
     pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(pd_flags);
-    config->param = *pmu_sleep_param_config_default(&param_default, &power_default, pd_flags, adjustment, slowclk_period, fastclk_period);
+    config->param = *pmu_sleep_param_config_default(&param_default, &power_default, pd_flags, adjustment, slowclk_src, slowclk_period, fastclk_period);
 
     if (dslp) {
         config->param.lp_sys.analog_wait_target_cycle  = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);
diff --git a/components/esp_hw_support/port/esp32c5/rtc_time.c b/components/esp_hw_support/port/esp32c5/rtc_time.c
index 4e260b2389..15a6f5873d 100644
--- a/components/esp_hw_support/port/esp32c5/rtc_time.c
+++ b/components/esp_hw_support/port/esp32c5/rtc_time.c
@@ -269,6 +269,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)
diff --git a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h
index 2041422b49..404d0d68a9 100644
--- a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h
@@ -456,6 +456,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 
 // -------------------------- CLOCK TREE DEFS ALIAS ----------------------------
 // **WARNING**: The following are only for backwards compatibility.
diff --git a/components/esp_hw_support/port/esp32c6/pmu_sleep.c b/components/esp_hw_support/port/esp32c6/pmu_sleep.c
index 4a8be881da..4c850a36f9 100644
--- a/components/esp_hw_support/port/esp32c6/pmu_sleep.c
+++ b/components/esp_hw_support/port/esp32c6/pmu_sleep.c
@@ -105,7 +105,7 @@ void pmu_sleep_disable_regdma_backup(void)
     }
 }
 
-uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period)
+uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period)
 {
     const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
 
@@ -147,8 +147,20 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_pe
      *                     |                           wake-up delay                          |
      */
 #if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
+    int min_slp_time_adjustment_us = 0;
+#if SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED
+    if (slowclk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
+        const uint32_t slowclk_period_fixed = rtc_clk_freq_to_period(SOC_CLK_RC_SLOW_FREQ_APPROX);
+        const int min_slp_cycle_fixed = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period_fixed);
+        const int min_slp_cycle_calib = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
+        const int min_slp_cycle_diff = (min_slp_cycle_calib > min_slp_cycle_fixed) ? \
+                       (min_slp_cycle_calib - min_slp_cycle_fixed) : (min_slp_cycle_fixed - min_slp_cycle_calib);
+        const int min_slp_time_diff = rtc_time_slowclk_to_us(min_slp_cycle_diff, slowclk_period_fixed);
+        min_slp_time_adjustment_us = (min_slp_cycle_calib > min_slp_cycle_fixed) ? min_slp_time_diff : -min_slp_time_diff;
+    }
+#endif
     const int rf_on_protect_time_us = mc->hp.regdma_rf_on_work_time_us;
-    const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us + mc->hp.clock_domain_sync_time_us;
+    const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us + mc->hp.clock_domain_sync_time_us + min_slp_time_adjustment_us;
 #else
     const int rf_on_protect_time_us = 0;
     const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us;
@@ -163,24 +175,31 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
         pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
         const uint32_t pd_flags,
         const uint32_t adjustment,
+        soc_rtc_slow_clk_src_t slowclk_src,
         const uint32_t slowclk_period,
         const uint32_t fastclk_period
     )
 {
     const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
 
-    param->hp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
+#if (SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED && SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP)
+    const uint32_t slowclk_period_fixed = (slowclk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? rtc_clk_freq_to_period(SOC_CLK_RC_SLOW_FREQ_APPROX) : slowclk_period;
+#else
+    const uint32_t slowclk_period_fixed = slowclk_period;
+#endif
+
+    param->hp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period_fixed);
     param->hp_sys.analog_wait_target_cycle        = rtc_time_us_to_fastclk(mc->hp.analog_wait_time_us, fastclk_period);
     param->hp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_supply_wait_time_us, fastclk_period);
     param->hp_sys.digital_power_up_wait_cycle     = rtc_time_us_to_fastclk(mc->hp.power_up_wait_time_us, fastclk_period);
     param->hp_sys.pll_stable_wait_cycle           = rtc_time_us_to_fastclk(mc->hp.pll_wait_stable_time_us, fastclk_period);
 
-    const int hw_wait_time_us = pmu_sleep_calculate_hw_wait_time(pd_flags, slowclk_period, fastclk_period);
+    const int hw_wait_time_us = pmu_sleep_calculate_hw_wait_time(pd_flags, slowclk_src, slowclk_period, fastclk_period);
     const int modem_state_skip_time_us = mc->hp.regdma_m2a_work_time_us + mc->hp.system_dfs_up_work_time_us + mc->lp.min_slp_time_us;
     const int modem_wakeup_wait_time_us = adjustment - hw_wait_time_us + modem_state_skip_time_us + mc->hp.regdma_rf_on_work_time_us;
     param->hp_sys.modem_wakeup_wait_cycle         = rtc_time_us_to_fastclk(modem_wakeup_wait_time_us, fastclk_period);
 
-    param->lp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period);
+    param->lp_sys.min_slp_slow_clk_cycle          = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period_fixed);
     param->lp_sys.analog_wait_target_cycle        = rtc_time_us_to_slowclk(mc->lp.analog_wait_time_us, slowclk_period);
     param->lp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_supply_wait_time_us, fastclk_period);
     param->lp_sys.digital_power_up_wait_cycle     = rtc_time_us_to_fastclk(mc->lp.power_up_wait_time_us, fastclk_period);
@@ -197,6 +216,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
         pmu_sleep_config_t *config,
         uint32_t pd_flags,
         uint32_t adjustment,
+        soc_rtc_slow_clk_src_t slowclk_src,
         uint32_t slowclk_period,
         uint32_t fastclk_period,
         bool dslp
@@ -207,7 +227,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
     config->power = power_default;
 
     pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(pd_flags);
-    config->param = *pmu_sleep_param_config_default(&param_default, &power_default, pd_flags, adjustment, slowclk_period, fastclk_period);
+    config->param = *pmu_sleep_param_config_default(&param_default, &power_default, pd_flags, adjustment, slowclk_src, slowclk_period, fastclk_period);
 
     if (dslp) {
         config->param.lp_sys.analog_wait_target_cycle  = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);
diff --git a/components/esp_hw_support/port/esp32c6/rtc_time.c b/components/esp_hw_support/port/esp32c6/rtc_time.c
index a2393ec04a..917eb6cc2f 100644
--- a/components/esp_hw_support/port/esp32c6/rtc_time.c
+++ b/components/esp_hw_support/port/esp32c6/rtc_time.c
@@ -271,6 +271,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)
diff --git a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h
index 2f8ac74bfd..c17f22255b 100644
--- a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h
@@ -495,6 +495,14 @@ typedef soc_xtal_freq_t rtc_xtal_freq_t;
 #define rtc_clk_fast_freq_set(fast_freq) rtc_clk_fast_src_set(fast_freq)
 #define rtc_clk_fast_freq_get() rtc_clk_fast_src_get()
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_hw_support/port/esp32c61/rtc_time.c b/components/esp_hw_support/port/esp32c61/rtc_time.c
index 688b777334..560e8f56a0 100644
--- a/components/esp_hw_support/port/esp32c61/rtc_time.c
+++ b/components/esp_hw_support/port/esp32c61/rtc_time.c
@@ -268,6 +268,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)
diff --git a/components/esp_hw_support/port/esp32h2/include/soc/rtc.h b/components/esp_hw_support/port/esp32h2/include/soc/rtc.h
index d429e5d611..8497ed8b9f 100644
--- a/components/esp_hw_support/port/esp32h2/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32h2/include/soc/rtc.h
@@ -454,6 +454,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 // -------------------------- CLOCK TREE DEFS ALIAS ----------------------------
 // **WARNING**: The following are only for backwards compatibility.
 // Please use the declarations in soc/clk_tree_defs.h instead.
diff --git a/components/esp_hw_support/port/esp32h2/pmu_sleep.c b/components/esp_hw_support/port/esp32h2/pmu_sleep.c
index 0bf4b439e0..45d6d7ae24 100644
--- a/components/esp_hw_support/port/esp32h2/pmu_sleep.c
+++ b/components/esp_hw_support/port/esp32h2/pmu_sleep.c
@@ -63,7 +63,7 @@ void pmu_sleep_disable_regdma_backup(void)
     pmu_hal_hp_set_sleep_active_backup_disable(PMU_instance()->hal);
 }
 
-uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period)
+uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period)
 {
     pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
 
@@ -129,6 +129,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
         pmu_sleep_config_t *config,
         uint32_t pd_flags,
         uint32_t adjustment,
+        soc_rtc_slow_clk_src_t slowclk_src,
         uint32_t slowclk_period,
         uint32_t fastclk_period,
         bool dslp
diff --git a/components/esp_hw_support/port/esp32h2/rtc_time.c b/components/esp_hw_support/port/esp32h2/rtc_time.c
index ccd3dc491f..c682832eca 100644
--- a/components/esp_hw_support/port/esp32h2/rtc_time.c
+++ b/components/esp_hw_support/port/esp32h2/rtc_time.c
@@ -271,6 +271,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)
diff --git a/components/esp_hw_support/port/esp32p4/include/soc/rtc.h b/components/esp_hw_support/port/esp32p4/include/soc/rtc.h
index df86bffa5a..940409df6c 100644
--- a/components/esp_hw_support/port/esp32p4/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32p4/include/soc/rtc.h
@@ -469,6 +469,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 /**
  * @brief Enable or disable APLL
  *
diff --git a/components/esp_hw_support/port/esp32p4/pmu_sleep.c b/components/esp_hw_support/port/esp32p4/pmu_sleep.c
index 38f89957fe..5a54324c18 100644
--- a/components/esp_hw_support/port/esp32p4/pmu_sleep.c
+++ b/components/esp_hw_support/port/esp32p4/pmu_sleep.c
@@ -102,7 +102,7 @@ uint32_t pmu_sleep_calculate_hp_hw_wait_time(uint32_t pd_flags, uint32_t slowclk
     return (uint32_t)hp_hw_wait_time_us;
 }
 
-uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period)
+uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period)
 {
     const uint32_t lp_hw_wait_time_us = pmu_sleep_calculate_lp_hw_wait_time(pd_flags, slowclk_period, fastclk_period);
     const uint32_t hp_hw_wait_time_us = pmu_sleep_calculate_hp_hw_wait_time(pd_flags, slowclk_period, fastclk_period);
@@ -117,6 +117,7 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
         pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
         const uint32_t pd_flags,
         const uint32_t adjustment,
+        soc_rtc_slow_clk_src_t slowclk_src,
         const uint32_t slowclk_period,
         const uint32_t fastclk_period
     )
@@ -146,6 +147,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
         pmu_sleep_config_t *config,
         uint32_t pd_flags,
         uint32_t adjustment,
+        soc_rtc_slow_clk_src_t slowclk_src,
         uint32_t slowclk_period,
         uint32_t fastclk_period,
         bool dslp
@@ -207,7 +209,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
 
     config->power = power_default;
     pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(pd_flags);
-    config->param = *pmu_sleep_param_config_default(&param_default, &power_default, pd_flags, adjustment, slowclk_period, fastclk_period);
+    config->param = *pmu_sleep_param_config_default(&param_default, &power_default, pd_flags, adjustment, slowclk_src, slowclk_period, fastclk_period);
 
     return config;
 }
diff --git a/components/esp_hw_support/port/esp32p4/rtc_time.c b/components/esp_hw_support/port/esp32p4/rtc_time.c
index d7a9cf5bab..8c5a526233 100644
--- a/components/esp_hw_support/port/esp32p4/rtc_time.c
+++ b/components/esp_hw_support/port/esp32p4/rtc_time.c
@@ -228,6 +228,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)
diff --git a/components/esp_hw_support/port/esp32s2/include/soc/rtc.h b/components/esp_hw_support/port/esp32s2/include/soc/rtc.h
index 08dcc1ca19..c173e99926 100644
--- a/components/esp_hw_support/port/esp32s2/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32s2/include/soc/rtc.h
@@ -569,6 +569,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 /**
  * @brief Power down flags for rtc_sleep_pd function
  */
diff --git a/components/esp_hw_support/port/esp32s2/rtc_time.c b/components/esp_hw_support/port/esp32s2/rtc_time.c
index 76df279092..39e59e56a1 100644
--- a/components/esp_hw_support/port/esp32s2/rtc_time.c
+++ b/components/esp_hw_support/port/esp32s2/rtc_time.c
@@ -259,6 +259,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)
diff --git a/components/esp_hw_support/port/esp32s3/include/soc/rtc.h b/components/esp_hw_support/port/esp32s3/include/soc/rtc.h
index 7c503c7f5a..5df4d082d0 100644
--- a/components/esp_hw_support/port/esp32s3/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32s3/include/soc/rtc.h
@@ -547,6 +547,14 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
+/**
+ * @brief Calculate the slow clock period value by slow clock frequency
+ *
+ * @param freq_hz Frequency of the slow clock in Hz
+ * @return Fixed point value of slow clock period in microseconds
+ */
+uint32_t rtc_clk_freq_to_period(uint32_t freq_hz);
+
 /**
  * @brief Power up flags for rtc_sleep_pd function
  */
diff --git a/components/esp_hw_support/port/esp32s3/rtc_time.c b/components/esp_hw_support/port/esp32s3/rtc_time.c
index 834676a880..4b78096c5c 100644
--- a/components/esp_hw_support/port/esp32s3/rtc_time.c
+++ b/components/esp_hw_support/port/esp32s3/rtc_time.c
@@ -193,6 +193,8 @@ uint32_t rtc_clk_freq_cal(uint32_t cal_val)
     return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }
 
+uint32_t rtc_clk_freq_to_period(uint32_t) __attribute__((alias("rtc_clk_freq_cal")));
+
 /// @brief if the calibration is used, we need to enable the timer group0 first
 __attribute__((constructor))
 static void enable_timer_group0_for_calibration(void)
diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c
index 9fd969944b..51d3e7868a 100644
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@@ -940,7 +940,7 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
 
     pmu_sleep_config_t config;
     pmu_sleep_init(pmu_sleep_config_default(&config, sleep_flags, s_config.sleep_time_adjustment,
-            s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period,
+            rtc_clk_slow_src_get(), s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period,
             deep_sleep), deep_sleep);
 #else
     rtc_sleep_config_t config;
@@ -1382,7 +1382,7 @@ esp_err_t esp_light_sleep_start(void)
      */
 #if SOC_PMU_SUPPORTED
     int sleep_time_sw_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US + sleep_time_overhead_in + s_config.sleep_time_overhead_out;
-    int sleep_time_hw_adjustment = pmu_sleep_calculate_hw_wait_time(pd_flags, s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period);
+    int sleep_time_hw_adjustment = pmu_sleep_calculate_hw_wait_time(pd_flags, rtc_clk_slow_src_get(), s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period);
     s_config.sleep_time_adjustment = sleep_time_sw_adjustment + sleep_time_hw_adjustment;
 #else
     uint32_t rtc_cntl_xtl_buf_wait_slp_cycles = rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, s_config.rtc_clk_cal_period);
diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld
index 8e3f55b764..7c128e14b3 100644
--- a/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld
+++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld
@@ -58,7 +58,7 @@ ppTxFragmentProc = 0x40001e08;
 esf_buf_setup = 0x40001e0c;
 hal_crypto_set_key_entry = 0x40001e18;
 pm_start = 0x40001e34;
-pm_stop = 0x40001e38;
+/*pm_stop = 0x40001e38;*/
 hal_set_sta_tbtt = 0x40001e4c;
 //pm_update_next_tbtt = 0x40001e50;
 pm_set_sleep_type = 0x40001e54;
@@ -203,7 +203,7 @@ pm_beacon_offset_init = 0x400030b0;
 pm_beacon_offset_deinit = 0x400030b4;
 pm_get_tbtt_count = 0x400030b8;
 pm_coex_schm_overall_period_get = 0x400030bc;
-pm_coex_pwr_update = 0x400030c0;
+//pm_coex_pwr_update = 0x400030c0;
 /* Data (.data, .bss, .rodata) */
 s_pm_beacon_offset_ptr = 0x3fcdfa64;
 s_pm_beacon_offset_config_ptr = 0x3fcdfa60;
diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.ld
index 9b061ca5e4..c6cae113bc 100644
--- a/components/esp_rom/esp32c2/ld/esp32c2.rom.ld
+++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.ld
@@ -528,8 +528,8 @@ pm_mac_sleep = 0x40001b80;
 pm_enable_active_timer = 0x40001b84;
 pm_enable_sleep_delay_timer = 0x40001b88;
 pm_local_tsf_process = 0x40001b8c;
-pm_set_beacon_filter = 0x40001b90;
-pm_is_in_wifi_slice_threshold = 0x40001b94;
+//pm_set_beacon_filter = 0x40001b90;
+/*pm_is_in_wifi_slice_threshold = 0x40001b94;*/
 pm_is_waked = 0x40001b98;
 /*pm_keep_alive = 0x40001b9c;*/
 /* pm_on_beacon_rx = 0x40001ba0; */
diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.ld
index b714646678..a8c7e668aa 100644
--- a/components/esp_rom/esp32c3/ld/esp32c3.rom.ld
+++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.ld
@@ -717,8 +717,8 @@ pm_mac_sleep = 0x4000165c;
 pm_enable_active_timer = 0x40001660;
 pm_enable_sleep_delay_timer = 0x40001664;
 pm_local_tsf_process = 0x40001668;
-pm_set_beacon_filter = 0x4000166c;
-pm_is_in_wifi_slice_threshold = 0x40001670;
+//pm_set_beacon_filter = 0x4000166c;
+/*pm_is_in_wifi_slice_threshold = 0x40001670;*/
 pm_is_waked = 0x40001674;
 /*pm_keep_alive = 0x40001678;*/
 /* pm_on_beacon_rx = 0x4000167c; */
diff --git a/components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.pp.ld b/components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.pp.ld
index 28ac5da740..b7eeca0b44 100644
--- a/components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.pp.ld
+++ b/components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.pp.ld
@@ -115,8 +115,8 @@ pm_mac_sleep = 0x40000d5c;
 /*pm_enable_active_timer = 0x40000d60;*/
 pm_enable_sleep_delay_timer = 0x40000d64;
 pm_local_tsf_process = 0x40000d68;
-pm_set_beacon_filter = 0x40000d6c;
-pm_is_in_wifi_slice_threshold = 0x40000d70;
+//pm_set_beacon_filter = 0x40000d6c;
+/*pm_is_in_wifi_slice_threshold = 0x40000d70;*/
 pm_is_waked = 0x40000d74;
 //pm_keep_alive = 0x40000d78;
 /*pm_on_beacon_rx = 0x40000d7c;*/
@@ -151,16 +151,16 @@ pm_is_twt_start = 0x40000dec;
 pm_twt_set_target_wdev_time = 0x40000df0;
 pm_twt_set_target_tsf = 0x40000df4;
 pm_enable_twt_keep_alive_timer = 0x40000df8;
-pm_mac_try_enable_modem_state = 0x40000dfc;
+/*pm_mac_try_enable_modem_state = 0x40000dfc;*/
 pm_beacon_monitor_tbtt_timeout_process = 0x40000e00;
 /*pm_update_next_tbtt = 0x40000e04;*/
 pm_twt_disallow_tx = 0x40000e08;
 pm_clear_wakeup_signal = 0x40000e0c;
 pm_mac_disable_tsf_tbtt_soc_wakeup = 0x40000e10;
 pm_mac_disable_tsf_tbtt_modem_wakeup = 0x40000e14;
-pm_mac_enable_tsf_tbtt_soc_wakeup = 0x40000e18;
-pm_mac_enable_tsf_tbtt_modem_wakeup = 0x40000e1c;
-pm_mac_modem_params_rt_update = 0x40000e20;
+// pm_mac_enable_tsf_tbtt_soc_wakeup = 0x40000e18;
+// pm_mac_enable_tsf_tbtt_modem_wakeup = 0x40000e1c;
+// pm_mac_modem_params_rt_update = 0x40000e20;
 pm_update_at_next_beacon = 0x40000e24;
 tbtt_adaptive_setup = 0x40000e28;
 tbtt_adaptive_servo = 0x40000e2c;
diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.pp.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.pp.ld
index 43090c9bf3..7ff2770e50 100644
--- a/components/esp_rom/esp32c6/ld/esp32c6.rom.pp.ld
+++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.pp.ld
@@ -66,7 +66,7 @@ pm_mac_sleep = 0x40000c84;
 pm_enable_sleep_delay_timer = 0x40000c8c;
 pm_local_tsf_process = 0x40000c90;
 //pm_set_beacon_filter = 0x40000c94;
-pm_is_in_wifi_slice_threshold = 0x40000c98;
+/*pm_is_in_wifi_slice_threshold = 0x40000c98;*/
 pm_is_waked = 0x40000c9c;
 //pm_keep_alive = 0x40000ca0;
 /* pm_on_beacon_rx = 0x40000ca4; */
diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld
index 6aef3be281..047b946a94 100644
--- a/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld
+++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld
@@ -62,13 +62,13 @@ pm_dream = 0x40000b98;
 pm_mac_wakeup = 0x40000b9c;
 pm_mac_sleep = 0x40000ba0;
 pm_enable_active_timer = 0x40000ba4;
-pm_enable_sleep_delay_timer = 0x40000ba8;
+pm_enable_sleep_delay_timer = 0x40000ba8
 pm_local_tsf_process = 0x40000bac;
-pm_set_beacon_filter = 0x40000bb0;
-pm_is_in_wifi_slice_threshold = 0x40000bb4;
+//pm_set_beacon_filter = 0x40000bb0;
+/* pm_is_in_wifi_slice_threshold = 0x40000bb4;*/
 pm_is_waked = 0x40000bb8;
 //pm_keep_alive = 0x40000bbc;
-pm_on_beacon_rx = 0x40000bc0;
+/*pm_on_beacon_rx = 0x40000bc0;*/
 pm_on_data_rx = 0x40000bc4;
 pm_on_tbtt = 0x40000bc8;
 pm_parse_beacon = 0x40000bcc;
diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld
index 25e18af8e7..d4e2b292b3 100644
--- a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld
+++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld
@@ -971,8 +971,8 @@ pm_mac_sleep = 0x40005454;
 pm_enable_active_timer = 0x40005460;
 pm_enable_sleep_delay_timer = 0x4000546c;
 pm_local_tsf_process = 0x40005478;
-pm_set_beacon_filter = 0x40005484;
-pm_is_in_wifi_slice_threshold = 0x40005490;
+//pm_set_beacon_filter = 0x40005484;
+/*pm_is_in_wifi_slice_threshold = 0x40005490;*/
 pm_is_waked = 0x4000549c;
 /*pm_keep_alive = 0x400054a8;*/
 /* pm_on_beacon_rx = 0x400054b4; */
diff --git a/components/esp_wifi/esp32/esp_adapter.c b/components/esp_wifi/esp32/esp_adapter.c
index 3d69706012..50be0e7eb9 100644
--- a/components/esp_wifi/esp32/esp_adapter.c
+++ b/components/esp_wifi/esp32/esp_adapter.c
@@ -594,6 +594,15 @@ static uint8_t coex_schm_flexible_period_get_wrapper(void)
 #endif
 }
 
+static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx)
+{
+#if CONFIG_SW_COEXIST_ENABLE
+    return coex_schm_get_phase_by_idx(phase_idx);
+#else
+    return NULL;
+#endif
+}
+
 static void IRAM_ATTR esp_empty_wrapper(void)
 {
 
@@ -730,5 +739,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
     ._coex_schm_register_cb = coex_schm_register_cb_wrapper,
     ._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
     ._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
+    ._coex_schm_get_phase_by_idx = coex_schm_get_phase_by_idx_wrapper,
     ._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
 };
diff --git a/components/esp_wifi/esp32c2/esp_adapter.c b/components/esp_wifi/esp32c2/esp_adapter.c
index bdcb1bffe8..95f856b29f 100644
--- a/components/esp_wifi/esp32c2/esp_adapter.c
+++ b/components/esp_wifi/esp32c2/esp_adapter.c
@@ -535,6 +535,15 @@ static uint8_t coex_schm_flexible_period_get_wrapper(void)
 #endif
 }
 
+static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx)
+{
+#if CONFIG_SW_COEXIST_ENABLE
+    return coex_schm_get_phase_by_idx(phase_idx);
+#else
+    return NULL;
+#endif
+}
+
 static void IRAM_ATTR esp_empty_wrapper(void)
 {
 
@@ -670,5 +679,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
     ._coex_schm_register_cb = coex_schm_register_cb_wrapper,
     ._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
     ._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
+    ._coex_schm_get_phase_by_idx = coex_schm_get_phase_by_idx_wrapper,
     ._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
 };
diff --git a/components/esp_wifi/esp32c3/esp_adapter.c b/components/esp_wifi/esp32c3/esp_adapter.c
index ceda4a73c6..df052ebe50 100644
--- a/components/esp_wifi/esp32c3/esp_adapter.c
+++ b/components/esp_wifi/esp32c3/esp_adapter.c
@@ -552,6 +552,15 @@ static uint8_t coex_schm_flexible_period_get_wrapper(void)
 #endif
 }
 
+static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx)
+{
+#if CONFIG_SW_COEXIST_ENABLE
+    return coex_schm_get_phase_by_idx(phase_idx);
+#else
+    return NULL;
+#endif
+}
+
 static void IRAM_ATTR esp_empty_wrapper(void)
 {
 
@@ -687,5 +696,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
     ._coex_schm_register_cb = coex_schm_register_cb_wrapper,
     ._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
     ._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
+    ._coex_schm_get_phase_by_idx = coex_schm_get_phase_by_idx_wrapper,
     ._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
 };
diff --git a/components/esp_wifi/esp32c5/esp_adapter.c b/components/esp_wifi/esp32c5/esp_adapter.c
index f27fb16478..4d490bd7c0 100644
--- a/components/esp_wifi/esp32c5/esp_adapter.c
+++ b/components/esp_wifi/esp32c5/esp_adapter.c
@@ -565,6 +565,15 @@ static uint8_t coex_schm_flexible_period_get_wrapper(void)
 #endif
 }
 
+static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx)
+{
+#if CONFIG_SW_COEXIST_ENABLE
+    return coex_schm_get_phase_by_idx(phase_idx);
+#else
+    return NULL;
+#endif
+}
+
 static void IRAM_ATTR esp_empty_wrapper(void)
 {
 
@@ -709,5 +718,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
     ._coex_schm_register_cb = coex_schm_register_cb_wrapper,
     ._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
     ._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
+    ._coex_schm_get_phase_by_idx = coex_schm_get_phase_by_idx_wrapper,
     ._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
 };
diff --git a/components/esp_wifi/esp32c6/esp_adapter.c b/components/esp_wifi/esp32c6/esp_adapter.c
index 7de78457b6..4ff4bca9c9 100644
--- a/components/esp_wifi/esp32c6/esp_adapter.c
+++ b/components/esp_wifi/esp32c6/esp_adapter.c
@@ -541,6 +541,15 @@ static uint8_t coex_schm_flexible_period_get_wrapper(void)
 #endif
 }
 
+static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx)
+{
+#if CONFIG_SW_COEXIST_ENABLE
+    return coex_schm_get_phase_by_idx(phase_idx);
+#else
+    return NULL;
+#endif
+}
+
 static void IRAM_ATTR esp_empty_wrapper(void)
 {
 
@@ -692,5 +701,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
     ._coex_schm_register_cb = coex_schm_register_cb_wrapper,
     ._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
     ._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
+    ._coex_schm_get_phase_by_idx = coex_schm_get_phase_by_idx_wrapper,
     ._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
 };
diff --git a/components/esp_wifi/esp32p4/esp_adapter.c b/components/esp_wifi/esp32p4/esp_adapter.c
index 4def952a2c..8843258dfc 100644
--- a/components/esp_wifi/esp32p4/esp_adapter.c
+++ b/components/esp_wifi/esp32p4/esp_adapter.c
@@ -554,6 +554,11 @@ static uint8_t coex_schm_flexible_period_get_wrapper(void)
     return 1;
 }
 
+static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx)
+{
+    return NULL;
+}
+
 static void IRAM_ATTR esp_empty_wrapper(void)
 {
 
@@ -810,5 +815,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
     ._coex_schm_register_cb = coex_schm_register_cb_wrapper,
     ._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
     ._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
+    ._coex_schm_get_phase_by_idx = coex_schm_get_phase_by_idx_wrapper,
     ._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
 };
diff --git a/components/esp_wifi/esp32s2/esp_adapter.c b/components/esp_wifi/esp32s2/esp_adapter.c
index 5da62d7d2f..878a12f4eb 100644
--- a/components/esp_wifi/esp32s2/esp_adapter.c
+++ b/components/esp_wifi/esp32s2/esp_adapter.c
@@ -589,6 +589,15 @@ static uint8_t coex_schm_flexible_period_get_wrapper(void)
 #endif
 }
 
+static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx)
+{
+#if CONFIG_SW_COEXIST_ENABLE
+    return coex_schm_get_phase_by_idx(phase_idx);
+#else
+    return NULL;
+#endif
+}
+
 static void IRAM_ATTR esp_empty_wrapper(void)
 {
 
@@ -724,5 +733,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
     ._coex_schm_register_cb = coex_schm_register_cb_wrapper,
     ._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
     ._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
+    ._coex_schm_get_phase_by_idx = coex_schm_get_phase_by_idx_wrapper,
     ._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
 };
diff --git a/components/esp_wifi/esp32s3/esp_adapter.c b/components/esp_wifi/esp32s3/esp_adapter.c
index 0e089b4ddb..15ecb30b5b 100644
--- a/components/esp_wifi/esp32s3/esp_adapter.c
+++ b/components/esp_wifi/esp32s3/esp_adapter.c
@@ -606,6 +606,15 @@ static uint8_t coex_schm_flexible_period_get_wrapper(void)
 #endif
 }
 
+static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx)
+{
+#if CONFIG_SW_COEXIST_ENABLE
+    return coex_schm_get_phase_by_idx(phase_idx);
+#else
+    return NULL;
+#endif
+}
+
 static void IRAM_ATTR esp_empty_wrapper(void)
 {
 
@@ -741,5 +750,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
     ._coex_schm_register_cb = coex_schm_register_cb_wrapper,
     ._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
     ._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
+    ._coex_schm_get_phase_by_idx = coex_schm_get_phase_by_idx_wrapper,
     ._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
 };
diff --git a/components/esp_wifi/include/esp_private/wifi_os_adapter.h b/components/esp_wifi/include/esp_private/wifi_os_adapter.h
index ded8bc0c21..8268c06396 100644
--- a/components/esp_wifi/include/esp_private/wifi_os_adapter.h
+++ b/components/esp_wifi/include/esp_private/wifi_os_adapter.h
@@ -155,6 +155,7 @@ typedef struct wifi_osi_funcs_t {
 #endif
     int (*_coex_schm_flexible_period_set)(uint8_t);
     uint8_t (*_coex_schm_flexible_period_get)(void);
+    void * (*_coex_schm_get_phase_by_idx)(int);
     int32_t _magic;
 } wifi_osi_funcs_t;
 
diff --git a/components/esp_wifi/include/esp_wifi.h b/components/esp_wifi/include/esp_wifi.h
index 3e9eac908a..109af95c97 100644
--- a/components/esp_wifi/include/esp_wifi.h
+++ b/components/esp_wifi/include/esp_wifi.h
@@ -974,6 +974,7 @@ esp_err_t esp_wifi_get_promiscuous_ctrl_filter(wifi_promiscuous_filter_t *filter
   *    - ESP_ERR_WIFI_MODE: invalid mode
   *    - ESP_ERR_WIFI_PASSWORD: invalid password
   *    - ESP_ERR_WIFI_NVS: WiFi internal NVS error
+  *    - ESP_ERR_WIFI_STATE: WiFi still connecting when invoke esp_wifi_set_config
   *    - others: refer to the error code in esp_err.h
   */
 esp_err_t esp_wifi_set_config(wifi_interface_t interface, wifi_config_t *conf);
diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib
index f847af5145..d4f0a1849a 160000
--- a/components/esp_wifi/lib
+++ b/components/esp_wifi/lib
@@ -1 +1 @@
-Subproject commit f847af5145d8b311a52fbc4d38f68e1eb569db57
+Subproject commit d4f0a1849a3f7eb1b5d0a86bd82a0eff5598a1fc
diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
index cc07216d0c..a607325fd0 100644
--- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
@@ -1395,6 +1395,10 @@ config SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE
     bool
     default y
 
+config SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED
+    bool
+    default y
+
 config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
     bool
     default y
diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h
index 12ea7d015f..a74ab16e8b 100644
--- a/components/soc/esp32c6/include/soc/soc_caps.h
+++ b/components/soc/esp32c6/include/soc/soc_caps.h
@@ -550,6 +550,7 @@
 #define SOC_PM_RETENTION_MODULE_NUM         (32)
 
 #define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE  (1)
+#define SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED    (1)
 
 /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
 #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (1)
diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
index 7d19b8acbd..9cdebb6a5f 100644
--- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
@@ -975,6 +975,10 @@ config SOC_PM_PAU_LINK_NUM
     int
     default 4
 
+config SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED
+    bool
+    default y
+
 config SOC_PM_RETENTION_MODULE_NUM
     int
     default 32
diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h
index 6453f091d6..8342636d3a 100644
--- a/components/soc/esp32c61/include/soc/soc_caps.h
+++ b/components/soc/esp32c61/include/soc/soc_caps.h
@@ -534,6 +534,8 @@
 
 #define SOC_PM_PAU_LINK_NUM             (4)
 
+#define SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED    (1)
+
 #define SOC_PM_RETENTION_MODULE_NUM         (32)
 
 /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
diff --git a/docs/en/api-guides/wifi.rst b/docs/en/api-guides/wifi.rst
index f81ced3a1a..05d6645380 100644
--- a/docs/en/api-guides/wifi.rst
+++ b/docs/en/api-guides/wifi.rst
@@ -1825,7 +1825,11 @@ At the start of `Interval` time, RF, PHY, BB would be turned on and kept for `Wi
 
  - Event `WIFI_EVENT_CONNECTIONLESS_MODULE_WAKE_INTERVAL_START`_ would be posted at the start of `Interval`. Since `Window` also starts at that moment, its recommended to TX in that event.
 
- - At connected state, the start of `Interval` would be aligned with TBTT.
+ - At connected state, the start of `Interval` would be aligned with TBTT. To improve the packet reception success rate in connectionless modules, the sender and receiver can be connected to the same AP, and packets can be transmitted within the event `WIFI_EVENT_CONNECTIONLESS_MODULE_WAKE_INTERVAL_START`_. This synchronization helps align the connectionless modules transmission window.
+
+ .. only:: esp32
+
+    On the ESP32, TBTT timing is affected by DFS(Dynamic Frequency Scaling). To synchronize the connectionless modules transmission window using TBTT on the ESP32, DFS must be disabled.
 
 **Window**
 
diff --git a/docs/zh_CN/api-guides/wifi.rst b/docs/zh_CN/api-guides/wifi.rst
index 28146032a7..170acda682 100644
--- a/docs/zh_CN/api-guides/wifi.rst
+++ b/docs/zh_CN/api-guides/wifi.rst
@@ -1797,7 +1797,11 @@ AP 睡眠
 
  - 在 `Interval` 开始时，将会给出 `WIFI_EVENT_CONNECTIONLESS_MODULE_WAKE_INTERVAL_START`_ 事件，由于 `Window` 将在此时开始，可以在此事件内布置发包动作。
 
- - 在连接状态下，`Interval` 开始的时间点将会与 TBTT 时间点对齐。
+ - 在连接状态下，`Interval` 开始的时间点将会与 TBTT 时间点对齐。可以通过将非连接模块的接收端和发送端连接在同一路由器下，并在 `WIFI_EVENT_CONNECTIONLESS_MODULE_WAKE_INTERVAL_START`_ 事件内进行发包，以同步非连接模块的传输窗口，达到提高接收端收包成功率的效果。
+
+ .. only:: esp32
+
+    在 ESP32 上，TBTT 时间点会受到 DFS(Dynamic Frequency Scaling) 的干扰，如果想要在 ESP32 上通过 TBTT 同步非连接模块的传输窗口，需要禁用 DFS。
 
 **Window**