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Merge branch 'bugfix/bod_glitch_reset_c6_v5.0' into 'release/v5.0'

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bootloader: fix BOD and glitch reset on C6 and H2 (v5.0)

See merge request espressif/esp-idf!23407
This commit is contained in:
Jiang Jiang Jian
2023-06-13 10:25:47 +08:00
parent c0f55d9a53 8227ca97bd
commit c82d9ca887
11 changed files with 54 additions and 41 deletions
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4
components/soc/esp32c2/include/soc/rtc_cntl_reg.h
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@@ -1678,6 +1678,10 @@ RO CPU.*/
#define RTC_CNTL_FIB_SEL_V 0x7
#define RTC_CNTL_FIB_SEL_S 0
#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
#define RTC_CNTL_FIB_BOD_RST BIT(1)
#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0xFC)
/* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE : ;bitpos:[31] ;default: 1'b0 ; */
/*description: Need add desc.*/