esp32h2: support GPIO peripheral, IO_MUX, GPIO matrix.

Generic GPIO example is supported as well.

components/driver/gpio.c

@@ -561,7 +561,8 @@ esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
         }
 #endif
         portENTER_CRITICAL(&gpio_context.gpio_spinlock);
-        gpio_hal_wakeup_enable(gpio_context.gpio_hal, gpio_num, intr_type);
+        gpio_hal_set_intr_type(gpio_context.gpio_hal, gpio_num, intr_type);
+        gpio_hal_wakeup_enable(gpio_context.gpio_hal, gpio_num);
 #if SOC_GPIO_SUPPORT_SLP_SWITCH && CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND
         gpio_hal_sleep_sel_dis(gpio_context.gpio_hal, gpio_num);
 #endif
@@ -696,7 +697,7 @@ esp_err_t gpio_force_hold_all()
     rtc_gpio_force_hold_all();
 #endif
     portENTER_CRITICAL(&gpio_context.gpio_spinlock);
-    gpio_hal_force_hold_all(gpio_context.gpio_hal);
+    gpio_hal_force_hold_all();
     portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
     return ESP_OK;
 }

components/driver/test/test_gpio.c

@@ -70,6 +70,15 @@
 #define TEST_GPIO_OUTPUT_MAX            GPIO_NUM_MAX
 #define TEST_GPIO_INPUT_LEVEL_HIGH_PIN  10
 #define TEST_GPIO_INPUT_LEVEL_LOW_PIN   1
+#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
+#define TEST_GPIO_EXT_OUT_IO            6  // default output GPIO
+#define TEST_GPIO_EXT_IN_IO             7  // default input GPIO
+#define TEST_GPIO_OUTPUT_PIN            1
+#define TEST_GPIO_OUTPUT_MAX            GPIO_NUM_MAX
+#define TEST_GPIO_USB_DM_IO             24  // USB D- GPIO
+#define TEST_GPIO_USB_DP_IO             25  // USB D+ GPIO
+#define TEST_GPIO_INPUT_LEVEL_HIGH_PIN  9
+#define TEST_GPIO_INPUT_LEVEL_LOW_PIN   1
 #endif
 
 // If there is any input-only pin, enable input-only pin part of some tests.
@@ -113,7 +122,7 @@ __attribute__((unused)) static void gpio_isr_edge_handler(void *arg)
     edge_intr_times++;
 }
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2)
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32H2)
 //No runners
 // level interrupt event with "gpio_intr_disable"
 static void gpio_isr_level_handler(void *arg)
@@ -138,7 +147,7 @@ static void gpio_isr_level_handler2(void *arg)
     esp_rom_printf("GPIO[%d] intr, val: %d, level_intr_times = %d\n", TEST_GPIO_EXT_OUT_IO, gpio_get_level(TEST_GPIO_EXT_OUT_IO), level_intr_times);
     esp_rom_printf("GPIO[%d] intr, val: %d, level_intr_times = %d\n", gpio_num, gpio_get_level(gpio_num), level_intr_times);
 }
-#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3)
+#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32H2)
 
 #if !WAKE_UP_IGNORE
 // get result of waking up or not
@@ -223,7 +232,7 @@ TEST_CASE("GPIO config parameters test", "[gpio]")
 #endif // SOC_HAS_INPUT_ONLY_PIN
 }
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2)
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32H2)
 //No runners
 TEST_CASE("GPIO rising edge interrupt test", "[gpio][test_env=UT_T1_GPIO]")
 {
@@ -415,7 +424,7 @@ TEST_CASE("GPIO enable and disable interrupt test", "[gpio][test_env=UT_T1_GPIO]
     TEST_ASSERT(gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_level_handler, (void *) TEST_GPIO_EXT_IN_IO) == ESP_ERR_INVALID_STATE);
     TEST_ASSERT(gpio_isr_handler_remove(TEST_GPIO_EXT_IN_IO) == ESP_ERR_INVALID_STATE);
 }
-#endif //DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3)
+#endif //DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32H2)
 
 #if !CONFIG_FREERTOS_UNICORE
 static void install_isr_service_task(void *arg)
@@ -527,7 +536,7 @@ TEST_CASE("GPIO io pull up/down function", "[gpio]")
     TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(TEST_GPIO_EXT_IN_IO), 0, "gpio_pullup_dis error, it can pull up");
 }
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2)
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32H2)
 //No runners
 TEST_CASE("GPIO output and input mode test", "[gpio][test_env=UT_T1_GPIO]")
 {
@@ -601,7 +610,7 @@ TEST_CASE("GPIO repeate call service and isr has no memory leak test", "[gpio][t
     }
     TEST_ASSERT_INT32_WITHIN(size, esp_get_free_heap_size(), 100);
 }
-#endif //DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3)
+#endif //DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32H2)
 
 #if !WAKE_UP_IGNORE
 //this function development is not completed yet, set it ignored
@@ -848,7 +857,7 @@ TEST_CASE("GPIO ISR service test", "[gpio][ignore]")
     TEST_ASSERT((io9_param.isr_cnt == 1) && (io10_param.isr_cnt == 1));
 }
 
-#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
+#if SOC_USB_SERIAL_JTAG_SUPPORTED
 TEST_CASE("GPIO input and output of USB pins test", "[gpio]")
 {
     const int test_pins[] = {TEST_GPIO_USB_DP_IO, TEST_GPIO_USB_DM_IO};
@@ -885,4 +894,4 @@ TEST_CASE("GPIO input and output of USB pins test", "[gpio]")
         TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(pin), 1, "get level error! the level should be high!");
     }
 }
-#endif //CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
+#endif //SOC_USB_SERIAL_JTAG_SUPPORTED

components/esp_hw_support/port/esp32h2/rtc_clk_init.c

@@ -21,7 +21,6 @@
 #include "hal/cpu_hal.h"
 #include "regi2c_ctrl.h"
 #include "soc_log.h"
-#include "sdkconfig.h"
 #include "rtc_clk_common.h"
 #include "esp_rom_uart.h"
 #include "soc/efuse_reg.h"

components/hal/CMakeLists.txt

@@ -8,6 +8,14 @@ set(srcs "wdt_hal_iram.c"
 
 set(includes "${target}/include" "include" "platform_port/include")
 
+if(target STREQUAL "esp32h2")
+    if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1)
+        list(APPEND includes "${target}/include/rev1")
+    elseif(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2)
+        list(APPEND includes "${target}/include/rev2")
+    endif()
+endif()
+
 if(NOT BOOTLOADER_BUILD)
     list(APPEND srcs
         "rtc_io_hal.c"

components/hal/esp32/include/hal/gpio_ll.h

@@ -338,7 +338,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number
   */
-static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
+static inline __attribute__((always_inline)) void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
     if (gpio_num < 32) {
         hw->enable_w1ts = (0x1 << gpio_num);
@@ -397,7 +397,7 @@ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, gpio_num_t gpio_n
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number
   */
-static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+static inline __attribute__((always_inline)) void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
     hw->pin[gpio_num].pad_driver = 0;
 }
@@ -463,11 +463,9 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num)
  *
  * @param hw Peripheral GPIO hardware instance address.
  * @param gpio_num GPIO number.
- * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used.
  */
-static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
+static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    hw->pin[gpio_num].int_type = intr_type;
     hw->pin[gpio_num].wakeup_enable = 0x1;
 }
 

components/hal/esp32c2/include/hal/gpio_ll.h

@@ -7,7 +7,7 @@
 /*******************************************************************************
  * NOTICE
  * The hal is not public api, don't use in application code.
- * See readme.md in soc/include/hal/readme.md
+ * See readme.md in hal/include/hal/readme.md
  ******************************************************************************/
 
 // The LL layer for ESP32-C2 GPIO register operations
@@ -198,7 +198,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number
   */
-static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
+static inline __attribute__((always_inline)) void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
     hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num);
 }
@@ -209,7 +209,7 @@ static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number
   */
-static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+static inline __attribute__((always_inline)) void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
     hw->pin[gpio_num].pad_driver = 0;
 }
@@ -263,11 +263,9 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num)
  *
  * @param hw Peripheral GPIO hardware instance address.
  * @param gpio_num GPIO number.
- * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used.
  */
-static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
+static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    hw->pin[gpio_num].int_type = intr_type;
     hw->pin[gpio_num].wakeup_enable = 0x1;
 }
 
@@ -397,13 +395,21 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
     gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func);
 }
 
-static inline void gpio_ll_force_hold_all(gpio_dev_t *hw)
+/**
+  * @brief Force hold digital and rtc gpio pad.
+  * @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
+  */
+static inline void gpio_ll_force_hold_all(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
     SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
     SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M);
 }
 
+/**
+  * @brief Force unhold digital and rtc gpio pad.
+  * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
+  */
 static inline void gpio_ll_force_unhold_all(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);

components/hal/esp32c3/include/hal/gpio_ll.h

@@ -7,7 +7,7 @@
 /*******************************************************************************
  * NOTICE
  * The hal is not public api, don't use in application code.
- * See readme.md in soc/include/hal/readme.md
+ * See readme.md in hal/include/hal/readme.md
  ******************************************************************************/
 
 // The LL layer for ESP32-C3 GPIO register operations
@@ -200,7 +200,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number
   */
-static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
+static inline __attribute__((always_inline)) void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
     hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num);
 }
@@ -211,7 +211,7 @@ static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number
   */
-static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+static inline __attribute__((always_inline)) void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
     hw->pin[gpio_num].pad_driver = 0;
 }
@@ -265,11 +265,9 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num)
  *
  * @param hw Peripheral GPIO hardware instance address.
  * @param gpio_num GPIO number.
- * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used.
  */
-static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
+static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    hw->pin[gpio_num].int_type = intr_type;
     hw->pin[gpio_num].wakeup_enable = 0x1;
 }
 
@@ -403,13 +401,21 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
     gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func);
 }
 
-static inline void gpio_ll_force_hold_all(gpio_dev_t *hw)
+/**
+  * @brief Force hold digital and rtc gpio pad.
+  * @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
+  */
+static inline void gpio_ll_force_hold_all(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
     SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
     SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M);
 }
 
+/**
+  * @brief Force unhold digital and rtc gpio pad.
+  * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
+  */
 static inline void gpio_ll_force_unhold_all(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);

components/hal/esp32h2/include/rev1/hal/gpio_ll.h

@@ -0,0 +1,597 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The hal is not public api, don't use in application code.
+ * See readme.md in hal/include/hal/readme.md
+ ******************************************************************************/
+
+// The LL layer for ESP32-H2 GPIO register operations
+
+#pragma once
+
+#include "soc/soc.h"
+#include "soc/gpio_periph.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/gpio_struct.h"
+#include "soc/usb_serial_jtag_reg.h"
+#include "hal/gpio_types.h"
+#include "hal/assert.h"
+#include "stdlib.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Get GPIO hardware instance with giving gpio num
+#define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL)
+
+#define GPIO_LL_PRO_CPU_INTR_ENA      (BIT(0))
+#define GPIO_LL_PRO_CPU_NMI_INTR_ENA  (BIT(1))
+/**
+  * @brief Enable pull-up on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
+}
+
+/**
+  * @brief Disable pull-up on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
+}
+
+/**
+  * @brief Enable pull-down on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
+}
+
+/**
+  * @brief Disable pull-down on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
+}
+
+/**
+ * @brief  GPIO set interrupt trigger type
+ *
+ * @param  hw Peripheral GPIO hardware instance address.
+ * @param  gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ * @param  intr_type Interrupt type, select from gpio_int_type_t
+ */
+static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
+{
+    hw->pin[gpio_num].pin_int_type = intr_type;
+}
+
+/**
+  * @brief Get GPIO interrupt status
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param core_id interrupt core id
+  * @param status interrupt status
+  */
+static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
+{
+    *status = hw->pcpu_int.procpu_int;
+}
+
+/**
+  * @brief Get GPIO interrupt status high
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param core_id interrupt core id
+  * @param status interrupt status high
+  */
+static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
+{
+    *status = hw->pcpu_int1.procpu_int1;
+}
+
+/**
+  * @brief Clear GPIO interrupt status
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param mask interrupt status clear mask
+  */
+static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
+{
+    hw->status_w1tc.status_w1tc = mask;
+}
+
+/**
+  * @brief Clear GPIO interrupt status high
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param mask interrupt status high clear mask
+  */
+static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
+{
+    hw->status1_w1tc.status1_w1tc = mask;
+}
+
+/**
+ * @brief  Enable GPIO module interrupt signal
+ *
+ * @param  hw Peripheral GPIO hardware instance address.
+ * @param  core_id Interrupt enabled CPU to corresponding ID
+ * @param  gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ */
+static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num)
+{
+    HAL_ASSERT(core_id == 0 && "target SoC only has a single core");
+    GPIO.pin[gpio_num].pin_int_ena = GPIO_LL_PRO_CPU_INTR_ENA;     //enable pro cpu intr
+}
+
+/**
+ * @brief  Disable GPIO module interrupt signal
+ *
+ * @param  hw Peripheral GPIO hardware instance address.
+ * @param  gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ */
+static inline void gpio_ll_intr_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    hw->pin[gpio_num].pin_int_ena = 0;                             //disable GPIO intr
+}
+
+/**
+  * @brief Disable input mode on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Enable input mode on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Disable output mode on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    if (gpio_num < 32) {
+        hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num);
+    } else {
+        hw->enable1_w1tc.enable1_w1tc = (0x1 << (gpio_num - 32));
+    }
+    // Ensure no other output signal is routed via GPIO matrix to this pin
+    REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4),
+              SIG_GPIO_OUT_IDX);
+}
+
+/**
+  * @brief Enable output mode on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline __attribute__((always_inline)) void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    if (gpio_num < 32) {
+        hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num);
+    } else {
+        hw->enable1_w1ts.enable1_w1ts = (0x1 << (gpio_num - 32));
+    }
+}
+
+/**
+  * @brief Disable open-drain mode on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline __attribute__((always_inline)) void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    hw->pin[gpio_num].pin_pad_driver = 0;
+}
+
+/**
+  * @brief Enable open-drain mode on GPIO.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    hw->pin[gpio_num].pin_pad_driver = 1;
+}
+
+/**
+ * @brief  GPIO set output level
+ *
+ * @param  hw Peripheral GPIO hardware instance address.
+ * @param  gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ * @param  level Output level. 0: low ; 1: high
+ */
+static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32_t level)
+{
+    if (level) {
+        if (gpio_num < 32) {
+            hw->out_w1ts.out_w1ts = (1 << gpio_num);
+        } else {
+            hw->out1_w1ts.out1_w1ts = (1 << (gpio_num - 32));
+        }
+    } else {
+        if (gpio_num < 32) {
+            hw->out_w1tc.out_w1tc = (1 << gpio_num);
+        } else {
+            hw->out1_w1tc.out1_w1tc = (1 << (gpio_num - 32));
+        }
+    }
+}
+
+/**
+ * @brief  GPIO get input level
+ *
+ * @warning If the pad is not configured for input (or input and output) the returned value is always 0.
+ *
+ * @param  hw Peripheral GPIO hardware instance address.
+ * @param  gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ *
+ * @return
+ *     - 0 the GPIO input level is 0
+ *     - 1 the GPIO input level is 1
+ */
+static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    if (gpio_num < 32) {
+        return (hw->in.in_data_next >> gpio_num) & 0x1;
+    } else {
+        return (hw->in1.in1_data_next >> (gpio_num - 32)) & 0x1;
+    }
+}
+
+/**
+ * @brief Enable GPIO wake-up function.
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number.
+ */
+static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    hw->pin[gpio_num].pin_wakeup_enable = 0x1;
+}
+
+/**
+ * @brief Disable GPIO wake-up function.
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number
+ */
+static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    hw->pin[gpio_num].pin_wakeup_enable = 0;
+}
+
+/**
+  * @brief Set GPIO pad drive capability
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number, only support output GPIOs
+  * @param strength Drive capability of the pad
+  */
+static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t strength)
+{
+    SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S);
+}
+
+/**
+  * @brief Get GPIO pad drive capability
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number, only support output GPIOs
+  * @param strength Pointer to accept drive capability of the pad
+  */
+static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t *strength)
+{
+    *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
+}
+
+/**
+  * @brief Enable all digital gpio pad hold function during Deep-sleep.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  */
+static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw)
+{
+    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M);
+}
+
+/**
+  * @brief Disable all digital gpio pad hold function during Deep-sleep.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  */
+static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw)
+{
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD);
+}
+
+/**
+  * @brief Enable gpio pad hold function.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number, only support output GPIOs
+  */
+static inline void gpio_ll_hold_en(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    if (gpio_num <= GPIO_NUM_5) {
+        REG_SET_BIT(RTC_CNTL_PAD_HOLD_REG, BIT(gpio_num));
+    } else if (gpio_num <= GPIO_NUM_31) {
+        SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
+    } else {
+        SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD1_REG, GPIO_HOLD_MASK[gpio_num]);
+    }
+}
+
+/**
+  * @brief Disable gpio pad hold function.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number, only support output GPIOs
+  */
+static inline void gpio_ll_hold_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    if (gpio_num <= GPIO_NUM_5) {
+        REG_CLR_BIT(RTC_CNTL_PAD_HOLD_REG, BIT(gpio_num));
+    } else if (gpio_num <= GPIO_NUM_31) {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
+    } else {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD1_REG, GPIO_HOLD_MASK[gpio_num]);
+    }
+}
+
+/**
+  * @brief Set pad input to a peripheral signal through the IOMUX.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number of the pad.
+  * @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``.
+  */
+static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx)
+{
+    hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0;
+    PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]);
+}
+
+/**
+ * @brief  Select a function for the pin in the IOMUX
+ *
+ * @param  pin_name Pin name to configure
+ * @param  func Function to assign to the pin
+ */
+static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
+{
+    // Disable USB Serial JTAG if pins 18 or pins 19 needs to select an IOMUX function
+    if (pin_name == IO_MUX_GPIO18_REG || pin_name == IO_MUX_GPIO19_REG) {
+        CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
+    }
+    PIN_FUNC_SELECT(pin_name, func);
+}
+
+/**
+  * @brief Set peripheral output to an GPIO pad through the IOMUX.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num gpio_num GPIO number of the pad.
+  * @param func The function number of the peripheral pin to output pin.
+  *        One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``.
+  * @param oen_inv True if the output enable needs to be inverted, otherwise False.
+  */
+static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv)
+{
+    hw->func_out_sel_cfg[gpio_num].func_oen_sel = 0;
+    hw->func_out_sel_cfg[gpio_num].func_oen_inv_sel = oen_inv;
+    gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func);
+}
+
+/**
+  * @brief Force hold digital and rtc gpio pad.
+  * @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
+  */
+static inline void gpio_ll_force_hold_all(void)
+{
+    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
+    SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M);
+}
+
+/**
+  * @brief Force unhold digital and rtc gpio pad.
+  * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
+  */
+static inline void gpio_ll_force_unhold_all(void)
+{
+    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
+    CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD);
+}
+
+/**
+  * @brief Enable GPIO pin used for wakeup from sleep.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    PIN_SLP_SEL_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Disable GPIO pin used for wakeup from sleep.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    PIN_SLP_SEL_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Disable GPIO pull-up in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    PIN_SLP_PULLUP_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Enable GPIO pull-up in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    PIN_SLP_PULLUP_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Enable GPIO pull-down in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    PIN_SLP_PULLDOWN_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Disable GPIO pull-down in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    PIN_SLP_PULLDOWN_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Disable GPIO input in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    PIN_SLP_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Enable GPIO input in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    PIN_SLP_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Disable GPIO output in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    PIN_SLP_OUTPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+  * @brief Enable GPIO output in sleep mode.
+  *
+  * @param hw Peripheral GPIO hardware instance address.
+  * @param gpio_num GPIO number
+  */
+static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    PIN_SLP_OUTPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+}
+
+/**
+ * @brief Enable GPIO deep-sleep wake-up function.
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number.
+ * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used.
+ */
+static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
+{
+    HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function");
+
+    REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN_CLK_GATE);
+    REG_SET_BIT(RTC_CNTL_EXT_WAKEUP_CONF_REG, RTC_CNTL_GPIO_WAKEUP_FILTER);
+    SET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num));
+    uint32_t reg = REG_READ(RTC_CNTL_GPIO_WAKEUP_REG);
+    reg &= (~(RTC_CNTL_GPIO_PIN0_INT_TYPE_V << (RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3)));
+    reg |= (intr_type << (RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3));
+    REG_WRITE(RTC_CNTL_GPIO_WAKEUP_REG, reg);
+}
+
+/**
+ * @brief Disable GPIO deep-sleep wake-up function.
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number
+ */
+static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+{
+    HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function");
+
+    CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num));
+    CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3);
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/rev2/hal/gpio_ll.h

@@ -7,7 +7,7 @@
 /*******************************************************************************
  * NOTICE
  * The hal is not public api, don't use in application code.
- * See readme.md in soc/include/hal/readme.md
+ * See readme.md in hal/include/hal/readme.md
  ******************************************************************************/
 
 // The LL layer for ESP32-H2 GPIO register operations
@@ -18,24 +18,15 @@
 #include "soc/gpio_periph.h"
 #include "soc/rtc_cntl_reg.h"
 #include "soc/gpio_struct.h"
+#include "soc/usb_serial_jtag_reg.h"
 #include "hal/gpio_types.h"
+#include "hal/assert.h"
 #include "stdlib.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/*
- * The following defines are used to disable USB JTAG when pins 18 and pins 19
- * are set to be used as GPIO.
- * See gpio_pad_select_gpio() below.
- *
- * TODO: Delete these definitions once the USB device registers definition is
- * merged.
- */
-#define USB_DEVICE_CONF0_REG        (0x60043018)
-#define USB_DEVICE_USB_PAD_ENABLE   (BIT(14))
-
 // Get GPIO hardware instance with giving gpio num
 #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL)
 
@@ -94,7 +85,7 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
 {
-    hw->pin[gpio_num].int_type = intr_type;
+    hw->pin[gpio_num].pin_int_type = intr_type;
 }
 
 /**
@@ -106,7 +97,7 @@ static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, gpio_num_t gpio_num, gp
   */
 static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
-    *status = hw->pcpu_int.intr;
+    *status = hw->pcpu_int.procpu_int;
 }
 
 /**
@@ -118,7 +109,7 @@ static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uin
   */
 static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
-    *status = 0; // Less than 32 GPIOs in ESP32-H2
+    *status = 0; // Less than 32 GPIOs in ESP32-H2Beta2
 }
 
 /**
@@ -140,7 +131,7 @@ static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
   */
 static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 {
-    // Not supported on C3
+    // Less than 32 GPIOs in ESP32-H2Beta2. Do nothing.
 }
 
 /**
@@ -152,11 +143,8 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
  */
 static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num)
 {
-    if (core_id == 0) {
+    HAL_ASSERT(core_id == 0 && "target SoC only has a single core");
-        GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA;     //enable pro cpu intr
+    GPIO.pin[gpio_num].pin_int_ena = GPIO_LL_PRO_CPU_INTR_ENA;     //enable pro cpu intr
-    } else {
-        // GPIO.pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA;     //enable pro cpu intr
-    }
 }
 
 /**
@@ -167,7 +155,7 @@ static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id,
  */
 static inline void gpio_ll_intr_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    hw->pin[gpio_num].int_ena = 0;                             //disable GPIO intr
+    hw->pin[gpio_num].pin_int_ena = 0;                             //disable GPIO intr
 }
 
 /**
@@ -212,7 +200,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number
   */
-static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
+static inline __attribute__((always_inline)) void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
     hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num);
 }
@@ -223,9 +211,9 @@ static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number
   */
-static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+static inline __attribute__((always_inline)) void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    hw->pin[gpio_num].pad_driver = 0;
+    hw->pin[gpio_num].pin_pad_driver = 0;
 }
 
 /**
@@ -236,7 +224,7 @@ static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
   */
 static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    hw->pin[gpio_num].pad_driver = 1;
+    hw->pin[gpio_num].pin_pad_driver = 1;
 }
 
 /**
@@ -269,7 +257,7 @@ static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32
  */
 static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    return (hw->in.data >> gpio_num) & 0x1;
+    return (hw->in.in_data_next >> gpio_num) & 0x1;
 }
 
 /**
@@ -277,12 +265,10 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num)
  *
  * @param hw Peripheral GPIO hardware instance address.
  * @param gpio_num GPIO number.
- * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used.
  */
-static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
+static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    hw->pin[gpio_num].int_type = intr_type;
+    hw->pin[gpio_num].pin_wakeup_enable = 0x1;
-    hw->pin[gpio_num].wakeup_enable = 0x1;
 }
 
 /**
@@ -293,7 +279,7 @@ static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gp
  */
 static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    hw->pin[gpio_num].wakeup_enable = 0;
+    hw->pin[gpio_num].pin_wakeup_enable = 0;
 }
 
 /**
@@ -327,6 +313,7 @@ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_
   */
 static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw)
 {
+    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
     SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M);
 }
 
@@ -348,8 +335,8 @@ static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw)
   */
 static inline void gpio_ll_hold_en(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    if (gpio_num <= GPIO_NUM_5) {
+    if (gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_12) {
-        REG_SET_BIT(RTC_CNTL_PAD_HOLD_REG, BIT(gpio_num));
+        REG_SET_BIT(RTC_CNTL_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
     } else {
         SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
     }
@@ -363,8 +350,8 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, gpio_num_t gpio_num)
   */
 static inline void gpio_ll_hold_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    if (gpio_num <= GPIO_NUM_5) {
+    if (gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_12) {
-        REG_CLR_BIT(RTC_CNTL_PAD_HOLD_REG, BIT(gpio_num));
+        REG_CLR_BIT(RTC_CNTL_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
     } else {
         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
     }
@@ -391,8 +378,9 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign
  */
 static inline __attribute__((always_inline)) void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
 {
-    if (pin_name == IO_MUX_GPIO18_REG || pin_name == IO_MUX_GPIO19_REG) {
+    // Disable USB Serial JTAG if pin 24 or pin 25 needs to select an IOMUX function
-        CLEAR_PERI_REG_MASK(USB_DEVICE_CONF0_REG, USB_DEVICE_USB_PAD_ENABLE);
+    if (pin_name == IO_MUX_GPIO24_REG || pin_name == IO_MUX_GPIO25_REG) {
+        CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
     }
     PIN_FUNC_SELECT(pin_name, func);
 }
@@ -408,18 +396,26 @@ static inline __attribute__((always_inline)) void gpio_ll_iomux_func_sel(uint32_
   */
 static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv)
 {
-    hw->func_out_sel_cfg[gpio_num].oen_sel = 0;
+    hw->func_out_sel_cfg[gpio_num].func_oen_sel = 0;
-    hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
+    hw->func_out_sel_cfg[gpio_num].func_oen_inv_sel = oen_inv;
     gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func);
 }
 
-static inline void gpio_ll_force_hold_all(gpio_dev_t *hw)
+/**
+  * @brief Force hold digital and rtc gpio pad.
+  * @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
+  */
+static inline void gpio_ll_force_hold_all(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
     SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
     SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M);
 }
 
+/**
+  * @brief Force unhold digital and rtc gpio pad.
+  * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
+  */
 static inline void gpio_ll_force_unhold_all(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
@@ -547,9 +543,9 @@ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, gpio_num_t gpio_n
  */
 static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
 {
-    if (gpio_num > GPIO_NUM_5) {
+    HAL_ASSERT((gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_12) &&
-        abort(); // gpio lager than 5 doesn't support.
+                "only gpio7~12 support deep sleep wake-up function");
-    }
+
     REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN_CLK_GATE);
     REG_SET_BIT(RTC_CNTL_EXT_WAKEUP_CONF_REG, RTC_CNTL_GPIO_WAKEUP_FILTER);
     SET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num));
@@ -567,9 +563,9 @@ static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, gpio_num_t gp
  */
 static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    if (gpio_num > GPIO_NUM_5) {
+    HAL_ASSERT((gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_12) &&
-        abort(); // gpio lager than 5 doesn't support.
+                "only gpio7~12 support deep sleep wake-up function");
-    }
+
     CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num));
     CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3);
 }

components/hal/esp32s2/include/hal/gpio_ll.h

@@ -205,7 +205,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number
   */
-static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
+static inline __attribute__((always_inline)) void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
     if (gpio_num < 32) {
         hw->enable_w1ts = (0x1 << gpio_num);
@@ -220,7 +220,7 @@ static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number
   */
-static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+static inline __attribute__((always_inline)) void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
     hw->pin[gpio_num].pad_driver = 0;
 }
@@ -286,11 +286,9 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num)
  *
  * @param hw Peripheral GPIO hardware instance address.
  * @param gpio_num GPIO number.
- * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used.
  */
-static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
+static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    hw->pin[gpio_num].int_type = intr_type;
     hw->pin[gpio_num].wakeup_enable = 0x1;
 }
 
@@ -411,12 +409,20 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
     gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func);
 }
 
-static inline void gpio_ll_force_hold_all(gpio_dev_t *hw)
+/**
+  * @brief Force hold digital and rtc gpio pad.
+  * @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
+  */
+static inline void gpio_ll_force_hold_all(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
     SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
 }
 
+/**
+  * @brief Force unhold digital and rtc gpio pad.
+  * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
+  */
 static inline void gpio_ll_force_unhold_all(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);

components/hal/esp32s3/include/hal/gpio_ll.h

@@ -210,7 +210,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number
   */
-static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
+static inline __attribute__((always_inline)) void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
     if (gpio_num < 32) {
         hw->enable_w1ts = (0x1 << gpio_num);
@@ -225,7 +225,7 @@ static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number
   */
-static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
+static inline __attribute__((always_inline)) void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
     hw->pin[gpio_num].pad_driver = 0;
 }
@@ -291,11 +291,9 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num)
  *
  * @param hw Peripheral GPIO hardware instance address.
  * @param gpio_num GPIO number.
- * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used.
  */
-static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
+static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    hw->pin[gpio_num].int_type = intr_type;
     hw->pin[gpio_num].wakeup_enable = 0x1;
 }
 
@@ -419,12 +417,20 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
     gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func);
 }
 
-static inline void gpio_ll_force_hold_all(gpio_dev_t *hw)
+/**
+  * @brief Force hold digital and rtc gpio pad.
+  * @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
+  */
+static inline void gpio_ll_force_hold_all(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
     SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
 }
 
+/**
+  * @brief Force unhold digital and rtc gpio pad.
+  * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
+  */
 static inline void gpio_ll_force_unhold_all(void)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);

components/hal/include/hal/gpio_hal.h

@@ -203,9 +203,8 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, gpio_num_t gpio_num);
  *
  * @param hal Context of the HAL layer
  * @param gpio_num GPIO number.
- * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used.
  */
-#define gpio_hal_wakeup_enable(hal, gpio_num, intr_type) gpio_ll_wakeup_enable((hal)->dev, gpio_num, intr_type)
+#define gpio_hal_wakeup_enable(hal, gpio_num) gpio_ll_wakeup_enable((hal)->dev, gpio_num)
 
 /**
  * @brief Disable GPIO wake-up function.
@@ -312,17 +311,13 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, gpio_num_t gpio_num);
 /**
   * @brief Force hold digital and rtc gpio pad.
   * @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
-  *
+  */
-  * @param hal Context of the HAL layer
+#define gpio_hal_force_hold_all() gpio_ll_force_hold_all()
-  * */
-#define gpio_hal_force_hold_all(hal) gpio_ll_force_hold_all((hal)->dev)
 
 /**
   * @brief Force unhold digital and rtc gpio pad.
   * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
-  *
+  */
-  * @param hal Context of the HAL layer
-  * */
 #define gpio_hal_force_unhold_all() gpio_ll_force_unhold_all()
 #endif
 

components/hal/include/hal/gpio_types.h

@@ -19,62 +19,6 @@ typedef enum {
     GPIO_PORT_MAX,
 } gpio_port_t;
 
-#define GPIO_SEL_0              (BIT(0))                         /*!< Pin 0 selected */
-#define GPIO_SEL_1              (BIT(1))                         /*!< Pin 1 selected */
-#define GPIO_SEL_2              (BIT(2))                         /*!< Pin 2 selected */
-#define GPIO_SEL_3              (BIT(3))                         /*!< Pin 3 selected */
-#define GPIO_SEL_4              (BIT(4))                         /*!< Pin 4 selected */
-#define GPIO_SEL_5              (BIT(5))                         /*!< Pin 5 selected */
-#define GPIO_SEL_6              (BIT(6))                         /*!< Pin 6 selected */
-#define GPIO_SEL_7              (BIT(7))                         /*!< Pin 7 selected */
-#define GPIO_SEL_8              (BIT(8))                         /*!< Pin 8 selected */
-#define GPIO_SEL_9              (BIT(9))                         /*!< Pin 9 selected */
-#define GPIO_SEL_10             (BIT(10))                        /*!< Pin 10 selected */
-#define GPIO_SEL_11             (BIT(11))                        /*!< Pin 11 selected */
-#define GPIO_SEL_12             (BIT(12))                        /*!< Pin 12 selected */
-#define GPIO_SEL_13             (BIT(13))                        /*!< Pin 13 selected */
-#define GPIO_SEL_14             (BIT(14))                        /*!< Pin 14 selected */
-#define GPIO_SEL_15             (BIT(15))                        /*!< Pin 15 selected */
-#define GPIO_SEL_16             (BIT(16))                        /*!< Pin 16 selected */
-#define GPIO_SEL_17             (BIT(17))                        /*!< Pin 17 selected */
-#define GPIO_SEL_18             (BIT(18))                        /*!< Pin 18 selected */
-#define GPIO_SEL_19             (BIT(19))                        /*!< Pin 19 selected */
-#define GPIO_SEL_20             (BIT(20))                        /*!< Pin 20 selected */
-#define GPIO_SEL_21             (BIT(21))                        /*!< Pin 21 selected */
-#if CONFIG_IDF_TARGET_ESP32
-#define GPIO_SEL_22             (BIT(22))                        /*!< Pin 22 selected */
-#define GPIO_SEL_23             (BIT(23))                        /*!< Pin 23 selected */
-
-#define GPIO_SEL_25             (BIT(25))                        /*!< Pin 25 selected */
-#endif
-#define GPIO_SEL_26             (BIT(26))                        /*!< Pin 26 selected */
-#define GPIO_SEL_27             (BIT(27))                        /*!< Pin 27 selected */
-#define GPIO_SEL_28             (BIT(28))                        /*!< Pin 28 selected */
-#define GPIO_SEL_29             (BIT(29))                        /*!< Pin 29 selected */
-#define GPIO_SEL_30             (BIT(30))                        /*!< Pin 30 selected */
-#define GPIO_SEL_31             (BIT(31))                        /*!< Pin 31 selected */
-#define GPIO_SEL_32             ((uint64_t)(((uint64_t)1)<<32))  /*!< Pin 32 selected */
-#define GPIO_SEL_33             ((uint64_t)(((uint64_t)1)<<33))  /*!< Pin 33 selected */
-#define GPIO_SEL_34             ((uint64_t)(((uint64_t)1)<<34))  /*!< Pin 34 selected */
-#define GPIO_SEL_35             ((uint64_t)(((uint64_t)1)<<35))  /*!< Pin 35 selected */
-#define GPIO_SEL_36             ((uint64_t)(((uint64_t)1)<<36))  /*!< Pin 36 selected */
-#define GPIO_SEL_37             ((uint64_t)(((uint64_t)1)<<37))  /*!< Pin 37 selected */
-#define GPIO_SEL_38             ((uint64_t)(((uint64_t)1)<<38))  /*!< Pin 38 selected */
-#define GPIO_SEL_39             ((uint64_t)(((uint64_t)1)<<39))  /*!< Pin 39 selected */
-#if SOC_GPIO_PIN_COUNT > 40
-#define GPIO_SEL_40             ((uint64_t)(((uint64_t)1)<<40))  /*!< Pin 40 selected */
-#define GPIO_SEL_41             ((uint64_t)(((uint64_t)1)<<41))  /*!< Pin 41 selected */
-#define GPIO_SEL_42             ((uint64_t)(((uint64_t)1)<<42))  /*!< Pin 42 selected */
-#define GPIO_SEL_43             ((uint64_t)(((uint64_t)1)<<43))  /*!< Pin 43 selected */
-#define GPIO_SEL_44             ((uint64_t)(((uint64_t)1)<<44))  /*!< Pin 44 selected */
-#define GPIO_SEL_45             ((uint64_t)(((uint64_t)1)<<45))  /*!< Pin 45 selected */
-#define GPIO_SEL_46             ((uint64_t)(((uint64_t)1)<<46))  /*!< Pin 46 selected */
-#if CONFIG_IDF_TARGET_ESP32S3
-#define GPIO_SEL_47             ((uint64_t)(((uint64_t)1)<<47))  /*!< Pin 47 selected */
-#define GPIO_SEL_48             ((uint64_t)(((uint64_t)1)<<48))  /*!< Pin 48 selected */
-#endif
-#endif
-
 #define GPIO_PIN_REG_0          IO_MUX_GPIO0_REG
 #define GPIO_PIN_REG_1          IO_MUX_GPIO1_REG
 #define GPIO_PIN_REG_2          IO_MUX_GPIO2_REG
@@ -298,7 +242,7 @@ typedef enum {
     GPIO_NUM_MAX,
 /** @endcond */
 } gpio_num_t;
-#elif CONFIG_IDF_TARGET_ESP32H2
+#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
 typedef enum {
     GPIO_NUM_NC = -1,    /*!< Use to signal not connected to S/W */
     GPIO_NUM_0 = 0,     /*!< GPIO0, input and output */
@@ -324,6 +268,9 @@ typedef enum {
     GPIO_NUM_20 = 20,   /*!< GPIO20, input and output */
     GPIO_NUM_21 = 21,   /*!< GPIO21, input and output */
     GPIO_NUM_22 = 22,   /*!< GPIO22, input and output */
+    GPIO_NUM_23 = 23,   /*!< GPIO23, input and output */
+    GPIO_NUM_24 = 24,   /*!< GPIO24, input and output */
+    GPIO_NUM_25 = 25,   /*!< GPIO25, input and output */
     GPIO_NUM_26 = 26,   /*!< GPIO26, input and output */
     GPIO_NUM_27 = 27,   /*!< GPIO27, input and output */
     GPIO_NUM_28 = 28,   /*!< GPIO28, input and output */
@@ -342,6 +289,38 @@ typedef enum {
     GPIO_NUM_MAX,
 /** @endcond */
 } gpio_num_t;
+#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
+typedef enum {
+    GPIO_NUM_NC = -1,    /*!< Use to signal not connected to S/W */
+    GPIO_NUM_0 = 0,     /*!< GPIO0, input and output */
+    GPIO_NUM_1 = 1,     /*!< GPIO1, input and output */
+    GPIO_NUM_2 = 2,     /*!< GPIO2, input and output */
+    GPIO_NUM_3 = 3,     /*!< GPIO3, input and output */
+    GPIO_NUM_4 = 4,     /*!< GPIO4, input and output */
+    GPIO_NUM_5 = 5,     /*!< GPIO5, input and output */
+    GPIO_NUM_6 = 6,     /*!< GPIO6, input and output */
+    GPIO_NUM_7 = 7,     /*!< GPIO7, input and output */
+    GPIO_NUM_8 = 8,     /*!< GPIO8, input and output */
+    GPIO_NUM_9 = 9,     /*!< GPIO9, input and output */
+    GPIO_NUM_10 = 10,   /*!< GPIO10, input and output */
+    GPIO_NUM_11 = 11,   /*!< GPIO11, input and output */
+    GPIO_NUM_12 = 12,   /*!< GPIO12, input and output */
+    GPIO_NUM_13 = 13,   /*!< GPIO13, input and output */
+    GPIO_NUM_14 = 14,   /*!< GPIO14, input and output */
+    GPIO_NUM_15 = 15,   /*!< GPIO15, input and output */
+    GPIO_NUM_16 = 16,   /*!< GPIO16, input and output */
+    GPIO_NUM_17 = 17,   /*!< GPIO17, input and output */
+    GPIO_NUM_18 = 18,   /*!< GPIO18, input and output */
+    GPIO_NUM_19 = 19,   /*!< GPIO19, input and output */
+    GPIO_NUM_20 = 20,   /*!< GPIO20, input and output */
+    GPIO_NUM_21 = 21,   /*!< GPIO21, input and output */
+    GPIO_NUM_22 = 22,   /*!< GPIO22, input and output */
+    GPIO_NUM_23 = 23,   /*!< GPIO23, input and output */
+    GPIO_NUM_24 = 24,   /*!< GPIO24, input and output */
+    GPIO_NUM_25 = 25,   /*!< GPIO25, input and output */
+    GPIO_NUM_MAX,
+/** @endcond */
+} gpio_num_t;
 #elif CONFIG_IDF_TARGET_ESP32C2
 typedef enum {
     GPIO_NUM_NC = -1,    /*!< Use to signal not connected to S/W */

components/soc/esp32h2/gpio_periph.c

@@ -6,7 +6,6 @@
 
 #include "soc/gpio_periph.h"
 
-// ESP32H2-TODO: IDF-3439
 const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
     IO_MUX_GPIO0_REG,
     IO_MUX_GPIO1_REG,
@@ -30,29 +29,98 @@ const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
     IO_MUX_GPIO19_REG,
     IO_MUX_GPIO20_REG,
     IO_MUX_GPIO21_REG,
+    IO_MUX_GPIO22_REG,
+    IO_MUX_GPIO23_REG,
+    IO_MUX_GPIO24_REG,
+    IO_MUX_GPIO25_REG,
+#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
+    IO_MUX_GPIO26_REG,
+    IO_MUX_GPIO27_REG,
+    IO_MUX_GPIO28_REG,
+    IO_MUX_GPIO29_REG,
+    IO_MUX_GPIO30_REG,
+    IO_MUX_GPIO31_REG,
+    IO_MUX_GPIO32_REG,
+    IO_MUX_GPIO33_REG,
+    IO_MUX_GPIO34_REG,
+    IO_MUX_GPIO35_REG,
+    IO_MUX_GPIO36_REG,
+    IO_MUX_GPIO37_REG,
+    IO_MUX_GPIO38_REG,
+    IO_MUX_GPIO39_REG,
+    IO_MUX_GPIO40_REG,
+#endif
 };
 
 const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
-    BIT(0),     //GPIO0
+#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
-    BIT(1),     //GPIO1
+    BIT(0),          //GPIO0
-    BIT(2),     //GPIO2
+    BIT(1),          //GPIO1
-    BIT(3),     //GPIO3
+    BIT(2),          //GPIO2
-    BIT(4),     //GPIO4
+    BIT(3),          //GPIO3
-    BIT(5),     //GPIO5
+    BIT(4),          //GPIO4
-    BIT(5),     //GPIO6
+    BIT(5),          //GPIO5
-    BIT(6),     //GPIO7
+    BIT(6),          //GPIO6
-    BIT(3),     //GPIO8
+    BIT(7),          //GPIO7
-    BIT(4),     //GPIO9
+    BIT(8),          //GPIO8
-    BIT(0),     //GPIO10
+    BIT(9),          //GPIO9
-    BIT(15),    //GPIO11
+    BIT(10),         //GPIO10
-    BIT(10),    //GPIO12
+    BIT(11),         //GPIO11
-    BIT(12),    //GPIO13
+    BIT(12),         //GPIO12
-    BIT(8),     //GPIO14
+    BIT(13),         //GPIO13
-    BIT(7),     //GPIO15
+    BIT(14),         //GPIO14
-    BIT(9),     //GPIO16
+    BIT(15),         //GPIO15
-    BIT(11),    //GPIO17
+    BIT(16),         //GPIO16
-    BIT(1),     //GPIO18
+    BIT(17),         //GPIO17
-    BIT(2),     //GPIO19
+    BIT(18),         //GPIO18
-    BIT(13),    //GPIO20
+    BIT(19),         //GPIO19
-    BIT(14),    //GPIO21
+    BIT(20),         //GPIO20
+    BIT(21),         //GPIO21
+    BIT(22),         //GPIO22
+    BIT(23),         //GPIO23
+    BIT(24),         //GPIO24
+    BIT(25),         //GPIO25
+    BIT(26),         //GPIO26
+    BIT(27),         //GPIO27
+    BIT(28),         //GPIO28
+    BIT(29),         //GPIO29
+    BIT(30),         //GPIO30
+    BIT(31),         //GPIO31
+    BIT(0),          //GPIO32
+    BIT(1),          //GPIO33
+    BIT(2),          //GPIO34
+    BIT(3),          //GPIO35
+    BIT(4),          //GPIO36
+    BIT(5),          //GPIO37
+    BIT(6),          //GPIO38
+    BIT(7),          //GPIO39
+    BIT(8),          //GPIO40
+#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
+    BIT(0),          //GPIO0
+    BIT(1),          //GPIO1
+    BIT(2),          //GPIO2
+    BIT(3),          //GPIO3
+    BIT(4),          //GPIO4
+    BIT(5),          //GPIO5
+    BIT(6),          //GPIO6
+    BIT(0),          //GPIO7
+    BIT(1),          //GPIO8
+    BIT(2),          //GPIO9
+    BIT(4),          //GPIO10
+    BIT(3),          //GPIO11
+    BIT(5),          //GPIO12
+    BIT(13),         //GPIO13
+    BIT(14),         //GPIO14
+    BIT(15),         //GPIO15
+    BIT(16),         //GPIO16
+    BIT(17),         //GPIO17
+    BIT(18),         //GPIO18
+    BIT(19),         //GPIO19
+    BIT(20),         //GPIO20
+    BIT(21),         //GPIO21
+    BIT(22),         //GPIO22
+    BIT(23),         //GPIO23
+    BIT(24),         //GPIO24
+    BIT(25),         //GPIO25
+#endif
 };

components/soc/esp32h2/include/rev1/soc/gpio_struct.h

@@ -0,0 +1,609 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configuration register */
+/** Type of bt_select register
+ *  GPIO bit select register
+ */
+typedef union {
+    struct {
+        /** bt_sel : R/W; bitpos: [31:0]; default: 0;
+         *  GPIO bit select register
+         */
+        uint32_t bt_sel:32;
+    };
+    uint32_t val;
+} gpio_bt_select_reg_t;
+
+/** Type of out register
+ *  GPIO output register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** out_data_orig : R/W/WS/WC; bitpos: [31:0]; default: 0;
+         *  GPIO output register for GPIO0-31
+         */
+        uint32_t out_data_orig:32;
+    };
+    uint32_t val;
+} gpio_out_reg_t;
+
+/** Type of out_w1ts register
+ *  GPIO output set register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** out_w1ts : WT; bitpos: [31:0]; default: 0;
+         *  GPIO output set register for GPIO0-31
+         */
+        uint32_t out_w1ts:32;
+    };
+    uint32_t val;
+} gpio_out_w1ts_reg_t;
+
+/** Type of out_w1tc register
+ *  GPIO output clear register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** out_w1tc : WT; bitpos: [31:0]; default: 0;
+         *  GPIO output clear register for GPIO0-31
+         */
+        uint32_t out_w1tc:32;
+    };
+    uint32_t val;
+} gpio_out_w1tc_reg_t;
+
+/** Type of out1 register
+ *  GPIO output register for GPIO32-44
+ */
+typedef union {
+    struct {
+        /** out1_data_orig : R/W/WS/WC; bitpos: [12:0]; default: 0;
+         *  GPIO output register for GPIO32-44
+         */
+        uint32_t out1_data_orig:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} gpio_out1_reg_t;
+
+/** Type of out1_w1ts register
+ *  GPIO output set register for GPIO32-44
+ */
+typedef union {
+    struct {
+        /** out1_w1ts : WT; bitpos: [12:0]; default: 0;
+         *  GPIO output set register for GPIO32-44
+         */
+        uint32_t out1_w1ts:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} gpio_out1_w1ts_reg_t;
+
+/** Type of out1_w1tc register
+ *  GPIO output clear register for GPIO32-44
+ */
+typedef union {
+    struct {
+        /** out1_w1tc : WT; bitpos: [12:0]; default: 0;
+         *  GPIO output clear register for GPIO32-44
+         */
+        uint32_t out1_w1tc:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} gpio_out1_w1tc_reg_t;
+
+/** Type of sdio_select register
+ *  GPIO sdio select register
+ */
+typedef union {
+    struct {
+        /** sdio_sel : R/W; bitpos: [7:0]; default: 0;
+         *  GPIO sdio select register
+         */
+        uint32_t sdio_sel:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_sdio_select_reg_t;
+
+/** Type of enable register
+ *  GPIO output enable register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** enable_data : R/W/SS; bitpos: [31:0]; default: 0;
+         *  GPIO output enable register for GPIO0-31
+         */
+        uint32_t enable_data:32;
+    };
+    uint32_t val;
+} gpio_enable_reg_t;
+
+/** Type of enable_w1ts register
+ *  GPIO output enable set register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** enable_w1ts : WT; bitpos: [31:0]; default: 0;
+         *  GPIO output enable set register for GPIO0-31
+         */
+        uint32_t enable_w1ts:32;
+    };
+    uint32_t val;
+} gpio_enable_w1ts_reg_t;
+
+/** Type of enable_w1tc register
+ *  GPIO output enable clear register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** enable_w1tc : WT; bitpos: [31:0]; default: 0;
+         *  GPIO output enable clear register for GPIO0-31
+         */
+        uint32_t enable_w1tc:32;
+    };
+    uint32_t val;
+} gpio_enable_w1tc_reg_t;
+
+/** Type of enable1 register
+ *  GPIO output enable register for GPIO32-44
+ */
+typedef union {
+    struct {
+        /** enable1_data : R/W/SS; bitpos: [12:0]; default: 0;
+         *  GPIO output enable register for GPIO32-44
+         */
+        uint32_t enable1_data:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} gpio_enable1_reg_t;
+
+/** Type of enable1_w1ts register
+ *  GPIO output enable set register for GPIO32-44
+ */
+typedef union {
+    struct {
+        /** enable1_w1ts : WT; bitpos: [12:0]; default: 0;
+         *  GPIO output enable set register for GPIO32-44
+         */
+        uint32_t enable1_w1ts:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} gpio_enable1_w1ts_reg_t;
+
+/** Type of enable1_w1tc register
+ *  GPIO output enable clear register for GPIO32-44
+ */
+typedef union {
+    struct {
+        /** enable1_w1tc : WT; bitpos: [12:0]; default: 0;
+         *  GPIO output enable clear register for GPIO32-44
+         */
+        uint32_t enable1_w1tc:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} gpio_enable1_w1tc_reg_t;
+
+/** Type of strap register
+ *  pad strapping register
+ */
+typedef union {
+    struct {
+        /** strapping : RO; bitpos: [15:0]; default: 0;
+         *  pad strapping register
+         */
+        uint32_t strapping:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gpio_strap_reg_t;
+
+/** Type of in register
+ *  GPIO input register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** in_data_next : RO; bitpos: [31:0]; default: 0;
+         *  GPIO input register for GPIO0-31
+         */
+        uint32_t in_data_next:32;
+    };
+    uint32_t val;
+} gpio_in_reg_t;
+
+/** Type of in1 register
+ *  GPIO input register for GPIO32-44
+ */
+typedef union {
+    struct {
+        /** in1_data_next : RO; bitpos: [12:0]; default: 0;
+         *  GPIO input register for GPIO32-44
+         */
+        uint32_t in1_data_next:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} gpio_in1_reg_t;
+
+/** Type of status register
+ *  GPIO interrupt status register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** status_interrupt : R/W/SS; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt status register for GPIO0-31
+         */
+        uint32_t status_interrupt:32;
+    };
+    uint32_t val;
+} gpio_status_reg_t;
+
+/** Type of status_w1ts register
+ *  GPIO interrupt status set register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** status_w1ts : WT; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt status set register for GPIO0-31
+         */
+        uint32_t status_w1ts:32;
+    };
+    uint32_t val;
+} gpio_status_w1ts_reg_t;
+
+/** Type of status_w1tc register
+ *  GPIO interrupt status clear register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** status_w1tc : WT; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt status clear register for GPIO0-31
+         */
+        uint32_t status_w1tc:32;
+    };
+    uint32_t val;
+} gpio_status_w1tc_reg_t;
+
+/** Type of status1 register
+ *  GPIO interrupt status register for GPIO32-44
+ */
+typedef union {
+    struct {
+        /** status1_interrupt : R/W/SS; bitpos: [12:0]; default: 0;
+         *  GPIO interrupt status register for GPIO32-44
+         */
+        uint32_t status1_interrupt:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} gpio_status1_reg_t;
+
+/** Type of status1_w1ts register
+ *  GPIO interrupt status set register for GPIO32-44
+ */
+typedef union {
+    struct {
+        /** status1_w1ts : WT; bitpos: [12:0]; default: 0;
+         *  GPIO interrupt status set register for GPIO32-44
+         */
+        uint32_t status1_w1ts:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} gpio_status1_w1ts_reg_t;
+
+/** Type of status1_w1tc register
+ *  GPIO interrupt status clear register for GPIO32-44
+ */
+typedef union {
+    struct {
+        /** status1_w1tc : WT; bitpos: [12:0]; default: 0;
+         *  GPIO interrupt status clear register for GPIO32-44
+         */
+        uint32_t status1_w1tc:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} gpio_status1_w1tc_reg_t;
+
+/** Type of pcpu_int register
+ *  GPIO PRO_CPU interrupt status register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** procpu_int : RO; bitpos: [31:0]; default: 0;
+         *  GPIO PRO_CPU interrupt status register for GPIO0-31
+         */
+        uint32_t procpu_int:32;
+    };
+    uint32_t val;
+} gpio_pcpu_int_reg_t;
+
+/** Type of pcpu_nmi_int register
+ *  GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** procpu_nmi_int : RO; bitpos: [31:0]; default: 0;
+         *  GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31
+         */
+        uint32_t procpu_nmi_int:32;
+    };
+    uint32_t val;
+} gpio_pcpu_nmi_int_reg_t;
+
+/** Type of cpusdio_int register
+ *  GPIO CPUSDIO interrupt status register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** sdio_int : RO; bitpos: [31:0]; default: 0;
+         *  GPIO CPUSDIO interrupt status register for GPIO0-31
+         */
+        uint32_t sdio_int:32;
+    };
+    uint32_t val;
+} gpio_cpusdio_int_reg_t;
+
+/** Type of pcpu_int1 register
+ *  GPIO PRO_CPU interrupt status register for GPIO32-44
+ */
+typedef union {
+    struct {
+        /** procpu_int1 : RO; bitpos: [12:0]; default: 0;
+         *  GPIO PRO_CPU interrupt status register for GPIO32-44
+         */
+        uint32_t procpu_int1:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} gpio_pcpu_int1_reg_t;
+
+/** Type of pcpu_nmi_int1 register
+ *  GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-44
+ */
+typedef union {
+    struct {
+        /** procpu_nmi_int1 : RO; bitpos: [12:0]; default: 0;
+         *  GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-44
+         */
+        uint32_t procpu_nmi_int1:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} gpio_pcpu_nmi_int1_reg_t;
+
+/** Type of cpusdio_int1 register
+ *  GPIO CPUSDIO interrupt status register for GPIO32-44
+ */
+typedef union {
+    struct {
+        /** sdio_int1 : RO; bitpos: [12:0]; default: 0;
+         *  GPIO CPUSDIO interrupt status register for GPIO32-44
+         */
+        uint32_t sdio_int1:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} gpio_cpusdio_int1_reg_t;
+
+/** Type of pin register
+ *  GPIO pin configuration register
+ */
+typedef union {
+    struct {
+        /** pin_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
+         *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+         *  posedge.
+         */
+        uint32_t pin_sync2_bypass:2;
+        /** pin_pad_driver : R/W; bitpos: [2]; default: 0;
+         *  set this bit to select pad driver. 1:open-drain. 0:normal.
+         */
+        uint32_t pin_pad_driver:1;
+        /** pin_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
+         *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+         *  posedge.
+         */
+        uint32_t pin_sync1_bypass:2;
+        uint32_t reserved_5:2;
+        /** pin_int_type : R/W; bitpos: [9:7]; default: 0;
+         *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+         *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+         *  at high level
+         */
+        uint32_t pin_int_type:3;
+        /** pin_wakeup_enable : R/W; bitpos: [10]; default: 0;
+         *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+         */
+        uint32_t pin_wakeup_enable:1;
+        /** pin_config : R/W; bitpos: [12:11]; default: 0;
+         *  reserved
+         */
+        uint32_t pin_config:2;
+        /** pin_int_ena : R/W; bitpos: [17:13]; default: 0;
+         *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+         *  interrupt.
+         */
+        uint32_t pin_int_ena:5;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} gpio_pin_reg_t;
+
+/** Type of status_next register
+ *  GPIO interrupt source register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** status_interrupt_next : RO; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt source register for GPIO0-31
+         */
+        uint32_t status_interrupt_next:32;
+    };
+    uint32_t val;
+} gpio_status_next_reg_t;
+
+/** Type of status_next1 register
+ *  GPIO interrupt source register for GPIO32-44
+ */
+typedef union {
+    struct {
+        /** status_interrupt_next1 : RO; bitpos: [12:0]; default: 0;
+         *  GPIO interrupt source register for GPIO32-44
+         */
+        uint32_t status_interrupt_next1:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} gpio_status_next1_reg_t;
+
+/** Type of func_in_sel_cfg register
+ *  GPIO input function configuration register
+ */
+typedef union {
+    struct {
+        /** func_in_sel : R/W; bitpos: [5:0]; default: 0;
+         *  set this value: s=0-44: connect GPIO[s] to this port. s=0x38: set this port always
+         *  high level. s=0x3C: set this port always low level.
+         */
+        uint32_t func_in_sel:6;
+        /** func_in_inv_sel : R/W; bitpos: [6]; default: 0;
+         *  set this bit to invert input signal. 1:invert. 0:not invert.
+         */
+        uint32_t func_in_inv_sel:1;
+        /** sig_in_sel : R/W; bitpos: [7]; default: 0;
+         *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+         */
+        uint32_t sig_in_sel:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_func_in_sel_cfg_reg_t;
+
+/** Type of func_out_sel_cfg register
+ *  GPIO output function select register
+ */
+typedef union {
+    struct {
+        /** func_out_sel : R/W; bitpos: [7:0]; default: 128;
+         *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127:
+         *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
+         *  GPIO_OUT_REG[n].
+         */
+        uint32_t func_out_sel:8;
+        /** func_out_inv_sel : R/W; bitpos: [8]; default: 0;
+         *  set this bit to invert output signal.1:invert.0:not invert.
+         */
+        uint32_t func_out_inv_sel:1;
+        /** func_oen_sel : R/W; bitpos: [9]; default: 0;
+         *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+         *  enable signal.0:use peripheral output enable signal.
+         */
+        uint32_t func_oen_sel:1;
+        /** func_oen_inv_sel : R/W; bitpos: [10]; default: 0;
+         *  set this bit to invert output enable signal.1:invert.0:not invert.
+         */
+        uint32_t func_oen_inv_sel:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} gpio_func_out_sel_cfg_reg_t;
+
+/** Type of clock_gate register
+ *  GPIO clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  set this bit to enable GPIO clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} gpio_clock_gate_reg_t;
+
+/** Type of reg_date register
+ *  GPIO version register
+ */
+typedef union {
+    struct {
+        /** reg_date : R/W; bitpos: [27:0]; default: 33628944;
+         *  version register
+         */
+        uint32_t reg_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpio_reg_date_reg_t;
+
+
+typedef struct {
+    volatile gpio_bt_select_reg_t bt_select;
+    volatile gpio_out_reg_t out;
+    volatile gpio_out_w1ts_reg_t out_w1ts;
+    volatile gpio_out_w1tc_reg_t out_w1tc;
+    volatile gpio_out1_reg_t out1;
+    volatile gpio_out1_w1ts_reg_t out1_w1ts;
+    volatile gpio_out1_w1tc_reg_t out1_w1tc;
+    volatile gpio_sdio_select_reg_t sdio_select;
+    volatile gpio_enable_reg_t enable;
+    volatile gpio_enable_w1ts_reg_t enable_w1ts;
+    volatile gpio_enable_w1tc_reg_t enable_w1tc;
+    volatile gpio_enable1_reg_t enable1;
+    volatile gpio_enable1_w1ts_reg_t enable1_w1ts;
+    volatile gpio_enable1_w1tc_reg_t enable1_w1tc;
+    volatile gpio_strap_reg_t strap;
+    volatile gpio_in_reg_t in;
+    volatile gpio_in1_reg_t in1;
+    volatile gpio_status_reg_t status;
+    volatile gpio_status_w1ts_reg_t status_w1ts;
+    volatile gpio_status_w1tc_reg_t status_w1tc;
+    volatile gpio_status1_reg_t status1;
+    volatile gpio_status1_w1ts_reg_t status1_w1ts;
+    volatile gpio_status1_w1tc_reg_t status1_w1tc;
+    volatile gpio_pcpu_int_reg_t pcpu_int;
+    volatile gpio_pcpu_nmi_int_reg_t pcpu_nmi_int;
+    volatile gpio_cpusdio_int_reg_t cpusdio_int;
+    volatile gpio_pcpu_int1_reg_t pcpu_int1;
+    volatile gpio_pcpu_nmi_int1_reg_t pcpu_nmi_int1;
+    volatile gpio_cpusdio_int1_reg_t cpusdio_int1;
+    volatile gpio_pin_reg_t pin[45];
+    uint32_t reserved_128[9];
+    volatile gpio_status_next_reg_t status_next;
+    volatile gpio_status_next1_reg_t status_next1;
+    volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[128];
+    uint32_t reserved_354[128];
+    volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[45];
+    uint32_t reserved_608[9];
+    volatile gpio_clock_gate_reg_t clock_gate;
+    uint32_t reserved_630[51];
+    volatile gpio_reg_date_reg_t reg_date;
+} gpio_dev_t;
+
+extern gpio_dev_t GPIO;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(gpio_dev_t) == 0x700, "Invalid size of gpio_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h2/include/rev1/soc/io_mux_reg.h

@@ -86,28 +86,47 @@
 #define PIN_PULLDWN_EN(PIN_NAME)              REG_SET_BIT(PIN_NAME, FUN_PD)
 #define PIN_FUNC_SELECT(PIN_NAME, FUNC)      REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
 
-#define IO_MUX_GPIO0_REG		PERIPHS_IO_MUX_XTAL_32K_P_U
+#define IO_MUX_GPIO0_REG        PERIPHS_IO_MUX_XTAL_32K_P_U
-#define IO_MUX_GPIO1_REG		PERIPHS_IO_MUX_XTAL_32K_N_U
+#define IO_MUX_GPIO1_REG        PERIPHS_IO_MUX_XTAL_32K_N_U
-#define IO_MUX_GPIO2_REG		PERIPHS_IO_MUX_GPIO2_U
+#define IO_MUX_GPIO2_REG        PERIPHS_IO_MUX_GPIO2_U
-#define IO_MUX_GPIO3_REG		PERIPHS_IO_MUX_GPIO3_U
+#define IO_MUX_GPIO3_REG        PERIPHS_IO_MUX_GPIO3_U
-#define IO_MUX_GPIO4_REG		PERIPHS_IO_MUX_MTMS_U
+#define IO_MUX_GPIO4_REG        PERIPHS_IO_MUX_MTMS_U
-#define IO_MUX_GPIO5_REG		PERIPHS_IO_MUX_MTDI_U
+#define IO_MUX_GPIO5_REG        PERIPHS_IO_MUX_MTDI_U
-#define IO_MUX_GPIO6_REG		PERIPHS_IO_MUX_MTCK_U
+#define IO_MUX_GPIO6_REG        PERIPHS_IO_MUX_MTCK_U
-#define IO_MUX_GPIO7_REG		PERIPHS_IO_MUX_MTDO_U
+#define IO_MUX_GPIO7_REG        PERIPHS_IO_MUX_MTDO_U
-#define IO_MUX_GPIO8_REG		PERIPHS_IO_MUX_GPIO8_U
+#define IO_MUX_GPIO8_REG        PERIPHS_IO_MUX_GPIO8_U
-#define IO_MUX_GPIO9_REG		PERIPHS_IO_MUX_GPIO9_U
+#define IO_MUX_GPIO9_REG        PERIPHS_IO_MUX_GPIO9_U
-#define IO_MUX_GPIO10_REG	PERIPHS_IO_MUX_GPIO10_U
+#define IO_MUX_GPIO10_REG       PERIPHS_IO_MUX_GPIO10_U
-#define IO_MUX_GPIO11_REG	PERIPHS_IO_MUX_VDD_SPI_U
+#define IO_MUX_GPIO11_REG       PERIPHS_IO_MUX_VDD_SPI_U
-#define IO_MUX_GPIO12_REG	PERIPHS_IO_MUX_SPIHD_U
+#define IO_MUX_GPIO12_REG       PERIPHS_IO_MUX_SPIHD_U
-#define IO_MUX_GPIO13_REG	PERIPHS_IO_MUX_SPIWP_U
+#define IO_MUX_GPIO13_REG       PERIPHS_IO_MUX_SPIWP_U
-#define IO_MUX_GPIO14_REG	PERIPHS_IO_MUX_SPICS0_U
+#define IO_MUX_GPIO14_REG       PERIPHS_IO_MUX_SPICS0_U
-#define IO_MUX_GPIO15_REG	PERIPHS_IO_MUX_SPICLK_U
+#define IO_MUX_GPIO15_REG       PERIPHS_IO_MUX_SPICLK_U
-#define IO_MUX_GPIO16_REG	PERIPHS_IO_MUX_SPID_U
+#define IO_MUX_GPIO16_REG       PERIPHS_IO_MUX_SPID_U
-#define IO_MUX_GPIO17_REG	PERIPHS_IO_MUX_SPIQ_U
+#define IO_MUX_GPIO17_REG       PERIPHS_IO_MUX_SPIQ_U
-#define IO_MUX_GPIO18_REG	PERIPHS_IO_MUX_GPIO18_U
+#define IO_MUX_GPIO18_REG       PERIPHS_IO_MUX_GPIO18_U
-#define IO_MUX_GPIO19_REG	PERIPHS_IO_MUX_GPIO19_U
+#define IO_MUX_GPIO19_REG       PERIPHS_IO_MUX_GPIO19_U
-#define IO_MUX_GPIO20_REG	PERIPHS_IO_MUX_U0RXD_U
+#define IO_MUX_GPIO20_REG       PERIPHS_IO_MUX_U0RXD_U
-#define IO_MUX_GPIO21_REG	PERIPHS_IO_MUX_U0TXD_U
+#define IO_MUX_GPIO21_REG       PERIPHS_IO_MUX_U0TXD_U
+#define IO_MUX_GPIO22_REG       PERIPHS_IO_MUX_GPIO22_U
+#define IO_MUX_GPIO23_REG       PERIPHS_IO_MUX_GPIO23_U
+#define IO_MUX_GPIO24_REG       PERIPHS_IO_MUX_GPIO24_U
+#define IO_MUX_GPIO25_REG       PERIPHS_IO_MUX_GPIO25_U
+#define IO_MUX_GPIO26_REG       PERIPHS_IO_MUX_GPIO26_U
+#define IO_MUX_GPIO27_REG       PERIPHS_IO_MUX_GPIO27_U
+#define IO_MUX_GPIO28_REG       PERIPHS_IO_MUX_GPIO28_U
+#define IO_MUX_GPIO29_REG       PERIPHS_IO_MUX_GPIO29_U
+#define IO_MUX_GPIO30_REG       PERIPHS_IO_MUX_GPIO30_U
+#define IO_MUX_GPIO31_REG       PERIPHS_IO_MUX_GPIO31_U
+#define IO_MUX_GPIO32_REG       PERIPHS_IO_MUX_GPIO32_U
+#define IO_MUX_GPIO33_REG       PERIPHS_IO_MUX_GPIO33_U
+#define IO_MUX_GPIO34_REG       PERIPHS_IO_MUX_GPIO34_U
+#define IO_MUX_GPIO35_REG       PERIPHS_IO_MUX_GPIO35_U
+#define IO_MUX_GPIO36_REG       PERIPHS_IO_MUX_GPIO36_U
+#define IO_MUX_GPIO37_REG       PERIPHS_IO_MUX_GPIO37_U
+#define IO_MUX_GPIO38_REG       PERIPHS_IO_MUX_GPIO38_U
+#define IO_MUX_GPIO39_REG       PERIPHS_IO_MUX_GPIO39_U
+#define IO_MUX_GPIO40_REG       PERIPHS_IO_MUX_GPIO40_U
 
 /* Value to set in IO Mux to use a pin as GPIO. */
 #define PIN_FUNC_GPIO								1
@@ -130,9 +149,9 @@
 #define SD_DATA2_GPIO_NUM 9
 #define SD_DATA3_GPIO_NUM 10
 
-#define MAX_RTC_GPIO_NUM 0
+#define MAX_RTC_GPIO_NUM 5
-#define MAX_PAD_GPIO_NUM 22
+#define MAX_PAD_GPIO_NUM 40
-#define MAX_GPIO_NUM    22
+#define MAX_GPIO_NUM    44
 
 #define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
 #define PIN_CTRL                          (REG_IO_MUX_BASE +0x00)
@@ -255,9 +274,93 @@
 #define FUNC_U0TXD_GPIO21                           1
 #define FUNC_U0TXD_U0TXD                            0
 
-#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
+#define PERIPHS_IO_MUX_GPIO22_U           (REG_IO_MUX_BASE +0x5c)
-#define IO_MUX_DATE 0xFFFFFFFF
+#define FUNC_GPIO22_GPIO22                          1
-#define IO_MUX_DATE_S 0
+#define FUNC_GPIO22_GPIO22_0                        0
-#define IO_MUX_DATE_VERSION 0x2006050
+
+#define PERIPHS_IO_MUX_GPIO23_U           (REG_IO_MUX_BASE +0x60)
+#define FUNC_GPIO23_GPIO23                          1
+#define FUNC_GPIO23_GPIO23_0                        0
+
+#define PERIPHS_IO_MUX_GPIO24_U           (REG_IO_MUX_BASE +0x64)
+#define FUNC_GPIO24_GPIO24                          1
+#define FUNC_GPIO24_GPIO24_0                        0
+
+#define PERIPHS_IO_MUX_GPIO25_U           (REG_IO_MUX_BASE +0x68)
+#define FUNC_GPIO25_GPIO25                          1
+#define FUNC_GPIO25_GPIO25_0                        0
+
+#define PERIPHS_IO_MUX_GPIO26_U           (REG_IO_MUX_BASE +0x6c)
+#define FUNC_GPIO26_GPIO26                          1
+#define FUNC_GPIO26_GPIO26_0                        0
+
+#define PERIPHS_IO_MUX_GPIO27_U           (REG_IO_MUX_BASE +0x70)
+#define FUNC_GPIO27_GPIO27                          1
+#define FUNC_GPIO27_GPIO27_0                        0
+
+#define PERIPHS_IO_MUX_GPIO28_U           (REG_IO_MUX_BASE +0x74)
+#define FUNC_GPIO28_GPIO28                          1
+#define FUNC_GPIO28_GPIO28_0                        0
+
+#define PERIPHS_IO_MUX_GPIO29_U           (REG_IO_MUX_BASE +0x78)
+#define FUNC_GPIO29_GPIO29                          1
+#define FUNC_GPIO29_GPIO29_0                        0
+
+#define PERIPHS_IO_MUX_GPIO30_U           (REG_IO_MUX_BASE +0x7c)
+#define FUNC_GPIO30_GPIO30                          1
+#define FUNC_GPIO30_GPIO30_0                        0
+
+#define PERIPHS_IO_MUX_GPIO31_U           (REG_IO_MUX_BASE +0x80)
+#define FUNC_GPIO31_GPIO31                          1
+#define FUNC_GPIO31_GPIO31_0                        0
+
+#define PERIPHS_IO_MUX_GPIO32_U           (REG_IO_MUX_BASE +0x84)
+#define FUNC_GPIO32_GPIO32                          1
+#define FUNC_GPIO32_GPIO32_0                        0
+
+#define PERIPHS_IO_MUX_GPIO33_U           (REG_IO_MUX_BASE +0x88)
+#define FUNC_GPIO33_GPIO33                          1
+#define FUNC_GPIO33_GPIO33_0                        0
+
+#define PERIPHS_IO_MUX_GPIO34_U           (REG_IO_MUX_BASE +0x8c)
+#define FUNC_GPIO34_GPIO34                          1
+#define FUNC_GPIO34_GPIO34_0                        0
+
+#define PERIPHS_IO_MUX_GPIO35_U           (REG_IO_MUX_BASE +0x90)
+#define FUNC_GPIO35_GPIO35                          1
+#define FUNC_GPIO35_GPIO35_0                        0
+
+#define PERIPHS_IO_MUX_GPIO36_U           (REG_IO_MUX_BASE +0x94)
+#define FUNC_GPIO36_GPIO36                          1
+#define FUNC_GPIO36_GPIO36_0                        0
+
+#define PERIPHS_IO_MUX_GPIO37_U           (REG_IO_MUX_BASE +0x98)
+#define FUNC_GPIO37_GPIO37                          1
+#define FUNC_GPIO37_GPIO37_0                        0
+
+#define PERIPHS_IO_MUX_GPIO38_U           (REG_IO_MUX_BASE +0x9c)
+#define FUNC_GPIO38_GPIO38                          1
+#define FUNC_GPIO38_GPIO38_0                        0
+
+#define PERIPHS_IO_MUX_GPIO39_U           (REG_IO_MUX_BASE +0xa0)
+#define FUNC_GPIO39_GPIO39                          1
+#define FUNC_GPIO39_GPIO39_0                        0
+
+#define PERIPHS_IO_MUX_GPIO40_U           (REG_IO_MUX_BASE +0xa4)
+#define FUNC_GPIO40_GPIO40                          1
+#define FUNC_GPIO40_GPIO40_0                        0
+
+/** IO_MUX_DATE_REG register
+ *  IO MUX Version Control Register
+ */
+#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0xfc)
+/** IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 33628944;
+ *  Version control register
+ */
+#define IO_MUX_REG_DATE    0x0FFFFFFFU
+#define IO_MUX_REG_DATE_M  (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S)
+#define IO_MUX_REG_DATE_V  0x0FFFFFFFU
+#define IO_MUX_REG_DATE_S  0
+#define IO_MUX_DATE_VERSION 0x2012310
 
 #endif

components/soc/esp32h2/include/rev1/soc/usb_serial_jtag_reg.h

@@ -18,7 +18,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_EP1_REG register
  *  USB_SERIAL_JTAG_EP1_REG.
  */
-#define USB_SERIAL_JTAG_EP1_REG (SOC_DPORT_USB_BASE + 0x0)
+#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
 /* USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [8:0]; default: 0;
  * Write and read byte data to/from UART Tx/Rx FIFO through this field.
  * When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set  then user can write
@@ -37,7 +37,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_CONF0_REG register
  *  USB_SERIAL_JTAG_CONF0_REG.
  */
-#define USB_SERIAL_JTAG_CONF0_REG (SOC_DPORT_USB_BASE + 0x18)
+#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
 /* USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
  * Select internal/external PHY. 1’b0: internal PHY, 1’b1: external
  * PHY
@@ -146,7 +146,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_TEST_REG register
  *  USB_SERIAL_JTAG_TEST_REG.
  */
-#define USB_SERIAL_JTAG_TEST_REG (SOC_DPORT_USB_BASE + 0x1c)
+#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
 /* USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
  * Enable test of the USB
  * pad
@@ -183,7 +183,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_MISC_CONF_REG register
  *  USB_SERIAL_JTAG_MISC_CONF_REG.
  */
-#define USB_SERIAL_JTAG_MISC_CONF_REG (SOC_DPORT_USB_BASE + 0x44)
+#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
 /* USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
  * 1'h1: Force clock on for register. 1'h0: Support clock only when
  * application writes
@@ -197,7 +197,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_MEM_CONF_REG register
  *  USB_SERIAL_JTAG_MEM_CONF_REG.
  */
-#define USB_SERIAL_JTAG_MEM_CONF_REG (SOC_DPORT_USB_BASE + 0x48)
+#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
 /* USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
  * 1: power down usb
  * memory.
@@ -221,7 +221,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_EP1_CONF_REG register
  *  USB_SERIAL_JTAG_EP1_CONF_REG.
  */
-#define USB_SERIAL_JTAG_EP1_CONF_REG (SOC_DPORT_USB_BASE + 0x4)
+#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
 /* USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
  * Set this bit to indicate writing byte data to UART Tx FIFO is done.
  * This bit then stays 0 until data in UART Tx FIFO is read by the USB
@@ -253,7 +253,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_JFIFO_ST_REG register
  *  USB_SERIAL_JTAG_JFIFO_ST_REG.
  */
-#define USB_SERIAL_JTAG_JFIFO_ST_REG (SOC_DPORT_USB_BASE + 0x20)
+#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
 /* USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [2:0]; default: 0;
  * JTAG in fifo
  * counter.
@@ -322,7 +322,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_FRAM_NUM_REG register
  *  USB_SERIAL_JTAG_FRAM_NUM_REG.
  */
-#define USB_SERIAL_JTAG_FRAM_NUM_REG (SOC_DPORT_USB_BASE + 0x24)
+#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
 /* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [11:0]; default: 0;
  * Frame index of received SOF
  * frame.
@@ -335,7 +335,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_IN_EP0_ST_REG register
  *  USB_SERIAL_JTAG_IN_EP0_ST_REG.
  */
-#define USB_SERIAL_JTAG_IN_EP0_ST_REG (SOC_DPORT_USB_BASE + 0x28)
+#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
 /* USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [2:0]; default: 1;
  * State of IN Endpoint
  * 0.
@@ -364,7 +364,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_IN_EP1_ST_REG register
  *  USB_SERIAL_JTAG_IN_EP1_ST_REG.
  */
-#define USB_SERIAL_JTAG_IN_EP1_ST_REG (SOC_DPORT_USB_BASE + 0x2c)
+#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
 /* USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [2:0]; default: 1;
  * State of IN Endpoint
  * 1.
@@ -393,7 +393,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_IN_EP2_ST_REG register
  *  USB_SERIAL_JTAG_IN_EP2_ST_REG.
  */
-#define USB_SERIAL_JTAG_IN_EP2_ST_REG (SOC_DPORT_USB_BASE + 0x30)
+#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
 /* USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [2:0]; default: 1;
  * State of IN Endpoint
  * 2.
@@ -422,7 +422,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_IN_EP3_ST_REG register
  *  USB_SERIAL_JTAG_IN_EP3_ST_REG.
  */
-#define USB_SERIAL_JTAG_IN_EP3_ST_REG (SOC_DPORT_USB_BASE + 0x34)
+#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
 /* USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [2:0]; default: 1;
  * State of IN Endpoint
  * 3.
@@ -451,7 +451,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
  *  USB_SERIAL_JTAG_OUT_EP0_ST_REG.
  */
-#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (SOC_DPORT_USB_BASE + 0x38)
+#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
 /* USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [2:0]; default: 0;
  * State of OUT Endpoint
  * 0.
@@ -482,7 +482,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
  *  USB_SERIAL_JTAG_OUT_EP1_ST_REG.
  */
-#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (SOC_DPORT_USB_BASE + 0x3c)
+#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
 /* USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [2:0]; default: 0;
  * State of OUT Endpoint
  * 1.
@@ -521,7 +521,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
  *  USB_SERIAL_JTAG_OUT_EP2_ST_REG.
  */
-#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (SOC_DPORT_USB_BASE + 0x40)
+#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
 /* USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [2:0]; default: 0;
  * State of OUT Endpoint
  * 2.
@@ -555,7 +555,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_INT_RAW_REG register
  *  USB_SERIAL_JTAG_INT_RAW_REG.
  */
-#define USB_SERIAL_JTAG_INT_RAW_REG (SOC_DPORT_USB_BASE + 0x8)
+#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
 /* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
  * The raw interrupt bit turns to high level when a flush command is
  * received for IN endpoint 2 of
@@ -662,7 +662,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_INT_ST_REG register
  *  USB_SERIAL_JTAG_INT_ST_REG.
  */
-#define USB_SERIAL_JTAG_INT_ST_REG (SOC_DPORT_USB_BASE + 0xc)
+#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
 /* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
  * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
  * interrupt.
@@ -768,7 +768,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_INT_ENA_REG register
  *  USB_SERIAL_JTAG_INT_ENA_REG.
  */
-#define USB_SERIAL_JTAG_INT_ENA_REG (SOC_DPORT_USB_BASE + 0x10)
+#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
 /* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
  * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
  * interrupt.
@@ -873,7 +873,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_INT_CLR_REG register
  *  USB_SERIAL_JTAG_INT_CLR_REG.
  */
-#define USB_SERIAL_JTAG_INT_CLR_REG (SOC_DPORT_USB_BASE + 0x14)
+#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
 /* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
  * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
  * interrupt.
@@ -977,7 +977,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_DATE_REG register
  *  USB_SERIAL_JTAG_DATE_REG.
  */
-#define USB_SERIAL_JTAG_DATE_REG (SOC_DPORT_USB_BASE + 0x80)
+#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
 /* USB_SERIAL_JTAG_DATE : R/W; bitpos: [32:0]; default: 33583872;
  * register
  * version.

components/soc/esp32h2/include/rev2/soc/gpio_struct.h

@@ -0,0 +1,420 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configuration register */
+/** Type of bt_select register
+ *  GPIO bit select register
+ */
+typedef union {
+    struct {
+        /** bt_sel : R/W; bitpos: [31:0]; default: 0;
+         *  GPIO bit select register
+         */
+        uint32_t bt_sel:32;
+    };
+    uint32_t val;
+} gpio_bt_select_reg_t;
+
+/** Type of out register
+ *  GPIO output register for GPIO0-29
+ */
+typedef union {
+    struct {
+        /** out_data_orig : R/W/WS/WC; bitpos: [29:0]; default: 0;
+         *  GPIO output register for GPIO0-29
+         */
+        uint32_t out_data_orig:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_out_reg_t;
+
+/** Type of out_w1ts register
+ *  GPIO output set register for GPIO0-29
+ */
+typedef union {
+    struct {
+        /** out_w1ts : WT; bitpos: [29:0]; default: 0;
+         *  GPIO output set register for GPIO0-29
+         */
+        uint32_t out_w1ts:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_out_w1ts_reg_t;
+
+/** Type of out_w1tc register
+ *  GPIO output clear register for GPIO0-29
+ */
+typedef union {
+    struct {
+        /** out_w1tc : WT; bitpos: [29:0]; default: 0;
+         *  GPIO output clear register for GPIO0-29
+         */
+        uint32_t out_w1tc:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_out_w1tc_reg_t;
+
+/** Type of sdio_select register
+ *  GPIO sdio select register
+ */
+typedef union {
+    struct {
+        /** sdio_sel : R/W; bitpos: [7:0]; default: 0;
+         *  GPIO sdio select register
+         */
+        uint32_t sdio_sel:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_sdio_select_reg_t;
+
+/** Type of enable register
+ *  GPIO output enable register for GPIO0-29
+ */
+typedef union {
+    struct {
+        /** enable_data : R/W/SS; bitpos: [29:0]; default: 0;
+         *  GPIO output enable register for GPIO0-29
+         */
+        uint32_t enable_data:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_enable_reg_t;
+
+/** Type of enable_w1ts register
+ *  GPIO output enable set register for GPIO0-29
+ */
+typedef union {
+    struct {
+        /** enable_w1ts : WT; bitpos: [29:0]; default: 0;
+         *  GPIO output enable set register for GPIO0-29
+         */
+        uint32_t enable_w1ts:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_enable_w1ts_reg_t;
+
+/** Type of enable_w1tc register
+ *  GPIO output enable clear register for GPIO0-29
+ */
+typedef union {
+    struct {
+        /** enable_w1tc : WT; bitpos: [29:0]; default: 0;
+         *  GPIO output enable clear register for GPIO0-29
+         */
+        uint32_t enable_w1tc:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_enable_w1tc_reg_t;
+
+/** Type of strap register
+ *  pad strapping register
+ */
+typedef union {
+    struct {
+        /** strapping : RO; bitpos: [15:0]; default: 0;
+         *  pad strapping register
+         */
+        uint32_t strapping:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gpio_strap_reg_t;
+
+/** Type of in register
+ *  GPIO input register for GPIO0-29
+ */
+typedef union {
+    struct {
+        /** in_data_next : RO; bitpos: [29:0]; default: 0;
+         *  GPIO input register for GPIO0-29
+         */
+        uint32_t in_data_next:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_in_reg_t;
+
+/** Type of status register
+ *  GPIO interrupt status register for GPIO0-29
+ */
+typedef union {
+    struct {
+        /** status_interrupt : R/W/SS; bitpos: [29:0]; default: 0;
+         *  GPIO interrupt status register for GPIO0-29
+         */
+        uint32_t status_interrupt:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_status_reg_t;
+
+/** Type of status_w1ts register
+ *  GPIO interrupt status set register for GPIO0-29
+ */
+typedef union {
+    struct {
+        /** status_w1ts : WT; bitpos: [29:0]; default: 0;
+         *  GPIO interrupt status set register for GPIO0-29
+         */
+        uint32_t status_w1ts:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_status_w1ts_reg_t;
+
+/** Type of status_w1tc register
+ *  GPIO interrupt status clear register for GPIO0-29
+ */
+typedef union {
+    struct {
+        /** status_w1tc : WT; bitpos: [29:0]; default: 0;
+         *  GPIO interrupt status clear register for GPIO0-29
+         */
+        uint32_t status_w1tc:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_status_w1tc_reg_t;
+
+/** Type of pin register
+ *  GPIO pin configuration register
+ */
+typedef union {
+    struct {
+        /** pin_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
+         *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+         *  posedge.
+         */
+        uint32_t pin_sync2_bypass:2;
+        /** pin_pad_driver : R/W; bitpos: [2]; default: 0;
+         *  set this bit to select pad driver. 1:open-drain. 0:normal.
+         */
+        uint32_t pin_pad_driver:1;
+        /** pin_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
+         *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+         *  posedge.
+         */
+        uint32_t pin_sync1_bypass:2;
+        uint32_t reserved_5:2;
+        /** pin_int_type : R/W; bitpos: [9:7]; default: 0;
+         *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+         *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+         *  at high level
+         */
+        uint32_t pin_int_type:3;
+        /** pin_wakeup_enable : R/W; bitpos: [10]; default: 0;
+         *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+         */
+        uint32_t pin_wakeup_enable:1;
+        /** pin_config : R/W; bitpos: [12:11]; default: 0;
+         *  reserved
+         */
+        uint32_t pin_config:2;
+        /** pin_int_ena : R/W; bitpos: [17:13]; default: 0;
+         *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+         *  interrupt.
+         */
+        uint32_t pin_int_ena:5;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} gpio_pin_reg_t;
+
+/** Type of status_next register
+ *  GPIO interrupt source register for GPIO0-29
+ */
+typedef union {
+    struct {
+        /** status_interrupt_next : RO; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt source register for GPIO0-29
+         */
+        uint32_t status_interrupt_next:32;
+    };
+    uint32_t val;
+} gpio_status_next_reg_t;
+
+/** Type of func_in_sel_cfg register
+ *  GPIO input function configuration register
+ */
+typedef union {
+    struct {
+        /** func_in_sel : R/W; bitpos: [4:0]; default: 0;
+         *  set this value: s=0-29: connect GPIO[s] to this port. s=0x38: set this port always
+         *  high level. s=0x3C: set this port always low level.
+         */
+        uint32_t func_in_sel:5;
+        /** func_in_inv_sel : R/W; bitpos: [5]; default: 0;
+         *  set this bit to invert input signal. 1:invert. 0:not invert.
+         */
+        uint32_t func_in_inv_sel:1;
+        /** sig_in_sel : R/W; bitpos: [6]; default: 0;
+         *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+         */
+        uint32_t sig_in_sel:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} gpio_func_in_sel_cfg_reg_t;
+
+/** Type of func_out_sel_cfg register
+ *  GPIO output function select register
+ */
+typedef union {
+    struct {
+        /** func_out_sel : R/W; bitpos: [7:0]; default: 128;
+         *  The value of the bits: 0<=s<=128. Set the value to select output signal. s=0-127:
+         *  output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals
+         *  GPIO_OUT_REG[n].
+         */
+        uint32_t func_out_sel:8;
+        /** func_out_inv_sel : R/W; bitpos: [8]; default: 0;
+         *  set this bit to invert output signal.1:invert.0:not invert.
+         */
+        uint32_t func_out_inv_sel:1;
+        /** func_oen_sel : R/W; bitpos: [9]; default: 0;
+         *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+         *  enable signal.0:use peripheral output enable signal.
+         */
+        uint32_t func_oen_sel:1;
+        /** func_oen_inv_sel : R/W; bitpos: [10]; default: 0;
+         *  set this bit to invert output enable signal.1:invert.0:not invert.
+         */
+        uint32_t func_oen_inv_sel:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} gpio_func_out_sel_cfg_reg_t;
+
+/** Type of clock_gate register
+ *  GPIO clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  set this bit to enable GPIO clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} gpio_clock_gate_reg_t;
+
+/** Type of reg_date register
+ *  GPIO version register
+ */
+typedef union {
+    struct {
+        /** reg_date : R/W; bitpos: [27:0]; default: 34640016;
+         *  version register
+         */
+        uint32_t reg_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpio_reg_date_reg_t;
+
+
+/** Group: interrupt register */
+/** Type of pcpu_int register
+ *  GPIO PRO_CPU interrupt status register for GPIO0-29
+ */
+typedef union {
+    struct {
+        /** procpu_int : RO; bitpos: [29:0]; default: 0;
+         *  GPIO PRO_CPU interrupt status register for GPIO0-29
+         */
+        uint32_t procpu_int:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_pcpu_int_reg_t;
+
+/** Type of pcpu_nmi_int register
+ *  GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-29
+ */
+typedef union {
+    struct {
+        /** procpu_nmi_int : RO; bitpos: [29:0]; default: 0;
+         *  GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-29
+         */
+        uint32_t procpu_nmi_int:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_pcpu_nmi_int_reg_t;
+
+/** Type of cpusdio_int register
+ *  GPIO CPUSDIO interrupt status register for GPIO0-29
+ */
+typedef union {
+    struct {
+        /** sdio_int : RO; bitpos: [29:0]; default: 0;
+         *  GPIO CPUSDIO interrupt status register for GPIO0-29
+         */
+        uint32_t sdio_int:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_cpusdio_int_reg_t;
+
+
+typedef struct {
+    volatile gpio_bt_select_reg_t bt_select;
+    volatile gpio_out_reg_t out;
+    volatile gpio_out_w1ts_reg_t out_w1ts;
+    volatile gpio_out_w1tc_reg_t out_w1tc;
+    uint32_t reserved_010[3];
+    volatile gpio_sdio_select_reg_t sdio_select;
+    volatile gpio_enable_reg_t enable;
+    volatile gpio_enable_w1ts_reg_t enable_w1ts;
+    volatile gpio_enable_w1tc_reg_t enable_w1tc;
+    uint32_t reserved_02c[3];
+    volatile gpio_strap_reg_t strap;
+    volatile gpio_in_reg_t in;
+    uint32_t reserved_040;
+    volatile gpio_status_reg_t status;
+    volatile gpio_status_w1ts_reg_t status_w1ts;
+    volatile gpio_status_w1tc_reg_t status_w1tc;
+    uint32_t reserved_050[3];
+    volatile gpio_pcpu_int_reg_t pcpu_int;
+    volatile gpio_pcpu_nmi_int_reg_t pcpu_nmi_int;
+    volatile gpio_cpusdio_int_reg_t cpusdio_int;
+    uint32_t reserved_068[3];
+    volatile gpio_pin_reg_t pin[30];
+    uint32_t reserved_0ec[24];
+    volatile gpio_status_next_reg_t status_next;
+    uint32_t reserved_150;
+    volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[128];
+    uint32_t reserved_354[128];
+    volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[30];
+    uint32_t reserved_5cc[24];
+    volatile gpio_clock_gate_reg_t clock_gate;
+    uint32_t reserved_630[51];
+    volatile gpio_reg_date_reg_t reg_date;
+} gpio_dev_t;
+
+extern gpio_dev_t GPIO;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(gpio_dev_t) == 0x700, "Invalid size of gpio_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h2/include/rev2/soc/io_mux_reg.h

@@ -4,6 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 #pragma once
+
 #include "soc/soc.h"
 
 /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
@@ -110,7 +111,6 @@
 #define IO_MUX_GPIO24_REG              PERIPHS_IO_MUX_GPIO24_U
 #define IO_MUX_GPIO25_REG              PERIPHS_IO_MUX_GPIO25_U
 
-#define FUNC_GPIO_GPIO                              1
 #define PIN_FUNC_GPIO								1
 
 #define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
@@ -124,9 +124,9 @@
 #define SPI_D_GPIO_NUM               18
 #define SPI_Q_GPIO_NUM               14
 
-#define MAX_RTC_GPIO_NUM              5
+#define MAX_RTC_GPIO_NUM             12            // GPIO7~12 are the rtc_io pads
-#define MAX_PAD_GPIO_NUM             20
+#define MAX_PAD_GPIO_NUM             25
-#define MAX_GPIO_NUM                 24
+#define MAX_GPIO_NUM                 29
 #define DIG_IO_HOLD_BIT_SHIFT         0
 
 

components/soc/esp32h2/include/rev2/soc/usb_serial_jtag_reg.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -14,7 +14,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_EP1_REG register
  *  FIFO access for the CDC-ACM data IN and OUT endpoints.
  */
-#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x0)
+#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
 /** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0;
  *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
  *  USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
@@ -30,7 +30,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_EP1_CONF_REG register
  *  Configuration and control registers for the CDC-ACM FIFOs.
  */
-#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x4)
+#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
 /** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
  *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
  */
@@ -58,7 +58,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_INT_RAW_REG register
  *  Interrupt raw status register.
  */
-#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x8)
+#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
 /** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
  *  The raw interrupt bit turns to high level when flush cmd is received for IN
  *  endpoint 2 of JTAG.
@@ -152,7 +152,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_INT_ST_REG register
  *  Interrupt status register.
  */
-#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0xc)
+#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
 /** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
  *  The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
  */
@@ -245,7 +245,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_INT_ENA_REG register
  *  Interrupt enable status register.
  */
-#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x10)
+#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
 /** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
  *  The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
  */
@@ -334,7 +334,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_INT_CLR_REG register
  *  Interrupt clear status register.
  */
-#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_DEVICE_BASE + 0x14)
+#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
 /** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
  *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
  */
@@ -423,7 +423,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_CONF0_REG register
  *  PHY hardware configuration.
  */
-#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_DEVICE_BASE + 0x18)
+#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
 /** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
  *  Select internal/external PHY
  */
@@ -534,7 +534,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_TEST_REG register
  *  Registers used for debugging the PHY.
  */
-#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x1c)
+#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
 /** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
  *  Enable test of the USB pad
  */
@@ -588,7 +588,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_JFIFO_ST_REG register
  *  JTAG FIFO status and control registers.
  */
-#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x20)
+#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
 /** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0;
  *  JTAT in fifo counter.
  */
@@ -649,7 +649,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_FRAM_NUM_REG register
  *  Last received SOF frame index register.
  */
-#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x24)
+#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
 /** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0;
  *  Frame index of received SOF frame.
  */
@@ -661,7 +661,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_IN_EP0_ST_REG register
  *  Control IN endpoint status information.
  */
-#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x28)
+#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
 /** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1;
  *  State of IN Endpoint 0.
  */
@@ -687,7 +687,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_IN_EP1_ST_REG register
  *  CDC-ACM IN endpoint status information.
  */
-#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x2c)
+#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
 /** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1;
  *  State of IN Endpoint 1.
  */
@@ -713,7 +713,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_IN_EP2_ST_REG register
  *  CDC-ACM interrupt IN endpoint status information.
  */
-#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x30)
+#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
 /** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1;
  *  State of IN Endpoint 2.
  */
@@ -739,7 +739,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_IN_EP3_ST_REG register
  *  JTAG IN endpoint status information.
  */
-#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x34)
+#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
 /** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1;
  *  State of IN Endpoint 3.
  */
@@ -765,7 +765,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
  *  Control OUT endpoint status information.
  */
-#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x38)
+#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
 /** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0;
  *  State of OUT Endpoint 0.
  */
@@ -792,7 +792,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
  *  CDC-ACM OUT endpoint status information.
  */
-#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x3c)
+#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
 /** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0;
  *  State of OUT Endpoint 1.
  */
@@ -826,7 +826,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
  *  JTAG OUT endpoint status information.
  */
-#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x40)
+#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
 /** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0;
  *  State of OUT Endpoint 2.
  */
@@ -853,7 +853,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_MISC_CONF_REG register
  *  Clock enable control
  */
-#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x44)
+#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
 /** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
  *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
  *  registers.
@@ -866,7 +866,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_MEM_CONF_REG register
  *  Memory power control
  */
-#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x48)
+#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
 /** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
  *  1: power down usb memory.
  */
@@ -885,7 +885,7 @@ extern "C" {
 /** USB_SERIAL_JTAG_DATE_REG register
  *  Date register
  */
-#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_DEVICE_BASE + 0x80)
+#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
 /** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34607505;
  *  register version.
  */

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -213,7 +213,7 @@ config SOC_GPIO_PORT
 
 config SOC_GPIO_PIN_COUNT
     int
-    default 22
+    default 41
 
 config SOC_GPIO_SUPPORTS_RTC_INDEPENDENT
     bool

components/soc/esp32h2/include/soc/gpio_struct.h

@@ -1,437 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_GPIO_STRUCT_H_
-#define _SOC_GPIO_STRUCT_H_
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct gpio_dev_s {
-    uint32_t bt_select;                               /**/
-    union {
-        struct {
-            uint32_t data:         26;
-            uint32_t reserved26:    6;
-        };
-        uint32_t val;
-    } out;
-    union {
-        struct {
-            uint32_t out_w1ts:  26;
-            uint32_t reserved26: 6;
-        };
-        uint32_t val;
-    } out_w1ts;
-    union {
-        struct {
-            uint32_t out_w1tc:  26;
-            uint32_t reserved26: 6;
-        };
-        uint32_t val;
-    } out_w1tc;
-    uint32_t reserved_10;
-    uint32_t reserved_14;
-    uint32_t reserved_18;
-    union {
-        struct {
-            uint32_t sel:        8;
-            uint32_t reserved8: 24;
-        };
-        uint32_t val;
-    } sdio_select;
-    union {
-        struct {
-            uint32_t data:       26;
-            uint32_t reserved26:  6;
-        };
-        uint32_t val;
-    } enable;
-    union {
-        struct {
-            uint32_t enable_w1ts:26;
-            uint32_t reserved26:  6;
-        };
-        uint32_t val;
-    } enable_w1ts;
-    union {
-        struct {
-            uint32_t enable_w1tc:26;
-            uint32_t reserved26:  6;
-        };
-        uint32_t val;
-    } enable_w1tc;
-    uint32_t reserved_2c;
-    uint32_t reserved_30;
-    uint32_t reserved_34;
-    union {
-        struct {
-            uint32_t strapping: 16;
-            uint32_t reserved16:16;
-        };
-        uint32_t val;
-    } strap;
-    union {
-        struct {
-            uint32_t data:        26;
-            uint32_t reserved26:   6;
-        };
-        uint32_t val;
-    } in;
-    uint32_t reserved_40;
-    union {
-        struct {
-            uint32_t intr_st:         26;
-            uint32_t reserved26:       6;
-        };
-        uint32_t val;
-    } status;
-    union {
-        struct {
-            uint32_t status_w1ts:26;
-            uint32_t reserved26:  6;
-        };
-        uint32_t val;
-    } status_w1ts;
-    union {
-        struct {
-            uint32_t status_w1tc:26;
-            uint32_t reserved26:  6;
-        };
-        uint32_t val;
-    } status_w1tc;
-    uint32_t reserved_50;
-    uint32_t reserved_54;
-    uint32_t reserved_58;
-    union {
-        struct {
-            uint32_t intr:      26;
-            uint32_t reserved26: 6;
-        };
-        uint32_t val;
-    } pcpu_int;
-    union {
-        struct {
-            uint32_t intr:          26;
-            uint32_t reserved26:     6;
-        };
-        uint32_t val;
-    } pcpu_nmi_int;
-    union {
-        struct {
-            uint32_t intr:      26;
-            uint32_t reserved26: 6;
-        };
-        uint32_t val;
-    } cpusdio_int;
-    uint32_t reserved_68;
-    uint32_t reserved_6c;
-    uint32_t reserved_70;
-    union {
-        struct {
-            uint32_t sync2_bypass:       2;
-            uint32_t pad_driver:         1;
-            uint32_t sync1_bypass:       2;
-            uint32_t reserved5:          2;
-            uint32_t int_type:           3;
-            uint32_t wakeup_enable:      1;
-            uint32_t config:             2;
-            uint32_t int_ena:            5;
-            uint32_t reserved18:        14;
-        };
-        uint32_t val;
-    } pin[26];
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    uint32_t reserved_fc;
-    uint32_t reserved_100;
-    uint32_t reserved_104;
-    uint32_t reserved_108;
-    uint32_t reserved_10c;
-    uint32_t reserved_110;
-    uint32_t reserved_114;
-    uint32_t reserved_118;
-    uint32_t reserved_11c;
-    uint32_t reserved_120;
-    uint32_t reserved_124;
-    uint32_t reserved_128;
-    uint32_t reserved_12c;
-    uint32_t reserved_130;
-    uint32_t reserved_134;
-    uint32_t reserved_138;
-    uint32_t reserved_13c;
-    uint32_t reserved_140;
-    uint32_t reserved_144;
-    uint32_t reserved_148;
-    union {
-        struct {
-            uint32_t intr_st_next:         26;
-            uint32_t reserved26:            6;
-        };
-        uint32_t val;
-    } status_next;
-    uint32_t reserved_150;
-    union {
-        struct {
-            uint32_t func_sel:         5;
-            uint32_t sig_in_inv:       1;
-            uint32_t sig_in_sel:       1;
-            uint32_t reserved7:       25;
-        };
-        uint32_t val;
-    } func_in_sel_cfg[128];
-    uint32_t reserved_354;
-    uint32_t reserved_358;
-    uint32_t reserved_35c;
-    uint32_t reserved_360;
-    uint32_t reserved_364;
-    uint32_t reserved_368;
-    uint32_t reserved_36c;
-    uint32_t reserved_370;
-    uint32_t reserved_374;
-    uint32_t reserved_378;
-    uint32_t reserved_37c;
-    uint32_t reserved_380;
-    uint32_t reserved_384;
-    uint32_t reserved_388;
-    uint32_t reserved_38c;
-    uint32_t reserved_390;
-    uint32_t reserved_394;
-    uint32_t reserved_398;
-    uint32_t reserved_39c;
-    uint32_t reserved_3a0;
-    uint32_t reserved_3a4;
-    uint32_t reserved_3a8;
-    uint32_t reserved_3ac;
-    uint32_t reserved_3b0;
-    uint32_t reserved_3b4;
-    uint32_t reserved_3b8;
-    uint32_t reserved_3bc;
-    uint32_t reserved_3c0;
-    uint32_t reserved_3c4;
-    uint32_t reserved_3c8;
-    uint32_t reserved_3cc;
-    uint32_t reserved_3d0;
-    uint32_t reserved_3d4;
-    uint32_t reserved_3d8;
-    uint32_t reserved_3dc;
-    uint32_t reserved_3e0;
-    uint32_t reserved_3e4;
-    uint32_t reserved_3e8;
-    uint32_t reserved_3ec;
-    uint32_t reserved_3f0;
-    uint32_t reserved_3f4;
-    uint32_t reserved_3f8;
-    uint32_t reserved_3fc;
-    uint32_t reserved_400;
-    uint32_t reserved_404;
-    uint32_t reserved_408;
-    uint32_t reserved_40c;
-    uint32_t reserved_410;
-    uint32_t reserved_414;
-    uint32_t reserved_418;
-    uint32_t reserved_41c;
-    uint32_t reserved_420;
-    uint32_t reserved_424;
-    uint32_t reserved_428;
-    uint32_t reserved_42c;
-    uint32_t reserved_430;
-    uint32_t reserved_434;
-    uint32_t reserved_438;
-    uint32_t reserved_43c;
-    uint32_t reserved_440;
-    uint32_t reserved_444;
-    uint32_t reserved_448;
-    uint32_t reserved_44c;
-    uint32_t reserved_450;
-    uint32_t reserved_454;
-    uint32_t reserved_458;
-    uint32_t reserved_45c;
-    uint32_t reserved_460;
-    uint32_t reserved_464;
-    uint32_t reserved_468;
-    uint32_t reserved_46c;
-    uint32_t reserved_470;
-    uint32_t reserved_474;
-    uint32_t reserved_478;
-    uint32_t reserved_47c;
-    uint32_t reserved_480;
-    uint32_t reserved_484;
-    uint32_t reserved_488;
-    uint32_t reserved_48c;
-    uint32_t reserved_490;
-    uint32_t reserved_494;
-    uint32_t reserved_498;
-    uint32_t reserved_49c;
-    uint32_t reserved_4a0;
-    uint32_t reserved_4a4;
-    uint32_t reserved_4a8;
-    uint32_t reserved_4ac;
-    uint32_t reserved_4b0;
-    uint32_t reserved_4b4;
-    uint32_t reserved_4b8;
-    uint32_t reserved_4bc;
-    uint32_t reserved_4c0;
-    uint32_t reserved_4c4;
-    uint32_t reserved_4c8;
-    uint32_t reserved_4cc;
-    uint32_t reserved_4d0;
-    uint32_t reserved_4d4;
-    uint32_t reserved_4d8;
-    uint32_t reserved_4dc;
-    uint32_t reserved_4e0;
-    uint32_t reserved_4e4;
-    uint32_t reserved_4e8;
-    uint32_t reserved_4ec;
-    uint32_t reserved_4f0;
-    uint32_t reserved_4f4;
-    uint32_t reserved_4f8;
-    uint32_t reserved_4fc;
-    uint32_t reserved_500;
-    uint32_t reserved_504;
-    uint32_t reserved_508;
-    uint32_t reserved_50c;
-    uint32_t reserved_510;
-    uint32_t reserved_514;
-    uint32_t reserved_518;
-    uint32_t reserved_51c;
-    uint32_t reserved_520;
-    uint32_t reserved_524;
-    uint32_t reserved_528;
-    uint32_t reserved_52c;
-    uint32_t reserved_530;
-    uint32_t reserved_534;
-    uint32_t reserved_538;
-    uint32_t reserved_53c;
-    uint32_t reserved_540;
-    uint32_t reserved_544;
-    uint32_t reserved_548;
-    uint32_t reserved_54c;
-    uint32_t reserved_550;
-    union {
-        struct {
-            uint32_t func_sel:          8;
-            uint32_t inv_sel:           1;
-            uint32_t oen_sel:           1;
-            uint32_t oen_inv_sel:       1;
-            uint32_t reserved11:       21;
-        };
-        uint32_t val;
-    } func_out_sel_cfg[26];
-    uint32_t reserved_5bc;
-    uint32_t reserved_5c0;
-    uint32_t reserved_5c4;
-    uint32_t reserved_5c8;
-    uint32_t reserved_5cc;
-    uint32_t reserved_5d0;
-    uint32_t reserved_5d4;
-    uint32_t reserved_5d8;
-    uint32_t reserved_5dc;
-    uint32_t reserved_5e0;
-    uint32_t reserved_5e4;
-    uint32_t reserved_5e8;
-    uint32_t reserved_5ec;
-    uint32_t reserved_5f0;
-    uint32_t reserved_5f4;
-    uint32_t reserved_5f8;
-    uint32_t reserved_5fc;
-    uint32_t reserved_600;
-    uint32_t reserved_604;
-    uint32_t reserved_608;
-    uint32_t reserved_60c;
-    uint32_t reserved_610;
-    uint32_t reserved_614;
-    uint32_t reserved_618;
-    uint32_t reserved_61c;
-    uint32_t reserved_620;
-    uint32_t reserved_624;
-    uint32_t reserved_628;
-    union {
-        struct {
-            uint32_t clk_en:     1;
-            uint32_t reserved1: 31;
-        };
-        uint32_t val;
-    } clock_gate;
-    uint32_t reserved_630;
-    uint32_t reserved_634;
-    uint32_t reserved_638;
-    uint32_t reserved_63c;
-    uint32_t reserved_640;
-    uint32_t reserved_644;
-    uint32_t reserved_648;
-    uint32_t reserved_64c;
-    uint32_t reserved_650;
-    uint32_t reserved_654;
-    uint32_t reserved_658;
-    uint32_t reserved_65c;
-    uint32_t reserved_660;
-    uint32_t reserved_664;
-    uint32_t reserved_668;
-    uint32_t reserved_66c;
-    uint32_t reserved_670;
-    uint32_t reserved_674;
-    uint32_t reserved_678;
-    uint32_t reserved_67c;
-    uint32_t reserved_680;
-    uint32_t reserved_684;
-    uint32_t reserved_688;
-    uint32_t reserved_68c;
-    uint32_t reserved_690;
-    uint32_t reserved_694;
-    uint32_t reserved_698;
-    uint32_t reserved_69c;
-    uint32_t reserved_6a0;
-    uint32_t reserved_6a4;
-    uint32_t reserved_6a8;
-    uint32_t reserved_6ac;
-    uint32_t reserved_6b0;
-    uint32_t reserved_6b4;
-    uint32_t reserved_6b8;
-    uint32_t reserved_6bc;
-    uint32_t reserved_6c0;
-    uint32_t reserved_6c4;
-    uint32_t reserved_6c8;
-    uint32_t reserved_6cc;
-    uint32_t reserved_6d0;
-    uint32_t reserved_6d4;
-    uint32_t reserved_6d8;
-    uint32_t reserved_6dc;
-    uint32_t reserved_6e0;
-    uint32_t reserved_6e4;
-    uint32_t reserved_6e8;
-    uint32_t reserved_6ec;
-    uint32_t reserved_6f0;
-    uint32_t reserved_6f4;
-    uint32_t reserved_6f8;
-    union {
-        struct {
-            uint32_t date:      28;
-            uint32_t reserved28: 4;
-        };
-        uint32_t val;
-    } date;
-} gpio_dev_t;
-extern gpio_dev_t GPIO;
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_GPIO_STRUCT_H_ */

components/soc/esp32h2/include/soc/reg_base.h

@@ -70,5 +70,5 @@
 #define DR_REG_APB_SARADC_BASE                  0x60040000
 #define DR_REG_LCD_CAM_BASE                     0x60041000
 #define DR_REG_AES_XTS_BASE                     0x600CC000
-#define DR_REG_USB_DEVICE_BASE                  0x60043000
+#define DR_REG_USB_SERIAL_JTAG_BASE             0x60043000
 #define DR_REG_CLKRST_BASE                      0x6004B000

components/soc/esp32h2/include/soc/soc_caps.h

@@ -23,6 +23,15 @@
 
 #pragma once
 
+#ifdef __has_include
+#  if __has_include("sdkconfig.h")
+#   include "sdkconfig.h"
+#  else
+#   warning Chip version cannot be determined. Default chip to ESP32H2_BETA_VERSION_1.
+#   define CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1     1
+#  endif
+#endif
+
 /*-------------------------- COMMON CAPS ---------------------------------------*/
 #define SOC_CPU_CORES_NUM               1
 #define SOC_ADC_SUPPORTED               1
@@ -110,21 +119,29 @@
 #define SOC_GDMA_TX_RX_SHARE_INTERRUPT  (1)  // TX and RX channel in the same pair will share the same interrupt source number
 
 /*-------------------------- GPIO CAPS ---------------------------------------*/
-// ESP32-C3 has 1 GPIO peripheral
+// ESP32-H2 has 1 GPIO peripheral
 #define SOC_GPIO_PORT               (1U)
-#define SOC_GPIO_PIN_COUNT          (22)
+#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
+#define SOC_GPIO_PIN_COUNT          (41)
+#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
+#define SOC_GPIO_PIN_COUNT          (26)
+#endif
 
 // Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
-// On ESP32-C3, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.
+// On ESP32-H2, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.
 #define SOC_GPIO_SUPPORTS_RTC_INDEPENDENT       (1)
-// Force hold is a new function of ESP32-C3
+// Force hold is a new function of ESP32-H2
 #define SOC_GPIO_SUPPORT_FORCE_HOLD         (1)
-// GPIO0~5 on ESP32C3 can support chip deep sleep wakeup
+// GPIO0~5 on ESP32H2Beta1 / GPIO7~12 on ESP32H2Beta2 can support chip deep sleep wakeup
 #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)
 
-#define SOC_GPIO_VALID_GPIO_MASK        ((1U<<SOC_GPIO_PIN_COUNT) - 1)
+#define SOC_GPIO_VALID_GPIO_MASK        ((1ULL<<SOC_GPIO_PIN_COUNT) - 1)
 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
+#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
 #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
+#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
+#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT7 | BIT8 | BIT9 | BIT10 | BIT11 | BIT12)
+#endif
 
 // Support to configure sleep status
 #define SOC_GPIO_SUPPORT_SLP_SWITCH  (1)
@@ -188,7 +205,7 @@
 #define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE  (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
 
 /*-------------------------- RTCIO CAPS --------------------------------------*/
-/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported
+/* No dedicated RTCIO subsystem on ESP32-H2. RTC functions are still supported
  * for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
 #define SOC_RTCIO_PIN_COUNT    (0U)
 
@@ -267,7 +284,7 @@
 #define SOC_TIMER_GROUP_TOTAL_TIMERS      (2)
 
 /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
-#define SOC_TOUCH_SENSOR_NUM            (0)    /*! No touch sensors on ESP32-C3 */
+#define SOC_TOUCH_SENSOR_NUM            (0)    /*! No touch sensors on ESP32-H2 */
 
 /*-------------------------- TWAI CAPS ---------------------------------------*/
 #define SOC_TWAI_BRP_MIN                2

components/soc/esp32s3/include/soc/reg_base.h

@@ -46,7 +46,7 @@
 #define DR_REG_PWM1_BASE                        0x6002C000
 #define DR_REG_I2S1_BASE                        0x6002D000
 #define DR_REG_UART2_BASE                       0x6002E000
-#define DR_REG_USB_DEVICE_BASE                  0x60038000
+#define DR_REG_USB_SERIAL_JTAG_BASE             0x60038000
 #define DR_REG_USB_WRAP_BASE                    0x60039000
 #define DR_REG_AES_BASE                         0x6003A000
 #define DR_REG_SHA_BASE                         0x6003B000

components/soc/esp32s3/include/soc/usb_device_reg.h

@@ -1,737 +0,0 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_USB_DEVICE_REG_H_
-#define _SOC_USB_DEVICE_REG_H_
-
-
-#include "soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define USB_DEVICE_EP1_REG          (DR_REG_USB_DEVICE_BASE + 0x0)
-/* USB_DEVICE_RDWR_BYTE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DE
-VICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into
-UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB
-_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is rece
-ived, then read data from UART Rx FIFO..*/
-#define USB_DEVICE_RDWR_BYTE    0x000000FF
-#define USB_DEVICE_RDWR_BYTE_M  ((USB_DEVICE_RDWR_BYTE_V)<<(USB_DEVICE_RDWR_BYTE_S))
-#define USB_DEVICE_RDWR_BYTE_V  0xFF
-#define USB_DEVICE_RDWR_BYTE_S  0
-
-#define USB_DEVICE_EP1_CONF_REG          (DR_REG_USB_DEVICE_BASE + 0x4)
-/* USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: 1'b1: Indicate there is data in UART Rx FIFO..*/
-#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
-#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL_M  (BIT(2))
-#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL_V  0x1
-#define USB_DEVICE_SERIAL_OUT_EP_DATA_AVAIL_S  2
-/* USB_DEVICE_SERIAL_IN_EP_DATA_FREE : RO ;bitpos:[1] ;default: 1'b1 ; */
-/*description: 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writin
-g USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
-USB Host..*/
-#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE    (BIT(1))
-#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE_M  (BIT(1))
-#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE_V  0x1
-#define USB_DEVICE_SERIAL_IN_EP_DATA_FREE_S  1
-/* USB_DEVICE_WR_DONE : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to indicate writing byte data to UART Tx FIFO is done..*/
-#define USB_DEVICE_WR_DONE    (BIT(0))
-#define USB_DEVICE_WR_DONE_M  (BIT(0))
-#define USB_DEVICE_WR_DONE_V  0x1
-#define USB_DEVICE_WR_DONE_S  0
-
-#define USB_DEVICE_INT_RAW_REG          (DR_REG_USB_DEVICE_BASE + 0x8)
-/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when OUT endpoint 2 received packet wi
-th zero palyload..*/
-#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
-#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (BIT(11))
-#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x1
-#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
-/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when OUT endpoint 1 received packet wi
-th zero palyload..*/
-#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
-#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (BIT(10))
-#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x1
-#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
-/* USB_DEVICE_USB_BUS_RESET_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when usb bus reset is detected..*/
-#define USB_DEVICE_USB_BUS_RESET_INT_RAW    (BIT(9))
-#define USB_DEVICE_USB_BUS_RESET_INT_RAW_M  (BIT(9))
-#define USB_DEVICE_USB_BUS_RESET_INT_RAW_V  0x1
-#define USB_DEVICE_USB_BUS_RESET_INT_RAW_S  9
-/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when IN token for IN endpoint 1 is rec
-eived..*/
-#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
-#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (BIT(8))
-#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x1
-#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
-/* USB_DEVICE_STUFF_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when stuff error is detected..*/
-#define USB_DEVICE_STUFF_ERR_INT_RAW    (BIT(7))
-#define USB_DEVICE_STUFF_ERR_INT_RAW_M  (BIT(7))
-#define USB_DEVICE_STUFF_ERR_INT_RAW_V  0x1
-#define USB_DEVICE_STUFF_ERR_INT_RAW_S  7
-/* USB_DEVICE_CRC16_ERR_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when CRC16 error is detected..*/
-#define USB_DEVICE_CRC16_ERR_INT_RAW    (BIT(6))
-#define USB_DEVICE_CRC16_ERR_INT_RAW_M  (BIT(6))
-#define USB_DEVICE_CRC16_ERR_INT_RAW_V  0x1
-#define USB_DEVICE_CRC16_ERR_INT_RAW_S  6
-/* USB_DEVICE_CRC5_ERR_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when CRC5 error is detected..*/
-#define USB_DEVICE_CRC5_ERR_INT_RAW    (BIT(5))
-#define USB_DEVICE_CRC5_ERR_INT_RAW_M  (BIT(5))
-#define USB_DEVICE_CRC5_ERR_INT_RAW_V  0x1
-#define USB_DEVICE_CRC5_ERR_INT_RAW_S  5
-/* USB_DEVICE_PID_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when pid error is detected..*/
-#define USB_DEVICE_PID_ERR_INT_RAW    (BIT(4))
-#define USB_DEVICE_PID_ERR_INT_RAW_M  (BIT(4))
-#define USB_DEVICE_PID_ERR_INT_RAW_V  0x1
-#define USB_DEVICE_PID_ERR_INT_RAW_S  4
-/* USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b1 ; */
-/*description: The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty..*/
-#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
-#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW_M  (BIT(3))
-#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW_V  0x1
-#define USB_DEVICE_SERIAL_IN_EMPTY_INT_RAW_S  3
-/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
- one packet..*/
-#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
-#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW_M  (BIT(2))
-#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x1
-#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
-/* USB_DEVICE_SOF_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when SOF frame is received..*/
-#define USB_DEVICE_SOF_INT_RAW    (BIT(1))
-#define USB_DEVICE_SOF_INT_RAW_M  (BIT(1))
-#define USB_DEVICE_SOF_INT_RAW_V  0x1
-#define USB_DEVICE_SOF_INT_RAW_S  1
-/* USB_DEVICE_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when flush cmd is received for IN endp
-oint 2 of JTAG..*/
-#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
-#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW_M  (BIT(0))
-#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW_V  0x1
-#define USB_DEVICE_JTAG_IN_FLUSH_INT_RAW_S  0
-
-#define USB_DEVICE_INT_ST_REG          (DR_REG_USB_DEVICE_BASE + 0xC)
-/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interru
-pt..*/
-#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
-#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (BIT(11))
-#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x1
-#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
-/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interru
-pt..*/
-#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
-#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (BIT(10))
-#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x1
-#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
-/* USB_DEVICE_USB_BUS_RESET_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt..*/
-#define USB_DEVICE_USB_BUS_RESET_INT_ST    (BIT(9))
-#define USB_DEVICE_USB_BUS_RESET_INT_ST_M  (BIT(9))
-#define USB_DEVICE_USB_BUS_RESET_INT_ST_V  0x1
-#define USB_DEVICE_USB_BUS_RESET_INT_ST_S  9
-/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrup
-t..*/
-#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
-#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST_M  (BIT(8))
-#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x1
-#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
-/* USB_DEVICE_STUFF_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt..*/
-#define USB_DEVICE_STUFF_ERR_INT_ST    (BIT(7))
-#define USB_DEVICE_STUFF_ERR_INT_ST_M  (BIT(7))
-#define USB_DEVICE_STUFF_ERR_INT_ST_V  0x1
-#define USB_DEVICE_STUFF_ERR_INT_ST_S  7
-/* USB_DEVICE_CRC16_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt..*/
-#define USB_DEVICE_CRC16_ERR_INT_ST    (BIT(6))
-#define USB_DEVICE_CRC16_ERR_INT_ST_M  (BIT(6))
-#define USB_DEVICE_CRC16_ERR_INT_ST_V  0x1
-#define USB_DEVICE_CRC16_ERR_INT_ST_S  6
-/* USB_DEVICE_CRC5_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt..*/
-#define USB_DEVICE_CRC5_ERR_INT_ST    (BIT(5))
-#define USB_DEVICE_CRC5_ERR_INT_ST_M  (BIT(5))
-#define USB_DEVICE_CRC5_ERR_INT_ST_V  0x1
-#define USB_DEVICE_CRC5_ERR_INT_ST_S  5
-/* USB_DEVICE_PID_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt..*/
-#define USB_DEVICE_PID_ERR_INT_ST    (BIT(4))
-#define USB_DEVICE_PID_ERR_INT_ST_M  (BIT(4))
-#define USB_DEVICE_PID_ERR_INT_ST_V  0x1
-#define USB_DEVICE_PID_ERR_INT_ST_S  4
-/* USB_DEVICE_SERIAL_IN_EMPTY_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt..*/
-#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
-#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST_M  (BIT(3))
-#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST_V  0x1
-#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ST_S  3
-/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrup
-t..*/
-#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
-#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST_M  (BIT(2))
-#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST_V  0x1
-#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ST_S  2
-/* USB_DEVICE_SOF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt..*/
-#define USB_DEVICE_SOF_INT_ST    (BIT(1))
-#define USB_DEVICE_SOF_INT_ST_M  (BIT(1))
-#define USB_DEVICE_SOF_INT_ST_V  0x1
-#define USB_DEVICE_SOF_INT_ST_S  1
-/* USB_DEVICE_JTAG_IN_FLUSH_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt..*/
-#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST    (BIT(0))
-#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST_M  (BIT(0))
-#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST_V  0x1
-#define USB_DEVICE_JTAG_IN_FLUSH_INT_ST_S  0
-
-#define USB_DEVICE_INT_ENA_REG          (DR_REG_USB_DEVICE_BASE + 0x10)
-/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/
-#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
-#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (BIT(11))
-#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x1
-#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
-/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt..*/
-#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
-#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (BIT(10))
-#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x1
-#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
-/* USB_DEVICE_USB_BUS_RESET_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt..*/
-#define USB_DEVICE_USB_BUS_RESET_INT_ENA    (BIT(9))
-#define USB_DEVICE_USB_BUS_RESET_INT_ENA_M  (BIT(9))
-#define USB_DEVICE_USB_BUS_RESET_INT_ENA_V  0x1
-#define USB_DEVICE_USB_BUS_RESET_INT_ENA_S  9
-/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt..*/
-#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
-#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (BIT(8))
-#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x1
-#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
-/* USB_DEVICE_STUFF_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt..*/
-#define USB_DEVICE_STUFF_ERR_INT_ENA    (BIT(7))
-#define USB_DEVICE_STUFF_ERR_INT_ENA_M  (BIT(7))
-#define USB_DEVICE_STUFF_ERR_INT_ENA_V  0x1
-#define USB_DEVICE_STUFF_ERR_INT_ENA_S  7
-/* USB_DEVICE_CRC16_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt..*/
-#define USB_DEVICE_CRC16_ERR_INT_ENA    (BIT(6))
-#define USB_DEVICE_CRC16_ERR_INT_ENA_M  (BIT(6))
-#define USB_DEVICE_CRC16_ERR_INT_ENA_V  0x1
-#define USB_DEVICE_CRC16_ERR_INT_ENA_S  6
-/* USB_DEVICE_CRC5_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt..*/
-#define USB_DEVICE_CRC5_ERR_INT_ENA    (BIT(5))
-#define USB_DEVICE_CRC5_ERR_INT_ENA_M  (BIT(5))
-#define USB_DEVICE_CRC5_ERR_INT_ENA_V  0x1
-#define USB_DEVICE_CRC5_ERR_INT_ENA_S  5
-/* USB_DEVICE_PID_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt..*/
-#define USB_DEVICE_PID_ERR_INT_ENA    (BIT(4))
-#define USB_DEVICE_PID_ERR_INT_ENA_M  (BIT(4))
-#define USB_DEVICE_PID_ERR_INT_ENA_V  0x1
-#define USB_DEVICE_PID_ERR_INT_ENA_S  4
-/* USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt..*/
-#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
-#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA_M  (BIT(3))
-#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA_V  0x1
-#define USB_DEVICE_SERIAL_IN_EMPTY_INT_ENA_S  3
-/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt..*/
-#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
-#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA_M  (BIT(2))
-#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x1
-#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
-/* USB_DEVICE_SOF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt..*/
-#define USB_DEVICE_SOF_INT_ENA    (BIT(1))
-#define USB_DEVICE_SOF_INT_ENA_M  (BIT(1))
-#define USB_DEVICE_SOF_INT_ENA_V  0x1
-#define USB_DEVICE_SOF_INT_ENA_S  1
-/* USB_DEVICE_JTAG_IN_FLUSH_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt..*/
-#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
-#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA_M  (BIT(0))
-#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA_V  0x1
-#define USB_DEVICE_JTAG_IN_FLUSH_INT_ENA_S  0
-
-#define USB_DEVICE_INT_CLR_REG          (DR_REG_USB_DEVICE_BASE + 0x14)
-/* USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/
-#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
-#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (BIT(11))
-#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x1
-#define USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
-/* USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt..*/
-#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
-#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (BIT(10))
-#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x1
-#define USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
-/* USB_DEVICE_USB_BUS_RESET_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt..*/
-#define USB_DEVICE_USB_BUS_RESET_INT_CLR    (BIT(9))
-#define USB_DEVICE_USB_BUS_RESET_INT_CLR_M  (BIT(9))
-#define USB_DEVICE_USB_BUS_RESET_INT_CLR_V  0x1
-#define USB_DEVICE_USB_BUS_RESET_INT_CLR_S  9
-/* USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt..*/
-#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
-#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (BIT(8))
-#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x1
-#define USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
-/* USB_DEVICE_STUFF_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt..*/
-#define USB_DEVICE_STUFF_ERR_INT_CLR    (BIT(7))
-#define USB_DEVICE_STUFF_ERR_INT_CLR_M  (BIT(7))
-#define USB_DEVICE_STUFF_ERR_INT_CLR_V  0x1
-#define USB_DEVICE_STUFF_ERR_INT_CLR_S  7
-/* USB_DEVICE_CRC16_ERR_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt..*/
-#define USB_DEVICE_CRC16_ERR_INT_CLR    (BIT(6))
-#define USB_DEVICE_CRC16_ERR_INT_CLR_M  (BIT(6))
-#define USB_DEVICE_CRC16_ERR_INT_CLR_V  0x1
-#define USB_DEVICE_CRC16_ERR_INT_CLR_S  6
-/* USB_DEVICE_CRC5_ERR_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt..*/
-#define USB_DEVICE_CRC5_ERR_INT_CLR    (BIT(5))
-#define USB_DEVICE_CRC5_ERR_INT_CLR_M  (BIT(5))
-#define USB_DEVICE_CRC5_ERR_INT_CLR_V  0x1
-#define USB_DEVICE_CRC5_ERR_INT_CLR_S  5
-/* USB_DEVICE_PID_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt..*/
-#define USB_DEVICE_PID_ERR_INT_CLR    (BIT(4))
-#define USB_DEVICE_PID_ERR_INT_CLR_M  (BIT(4))
-#define USB_DEVICE_PID_ERR_INT_CLR_V  0x1
-#define USB_DEVICE_PID_ERR_INT_CLR_S  4
-/* USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt..*/
-#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
-#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR_M  (BIT(3))
-#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR_V  0x1
-#define USB_DEVICE_SERIAL_IN_EMPTY_INT_CLR_S  3
-/* USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt..*/
-#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
-#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR_M  (BIT(2))
-#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x1
-#define USB_DEVICE_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
-/* USB_DEVICE_SOF_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt..*/
-#define USB_DEVICE_SOF_INT_CLR    (BIT(1))
-#define USB_DEVICE_SOF_INT_CLR_M  (BIT(1))
-#define USB_DEVICE_SOF_INT_CLR_V  0x1
-#define USB_DEVICE_SOF_INT_CLR_S  1
-/* USB_DEVICE_JTAG_IN_FLUSH_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt..*/
-#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
-#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR_M  (BIT(0))
-#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR_V  0x1
-#define USB_DEVICE_JTAG_IN_FLUSH_INT_CLR_S  0
-
-#define USB_DEVICE_CONF0_REG          (DR_REG_USB_DEVICE_BASE + 0x18)
-/* USB_DEVICE_PHY_TX_EDGE_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: 0: TX output at clock negedge. 1: Tx output at clock posedge..*/
-#define USB_DEVICE_PHY_TX_EDGE_SEL    (BIT(15))
-#define USB_DEVICE_PHY_TX_EDGE_SEL_M  (BIT(15))
-#define USB_DEVICE_PHY_TX_EDGE_SEL_V  0x1
-#define USB_DEVICE_PHY_TX_EDGE_SEL_S  15
-/* USB_DEVICE_USB_PAD_ENABLE : R/W ;bitpos:[14] ;default: 1'b1 ; */
-/*description: Enable USB pad function..*/
-#define USB_DEVICE_USB_PAD_ENABLE    (BIT(14))
-#define USB_DEVICE_USB_PAD_ENABLE_M  (BIT(14))
-#define USB_DEVICE_USB_PAD_ENABLE_V  0x1
-#define USB_DEVICE_USB_PAD_ENABLE_S  14
-/* USB_DEVICE_PULLUP_VALUE : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Control pull up value..*/
-#define USB_DEVICE_PULLUP_VALUE    (BIT(13))
-#define USB_DEVICE_PULLUP_VALUE_M  (BIT(13))
-#define USB_DEVICE_PULLUP_VALUE_V  0x1
-#define USB_DEVICE_PULLUP_VALUE_S  13
-/* USB_DEVICE_DM_PULLDOWN : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Control USB D- pull down..*/
-#define USB_DEVICE_DM_PULLDOWN    (BIT(12))
-#define USB_DEVICE_DM_PULLDOWN_M  (BIT(12))
-#define USB_DEVICE_DM_PULLDOWN_V  0x1
-#define USB_DEVICE_DM_PULLDOWN_S  12
-/* USB_DEVICE_DM_PULLUP : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Control USB D- pull up..*/
-#define USB_DEVICE_DM_PULLUP    (BIT(11))
-#define USB_DEVICE_DM_PULLUP_M  (BIT(11))
-#define USB_DEVICE_DM_PULLUP_V  0x1
-#define USB_DEVICE_DM_PULLUP_S  11
-/* USB_DEVICE_DP_PULLDOWN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Control USB D+ pull down..*/
-#define USB_DEVICE_DP_PULLDOWN    (BIT(10))
-#define USB_DEVICE_DP_PULLDOWN_M  (BIT(10))
-#define USB_DEVICE_DP_PULLDOWN_V  0x1
-#define USB_DEVICE_DP_PULLDOWN_S  10
-/* USB_DEVICE_DP_PULLUP : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: Control USB D+ pull up..*/
-#define USB_DEVICE_DP_PULLUP    (BIT(9))
-#define USB_DEVICE_DP_PULLUP_M  (BIT(9))
-#define USB_DEVICE_DP_PULLUP_V  0x1
-#define USB_DEVICE_DP_PULLUP_S  9
-/* USB_DEVICE_PAD_PULL_OVERRIDE : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Enable software control USB D+ D- pullup pulldown.*/
-#define USB_DEVICE_PAD_PULL_OVERRIDE    (BIT(8))
-#define USB_DEVICE_PAD_PULL_OVERRIDE_M  (BIT(8))
-#define USB_DEVICE_PAD_PULL_OVERRIDE_V  0x1
-#define USB_DEVICE_PAD_PULL_OVERRIDE_S  8
-/* USB_DEVICE_VREF_OVERRIDE : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Enable software control input  threshold.*/
-#define USB_DEVICE_VREF_OVERRIDE    (BIT(7))
-#define USB_DEVICE_VREF_OVERRIDE_M  (BIT(7))
-#define USB_DEVICE_VREF_OVERRIDE_V  0x1
-#define USB_DEVICE_VREF_OVERRIDE_S  7
-/* USB_DEVICE_VREFL : R/W ;bitpos:[6:5] ;default: 2'b0 ; */
-/*description: Control single-end input low threshold,0.8V to 1.04V, step 80mV.*/
-#define USB_DEVICE_VREFL    0x00000003
-#define USB_DEVICE_VREFL_M  ((USB_DEVICE_VREFL_V)<<(USB_DEVICE_VREFL_S))
-#define USB_DEVICE_VREFL_V  0x3
-#define USB_DEVICE_VREFL_S  5
-/* USB_DEVICE_VREFH : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
-/*description: Control single-end input high threshold,1.76V to 2V, step 80mV.*/
-#define USB_DEVICE_VREFH    0x00000003
-#define USB_DEVICE_VREFH_M  ((USB_DEVICE_VREFH_V)<<(USB_DEVICE_VREFH_S))
-#define USB_DEVICE_VREFH_V  0x3
-#define USB_DEVICE_VREFH_S  3
-/* USB_DEVICE_EXCHG_PINS : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: USB D+ D- exchange.*/
-#define USB_DEVICE_EXCHG_PINS    (BIT(2))
-#define USB_DEVICE_EXCHG_PINS_M  (BIT(2))
-#define USB_DEVICE_EXCHG_PINS_V  0x1
-#define USB_DEVICE_EXCHG_PINS_S  2
-/* USB_DEVICE_EXCHG_PINS_OVERRIDE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Enable software control USB D+ D- exchange.*/
-#define USB_DEVICE_EXCHG_PINS_OVERRIDE    (BIT(1))
-#define USB_DEVICE_EXCHG_PINS_OVERRIDE_M  (BIT(1))
-#define USB_DEVICE_EXCHG_PINS_OVERRIDE_V  0x1
-#define USB_DEVICE_EXCHG_PINS_OVERRIDE_S  1
-/* USB_DEVICE_PHY_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Select internal/external PHY.*/
-#define USB_DEVICE_PHY_SEL    (BIT(0))
-#define USB_DEVICE_PHY_SEL_M  (BIT(0))
-#define USB_DEVICE_PHY_SEL_V  0x1
-#define USB_DEVICE_PHY_SEL_S  0
-
-#define USB_DEVICE_TEST_REG          (DR_REG_USB_DEVICE_BASE + 0x1C)
-/* USB_DEVICE_TEST_RX_DM : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: USB D- rx value in test.*/
-#define USB_DEVICE_TEST_RX_DM    (BIT(6))
-#define USB_DEVICE_TEST_RX_DM_M  (BIT(6))
-#define USB_DEVICE_TEST_RX_DM_V  0x1
-#define USB_DEVICE_TEST_RX_DM_S  6
-/* USB_DEVICE_TEST_RX_DP : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: USB D+ rx value in test.*/
-#define USB_DEVICE_TEST_RX_DP    (BIT(5))
-#define USB_DEVICE_TEST_RX_DP_M  (BIT(5))
-#define USB_DEVICE_TEST_RX_DP_V  0x1
-#define USB_DEVICE_TEST_RX_DP_S  5
-/* USB_DEVICE_TEST_RX_RCV : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: USB differential rx value in test.*/
-#define USB_DEVICE_TEST_RX_RCV    (BIT(4))
-#define USB_DEVICE_TEST_RX_RCV_M  (BIT(4))
-#define USB_DEVICE_TEST_RX_RCV_V  0x1
-#define USB_DEVICE_TEST_RX_RCV_S  4
-/* USB_DEVICE_TEST_TX_DM : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: USB D- tx value in test.*/
-#define USB_DEVICE_TEST_TX_DM    (BIT(3))
-#define USB_DEVICE_TEST_TX_DM_M  (BIT(3))
-#define USB_DEVICE_TEST_TX_DM_V  0x1
-#define USB_DEVICE_TEST_TX_DM_S  3
-/* USB_DEVICE_TEST_TX_DP : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: USB D+ tx value in test.*/
-#define USB_DEVICE_TEST_TX_DP    (BIT(2))
-#define USB_DEVICE_TEST_TX_DP_M  (BIT(2))
-#define USB_DEVICE_TEST_TX_DP_V  0x1
-#define USB_DEVICE_TEST_TX_DP_S  2
-/* USB_DEVICE_TEST_USB_OE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: USB pad oen in test.*/
-#define USB_DEVICE_TEST_USB_OE    (BIT(1))
-#define USB_DEVICE_TEST_USB_OE_M  (BIT(1))
-#define USB_DEVICE_TEST_USB_OE_V  0x1
-#define USB_DEVICE_TEST_USB_OE_S  1
-/* USB_DEVICE_TEST_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Enable test of the USB pad.*/
-#define USB_DEVICE_TEST_ENABLE    (BIT(0))
-#define USB_DEVICE_TEST_ENABLE_M  (BIT(0))
-#define USB_DEVICE_TEST_ENABLE_V  0x1
-#define USB_DEVICE_TEST_ENABLE_S  0
-
-#define USB_DEVICE_JFIFO_ST_REG          (DR_REG_USB_DEVICE_BASE + 0x20)
-/* USB_DEVICE_OUT_FIFO_RESET : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Write 1 to reset JTAG out fifo..*/
-#define USB_DEVICE_OUT_FIFO_RESET    (BIT(9))
-#define USB_DEVICE_OUT_FIFO_RESET_M  (BIT(9))
-#define USB_DEVICE_OUT_FIFO_RESET_V  0x1
-#define USB_DEVICE_OUT_FIFO_RESET_S  9
-/* USB_DEVICE_IN_FIFO_RESET : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Write 1 to reset JTAG in fifo..*/
-#define USB_DEVICE_IN_FIFO_RESET    (BIT(8))
-#define USB_DEVICE_IN_FIFO_RESET_M  (BIT(8))
-#define USB_DEVICE_IN_FIFO_RESET_V  0x1
-#define USB_DEVICE_IN_FIFO_RESET_S  8
-/* USB_DEVICE_OUT_FIFO_FULL : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: 1: JTAG out fifo is full..*/
-#define USB_DEVICE_OUT_FIFO_FULL    (BIT(7))
-#define USB_DEVICE_OUT_FIFO_FULL_M  (BIT(7))
-#define USB_DEVICE_OUT_FIFO_FULL_V  0x1
-#define USB_DEVICE_OUT_FIFO_FULL_S  7
-/* USB_DEVICE_OUT_FIFO_EMPTY : RO ;bitpos:[6] ;default: 1'b1 ; */
-/*description: 1: JTAG out fifo is empty..*/
-#define USB_DEVICE_OUT_FIFO_EMPTY    (BIT(6))
-#define USB_DEVICE_OUT_FIFO_EMPTY_M  (BIT(6))
-#define USB_DEVICE_OUT_FIFO_EMPTY_V  0x1
-#define USB_DEVICE_OUT_FIFO_EMPTY_S  6
-/* USB_DEVICE_OUT_FIFO_CNT : RO ;bitpos:[5:4] ;default: 2'd0 ; */
-/*description: JTAT out fifo counter..*/
-#define USB_DEVICE_OUT_FIFO_CNT    0x00000003
-#define USB_DEVICE_OUT_FIFO_CNT_M  ((USB_DEVICE_OUT_FIFO_CNT_V)<<(USB_DEVICE_OUT_FIFO_CNT_S))
-#define USB_DEVICE_OUT_FIFO_CNT_V  0x3
-#define USB_DEVICE_OUT_FIFO_CNT_S  4
-/* USB_DEVICE_IN_FIFO_FULL : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: 1: JTAG in fifo is full..*/
-#define USB_DEVICE_IN_FIFO_FULL    (BIT(3))
-#define USB_DEVICE_IN_FIFO_FULL_M  (BIT(3))
-#define USB_DEVICE_IN_FIFO_FULL_V  0x1
-#define USB_DEVICE_IN_FIFO_FULL_S  3
-/* USB_DEVICE_IN_FIFO_EMPTY : RO ;bitpos:[2] ;default: 1'b1 ; */
-/*description: 1: JTAG in fifo is empty..*/
-#define USB_DEVICE_IN_FIFO_EMPTY    (BIT(2))
-#define USB_DEVICE_IN_FIFO_EMPTY_M  (BIT(2))
-#define USB_DEVICE_IN_FIFO_EMPTY_V  0x1
-#define USB_DEVICE_IN_FIFO_EMPTY_S  2
-/* USB_DEVICE_IN_FIFO_CNT : RO ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: JTAT in fifo counter..*/
-#define USB_DEVICE_IN_FIFO_CNT    0x00000003
-#define USB_DEVICE_IN_FIFO_CNT_M  ((USB_DEVICE_IN_FIFO_CNT_V)<<(USB_DEVICE_IN_FIFO_CNT_S))
-#define USB_DEVICE_IN_FIFO_CNT_V  0x3
-#define USB_DEVICE_IN_FIFO_CNT_S  0
-
-#define USB_DEVICE_FRAM_NUM_REG          (DR_REG_USB_DEVICE_BASE + 0x24)
-/* USB_DEVICE_SOF_FRAME_INDEX : RO ;bitpos:[10:0] ;default: 11'd0 ; */
-/*description: Frame index of received SOF frame..*/
-#define USB_DEVICE_SOF_FRAME_INDEX    0x000007FF
-#define USB_DEVICE_SOF_FRAME_INDEX_M  ((USB_DEVICE_SOF_FRAME_INDEX_V)<<(USB_DEVICE_SOF_FRAME_INDEX_S))
-#define USB_DEVICE_SOF_FRAME_INDEX_V  0x7FF
-#define USB_DEVICE_SOF_FRAME_INDEX_S  0
-
-#define USB_DEVICE_IN_EP0_ST_REG          (DR_REG_USB_DEVICE_BASE + 0x28)
-/* USB_DEVICE_IN_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
-/*description: Read data address of IN endpoint 0..*/
-#define USB_DEVICE_IN_EP0_RD_ADDR    0x0000007F
-#define USB_DEVICE_IN_EP0_RD_ADDR_M  ((USB_DEVICE_IN_EP0_RD_ADDR_V)<<(USB_DEVICE_IN_EP0_RD_ADDR_S))
-#define USB_DEVICE_IN_EP0_RD_ADDR_V  0x7F
-#define USB_DEVICE_IN_EP0_RD_ADDR_S  9
-/* USB_DEVICE_IN_EP0_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
-/*description: Write data address of IN endpoint 0..*/
-#define USB_DEVICE_IN_EP0_WR_ADDR    0x0000007F
-#define USB_DEVICE_IN_EP0_WR_ADDR_M  ((USB_DEVICE_IN_EP0_WR_ADDR_V)<<(USB_DEVICE_IN_EP0_WR_ADDR_S))
-#define USB_DEVICE_IN_EP0_WR_ADDR_V  0x7F
-#define USB_DEVICE_IN_EP0_WR_ADDR_S  2
-/* USB_DEVICE_IN_EP0_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: State of IN Endpoint 0..*/
-#define USB_DEVICE_IN_EP0_STATE    0x00000003
-#define USB_DEVICE_IN_EP0_STATE_M  ((USB_DEVICE_IN_EP0_STATE_V)<<(USB_DEVICE_IN_EP0_STATE_S))
-#define USB_DEVICE_IN_EP0_STATE_V  0x3
-#define USB_DEVICE_IN_EP0_STATE_S  0
-
-#define USB_DEVICE_IN_EP1_ST_REG          (DR_REG_USB_DEVICE_BASE + 0x2C)
-/* USB_DEVICE_IN_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
-/*description: Read data address of IN endpoint 1..*/
-#define USB_DEVICE_IN_EP1_RD_ADDR    0x0000007F
-#define USB_DEVICE_IN_EP1_RD_ADDR_M  ((USB_DEVICE_IN_EP1_RD_ADDR_V)<<(USB_DEVICE_IN_EP1_RD_ADDR_S))
-#define USB_DEVICE_IN_EP1_RD_ADDR_V  0x7F
-#define USB_DEVICE_IN_EP1_RD_ADDR_S  9
-/* USB_DEVICE_IN_EP1_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
-/*description: Write data address of IN endpoint 1..*/
-#define USB_DEVICE_IN_EP1_WR_ADDR    0x0000007F
-#define USB_DEVICE_IN_EP1_WR_ADDR_M  ((USB_DEVICE_IN_EP1_WR_ADDR_V)<<(USB_DEVICE_IN_EP1_WR_ADDR_S))
-#define USB_DEVICE_IN_EP1_WR_ADDR_V  0x7F
-#define USB_DEVICE_IN_EP1_WR_ADDR_S  2
-/* USB_DEVICE_IN_EP1_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: State of IN Endpoint 1..*/
-#define USB_DEVICE_IN_EP1_STATE    0x00000003
-#define USB_DEVICE_IN_EP1_STATE_M  ((USB_DEVICE_IN_EP1_STATE_V)<<(USB_DEVICE_IN_EP1_STATE_S))
-#define USB_DEVICE_IN_EP1_STATE_V  0x3
-#define USB_DEVICE_IN_EP1_STATE_S  0
-
-#define USB_DEVICE_IN_EP2_ST_REG          (DR_REG_USB_DEVICE_BASE + 0x30)
-/* USB_DEVICE_IN_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
-/*description: Read data address of IN endpoint 2..*/
-#define USB_DEVICE_IN_EP2_RD_ADDR    0x0000007F
-#define USB_DEVICE_IN_EP2_RD_ADDR_M  ((USB_DEVICE_IN_EP2_RD_ADDR_V)<<(USB_DEVICE_IN_EP2_RD_ADDR_S))
-#define USB_DEVICE_IN_EP2_RD_ADDR_V  0x7F
-#define USB_DEVICE_IN_EP2_RD_ADDR_S  9
-/* USB_DEVICE_IN_EP2_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
-/*description: Write data address of IN endpoint 2..*/
-#define USB_DEVICE_IN_EP2_WR_ADDR    0x0000007F
-#define USB_DEVICE_IN_EP2_WR_ADDR_M  ((USB_DEVICE_IN_EP2_WR_ADDR_V)<<(USB_DEVICE_IN_EP2_WR_ADDR_S))
-#define USB_DEVICE_IN_EP2_WR_ADDR_V  0x7F
-#define USB_DEVICE_IN_EP2_WR_ADDR_S  2
-/* USB_DEVICE_IN_EP2_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: State of IN Endpoint 2..*/
-#define USB_DEVICE_IN_EP2_STATE    0x00000003
-#define USB_DEVICE_IN_EP2_STATE_M  ((USB_DEVICE_IN_EP2_STATE_V)<<(USB_DEVICE_IN_EP2_STATE_S))
-#define USB_DEVICE_IN_EP2_STATE_V  0x3
-#define USB_DEVICE_IN_EP2_STATE_S  0
-
-#define USB_DEVICE_IN_EP3_ST_REG          (DR_REG_USB_DEVICE_BASE + 0x34)
-/* USB_DEVICE_IN_EP3_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
-/*description: Read data address of IN endpoint 3..*/
-#define USB_DEVICE_IN_EP3_RD_ADDR    0x0000007F
-#define USB_DEVICE_IN_EP3_RD_ADDR_M  ((USB_DEVICE_IN_EP3_RD_ADDR_V)<<(USB_DEVICE_IN_EP3_RD_ADDR_S))
-#define USB_DEVICE_IN_EP3_RD_ADDR_V  0x7F
-#define USB_DEVICE_IN_EP3_RD_ADDR_S  9
-/* USB_DEVICE_IN_EP3_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
-/*description: Write data address of IN endpoint 3..*/
-#define USB_DEVICE_IN_EP3_WR_ADDR    0x0000007F
-#define USB_DEVICE_IN_EP3_WR_ADDR_M  ((USB_DEVICE_IN_EP3_WR_ADDR_V)<<(USB_DEVICE_IN_EP3_WR_ADDR_S))
-#define USB_DEVICE_IN_EP3_WR_ADDR_V  0x7F
-#define USB_DEVICE_IN_EP3_WR_ADDR_S  2
-/* USB_DEVICE_IN_EP3_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: State of IN Endpoint 3..*/
-#define USB_DEVICE_IN_EP3_STATE    0x00000003
-#define USB_DEVICE_IN_EP3_STATE_M  ((USB_DEVICE_IN_EP3_STATE_V)<<(USB_DEVICE_IN_EP3_STATE_S))
-#define USB_DEVICE_IN_EP3_STATE_V  0x3
-#define USB_DEVICE_IN_EP3_STATE_S  0
-
-#define USB_DEVICE_OUT_EP0_ST_REG          (DR_REG_USB_DEVICE_BASE + 0x38)
-/* USB_DEVICE_OUT_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
-/*description: Read data address of OUT endpoint 0..*/
-#define USB_DEVICE_OUT_EP0_RD_ADDR    0x0000007F
-#define USB_DEVICE_OUT_EP0_RD_ADDR_M  ((USB_DEVICE_OUT_EP0_RD_ADDR_V)<<(USB_DEVICE_OUT_EP0_RD_ADDR_S))
-#define USB_DEVICE_OUT_EP0_RD_ADDR_V  0x7F
-#define USB_DEVICE_OUT_EP0_RD_ADDR_S  9
-/* USB_DEVICE_OUT_EP0_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
-/*description: Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
- detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0..*/
-#define USB_DEVICE_OUT_EP0_WR_ADDR    0x0000007F
-#define USB_DEVICE_OUT_EP0_WR_ADDR_M  ((USB_DEVICE_OUT_EP0_WR_ADDR_V)<<(USB_DEVICE_OUT_EP0_WR_ADDR_S))
-#define USB_DEVICE_OUT_EP0_WR_ADDR_V  0x7F
-#define USB_DEVICE_OUT_EP0_WR_ADDR_S  2
-/* USB_DEVICE_OUT_EP0_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: State of OUT Endpoint 0..*/
-#define USB_DEVICE_OUT_EP0_STATE    0x00000003
-#define USB_DEVICE_OUT_EP0_STATE_M  ((USB_DEVICE_OUT_EP0_STATE_V)<<(USB_DEVICE_OUT_EP0_STATE_S))
-#define USB_DEVICE_OUT_EP0_STATE_V  0x3
-#define USB_DEVICE_OUT_EP0_STATE_S  0
-
-#define USB_DEVICE_OUT_EP1_ST_REG          (DR_REG_USB_DEVICE_BASE + 0x3C)
-/* USB_DEVICE_OUT_EP1_REC_DATA_CNT : RO ;bitpos:[22:16] ;default: 7'd0 ; */
-/*description: Data count in OUT endpoint 1 when one packet is received..*/
-#define USB_DEVICE_OUT_EP1_REC_DATA_CNT    0x0000007F
-#define USB_DEVICE_OUT_EP1_REC_DATA_CNT_M  ((USB_DEVICE_OUT_EP1_REC_DATA_CNT_V)<<(USB_DEVICE_OUT_EP1_REC_DATA_CNT_S))
-#define USB_DEVICE_OUT_EP1_REC_DATA_CNT_V  0x7F
-#define USB_DEVICE_OUT_EP1_REC_DATA_CNT_S  16
-/* USB_DEVICE_OUT_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
-/*description: Read data address of OUT endpoint 1..*/
-#define USB_DEVICE_OUT_EP1_RD_ADDR    0x0000007F
-#define USB_DEVICE_OUT_EP1_RD_ADDR_M  ((USB_DEVICE_OUT_EP1_RD_ADDR_V)<<(USB_DEVICE_OUT_EP1_RD_ADDR_S))
-#define USB_DEVICE_OUT_EP1_RD_ADDR_V  0x7F
-#define USB_DEVICE_OUT_EP1_RD_ADDR_S  9
-/* USB_DEVICE_OUT_EP1_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
-/*description: Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
- detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1..*/
-#define USB_DEVICE_OUT_EP1_WR_ADDR    0x0000007F
-#define USB_DEVICE_OUT_EP1_WR_ADDR_M  ((USB_DEVICE_OUT_EP1_WR_ADDR_V)<<(USB_DEVICE_OUT_EP1_WR_ADDR_S))
-#define USB_DEVICE_OUT_EP1_WR_ADDR_V  0x7F
-#define USB_DEVICE_OUT_EP1_WR_ADDR_S  2
-/* USB_DEVICE_OUT_EP1_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: State of OUT Endpoint 1..*/
-#define USB_DEVICE_OUT_EP1_STATE    0x00000003
-#define USB_DEVICE_OUT_EP1_STATE_M  ((USB_DEVICE_OUT_EP1_STATE_V)<<(USB_DEVICE_OUT_EP1_STATE_S))
-#define USB_DEVICE_OUT_EP1_STATE_V  0x3
-#define USB_DEVICE_OUT_EP1_STATE_S  0
-
-#define USB_DEVICE_OUT_EP2_ST_REG          (DR_REG_USB_DEVICE_BASE + 0x40)
-/* USB_DEVICE_OUT_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
-/*description: Read data address of OUT endpoint 2..*/
-#define USB_DEVICE_OUT_EP2_RD_ADDR    0x0000007F
-#define USB_DEVICE_OUT_EP2_RD_ADDR_M  ((USB_DEVICE_OUT_EP2_RD_ADDR_V)<<(USB_DEVICE_OUT_EP2_RD_ADDR_S))
-#define USB_DEVICE_OUT_EP2_RD_ADDR_V  0x7F
-#define USB_DEVICE_OUT_EP2_RD_ADDR_S  9
-/* USB_DEVICE_OUT_EP2_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
-/*description: Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
- detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2..*/
-#define USB_DEVICE_OUT_EP2_WR_ADDR    0x0000007F
-#define USB_DEVICE_OUT_EP2_WR_ADDR_M  ((USB_DEVICE_OUT_EP2_WR_ADDR_V)<<(USB_DEVICE_OUT_EP2_WR_ADDR_S))
-#define USB_DEVICE_OUT_EP2_WR_ADDR_V  0x7F
-#define USB_DEVICE_OUT_EP2_WR_ADDR_S  2
-/* USB_DEVICE_OUT_EP2_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: State of OUT Endpoint 2..*/
-#define USB_DEVICE_OUT_EP2_STATE    0x00000003
-#define USB_DEVICE_OUT_EP2_STATE_M  ((USB_DEVICE_OUT_EP2_STATE_V)<<(USB_DEVICE_OUT_EP2_STATE_S))
-#define USB_DEVICE_OUT_EP2_STATE_V  0x3
-#define USB_DEVICE_OUT_EP2_STATE_S  0
-
-#define USB_DEVICE_MISC_CONF_REG          (DR_REG_USB_DEVICE_BASE + 0x44)
-/* USB_DEVICE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1'h1: Force clock on for register. 1'h0: Support clock only when application wri
-tes registers..*/
-#define USB_DEVICE_CLK_EN    (BIT(0))
-#define USB_DEVICE_CLK_EN_M  (BIT(0))
-#define USB_DEVICE_CLK_EN_V  0x1
-#define USB_DEVICE_CLK_EN_S  0
-
-#define USB_DEVICE_MEM_CONF_REG          (DR_REG_USB_DEVICE_BASE + 0x48)
-/* USB_DEVICE_USB_MEM_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: 1: Force clock on for usb memory..*/
-#define USB_DEVICE_USB_MEM_CLK_EN    (BIT(1))
-#define USB_DEVICE_USB_MEM_CLK_EN_M  (BIT(1))
-#define USB_DEVICE_USB_MEM_CLK_EN_V  0x1
-#define USB_DEVICE_USB_MEM_CLK_EN_S  1
-/* USB_DEVICE_USB_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1: power down usb memory..*/
-#define USB_DEVICE_USB_MEM_PD    (BIT(0))
-#define USB_DEVICE_USB_MEM_PD_M  (BIT(0))
-#define USB_DEVICE_USB_MEM_PD_V  0x1
-#define USB_DEVICE_USB_MEM_PD_S  0
-
-#define USB_DEVICE_DATE_REG          (DR_REG_USB_DEVICE_BASE + 0x80)
-/* USB_DEVICE_DATE : R/W ;bitpos:[31:0] ;default: 32'h2011190 ; */
-/*description: register version..*/
-#define USB_DEVICE_DATE    0xFFFFFFFF
-#define USB_DEVICE_DATE_M  ((USB_DEVICE_DATE_V)<<(USB_DEVICE_DATE_S))
-#define USB_DEVICE_DATE_V  0xFFFFFFFF
-#define USB_DEVICE_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_USB_DEVICE_REG_H_ */

components/soc/esp32s3/include/soc/usb_serial_jtag_reg.h

@@ -1,18 +1,9 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
-//
+#pragma once
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_USB_DEVICE_REG_H_
-#define _SOC_USB_DEVICE_REG_H_
 
 
 #ifdef __cplusplus
@@ -20,7 +11,7 @@ extern "C" {
 #endif
 #include "soc.h"
 
-#define USB_SERIAL_JTAG_EP1_REG          (DR_REG_USB_DEVICE_BASE + 0x0)
+#define USB_SERIAL_JTAG_EP1_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
 /* USB_SERIAL_JTAG_RDWR_BYTE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
 /*description: Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DE
 VICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into
@@ -32,7 +23,7 @@ ived, then read data from UART Rx FIFO..*/
 #define USB_SERIAL_JTAG_RDWR_BYTE_V  0xFF
 #define USB_SERIAL_JTAG_RDWR_BYTE_S  0
 
-#define USB_SERIAL_JTAG_EP1_CONF_REG          (DR_REG_USB_DEVICE_BASE + 0x4)
+#define USB_SERIAL_JTAG_EP1_CONF_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
 /* USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO ;bitpos:[2] ;default: 1'b0 ; */
 /*description: 1'b1: Indicate there is data in UART Rx FIFO..*/
 #define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
@@ -54,7 +45,7 @@ USB Host..*/
 #define USB_SERIAL_JTAG_WR_DONE_V  0x1
 #define USB_SERIAL_JTAG_WR_DONE_S  0
 
-#define USB_SERIAL_JTAG_INT_RAW_REG          (DR_REG_USB_DEVICE_BASE + 0x8)
+#define USB_SERIAL_JTAG_INT_RAW_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
 /* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
 /*description: The raw interrupt bit turns to high level when OUT endpoint 2 received packet wi
 th zero palyload..*/
@@ -133,7 +124,7 @@ oint 2 of JTAG..*/
 #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x1
 #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
 
-#define USB_SERIAL_JTAG_INT_ST_REG          (DR_REG_USB_DEVICE_BASE + 0xC)
+#define USB_SERIAL_JTAG_INT_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0xC)
 /* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
 /*description: The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interru
 pt..*/
@@ -211,7 +202,7 @@ t..*/
 #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x1
 #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
 
-#define USB_SERIAL_JTAG_INT_ENA_REG          (DR_REG_USB_DEVICE_BASE + 0x10)
+#define USB_SERIAL_JTAG_INT_ENA_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
 /* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
 /*description: The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/
 #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
@@ -285,7 +276,7 @@ t..*/
 #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x1
 #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
 
-#define USB_SERIAL_JTAG_INT_CLR_REG          (DR_REG_USB_DEVICE_BASE + 0x14)
+#define USB_SERIAL_JTAG_INT_CLR_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
 /* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
 /*description: Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/
 #define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
@@ -359,7 +350,7 @@ t..*/
 #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x1
 #define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
 
-#define USB_SERIAL_JTAG_CONF0_REG          (DR_REG_USB_DEVICE_BASE + 0x18)
+#define USB_SERIAL_JTAG_CONF0_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
 /* USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
 /*description: Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disc
 onnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input thr
@@ -453,7 +444,7 @@ ough GPIO Matrix..*/
 #define USB_SERIAL_JTAG_PHY_SEL_V  0x1
 #define USB_SERIAL_JTAG_PHY_SEL_S  0
 
-#define USB_SERIAL_JTAG_TEST_REG          (DR_REG_USB_DEVICE_BASE + 0x1C)
+#define USB_SERIAL_JTAG_TEST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x1C)
 /* USB_SERIAL_JTAG_TEST_RX_DM : RO ;bitpos:[6] ;default: 1'b0 ; */
 /*description: USB D- rx value in test.*/
 #define USB_SERIAL_JTAG_TEST_RX_DM    (BIT(6))
@@ -497,7 +488,7 @@ ough GPIO Matrix..*/
 #define USB_SERIAL_JTAG_TEST_ENABLE_V  0x1
 #define USB_SERIAL_JTAG_TEST_ENABLE_S  0
 
-#define USB_SERIAL_JTAG_JFIFO_ST_REG          (DR_REG_USB_DEVICE_BASE + 0x20)
+#define USB_SERIAL_JTAG_JFIFO_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
 /* USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W ;bitpos:[9] ;default: 1'b0 ; */
 /*description: Write 1 to reset JTAG out fifo..*/
 #define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
@@ -547,7 +538,7 @@ ough GPIO Matrix..*/
 #define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x3
 #define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
 
-#define USB_SERIAL_JTAG_FRAM_NUM_REG          (DR_REG_USB_DEVICE_BASE + 0x24)
+#define USB_SERIAL_JTAG_FRAM_NUM_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
 /* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO ;bitpos:[10:0] ;default: 11'd0 ; */
 /*description: Frame index of received SOF frame..*/
 #define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FF
@@ -555,7 +546,7 @@ ough GPIO Matrix..*/
 #define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x7FF
 #define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
 
-#define USB_SERIAL_JTAG_IN_EP0_ST_REG          (DR_REG_USB_DEVICE_BASE + 0x28)
+#define USB_SERIAL_JTAG_IN_EP0_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
 /* USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
 /*description: Read data address of IN endpoint 0..*/
 #define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007F
@@ -575,7 +566,7 @@ ough GPIO Matrix..*/
 #define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x3
 #define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
 
-#define USB_SERIAL_JTAG_IN_EP1_ST_REG          (DR_REG_USB_DEVICE_BASE + 0x2C)
+#define USB_SERIAL_JTAG_IN_EP1_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x2C)
 /* USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
 /*description: Read data address of IN endpoint 1..*/
 #define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007F
@@ -595,7 +586,7 @@ ough GPIO Matrix..*/
 #define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x3
 #define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
 
-#define USB_SERIAL_JTAG_IN_EP2_ST_REG          (DR_REG_USB_DEVICE_BASE + 0x30)
+#define USB_SERIAL_JTAG_IN_EP2_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
 /* USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
 /*description: Read data address of IN endpoint 2..*/
 #define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007F
@@ -615,7 +606,7 @@ ough GPIO Matrix..*/
 #define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x3
 #define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
 
-#define USB_SERIAL_JTAG_IN_EP3_ST_REG          (DR_REG_USB_DEVICE_BASE + 0x34)
+#define USB_SERIAL_JTAG_IN_EP3_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
 /* USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
 /*description: Read data address of IN endpoint 3..*/
 #define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007F
@@ -635,7 +626,7 @@ ough GPIO Matrix..*/
 #define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x3
 #define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
 
-#define USB_SERIAL_JTAG_OUT_EP0_ST_REG          (DR_REG_USB_DEVICE_BASE + 0x38)
+#define USB_SERIAL_JTAG_OUT_EP0_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
 /* USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
 /*description: Read data address of OUT endpoint 0..*/
 #define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007F
@@ -656,7 +647,7 @@ ough GPIO Matrix..*/
 #define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x3
 #define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
 
-#define USB_SERIAL_JTAG_OUT_EP1_ST_REG          (DR_REG_USB_DEVICE_BASE + 0x3C)
+#define USB_SERIAL_JTAG_OUT_EP1_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x3C)
 /* USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO ;bitpos:[22:16] ;default: 7'd0 ; */
 /*description: Data count in OUT endpoint 1 when one packet is received..*/
 #define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007F
@@ -683,7 +674,7 @@ ough GPIO Matrix..*/
 #define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x3
 #define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
 
-#define USB_SERIAL_JTAG_OUT_EP2_ST_REG          (DR_REG_USB_DEVICE_BASE + 0x40)
+#define USB_SERIAL_JTAG_OUT_EP2_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
 /* USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
 /*description: Read data address of OUT endpoint 2..*/
 #define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007F
@@ -704,7 +695,7 @@ ough GPIO Matrix..*/
 #define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x3
 #define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
 
-#define USB_SERIAL_JTAG_MISC_CONF_REG          (DR_REG_USB_DEVICE_BASE + 0x44)
+#define USB_SERIAL_JTAG_MISC_CONF_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
 /* USB_SERIAL_JTAG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
 /*description: 1'h1: Force clock on for register. 1'h0: Support clock only when application wri
 tes registers..*/
@@ -713,7 +704,7 @@ tes registers..*/
 #define USB_SERIAL_JTAG_CLK_EN_V  0x1
 #define USB_SERIAL_JTAG_CLK_EN_S  0
 
-#define USB_SERIAL_JTAG_MEM_CONF_REG          (DR_REG_USB_DEVICE_BASE + 0x48)
+#define USB_SERIAL_JTAG_MEM_CONF_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
 /* USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
 /*description: 1: Force clock on for usb memory..*/
 #define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
@@ -727,7 +718,7 @@ tes registers..*/
 #define USB_SERIAL_JTAG_USB_MEM_PD_V  0x1
 #define USB_SERIAL_JTAG_USB_MEM_PD_S  0
 
-#define USB_SERIAL_JTAG_DATE_REG          (DR_REG_USB_DEVICE_BASE + 0x80)
+#define USB_SERIAL_JTAG_DATE_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
 /* USB_SERIAL_JTAG_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101200 ; */
 /*description: register version..*/
 #define USB_SERIAL_JTAG_DATE    0xFFFFFFFF
@@ -739,7 +730,3 @@ tes registers..*/
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_USB_DEVICE_REG_H_ */

components/spi_flash/esp_flash_spi_init.c

@@ -144,6 +144,9 @@ static IRAM_ATTR NOINLINE_ATTR void cs_initialize(esp_flash_t *chip, const esp_f
     int spics_out = spi_periph_signal[config->host_id].spics_out[cs_id];
     int spics_func = spi_periph_signal[config->host_id].func;
     uint32_t iomux_reg = GPIO_PIN_MUX_REG[cs_io_num];
+    gpio_hal_context_t gpio_hal = {
+        .dev = GPIO_HAL_GET_HW(GPIO_PORT_0)
+    };
 
     //To avoid the panic caused by flash data line conflicts during cs line
     //initialization, disable the cache temporarily
@@ -152,16 +155,8 @@ static IRAM_ATTR NOINLINE_ATTR void cs_initialize(esp_flash_t *chip, const esp_f
     if (use_iomux) {
         gpio_hal_iomux_func_sel(iomux_reg, spics_func);
     } else {
-#if SOC_GPIO_PIN_COUNT <= 32
+        gpio_hal_output_enable(&gpio_hal, cs_io_num);
-        GPIO.enable_w1ts.val = (0x1 << cs_io_num);
+        gpio_hal_od_disable(&gpio_hal, cs_io_num);
-#else
-        if (cs_io_num < 32) {
-            GPIO.enable_w1ts = (0x1 << cs_io_num);
-        } else {
-            GPIO.enable1_w1ts.data = (0x1 << (cs_io_num - 32));
-        }
-#endif
-        GPIO.pin[cs_io_num].pad_driver = 0;
         esp_rom_gpio_connect_out_signal(cs_io_num, spics_out, false, false);
         if (cs_id == 0) {
             esp_rom_gpio_connect_in_signal(cs_io_num, spics_in, false);

examples/system/deep_sleep/main/Kconfig.projbuild

@@ -33,16 +33,18 @@ menu "Example Configuration"
         default y
         depends on SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
         help
-            This option enables wake up from GPIO, only GPIO0~5 can be used to wake up. Be aware that if you use low
+            This option enables wake up from GPIO. Be aware that if you use low level to trigger wakeup, we strongly
-            level to trigger wakeup, we strongly recommand you to connect external pull-up resistance.
+            recommand you to connect external pull-up resistance.
 
     menu "GPIO wakeup configuration"
         visible if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
 
         config EXAMPLE_GPIO_WAKEUP_PIN
             int "Enable wakeup from GPIO"
-            default 0
+            default 0 if !IDF_TARGET_ESP32H2_BETA_VERSION_2
-            range 0 5
+            default 7 if IDF_TARGET_ESP32H2_BETA_VERSION_2
+            range 0 5 if !IDF_TARGET_ESP32H2_BETA_VERSION_2
+            range 7 12 if IDF_TARGET_ESP32H2_BETA_VERSION_2
 
         config EXAMPLE_GPIO_WAKEUP_HIGH_LEVEL
             bool "Enable GPIO high-level wakeup"

tools/ci/check_copyright_ignore.txt

@@ -1444,7 +1444,6 @@ components/soc/esp32h2/include/soc/fe_reg.h
 components/soc/esp32h2/include/soc/gpio_pins.h
 components/soc/esp32h2/include/soc/gpio_sd_reg.h
 components/soc/esp32h2/include/soc/gpio_sd_struct.h
-components/soc/esp32h2/include/soc/gpio_struct.h
 components/soc/esp32h2/include/soc/hwcrypto_reg.h
 components/soc/esp32h2/include/soc/interrupt_reg.h
 components/soc/esp32h2/include/soc/ledc_reg.h
@@ -1647,10 +1646,8 @@ components/soc/esp32s3/include/soc/uart_reg.h
 components/soc/esp32s3/include/soc/uart_struct.h
 components/soc/esp32s3/include/soc/uhci_reg.h
 components/soc/esp32s3/include/soc/uhci_struct.h
-components/soc/esp32s3/include/soc/usb_device_reg.h
 components/soc/esp32s3/include/soc/usb_pins.h
 components/soc/esp32s3/include/soc/usb_reg.h
-components/soc/esp32s3/include/soc/usb_serial_jtag_reg.h
 components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h
 components/soc/esp32s3/include/soc/usb_struct.h
 components/soc/esp32s3/include/soc/usb_types.h