Merge branch 'bugfix/s3_sleep_voltage_enable_ulp' into 'master'

ulp: re-enable support, example and CI jobs for S2 and S3

Closes IDF-4514, IDFGH-7075, and IDFGH-7531

See merge request espressif/esp-idf!18308

.gitlab/ci/target-test.yml

@@ -211,6 +211,26 @@ example_test_pytest_esp32c3_flash_encryption:
     TARGET: ESP32C3
     ENV_MARKER: flash_encryption
 
+example_test_pytest_esp32s2_deepsleep: # Temp tag, will be removed IDF-5213
+  extends:
+    - .pytest_examples_dir_template
+    - .rules:test:example_test-esp32s2
+  needs:
+    - build_pytest_examples_esp32s2
+  variables:
+    TARGET: ESP32S2
+    ENV_MARKER: deepsleep_temp_tag
+
+example_test_pytest_esp32s3_deepsleep: # Temp tag, will be removed IDF-5213
+  extends:
+    - .pytest_examples_dir_template
+    - .rules:test:example_test-esp32s3
+  needs:
+    - build_pytest_examples_esp32s3
+  variables:
+    TARGET: ESP32S3
+    ENV_MARKER: deepsleep_temp_tag
+
 .pytest_components_dir_template:
   extends: .pytest_template
   variables:

components/ulp/ulp_fsm/ulp.c

@@ -42,12 +42,6 @@ static const char* TAG = "ulp";
 
 esp_err_t ulp_run(uint32_t entry_point)
 {
-#if CONFIG_IDF_TARGET_ESP32S3
-    ESP_LOGE(TAG, "ULP temporarily unsupported on ESP32-S3, running sleep + ULP risks causing permanent damage to chip");
-    abort();
-// Fix in-progress: DIG-160
-#endif //CONFIG_IDF_TARGET_ESP32S3
-
 #if CONFIG_IDF_TARGET_ESP32
     // disable ULP timer
     CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);

components/ulp/ulp_riscv/ulp_riscv.c

@@ -48,15 +48,12 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg)
 {
     esp_err_t ret = ESP_OK;
 
-#if CONFIG_IDF_TARGET_ESP32S3
-    ESP_LOGE(TAG, "ULP temporarily unsupported on ESP32-S3, running sleep + ULP risks causing permanent damage to chip");
-    abort();
-// Fix in-progress: DIG-160
-#endif //CONFIG_IDF_TARGET_ESP32S3
 
 #if CONFIG_IDF_TARGET_ESP32S2
-    /* Set RTC_CNTL_COCPU_SHUT_RESET_EN to make sure COCPU is reset after halt. */
+    /* Reset COCPU when power on. */
     SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
+    esp_rom_delay_us(20);
+    CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
 
      /* The coprocessor cpu trap signal doesnt have a stable reset value,
        force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
@@ -75,14 +72,12 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg)
     ret = ulp_riscv_config_wakeup_source(cfg->wakeup_source);
 
 #elif CONFIG_IDF_TARGET_ESP32S3
-    /* The coprocessor cpu trap signal doesnt have a stable reset value,
+    /* Reset COCPU when power on. */
-       force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
     SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
+    SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
     esp_rom_delay_us(20);
     CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
-
+    CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
-    /* Set RTC_CNTL_COCPU_SHUT_RESET_EN to make sure COCPU is reset after halt. */
-    SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
 
     /* Disable ULP timer */
     CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);

components/ulp/ulp_riscv/ulp_riscv_utils.c

@@ -13,7 +13,7 @@
 void ulp_riscv_rescue_from_monitor(void)
 {
     /* Rescue RISCV from monitor state. */
-    CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE);
+    CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE | RTC_CNTL_COCPU_SHUT_RESET_EN);
 }
 
 void ulp_riscv_wakeup_main_processor(void)

examples/system/deep_sleep/README.md

@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-S2 | ESP32-C3 |
+| Supported Targets | ESP32 | ESP32-S2 | ESP32-S3 | ESP32-C3 |
-| ----------------- | ----- | -------- | -------- |
+| ----------------- | ----- | -------- | -------- | -------- |
 
 # Deep Sleep Example
 

examples/system/deep_sleep/pytest_deep_sleep.py

@@ -9,15 +9,8 @@ from pytest_embedded import Dut
 
 touch_wake_up_support = ['esp32', 'esp32s2']
 
-CONFIGS = [
-    pytest.param('esp32_singlecore', marks=[pytest.mark.esp32]),
-    pytest.param('generic', marks=[pytest.mark.esp32, pytest.mark.esp32c3]),  # Disabled for now: IDF-4801
-]
 
-
+def deep_sleep_test(dut: Dut) -> None:
-@pytest.mark.parametrize('config', CONFIGS, indirect=True)
-@pytest.mark.generic
-def test_deep_sleep(dut: Dut) -> None:
 
     def expect_enable_deep_sleep_touch() -> None:
         # different targets configure different wake pin(s)
@@ -64,3 +57,26 @@ def test_deep_sleep(dut: Dut) -> None:
     # Check that it measured 2xxxxms in deep sleep, i.e at least 20 seconds:
     dut.expect(r'Wake up from timer. Time spent in deep sleep: 2\d{4}ms', timeout=2)
     expect_enable_deep_sleep()
+
+
+CONFIGS = [
+    pytest.param('esp32_singlecore', marks=[pytest.mark.esp32]),
+    pytest.param('basic', marks=[pytest.mark.esp32, pytest.mark.esp32c3]),
+]
+
+
+@pytest.mark.parametrize('config', CONFIGS, indirect=True)
+@pytest.mark.generic
+def test_deep_sleep(dut: Dut) -> None:
+    deep_sleep_test(dut)
+
+
+CONFIGS_S2_S3 = [
+    pytest.param('basic', marks=[pytest.mark.esp32s2, pytest.mark.esp32s3]),  # S2/S3 runner on isolated runners for now, IDF-XX
+]
+
+
+@pytest.mark.parametrize('config', CONFIGS_S2_S3, indirect=True)
+@pytest.mark.deepsleep_temp_tag
+def test_deep_sleep_s2_s3(dut: Dut) -> None:
+    deep_sleep_test(dut)

examples/system/ulp_fsm/ulp/CMakeLists.txt

@@ -2,11 +2,5 @@
 # in this exact order for cmake to work correctly
 cmake_minimum_required(VERSION 3.16)
 
-if(IDF_TARGET STREQUAL "esp32s3")
-    #IDF-4514
-    message(FATAL_ERROR "\n **** ERROR **** : DO NOT BUILD AND RUN THIS APP ON ESP32-S3 AS IT MAY BRICK YOUR DEVICE")
-    return()
-endif()
-
 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
 project(ulp_example)

examples/system/ulp_riscv/ds18b20_onewire/CMakeLists.txt

@@ -2,11 +2,5 @@
 # in this exact order for cmake to work correctly
 cmake_minimum_required(VERSION 3.16)
 
-if(NOT IDF_TARGET STREQUAL "esp32s2")
-    #IDF-4514
-    message(FATAL_ERROR "DO NOT BUILD THIS APP FOR ANY TARGET OTHER THAN ESP32-S2 OTHERWISE YOU MAY BRICK YOUR DEVICE")
-    return()
-endif()
-
 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
 project(ulp_riscv_ds18b20_example)

examples/system/ulp_riscv/ds18b20_onewire/sdkconfig.defaults

@@ -1,4 +1,3 @@
-CONFIG_IDF_TARGET="esp32s2"
 # Enable ULP
 CONFIG_ULP_COPROC_ENABLED=y
 CONFIG_ULP_COPROC_RISCV=y

examples/system/ulp_riscv/gpio/CMakeLists.txt

@@ -2,11 +2,5 @@
 # in this exact order for cmake to work correctly
 cmake_minimum_required(VERSION 3.16)
 
-if(NOT IDF_TARGET STREQUAL "esp32s2")
-    #IDF-4514
-    message(FATAL_ERROR "DO NOT BUILD THIS APP FOR ANY TARGET OTHER THAN ESP32-S2 OTHERWISE YOU MAY BRICK YOUR DEVICE")
-    return()
-endif()
-
 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
 project(ulp_riscv_example)

examples/system/ulp_riscv/gpio/README.md

@@ -1,5 +1,5 @@
-| Supported Targets | ESP32-S2 |
+| Supported Targets | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- |
+| ----------------- | -------- | -------- |
 
 # ULP-RISC-V simple example with GPIO Polling:
 

examples/system/ulp_riscv/gpio/pytest_ulp_riscv_gpio.py

@@ -1,18 +1,24 @@
 # SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: CC0-1.0
 
+import time
+
 import pexpect
 import pytest
 from pytest_embedded import Dut
 
 
 @pytest.mark.esp32s2
-@pytest.mark.generic
+@pytest.mark.esp32s3
+@pytest.mark.deepsleep_temp_tag
 def test_ulp_riscv_gpio(dut: Dut) -> None:
 
     dut.expect_exact('Not a ULP-RISC-V wakeup, initializing it!')
     dut.expect_exact('Entering in deep sleep')
 
+    # Give the chip time to enter deepsleep
+    time.sleep(1)
+
     # Run two times to make sure device sleep
     # and wake up properly
     for i in range(0, 2):

examples/system/ulp_riscv/gpio/sdkconfig.defaults

@@ -1,4 +1,3 @@
-CONFIG_IDF_TARGET="esp32s2"
 # Enable ULP
 CONFIG_ULP_COPROC_ENABLED=y
 CONFIG_ULP_COPROC_RISCV=y

examples/system/ulp_riscv/gpio_interrupt/CMakeLists.txt

@@ -2,11 +2,5 @@
 # in this exact order for cmake to work correctly
 cmake_minimum_required(VERSION 3.16)
 
-if(NOT IDF_TARGET STREQUAL "esp32s2")
-    #IDF-4514
-    message(FATAL_ERROR "DO NOT BUILD THIS APP FOR ANY TARGET OTHER THAN ESP32-S2 OTHERWISE YOU MAY BRICK YOUR DEVICE")
-    return()
-endif()
-
 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
 project(ulp_riscv_example)

examples/system/ulp_riscv/gpio_interrupt/README.md

@@ -1,6 +1,5 @@
-| Supported Targets | ESP32-S2 |
+| Supported Targets | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- |
+| ----------------- | -------- | -------- |
-
 # ULP-RISC-V simple example with GPIO Interrupt:
 
 This example demonstrates how to program the ULP-RISC-V coprocessor to wake up from a RTC IO interrupt, instead of waking periodically from the ULP timer.

pytest.ini

@@ -44,7 +44,7 @@ markers =
   ethernet_flash_8m: ethernet runner with 8mb flash
   wifi: wifi runner
   wifi_bt: wifi runner with bluetooth
-  deepsleep: deepsleep runners
+  deepsleep_temp_tag: temporary env for running potentially harmfull deepsleep related tests
 
   # multi-dut markers
   multi_dut_generic: tests should be run on generic runners, at least have two duts connected.