diff --git a/components/driver/gpio/gpio.c b/components/driver/gpio/gpio.c index f5644c3917..5af1be2d54 100644 --- a/components/driver/gpio/gpio.c +++ b/components/driver/gpio/gpio.c @@ -927,7 +927,7 @@ esp_err_t gpio_sleep_pupd_config_unapply(gpio_num_t gpio_num) #if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP esp_err_t gpio_deep_sleep_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type) { - if (!gpio_hal_is_valid_deepsleep_wakeup_gpio(gpio_num)) { + if (!GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num)) { ESP_LOGE(GPIO_TAG, "GPIO %d does not support deep sleep wakeup", gpio_num); return ESP_ERR_INVALID_ARG; } @@ -946,7 +946,7 @@ esp_err_t gpio_deep_sleep_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t int esp_err_t gpio_deep_sleep_wakeup_disable(gpio_num_t gpio_num) { - if (!gpio_hal_is_valid_deepsleep_wakeup_gpio(gpio_num)) { + if (!GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num)) { ESP_LOGE(GPIO_TAG, "GPIO %d does not support deep sleep wakeup", gpio_num); return ESP_ERR_INVALID_ARG; } diff --git a/components/driver/gpio/rtc_io.c b/components/driver/gpio/rtc_io.c index 0920b0e729..08eb80b774 100644 --- a/components/driver/gpio/rtc_io.c +++ b/components/driver/gpio/rtc_io.c @@ -226,6 +226,8 @@ bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num) { #if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED return (gpio_num < GPIO_PIN_COUNT && rtc_io_num_map[gpio_num] >= 0); +#elif CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-6027 + return (gpio_num >= 0 && gpio_num < 8); #else return false; #endif diff --git a/components/driver/test_apps/gpio/main/test_gpio.c b/components/driver/test_apps/gpio/main/test_gpio.c index 4fcb33db07..981912918b 100644 --- a/components/driver/test_apps/gpio/main/test_gpio.c +++ b/components/driver/test_apps/gpio/main/test_gpio.c @@ -844,6 +844,7 @@ TEST_CASE("GPIO_USB_DP_pin_pullup_disable_test", "[gpio]") } #endif //SOC_USB_SERIAL_JTAG_SUPPORTED +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6) // TODO: IDF-5348 Remove when light sleep is supported on ESP32C6 // Ignored in CI because it needs manually connect TEST_GPIO_INPUT_LEVEL_LOW_PIN to 3.3v to wake up from light sleep TEST_CASE_CI_IGNORE("GPIO_light_sleep_wake_up_test", "[gpio]") { @@ -860,3 +861,4 @@ TEST_CASE_CI_IGNORE("GPIO_light_sleep_wake_up_test", "[gpio]") printf("Waked up from light sleep\n"); TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_GPIO); } +#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6) diff --git a/components/driver/test_apps/gpio/main/test_gpio.h b/components/driver/test_apps/gpio/main/test_gpio.h index 6ab38136ea..5d437c202d 100644 --- a/components/driver/test_apps/gpio/main/test_gpio.h +++ b/components/driver/test_apps/gpio/main/test_gpio.h @@ -31,12 +31,7 @@ extern "C" { #define TEST_GPIO_EXT_IN_IO (21) #define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1) #define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC208_IDX) -#elif CONFIG_IDF_TARGET_ESP32C3 -#define TEST_GPIO_EXT_OUT_IO (2) -#define TEST_GPIO_EXT_IN_IO (3) -#define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1) -#define TEST_GPIO_SIGNAL_IDX (SIG_IN_FUNC97_IDX) -#elif CONFIG_IDF_TARGET_ESP32C2 +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 #define TEST_GPIO_EXT_OUT_IO (2) #define TEST_GPIO_EXT_IN_IO (3) #define TEST_GPIO_INPUT_LEVEL_LOW_PIN (1) diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 3a6b94b3c1..39b6a8ecbb 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -988,7 +988,7 @@ touch_pad_t esp_sleep_get_touchpad_wakeup_status(void) bool esp_sleep_is_valid_wakeup_gpio(gpio_num_t gpio_num) { -#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED +#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED || CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-6027 C6 IO0-7 meet both conditions here return RTC_GPIO_IS_VALID_GPIO(gpio_num); #else return GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num); diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 88d2abeade..606a4a452d 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -529,6 +529,8 @@ void IRAM_ATTR call_start_cpu0(void) #if SOC_RTCIO_HOLD_SUPPORTED rtcio_hal_unhold_all(); +#elif CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-6027 + CLEAR_PERI_REG_MASK(LP_AON_GPIO_HOLD0_REG, 0xFF); #else gpio_hal_force_unhold_all(); #endif diff --git a/components/hal/esp32c3/include/hal/gpio_ll.h b/components/hal/esp32c3/include/hal/gpio_ll.h index fae5f48ca5..53eb2e40b4 100644 --- a/components/hal/esp32c3/include/hal/gpio_ll.h +++ b/components/hal/esp32c3/include/hal/gpio_ll.h @@ -254,7 +254,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num) static inline __attribute__((always_inline)) void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func) { // Disable USB Serial JTAG if pins 18 or pins 19 needs to select an IOMUX function - if (gpio_num == 18 || gpio_num == 19) { + if (gpio_num == USB_DM_GPIO_NUM || gpio_num == USB_DP_GPIO_NUM) { CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); } PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func); diff --git a/components/hal/esp32c6/include/hal/gpio_ll.h b/components/hal/esp32c6/include/hal/gpio_ll.h index 8232384afe..de9a174f7f 100644 --- a/components/hal/esp32c6/include/hal/gpio_ll.h +++ b/components/hal/esp32c6/include/hal/gpio_ll.h @@ -14,16 +14,16 @@ #pragma once +#include #include "soc/soc.h" #include "soc/gpio_periph.h" #include "soc/gpio_struct.h" #include "soc/lp_aon_reg.h" -#include "soc/lp_io_reg.h" +#include "soc/lp_io_struct.h" #include "soc/pmu_reg.h" #include "soc/usb_serial_jtag_reg.h" #include "hal/gpio_types.h" #include "hal/assert.h" -#include #ifdef __cplusplus extern "C" { @@ -42,7 +42,7 @@ extern "C" { */ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) { - REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); + REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); } /** @@ -51,9 +51,10 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) { - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); + REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU); } /** @@ -64,7 +65,7 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) { - REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); + REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD); } /** @@ -73,17 +74,18 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) { // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value // USB DP pin is default to PU enabled // Note that esp32c6 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin // which should be checked is USB_DM_GPIO_NUM instead. - // if (gpio_num == USB_DP_GPIO_NUM) { // TODO: IDF-5321 find out pin number - // SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE); - // CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP); - // } - REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD); + if (gpio_num == USB_DP_GPIO_NUM) { + SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE); + CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP); + } + REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD); } /** @@ -181,9 +183,10 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); + PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); } /** @@ -194,7 +197,7 @@ static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num) { - PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); + PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); } /** @@ -203,6 +206,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num) * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ +__attribute__((always_inline)) static inline void gpio_ll_output_disable(gpio_dev_t *hw, uint32_t gpio_num) { hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num); @@ -309,7 +313,7 @@ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength) { - SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S); + SET_PERI_REG_BITS(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, strength, FUN_DRV_S); } /** @@ -321,29 +325,27 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu */ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength) { - *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S); + *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, FUN_DRV_S); } /** - * @brief Enable all digital gpio pad hold function during Deep-sleep. + * @brief Enable all digital gpio pads hold function during Deep-sleep. * * @param hw Peripheral GPIO hardware instance address. */ static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw) { - // ESP32C6 has removed deepsleep and replace with software backup sleep - // TODO: IDF-5321 + REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_HIGH_HP_PAD_HOLD_ALL); } /** - * @brief Disable all digital gpio pad hold function during Deep-sleep. + * @brief Disable all digital gpio pads hold function during Deep-sleep. * * @param hw Peripheral GPIO hardware instance address. */ static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw) { - // ESP32C6 has removed deepsleep and replace with software backup sleep - // TODO: IDF-5321 + REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_LOW_HP_PAD_HOLD_ALL); } /** @@ -354,12 +356,7 @@ static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw) */ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num) { - // TODO: IDF-5321 - // if (gpio_num <32) { - // SET_PERI_REG_MASK(LP_AON_GPIO_HOLD0_REG, GPIO_HOLD_MASK[gpio_num]); - // } else if (gpio_num <= MAX_PAD_GPIO_NUM) { - // SET_PERI_REG_MASK(LP_AON_GPIO_HOLD1_REG, GPIO_HOLD_MASK[gpio_num]); - // } + SET_PERI_REG_MASK(LP_AON_GPIO_HOLD0_REG, GPIO_HOLD_MASK[gpio_num]); } /** @@ -370,12 +367,7 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) { - // TODO: IDF-5321 - // if (gpio_num <32) { - // CLEAR_PERI_REG_MASK(LP_AON_GPIO_HOLD0_REG, GPIO_HOLD_MASK[gpio_num]); - // } else if (gpio_num <= MAX_PAD_GPIO_NUM) { - // CLEAR_PERI_REG_MASK(LP_AON_GPIO_HOLD1_REG, GPIO_HOLD_MASK[gpio_num]); - // } + CLEAR_PERI_REG_MASK(LP_AON_GPIO_HOLD0_REG, GPIO_HOLD_MASK[gpio_num]); } /** @@ -388,7 +380,7 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num) static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx) { hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0; - PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]); + PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio * 4)); } /** @@ -399,12 +391,28 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign */ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func) { - // TODO: IDF-5321 - // // Disable USB Serial JTAG if pins 18 or pins 19 needs to select an IOMUX function - // if (pin_name == IO_MUX_GPIO18_REG || pin_name == IO_MUX_GPIO19_REG) { - // CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); - // } - // PIN_FUNC_SELECT(pin_name, func); + // Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function + if (pin_name == IO_MUX_GPIO12_REG || pin_name == IO_MUX_GPIO13_REG) { + CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); + } + PIN_FUNC_SELECT(pin_name, func); +} + +/** + * @brief Select a function for the pin in the IOMUX + * + * @param hw Peripheral GPIO hardware instance address. + * @param gpio_num GPIO number + * @param func Function to assign to the pin + */ +__attribute__((always_inline)) +static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func) +{ + // Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function + if (gpio_num == USB_DM_GPIO_NUM || gpio_num == USB_DP_GPIO_NUM) { + CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); + } + PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func); } /** @@ -420,53 +428,30 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, { hw->func_out_sel_cfg[gpio_num].oen_sel = 0; hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; - gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func); + gpio_ll_iomux_func_sel(IO_MUX_GPIO0_REG + (gpio_num * 4), func); } /** - * @brief Force hold digital and rtc gpio pad. - * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. - */ -static inline void gpio_ll_force_hold_all(void) -{ - // TODO: IDF-5321 - // REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_HIGH_HP_PAD_HOLD_ALL); - // REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_HIGH_LP_PAD_HOLD_ALL); -} - -/** - * @brief Force unhold digital and rtc gpio pad. - * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. - */ -static inline void gpio_ll_force_unhold_all(void) -{ - // TODO: IDF-5321 - // REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_LOW_HP_PAD_HOLD_ALL); - // REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_LOW_LP_PAD_HOLD_ALL); -} - -/** - * @brief Enable GPIO pin used for wakeup from sleep. + * @brief Enable GPIO pin to use sleep mode pin functions during light sleep. * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num) { - // TODO: IDF-5321 - // PIN_SLP_SEL_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); + PIN_SLP_SEL_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); } /** - * @brief Disable GPIO pin used for wakeup from sleep. + * @brief Disable GPIO pin to use sleep mode pin functions during light sleep. + * Pin functions remains the same in both normal execution and in light-sleep mode. * * @param hw Peripheral GPIO hardware instance address. * @param gpio_num GPIO number */ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num) { - // TODO: IDF-5321 - // PIN_SLP_SEL_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); + PIN_SLP_SEL_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); } /** @@ -477,8 +462,7 @@ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) { - // TODO: IDF-5321 - // PIN_SLP_PULLUP_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); + PIN_SLP_PULLUP_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); } /** @@ -489,8 +473,7 @@ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) { - // TODO: IDF-5321 - // PIN_SLP_PULLUP_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); + PIN_SLP_PULLUP_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); } /** @@ -501,8 +484,7 @@ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) { - // TODO: IDF-5321 - // PIN_SLP_PULLDOWN_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); + PIN_SLP_PULLDOWN_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); } /** @@ -513,8 +495,7 @@ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) { - // TODO: IDF-5321 - // PIN_SLP_PULLDOWN_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); + PIN_SLP_PULLDOWN_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); } /** @@ -525,8 +506,7 @@ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num) { - // TODO: IDF-5321 - // PIN_SLP_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); + PIN_SLP_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); } /** @@ -537,8 +517,7 @@ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num */ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num) { - // TODO: IDF-5321 - // PIN_SLP_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); + PIN_SLP_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); } /** @@ -549,8 +528,7 @@ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num) */ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num) { - // TODO: IDF-5321 - // PIN_SLP_OUTPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]); + PIN_SLP_OUTPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); } /** @@ -561,8 +539,7 @@ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_nu */ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num) { - // TODO: IDF-5321 - // PIN_SLP_OUTPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]); + PIN_SLP_OUTPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4)); } /** @@ -574,11 +551,10 @@ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num */ static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num, gpio_int_type_t intr_type) { - HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function"); - - // TODO: IDF-5321 - // SET_PERI_REG_MASK(LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_WAKEUP_ENABLE); - // REG_SET_FIELD(LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_INT_TYPE, intr_type); + HAL_ASSERT(gpio_num <= GPIO_NUM_7 && "gpio larger than 7 does not support deep sleep wake-up function"); + // On ESP32-C6, (lp_io pin number) == (gpio pin number) + LP_IO.pin[gpio_num].wakeup_enable = 1; + LP_IO.pin[gpio_num].int_type = intr_type; } /** @@ -589,11 +565,10 @@ static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, uint32_t gpio */ static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num) { - HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function"); - - // TODO: IDF-5321 - // CLEAR_PERI_REG_MASK(LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_WAKEUP_ENABLE); - // CLEAR_PERI_REG_MASK(LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_INT_TYPE); + HAL_ASSERT(gpio_num <= GPIO_NUM_7 && "gpio larger than 7 does not support deep sleep wake-up function"); + // On ESP32-C6, (lp_io pin number) == (gpio pin number) + LP_IO.pin[gpio_num].wakeup_enable = 0; + LP_IO.pin[gpio_num].int_type = 0; // Disable io interrupt } #ifdef __cplusplus diff --git a/components/hal/esp32h2/include/rev1/hal/gpio_ll.h b/components/hal/esp32h2/include/rev1/hal/gpio_ll.h index bb7376aae5..207d9f6d15 100644 --- a/components/hal/esp32h2/include/rev1/hal/gpio_ll.h +++ b/components/hal/esp32h2/include/rev1/hal/gpio_ll.h @@ -14,6 +14,7 @@ #pragma once +#include #include "soc/soc.h" #include "soc/gpio_periph.h" #include "soc/rtc_cntl_reg.h" @@ -21,7 +22,6 @@ #include "soc/usb_serial_jtag_reg.h" #include "hal/gpio_types.h" #include "hal/assert.h" -#include "stdlib.h" #ifdef __cplusplus extern "C" { diff --git a/components/hal/esp32h2/include/rev2/hal/gpio_ll.h b/components/hal/esp32h2/include/rev2/hal/gpio_ll.h index 7975f502a2..687c894eba 100644 --- a/components/hal/esp32h2/include/rev2/hal/gpio_ll.h +++ b/components/hal/esp32h2/include/rev2/hal/gpio_ll.h @@ -14,6 +14,7 @@ #pragma once +#include #include "soc/soc.h" #include "soc/gpio_periph.h" #include "soc/rtc_cntl_reg.h" @@ -21,7 +22,6 @@ #include "soc/usb_serial_jtag_reg.h" #include "hal/gpio_types.h" #include "hal/assert.h" -#include "stdlib.h" #ifdef __cplusplus extern "C" { diff --git a/components/hal/esp32s3/include/hal/gpio_ll.h b/components/hal/esp32s3/include/hal/gpio_ll.h index 520707dd9c..93836fb663 100644 --- a/components/hal/esp32s3/include/hal/gpio_ll.h +++ b/components/hal/esp32s3/include/hal/gpio_ll.h @@ -269,7 +269,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num) */ static inline __attribute__((always_inline)) void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func) { - if (gpio_num == 19 || gpio_num == 20) { + if (gpio_num == USB_DM_GPIO_NUM || gpio_num == USB_DP_GPIO_NUM) { CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE); } PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func); diff --git a/components/hal/include/hal/gpio_hal.h b/components/hal/include/hal/gpio_hal.h index 2c9c08bfa9..0c1c920942 100644 --- a/components/hal/include/hal/gpio_hal.h +++ b/components/hal/include/hal/gpio_hal.h @@ -451,7 +451,6 @@ void gpio_hal_sleep_pupd_config_unapply(gpio_hal_context_t *hal, uint32_t gpio_n #endif //SOC_GPIO_SUPPORT_SLP_SWITCH #if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP - /** * @brief Enable GPIO deep-sleep wake-up function. * @@ -468,14 +467,6 @@ void gpio_hal_sleep_pupd_config_unapply(gpio_hal_context_t *hal, uint32_t gpio_n * @param gpio_num GPIO number */ #define gpio_hal_deepsleep_wakeup_disable(hal, gpio_num) gpio_ll_deepsleep_wakeup_disable((hal)->dev, gpio_num) - -/** - * @brief Judge if the gpio is valid for waking up chip from deep-sleep - * - * @param gpio_num GPIO number - */ -#define gpio_hal_is_valid_deepsleep_wakeup_gpio(gpio_num) (gpio_num <= GPIO_NUM_5) - #endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP /** diff --git a/components/soc/esp32/include/soc/clkout_channel.h b/components/soc/esp32/include/soc/clkout_channel.h index 5161e3f0b6..a2b05fcb2c 100644 --- a/components/soc/esp32/include/soc/clkout_channel.h +++ b/components/soc/esp32/include/soc/clkout_channel.h @@ -1,21 +1,15 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_CLKOUT_CHANNEL_H #define _SOC_CLKOUT_CHANNEL_H //CLKOUT channels +#define CLKOUT_IOMUX_FUNC_NUM 1 + #define CLKOUT_GPIO0_DIRECT_CHANNEL CLKOUT_CHANNEL_1 #define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 0 #define CLKOUT_GPIO3_DIRECT_CHANNEL CLKOUT_CHANNEL_2 diff --git a/components/soc/esp32c2/include/soc/clkout_channel.h b/components/soc/esp32c2/include/soc/clkout_channel.h index 0a213304f6..ceb3369171 100644 --- a/components/soc/esp32c2/include/soc/clkout_channel.h +++ b/components/soc/esp32c2/include/soc/clkout_channel.h @@ -7,12 +7,6 @@ #ifndef _SOC_CLKOUT_CHANNEL_H #define _SOC_CLKOUT_CHANNEL_H -//CLKOUT channels -#define CLKOUT_GPIO20_DIRECT_CHANNEL CLKOUT_CHANNEL_1 -#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 20 -#define CLKOUT_GPIO19_DIRECT_CHANNEL CLKOUT_CHANNEL_2 -#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM 19 -#define CLKOUT_GPIO18_DIRECT_CHANNEL CLKOUT_CHANNEL_3 -#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM 18 +// ESP32C2 CLKOUT signals has no corresponding iomux pins #endif diff --git a/components/soc/esp32c3/include/soc/clkout_channel.h b/components/soc/esp32c3/include/soc/clkout_channel.h index c9e9a0c245..0d36368328 100644 --- a/components/soc/esp32c3/include/soc/clkout_channel.h +++ b/components/soc/esp32c3/include/soc/clkout_channel.h @@ -1,26 +1,12 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_CLKOUT_CHANNEL_H #define _SOC_CLKOUT_CHANNEL_H -//CLKOUT channels -#define CLKOUT_GPIO20_DIRECT_CHANNEL CLKOUT_CHANNEL_1 -#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 20 -#define CLKOUT_GPIO19_DIRECT_CHANNEL CLKOUT_CHANNEL_2 -#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM 19 -#define CLKOUT_GPIO18_DIRECT_CHANNEL CLKOUT_CHANNEL_3 -#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM 18 +// ESP32C3 CLKOUT signals has no corresponding iomux pins #endif diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index e9c25a9b5e..2f41d6692e 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -231,11 +231,7 @@ config SOC_GPIO_PIN_COUNT int default 31 -config SOC_GPIO_SUPPORTS_RTC_INDEPENDENT - bool - default y - -config SOC_GPIO_SUPPORT_FORCE_HOLD +config SOC_GPIO_SUPPORT_RTC_INDEPENDENT bool default y diff --git a/components/soc/esp32c6/include/soc/clkout_channel.h b/components/soc/esp32c6/include/soc/clkout_channel.h index d821cef127..f0c2238f02 100644 --- a/components/soc/esp32c6/include/soc/clkout_channel.h +++ b/components/soc/esp32c6/include/soc/clkout_channel.h @@ -7,13 +7,6 @@ #ifndef _SOC_CLKOUT_CHANNEL_H #define _SOC_CLKOUT_CHANNEL_H -// TODO: IDF-5870 -//CLKOUT channels -#define CLKOUT_GPIO20_DIRECT_CHANNEL CLKOUT_CHANNEL_1 -#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 20 -#define CLKOUT_GPIO19_DIRECT_CHANNEL CLKOUT_CHANNEL_2 -#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM 19 -#define CLKOUT_GPIO18_DIRECT_CHANNEL CLKOUT_CHANNEL_3 -#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM 18 +// ESP32C6 CLKOUT signals has no corresponding iomux pins #endif diff --git a/components/soc/esp32c6/include/soc/io_mux_reg.h b/components/soc/esp32c6/include/soc/io_mux_reg.h index 8a0a64acec..cbba6b20f4 100644 --- a/components/soc/esp32c6/include/soc/io_mux_reg.h +++ b/components/soc/esp32c6/include/soc/io_mux_reg.h @@ -13,7 +13,7 @@ #define SLP_OE_M (BIT(0)) #define SLP_OE_V 1 #define SLP_OE_S 0 -/* Pin used for wakeup from sleep */ +/* Used to enable sleep mode pin functions */ #define SLP_SEL (BIT(1)) #define SLP_SEL_M (BIT(1)) #define SLP_SEL_V 1 @@ -64,14 +64,25 @@ #define MCU_SEL_V 0x7 #define MCU_SEL_S 12 -#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) -#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) -#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); -#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) -#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) -#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) -#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) -#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) +#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) +#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) + +#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); +#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) +#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) #define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U #define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_XTAL_32K_N_U @@ -125,7 +136,10 @@ #define SD_DATA2_GPIO_NUM 22 #define SD_DATA3_GPIO_NUM 23 -#define MAX_RTC_GPIO_NUM 5 +#define USB_DM_GPIO_NUM 12 +#define USB_DP_GPIO_NUM 13 + +#define MAX_RTC_GPIO_NUM 8 #define MAX_PAD_GPIO_NUM 30 #define MAX_GPIO_NUM 34 #define DIG_IO_HOLD_BIT_SHIFT 32 @@ -133,25 +147,16 @@ #define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE #define PIN_CTRL (REG_IO_MUX_BASE +0x00) -#define PAD_POWER_SEL BIT(15) -#define PAD_POWER_SEL_V 0x1 -#define PAD_POWER_SEL_M BIT(15) -#define PAD_POWER_SEL_S 15 -#define PAD_POWER_SWITCH_DELAY 0x7 -#define PAD_POWER_SWITCH_DELAY_V 0x7 -#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S) -#define PAD_POWER_SWITCH_DELAY_S 12 - -#define CLK_OUT3 0xf +#define CLK_OUT3 0x1f #define CLK_OUT3_V CLK_OUT3 -#define CLK_OUT3_S 8 +#define CLK_OUT3_S 10 #define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S) -#define CLK_OUT2 0xf +#define CLK_OUT2 0x1f #define CLK_OUT2_V CLK_OUT2 -#define CLK_OUT2_S 4 +#define CLK_OUT2_S 5 #define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S) -#define CLK_OUT1 0xf +#define CLK_OUT1 0x1f #define CLK_OUT1_V CLK_OUT1 #define CLK_OUT1_S 0 #define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S) diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index 3570842015..d32ecce6df 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -139,23 +139,20 @@ #define SOC_GDMA_GROUPS (1U) // Number of GDMA groups #define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group -// TODO: IDF-5321 (Copy from esp32c3, need check) /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-C6 has 1 GPIO peripheral #define SOC_GPIO_PORT (1U) #define SOC_GPIO_PIN_COUNT (31) -// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC -// On ESP32-C6, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers. -#define SOC_GPIO_SUPPORTS_RTC_INDEPENDENT (1) -// Force hold is a new function of ESP32-C6 -#define SOC_GPIO_SUPPORT_FORCE_HOLD (1) -// GPIO0~5 on ESP32C6 can support chip deep sleep wakeup +// Target has the full LP IO subsystem +// On ESP32-C6, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. +#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) +// GPIO0~7 on ESP32C6 can support chip deep sleep wakeup #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) #define SOC_GPIO_VALID_GPIO_MASK ((1U< *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. + + The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions. + + .. list-table:: + :header-rows: 1 + :widths: 8 12 12 20 + + * - GPIO + - Analog Function + - LP GPIO + - Comment + + * - GPIO0 + - ADC1_CH0 + - LP_GPIO0 + - + + * - GPIO1 + - ADC1_CH1 + - LP_GPIO1 + - + + * - GPIO2 + - ADC1_CH2 + - LP_GPIO2 + - + + * - GPIO3 + - ADC1_CH3 + - LP_GPIO3 + - + + * - GPIO4 + - ADC1_CH4 + - LP_GPIO4 + - Strapping pin + + * - GPIO5 + - ADC1_CH5 + - LP_GPIO5 + - Strapping pin + + * - GPIO6 + - ADC1_CH6 + - LP_GPIO6 + - + + * - GPIO7 + - + - LP_GPIO7 + - + + * - GPIO8 + - + - + - Strapping pin + + * - GPIO9 + - + - + - Strapping pin + + * - GPIO10 + - + - + - + + * - GPIO11 + - + - + - + + * - GPIO12 + - + - + - USB-JTAG + + * - GPIO13 + - + - + - USB-JTAG + + * - GPIO14 + - + - + - + + * - GPIO15 + - + - + - Strapping pin + + * - GPIO16 + - + - + - + + * - GPIO17 + - + - + - + + * - GPIO18 + - + - + - + + * - GPIO19 + - + - + - + + * - GPIO20 + - + - + - + + * - GPIO21 + - + - + - + + * - GPIO22 + - + - + - + + * - GPIO23 + - + - + - + + * - GPIO24 + - + - + - SPI0/1 + + * - GPIO25 + - + - + - SPI0/1 + + * - GPIO26 + - + - + - SPI0/1 + + * - GPIO27 + - + - + - SPI0/1 + + * - GPIO28 + - + - + - SPI0/1 + + * - GPIO29 + - + - + - SPI0/1 + + * - GPIO30 + - + - + - SPI0/1 + + .. note:: + + - Strapping pin: GPIO4, GPIO5, GPIO8, GPIO9, and GPIO15 are strapping pins. For more infomation, please refer to `ESP32C6 datasheet `_. + - SPI0/1: GPIO24-30 are usually used for SPI flash and not recommended for other uses. + - USB-JTAG: GPIO 12 and 13 are used by USB-JTAG by default. In order to use them as GPIOs, USB-JTAG will be disabled by the drivers. .. only:: SOC_RTCIO_INPUT_OUTPUT_SUPPORTED diff --git a/docs/zh_CN/api-reference/peripherals/gpio.rst b/docs/zh_CN/api-reference/peripherals/gpio.rst index 59b943fb71..d03678dc89 100644 --- a/docs/zh_CN/api-reference/peripherals/gpio.rst +++ b/docs/zh_CN/api-reference/peripherals/gpio.rst @@ -903,6 +903,186 @@ GPIO & RTC GPIO - SPI0/1：GPIO12-17 通常用于 SPI flash，不推荐用于其他用途。 - RTC：GPIO0-5 可以在 Deep-sleep 模式时使用。 +.. only:: esp32c6 + + {IDF_TARGET_NAME} 芯片具有 31 个物理 GPIO 管脚（GPIO0 ~ GPIO30）。 + + - 对于内置 SiP flash 的芯片型号，GPIO24 ~ GPIO30 专门用于连接 SiP flash; 且 GPIO10 ~ GPIO11 未引出至芯片管脚。因此，对于这类芯片只有 22 个 GPIO 管脚可用。 + - 对于无内置 SiP flash 的芯片型号，则 GPIO14 未引出至芯片管脚。 + + 每个管脚都可用作一个通用 IO，或连接一个内部的外设 信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输 出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。 + + 下表提供了各管脚的详细信息，部分 GPIO 具有特殊的使用限制，具体可参考表中的注释列。 + + .. list-table:: + :header-rows: 1 + :widths: 8 12 12 20 + + * - GPIO + - 模拟功能 + - LP GPIO + - 注释 + + * - GPIO0 + - ADC1_CH0 + - LP_GPIO0 + - + + * - GPIO1 + - ADC1_CH1 + - LP_GPIO1 + - + + * - GPIO2 + - ADC1_CH2 + - LP_GPIO2 + - + + * - GPIO3 + - ADC1_CH3 + - LP_GPIO3 + - + + * - GPIO4 + - ADC1_CH4 + - LP_GPIO4 + - Strapping 管脚 + + * - GPIO5 + - ADC1_CH5 + - LP_GPIO5 + - Strapping 管脚 + + * - GPIO6 + - ADC1_CH6 + - LP_GPIO6 + - + + * - GPIO7 + - + - LP_GPIO7 + - + + * - GPIO8 + - + - + - Strapping 管脚 + + * - GPIO9 + - + - + - Strapping 管脚 + + * - GPIO10 + - + - + - + + * - GPIO11 + - + - + - + + * - GPIO12 + - + - + - USB-JTAG + + * - GPIO13 + - + - + - USB-JTAG + + * - GPIO14 + - + - + - + + * - GPIO15 + - + - + - Strapping 管脚 + + * - GPIO16 + - + - + - + + * - GPIO17 + - + - + - + + * - GPIO18 + - + - + - + + * - GPIO19 + - + - + - + + * - GPIO20 + - + - + - + + * - GPIO21 + - + - + - + + * - GPIO22 + - + - + - + + * - GPIO23 + - + - + - + + * - GPIO24 + - + - + - SPI0/1 + + * - GPIO25 + - + - + - SPI0/1 + + * - GPIO26 + - + - + - SPI0/1 + + * - GPIO27 + - + - + - SPI0/1 + + * - GPIO28 + - + - + - SPI0/1 + + * - GPIO29 + - + - + - SPI0/1 + + * - GPIO30 + - + - + - SPI0/1 + + .. note:: + + - Strapping 管脚：GPIO4、GPIO5、GPIO8、GPIO9 和 GPIO15 是 Strapping 管脚。更多信息请参考 `ESP32-C6 技术规格书 `_。 + - SPI0/1：GPIO24-30 通常用于 SPI flash，不推荐用于其他用途。 + - USB-JTAG：GPIO12 和 GPIO13 默认用于 USB-JTAG。用做 GPIO 时驱动程序将禁用 USB-JTAG。 .. only:: SOC_RTCIO_INPUT_OUTPUT_SUPPORTED diff --git a/examples/peripherals/gpio/generic_gpio/main/Kconfig.projbuild b/examples/peripherals/gpio/generic_gpio/main/Kconfig.projbuild index 37e7b74ce0..511b47633b 100644 --- a/examples/peripherals/gpio/generic_gpio/main/Kconfig.projbuild +++ b/examples/peripherals/gpio/generic_gpio/main/Kconfig.projbuild @@ -5,16 +5,16 @@ menu "Example Configuration" config GPIO_OUTPUT_0 int "GPIO output pin 0" range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 18 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 default 8 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H2 + default 18 help GPIO pin number to be used as GPIO_OUTPUT_IO_0. config GPIO_OUTPUT_1 int "GPIO output pin 1" range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX - default 19 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 default 9 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H2 + default 19 help GPIO pin number to be used as GPIO_OUTPUT_IO_1. diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index f88797bcd2..3314ead3f3 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -936,7 +936,6 @@ components/soc/esp32/include/soc/bb_reg.h components/soc/esp32/include/soc/boot_mode.h components/soc/esp32/include/soc/can_periph.h components/soc/esp32/include/soc/can_struct.h -components/soc/esp32/include/soc/clkout_channel.h components/soc/esp32/include/soc/dac_channel.h components/soc/esp32/include/soc/emac_dma_struct.h components/soc/esp32/include/soc/emac_ext_struct.h @@ -999,7 +998,6 @@ components/soc/esp32c3/include/soc/apb_saradc_reg.h components/soc/esp32c3/include/soc/assist_debug_reg.h components/soc/esp32c3/include/soc/bb_reg.h components/soc/esp32c3/include/soc/boot_mode.h -components/soc/esp32c3/include/soc/clkout_channel.h components/soc/esp32c3/include/soc/extmem_reg.h components/soc/esp32c3/include/soc/fe_reg.h components/soc/esp32c3/include/soc/gpio_pins.h @@ -1040,7 +1038,6 @@ components/soc/esp32h2/include/soc/apb_saradc_reg.h components/soc/esp32h2/include/soc/apb_saradc_struct.h components/soc/esp32h2/include/soc/bb_reg.h components/soc/esp32h2/include/soc/boot_mode.h -components/soc/esp32h2/include/soc/clkout_channel.h components/soc/esp32h2/include/soc/clkrst_reg.h components/soc/esp32h2/include/soc/efuse_reg.h components/soc/esp32h2/include/soc/efuse_struct.h @@ -1079,7 +1076,6 @@ components/soc/esp32s2/include/soc/apb_saradc_reg.h components/soc/esp32s2/include/soc/assist_debug_reg.h components/soc/esp32s2/include/soc/bb_reg.h components/soc/esp32s2/include/soc/boot_mode.h -components/soc/esp32s2/include/soc/clkout_channel.h components/soc/esp32s2/include/soc/crypto_dma_reg.h components/soc/esp32s2/include/soc/dac_channel.h components/soc/esp32s2/include/soc/dedic_gpio_reg.h @@ -1135,7 +1131,6 @@ components/soc/esp32s3/include/soc/assist_debug_struct.h components/soc/esp32s3/include/soc/bb_reg.h components/soc/esp32s3/include/soc/boot_mode.h components/soc/esp32s3/include/soc/brownout_caps.h -components/soc/esp32s3/include/soc/clkout_channel.h components/soc/esp32s3/include/soc/cpu.h components/soc/esp32s3/include/soc/extmem_reg.h components/soc/esp32s3/include/soc/extmem_struct.h