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Merge branch 'feature/enable_ecc_support_for_c5_mp' into 'master'

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feat: added ecc peripheral support for esp32c5 for mp version

Closes IDF-8625

See merge request espressif/esp-idf!30744
This commit is contained in:
Mahavir Jain
2024-05-15 12:01:41 +08:00
parent fc6a068a52 948d46a765
commit c8d59db5a0
3 changed files with 10 additions and 15 deletions
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14
components/hal/esp32c5/include/hal/ecc_ll.h
View File

@@ -21,11 +21,9 @@ typedef enum {
ECC_PARAM_PX = 0x0, ECC_PARAM_PX = 0x0,
ECC_PARAM_PY, ECC_PARAM_PY,
ECC_PARAM_K, ECC_PARAM_K,
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
ECC_PARAM_QX, ECC_PARAM_QX,
ECC_PARAM_QY, ECC_PARAM_QY,
ECC_PARAM_QZ, ECC_PARAM_QZ,
#endif
} ecc_ll_param_t; } ecc_ll_param_t;
/** /**
@@ -45,10 +43,8 @@ static inline void ecc_ll_reset_register(void)
{ {
PCR.ecc_conf.ecc_rst_en = 1; PCR.ecc_conf.ecc_rst_en = 1;
PCR.ecc_conf.ecc_rst_en = 0; PCR.ecc_conf.ecc_rst_en = 0;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// Clear reset on ECDSA, otherwise ECC is held in reset // Clear reset on ECDSA, otherwise ECC is held in reset
PCR.ecdsa_conf.ecdsa_rst_en = 0; PCR.ecdsa_conf.ecdsa_rst_en = 0;
#endif
} }
static inline void ecc_ll_enable_interrupt(void) static inline void ecc_ll_enable_interrupt(void)
@@ -78,7 +74,6 @@ static inline void ecc_ll_set_mode(ecc_mode_t mode)
case ECC_MODE_VERIFY_THEN_POINT_MUL: case ECC_MODE_VERIFY_THEN_POINT_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3); REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
break; break;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case ECC_MODE_JACOBIAN_POINT_MUL: case ECC_MODE_JACOBIAN_POINT_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 4); REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 4);
break; break;
@@ -103,7 +98,6 @@ static inline void ecc_ll_set_mode(ecc_mode_t mode)
case ECC_MODE_INVERSE_MUL: case ECC_MODE_INVERSE_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 11); REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 11);
break; break;
#endif
default: default:
HAL_ASSERT(false && "Unsupported mode"); HAL_ASSERT(false && "Unsupported mode");
break; break;
@@ -125,7 +119,6 @@ static inline void ecc_ll_set_curve(ecc_curve_t curve)
} }
} }
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
static inline void ecc_ll_set_mod_base(ecc_mod_base_t base) static inline void ecc_ll_set_mod_base(ecc_mod_base_t base)
{ {
switch(base) { switch(base) {
@@ -140,7 +133,6 @@ static inline void ecc_ll_set_mod_base(ecc_mod_base_t base)
return; return;
} }
} }
#endif
static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf, uint16_t len) static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf, uint16_t len)
{ {
@@ -156,7 +148,6 @@ static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf,
case ECC_PARAM_K: case ECC_PARAM_K:
reg = ECC_MULT_K_MEM; reg = ECC_MULT_K_MEM;
break; break;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case ECC_PARAM_QX: case ECC_PARAM_QX:
reg = ECC_MULT_QX_MEM; reg = ECC_MULT_QX_MEM;
break; break;
@@ -166,7 +157,6 @@ static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf,
case ECC_PARAM_QZ: case ECC_PARAM_QZ:
reg = ECC_MULT_QZ_MEM; reg = ECC_MULT_QZ_MEM;
break; break;
#endif
default: default:
HAL_ASSERT(false && "Invalid parameter"); HAL_ASSERT(false && "Invalid parameter");
return; return;
@@ -203,12 +193,10 @@ static inline ecc_curve_t ecc_ll_get_curve(void)
return (ecc_curve_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH)); return (ecc_curve_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH));
} }
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
static inline ecc_mod_base_t ecc_ll_get_mod_base(void) static inline ecc_mod_base_t ecc_ll_get_mod_base(void)
{ {
return (ecc_mod_base_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE)); return (ecc_mod_base_t)(REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE));
} }
#endif
static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_t len) static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_t len)
{ {
@@ -223,7 +211,6 @@ static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_
case ECC_PARAM_K: case ECC_PARAM_K:
reg = ECC_MULT_K_MEM; reg = ECC_MULT_K_MEM;
break; break;
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
case ECC_PARAM_QX: case ECC_PARAM_QX:
reg = ECC_MULT_QX_MEM; reg = ECC_MULT_QX_MEM;
break; break;
@@ -233,7 +220,6 @@ static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_
case ECC_PARAM_QZ: case ECC_PARAM_QZ:
reg = ECC_MULT_QZ_MEM; reg = ECC_MULT_QZ_MEM;
break; break;
#endif
default: default:
HAL_ASSERT(false && "Invalid parameter"); HAL_ASSERT(false && "Invalid parameter");
return; return;

8
components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
View File

@@ -47,6 +47,14 @@ config SOC_SYSTIMER_SUPPORTED
bool bool
default y default y
config SOC_ECC_SUPPORTED
bool
default y
config SOC_ECC_EXTENDED_MODES_SUPPORTED
bool
default y
config SOC_FLASH_ENC_SUPPORTED config SOC_FLASH_ENC_SUPPORTED
bool bool
default y default y

3
components/soc/esp32c5/mp/include/soc/soc_caps.h
View File

@@ -51,7 +51,8 @@
// #define SOC_RSA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8620 // #define SOC_RSA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8620
// #define SOC_HMAC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8616 // #define SOC_HMAC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8616
// #define SOC_DIG_SIGN_SUPPORTED 1 // TODO: [ESP32C5] IDF-8619 // #define SOC_DIG_SIGN_SUPPORTED 1 // TODO: [ESP32C5] IDF-8619
// #define SOC_ECC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8625 #define SOC_ECC_SUPPORTED 1
#define SOC_ECC_EXTENDED_MODES_SUPPORTED 1
#define SOC_FLASH_ENC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8622 #define SOC_FLASH_ENC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8622
// #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8623 // #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8623
// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32C5] IDF-8647 // #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32C5] IDF-8647