soc: create abstraction for cpu related operations

2025-10-28 21:51:46 +01:00 · 2020-01-19 10:02:21 +08:00
parent ac55328efd
commit c9a51bfbb2
34 changed files with 1263 additions and 117 deletions
--- a/components/soc/src/cpu_util.c
+++ b/components/soc/src/cpu_util.c
@@ -0,0 +1,118 @@
+// Copyright 2013-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "esp_attr.h"
+#include "soc/cpu.h"
+#include "soc/soc.h"
+#include "soc/rtc_cntl_reg.h"
+#include "esp_err.h"
+
+#include "sdkconfig.h"
+
+void IRAM_ATTR esp_cpu_stall(int cpu_id)
+{
+    if (cpu_id == 1) {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_APPCPU_C1_M);
+        SET_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, 0x21<<RTC_CNTL_SW_STALL_APPCPU_C1_S);
+        CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_APPCPU_C0_M);
+        SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, 2<<RTC_CNTL_SW_STALL_APPCPU_C0_S);
+    } else {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_PROCPU_C1_M);
+        SET_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, 0x21<<RTC_CNTL_SW_STALL_PROCPU_C1_S);
+        CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_PROCPU_C0_M);
+        SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, 2<<RTC_CNTL_SW_STALL_PROCPU_C0_S);
+    }
+}
+
+void IRAM_ATTR esp_cpu_unstall(int cpu_id)
+{
+    if (cpu_id == 1) {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_APPCPU_C1_M);
+        CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_APPCPU_C0_M);
+    } else {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_PROCPU_C1_M);
+        CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_PROCPU_C0_M);
+    }
+}
+
+void IRAM_ATTR esp_cpu_reset(int cpu_id)
+{
+    SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
+            cpu_id == 0 ? RTC_CNTL_SW_PROCPU_RST_M : RTC_CNTL_SW_APPCPU_RST_M);
+}
+
+bool IRAM_ATTR esp_cpu_in_ocd_debug_mode(void)
+{
+#if CONFIG_ESP32S2_DEBUG_OCDAWARE
+    int dcr;
+    int reg=0x10200C; //DSRSET register
+    asm("rer %0,%1":"=r"(dcr):"r"(reg));
+    return (dcr&0x1);
+#else
+    return false; // Always return false if "OCD aware" is disabled
+#endif
+}
+
+esp_err_t esp_set_watchpoint(int no, void *adr, int size, int flags)
+{
+    int x;
+    if (no < 0 || no > 1) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    if (flags & (~0xC0000000)) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    int dbreakc = 0x3F;
+    //We support watching 2^n byte values, from 1 to 64. Calculate the mask for that.
+    for (x = 0; x < 7; x++) {
+        if (size == (1 << x)) {
+            break;
+        }
+        dbreakc <<= 1;
+    }
+    if (x == 7) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    //Mask mask and add in flags.
+    dbreakc = (dbreakc & 0x3f) | flags;
+
+    if (no == 0) {
+        asm volatile(
+            "wsr.dbreaka0 %0\n" \
+            "wsr.dbreakc0 %1\n" \
+            ::"r"(adr), "r"(dbreakc));
+    } else {
+        asm volatile(
+            "wsr.dbreaka1 %0\n" \
+            "wsr.dbreakc1 %1\n" \
+            ::"r"(adr), "r"(dbreakc));
+    }
+    return ESP_OK;
+}
+
+void esp_clear_watchpoint(int no)
+{
+    //Setting a dbreakc register to 0 makes it trigger on neither load nor store, effectively disabling it.
+    int dbreakc = 0;
+    if (no == 0) {
+        asm volatile(
+            "wsr.dbreakc0 %0\n" \
+            ::"r"(dbreakc));
+    } else {
+        asm volatile(
+            "wsr.dbreakc1 %0\n" \
+            ::"r"(dbreakc));
+    }
+}
+