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heap: update esp32&s2&c3&h2 soc caps

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wuzhenghui
2021-11-03 19:20:39 +08:00
parent e14b39e8fb
commit ca1c4114bc
5 changed files with 19 additions and 46 deletions
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20
components/heap/port/esp32/memory_layout.c
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@@ -1,16 +1,8 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef BOOTLOADER_BUILD #ifndef BOOTLOADER_BUILD
#include <stdlib.h> #include <stdlib.h>
@@ -69,7 +61,7 @@ const soc_memory_type_desc_t soc_memory_types[] = {
//Type 15: SPI SRAM data //Type 15: SPI SRAM data
{ "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false}, { "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
//Type 16: RTC Fast RAM //Type 16: RTC Fast RAM
{ "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, 0 }, false, false}, { "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, MALLOC_CAP_RTCRAM }, false, false},
}; };
const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t); const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t);

20
components/heap/port/esp32c3/memory_layout.c
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@@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef BOOTLOADER_BUILD #ifndef BOOTLOADER_BUILD
#include <stdint.h> #include <stdint.h>
@@ -43,7 +35,7 @@ const soc_memory_type_desc_t soc_memory_types[] = {
// Type 3: IRAM // Type 3: IRAM
{ "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false}, { "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
// Type 4: RTCRAM // Type 4: RTCRAM
{ "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, 0 }, false, false}, { "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, MALLOC_CAP_RTCRAM }, false, false},
}; };
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE

20
components/heap/port/esp32h2/memory_layout.c
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@@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef BOOTLOADER_BUILD #ifndef BOOTLOADER_BUILD
#include <stdint.h> #include <stdint.h>
@@ -43,7 +35,7 @@ const soc_memory_type_desc_t soc_memory_types[] = {
// Type 3: IRAM // Type 3: IRAM
{ "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false}, { "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
// Type 4: RTCRAM // Type 4: RTCRAM
{ "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, 0 }, false, false}, { "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, MALLOC_CAP_RTCRAM }, false, false},
}; };
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE

2
components/heap/port/esp32s2/memory_layout.c
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@@ -45,7 +45,7 @@ const soc_memory_type_desc_t soc_memory_types[] = {
//TODO, in fact, part of them support EDMA, to be supported. //TODO, in fact, part of them support EDMA, to be supported.
{ "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false}, { "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
//Type 5: RTC Fast RAM //Type 5: RTC Fast RAM
{ "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, 0 }, false, false}, { "RTCRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT, MALLOC_CAP_RTCRAM }, false, false},
}; };
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE

3
tools/ci/check_copyright_ignore.txt
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@@ -1467,9 +1467,6 @@ components/heap/multi_heap_config.h
components/heap/multi_heap_internal.h components/heap/multi_heap_internal.h
components/heap/multi_heap_platform.h components/heap/multi_heap_platform.h
components/heap/multi_heap_poisoning.c components/heap/multi_heap_poisoning.c
components/heap/port/esp32/memory_layout.c
components/heap/port/esp32c3/memory_layout.c
components/heap/port/esp32h2/memory_layout.c
components/heap/port/memory_layout_utils.c components/heap/port/memory_layout_utils.c
components/heap/test/test_aligned_alloc_caps.c components/heap/test/test_aligned_alloc_caps.c
components/heap/test/test_allocator_timings.c components/heap/test/test_allocator_timings.c