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Merge branch 'fix/fix_psram_mode_reg_wrong_timing_v5.4' into 'release/v5.4'

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psram: fixed mode reg read bad timing on octal and hex psrams (v5.4)

See merge request espressif/esp-idf!35955
This commit is contained in:
morris
2025-01-06 14:52:13 +08:00
parent f335a2d6ea e12812a4d7
commit cab5334de2
2 changed files with 8 additions and 4 deletions
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7
components/esp_psram/device/esp_psram_impl_ap_hex.c
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@ -30,16 +30,19 @@
#if CONFIG_SPIRAM_SPEED_250M #if CONFIG_SPIRAM_SPEED_250M
#define AP_HEX_PSRAM_RD_DUMMY_BITLEN (2*(18-1)) #define AP_HEX_PSRAM_RD_DUMMY_BITLEN (2*(18-1))
#define AP_HEX_PSRAM_RD_REG_DUMMY_BITLEN (2*(9-1))
#define AP_HEX_PSRAM_WR_DUMMY_BITLEN (2*(9-1)) #define AP_HEX_PSRAM_WR_DUMMY_BITLEN (2*(9-1))
#define AP_HEX_PSRAM_RD_LATENCY 6 #define AP_HEX_PSRAM_RD_LATENCY 6
#define AP_HEX_PSRAM_WR_LATENCY 3 #define AP_HEX_PSRAM_WR_LATENCY 3
#elif CONFIG_SPIRAM_SPEED_200M #elif CONFIG_SPIRAM_SPEED_200M
#define AP_HEX_PSRAM_RD_DUMMY_BITLEN (2*(14-1)) #define AP_HEX_PSRAM_RD_DUMMY_BITLEN (2*(14-1))
#define AP_HEX_PSRAM_RD_REG_DUMMY_BITLEN (2*(7-1))
#define AP_HEX_PSRAM_WR_DUMMY_BITLEN (2*(7-1)) #define AP_HEX_PSRAM_WR_DUMMY_BITLEN (2*(7-1))
#define AP_HEX_PSRAM_RD_LATENCY 4 #define AP_HEX_PSRAM_RD_LATENCY 4
#define AP_HEX_PSRAM_WR_LATENCY 1 #define AP_HEX_PSRAM_WR_LATENCY 1
#else #else
#define AP_HEX_PSRAM_RD_DUMMY_BITLEN (2*(10-1)) #define AP_HEX_PSRAM_RD_DUMMY_BITLEN (2*(10-1))
#define AP_HEX_PSRAM_RD_REG_DUMMY_BITLEN (2*(5-1))
#define AP_HEX_PSRAM_WR_DUMMY_BITLEN (2*(5-1)) #define AP_HEX_PSRAM_WR_DUMMY_BITLEN (2*(5-1))
#define AP_HEX_PSRAM_RD_LATENCY 2 #define AP_HEX_PSRAM_RD_LATENCY 2
#define AP_HEX_PSRAM_WR_LATENCY 2 #define AP_HEX_PSRAM_WR_LATENCY 2
@ -137,7 +140,7 @@ static void s_init_psram_mode_reg(int spi_num, hex_psram_mode_reg_t *mode_reg_co
int cmd_len = 16; int cmd_len = 16;
uint32_t addr = 0x0; uint32_t addr = 0x0;
int addr_bit_len = 32; int addr_bit_len = 32;
int dummy = AP_HEX_PSRAM_RD_DUMMY_BITLEN; int dummy = AP_HEX_PSRAM_RD_REG_DUMMY_BITLEN;
hex_psram_mode_reg_t mode_reg = {0}; hex_psram_mode_reg_t mode_reg = {0};
int data_bit_len = 16; int data_bit_len = 16;
@ -216,7 +219,7 @@ static void s_get_psram_mode_reg(int spi_num, hex_psram_mode_reg_t *out_reg)
{ {
int cmd_len = 16; int cmd_len = 16;
int addr_bit_len = 32; int addr_bit_len = 32;
int dummy = AP_HEX_PSRAM_RD_DUMMY_BITLEN; int dummy = AP_HEX_PSRAM_RD_REG_DUMMY_BITLEN;
int data_bit_len = 16; int data_bit_len = 16;
//Read MR0~1 register //Read MR0~1 register

5
components/esp_psram/esp32s3/esp_psram_impl_octal.c
View File

@ -31,6 +31,7 @@
#define OCT_PSRAM_WR_CMD_BITLEN 16 #define OCT_PSRAM_WR_CMD_BITLEN 16
#define OCT_PSRAM_ADDR_BITLEN 32 #define OCT_PSRAM_ADDR_BITLEN 32
#define OCT_PSRAM_RD_DUMMY_BITLEN (2*(10-1)) #define OCT_PSRAM_RD_DUMMY_BITLEN (2*(10-1))
#define OCT_PSRAM_RD_REG_DUMMY_BITLEN (2*(5-1))
#define OCT_PSRAM_WR_DUMMY_BITLEN (2*(5-1)) #define OCT_PSRAM_WR_DUMMY_BITLEN (2*(5-1))
#define OCT_PSRAM_CS1_IO MSPI_IOMUX_PIN_NUM_CS1 #define OCT_PSRAM_CS1_IO MSPI_IOMUX_PIN_NUM_CS1
#define OCT_PSRAM_VENDOR_ID 0xD #define OCT_PSRAM_VENDOR_ID 0xD
@ -115,7 +116,7 @@ static void s_init_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *mode_reg_co
int cmd_len = 16; int cmd_len = 16;
uint32_t addr = 0x0; //0x0 is the MR0 register uint32_t addr = 0x0; //0x0 is the MR0 register
int addr_bit_len = 32; int addr_bit_len = 32;
int dummy = OCT_PSRAM_RD_DUMMY_BITLEN; int dummy = OCT_PSRAM_RD_REG_DUMMY_BITLEN;
opi_psram_mode_reg_t mode_reg = {0}; opi_psram_mode_reg_t mode_reg = {0};
int data_bit_len = 16; int data_bit_len = 16;
@ -178,7 +179,7 @@ static void s_get_psram_mode_reg(int spi_num, opi_psram_mode_reg_t *out_reg)
esp_rom_spiflash_read_mode_t mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE; esp_rom_spiflash_read_mode_t mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE;
int cmd_len = 16; int cmd_len = 16;
int addr_bit_len = 32; int addr_bit_len = 32;
int dummy = OCT_PSRAM_RD_DUMMY_BITLEN; int dummy = OCT_PSRAM_RD_REG_DUMMY_BITLEN;
int data_bit_len = 16; int data_bit_len = 16;
//Read MR0~1 register //Read MR0~1 register