diff --git a/components/soc/esp32c61/include/soc/assist_debug_reg.h b/components/soc/esp32c61/include/soc/assist_debug_reg.h new file mode 100644 index 0000000000..4b7e6b6ff5 --- /dev/null +++ b/components/soc/esp32c61/include/soc/assist_debug_reg.h @@ -0,0 +1,824 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ASSIST_DEBUG_CORE_0_MONTR_ENA_REG register + * core0 monitor enable configuration register + */ +#define ASSIST_DEBUG_CORE_0_MONTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0; + * Configures whether to monitor read operations in region 0 by the Data bus. \\ + * 0: Not monitor\\ + * 1: Monitor\\ + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0; + * Configures whether to monitor write operations in region 0 by the Data bus.\\ + * 0: Not monitor\\ + * 1: Monitor\\ + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0; + * Configures whether to monitor read operations in region 1 by the Data bus.\\ + * 0: Not Monitor\\ + * 1: Monitor\\ + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0; + * Configures whether to monitor write operations in region 1 by the Data bus.\\ + * 0: Not Monitor\\ + * 1: Monitor\\ + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0; + * Configures whether to monitor read operations in region 0 by the Peripheral bus.\\ + * 0: Not Monitor\\ + * 1: Monitor\\ + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0; + * Configures whether to monitor write operations in region 0 by the Peripheral bus.\\ + * 0: Not Monitor\\ + * 1: Monitor\\ + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0; + * Configures whether to monitor read operations in region 1 by the Peripheral bus.\\ + * 0: Not Monitor\\ + * 1: Monitor\\ + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0; + * Configures whether to monitor write operations in region 1 by the Peripheral bus.\\ + * 0: Not Monitor\\ + * 1: Monitor\\ + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0; + * Configures whether to monitor SP exceeding the lower bound address of SP monitored + * region.\\ + * 0: Not Monitor\\ + * 1: Monitor\\ + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0; + * Configures whether to monitor SP exceeding the upper bound address of SP monitored + * region.\\ + * 0: Not Monitor\\ + * 1: Monitor\\ + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9 +/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [10]; default: 0; + * IBUS busy monitor enable + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10 +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0; + * DBUS busy monitor enbale + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11 + +/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register + * core0 monitor interrupt status register + */ +#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0; + * The raw interrupt status of read operations in region 0 by Data bus. + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0; + * The raw interrupt status of write operations in region 0 by Data bus. + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0; + * The raw interrupt status of read operations in region 1 by Data bus. + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0; + * The raw interrupt status of write operations in region 1 by Data bus. + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0; + * The raw interrupt status of read operations in region 0 by Peripheral bus. + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0; + * The raw interrupt status of write operations in region 0 by Peripheral bus. + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0; + * The raw interrupt status of read operations in region 1 by Peripheral bus. + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0; + * The raw interrupt status of write operations in region 1 by Peripheral bus. + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0; + * The raw interrupt status of SP exceeding the lower bound address of SP monitored + * region. + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0; + * The raw interrupt status of SP exceeding the upper bound address of SP monitored + * region. + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9 +/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [10]; default: 0; + * IBUS busy monitor interrupt status + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10 +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [11]; default: 0; + * DBUS busy monitor initerrupt status + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11 + +/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register + * core0 monitor interrupt enable register + */ +#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA : R/W; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA : R/W; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA : R/W; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA : R/W; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA : R/W; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA : R/W; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA : R/W; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA : R/W; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA : R/W; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S 9 +/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA : R/W; bitpos: [10]; default: 0; + * IBUS busy monitor interrupt enable + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_S 10 +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA : R/W; bitpos: [11]; default: 0; + * DBUS busy monitor interrupt enbale + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_S 11 + +/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register + * core0 monitor interrupt clear register + */ +#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear the interrupt for read operations in region 0 by Data bus. + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear the interrupt for write operations in region 0 by Data bus. + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0; + * Write 1 to clear the interrupt for read operations in region 1 by Data bus. + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2 +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0; + * Write 1 to clear the interrupt for write operations in region 1 by Data bus. + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0; + * Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus. + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0; + * Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus. + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0; + * Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus. + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6 +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0; + * Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus. + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0; + * Write 1 to clear the interrupt for SP exceeding the lower bound address of SP + * monitored region. + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8 +/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0; + * Write 1 to clear the interrupt for SP exceeding the upper bound address of SP + * monitored region. + */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9 +/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [10]; default: 0; + * IBUS busy monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10 +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [11]; default: 0; + * DBUS busy monitor interrupt clr + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register + * Configures lower boundary address of region 0 monitored on Data bus + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the lower bound address of Data bus region 0. + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register + * Configures upper boundary address of region 0 monitored on Data bus + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0; + * Configures the upper bound address of Data bus region 0. + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register + * Configures lower boundary address of region 1 monitored on Data bus + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the lower bound address of Data bus region 1. + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register + * Configures upper boundary address of region 1 monitored on Data bus + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c) +/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0; + * Configures the upper bound address of Data bus region 1. + */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register + * Configures lower boundary address of region 0 monitored on Peripheral bus + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the lower bound address of Peripheral bus region 0. + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register + * Configures upper boundary address of region 0 monitored on Peripheral bus + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0; + * Configures the upper bound address of Peripheral bus region 0. + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register + * Configures lower boundary address of region 1 monitored on Peripheral bus + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the lower bound address of Peripheral bus region 1. + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register + * Configures upper boundary address of region 1 monitored on Peripheral bus + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c) +/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0; + * Configures the upper bound address of Peripheral bus region 1. + */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register + * Region monitoring HP CPU PC status register + */ +#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30) +/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0; + * Represents the PC value when an interrupt is triggered during region monitoring. + */ +#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PC_M (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S) +#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0 + +/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register + * Region monitoring HP CPU SP status register + */ +#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34) +/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0; + * Represents the SP value when an interrupt is triggered during region monitoring. + */ +#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_SP_M (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S) +#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0 + +/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register + * Configures stack monitoring lower boundary address + */ +#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38) +/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0; + * Configures the lower bound address of SP. + */ +#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S) +#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0 + +/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register + * Configures stack monitoring upper boundary address + */ +#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c) +/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the upper bound address of SP. + */ +#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MAX_M (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S) +#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0 + +/** ASSIST_DEBUG_CORE_0_SP_PC_REG register + * Stack monitoring HP CPU PC status register + */ +#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40) +/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0; + * Represents the PC value during stack monitoring. + */ +#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S) +#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_SP_PC_S 0 + +/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register + * HP CPU PC logging enable register + */ +#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44) +/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0; + * Configures whether to enable PC logging.\\ + * 0: Disable\\ + * 1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time\\ + */ +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0)) +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S) +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0 +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0; + * Configures whether to enable HP CPU debugging.\\ + * 0: Disable\\ + * 1: HP CPU outputs PC\\ + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1 + +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register + * PC logging register + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48) +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0; + * Represents the PC value at HP CPU reset. + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0 + +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register + * PC logging register + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c) +/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0; + * Represents SP. + */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0 + +/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register + * exception monitor status register0 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50) +/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [29:0]; default: 0; + * reg_core_0_iram0_recording_addr_0 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x3FFFFFFFU +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0x3FFFFFFFU +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0 +/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [30]; default: 0; + * reg_core_0_iram0_recording_wr_0 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(30)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 30 +/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [31]; default: 0; + * reg_core_0_iram0_recording_loadstore_0 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(31)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 31 + +/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register + * exception monitor status register1 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54) +/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [29:0]; default: 0; + * reg_core_0_iram0_recording_addr_1 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x3FFFFFFFU +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0x3FFFFFFFU +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0 +/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [30]; default: 0; + * reg_core_0_iram0_recording_wr_1 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(30)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 30 +/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [31]; default: 0; + * reg_core_0_iram0_recording_loadstore_1 + */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(31)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 31 + +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register + * exception monitor status register2 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58) +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [0]; default: 0; + * reg_core_0_dram0_recording_wr_0 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(0)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 0 +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [4:1]; default: 0; + * reg_core_0_dram0_recording_byteen_0 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000000FU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0x0000000FU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 1 + +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register + * exception monitor status register3 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c) +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [29:0]; default: 0; + * reg_core_0_dram0_recording_addr_0 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x3FFFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0x3FFFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0 + +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register + * exception monitor status register4 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60) +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0; + * reg_core_0_dram0_recording_pc_0 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0 + +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register + * exception monitor status register5 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64) +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [0]; default: 0; + * reg_core_0_dram0_recording_wr_1 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(0)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 0 +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [4:1]; default: 0; + * reg_core_0_dram0_recording_byteen_1 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000000FU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0x0000000FU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 1 + +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG register + * exception monitor status register6 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68) +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [29:0]; default: 0; + * reg_core_0_dram0_recording_addr_1 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x3FFFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0x3FFFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0 + +/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG register + * exception monitor status register7 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c) +/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0; + * reg_core_0_dram0_recording_pc_1 + */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0 + +/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register + * cpu status register + */ +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70) +/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0; + * Represents the PC of the last command before the HP CPU enters exception. + */ +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S) +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU +#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0 + +/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register + * cpu status register + */ +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74) +/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0; + * Represents whether RISC-V CPU (HP CPU) is in debugging mode.\\ + * 1: In debugging mode\\ + * 0: Not in debugging mode\\ + */ +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0)) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0 +/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0; + * Represents the status of the RISC-V CPU (HP CPU) debug module.\\ + * 1: Active status\\ + * Other: Inactive status\\ + */ +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1)) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S) +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U +#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1 + +/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register + * exception monitor status register8 + */ +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x100) +/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0; + * reg_core_x_iram0_dram0_limit_cycle_0 + */ +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFFU +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S) +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0x000FFFFFU +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0 + +/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register + * exception monitor status register9 + */ +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x104) +/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0; + * reg_core_x_iram0_dram0_limit_cycle_1 + */ +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFFU +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S) +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0x000FFFFFU +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0 + +/** ASSIST_DEBUG_CLOCK_GATE_REG register + * Register clock control + */ +#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x108) +/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether to enable the register clock gating. \\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define ASSIST_DEBUG_CLK_EN (BIT(0)) +#define ASSIST_DEBUG_CLK_EN_M (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S) +#define ASSIST_DEBUG_CLK_EN_V 0x00000001U +#define ASSIST_DEBUG_CLK_EN_S 0 + +/** ASSIST_DEBUG_DATE_REG register + * Version control register + */ +#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc) +/** ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34640176; + * version register + */ +#define ASSIST_DEBUG_DATE 0x0FFFFFFFU +#define ASSIST_DEBUG_DATE_M (ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_DATE_S) +#define ASSIST_DEBUG_DATE_V 0x0FFFFFFFU +#define ASSIST_DEBUG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/assist_debug_struct.h b/components/soc/esp32c61/include/soc/assist_debug_struct.h new file mode 100644 index 0000000000..243b6959aa --- /dev/null +++ b/components/soc/esp32c61/include/soc/assist_debug_struct.h @@ -0,0 +1,774 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: monitor configuration registers */ +/** Type of core_0_montr_ena register + * core0 monitor enable configuration register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0; + * Configures whether to monitor read operations in region 0 by the Data bus. \\ + * 0: Not monitor\\ + * 1: Monitor\\ + */ + uint32_t core_0_area_dram0_0_rd_ena:1; + /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0; + * Configures whether to monitor write operations in region 0 by the Data bus.\\ + * 0: Not monitor\\ + * 1: Monitor\\ + */ + uint32_t core_0_area_dram0_0_wr_ena:1; + /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0; + * Configures whether to monitor read operations in region 1 by the Data bus.\\ + * 0: Not Monitor\\ + * 1: Monitor\\ + */ + uint32_t core_0_area_dram0_1_rd_ena:1; + /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0; + * Configures whether to monitor write operations in region 1 by the Data bus.\\ + * 0: Not Monitor\\ + * 1: Monitor\\ + */ + uint32_t core_0_area_dram0_1_wr_ena:1; + /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0; + * Configures whether to monitor read operations in region 0 by the Peripheral bus.\\ + * 0: Not Monitor\\ + * 1: Monitor\\ + */ + uint32_t core_0_area_pif_0_rd_ena:1; + /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0; + * Configures whether to monitor write operations in region 0 by the Peripheral bus.\\ + * 0: Not Monitor\\ + * 1: Monitor\\ + */ + uint32_t core_0_area_pif_0_wr_ena:1; + /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0; + * Configures whether to monitor read operations in region 1 by the Peripheral bus.\\ + * 0: Not Monitor\\ + * 1: Monitor\\ + */ + uint32_t core_0_area_pif_1_rd_ena:1; + /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0; + * Configures whether to monitor write operations in region 1 by the Peripheral bus.\\ + * 0: Not Monitor\\ + * 1: Monitor\\ + */ + uint32_t core_0_area_pif_1_wr_ena:1; + /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0; + * Configures whether to monitor SP exceeding the lower bound address of SP monitored + * region.\\ + * 0: Not Monitor\\ + * 1: Monitor\\ + */ + uint32_t core_0_sp_spill_min_ena:1; + /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0; + * Configures whether to monitor SP exceeding the upper bound address of SP monitored + * region.\\ + * 0: Not Monitor\\ + * 1: Monitor\\ + */ + uint32_t core_0_sp_spill_max_ena:1; + /** core_0_iram0_exception_monitor_ena : R/W; bitpos: [10]; default: 0; + * IBUS busy monitor enable + */ + uint32_t core_0_iram0_exception_monitor_ena:1; + /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0; + * DBUS busy monitor enbale + */ + uint32_t core_0_dram0_exception_monitor_ena:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} assist_debug_core_0_montr_ena_reg_t; + +/** Type of core_0_area_dram0_0_min register + * Configures lower boundary address of region 0 monitored on Data bus + */ +typedef union { + struct { + /** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the lower bound address of Data bus region 0. + */ + uint32_t core_0_area_dram0_0_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_0_min_reg_t; + +/** Type of core_0_area_dram0_0_max register + * Configures upper boundary address of region 0 monitored on Data bus + */ +typedef union { + struct { + /** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0; + * Configures the upper bound address of Data bus region 0. + */ + uint32_t core_0_area_dram0_0_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_0_max_reg_t; + +/** Type of core_0_area_dram0_1_min register + * Configures lower boundary address of region 1 monitored on Data bus + */ +typedef union { + struct { + /** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the lower bound address of Data bus region 1. + */ + uint32_t core_0_area_dram0_1_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_1_min_reg_t; + +/** Type of core_0_area_dram0_1_max register + * Configures upper boundary address of region 1 monitored on Data bus + */ +typedef union { + struct { + /** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0; + * Configures the upper bound address of Data bus region 1. + */ + uint32_t core_0_area_dram0_1_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_dram0_1_max_reg_t; + +/** Type of core_0_area_pif_0_min register + * Configures lower boundary address of region 0 monitored on Peripheral bus + */ +typedef union { + struct { + /** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the lower bound address of Peripheral bus region 0. + */ + uint32_t core_0_area_pif_0_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_0_min_reg_t; + +/** Type of core_0_area_pif_0_max register + * Configures upper boundary address of region 0 monitored on Peripheral bus + */ +typedef union { + struct { + /** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0; + * Configures the upper bound address of Peripheral bus region 0. + */ + uint32_t core_0_area_pif_0_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_0_max_reg_t; + +/** Type of core_0_area_pif_1_min register + * Configures lower boundary address of region 1 monitored on Peripheral bus + */ +typedef union { + struct { + /** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the lower bound address of Peripheral bus region 1. + */ + uint32_t core_0_area_pif_1_min:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_1_min_reg_t; + +/** Type of core_0_area_pif_1_max register + * Configures upper boundary address of region 1 monitored on Peripheral bus + */ +typedef union { + struct { + /** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0; + * Configures the upper bound address of Peripheral bus region 1. + */ + uint32_t core_0_area_pif_1_max:32; + }; + uint32_t val; +} assist_debug_core_0_area_pif_1_max_reg_t; + +/** Type of core_0_area_pc register + * Region monitoring HP CPU PC status register + */ +typedef union { + struct { + /** core_0_area_pc : RO; bitpos: [31:0]; default: 0; + * Represents the PC value when an interrupt is triggered during region monitoring. + */ + uint32_t core_0_area_pc:32; + }; + uint32_t val; +} assist_debug_core_0_area_pc_reg_t; + +/** Type of core_0_area_sp register + * Region monitoring HP CPU SP status register + */ +typedef union { + struct { + /** core_0_area_sp : RO; bitpos: [31:0]; default: 0; + * Represents the SP value when an interrupt is triggered during region monitoring. + */ + uint32_t core_0_area_sp:32; + }; + uint32_t val; +} assist_debug_core_0_area_sp_reg_t; + +/** Type of core_0_sp_min register + * Configures stack monitoring lower boundary address + */ +typedef union { + struct { + /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0; + * Configures the lower bound address of SP. + */ + uint32_t core_0_sp_min:32; + }; + uint32_t val; +} assist_debug_core_0_sp_min_reg_t; + +/** Type of core_0_sp_max register + * Configures stack monitoring upper boundary address + */ +typedef union { + struct { + /** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the upper bound address of SP. + */ + uint32_t core_0_sp_max:32; + }; + uint32_t val; +} assist_debug_core_0_sp_max_reg_t; + +/** Type of core_0_sp_pc register + * Stack monitoring HP CPU PC status register + */ +typedef union { + struct { + /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0; + * Represents the PC value during stack monitoring. + */ + uint32_t core_0_sp_pc:32; + }; + uint32_t val; +} assist_debug_core_0_sp_pc_reg_t; + + +/** Group: interrupt configuration register */ +/** Type of core_0_intr_raw register + * core0 monitor interrupt status register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0; + * The raw interrupt status of read operations in region 0 by Data bus. + */ + uint32_t core_0_area_dram0_0_rd_raw:1; + /** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0; + * The raw interrupt status of write operations in region 0 by Data bus. + */ + uint32_t core_0_area_dram0_0_wr_raw:1; + /** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0; + * The raw interrupt status of read operations in region 1 by Data bus. + */ + uint32_t core_0_area_dram0_1_rd_raw:1; + /** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0; + * The raw interrupt status of write operations in region 1 by Data bus. + */ + uint32_t core_0_area_dram0_1_wr_raw:1; + /** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0; + * The raw interrupt status of read operations in region 0 by Peripheral bus. + */ + uint32_t core_0_area_pif_0_rd_raw:1; + /** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0; + * The raw interrupt status of write operations in region 0 by Peripheral bus. + */ + uint32_t core_0_area_pif_0_wr_raw:1; + /** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0; + * The raw interrupt status of read operations in region 1 by Peripheral bus. + */ + uint32_t core_0_area_pif_1_rd_raw:1; + /** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0; + * The raw interrupt status of write operations in region 1 by Peripheral bus. + */ + uint32_t core_0_area_pif_1_wr_raw:1; + /** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0; + * The raw interrupt status of SP exceeding the lower bound address of SP monitored + * region. + */ + uint32_t core_0_sp_spill_min_raw:1; + /** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0; + * The raw interrupt status of SP exceeding the upper bound address of SP monitored + * region. + */ + uint32_t core_0_sp_spill_max_raw:1; + /** core_0_iram0_exception_monitor_raw : RO; bitpos: [10]; default: 0; + * IBUS busy monitor interrupt status + */ + uint32_t core_0_iram0_exception_monitor_raw:1; + /** core_0_dram0_exception_monitor_raw : RO; bitpos: [11]; default: 0; + * DBUS busy monitor initerrupt status + */ + uint32_t core_0_dram0_exception_monitor_raw:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} assist_debug_core_0_intr_raw_reg_t; + +/** Type of core_0_intr_ena register + * core0 monitor interrupt enable register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_intr_ena : R/W; bitpos: [0]; default: 0; + * Core0 dram0 area0 read monitor interrupt enable + */ + uint32_t core_0_area_dram0_0_rd_intr_ena:1; + /** core_0_area_dram0_0_wr_intr_ena : R/W; bitpos: [1]; default: 0; + * Core0 dram0 area0 write monitor interrupt enable + */ + uint32_t core_0_area_dram0_0_wr_intr_ena:1; + /** core_0_area_dram0_1_rd_intr_ena : R/W; bitpos: [2]; default: 0; + * Core0 dram0 area1 read monitor interrupt enable + */ + uint32_t core_0_area_dram0_1_rd_intr_ena:1; + /** core_0_area_dram0_1_wr_intr_ena : R/W; bitpos: [3]; default: 0; + * Core0 dram0 area1 write monitor interrupt enable + */ + uint32_t core_0_area_dram0_1_wr_intr_ena:1; + /** core_0_area_pif_0_rd_intr_ena : R/W; bitpos: [4]; default: 0; + * Core0 PIF area0 read monitor interrupt enable + */ + uint32_t core_0_area_pif_0_rd_intr_ena:1; + /** core_0_area_pif_0_wr_intr_ena : R/W; bitpos: [5]; default: 0; + * Core0 PIF area0 write monitor interrupt enable + */ + uint32_t core_0_area_pif_0_wr_intr_ena:1; + /** core_0_area_pif_1_rd_intr_ena : R/W; bitpos: [6]; default: 0; + * Core0 PIF area1 read monitor interrupt enable + */ + uint32_t core_0_area_pif_1_rd_intr_ena:1; + /** core_0_area_pif_1_wr_intr_ena : R/W; bitpos: [7]; default: 0; + * Core0 PIF area1 write monitor interrupt enable + */ + uint32_t core_0_area_pif_1_wr_intr_ena:1; + /** core_0_sp_spill_min_intr_ena : R/W; bitpos: [8]; default: 0; + * Core0 stackpoint underflow monitor interrupt enable + */ + uint32_t core_0_sp_spill_min_intr_ena:1; + /** core_0_sp_spill_max_intr_ena : R/W; bitpos: [9]; default: 0; + * Core0 stackpoint overflow monitor interrupt enable + */ + uint32_t core_0_sp_spill_max_intr_ena:1; + /** core_0_iram0_exception_monitor_intr_ena : R/W; bitpos: [10]; default: 0; + * IBUS busy monitor interrupt enable + */ + uint32_t core_0_iram0_exception_monitor_intr_ena:1; + /** core_0_dram0_exception_monitor_intr_ena : R/W; bitpos: [11]; default: 0; + * DBUS busy monitor interrupt enbale + */ + uint32_t core_0_dram0_exception_monitor_intr_ena:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} assist_debug_core_0_intr_ena_reg_t; + +/** Type of core_0_intr_clr register + * core0 monitor interrupt clear register + */ +typedef union { + struct { + /** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear the interrupt for read operations in region 0 by Data bus. + */ + uint32_t core_0_area_dram0_0_rd_clr:1; + /** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear the interrupt for write operations in region 0 by Data bus. + */ + uint32_t core_0_area_dram0_0_wr_clr:1; + /** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0; + * Write 1 to clear the interrupt for read operations in region 1 by Data bus. + */ + uint32_t core_0_area_dram0_1_rd_clr:1; + /** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0; + * Write 1 to clear the interrupt for write operations in region 1 by Data bus. + */ + uint32_t core_0_area_dram0_1_wr_clr:1; + /** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0; + * Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus. + */ + uint32_t core_0_area_pif_0_rd_clr:1; + /** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0; + * Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus. + */ + uint32_t core_0_area_pif_0_wr_clr:1; + /** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0; + * Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus. + */ + uint32_t core_0_area_pif_1_rd_clr:1; + /** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0; + * Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus. + */ + uint32_t core_0_area_pif_1_wr_clr:1; + /** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0; + * Write 1 to clear the interrupt for SP exceeding the lower bound address of SP + * monitored region. + */ + uint32_t core_0_sp_spill_min_clr:1; + /** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0; + * Write 1 to clear the interrupt for SP exceeding the upper bound address of SP + * monitored region. + */ + uint32_t core_0_sp_spill_max_clr:1; + /** core_0_iram0_exception_monitor_clr : WT; bitpos: [10]; default: 0; + * IBUS busy monitor interrupt clr + */ + uint32_t core_0_iram0_exception_monitor_clr:1; + /** core_0_dram0_exception_monitor_clr : WT; bitpos: [11]; default: 0; + * DBUS busy monitor interrupt clr + */ + uint32_t core_0_dram0_exception_monitor_clr:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} assist_debug_core_0_intr_clr_reg_t; + + +/** Group: pc reording configuration register */ +/** Type of core_0_rcd_en register + * HP CPU PC logging enable register + */ +typedef union { + struct { + /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0; + * Configures whether to enable PC logging.\\ + * 0: Disable\\ + * 1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time\\ + */ + uint32_t core_0_rcd_recorden:1; + /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0; + * Configures whether to enable HP CPU debugging.\\ + * 0: Disable\\ + * 1: HP CPU outputs PC\\ + */ + uint32_t core_0_rcd_pdebugen:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} assist_debug_core_0_rcd_en_reg_t; + + +/** Group: pc reording status register */ +/** Type of core_0_rcd_pdebugpc register + * PC logging register + */ +typedef union { + struct { + /** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0; + * Represents the PC value at HP CPU reset. + */ + uint32_t core_0_rcd_pdebugpc:32; + }; + uint32_t val; +} assist_debug_core_0_rcd_pdebugpc_reg_t; + +/** Type of core_0_rcd_pdebugsp register + * PC logging register + */ +typedef union { + struct { + /** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0; + * Represents SP. + */ + uint32_t core_0_rcd_pdebugsp:32; + }; + uint32_t val; +} assist_debug_core_0_rcd_pdebugsp_reg_t; + + +/** Group: exception monitor regsiter */ +/** Type of core_0_iram0_exception_monitor_0 register + * exception monitor status register0 + */ +typedef union { + struct { + /** core_0_iram0_recording_addr_0 : RO; bitpos: [29:0]; default: 0; + * reg_core_0_iram0_recording_addr_0 + */ + uint32_t core_0_iram0_recording_addr_0:30; + /** core_0_iram0_recording_wr_0 : RO; bitpos: [30]; default: 0; + * reg_core_0_iram0_recording_wr_0 + */ + uint32_t core_0_iram0_recording_wr_0:1; + /** core_0_iram0_recording_loadstore_0 : RO; bitpos: [31]; default: 0; + * reg_core_0_iram0_recording_loadstore_0 + */ + uint32_t core_0_iram0_recording_loadstore_0:1; + }; + uint32_t val; +} assist_debug_core_0_iram0_exception_monitor_0_reg_t; + +/** Type of core_0_iram0_exception_monitor_1 register + * exception monitor status register1 + */ +typedef union { + struct { + /** core_0_iram0_recording_addr_1 : RO; bitpos: [29:0]; default: 0; + * reg_core_0_iram0_recording_addr_1 + */ + uint32_t core_0_iram0_recording_addr_1:30; + /** core_0_iram0_recording_wr_1 : RO; bitpos: [30]; default: 0; + * reg_core_0_iram0_recording_wr_1 + */ + uint32_t core_0_iram0_recording_wr_1:1; + /** core_0_iram0_recording_loadstore_1 : RO; bitpos: [31]; default: 0; + * reg_core_0_iram0_recording_loadstore_1 + */ + uint32_t core_0_iram0_recording_loadstore_1:1; + }; + uint32_t val; +} assist_debug_core_0_iram0_exception_monitor_1_reg_t; + +/** Type of core_0_dram0_exception_monitor_0 register + * exception monitor status register2 + */ +typedef union { + struct { + /** core_0_dram0_recording_wr_0 : RO; bitpos: [0]; default: 0; + * reg_core_0_dram0_recording_wr_0 + */ + uint32_t core_0_dram0_recording_wr_0:1; + /** core_0_dram0_recording_byteen_0 : RO; bitpos: [4:1]; default: 0; + * reg_core_0_dram0_recording_byteen_0 + */ + uint32_t core_0_dram0_recording_byteen_0:4; + uint32_t reserved_5:27; + }; + uint32_t val; +} assist_debug_core_0_dram0_exception_monitor_0_reg_t; + +/** Type of core_0_dram0_exception_monitor_1 register + * exception monitor status register3 + */ +typedef union { + struct { + /** core_0_dram0_recording_addr_0 : RO; bitpos: [29:0]; default: 0; + * reg_core_0_dram0_recording_addr_0 + */ + uint32_t core_0_dram0_recording_addr_0:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} assist_debug_core_0_dram0_exception_monitor_1_reg_t; + +/** Type of core_0_dram0_exception_monitor_2 register + * exception monitor status register4 + */ +typedef union { + struct { + /** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0; + * reg_core_0_dram0_recording_pc_0 + */ + uint32_t core_0_dram0_recording_pc_0:32; + }; + uint32_t val; +} assist_debug_core_0_dram0_exception_monitor_2_reg_t; + +/** Type of core_0_dram0_exception_monitor_3 register + * exception monitor status register5 + */ +typedef union { + struct { + /** core_0_dram0_recording_wr_1 : RO; bitpos: [0]; default: 0; + * reg_core_0_dram0_recording_wr_1 + */ + uint32_t core_0_dram0_recording_wr_1:1; + /** core_0_dram0_recording_byteen_1 : RO; bitpos: [4:1]; default: 0; + * reg_core_0_dram0_recording_byteen_1 + */ + uint32_t core_0_dram0_recording_byteen_1:4; + uint32_t reserved_5:27; + }; + uint32_t val; +} assist_debug_core_0_dram0_exception_monitor_3_reg_t; + +/** Type of core_0_dram0_exception_monitor_4 register + * exception monitor status register6 + */ +typedef union { + struct { + /** core_0_dram0_recording_addr_1 : RO; bitpos: [29:0]; default: 0; + * reg_core_0_dram0_recording_addr_1 + */ + uint32_t core_0_dram0_recording_addr_1:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} assist_debug_core_0_dram0_exception_monitor_4_reg_t; + +/** Type of core_0_dram0_exception_monitor_5 register + * exception monitor status register7 + */ +typedef union { + struct { + /** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0; + * reg_core_0_dram0_recording_pc_1 + */ + uint32_t core_0_dram0_recording_pc_1:32; + }; + uint32_t val; +} assist_debug_core_0_dram0_exception_monitor_5_reg_t; + +/** Type of core_x_iram0_dram0_exception_monitor_0 register + * exception monitor status register8 + */ +typedef union { + struct { + /** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0; + * reg_core_x_iram0_dram0_limit_cycle_0 + */ + uint32_t core_x_iram0_dram0_limit_cycle_0:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t; + +/** Type of core_x_iram0_dram0_exception_monitor_1 register + * exception monitor status register9 + */ +typedef union { + struct { + /** core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0; + * reg_core_x_iram0_dram0_limit_cycle_1 + */ + uint32_t core_x_iram0_dram0_limit_cycle_1:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t; + + +/** Group: cpu status registers */ +/** Type of core_0_lastpc_before_exception register + * cpu status register + */ +typedef union { + struct { + /** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0; + * Represents the PC of the last command before the HP CPU enters exception. + */ + uint32_t core_0_lastpc_before_exc:32; + }; + uint32_t val; +} assist_debug_core_0_lastpc_before_exception_reg_t; + +/** Type of core_0_debug_mode register + * cpu status register + */ +typedef union { + struct { + /** core_0_debug_mode : RO; bitpos: [0]; default: 0; + * Represents whether RISC-V CPU (HP CPU) is in debugging mode.\\ + * 1: In debugging mode\\ + * 0: Not in debugging mode\\ + */ + uint32_t core_0_debug_mode:1; + /** core_0_debug_module_active : RO; bitpos: [1]; default: 0; + * Represents the status of the RISC-V CPU (HP CPU) debug module.\\ + * 1: Active status\\ + * Other: Inactive status\\ + */ + uint32_t core_0_debug_module_active:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} assist_debug_core_0_debug_mode_reg_t; + + +/** Group: Configuration Registers */ +/** Type of clock_gate register + * Register clock control + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether to enable the register clock gating. \\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} assist_debug_clock_gate_reg_t; + +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 34640176; + * version register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} assist_debug_date_reg_t; + + +typedef struct { + volatile assist_debug_core_0_montr_ena_reg_t core_0_montr_ena; + volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw; + volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena; + volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr; + volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min; + volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max; + volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min; + volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max; + volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min; + volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max; + volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min; + volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max; + volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc; + volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp; + volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min; + volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max; + volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc; + volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en; + volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc; + volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp; + volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0; + volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1; + volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0; + volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1; + volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2; + volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3; + volatile assist_debug_core_0_dram0_exception_monitor_4_reg_t core_0_dram0_exception_monitor_4; + volatile assist_debug_core_0_dram0_exception_monitor_5_reg_t core_0_dram0_exception_monitor_5; + volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception; + volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode; + uint32_t reserved_078[34]; + volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0; + volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1; + volatile assist_debug_clock_gate_reg_t clock_gate; + uint32_t reserved_10c[188]; + volatile assist_debug_date_reg_t date; +} assist_debug_dev_t; + +extern assist_debug_dev_t ASSIST_DEBUG; + +#ifndef __cplusplus +_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/ecc_mult_reg.h b/components/soc/esp32c61/include/soc/ecc_mult_reg.h new file mode 100644 index 0000000000..0da5d23e77 --- /dev/null +++ b/components/soc/esp32c61/include/soc/ecc_mult_reg.h @@ -0,0 +1,208 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ECC_MULT_INT_RAW_REG register + * ECC raw interrupt status register + */ +#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc) +/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of the ECC_CALC_DONE_INT interrupt. + */ +#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S) +#define ECC_MULT_CALC_DONE_INT_RAW_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_RAW_S 0 + +/** ECC_MULT_INT_ST_REG register + * ECC masked interrupt status register + */ +#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10) +/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status of the ECC_CALC_DONE_INT interrupt. + */ +#define ECC_MULT_CALC_DONE_INT_ST (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S) +#define ECC_MULT_CALC_DONE_INT_ST_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_ST_S 0 + +/** ECC_MULT_INT_ENA_REG register + * ECC interrupt enable register + */ +#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14) +/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable the ECC_CALC_DONE_INT interrupt. + */ +#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S) +#define ECC_MULT_CALC_DONE_INT_ENA_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_ENA_S 0 + +/** ECC_MULT_INT_CLR_REG register + * ECC interrupt clear register + */ +#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18) +/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear the ECC_CALC_DONE_INT interrupt. + */ +#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S) +#define ECC_MULT_CALC_DONE_INT_CLR_V 0x00000001U +#define ECC_MULT_CALC_DONE_INT_CLR_S 0 + +/** ECC_MULT_CONF_REG register + * ECC configuration register + */ +#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c) +/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0; + * Configures whether to start calculation of ECC Accelerator. This bit will be + * self-cleared after the calculation is done. \\ + * 0: No effect\\ + * 1: Start calculation of ECC Accelerator\\ + */ +#define ECC_MULT_START (BIT(0)) +#define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S) +#define ECC_MULT_START_V 0x00000001U +#define ECC_MULT_START_S 0 +/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0; + * Configures whether to reset ECC Accelerator. \\ + * 0: No effect\\ + * 1: Reset\\ + */ +#define ECC_MULT_RESET (BIT(1)) +#define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S) +#define ECC_MULT_RESET_V 0x00000001U +#define ECC_MULT_RESET_S 1 +/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0; + * Configures the key length mode bit of ECC Accelerator. \\ + * 0: P-192\\ + * 1: P-256\\ + */ +#define ECC_MULT_KEY_LENGTH (BIT(2)) +#define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S) +#define ECC_MULT_KEY_LENGTH_V 0x00000001U +#define ECC_MULT_KEY_LENGTH_S 2 +/** ECC_MULT_MOD_BASE : R/W; bitpos: [3]; default: 0; + * Configures the mod base of mod operation, only valid in work_mode 8-11. \\ + * 0: n(order of curve)\\ + * 1: p(mod base of curve)\\ + */ +#define ECC_MULT_MOD_BASE (BIT(3)) +#define ECC_MULT_MOD_BASE_M (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S) +#define ECC_MULT_MOD_BASE_V 0x00000001U +#define ECC_MULT_MOD_BASE_S 3 +/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:4]; default: 0; + * Configures the work mode of ECC Accelerator.\\ + * 0: Point Multi mode\\ + * 1: Reserved\\ + * 2: Point Verif mode\\ + * 3: Point Verif + Multi mode\\ + * 4: Jacobian Point Multi mode\\ + * 5: Reserved\\ + * 6: Jacobian Point Verif mode\\ + * 7: Point Verif + Jacobian Point Multi mode\\ + * 8: Mod Add mode\\ + * 9. Mod Sub mode\\ + * 10: Mod Multi mode\\ + * 11: Mod Div mode\\ + */ +#define ECC_MULT_WORK_MODE 0x0000000FU +#define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S) +#define ECC_MULT_WORK_MODE_V 0x0000000FU +#define ECC_MULT_WORK_MODE_S 4 +/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [8]; default: 0; + * Configures the security mode of ECC Accelerator.\\ + * 0: no secure function enabled.\\ + * 1: enable constant-time calculation in all point multiplication modes.\\ + */ +#define ECC_MULT_SECURITY_MODE (BIT(8)) +#define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S) +#define ECC_MULT_SECURITY_MODE_V 0x00000001U +#define ECC_MULT_SECURITY_MODE_S 8 +/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0; + * Represents the verification result of ECC Accelerator, valid only when calculation + * is done. + */ +#define ECC_MULT_VERIFICATION_RESULT (BIT(29)) +#define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S) +#define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U +#define ECC_MULT_VERIFICATION_RESULT_S 29 +/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0; + * Configures whether to force on register clock gate. \\ + * 0: No effect\\ + * 1: Force on\\ + */ +#define ECC_MULT_CLK_EN (BIT(30)) +#define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S) +#define ECC_MULT_CLK_EN_V 0x00000001U +#define ECC_MULT_CLK_EN_S 30 +/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0; + * Configures whether to force on ECC memory clock gate. \\ + * 0: No effect\\ + * 1: Force on\\ + */ +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON (BIT(31)) +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S) +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V 0x00000001U +#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S 31 + +/** ECC_MULT_DATE_REG register + * Version control register + */ +#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc) +/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 37752928; + * ECC mult version control register + */ +#define ECC_MULT_DATE 0x0FFFFFFFU +#define ECC_MULT_DATE_M (ECC_MULT_DATE_V << ECC_MULT_DATE_S) +#define ECC_MULT_DATE_V 0x0FFFFFFFU +#define ECC_MULT_DATE_S 0 + +/** ECC_MULT_K_MEM register + * The memory that stores k. + */ +#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100) +#define ECC_MULT_K_MEM_SIZE_BYTES 32 + +/** ECC_MULT_PX_MEM register + * The memory that stores Px. + */ +#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120) +#define ECC_MULT_PX_MEM_SIZE_BYTES 32 + +/** ECC_MULT_PY_MEM register + * The memory that stores Py. + */ +#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140) +#define ECC_MULT_PY_MEM_SIZE_BYTES 32 + +/** ECC_MULT_QX_MEM register + * The memory that stores Qx. + */ +#define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x160) +#define ECC_MULT_QX_MEM_SIZE_BYTES 32 + +/** ECC_MULT_QY_MEM register + * The memory that stores Qy. + */ +#define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x180) +#define ECC_MULT_QY_MEM_SIZE_BYTES 32 + +/** ECC_MULT_QZ_MEM register + * The memory that stores Qz. + */ +#define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1a0) +#define ECC_MULT_QZ_MEM_SIZE_BYTES 32 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/ecc_mult_struct.h b/components/soc/esp32c61/include/soc/ecc_mult_struct.h new file mode 100644 index 0000000000..929767509e --- /dev/null +++ b/components/soc/esp32c61/include/soc/ecc_mult_struct.h @@ -0,0 +1,190 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory data */ + +/** Group: Interrupt registers */ +/** Type of int_raw register + * ECC raw interrupt status register + */ +typedef union { + struct { + /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status of the ECC_CALC_DONE_INT interrupt. + */ + uint32_t calc_done_int_raw:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_raw_reg_t; + +/** Type of int_st register + * ECC masked interrupt status register + */ +typedef union { + struct { + /** calc_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status of the ECC_CALC_DONE_INT interrupt. + */ + uint32_t calc_done_int_st:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_st_reg_t; + +/** Type of int_ena register + * ECC interrupt enable register + */ +typedef union { + struct { + /** calc_done_int_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable the ECC_CALC_DONE_INT interrupt. + */ + uint32_t calc_done_int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_ena_reg_t; + +/** Type of int_clr register + * ECC interrupt clear register + */ +typedef union { + struct { + /** calc_done_int_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear the ECC_CALC_DONE_INT interrupt. + */ + uint32_t calc_done_int_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecc_mult_int_clr_reg_t; + + +/** Group: RX Control and configuration registers */ +/** Type of conf register + * ECC configuration register + */ +typedef union { + struct { + /** start : R/W/SC; bitpos: [0]; default: 0; + * Configures whether to start calculation of ECC Accelerator. This bit will be + * self-cleared after the calculation is done. \\ + * 0: No effect\\ + * 1: Start calculation of ECC Accelerator\\ + */ + uint32_t start:1; + /** reset : WT; bitpos: [1]; default: 0; + * Configures whether to reset ECC Accelerator. \\ + * 0: No effect\\ + * 1: Reset\\ + */ + uint32_t reset:1; + /** key_length : R/W; bitpos: [2]; default: 0; + * Configures the key length mode bit of ECC Accelerator. \\ + * 0: P-192\\ + * 1: P-256\\ + */ + uint32_t key_length:1; + /** mod_base : R/W; bitpos: [3]; default: 0; + * Configures the mod base of mod operation, only valid in work_mode 8-11. \\ + * 0: n(order of curve)\\ + * 1: p(mod base of curve)\\ + */ + uint32_t mod_base:1; + /** work_mode : R/W; bitpos: [7:4]; default: 0; + * Configures the work mode of ECC Accelerator.\\ + * 0: Point Multi mode\\ + * 1: Reserved\\ + * 2: Point Verif mode\\ + * 3: Point Verif + Multi mode\\ + * 4: Jacobian Point Multi mode\\ + * 5: Reserved\\ + * 6: Jacobian Point Verif mode\\ + * 7: Point Verif + Jacobian Point Multi mode\\ + * 8: Mod Add mode\\ + * 9. Mod Sub mode\\ + * 10: Mod Multi mode\\ + * 11: Mod Div mode\\ + */ + uint32_t work_mode:4; + /** security_mode : R/W; bitpos: [8]; default: 0; + * Configures the security mode of ECC Accelerator.\\ + * 0: no secure function enabled.\\ + * 1: enable constant-time calculation in all point multiplication modes.\\ + */ + uint32_t security_mode:1; + uint32_t reserved_9:20; + /** verification_result : RO/SS; bitpos: [29]; default: 0; + * Represents the verification result of ECC Accelerator, valid only when calculation + * is done. + */ + uint32_t verification_result:1; + /** clk_en : R/W; bitpos: [30]; default: 0; + * Configures whether to force on register clock gate. \\ + * 0: No effect\\ + * 1: Force on\\ + */ + uint32_t clk_en:1; + /** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0; + * Configures whether to force on ECC memory clock gate. \\ + * 0: No effect\\ + * 1: Force on\\ + */ + uint32_t mem_clock_gate_force_on:1; + }; + uint32_t val; +} ecc_mult_conf_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 37752928; + * ECC mult version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} ecc_mult_date_reg_t; + + +typedef struct { + uint32_t reserved_000[3]; + volatile ecc_mult_int_raw_reg_t int_raw; + volatile ecc_mult_int_st_reg_t int_st; + volatile ecc_mult_int_ena_reg_t int_ena; + volatile ecc_mult_int_clr_reg_t int_clr; + volatile ecc_mult_conf_reg_t conf; + uint32_t reserved_020[55]; + volatile ecc_mult_date_reg_t date; + volatile uint32_t k[8]; + volatile uint32_t px[8]; + volatile uint32_t py[8]; + volatile uint32_t qx[8]; + volatile uint32_t qy[8]; + volatile uint32_t qz[8]; +} ecc_mult_dev_t; + +extern ecc_mult_dev_t ECC; + +#ifndef __cplusplus +_Static_assert(sizeof(ecc_mult_dev_t) == 0x1c0, "Invalid size of ecc_mult_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/ecdsa_reg.h b/components/soc/esp32c61/include/soc/ecdsa_reg.h new file mode 100644 index 0000000000..aca4b64b19 --- /dev/null +++ b/components/soc/esp32c61/include/soc/ecdsa_reg.h @@ -0,0 +1,374 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** ECDSA_CONF_REG register + * ECDSA configure register + */ +#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4) +/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0; + * The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature + * Generate Mode. 2: Export Public Key Mode. 3: invalid. + */ +#define ECDSA_WORK_MODE 0x00000003U +#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S) +#define ECDSA_WORK_MODE_V 0x00000003U +#define ECDSA_WORK_MODE_S 0 +/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0; + * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. + */ +#define ECDSA_ECC_CURVE (BIT(2)) +#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S) +#define ECDSA_ECC_CURVE_V 0x00000001U +#define ECDSA_ECC_CURVE_S 2 +/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0; + * The source of k select bit. 0: k is automatically generated by hardware. 1: k is + * written by software. + */ +#define ECDSA_SOFTWARE_SET_K (BIT(3)) +#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S) +#define ECDSA_SOFTWARE_SET_K_V 0x00000001U +#define ECDSA_SOFTWARE_SET_K_S 3 +/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0; + * The source of z select bit. 0: z is generated from SHA result. 1: z is written by + * software. + */ +#define ECDSA_SOFTWARE_SET_Z (BIT(4)) +#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S) +#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U +#define ECDSA_SOFTWARE_SET_Z_S 4 +/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0; + * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by + * deterministic derivation algorithm. + */ +#define ECDSA_DETERMINISTIC_K (BIT(5)) +#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S) +#define ECDSA_DETERMINISTIC_K_V 0x00000001U +#define ECDSA_DETERMINISTIC_K_S 5 +/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0; + * The (loop number - 1) value in the deterministic derivation algorithm to derive k. + */ +#define ECDSA_DETERMINISTIC_LOOP 0x0000FFFFU +#define ECDSA_DETERMINISTIC_LOOP_M (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S) +#define ECDSA_DETERMINISTIC_LOOP_V 0x0000FFFFU +#define ECDSA_DETERMINISTIC_LOOP_S 6 + +/** ECDSA_CLK_REG register + * ECDSA clock gate register + */ +#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8) +/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0; + * Write 1 to force on register clock gate. + */ +#define ECDSA_CLK_GATE_FORCE_ON (BIT(0)) +#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S) +#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U +#define ECDSA_CLK_GATE_FORCE_ON_S 0 + +/** ECDSA_INT_RAW_REG register + * ECDSA interrupt raw register, valid in level. + */ +#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc) +/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecdsa_prep_done_int interrupt + */ +#define ECDSA_PREP_DONE_INT_RAW (BIT(0)) +#define ECDSA_PREP_DONE_INT_RAW_M (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S) +#define ECDSA_PREP_DONE_INT_RAW_V 0x00000001U +#define ECDSA_PREP_DONE_INT_RAW_S 0 +/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the ecdsa_proc_done_int interrupt + */ +#define ECDSA_PROC_DONE_INT_RAW (BIT(1)) +#define ECDSA_PROC_DONE_INT_RAW_M (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S) +#define ECDSA_PROC_DONE_INT_RAW_V 0x00000001U +#define ECDSA_PROC_DONE_INT_RAW_S 1 +/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the ecdsa_post_done_int interrupt + */ +#define ECDSA_POST_DONE_INT_RAW (BIT(2)) +#define ECDSA_POST_DONE_INT_RAW_M (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S) +#define ECDSA_POST_DONE_INT_RAW_V 0x00000001U +#define ECDSA_POST_DONE_INT_RAW_S 2 +/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_RAW (BIT(3)) +#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S) +#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_RAW_S 3 + +/** ECDSA_INT_ST_REG register + * ECDSA interrupt status register. + */ +#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10) +/** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecdsa_prep_done_int interrupt + */ +#define ECDSA_PREP_DONE_INT_ST (BIT(0)) +#define ECDSA_PREP_DONE_INT_ST_M (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S) +#define ECDSA_PREP_DONE_INT_ST_V 0x00000001U +#define ECDSA_PREP_DONE_INT_ST_S 0 +/** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the ecdsa_proc_done_int interrupt + */ +#define ECDSA_PROC_DONE_INT_ST (BIT(1)) +#define ECDSA_PROC_DONE_INT_ST_M (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S) +#define ECDSA_PROC_DONE_INT_ST_V 0x00000001U +#define ECDSA_PROC_DONE_INT_ST_S 1 +/** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the ecdsa_post_done_int interrupt + */ +#define ECDSA_POST_DONE_INT_ST (BIT(2)) +#define ECDSA_POST_DONE_INT_ST_M (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S) +#define ECDSA_POST_DONE_INT_ST_V 0x00000001U +#define ECDSA_POST_DONE_INT_ST_S 2 +/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_ST (BIT(3)) +#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S) +#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_ST_S 3 + +/** ECDSA_INT_ENA_REG register + * ECDSA interrupt enable register. + */ +#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14) +/** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecdsa_prep_done_int interrupt + */ +#define ECDSA_PREP_DONE_INT_ENA (BIT(0)) +#define ECDSA_PREP_DONE_INT_ENA_M (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S) +#define ECDSA_PREP_DONE_INT_ENA_V 0x00000001U +#define ECDSA_PREP_DONE_INT_ENA_S 0 +/** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the ecdsa_proc_done_int interrupt + */ +#define ECDSA_PROC_DONE_INT_ENA (BIT(1)) +#define ECDSA_PROC_DONE_INT_ENA_M (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S) +#define ECDSA_PROC_DONE_INT_ENA_V 0x00000001U +#define ECDSA_PROC_DONE_INT_ENA_S 1 +/** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the ecdsa_post_done_int interrupt + */ +#define ECDSA_POST_DONE_INT_ENA (BIT(2)) +#define ECDSA_POST_DONE_INT_ENA_M (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S) +#define ECDSA_POST_DONE_INT_ENA_V 0x00000001U +#define ECDSA_POST_DONE_INT_ENA_S 2 +/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_ENA (BIT(3)) +#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S) +#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_ENA_S 3 + +/** ECDSA_INT_CLR_REG register + * ECDSA interrupt clear register. + */ +#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18) +/** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecdsa_prep_done_int interrupt + */ +#define ECDSA_PREP_DONE_INT_CLR (BIT(0)) +#define ECDSA_PREP_DONE_INT_CLR_M (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S) +#define ECDSA_PREP_DONE_INT_CLR_V 0x00000001U +#define ECDSA_PREP_DONE_INT_CLR_S 0 +/** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the ecdsa_proc_done_int interrupt + */ +#define ECDSA_PROC_DONE_INT_CLR (BIT(1)) +#define ECDSA_PROC_DONE_INT_CLR_M (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S) +#define ECDSA_PROC_DONE_INT_CLR_V 0x00000001U +#define ECDSA_PROC_DONE_INT_CLR_S 1 +/** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the ecdsa_post_done_int interrupt + */ +#define ECDSA_POST_DONE_INT_CLR (BIT(2)) +#define ECDSA_POST_DONE_INT_CLR_M (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S) +#define ECDSA_POST_DONE_INT_CLR_V 0x00000001U +#define ECDSA_POST_DONE_INT_CLR_S 2 +/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the ecdsa_sha_release_int interrupt + */ +#define ECDSA_SHA_RELEASE_INT_CLR (BIT(3)) +#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S) +#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U +#define ECDSA_SHA_RELEASE_INT_CLR_S 3 + +/** ECDSA_START_REG register + * ECDSA start register + */ +#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c) +/** ECDSA_START : WT; bitpos: [0]; default: 0; + * Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared + * after configuration. + */ +#define ECDSA_START (BIT(0)) +#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S) +#define ECDSA_START_V 0x00000001U +#define ECDSA_START_S 0 +/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0; + * Write 1 to input load done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ +#define ECDSA_LOAD_DONE (BIT(1)) +#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S) +#define ECDSA_LOAD_DONE_V 0x00000001U +#define ECDSA_LOAD_DONE_S 1 +/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0; + * Write 1 to input get done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ +#define ECDSA_GET_DONE (BIT(2)) +#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S) +#define ECDSA_GET_DONE_V 0x00000001U +#define ECDSA_GET_DONE_S 2 + +/** ECDSA_STATE_REG register + * ECDSA status register + */ +#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20) +/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0; + * The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY + * state. + */ +#define ECDSA_BUSY 0x00000003U +#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S) +#define ECDSA_BUSY_V 0x00000003U +#define ECDSA_BUSY_S 0 + +/** ECDSA_RESULT_REG register + * ECDSA result register + */ +#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24) +/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0; + * The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is + * done. + */ +#define ECDSA_OPERATION_RESULT (BIT(0)) +#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S) +#define ECDSA_OPERATION_RESULT_V 0x00000001U +#define ECDSA_OPERATION_RESULT_S 0 +/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0; + * The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the + * curve order, then actually taken k = k mod n. + */ +#define ECDSA_K_VALUE_WARNING (BIT(1)) +#define ECDSA_K_VALUE_WARNING_M (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S) +#define ECDSA_K_VALUE_WARNING_V 0x00000001U +#define ECDSA_K_VALUE_WARNING_S 1 + +/** ECDSA_DATE_REG register + * Version control register + */ +#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc) +/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 36725040; + * ECDSA version control register + */ +#define ECDSA_DATE 0x0FFFFFFFU +#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S) +#define ECDSA_DATE_V 0x0FFFFFFFU +#define ECDSA_DATE_S 0 + +/** ECDSA_SHA_MODE_REG register + * ECDSA control SHA register + */ +#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200) +/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0; + * The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. + * Others: invalid. + */ +#define ECDSA_SHA_MODE 0x00000007U +#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S) +#define ECDSA_SHA_MODE_V 0x00000007U +#define ECDSA_SHA_MODE_S 0 + +/** ECDSA_SHA_START_REG register + * ECDSA control SHA register + */ +#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210) +/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0; + * Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ +#define ECDSA_SHA_START (BIT(0)) +#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S) +#define ECDSA_SHA_START_V 0x00000001U +#define ECDSA_SHA_START_S 0 + +/** ECDSA_SHA_CONTINUE_REG register + * ECDSA control SHA register + */ +#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214) +/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0; + * Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ +#define ECDSA_SHA_CONTINUE (BIT(0)) +#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S) +#define ECDSA_SHA_CONTINUE_V 0x00000001U +#define ECDSA_SHA_CONTINUE_S 0 + +/** ECDSA_SHA_BUSY_REG register + * ECDSA status register + */ +#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218) +/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0; + * The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in + * calculation. 0: SHA is idle. + */ +#define ECDSA_SHA_BUSY (BIT(0)) +#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S) +#define ECDSA_SHA_BUSY_V 0x00000001U +#define ECDSA_SHA_BUSY_S 0 + +/** ECDSA_MESSAGE_MEM register + * The memory that stores message. + */ +#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280) +#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32 + +/** ECDSA_R_MEM register + * The memory that stores r. + */ +#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x340) +#define ECDSA_R_MEM_SIZE_BYTES 32 + +/** ECDSA_S_MEM register + * The memory that stores s. + */ +#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x360) +#define ECDSA_S_MEM_SIZE_BYTES 32 + +/** ECDSA_Z_MEM register + * The memory that stores software written z. + */ +#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x380) +#define ECDSA_Z_MEM_SIZE_BYTES 32 + +/** ECDSA_QAX_MEM register + * The memory that stores x coordinates of QA or software written k. + */ +#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x3a0) +#define ECDSA_QAX_MEM_SIZE_BYTES 32 + +/** ECDSA_QAY_MEM register + * The memory that stores y coordinates of QA. + */ +#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x3c0) +#define ECDSA_QAY_MEM_SIZE_BYTES 32 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/ecdsa_struct.h b/components/soc/esp32c61/include/soc/ecdsa_struct.h new file mode 100644 index 0000000000..bed383c9da --- /dev/null +++ b/components/soc/esp32c61/include/soc/ecdsa_struct.h @@ -0,0 +1,356 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Data Memory */ + +/** Group: Configuration registers */ +/** Type of conf register + * ECDSA configure register + */ +typedef union { + struct { + /** work_mode : R/W; bitpos: [1:0]; default: 0; + * The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature + * Generate Mode. 2: Export Public Key Mode. 3: invalid. + */ + uint32_t work_mode:2; + /** ecc_curve : R/W; bitpos: [2]; default: 0; + * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. + */ + uint32_t ecc_curve:1; + /** software_set_k : R/W; bitpos: [3]; default: 0; + * The source of k select bit. 0: k is automatically generated by hardware. 1: k is + * written by software. + */ + uint32_t software_set_k:1; + /** software_set_z : R/W; bitpos: [4]; default: 0; + * The source of z select bit. 0: z is generated from SHA result. 1: z is written by + * software. + */ + uint32_t software_set_z:1; + /** deterministic_k : R/W; bitpos: [5]; default: 0; + * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by + * deterministic derivation algorithm. + */ + uint32_t deterministic_k:1; + /** deterministic_loop : R/W; bitpos: [21:6]; default: 0; + * The (loop number - 1) value in the deterministic derivation algorithm to derive k. + */ + uint32_t deterministic_loop:16; + uint32_t reserved_22:10; + }; + uint32_t val; +} ecdsa_conf_reg_t; + +/** Type of start register + * ECDSA start register + */ +typedef union { + struct { + /** start : WT; bitpos: [0]; default: 0; + * Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared + * after configuration. + */ + uint32_t start:1; + /** load_done : WT; bitpos: [1]; default: 0; + * Write 1 to input load done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ + uint32_t load_done:1; + /** get_done : WT; bitpos: [2]; default: 0; + * Write 1 to input get done signal of ECDSA Accelerator. This bit will be + * self-cleared after configuration. + */ + uint32_t get_done:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} ecdsa_start_reg_t; + + +/** Group: Clock and reset registers */ +/** Type of clk register + * ECDSA clock gate register + */ +typedef union { + struct { + /** clk_gate_force_on : R/W; bitpos: [0]; default: 0; + * Write 1 to force on register clock gate. + */ + uint32_t clk_gate_force_on:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_clk_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * ECDSA interrupt raw register, valid in level. + */ +typedef union { + struct { + /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt status bit for the ecdsa_prep_done_int interrupt + */ + uint32_t prep_done_int_raw:1; + /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt status bit for the ecdsa_proc_done_int interrupt + */ + uint32_t proc_done_int_raw:1; + /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt status bit for the ecdsa_post_done_int interrupt + */ + uint32_t post_done_int_raw:1; + /** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt status bit for the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_raw:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ecdsa_int_raw_reg_t; + +/** Type of int_st register + * ECDSA interrupt status register. + */ +typedef union { + struct { + /** prep_done_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the ecdsa_prep_done_int interrupt + */ + uint32_t prep_done_int_st:1; + /** proc_done_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the ecdsa_proc_done_int interrupt + */ + uint32_t proc_done_int_st:1; + /** post_done_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the ecdsa_post_done_int interrupt + */ + uint32_t post_done_int_st:1; + /** sha_release_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_st:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ecdsa_int_st_reg_t; + +/** Type of int_ena register + * ECDSA interrupt enable register. + */ +typedef union { + struct { + /** prep_done_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the ecdsa_prep_done_int interrupt + */ + uint32_t prep_done_int_ena:1; + /** proc_done_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the ecdsa_proc_done_int interrupt + */ + uint32_t proc_done_int_ena:1; + /** post_done_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the ecdsa_post_done_int interrupt + */ + uint32_t post_done_int_ena:1; + /** sha_release_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ecdsa_int_ena_reg_t; + +/** Type of int_clr register + * ECDSA interrupt clear register. + */ +typedef union { + struct { + /** prep_done_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear the ecdsa_prep_done_int interrupt + */ + uint32_t prep_done_int_clr:1; + /** proc_done_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear the ecdsa_proc_done_int interrupt + */ + uint32_t proc_done_int_clr:1; + /** post_done_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear the ecdsa_post_done_int interrupt + */ + uint32_t post_done_int_clr:1; + /** sha_release_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the ecdsa_sha_release_int interrupt + */ + uint32_t sha_release_int_clr:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} ecdsa_int_clr_reg_t; + + +/** Group: Status registers */ +/** Type of state register + * ECDSA status register + */ +typedef union { + struct { + /** busy : RO; bitpos: [1:0]; default: 0; + * The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY + * state. + */ + uint32_t busy:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_state_reg_t; + + +/** Group: Result registers */ +/** Type of result register + * ECDSA result register + */ +typedef union { + struct { + /** operation_result : RO/SS; bitpos: [0]; default: 0; + * The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is + * done. + */ + uint32_t operation_result:1; + /** k_value_warning : RO/SS; bitpos: [1]; default: 0; + * The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the + * curve order, then actually taken k = k mod n. + */ + uint32_t k_value_warning:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} ecdsa_result_reg_t; + + +/** Group: SHA register */ +/** Type of sha_mode register + * ECDSA control SHA register + */ +typedef union { + struct { + /** sha_mode : R/W; bitpos: [2:0]; default: 0; + * The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. + * Others: invalid. + */ + uint32_t sha_mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} ecdsa_sha_mode_reg_t; + +/** Type of sha_start register + * ECDSA control SHA register + */ +typedef union { + struct { + /** sha_start : WT; bitpos: [0]; default: 0; + * Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ + uint32_t sha_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_sha_start_reg_t; + +/** Type of sha_continue register + * ECDSA control SHA register + */ +typedef union { + struct { + /** sha_continue : WT; bitpos: [0]; default: 0; + * Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This + * bit will be self-cleared after configuration. + */ + uint32_t sha_continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_sha_continue_reg_t; + +/** Type of sha_busy register + * ECDSA status register + */ +typedef union { + struct { + /** sha_busy : RO; bitpos: [0]; default: 0; + * The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in + * calculation. 0: SHA is idle. + */ + uint32_t sha_busy:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} ecdsa_sha_busy_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36725040; + * ECDSA version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} ecdsa_date_reg_t; + + +typedef struct { + uint32_t reserved_000; + volatile ecdsa_conf_reg_t conf; + volatile ecdsa_clk_reg_t clk; + volatile ecdsa_int_raw_reg_t int_raw; + volatile ecdsa_int_st_reg_t int_st; + volatile ecdsa_int_ena_reg_t int_ena; + volatile ecdsa_int_clr_reg_t int_clr; + volatile ecdsa_start_reg_t start; + volatile ecdsa_state_reg_t state; + volatile ecdsa_result_reg_t result; + uint32_t reserved_028[53]; + volatile ecdsa_date_reg_t date; + uint32_t reserved_100[64]; + volatile ecdsa_sha_mode_reg_t sha_mode; + uint32_t reserved_204[3]; + volatile ecdsa_sha_start_reg_t sha_start; + volatile ecdsa_sha_continue_reg_t sha_continue; + volatile ecdsa_sha_busy_reg_t sha_busy; + uint32_t reserved_21c[25]; + volatile uint32_t message[8]; + uint32_t reserved_2a0[40]; + volatile uint32_t r[8]; + volatile uint32_t s[8]; + volatile uint32_t z[8]; + volatile uint32_t qax[8]; + volatile uint32_t qay[8]; +} ecdsa_dev_t; + +extern ecdsa_dev_t ECDSA; + +#ifndef __cplusplus +_Static_assert(sizeof(ecdsa_dev_t) == 0x3e0, "Invalid size of ecdsa_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/hp_apm_reg.h b/components/soc/esp32c61/include/soc/hp_apm_reg.h new file mode 100644 index 0000000000..657d3f42c6 --- /dev/null +++ b/components/soc/esp32c61/include/soc/hp_apm_reg.h @@ -0,0 +1,1970 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HP_APM_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define HP_APM_REGION_FILTER_EN_REG (DR_REG_HP_APM_BASE + 0x0) +/** HP_APM_REGION_FILTER_EN : R/W; bitpos: [15:0]; default: 1; + * Configure bit $n (0-15) to enable region $n.\\ + * 0: disable \\ + * 1: enable \\ + */ +#define HP_APM_REGION_FILTER_EN 0x0000FFFFU +#define HP_APM_REGION_FILTER_EN_M (HP_APM_REGION_FILTER_EN_V << HP_APM_REGION_FILTER_EN_S) +#define HP_APM_REGION_FILTER_EN_V 0x0000FFFFU +#define HP_APM_REGION_FILTER_EN_S 0 + +/** HP_APM_REGION0_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION0_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4) +/** HP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 0. + */ +#define HP_APM_REGION0_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_START_M (HP_APM_REGION0_ADDR_START_V << HP_APM_REGION0_ADDR_START_S) +#define HP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_START_S 0 + +/** HP_APM_REGION0_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION0_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8) +/** HP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 0. + */ +#define HP_APM_REGION0_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_END_M (HP_APM_REGION0_ADDR_END_V << HP_APM_REGION0_ADDR_END_S) +#define HP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION0_ADDR_END_S 0 + +/** HP_APM_REGION0_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION0_ATTR_REG (DR_REG_HP_APM_BASE + 0xc) +/** HP_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 0. + */ +#define HP_APM_REGION0_R0_X (BIT(0)) +#define HP_APM_REGION0_R0_X_M (HP_APM_REGION0_R0_X_V << HP_APM_REGION0_R0_X_S) +#define HP_APM_REGION0_R0_X_V 0x00000001U +#define HP_APM_REGION0_R0_X_S 0 +/** HP_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 0. + */ +#define HP_APM_REGION0_R0_W (BIT(1)) +#define HP_APM_REGION0_R0_W_M (HP_APM_REGION0_R0_W_V << HP_APM_REGION0_R0_W_S) +#define HP_APM_REGION0_R0_W_V 0x00000001U +#define HP_APM_REGION0_R0_W_S 1 +/** HP_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 0. + */ +#define HP_APM_REGION0_R0_R (BIT(2)) +#define HP_APM_REGION0_R0_R_M (HP_APM_REGION0_R0_R_V << HP_APM_REGION0_R0_R_S) +#define HP_APM_REGION0_R0_R_V 0x00000001U +#define HP_APM_REGION0_R0_R_S 2 +/** HP_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 0. + */ +#define HP_APM_REGION0_R1_X (BIT(4)) +#define HP_APM_REGION0_R1_X_M (HP_APM_REGION0_R1_X_V << HP_APM_REGION0_R1_X_S) +#define HP_APM_REGION0_R1_X_V 0x00000001U +#define HP_APM_REGION0_R1_X_S 4 +/** HP_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 0. + */ +#define HP_APM_REGION0_R1_W (BIT(5)) +#define HP_APM_REGION0_R1_W_M (HP_APM_REGION0_R1_W_V << HP_APM_REGION0_R1_W_S) +#define HP_APM_REGION0_R1_W_V 0x00000001U +#define HP_APM_REGION0_R1_W_S 5 +/** HP_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 0. + */ +#define HP_APM_REGION0_R1_R (BIT(6)) +#define HP_APM_REGION0_R1_R_M (HP_APM_REGION0_R1_R_V << HP_APM_REGION0_R1_R_S) +#define HP_APM_REGION0_R1_R_V 0x00000001U +#define HP_APM_REGION0_R1_R_S 6 +/** HP_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 0. + */ +#define HP_APM_REGION0_R2_X (BIT(8)) +#define HP_APM_REGION0_R2_X_M (HP_APM_REGION0_R2_X_V << HP_APM_REGION0_R2_X_S) +#define HP_APM_REGION0_R2_X_V 0x00000001U +#define HP_APM_REGION0_R2_X_S 8 +/** HP_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 0. + */ +#define HP_APM_REGION0_R2_W (BIT(9)) +#define HP_APM_REGION0_R2_W_M (HP_APM_REGION0_R2_W_V << HP_APM_REGION0_R2_W_S) +#define HP_APM_REGION0_R2_W_V 0x00000001U +#define HP_APM_REGION0_R2_W_S 9 +/** HP_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 0. + */ +#define HP_APM_REGION0_R2_R (BIT(10)) +#define HP_APM_REGION0_R2_R_M (HP_APM_REGION0_R2_R_V << HP_APM_REGION0_R2_R_S) +#define HP_APM_REGION0_R2_R_V 0x00000001U +#define HP_APM_REGION0_R2_R_S 10 +/** HP_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_APM_REGION0_LOCK (BIT(11)) +#define HP_APM_REGION0_LOCK_M (HP_APM_REGION0_LOCK_V << HP_APM_REGION0_LOCK_S) +#define HP_APM_REGION0_LOCK_V 0x00000001U +#define HP_APM_REGION0_LOCK_S 11 + +/** HP_APM_REGION1_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION1_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x10) +/** HP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 1. + */ +#define HP_APM_REGION1_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_START_M (HP_APM_REGION1_ADDR_START_V << HP_APM_REGION1_ADDR_START_S) +#define HP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_START_S 0 + +/** HP_APM_REGION1_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION1_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x14) +/** HP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 1. + */ +#define HP_APM_REGION1_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_END_M (HP_APM_REGION1_ADDR_END_V << HP_APM_REGION1_ADDR_END_S) +#define HP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION1_ADDR_END_S 0 + +/** HP_APM_REGION1_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION1_ATTR_REG (DR_REG_HP_APM_BASE + 0x18) +/** HP_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 1. + */ +#define HP_APM_REGION1_R0_X (BIT(0)) +#define HP_APM_REGION1_R0_X_M (HP_APM_REGION1_R0_X_V << HP_APM_REGION1_R0_X_S) +#define HP_APM_REGION1_R0_X_V 0x00000001U +#define HP_APM_REGION1_R0_X_S 0 +/** HP_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 1. + */ +#define HP_APM_REGION1_R0_W (BIT(1)) +#define HP_APM_REGION1_R0_W_M (HP_APM_REGION1_R0_W_V << HP_APM_REGION1_R0_W_S) +#define HP_APM_REGION1_R0_W_V 0x00000001U +#define HP_APM_REGION1_R0_W_S 1 +/** HP_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 1. + */ +#define HP_APM_REGION1_R0_R (BIT(2)) +#define HP_APM_REGION1_R0_R_M (HP_APM_REGION1_R0_R_V << HP_APM_REGION1_R0_R_S) +#define HP_APM_REGION1_R0_R_V 0x00000001U +#define HP_APM_REGION1_R0_R_S 2 +/** HP_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 1. + */ +#define HP_APM_REGION1_R1_X (BIT(4)) +#define HP_APM_REGION1_R1_X_M (HP_APM_REGION1_R1_X_V << HP_APM_REGION1_R1_X_S) +#define HP_APM_REGION1_R1_X_V 0x00000001U +#define HP_APM_REGION1_R1_X_S 4 +/** HP_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 1. + */ +#define HP_APM_REGION1_R1_W (BIT(5)) +#define HP_APM_REGION1_R1_W_M (HP_APM_REGION1_R1_W_V << HP_APM_REGION1_R1_W_S) +#define HP_APM_REGION1_R1_W_V 0x00000001U +#define HP_APM_REGION1_R1_W_S 5 +/** HP_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 1. + */ +#define HP_APM_REGION1_R1_R (BIT(6)) +#define HP_APM_REGION1_R1_R_M (HP_APM_REGION1_R1_R_V << HP_APM_REGION1_R1_R_S) +#define HP_APM_REGION1_R1_R_V 0x00000001U +#define HP_APM_REGION1_R1_R_S 6 +/** HP_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 1. + */ +#define HP_APM_REGION1_R2_X (BIT(8)) +#define HP_APM_REGION1_R2_X_M (HP_APM_REGION1_R2_X_V << HP_APM_REGION1_R2_X_S) +#define HP_APM_REGION1_R2_X_V 0x00000001U +#define HP_APM_REGION1_R2_X_S 8 +/** HP_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 1. + */ +#define HP_APM_REGION1_R2_W (BIT(9)) +#define HP_APM_REGION1_R2_W_M (HP_APM_REGION1_R2_W_V << HP_APM_REGION1_R2_W_S) +#define HP_APM_REGION1_R2_W_V 0x00000001U +#define HP_APM_REGION1_R2_W_S 9 +/** HP_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 1. + */ +#define HP_APM_REGION1_R2_R (BIT(10)) +#define HP_APM_REGION1_R2_R_M (HP_APM_REGION1_R2_R_V << HP_APM_REGION1_R2_R_S) +#define HP_APM_REGION1_R2_R_V 0x00000001U +#define HP_APM_REGION1_R2_R_S 10 +/** HP_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_APM_REGION1_LOCK (BIT(11)) +#define HP_APM_REGION1_LOCK_M (HP_APM_REGION1_LOCK_V << HP_APM_REGION1_LOCK_S) +#define HP_APM_REGION1_LOCK_V 0x00000001U +#define HP_APM_REGION1_LOCK_S 11 + +/** HP_APM_REGION2_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION2_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x1c) +/** HP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 2. + */ +#define HP_APM_REGION2_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_START_M (HP_APM_REGION2_ADDR_START_V << HP_APM_REGION2_ADDR_START_S) +#define HP_APM_REGION2_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_START_S 0 + +/** HP_APM_REGION2_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION2_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x20) +/** HP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 2. + */ +#define HP_APM_REGION2_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_END_M (HP_APM_REGION2_ADDR_END_V << HP_APM_REGION2_ADDR_END_S) +#define HP_APM_REGION2_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION2_ADDR_END_S 0 + +/** HP_APM_REGION2_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION2_ATTR_REG (DR_REG_HP_APM_BASE + 0x24) +/** HP_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 2. + */ +#define HP_APM_REGION2_R0_X (BIT(0)) +#define HP_APM_REGION2_R0_X_M (HP_APM_REGION2_R0_X_V << HP_APM_REGION2_R0_X_S) +#define HP_APM_REGION2_R0_X_V 0x00000001U +#define HP_APM_REGION2_R0_X_S 0 +/** HP_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 2. + */ +#define HP_APM_REGION2_R0_W (BIT(1)) +#define HP_APM_REGION2_R0_W_M (HP_APM_REGION2_R0_W_V << HP_APM_REGION2_R0_W_S) +#define HP_APM_REGION2_R0_W_V 0x00000001U +#define HP_APM_REGION2_R0_W_S 1 +/** HP_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 2. + */ +#define HP_APM_REGION2_R0_R (BIT(2)) +#define HP_APM_REGION2_R0_R_M (HP_APM_REGION2_R0_R_V << HP_APM_REGION2_R0_R_S) +#define HP_APM_REGION2_R0_R_V 0x00000001U +#define HP_APM_REGION2_R0_R_S 2 +/** HP_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 2. + */ +#define HP_APM_REGION2_R1_X (BIT(4)) +#define HP_APM_REGION2_R1_X_M (HP_APM_REGION2_R1_X_V << HP_APM_REGION2_R1_X_S) +#define HP_APM_REGION2_R1_X_V 0x00000001U +#define HP_APM_REGION2_R1_X_S 4 +/** HP_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 2. + */ +#define HP_APM_REGION2_R1_W (BIT(5)) +#define HP_APM_REGION2_R1_W_M (HP_APM_REGION2_R1_W_V << HP_APM_REGION2_R1_W_S) +#define HP_APM_REGION2_R1_W_V 0x00000001U +#define HP_APM_REGION2_R1_W_S 5 +/** HP_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 2. + */ +#define HP_APM_REGION2_R1_R (BIT(6)) +#define HP_APM_REGION2_R1_R_M (HP_APM_REGION2_R1_R_V << HP_APM_REGION2_R1_R_S) +#define HP_APM_REGION2_R1_R_V 0x00000001U +#define HP_APM_REGION2_R1_R_S 6 +/** HP_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 2. + */ +#define HP_APM_REGION2_R2_X (BIT(8)) +#define HP_APM_REGION2_R2_X_M (HP_APM_REGION2_R2_X_V << HP_APM_REGION2_R2_X_S) +#define HP_APM_REGION2_R2_X_V 0x00000001U +#define HP_APM_REGION2_R2_X_S 8 +/** HP_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 2. + */ +#define HP_APM_REGION2_R2_W (BIT(9)) +#define HP_APM_REGION2_R2_W_M (HP_APM_REGION2_R2_W_V << HP_APM_REGION2_R2_W_S) +#define HP_APM_REGION2_R2_W_V 0x00000001U +#define HP_APM_REGION2_R2_W_S 9 +/** HP_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 2. + */ +#define HP_APM_REGION2_R2_R (BIT(10)) +#define HP_APM_REGION2_R2_R_M (HP_APM_REGION2_R2_R_V << HP_APM_REGION2_R2_R_S) +#define HP_APM_REGION2_R2_R_V 0x00000001U +#define HP_APM_REGION2_R2_R_S 10 +/** HP_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_APM_REGION2_LOCK (BIT(11)) +#define HP_APM_REGION2_LOCK_M (HP_APM_REGION2_LOCK_V << HP_APM_REGION2_LOCK_S) +#define HP_APM_REGION2_LOCK_V 0x00000001U +#define HP_APM_REGION2_LOCK_S 11 + +/** HP_APM_REGION3_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION3_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x28) +/** HP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 3. + */ +#define HP_APM_REGION3_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_START_M (HP_APM_REGION3_ADDR_START_V << HP_APM_REGION3_ADDR_START_S) +#define HP_APM_REGION3_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_START_S 0 + +/** HP_APM_REGION3_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION3_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x2c) +/** HP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 3. + */ +#define HP_APM_REGION3_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_END_M (HP_APM_REGION3_ADDR_END_V << HP_APM_REGION3_ADDR_END_S) +#define HP_APM_REGION3_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION3_ADDR_END_S 0 + +/** HP_APM_REGION3_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION3_ATTR_REG (DR_REG_HP_APM_BASE + 0x30) +/** HP_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 3. + */ +#define HP_APM_REGION3_R0_X (BIT(0)) +#define HP_APM_REGION3_R0_X_M (HP_APM_REGION3_R0_X_V << HP_APM_REGION3_R0_X_S) +#define HP_APM_REGION3_R0_X_V 0x00000001U +#define HP_APM_REGION3_R0_X_S 0 +/** HP_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 3. + */ +#define HP_APM_REGION3_R0_W (BIT(1)) +#define HP_APM_REGION3_R0_W_M (HP_APM_REGION3_R0_W_V << HP_APM_REGION3_R0_W_S) +#define HP_APM_REGION3_R0_W_V 0x00000001U +#define HP_APM_REGION3_R0_W_S 1 +/** HP_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 3. + */ +#define HP_APM_REGION3_R0_R (BIT(2)) +#define HP_APM_REGION3_R0_R_M (HP_APM_REGION3_R0_R_V << HP_APM_REGION3_R0_R_S) +#define HP_APM_REGION3_R0_R_V 0x00000001U +#define HP_APM_REGION3_R0_R_S 2 +/** HP_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 3. + */ +#define HP_APM_REGION3_R1_X (BIT(4)) +#define HP_APM_REGION3_R1_X_M (HP_APM_REGION3_R1_X_V << HP_APM_REGION3_R1_X_S) +#define HP_APM_REGION3_R1_X_V 0x00000001U +#define HP_APM_REGION3_R1_X_S 4 +/** HP_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 3. + */ +#define HP_APM_REGION3_R1_W (BIT(5)) +#define HP_APM_REGION3_R1_W_M (HP_APM_REGION3_R1_W_V << HP_APM_REGION3_R1_W_S) +#define HP_APM_REGION3_R1_W_V 0x00000001U +#define HP_APM_REGION3_R1_W_S 5 +/** HP_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 3. + */ +#define HP_APM_REGION3_R1_R (BIT(6)) +#define HP_APM_REGION3_R1_R_M (HP_APM_REGION3_R1_R_V << HP_APM_REGION3_R1_R_S) +#define HP_APM_REGION3_R1_R_V 0x00000001U +#define HP_APM_REGION3_R1_R_S 6 +/** HP_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 3. + */ +#define HP_APM_REGION3_R2_X (BIT(8)) +#define HP_APM_REGION3_R2_X_M (HP_APM_REGION3_R2_X_V << HP_APM_REGION3_R2_X_S) +#define HP_APM_REGION3_R2_X_V 0x00000001U +#define HP_APM_REGION3_R2_X_S 8 +/** HP_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 3. + */ +#define HP_APM_REGION3_R2_W (BIT(9)) +#define HP_APM_REGION3_R2_W_M (HP_APM_REGION3_R2_W_V << HP_APM_REGION3_R2_W_S) +#define HP_APM_REGION3_R2_W_V 0x00000001U +#define HP_APM_REGION3_R2_W_S 9 +/** HP_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 3. + */ +#define HP_APM_REGION3_R2_R (BIT(10)) +#define HP_APM_REGION3_R2_R_M (HP_APM_REGION3_R2_R_V << HP_APM_REGION3_R2_R_S) +#define HP_APM_REGION3_R2_R_V 0x00000001U +#define HP_APM_REGION3_R2_R_S 10 +/** HP_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_APM_REGION3_LOCK (BIT(11)) +#define HP_APM_REGION3_LOCK_M (HP_APM_REGION3_LOCK_V << HP_APM_REGION3_LOCK_S) +#define HP_APM_REGION3_LOCK_V 0x00000001U +#define HP_APM_REGION3_LOCK_S 11 + +/** HP_APM_REGION4_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION4_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x34) +/** HP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 4. + */ +#define HP_APM_REGION4_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_START_M (HP_APM_REGION4_ADDR_START_V << HP_APM_REGION4_ADDR_START_S) +#define HP_APM_REGION4_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_START_S 0 + +/** HP_APM_REGION4_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION4_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x38) +/** HP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 4. + */ +#define HP_APM_REGION4_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_END_M (HP_APM_REGION4_ADDR_END_V << HP_APM_REGION4_ADDR_END_S) +#define HP_APM_REGION4_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION4_ADDR_END_S 0 + +/** HP_APM_REGION4_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION4_ATTR_REG (DR_REG_HP_APM_BASE + 0x3c) +/** HP_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 4. + */ +#define HP_APM_REGION4_R0_X (BIT(0)) +#define HP_APM_REGION4_R0_X_M (HP_APM_REGION4_R0_X_V << HP_APM_REGION4_R0_X_S) +#define HP_APM_REGION4_R0_X_V 0x00000001U +#define HP_APM_REGION4_R0_X_S 0 +/** HP_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 4. + */ +#define HP_APM_REGION4_R0_W (BIT(1)) +#define HP_APM_REGION4_R0_W_M (HP_APM_REGION4_R0_W_V << HP_APM_REGION4_R0_W_S) +#define HP_APM_REGION4_R0_W_V 0x00000001U +#define HP_APM_REGION4_R0_W_S 1 +/** HP_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 4. + */ +#define HP_APM_REGION4_R0_R (BIT(2)) +#define HP_APM_REGION4_R0_R_M (HP_APM_REGION4_R0_R_V << HP_APM_REGION4_R0_R_S) +#define HP_APM_REGION4_R0_R_V 0x00000001U +#define HP_APM_REGION4_R0_R_S 2 +/** HP_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 4. + */ +#define HP_APM_REGION4_R1_X (BIT(4)) +#define HP_APM_REGION4_R1_X_M (HP_APM_REGION4_R1_X_V << HP_APM_REGION4_R1_X_S) +#define HP_APM_REGION4_R1_X_V 0x00000001U +#define HP_APM_REGION4_R1_X_S 4 +/** HP_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 4. + */ +#define HP_APM_REGION4_R1_W (BIT(5)) +#define HP_APM_REGION4_R1_W_M (HP_APM_REGION4_R1_W_V << HP_APM_REGION4_R1_W_S) +#define HP_APM_REGION4_R1_W_V 0x00000001U +#define HP_APM_REGION4_R1_W_S 5 +/** HP_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 4. + */ +#define HP_APM_REGION4_R1_R (BIT(6)) +#define HP_APM_REGION4_R1_R_M (HP_APM_REGION4_R1_R_V << HP_APM_REGION4_R1_R_S) +#define HP_APM_REGION4_R1_R_V 0x00000001U +#define HP_APM_REGION4_R1_R_S 6 +/** HP_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 4. + */ +#define HP_APM_REGION4_R2_X (BIT(8)) +#define HP_APM_REGION4_R2_X_M (HP_APM_REGION4_R2_X_V << HP_APM_REGION4_R2_X_S) +#define HP_APM_REGION4_R2_X_V 0x00000001U +#define HP_APM_REGION4_R2_X_S 8 +/** HP_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 4. + */ +#define HP_APM_REGION4_R2_W (BIT(9)) +#define HP_APM_REGION4_R2_W_M (HP_APM_REGION4_R2_W_V << HP_APM_REGION4_R2_W_S) +#define HP_APM_REGION4_R2_W_V 0x00000001U +#define HP_APM_REGION4_R2_W_S 9 +/** HP_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 4. + */ +#define HP_APM_REGION4_R2_R (BIT(10)) +#define HP_APM_REGION4_R2_R_M (HP_APM_REGION4_R2_R_V << HP_APM_REGION4_R2_R_S) +#define HP_APM_REGION4_R2_R_V 0x00000001U +#define HP_APM_REGION4_R2_R_S 10 +/** HP_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_APM_REGION4_LOCK (BIT(11)) +#define HP_APM_REGION4_LOCK_M (HP_APM_REGION4_LOCK_V << HP_APM_REGION4_LOCK_S) +#define HP_APM_REGION4_LOCK_V 0x00000001U +#define HP_APM_REGION4_LOCK_S 11 + +/** HP_APM_REGION5_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION5_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x40) +/** HP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 5. + */ +#define HP_APM_REGION5_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_START_M (HP_APM_REGION5_ADDR_START_V << HP_APM_REGION5_ADDR_START_S) +#define HP_APM_REGION5_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_START_S 0 + +/** HP_APM_REGION5_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION5_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x44) +/** HP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 5. + */ +#define HP_APM_REGION5_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_END_M (HP_APM_REGION5_ADDR_END_V << HP_APM_REGION5_ADDR_END_S) +#define HP_APM_REGION5_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION5_ADDR_END_S 0 + +/** HP_APM_REGION5_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION5_ATTR_REG (DR_REG_HP_APM_BASE + 0x48) +/** HP_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 5. + */ +#define HP_APM_REGION5_R0_X (BIT(0)) +#define HP_APM_REGION5_R0_X_M (HP_APM_REGION5_R0_X_V << HP_APM_REGION5_R0_X_S) +#define HP_APM_REGION5_R0_X_V 0x00000001U +#define HP_APM_REGION5_R0_X_S 0 +/** HP_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 5. + */ +#define HP_APM_REGION5_R0_W (BIT(1)) +#define HP_APM_REGION5_R0_W_M (HP_APM_REGION5_R0_W_V << HP_APM_REGION5_R0_W_S) +#define HP_APM_REGION5_R0_W_V 0x00000001U +#define HP_APM_REGION5_R0_W_S 1 +/** HP_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 5. + */ +#define HP_APM_REGION5_R0_R (BIT(2)) +#define HP_APM_REGION5_R0_R_M (HP_APM_REGION5_R0_R_V << HP_APM_REGION5_R0_R_S) +#define HP_APM_REGION5_R0_R_V 0x00000001U +#define HP_APM_REGION5_R0_R_S 2 +/** HP_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 5. + */ +#define HP_APM_REGION5_R1_X (BIT(4)) +#define HP_APM_REGION5_R1_X_M (HP_APM_REGION5_R1_X_V << HP_APM_REGION5_R1_X_S) +#define HP_APM_REGION5_R1_X_V 0x00000001U +#define HP_APM_REGION5_R1_X_S 4 +/** HP_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 5. + */ +#define HP_APM_REGION5_R1_W (BIT(5)) +#define HP_APM_REGION5_R1_W_M (HP_APM_REGION5_R1_W_V << HP_APM_REGION5_R1_W_S) +#define HP_APM_REGION5_R1_W_V 0x00000001U +#define HP_APM_REGION5_R1_W_S 5 +/** HP_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 5. + */ +#define HP_APM_REGION5_R1_R (BIT(6)) +#define HP_APM_REGION5_R1_R_M (HP_APM_REGION5_R1_R_V << HP_APM_REGION5_R1_R_S) +#define HP_APM_REGION5_R1_R_V 0x00000001U +#define HP_APM_REGION5_R1_R_S 6 +/** HP_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 5. + */ +#define HP_APM_REGION5_R2_X (BIT(8)) +#define HP_APM_REGION5_R2_X_M (HP_APM_REGION5_R2_X_V << HP_APM_REGION5_R2_X_S) +#define HP_APM_REGION5_R2_X_V 0x00000001U +#define HP_APM_REGION5_R2_X_S 8 +/** HP_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 5. + */ +#define HP_APM_REGION5_R2_W (BIT(9)) +#define HP_APM_REGION5_R2_W_M (HP_APM_REGION5_R2_W_V << HP_APM_REGION5_R2_W_S) +#define HP_APM_REGION5_R2_W_V 0x00000001U +#define HP_APM_REGION5_R2_W_S 9 +/** HP_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 5. + */ +#define HP_APM_REGION5_R2_R (BIT(10)) +#define HP_APM_REGION5_R2_R_M (HP_APM_REGION5_R2_R_V << HP_APM_REGION5_R2_R_S) +#define HP_APM_REGION5_R2_R_V 0x00000001U +#define HP_APM_REGION5_R2_R_S 10 +/** HP_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_APM_REGION5_LOCK (BIT(11)) +#define HP_APM_REGION5_LOCK_M (HP_APM_REGION5_LOCK_V << HP_APM_REGION5_LOCK_S) +#define HP_APM_REGION5_LOCK_V 0x00000001U +#define HP_APM_REGION5_LOCK_S 11 + +/** HP_APM_REGION6_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION6_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4c) +/** HP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 6. + */ +#define HP_APM_REGION6_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_START_M (HP_APM_REGION6_ADDR_START_V << HP_APM_REGION6_ADDR_START_S) +#define HP_APM_REGION6_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_START_S 0 + +/** HP_APM_REGION6_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION6_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x50) +/** HP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 6. + */ +#define HP_APM_REGION6_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_END_M (HP_APM_REGION6_ADDR_END_V << HP_APM_REGION6_ADDR_END_S) +#define HP_APM_REGION6_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION6_ADDR_END_S 0 + +/** HP_APM_REGION6_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION6_ATTR_REG (DR_REG_HP_APM_BASE + 0x54) +/** HP_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 6. + */ +#define HP_APM_REGION6_R0_X (BIT(0)) +#define HP_APM_REGION6_R0_X_M (HP_APM_REGION6_R0_X_V << HP_APM_REGION6_R0_X_S) +#define HP_APM_REGION6_R0_X_V 0x00000001U +#define HP_APM_REGION6_R0_X_S 0 +/** HP_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 6. + */ +#define HP_APM_REGION6_R0_W (BIT(1)) +#define HP_APM_REGION6_R0_W_M (HP_APM_REGION6_R0_W_V << HP_APM_REGION6_R0_W_S) +#define HP_APM_REGION6_R0_W_V 0x00000001U +#define HP_APM_REGION6_R0_W_S 1 +/** HP_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 6. + */ +#define HP_APM_REGION6_R0_R (BIT(2)) +#define HP_APM_REGION6_R0_R_M (HP_APM_REGION6_R0_R_V << HP_APM_REGION6_R0_R_S) +#define HP_APM_REGION6_R0_R_V 0x00000001U +#define HP_APM_REGION6_R0_R_S 2 +/** HP_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 6. + */ +#define HP_APM_REGION6_R1_X (BIT(4)) +#define HP_APM_REGION6_R1_X_M (HP_APM_REGION6_R1_X_V << HP_APM_REGION6_R1_X_S) +#define HP_APM_REGION6_R1_X_V 0x00000001U +#define HP_APM_REGION6_R1_X_S 4 +/** HP_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 6. + */ +#define HP_APM_REGION6_R1_W (BIT(5)) +#define HP_APM_REGION6_R1_W_M (HP_APM_REGION6_R1_W_V << HP_APM_REGION6_R1_W_S) +#define HP_APM_REGION6_R1_W_V 0x00000001U +#define HP_APM_REGION6_R1_W_S 5 +/** HP_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 6. + */ +#define HP_APM_REGION6_R1_R (BIT(6)) +#define HP_APM_REGION6_R1_R_M (HP_APM_REGION6_R1_R_V << HP_APM_REGION6_R1_R_S) +#define HP_APM_REGION6_R1_R_V 0x00000001U +#define HP_APM_REGION6_R1_R_S 6 +/** HP_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 6. + */ +#define HP_APM_REGION6_R2_X (BIT(8)) +#define HP_APM_REGION6_R2_X_M (HP_APM_REGION6_R2_X_V << HP_APM_REGION6_R2_X_S) +#define HP_APM_REGION6_R2_X_V 0x00000001U +#define HP_APM_REGION6_R2_X_S 8 +/** HP_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 6. + */ +#define HP_APM_REGION6_R2_W (BIT(9)) +#define HP_APM_REGION6_R2_W_M (HP_APM_REGION6_R2_W_V << HP_APM_REGION6_R2_W_S) +#define HP_APM_REGION6_R2_W_V 0x00000001U +#define HP_APM_REGION6_R2_W_S 9 +/** HP_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 6. + */ +#define HP_APM_REGION6_R2_R (BIT(10)) +#define HP_APM_REGION6_R2_R_M (HP_APM_REGION6_R2_R_V << HP_APM_REGION6_R2_R_S) +#define HP_APM_REGION6_R2_R_V 0x00000001U +#define HP_APM_REGION6_R2_R_S 10 +/** HP_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_APM_REGION6_LOCK (BIT(11)) +#define HP_APM_REGION6_LOCK_M (HP_APM_REGION6_LOCK_V << HP_APM_REGION6_LOCK_S) +#define HP_APM_REGION6_LOCK_V 0x00000001U +#define HP_APM_REGION6_LOCK_S 11 + +/** HP_APM_REGION7_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION7_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x58) +/** HP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 7. + */ +#define HP_APM_REGION7_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_START_M (HP_APM_REGION7_ADDR_START_V << HP_APM_REGION7_ADDR_START_S) +#define HP_APM_REGION7_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_START_S 0 + +/** HP_APM_REGION7_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION7_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x5c) +/** HP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 7. + */ +#define HP_APM_REGION7_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_END_M (HP_APM_REGION7_ADDR_END_V << HP_APM_REGION7_ADDR_END_S) +#define HP_APM_REGION7_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION7_ADDR_END_S 0 + +/** HP_APM_REGION7_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION7_ATTR_REG (DR_REG_HP_APM_BASE + 0x60) +/** HP_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 7. + */ +#define HP_APM_REGION7_R0_X (BIT(0)) +#define HP_APM_REGION7_R0_X_M (HP_APM_REGION7_R0_X_V << HP_APM_REGION7_R0_X_S) +#define HP_APM_REGION7_R0_X_V 0x00000001U +#define HP_APM_REGION7_R0_X_S 0 +/** HP_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 7. + */ +#define HP_APM_REGION7_R0_W (BIT(1)) +#define HP_APM_REGION7_R0_W_M (HP_APM_REGION7_R0_W_V << HP_APM_REGION7_R0_W_S) +#define HP_APM_REGION7_R0_W_V 0x00000001U +#define HP_APM_REGION7_R0_W_S 1 +/** HP_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 7. + */ +#define HP_APM_REGION7_R0_R (BIT(2)) +#define HP_APM_REGION7_R0_R_M (HP_APM_REGION7_R0_R_V << HP_APM_REGION7_R0_R_S) +#define HP_APM_REGION7_R0_R_V 0x00000001U +#define HP_APM_REGION7_R0_R_S 2 +/** HP_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 7. + */ +#define HP_APM_REGION7_R1_X (BIT(4)) +#define HP_APM_REGION7_R1_X_M (HP_APM_REGION7_R1_X_V << HP_APM_REGION7_R1_X_S) +#define HP_APM_REGION7_R1_X_V 0x00000001U +#define HP_APM_REGION7_R1_X_S 4 +/** HP_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 7. + */ +#define HP_APM_REGION7_R1_W (BIT(5)) +#define HP_APM_REGION7_R1_W_M (HP_APM_REGION7_R1_W_V << HP_APM_REGION7_R1_W_S) +#define HP_APM_REGION7_R1_W_V 0x00000001U +#define HP_APM_REGION7_R1_W_S 5 +/** HP_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 7. + */ +#define HP_APM_REGION7_R1_R (BIT(6)) +#define HP_APM_REGION7_R1_R_M (HP_APM_REGION7_R1_R_V << HP_APM_REGION7_R1_R_S) +#define HP_APM_REGION7_R1_R_V 0x00000001U +#define HP_APM_REGION7_R1_R_S 6 +/** HP_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 7. + */ +#define HP_APM_REGION7_R2_X (BIT(8)) +#define HP_APM_REGION7_R2_X_M (HP_APM_REGION7_R2_X_V << HP_APM_REGION7_R2_X_S) +#define HP_APM_REGION7_R2_X_V 0x00000001U +#define HP_APM_REGION7_R2_X_S 8 +/** HP_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 7. + */ +#define HP_APM_REGION7_R2_W (BIT(9)) +#define HP_APM_REGION7_R2_W_M (HP_APM_REGION7_R2_W_V << HP_APM_REGION7_R2_W_S) +#define HP_APM_REGION7_R2_W_V 0x00000001U +#define HP_APM_REGION7_R2_W_S 9 +/** HP_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 7. + */ +#define HP_APM_REGION7_R2_R (BIT(10)) +#define HP_APM_REGION7_R2_R_M (HP_APM_REGION7_R2_R_V << HP_APM_REGION7_R2_R_S) +#define HP_APM_REGION7_R2_R_V 0x00000001U +#define HP_APM_REGION7_R2_R_S 10 +/** HP_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_APM_REGION7_LOCK (BIT(11)) +#define HP_APM_REGION7_LOCK_M (HP_APM_REGION7_LOCK_V << HP_APM_REGION7_LOCK_S) +#define HP_APM_REGION7_LOCK_V 0x00000001U +#define HP_APM_REGION7_LOCK_S 11 + +/** HP_APM_REGION8_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION8_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x64) +/** HP_APM_REGION8_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 8. + */ +#define HP_APM_REGION8_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_START_M (HP_APM_REGION8_ADDR_START_V << HP_APM_REGION8_ADDR_START_S) +#define HP_APM_REGION8_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_START_S 0 + +/** HP_APM_REGION8_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION8_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x68) +/** HP_APM_REGION8_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 8. + */ +#define HP_APM_REGION8_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_END_M (HP_APM_REGION8_ADDR_END_V << HP_APM_REGION8_ADDR_END_S) +#define HP_APM_REGION8_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION8_ADDR_END_S 0 + +/** HP_APM_REGION8_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION8_ATTR_REG (DR_REG_HP_APM_BASE + 0x6c) +/** HP_APM_REGION8_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 8. + */ +#define HP_APM_REGION8_R0_X (BIT(0)) +#define HP_APM_REGION8_R0_X_M (HP_APM_REGION8_R0_X_V << HP_APM_REGION8_R0_X_S) +#define HP_APM_REGION8_R0_X_V 0x00000001U +#define HP_APM_REGION8_R0_X_S 0 +/** HP_APM_REGION8_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 8. + */ +#define HP_APM_REGION8_R0_W (BIT(1)) +#define HP_APM_REGION8_R0_W_M (HP_APM_REGION8_R0_W_V << HP_APM_REGION8_R0_W_S) +#define HP_APM_REGION8_R0_W_V 0x00000001U +#define HP_APM_REGION8_R0_W_S 1 +/** HP_APM_REGION8_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 8. + */ +#define HP_APM_REGION8_R0_R (BIT(2)) +#define HP_APM_REGION8_R0_R_M (HP_APM_REGION8_R0_R_V << HP_APM_REGION8_R0_R_S) +#define HP_APM_REGION8_R0_R_V 0x00000001U +#define HP_APM_REGION8_R0_R_S 2 +/** HP_APM_REGION8_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 8. + */ +#define HP_APM_REGION8_R1_X (BIT(4)) +#define HP_APM_REGION8_R1_X_M (HP_APM_REGION8_R1_X_V << HP_APM_REGION8_R1_X_S) +#define HP_APM_REGION8_R1_X_V 0x00000001U +#define HP_APM_REGION8_R1_X_S 4 +/** HP_APM_REGION8_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 8. + */ +#define HP_APM_REGION8_R1_W (BIT(5)) +#define HP_APM_REGION8_R1_W_M (HP_APM_REGION8_R1_W_V << HP_APM_REGION8_R1_W_S) +#define HP_APM_REGION8_R1_W_V 0x00000001U +#define HP_APM_REGION8_R1_W_S 5 +/** HP_APM_REGION8_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 8. + */ +#define HP_APM_REGION8_R1_R (BIT(6)) +#define HP_APM_REGION8_R1_R_M (HP_APM_REGION8_R1_R_V << HP_APM_REGION8_R1_R_S) +#define HP_APM_REGION8_R1_R_V 0x00000001U +#define HP_APM_REGION8_R1_R_S 6 +/** HP_APM_REGION8_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 8. + */ +#define HP_APM_REGION8_R2_X (BIT(8)) +#define HP_APM_REGION8_R2_X_M (HP_APM_REGION8_R2_X_V << HP_APM_REGION8_R2_X_S) +#define HP_APM_REGION8_R2_X_V 0x00000001U +#define HP_APM_REGION8_R2_X_S 8 +/** HP_APM_REGION8_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 8. + */ +#define HP_APM_REGION8_R2_W (BIT(9)) +#define HP_APM_REGION8_R2_W_M (HP_APM_REGION8_R2_W_V << HP_APM_REGION8_R2_W_S) +#define HP_APM_REGION8_R2_W_V 0x00000001U +#define HP_APM_REGION8_R2_W_S 9 +/** HP_APM_REGION8_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 8. + */ +#define HP_APM_REGION8_R2_R (BIT(10)) +#define HP_APM_REGION8_R2_R_M (HP_APM_REGION8_R2_R_V << HP_APM_REGION8_R2_R_S) +#define HP_APM_REGION8_R2_R_V 0x00000001U +#define HP_APM_REGION8_R2_R_S 10 +/** HP_APM_REGION8_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_APM_REGION8_LOCK (BIT(11)) +#define HP_APM_REGION8_LOCK_M (HP_APM_REGION8_LOCK_V << HP_APM_REGION8_LOCK_S) +#define HP_APM_REGION8_LOCK_V 0x00000001U +#define HP_APM_REGION8_LOCK_S 11 + +/** HP_APM_REGION9_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION9_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x70) +/** HP_APM_REGION9_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 9. + */ +#define HP_APM_REGION9_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_START_M (HP_APM_REGION9_ADDR_START_V << HP_APM_REGION9_ADDR_START_S) +#define HP_APM_REGION9_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_START_S 0 + +/** HP_APM_REGION9_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION9_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x74) +/** HP_APM_REGION9_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 9. + */ +#define HP_APM_REGION9_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_END_M (HP_APM_REGION9_ADDR_END_V << HP_APM_REGION9_ADDR_END_S) +#define HP_APM_REGION9_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION9_ADDR_END_S 0 + +/** HP_APM_REGION9_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION9_ATTR_REG (DR_REG_HP_APM_BASE + 0x78) +/** HP_APM_REGION9_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 9. + */ +#define HP_APM_REGION9_R0_X (BIT(0)) +#define HP_APM_REGION9_R0_X_M (HP_APM_REGION9_R0_X_V << HP_APM_REGION9_R0_X_S) +#define HP_APM_REGION9_R0_X_V 0x00000001U +#define HP_APM_REGION9_R0_X_S 0 +/** HP_APM_REGION9_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 9. + */ +#define HP_APM_REGION9_R0_W (BIT(1)) +#define HP_APM_REGION9_R0_W_M (HP_APM_REGION9_R0_W_V << HP_APM_REGION9_R0_W_S) +#define HP_APM_REGION9_R0_W_V 0x00000001U +#define HP_APM_REGION9_R0_W_S 1 +/** HP_APM_REGION9_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 9. + */ +#define HP_APM_REGION9_R0_R (BIT(2)) +#define HP_APM_REGION9_R0_R_M (HP_APM_REGION9_R0_R_V << HP_APM_REGION9_R0_R_S) +#define HP_APM_REGION9_R0_R_V 0x00000001U +#define HP_APM_REGION9_R0_R_S 2 +/** HP_APM_REGION9_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 9. + */ +#define HP_APM_REGION9_R1_X (BIT(4)) +#define HP_APM_REGION9_R1_X_M (HP_APM_REGION9_R1_X_V << HP_APM_REGION9_R1_X_S) +#define HP_APM_REGION9_R1_X_V 0x00000001U +#define HP_APM_REGION9_R1_X_S 4 +/** HP_APM_REGION9_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 9. + */ +#define HP_APM_REGION9_R1_W (BIT(5)) +#define HP_APM_REGION9_R1_W_M (HP_APM_REGION9_R1_W_V << HP_APM_REGION9_R1_W_S) +#define HP_APM_REGION9_R1_W_V 0x00000001U +#define HP_APM_REGION9_R1_W_S 5 +/** HP_APM_REGION9_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 9. + */ +#define HP_APM_REGION9_R1_R (BIT(6)) +#define HP_APM_REGION9_R1_R_M (HP_APM_REGION9_R1_R_V << HP_APM_REGION9_R1_R_S) +#define HP_APM_REGION9_R1_R_V 0x00000001U +#define HP_APM_REGION9_R1_R_S 6 +/** HP_APM_REGION9_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 9. + */ +#define HP_APM_REGION9_R2_X (BIT(8)) +#define HP_APM_REGION9_R2_X_M (HP_APM_REGION9_R2_X_V << HP_APM_REGION9_R2_X_S) +#define HP_APM_REGION9_R2_X_V 0x00000001U +#define HP_APM_REGION9_R2_X_S 8 +/** HP_APM_REGION9_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 9. + */ +#define HP_APM_REGION9_R2_W (BIT(9)) +#define HP_APM_REGION9_R2_W_M (HP_APM_REGION9_R2_W_V << HP_APM_REGION9_R2_W_S) +#define HP_APM_REGION9_R2_W_V 0x00000001U +#define HP_APM_REGION9_R2_W_S 9 +/** HP_APM_REGION9_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 9. + */ +#define HP_APM_REGION9_R2_R (BIT(10)) +#define HP_APM_REGION9_R2_R_M (HP_APM_REGION9_R2_R_V << HP_APM_REGION9_R2_R_S) +#define HP_APM_REGION9_R2_R_V 0x00000001U +#define HP_APM_REGION9_R2_R_S 10 +/** HP_APM_REGION9_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_APM_REGION9_LOCK (BIT(11)) +#define HP_APM_REGION9_LOCK_M (HP_APM_REGION9_LOCK_V << HP_APM_REGION9_LOCK_S) +#define HP_APM_REGION9_LOCK_V 0x00000001U +#define HP_APM_REGION9_LOCK_S 11 + +/** HP_APM_REGION10_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION10_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x7c) +/** HP_APM_REGION10_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 10. + */ +#define HP_APM_REGION10_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_START_M (HP_APM_REGION10_ADDR_START_V << HP_APM_REGION10_ADDR_START_S) +#define HP_APM_REGION10_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_START_S 0 + +/** HP_APM_REGION10_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION10_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x80) +/** HP_APM_REGION10_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 10. + */ +#define HP_APM_REGION10_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_END_M (HP_APM_REGION10_ADDR_END_V << HP_APM_REGION10_ADDR_END_S) +#define HP_APM_REGION10_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION10_ADDR_END_S 0 + +/** HP_APM_REGION10_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION10_ATTR_REG (DR_REG_HP_APM_BASE + 0x84) +/** HP_APM_REGION10_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 10. + */ +#define HP_APM_REGION10_R0_X (BIT(0)) +#define HP_APM_REGION10_R0_X_M (HP_APM_REGION10_R0_X_V << HP_APM_REGION10_R0_X_S) +#define HP_APM_REGION10_R0_X_V 0x00000001U +#define HP_APM_REGION10_R0_X_S 0 +/** HP_APM_REGION10_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 10. + */ +#define HP_APM_REGION10_R0_W (BIT(1)) +#define HP_APM_REGION10_R0_W_M (HP_APM_REGION10_R0_W_V << HP_APM_REGION10_R0_W_S) +#define HP_APM_REGION10_R0_W_V 0x00000001U +#define HP_APM_REGION10_R0_W_S 1 +/** HP_APM_REGION10_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 10. + */ +#define HP_APM_REGION10_R0_R (BIT(2)) +#define HP_APM_REGION10_R0_R_M (HP_APM_REGION10_R0_R_V << HP_APM_REGION10_R0_R_S) +#define HP_APM_REGION10_R0_R_V 0x00000001U +#define HP_APM_REGION10_R0_R_S 2 +/** HP_APM_REGION10_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 10. + */ +#define HP_APM_REGION10_R1_X (BIT(4)) +#define HP_APM_REGION10_R1_X_M (HP_APM_REGION10_R1_X_V << HP_APM_REGION10_R1_X_S) +#define HP_APM_REGION10_R1_X_V 0x00000001U +#define HP_APM_REGION10_R1_X_S 4 +/** HP_APM_REGION10_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 10. + */ +#define HP_APM_REGION10_R1_W (BIT(5)) +#define HP_APM_REGION10_R1_W_M (HP_APM_REGION10_R1_W_V << HP_APM_REGION10_R1_W_S) +#define HP_APM_REGION10_R1_W_V 0x00000001U +#define HP_APM_REGION10_R1_W_S 5 +/** HP_APM_REGION10_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 10. + */ +#define HP_APM_REGION10_R1_R (BIT(6)) +#define HP_APM_REGION10_R1_R_M (HP_APM_REGION10_R1_R_V << HP_APM_REGION10_R1_R_S) +#define HP_APM_REGION10_R1_R_V 0x00000001U +#define HP_APM_REGION10_R1_R_S 6 +/** HP_APM_REGION10_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 10. + */ +#define HP_APM_REGION10_R2_X (BIT(8)) +#define HP_APM_REGION10_R2_X_M (HP_APM_REGION10_R2_X_V << HP_APM_REGION10_R2_X_S) +#define HP_APM_REGION10_R2_X_V 0x00000001U +#define HP_APM_REGION10_R2_X_S 8 +/** HP_APM_REGION10_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 10. + */ +#define HP_APM_REGION10_R2_W (BIT(9)) +#define HP_APM_REGION10_R2_W_M (HP_APM_REGION10_R2_W_V << HP_APM_REGION10_R2_W_S) +#define HP_APM_REGION10_R2_W_V 0x00000001U +#define HP_APM_REGION10_R2_W_S 9 +/** HP_APM_REGION10_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 10. + */ +#define HP_APM_REGION10_R2_R (BIT(10)) +#define HP_APM_REGION10_R2_R_M (HP_APM_REGION10_R2_R_V << HP_APM_REGION10_R2_R_S) +#define HP_APM_REGION10_R2_R_V 0x00000001U +#define HP_APM_REGION10_R2_R_S 10 +/** HP_APM_REGION10_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_APM_REGION10_LOCK (BIT(11)) +#define HP_APM_REGION10_LOCK_M (HP_APM_REGION10_LOCK_V << HP_APM_REGION10_LOCK_S) +#define HP_APM_REGION10_LOCK_V 0x00000001U +#define HP_APM_REGION10_LOCK_S 11 + +/** HP_APM_REGION11_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION11_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x88) +/** HP_APM_REGION11_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 11. + */ +#define HP_APM_REGION11_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_START_M (HP_APM_REGION11_ADDR_START_V << HP_APM_REGION11_ADDR_START_S) +#define HP_APM_REGION11_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_START_S 0 + +/** HP_APM_REGION11_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION11_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8c) +/** HP_APM_REGION11_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 11. + */ +#define HP_APM_REGION11_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_END_M (HP_APM_REGION11_ADDR_END_V << HP_APM_REGION11_ADDR_END_S) +#define HP_APM_REGION11_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION11_ADDR_END_S 0 + +/** HP_APM_REGION11_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION11_ATTR_REG (DR_REG_HP_APM_BASE + 0x90) +/** HP_APM_REGION11_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 11. + */ +#define HP_APM_REGION11_R0_X (BIT(0)) +#define HP_APM_REGION11_R0_X_M (HP_APM_REGION11_R0_X_V << HP_APM_REGION11_R0_X_S) +#define HP_APM_REGION11_R0_X_V 0x00000001U +#define HP_APM_REGION11_R0_X_S 0 +/** HP_APM_REGION11_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 11. + */ +#define HP_APM_REGION11_R0_W (BIT(1)) +#define HP_APM_REGION11_R0_W_M (HP_APM_REGION11_R0_W_V << HP_APM_REGION11_R0_W_S) +#define HP_APM_REGION11_R0_W_V 0x00000001U +#define HP_APM_REGION11_R0_W_S 1 +/** HP_APM_REGION11_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 11. + */ +#define HP_APM_REGION11_R0_R (BIT(2)) +#define HP_APM_REGION11_R0_R_M (HP_APM_REGION11_R0_R_V << HP_APM_REGION11_R0_R_S) +#define HP_APM_REGION11_R0_R_V 0x00000001U +#define HP_APM_REGION11_R0_R_S 2 +/** HP_APM_REGION11_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 11. + */ +#define HP_APM_REGION11_R1_X (BIT(4)) +#define HP_APM_REGION11_R1_X_M (HP_APM_REGION11_R1_X_V << HP_APM_REGION11_R1_X_S) +#define HP_APM_REGION11_R1_X_V 0x00000001U +#define HP_APM_REGION11_R1_X_S 4 +/** HP_APM_REGION11_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 11. + */ +#define HP_APM_REGION11_R1_W (BIT(5)) +#define HP_APM_REGION11_R1_W_M (HP_APM_REGION11_R1_W_V << HP_APM_REGION11_R1_W_S) +#define HP_APM_REGION11_R1_W_V 0x00000001U +#define HP_APM_REGION11_R1_W_S 5 +/** HP_APM_REGION11_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 11. + */ +#define HP_APM_REGION11_R1_R (BIT(6)) +#define HP_APM_REGION11_R1_R_M (HP_APM_REGION11_R1_R_V << HP_APM_REGION11_R1_R_S) +#define HP_APM_REGION11_R1_R_V 0x00000001U +#define HP_APM_REGION11_R1_R_S 6 +/** HP_APM_REGION11_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 11. + */ +#define HP_APM_REGION11_R2_X (BIT(8)) +#define HP_APM_REGION11_R2_X_M (HP_APM_REGION11_R2_X_V << HP_APM_REGION11_R2_X_S) +#define HP_APM_REGION11_R2_X_V 0x00000001U +#define HP_APM_REGION11_R2_X_S 8 +/** HP_APM_REGION11_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 11. + */ +#define HP_APM_REGION11_R2_W (BIT(9)) +#define HP_APM_REGION11_R2_W_M (HP_APM_REGION11_R2_W_V << HP_APM_REGION11_R2_W_S) +#define HP_APM_REGION11_R2_W_V 0x00000001U +#define HP_APM_REGION11_R2_W_S 9 +/** HP_APM_REGION11_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 11. + */ +#define HP_APM_REGION11_R2_R (BIT(10)) +#define HP_APM_REGION11_R2_R_M (HP_APM_REGION11_R2_R_V << HP_APM_REGION11_R2_R_S) +#define HP_APM_REGION11_R2_R_V 0x00000001U +#define HP_APM_REGION11_R2_R_S 10 +/** HP_APM_REGION11_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_APM_REGION11_LOCK (BIT(11)) +#define HP_APM_REGION11_LOCK_M (HP_APM_REGION11_LOCK_V << HP_APM_REGION11_LOCK_S) +#define HP_APM_REGION11_LOCK_V 0x00000001U +#define HP_APM_REGION11_LOCK_S 11 + +/** HP_APM_REGION12_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION12_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x94) +/** HP_APM_REGION12_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 12. + */ +#define HP_APM_REGION12_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_START_M (HP_APM_REGION12_ADDR_START_V << HP_APM_REGION12_ADDR_START_S) +#define HP_APM_REGION12_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_START_S 0 + +/** HP_APM_REGION12_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION12_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x98) +/** HP_APM_REGION12_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 12. + */ +#define HP_APM_REGION12_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_END_M (HP_APM_REGION12_ADDR_END_V << HP_APM_REGION12_ADDR_END_S) +#define HP_APM_REGION12_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION12_ADDR_END_S 0 + +/** HP_APM_REGION12_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION12_ATTR_REG (DR_REG_HP_APM_BASE + 0x9c) +/** HP_APM_REGION12_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 12. + */ +#define HP_APM_REGION12_R0_X (BIT(0)) +#define HP_APM_REGION12_R0_X_M (HP_APM_REGION12_R0_X_V << HP_APM_REGION12_R0_X_S) +#define HP_APM_REGION12_R0_X_V 0x00000001U +#define HP_APM_REGION12_R0_X_S 0 +/** HP_APM_REGION12_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 12. + */ +#define HP_APM_REGION12_R0_W (BIT(1)) +#define HP_APM_REGION12_R0_W_M (HP_APM_REGION12_R0_W_V << HP_APM_REGION12_R0_W_S) +#define HP_APM_REGION12_R0_W_V 0x00000001U +#define HP_APM_REGION12_R0_W_S 1 +/** HP_APM_REGION12_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 12. + */ +#define HP_APM_REGION12_R0_R (BIT(2)) +#define HP_APM_REGION12_R0_R_M (HP_APM_REGION12_R0_R_V << HP_APM_REGION12_R0_R_S) +#define HP_APM_REGION12_R0_R_V 0x00000001U +#define HP_APM_REGION12_R0_R_S 2 +/** HP_APM_REGION12_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 12. + */ +#define HP_APM_REGION12_R1_X (BIT(4)) +#define HP_APM_REGION12_R1_X_M (HP_APM_REGION12_R1_X_V << HP_APM_REGION12_R1_X_S) +#define HP_APM_REGION12_R1_X_V 0x00000001U +#define HP_APM_REGION12_R1_X_S 4 +/** HP_APM_REGION12_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 12. + */ +#define HP_APM_REGION12_R1_W (BIT(5)) +#define HP_APM_REGION12_R1_W_M (HP_APM_REGION12_R1_W_V << HP_APM_REGION12_R1_W_S) +#define HP_APM_REGION12_R1_W_V 0x00000001U +#define HP_APM_REGION12_R1_W_S 5 +/** HP_APM_REGION12_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 12. + */ +#define HP_APM_REGION12_R1_R (BIT(6)) +#define HP_APM_REGION12_R1_R_M (HP_APM_REGION12_R1_R_V << HP_APM_REGION12_R1_R_S) +#define HP_APM_REGION12_R1_R_V 0x00000001U +#define HP_APM_REGION12_R1_R_S 6 +/** HP_APM_REGION12_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 12. + */ +#define HP_APM_REGION12_R2_X (BIT(8)) +#define HP_APM_REGION12_R2_X_M (HP_APM_REGION12_R2_X_V << HP_APM_REGION12_R2_X_S) +#define HP_APM_REGION12_R2_X_V 0x00000001U +#define HP_APM_REGION12_R2_X_S 8 +/** HP_APM_REGION12_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 12. + */ +#define HP_APM_REGION12_R2_W (BIT(9)) +#define HP_APM_REGION12_R2_W_M (HP_APM_REGION12_R2_W_V << HP_APM_REGION12_R2_W_S) +#define HP_APM_REGION12_R2_W_V 0x00000001U +#define HP_APM_REGION12_R2_W_S 9 +/** HP_APM_REGION12_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 12. + */ +#define HP_APM_REGION12_R2_R (BIT(10)) +#define HP_APM_REGION12_R2_R_M (HP_APM_REGION12_R2_R_V << HP_APM_REGION12_R2_R_S) +#define HP_APM_REGION12_R2_R_V 0x00000001U +#define HP_APM_REGION12_R2_R_S 10 +/** HP_APM_REGION12_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_APM_REGION12_LOCK (BIT(11)) +#define HP_APM_REGION12_LOCK_M (HP_APM_REGION12_LOCK_V << HP_APM_REGION12_LOCK_S) +#define HP_APM_REGION12_LOCK_V 0x00000001U +#define HP_APM_REGION12_LOCK_S 11 + +/** HP_APM_REGION13_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION13_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xa0) +/** HP_APM_REGION13_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 13. + */ +#define HP_APM_REGION13_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_START_M (HP_APM_REGION13_ADDR_START_V << HP_APM_REGION13_ADDR_START_S) +#define HP_APM_REGION13_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_START_S 0 + +/** HP_APM_REGION13_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION13_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xa4) +/** HP_APM_REGION13_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 13. + */ +#define HP_APM_REGION13_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_END_M (HP_APM_REGION13_ADDR_END_V << HP_APM_REGION13_ADDR_END_S) +#define HP_APM_REGION13_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION13_ADDR_END_S 0 + +/** HP_APM_REGION13_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION13_ATTR_REG (DR_REG_HP_APM_BASE + 0xa8) +/** HP_APM_REGION13_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 13. + */ +#define HP_APM_REGION13_R0_X (BIT(0)) +#define HP_APM_REGION13_R0_X_M (HP_APM_REGION13_R0_X_V << HP_APM_REGION13_R0_X_S) +#define HP_APM_REGION13_R0_X_V 0x00000001U +#define HP_APM_REGION13_R0_X_S 0 +/** HP_APM_REGION13_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 13. + */ +#define HP_APM_REGION13_R0_W (BIT(1)) +#define HP_APM_REGION13_R0_W_M (HP_APM_REGION13_R0_W_V << HP_APM_REGION13_R0_W_S) +#define HP_APM_REGION13_R0_W_V 0x00000001U +#define HP_APM_REGION13_R0_W_S 1 +/** HP_APM_REGION13_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 13. + */ +#define HP_APM_REGION13_R0_R (BIT(2)) +#define HP_APM_REGION13_R0_R_M (HP_APM_REGION13_R0_R_V << HP_APM_REGION13_R0_R_S) +#define HP_APM_REGION13_R0_R_V 0x00000001U +#define HP_APM_REGION13_R0_R_S 2 +/** HP_APM_REGION13_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 13. + */ +#define HP_APM_REGION13_R1_X (BIT(4)) +#define HP_APM_REGION13_R1_X_M (HP_APM_REGION13_R1_X_V << HP_APM_REGION13_R1_X_S) +#define HP_APM_REGION13_R1_X_V 0x00000001U +#define HP_APM_REGION13_R1_X_S 4 +/** HP_APM_REGION13_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 13. + */ +#define HP_APM_REGION13_R1_W (BIT(5)) +#define HP_APM_REGION13_R1_W_M (HP_APM_REGION13_R1_W_V << HP_APM_REGION13_R1_W_S) +#define HP_APM_REGION13_R1_W_V 0x00000001U +#define HP_APM_REGION13_R1_W_S 5 +/** HP_APM_REGION13_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 13. + */ +#define HP_APM_REGION13_R1_R (BIT(6)) +#define HP_APM_REGION13_R1_R_M (HP_APM_REGION13_R1_R_V << HP_APM_REGION13_R1_R_S) +#define HP_APM_REGION13_R1_R_V 0x00000001U +#define HP_APM_REGION13_R1_R_S 6 +/** HP_APM_REGION13_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 13. + */ +#define HP_APM_REGION13_R2_X (BIT(8)) +#define HP_APM_REGION13_R2_X_M (HP_APM_REGION13_R2_X_V << HP_APM_REGION13_R2_X_S) +#define HP_APM_REGION13_R2_X_V 0x00000001U +#define HP_APM_REGION13_R2_X_S 8 +/** HP_APM_REGION13_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 13. + */ +#define HP_APM_REGION13_R2_W (BIT(9)) +#define HP_APM_REGION13_R2_W_M (HP_APM_REGION13_R2_W_V << HP_APM_REGION13_R2_W_S) +#define HP_APM_REGION13_R2_W_V 0x00000001U +#define HP_APM_REGION13_R2_W_S 9 +/** HP_APM_REGION13_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 13. + */ +#define HP_APM_REGION13_R2_R (BIT(10)) +#define HP_APM_REGION13_R2_R_M (HP_APM_REGION13_R2_R_V << HP_APM_REGION13_R2_R_S) +#define HP_APM_REGION13_R2_R_V 0x00000001U +#define HP_APM_REGION13_R2_R_S 10 +/** HP_APM_REGION13_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_APM_REGION13_LOCK (BIT(11)) +#define HP_APM_REGION13_LOCK_M (HP_APM_REGION13_LOCK_V << HP_APM_REGION13_LOCK_S) +#define HP_APM_REGION13_LOCK_V 0x00000001U +#define HP_APM_REGION13_LOCK_S 11 + +/** HP_APM_REGION14_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION14_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xac) +/** HP_APM_REGION14_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 14. + */ +#define HP_APM_REGION14_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_START_M (HP_APM_REGION14_ADDR_START_V << HP_APM_REGION14_ADDR_START_S) +#define HP_APM_REGION14_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_START_S 0 + +/** HP_APM_REGION14_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION14_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xb0) +/** HP_APM_REGION14_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 14. + */ +#define HP_APM_REGION14_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_END_M (HP_APM_REGION14_ADDR_END_V << HP_APM_REGION14_ADDR_END_S) +#define HP_APM_REGION14_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION14_ADDR_END_S 0 + +/** HP_APM_REGION14_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION14_ATTR_REG (DR_REG_HP_APM_BASE + 0xb4) +/** HP_APM_REGION14_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 14. + */ +#define HP_APM_REGION14_R0_X (BIT(0)) +#define HP_APM_REGION14_R0_X_M (HP_APM_REGION14_R0_X_V << HP_APM_REGION14_R0_X_S) +#define HP_APM_REGION14_R0_X_V 0x00000001U +#define HP_APM_REGION14_R0_X_S 0 +/** HP_APM_REGION14_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 14. + */ +#define HP_APM_REGION14_R0_W (BIT(1)) +#define HP_APM_REGION14_R0_W_M (HP_APM_REGION14_R0_W_V << HP_APM_REGION14_R0_W_S) +#define HP_APM_REGION14_R0_W_V 0x00000001U +#define HP_APM_REGION14_R0_W_S 1 +/** HP_APM_REGION14_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 14. + */ +#define HP_APM_REGION14_R0_R (BIT(2)) +#define HP_APM_REGION14_R0_R_M (HP_APM_REGION14_R0_R_V << HP_APM_REGION14_R0_R_S) +#define HP_APM_REGION14_R0_R_V 0x00000001U +#define HP_APM_REGION14_R0_R_S 2 +/** HP_APM_REGION14_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 14. + */ +#define HP_APM_REGION14_R1_X (BIT(4)) +#define HP_APM_REGION14_R1_X_M (HP_APM_REGION14_R1_X_V << HP_APM_REGION14_R1_X_S) +#define HP_APM_REGION14_R1_X_V 0x00000001U +#define HP_APM_REGION14_R1_X_S 4 +/** HP_APM_REGION14_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 14. + */ +#define HP_APM_REGION14_R1_W (BIT(5)) +#define HP_APM_REGION14_R1_W_M (HP_APM_REGION14_R1_W_V << HP_APM_REGION14_R1_W_S) +#define HP_APM_REGION14_R1_W_V 0x00000001U +#define HP_APM_REGION14_R1_W_S 5 +/** HP_APM_REGION14_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 14. + */ +#define HP_APM_REGION14_R1_R (BIT(6)) +#define HP_APM_REGION14_R1_R_M (HP_APM_REGION14_R1_R_V << HP_APM_REGION14_R1_R_S) +#define HP_APM_REGION14_R1_R_V 0x00000001U +#define HP_APM_REGION14_R1_R_S 6 +/** HP_APM_REGION14_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 14. + */ +#define HP_APM_REGION14_R2_X (BIT(8)) +#define HP_APM_REGION14_R2_X_M (HP_APM_REGION14_R2_X_V << HP_APM_REGION14_R2_X_S) +#define HP_APM_REGION14_R2_X_V 0x00000001U +#define HP_APM_REGION14_R2_X_S 8 +/** HP_APM_REGION14_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 14. + */ +#define HP_APM_REGION14_R2_W (BIT(9)) +#define HP_APM_REGION14_R2_W_M (HP_APM_REGION14_R2_W_V << HP_APM_REGION14_R2_W_S) +#define HP_APM_REGION14_R2_W_V 0x00000001U +#define HP_APM_REGION14_R2_W_S 9 +/** HP_APM_REGION14_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 14. + */ +#define HP_APM_REGION14_R2_R (BIT(10)) +#define HP_APM_REGION14_R2_R_M (HP_APM_REGION14_R2_R_V << HP_APM_REGION14_R2_R_S) +#define HP_APM_REGION14_R2_R_V 0x00000001U +#define HP_APM_REGION14_R2_R_S 10 +/** HP_APM_REGION14_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_APM_REGION14_LOCK (BIT(11)) +#define HP_APM_REGION14_LOCK_M (HP_APM_REGION14_LOCK_V << HP_APM_REGION14_LOCK_S) +#define HP_APM_REGION14_LOCK_V 0x00000001U +#define HP_APM_REGION14_LOCK_S 11 + +/** HP_APM_REGION15_ADDR_START_REG register + * Region address register + */ +#define HP_APM_REGION15_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xb8) +/** HP_APM_REGION15_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 15. + */ +#define HP_APM_REGION15_ADDR_START 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_START_M (HP_APM_REGION15_ADDR_START_V << HP_APM_REGION15_ADDR_START_S) +#define HP_APM_REGION15_ADDR_START_V 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_START_S 0 + +/** HP_APM_REGION15_ADDR_END_REG register + * Region address register + */ +#define HP_APM_REGION15_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xbc) +/** HP_APM_REGION15_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 15. + */ +#define HP_APM_REGION15_ADDR_END 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_END_M (HP_APM_REGION15_ADDR_END_V << HP_APM_REGION15_ADDR_END_S) +#define HP_APM_REGION15_ADDR_END_V 0xFFFFFFFFU +#define HP_APM_REGION15_ADDR_END_S 0 + +/** HP_APM_REGION15_ATTR_REG register + * Region access authority attribute register + */ +#define HP_APM_REGION15_ATTR_REG (DR_REG_HP_APM_BASE + 0xc0) +/** HP_APM_REGION15_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 15. + */ +#define HP_APM_REGION15_R0_X (BIT(0)) +#define HP_APM_REGION15_R0_X_M (HP_APM_REGION15_R0_X_V << HP_APM_REGION15_R0_X_S) +#define HP_APM_REGION15_R0_X_V 0x00000001U +#define HP_APM_REGION15_R0_X_S 0 +/** HP_APM_REGION15_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 15. + */ +#define HP_APM_REGION15_R0_W (BIT(1)) +#define HP_APM_REGION15_R0_W_M (HP_APM_REGION15_R0_W_V << HP_APM_REGION15_R0_W_S) +#define HP_APM_REGION15_R0_W_V 0x00000001U +#define HP_APM_REGION15_R0_W_S 1 +/** HP_APM_REGION15_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 15. + */ +#define HP_APM_REGION15_R0_R (BIT(2)) +#define HP_APM_REGION15_R0_R_M (HP_APM_REGION15_R0_R_V << HP_APM_REGION15_R0_R_S) +#define HP_APM_REGION15_R0_R_V 0x00000001U +#define HP_APM_REGION15_R0_R_S 2 +/** HP_APM_REGION15_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 15. + */ +#define HP_APM_REGION15_R1_X (BIT(4)) +#define HP_APM_REGION15_R1_X_M (HP_APM_REGION15_R1_X_V << HP_APM_REGION15_R1_X_S) +#define HP_APM_REGION15_R1_X_V 0x00000001U +#define HP_APM_REGION15_R1_X_S 4 +/** HP_APM_REGION15_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 15. + */ +#define HP_APM_REGION15_R1_W (BIT(5)) +#define HP_APM_REGION15_R1_W_M (HP_APM_REGION15_R1_W_V << HP_APM_REGION15_R1_W_S) +#define HP_APM_REGION15_R1_W_V 0x00000001U +#define HP_APM_REGION15_R1_W_S 5 +/** HP_APM_REGION15_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 15. + */ +#define HP_APM_REGION15_R1_R (BIT(6)) +#define HP_APM_REGION15_R1_R_M (HP_APM_REGION15_R1_R_V << HP_APM_REGION15_R1_R_S) +#define HP_APM_REGION15_R1_R_V 0x00000001U +#define HP_APM_REGION15_R1_R_S 6 +/** HP_APM_REGION15_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 15. + */ +#define HP_APM_REGION15_R2_X (BIT(8)) +#define HP_APM_REGION15_R2_X_M (HP_APM_REGION15_R2_X_V << HP_APM_REGION15_R2_X_S) +#define HP_APM_REGION15_R2_X_V 0x00000001U +#define HP_APM_REGION15_R2_X_S 8 +/** HP_APM_REGION15_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 15. + */ +#define HP_APM_REGION15_R2_W (BIT(9)) +#define HP_APM_REGION15_R2_W_M (HP_APM_REGION15_R2_W_V << HP_APM_REGION15_R2_W_S) +#define HP_APM_REGION15_R2_W_V 0x00000001U +#define HP_APM_REGION15_R2_W_S 9 +/** HP_APM_REGION15_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 15. + */ +#define HP_APM_REGION15_R2_R (BIT(10)) +#define HP_APM_REGION15_R2_R_M (HP_APM_REGION15_R2_R_V << HP_APM_REGION15_R2_R_S) +#define HP_APM_REGION15_R2_R_V 0x00000001U +#define HP_APM_REGION15_R2_R_S 10 +/** HP_APM_REGION15_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define HP_APM_REGION15_LOCK (BIT(11)) +#define HP_APM_REGION15_LOCK_M (HP_APM_REGION15_LOCK_V << HP_APM_REGION15_LOCK_S) +#define HP_APM_REGION15_LOCK_V 0x00000001U +#define HP_APM_REGION15_LOCK_S 11 + +/** HP_APM_FUNC_CTRL_REG register + * APM function control register + */ +#define HP_APM_FUNC_CTRL_REG (DR_REG_HP_APM_BASE + 0xc4) +/** HP_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define HP_APM_M0_FUNC_EN (BIT(0)) +#define HP_APM_M0_FUNC_EN_M (HP_APM_M0_FUNC_EN_V << HP_APM_M0_FUNC_EN_S) +#define HP_APM_M0_FUNC_EN_V 0x00000001U +#define HP_APM_M0_FUNC_EN_S 0 +/** HP_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ +#define HP_APM_M1_FUNC_EN (BIT(1)) +#define HP_APM_M1_FUNC_EN_M (HP_APM_M1_FUNC_EN_V << HP_APM_M1_FUNC_EN_S) +#define HP_APM_M1_FUNC_EN_V 0x00000001U +#define HP_APM_M1_FUNC_EN_S 1 +/** HP_APM_M2_FUNC_EN : R/W; bitpos: [2]; default: 1; + * PMS M2 function enable + */ +#define HP_APM_M2_FUNC_EN (BIT(2)) +#define HP_APM_M2_FUNC_EN_M (HP_APM_M2_FUNC_EN_V << HP_APM_M2_FUNC_EN_S) +#define HP_APM_M2_FUNC_EN_V 0x00000001U +#define HP_APM_M2_FUNC_EN_S 2 +/** HP_APM_M3_FUNC_EN : R/W; bitpos: [3]; default: 1; + * PMS M3 function enable + */ +#define HP_APM_M3_FUNC_EN (BIT(3)) +#define HP_APM_M3_FUNC_EN_M (HP_APM_M3_FUNC_EN_V << HP_APM_M3_FUNC_EN_S) +#define HP_APM_M3_FUNC_EN_V 0x00000001U +#define HP_APM_M3_FUNC_EN_S 3 + +/** HP_APM_M0_STATUS_REG register + * M0 status register + */ +#define HP_APM_M0_STATUS_REG (DR_REG_HP_APM_BASE + 0xc8) +/** HP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Represents exception status.\\ + * bit0: 1 represents authority_exception \\ + * bit1: 1 represents space_exception \\ + */ +#define HP_APM_M0_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M0_EXCEPTION_STATUS_M (HP_APM_M0_EXCEPTION_STATUS_V << HP_APM_M0_EXCEPTION_STATUS_S) +#define HP_APM_M0_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M0_EXCEPTION_STATUS_S 0 + +/** HP_APM_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define HP_APM_M0_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xcc) +/** HP_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ +#define HP_APM_M0_EXCEPTION_STATUS_CLR (BIT(0)) +#define HP_APM_M0_EXCEPTION_STATUS_CLR_M (HP_APM_M0_EXCEPTION_STATUS_CLR_V << HP_APM_M0_EXCEPTION_STATUS_CLR_S) +#define HP_APM_M0_EXCEPTION_STATUS_CLR_V 0x00000001U +#define HP_APM_M0_EXCEPTION_STATUS_CLR_S 0 + +/** HP_APM_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define HP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xd0) +/** HP_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ +#define HP_APM_M0_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M0_EXCEPTION_REGION_M (HP_APM_M0_EXCEPTION_REGION_V << HP_APM_M0_EXCEPTION_REGION_S) +#define HP_APM_M0_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M0_EXCEPTION_REGION_S 0 +/** HP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ +#define HP_APM_M0_EXCEPTION_MODE 0x00000003U +#define HP_APM_M0_EXCEPTION_MODE_M (HP_APM_M0_EXCEPTION_MODE_V << HP_APM_M0_EXCEPTION_MODE_S) +#define HP_APM_M0_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M0_EXCEPTION_MODE_S 16 +/** HP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ +#define HP_APM_M0_EXCEPTION_ID 0x0000001FU +#define HP_APM_M0_EXCEPTION_ID_M (HP_APM_M0_EXCEPTION_ID_V << HP_APM_M0_EXCEPTION_ID_S) +#define HP_APM_M0_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M0_EXCEPTION_ID_S 18 + +/** HP_APM_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define HP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xd4) +/** HP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ +#define HP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M0_EXCEPTION_ADDR_M (HP_APM_M0_EXCEPTION_ADDR_V << HP_APM_M0_EXCEPTION_ADDR_S) +#define HP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M0_EXCEPTION_ADDR_S 0 + +/** HP_APM_M1_STATUS_REG register + * M1 status register + */ +#define HP_APM_M1_STATUS_REG (DR_REG_HP_APM_BASE + 0xd8) +/** HP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Represents exception status.\\ + * bit0: 1 represents authority_exception \\ + * bit1: 1 represents space_exception \\ + */ +#define HP_APM_M1_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M1_EXCEPTION_STATUS_M (HP_APM_M1_EXCEPTION_STATUS_V << HP_APM_M1_EXCEPTION_STATUS_S) +#define HP_APM_M1_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M1_EXCEPTION_STATUS_S 0 + +/** HP_APM_M1_STATUS_CLR_REG register + * M1 status clear register + */ +#define HP_APM_M1_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xdc) +/** HP_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ +#define HP_APM_M1_EXCEPTION_STATUS_CLR (BIT(0)) +#define HP_APM_M1_EXCEPTION_STATUS_CLR_M (HP_APM_M1_EXCEPTION_STATUS_CLR_V << HP_APM_M1_EXCEPTION_STATUS_CLR_S) +#define HP_APM_M1_EXCEPTION_STATUS_CLR_V 0x00000001U +#define HP_APM_M1_EXCEPTION_STATUS_CLR_S 0 + +/** HP_APM_M1_EXCEPTION_INFO0_REG register + * M1 exception_info0 register + */ +#define HP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xe0) +/** HP_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ +#define HP_APM_M1_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M1_EXCEPTION_REGION_M (HP_APM_M1_EXCEPTION_REGION_V << HP_APM_M1_EXCEPTION_REGION_S) +#define HP_APM_M1_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M1_EXCEPTION_REGION_S 0 +/** HP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ +#define HP_APM_M1_EXCEPTION_MODE 0x00000003U +#define HP_APM_M1_EXCEPTION_MODE_M (HP_APM_M1_EXCEPTION_MODE_V << HP_APM_M1_EXCEPTION_MODE_S) +#define HP_APM_M1_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M1_EXCEPTION_MODE_S 16 +/** HP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ +#define HP_APM_M1_EXCEPTION_ID 0x0000001FU +#define HP_APM_M1_EXCEPTION_ID_M (HP_APM_M1_EXCEPTION_ID_V << HP_APM_M1_EXCEPTION_ID_S) +#define HP_APM_M1_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M1_EXCEPTION_ID_S 18 + +/** HP_APM_M1_EXCEPTION_INFO1_REG register + * M1 exception_info1 register + */ +#define HP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xe4) +/** HP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ +#define HP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M1_EXCEPTION_ADDR_M (HP_APM_M1_EXCEPTION_ADDR_V << HP_APM_M1_EXCEPTION_ADDR_S) +#define HP_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M1_EXCEPTION_ADDR_S 0 + +/** HP_APM_M2_STATUS_REG register + * M2 status register + */ +#define HP_APM_M2_STATUS_REG (DR_REG_HP_APM_BASE + 0xe8) +/** HP_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Represents exception status.\\ + * bit0: 1 represents authority_exception \\ + * bit1: 1 represents space_exception \\ + */ +#define HP_APM_M2_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M2_EXCEPTION_STATUS_M (HP_APM_M2_EXCEPTION_STATUS_V << HP_APM_M2_EXCEPTION_STATUS_S) +#define HP_APM_M2_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M2_EXCEPTION_STATUS_S 0 + +/** HP_APM_M2_STATUS_CLR_REG register + * M2 status clear register + */ +#define HP_APM_M2_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xec) +/** HP_APM_M2_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ +#define HP_APM_M2_EXCEPTION_STATUS_CLR (BIT(0)) +#define HP_APM_M2_EXCEPTION_STATUS_CLR_M (HP_APM_M2_EXCEPTION_STATUS_CLR_V << HP_APM_M2_EXCEPTION_STATUS_CLR_S) +#define HP_APM_M2_EXCEPTION_STATUS_CLR_V 0x00000001U +#define HP_APM_M2_EXCEPTION_STATUS_CLR_S 0 + +/** HP_APM_M2_EXCEPTION_INFO0_REG register + * M2 exception_info0 register + */ +#define HP_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xf0) +/** HP_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ +#define HP_APM_M2_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M2_EXCEPTION_REGION_M (HP_APM_M2_EXCEPTION_REGION_V << HP_APM_M2_EXCEPTION_REGION_S) +#define HP_APM_M2_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M2_EXCEPTION_REGION_S 0 +/** HP_APM_M2_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ +#define HP_APM_M2_EXCEPTION_MODE 0x00000003U +#define HP_APM_M2_EXCEPTION_MODE_M (HP_APM_M2_EXCEPTION_MODE_V << HP_APM_M2_EXCEPTION_MODE_S) +#define HP_APM_M2_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M2_EXCEPTION_MODE_S 16 +/** HP_APM_M2_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ +#define HP_APM_M2_EXCEPTION_ID 0x0000001FU +#define HP_APM_M2_EXCEPTION_ID_M (HP_APM_M2_EXCEPTION_ID_V << HP_APM_M2_EXCEPTION_ID_S) +#define HP_APM_M2_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M2_EXCEPTION_ID_S 18 + +/** HP_APM_M2_EXCEPTION_INFO1_REG register + * M2 exception_info1 register + */ +#define HP_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xf4) +/** HP_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ +#define HP_APM_M2_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M2_EXCEPTION_ADDR_M (HP_APM_M2_EXCEPTION_ADDR_V << HP_APM_M2_EXCEPTION_ADDR_S) +#define HP_APM_M2_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M2_EXCEPTION_ADDR_S 0 + +/** HP_APM_M3_STATUS_REG register + * M3 status register + */ +#define HP_APM_M3_STATUS_REG (DR_REG_HP_APM_BASE + 0xf8) +/** HP_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Represents exception status.\\ + * bit0: 1 represents authority_exception \\ + * bit1: 1 represents space_exception \\ + */ +#define HP_APM_M3_EXCEPTION_STATUS 0x00000003U +#define HP_APM_M3_EXCEPTION_STATUS_M (HP_APM_M3_EXCEPTION_STATUS_V << HP_APM_M3_EXCEPTION_STATUS_S) +#define HP_APM_M3_EXCEPTION_STATUS_V 0x00000003U +#define HP_APM_M3_EXCEPTION_STATUS_S 0 + +/** HP_APM_M3_STATUS_CLR_REG register + * M3 status clear register + */ +#define HP_APM_M3_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xfc) +/** HP_APM_M3_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ +#define HP_APM_M3_EXCEPTION_STATUS_CLR (BIT(0)) +#define HP_APM_M3_EXCEPTION_STATUS_CLR_M (HP_APM_M3_EXCEPTION_STATUS_CLR_V << HP_APM_M3_EXCEPTION_STATUS_CLR_S) +#define HP_APM_M3_EXCEPTION_STATUS_CLR_V 0x00000001U +#define HP_APM_M3_EXCEPTION_STATUS_CLR_S 0 + +/** HP_APM_M3_EXCEPTION_INFO0_REG register + * M3 exception_info0 register + */ +#define HP_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x100) +/** HP_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ +#define HP_APM_M3_EXCEPTION_REGION 0x0000FFFFU +#define HP_APM_M3_EXCEPTION_REGION_M (HP_APM_M3_EXCEPTION_REGION_V << HP_APM_M3_EXCEPTION_REGION_S) +#define HP_APM_M3_EXCEPTION_REGION_V 0x0000FFFFU +#define HP_APM_M3_EXCEPTION_REGION_S 0 +/** HP_APM_M3_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ +#define HP_APM_M3_EXCEPTION_MODE 0x00000003U +#define HP_APM_M3_EXCEPTION_MODE_M (HP_APM_M3_EXCEPTION_MODE_V << HP_APM_M3_EXCEPTION_MODE_S) +#define HP_APM_M3_EXCEPTION_MODE_V 0x00000003U +#define HP_APM_M3_EXCEPTION_MODE_S 16 +/** HP_APM_M3_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ +#define HP_APM_M3_EXCEPTION_ID 0x0000001FU +#define HP_APM_M3_EXCEPTION_ID_M (HP_APM_M3_EXCEPTION_ID_V << HP_APM_M3_EXCEPTION_ID_S) +#define HP_APM_M3_EXCEPTION_ID_V 0x0000001FU +#define HP_APM_M3_EXCEPTION_ID_S 18 + +/** HP_APM_M3_EXCEPTION_INFO1_REG register + * M3 exception_info1 register + */ +#define HP_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x104) +/** HP_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ +#define HP_APM_M3_EXCEPTION_ADDR 0xFFFFFFFFU +#define HP_APM_M3_EXCEPTION_ADDR_M (HP_APM_M3_EXCEPTION_ADDR_V << HP_APM_M3_EXCEPTION_ADDR_S) +#define HP_APM_M3_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define HP_APM_M3_EXCEPTION_ADDR_S 0 + +/** HP_APM_INT_EN_REG register + * APM interrupt enable register + */ +#define HP_APM_INT_EN_REG (DR_REG_HP_APM_BASE + 0x108) +/** HP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * Configures to enable APM M0 interrupt.\\ + * 0: disable \\ + * 1: enable \\ + */ +#define HP_APM_M0_APM_INT_EN (BIT(0)) +#define HP_APM_M0_APM_INT_EN_M (HP_APM_M0_APM_INT_EN_V << HP_APM_M0_APM_INT_EN_S) +#define HP_APM_M0_APM_INT_EN_V 0x00000001U +#define HP_APM_M0_APM_INT_EN_S 0 +/** HP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; + * Configures to enable APM M1 interrupt.\\ + * 0: disable \\ + * 1: enable \\ + */ +#define HP_APM_M1_APM_INT_EN (BIT(1)) +#define HP_APM_M1_APM_INT_EN_M (HP_APM_M1_APM_INT_EN_V << HP_APM_M1_APM_INT_EN_S) +#define HP_APM_M1_APM_INT_EN_V 0x00000001U +#define HP_APM_M1_APM_INT_EN_S 1 +/** HP_APM_M2_APM_INT_EN : R/W; bitpos: [2]; default: 0; + * Configures to enable APM M2 interrupt.\\ + * 0: disable \\ + * 1: enable \\ + */ +#define HP_APM_M2_APM_INT_EN (BIT(2)) +#define HP_APM_M2_APM_INT_EN_M (HP_APM_M2_APM_INT_EN_V << HP_APM_M2_APM_INT_EN_S) +#define HP_APM_M2_APM_INT_EN_V 0x00000001U +#define HP_APM_M2_APM_INT_EN_S 2 +/** HP_APM_M3_APM_INT_EN : R/W; bitpos: [3]; default: 0; + * Configures to enable APM M3 interrupt.\\ + * 0: disable \\ + * 1: enable \\ + */ +#define HP_APM_M3_APM_INT_EN (BIT(3)) +#define HP_APM_M3_APM_INT_EN_M (HP_APM_M3_APM_INT_EN_V << HP_APM_M3_APM_INT_EN_S) +#define HP_APM_M3_APM_INT_EN_V 0x00000001U +#define HP_APM_M3_APM_INT_EN_S 3 + +/** HP_APM_CLOCK_GATE_REG register + * Clock gating register + */ +#define HP_APM_CLOCK_GATE_REG (DR_REG_HP_APM_BASE + 0x7f8) +/** HP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on.\\ + * 0: enable automatic clock gating \\ + * 1: keep the clock always on \\ + */ +#define HP_APM_CLK_EN (BIT(0)) +#define HP_APM_CLK_EN_M (HP_APM_CLK_EN_V << HP_APM_CLK_EN_S) +#define HP_APM_CLK_EN_V 0x00000001U +#define HP_APM_CLK_EN_S 0 + +/** HP_APM_DATE_REG register + * Version control register + */ +#define HP_APM_DATE_REG (DR_REG_HP_APM_BASE + 0x7fc) +/** HP_APM_DATE : R/W; bitpos: [27:0]; default: 36774400; + * Version control register. + */ +#define HP_APM_DATE 0x0FFFFFFFU +#define HP_APM_DATE_M (HP_APM_DATE_V << HP_APM_DATE_S) +#define HP_APM_DATE_V 0x0FFFFFFFU +#define HP_APM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/hp_apm_struct.h b/components/soc/esp32c61/include/soc/hp_apm_struct.h new file mode 100644 index 0000000000..1b0770810b --- /dev/null +++ b/components/soc/esp32c61/include/soc/hp_apm_struct.h @@ -0,0 +1,584 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** region_filter_en : R/W; bitpos: [15:0]; default: 1; + * Configure bit $n (0-15) to enable region $n.\\ + * 0: disable \\ + * 1: enable \\ + */ + uint32_t region_filter_en:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} hp_apm_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of regionn_addr_start register + * Region address register + */ +typedef union { + struct { + /** regionn_addr_start : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region n. + */ + uint32_t regionn_addr_start:32; + }; + uint32_t val; +} hp_apm_regionn_addr_start_reg_t; + +/** Type of regionn_addr_end register + * Region address register + */ +typedef union { + struct { + /** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region n. + */ + uint32_t regionn_addr_end:32; + }; + uint32_t val; +} hp_apm_regionn_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of regionn_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** regionn_r0_x : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region n. + */ + uint32_t regionn_r0_x:1; + /** regionn_r0_w : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region n. + */ + uint32_t regionn_r0_w:1; + /** regionn_r0_r : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region n. + */ + uint32_t regionn_r0_r:1; + uint32_t reserved_3:1; + /** regionn_r1_x : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region n. + */ + uint32_t regionn_r1_x:1; + /** regionn_r1_w : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region n. + */ + uint32_t regionn_r1_w:1; + /** regionn_r1_r : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region n. + */ + uint32_t regionn_r1_r:1; + uint32_t reserved_7:1; + /** regionn_r2_x : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region n. + */ + uint32_t regionn_r2_x:1; + /** regionn_r2_w : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region n. + */ + uint32_t regionn_r2_w:1; + /** regionn_r2_r : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region n. + */ + uint32_t regionn_r2_r:1; + /** regionn_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ + uint32_t regionn_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} hp_apm_regionn_attr_reg_t; + + +/** Group: function control register */ +/** Type of func_ctrl register + * APM function control register + */ +typedef union { + struct { + /** m0_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t m0_func_en:1; + /** m1_func_en : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ + uint32_t m1_func_en:1; + /** m2_func_en : R/W; bitpos: [2]; default: 1; + * PMS M2 function enable + */ + uint32_t m2_func_en:1; + /** m3_func_en : R/W; bitpos: [3]; default: 1; + * PMS M3 function enable + */ + uint32_t m3_func_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} hp_apm_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of m0_status register + * M0 status register + */ +typedef union { + struct { + /** m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Represents exception status.\\ + * bit0: 1 represents authority_exception \\ + * bit1: 1 represents space_exception \\ + */ + uint32_t m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** m0_exception_status_clr : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ + uint32_t m0_exception_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** m0_exception_region : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ + uint32_t m0_exception_region:16; + /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ + uint32_t m0_exception_mode:2; + /** m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ + uint32_t m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ + uint32_t m0_exception_addr:32; + }; + uint32_t val; +} hp_apm_m0_exception_info1_reg_t; + + +/** Group: M1 status register */ +/** Type of m1_status register + * M1 status register + */ +typedef union { + struct { + /** m1_exception_status : RO; bitpos: [1:0]; default: 0; + * Represents exception status.\\ + * bit0: 1 represents authority_exception \\ + * bit1: 1 represents space_exception \\ + */ + uint32_t m1_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m1_status_reg_t; + + +/** Group: M1 status clear register */ +/** Type of m1_status_clr register + * M1 status clear register + */ +typedef union { + struct { + /** m1_exception_status_clr : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ + uint32_t m1_exception_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m1_status_clr_reg_t; + + +/** Group: M1 exception_info0 register */ +/** Type of m1_exception_info0 register + * M1 exception_info0 register + */ +typedef union { + struct { + /** m1_exception_region : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ + uint32_t m1_exception_region:16; + /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ + uint32_t m1_exception_mode:2; + /** m1_exception_id : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ + uint32_t m1_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m1_exception_info0_reg_t; + + +/** Group: M1 exception_info1 register */ +/** Type of m1_exception_info1 register + * M1 exception_info1 register + */ +typedef union { + struct { + /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ + uint32_t m1_exception_addr:32; + }; + uint32_t val; +} hp_apm_m1_exception_info1_reg_t; + + +/** Group: M2 status register */ +/** Type of m2_status register + * M2 status register + */ +typedef union { + struct { + /** m2_exception_status : RO; bitpos: [1:0]; default: 0; + * Represents exception status.\\ + * bit0: 1 represents authority_exception \\ + * bit1: 1 represents space_exception \\ + */ + uint32_t m2_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m2_status_reg_t; + + +/** Group: M2 status clear register */ +/** Type of m2_status_clr register + * M2 status clear register + */ +typedef union { + struct { + /** m2_exception_status_clr : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ + uint32_t m2_exception_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m2_status_clr_reg_t; + + +/** Group: M2 exception_info0 register */ +/** Type of m2_exception_info0 register + * M2 exception_info0 register + */ +typedef union { + struct { + /** m2_exception_region : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ + uint32_t m2_exception_region:16; + /** m2_exception_mode : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ + uint32_t m2_exception_mode:2; + /** m2_exception_id : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ + uint32_t m2_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m2_exception_info0_reg_t; + + +/** Group: M2 exception_info1 register */ +/** Type of m2_exception_info1 register + * M2 exception_info1 register + */ +typedef union { + struct { + /** m2_exception_addr : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ + uint32_t m2_exception_addr:32; + }; + uint32_t val; +} hp_apm_m2_exception_info1_reg_t; + + +/** Group: M3 status register */ +/** Type of m3_status register + * M3 status register + */ +typedef union { + struct { + /** m3_exception_status : RO; bitpos: [1:0]; default: 0; + * Represents exception status.\\ + * bit0: 1 represents authority_exception \\ + * bit1: 1 represents space_exception \\ + */ + uint32_t m3_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_apm_m3_status_reg_t; + + +/** Group: M3 status clear register */ +/** Type of m3_status_clr register + * M3 status clear register + */ +typedef union { + struct { + /** m3_exception_status_clr : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ + uint32_t m3_exception_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_m3_status_clr_reg_t; + + +/** Group: M3 exception_info0 register */ +/** Type of m3_exception_info0 register + * M3 exception_info0 register + */ +typedef union { + struct { + /** m3_exception_region : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ + uint32_t m3_exception_region:16; + /** m3_exception_mode : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ + uint32_t m3_exception_mode:2; + /** m3_exception_id : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ + uint32_t m3_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} hp_apm_m3_exception_info0_reg_t; + + +/** Group: M3 exception_info1 register */ +/** Type of m3_exception_info1 register + * M3 exception_info1 register + */ +typedef union { + struct { + /** m3_exception_addr : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ + uint32_t m3_exception_addr:32; + }; + uint32_t val; +} hp_apm_m3_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * Configures to enable APM M0 interrupt.\\ + * 0: disable \\ + * 1: enable \\ + */ + uint32_t m0_apm_int_en:1; + /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; + * Configures to enable APM M1 interrupt.\\ + * 0: disable \\ + * 1: enable \\ + */ + uint32_t m1_apm_int_en:1; + /** m2_apm_int_en : R/W; bitpos: [2]; default: 0; + * Configures to enable APM M2 interrupt.\\ + * 0: disable \\ + * 1: enable \\ + */ + uint32_t m2_apm_int_en:1; + /** m3_apm_int_en : R/W; bitpos: [3]; default: 0; + * Configures to enable APM M3 interrupt.\\ + * 0: disable \\ + * 1: enable \\ + */ + uint32_t m3_apm_int_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} hp_apm_int_en_reg_t; + + +/** Group: Clock gating register */ +/** Type of clock_gate register + * Clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on.\\ + * 0: enable automatic clock gating \\ + * 1: keep the clock always on \\ + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hp_apm_clock_gate_reg_t; + + +/** Group: Version control register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36774400; + * Version control register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} hp_apm_date_reg_t; + + +typedef struct { + volatile hp_apm_region_filter_en_reg_t region_filter_en; + volatile hp_apm_regionn_addr_start_reg_t region0_addr_start; + volatile hp_apm_regionn_addr_end_reg_t region0_addr_end; + volatile hp_apm_regionn_attr_reg_t region0_attr; + volatile hp_apm_regionn_addr_start_reg_t region1_addr_start; + volatile hp_apm_regionn_addr_end_reg_t region1_addr_end; + volatile hp_apm_regionn_attr_reg_t region1_attr; + volatile hp_apm_regionn_addr_start_reg_t region2_addr_start; + volatile hp_apm_regionn_addr_end_reg_t region2_addr_end; + volatile hp_apm_regionn_attr_reg_t region2_attr; + volatile hp_apm_regionn_addr_start_reg_t region3_addr_start; + volatile hp_apm_regionn_addr_end_reg_t region3_addr_end; + volatile hp_apm_regionn_attr_reg_t region3_attr; + volatile hp_apm_regionn_addr_start_reg_t region4_addr_start; + volatile hp_apm_regionn_addr_end_reg_t region4_addr_end; + volatile hp_apm_regionn_attr_reg_t region4_attr; + volatile hp_apm_regionn_addr_start_reg_t region5_addr_start; + volatile hp_apm_regionn_addr_end_reg_t region5_addr_end; + volatile hp_apm_regionn_attr_reg_t region5_attr; + volatile hp_apm_regionn_addr_start_reg_t region6_addr_start; + volatile hp_apm_regionn_addr_end_reg_t region6_addr_end; + volatile hp_apm_regionn_attr_reg_t region6_attr; + volatile hp_apm_regionn_addr_start_reg_t region7_addr_start; + volatile hp_apm_regionn_addr_end_reg_t region7_addr_end; + volatile hp_apm_regionn_attr_reg_t region7_attr; + volatile hp_apm_regionn_addr_start_reg_t region8_addr_start; + volatile hp_apm_regionn_addr_end_reg_t region8_addr_end; + volatile hp_apm_regionn_attr_reg_t region8_attr; + volatile hp_apm_regionn_addr_start_reg_t region9_addr_start; + volatile hp_apm_regionn_addr_end_reg_t region9_addr_end; + volatile hp_apm_regionn_attr_reg_t region9_attr; + volatile hp_apm_regionn_addr_start_reg_t region10_addr_start; + volatile hp_apm_regionn_addr_end_reg_t region10_addr_end; + volatile hp_apm_regionn_attr_reg_t region10_attr; + volatile hp_apm_regionn_addr_start_reg_t region11_addr_start; + volatile hp_apm_regionn_addr_end_reg_t region11_addr_end; + volatile hp_apm_regionn_attr_reg_t region11_attr; + volatile hp_apm_regionn_addr_start_reg_t region12_addr_start; + volatile hp_apm_regionn_addr_end_reg_t region12_addr_end; + volatile hp_apm_regionn_attr_reg_t region12_attr; + volatile hp_apm_regionn_addr_start_reg_t region13_addr_start; + volatile hp_apm_regionn_addr_end_reg_t region13_addr_end; + volatile hp_apm_regionn_attr_reg_t region13_attr; + volatile hp_apm_regionn_addr_start_reg_t region14_addr_start; + volatile hp_apm_regionn_addr_end_reg_t region14_addr_end; + volatile hp_apm_regionn_attr_reg_t region14_attr; + volatile hp_apm_regionn_addr_start_reg_t region15_addr_start; + volatile hp_apm_regionn_addr_end_reg_t region15_addr_end; + volatile hp_apm_regionn_attr_reg_t region15_attr; + volatile hp_apm_func_ctrl_reg_t func_ctrl; + volatile hp_apm_m0_status_reg_t m0_status; + volatile hp_apm_m0_status_clr_reg_t m0_status_clr; + volatile hp_apm_m0_exception_info0_reg_t m0_exception_info0; + volatile hp_apm_m0_exception_info1_reg_t m0_exception_info1; + volatile hp_apm_m1_status_reg_t m1_status; + volatile hp_apm_m1_status_clr_reg_t m1_status_clr; + volatile hp_apm_m1_exception_info0_reg_t m1_exception_info0; + volatile hp_apm_m1_exception_info1_reg_t m1_exception_info1; + volatile hp_apm_m2_status_reg_t m2_status; + volatile hp_apm_m2_status_clr_reg_t m2_status_clr; + volatile hp_apm_m2_exception_info0_reg_t m2_exception_info0; + volatile hp_apm_m2_exception_info1_reg_t m2_exception_info1; + volatile hp_apm_m3_status_reg_t m3_status; + volatile hp_apm_m3_status_clr_reg_t m3_status_clr; + volatile hp_apm_m3_exception_info0_reg_t m3_exception_info0; + volatile hp_apm_m3_exception_info1_reg_t m3_exception_info1; + volatile hp_apm_int_en_reg_t int_en; + uint32_t reserved_10c[443]; + volatile hp_apm_clock_gate_reg_t clock_gate; + volatile hp_apm_date_reg_t date; +} hp_apm_dev_t; + +extern hp_apm_dev_t HP_APM; + +#ifndef __cplusplus +_Static_assert(sizeof(hp_apm_dev_t) == 0x800, "Invalid size of hp_apm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/intpri_struct.h b/components/soc/esp32c61/include/soc/intpri_struct.h index 338fb09a38..995c5d3577 100644 --- a/components/soc/esp32c61/include/soc/intpri_struct.h +++ b/components/soc/esp32c61/include/soc/intpri_struct.h @@ -116,7 +116,7 @@ typedef struct { volatile intpri_rnd_eco_high_reg_t rnd_eco_high; } intpri_dev_t; -extern intpri_dev_t INTPRI_REG; +extern intpri_dev_t INTPRI; #ifndef __cplusplus _Static_assert(sizeof(intpri_dev_t) == 0x400, "Invalid size of intpri_dev_t structure"); diff --git a/components/soc/esp32c61/include/soc/lp_ana_reg.h b/components/soc/esp32c61/include/soc/lp_ana_reg.h new file mode 100644 index 0000000000..cea0165480 --- /dev/null +++ b/components/soc/esp32c61/include/soc/lp_ana_reg.h @@ -0,0 +1,228 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_ANA_BOD_MODE0_CNTL_REG register + * need_des + */ +#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANA_BASE + 0x0) +/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6)) +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S) +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S 6 +/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_PD_RF_ENA (BIT(7)) +#define LP_ANA_BOD_MODE0_PD_RF_ENA_M (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S) +#define LP_ANA_BOD_MODE0_PD_RF_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_PD_RF_ENA_S 7 +/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1; + * need_des + */ +#define LP_ANA_BOD_MODE0_INTR_WAIT 0x000003FFU +#define LP_ANA_BOD_MODE0_INTR_WAIT_M (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S) +#define LP_ANA_BOD_MODE0_INTR_WAIT_V 0x000003FFU +#define LP_ANA_BOD_MODE0_INTR_WAIT_S 8 +/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023; + * need_des + */ +#define LP_ANA_BOD_MODE0_RESET_WAIT 0x000003FFU +#define LP_ANA_BOD_MODE0_RESET_WAIT_M (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S) +#define LP_ANA_BOD_MODE0_RESET_WAIT_V 0x000003FFU +#define LP_ANA_BOD_MODE0_RESET_WAIT_S 18 +/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_CNT_CLR (BIT(28)) +#define LP_ANA_BOD_MODE0_CNT_CLR_M (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S) +#define LP_ANA_BOD_MODE0_CNT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_CNT_CLR_S 28 +/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INTR_ENA (BIT(29)) +#define LP_ANA_BOD_MODE0_INTR_ENA_M (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S) +#define LP_ANA_BOD_MODE0_INTR_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_INTR_ENA_S 29 +/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_RESET_SEL (BIT(30)) +#define LP_ANA_BOD_MODE0_RESET_SEL_M (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S) +#define LP_ANA_BOD_MODE0_RESET_SEL_V 0x00000001U +#define LP_ANA_BOD_MODE0_RESET_SEL_S 30 +/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_RESET_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_RESET_ENA_M (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S) +#define LP_ANA_BOD_MODE0_RESET_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_RESET_ENA_S 31 + +/** LP_ANA_BOD_MODE1_CNTL_REG register + * need_des + */ +#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_ANA_BASE + 0x4) +/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE1_RESET_ENA (BIT(31)) +#define LP_ANA_BOD_MODE1_RESET_ENA_M (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S) +#define LP_ANA_BOD_MODE1_RESET_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE1_RESET_ENA_S 31 + +/** LP_ANA_POWER_GLITCH_CNTL_REG register + * need_des + */ +#define LP_ANA_POWER_GLITCH_CNTL_REG (DR_REG_LP_ANA_BASE + 0x8) +/** LP_ANA_POWER_GLITCH_RESET_ENA : R/W; bitpos: [31:28]; default: 0; + * need_des + */ +#define LP_ANA_POWER_GLITCH_RESET_ENA 0x0000000FU +#define LP_ANA_POWER_GLITCH_RESET_ENA_M (LP_ANA_POWER_GLITCH_RESET_ENA_V << LP_ANA_POWER_GLITCH_RESET_ENA_S) +#define LP_ANA_POWER_GLITCH_RESET_ENA_V 0x0000000FU +#define LP_ANA_POWER_GLITCH_RESET_ENA_S 28 + +/** LP_ANA_FIB_ENABLE_REG register + * need_des + */ +#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_ANA_BASE + 0xc) +/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define LP_ANA_ANA_FIB_ENA 0xFFFFFFFFU +#define LP_ANA_ANA_FIB_ENA_M (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S) +#define LP_ANA_ANA_FIB_ENA_V 0xFFFFFFFFU +#define LP_ANA_ANA_FIB_ENA_S 0 + +/** LP_ANA_INT_RAW_REG register + * need_des + */ +#define LP_ANA_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x10) +/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_RAW (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_RAW_M (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S) +#define LP_ANA_BOD_MODE0_INT_RAW_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_RAW_S 31 + +/** LP_ANA_INT_ST_REG register + * need_des + */ +#define LP_ANA_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x14) +/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_ST (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_ST_M (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S) +#define LP_ANA_BOD_MODE0_INT_ST_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_ST_S 31 + +/** LP_ANA_INT_ENA_REG register + * need_des + */ +#define LP_ANA_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x18) +/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_ENA_M (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S) +#define LP_ANA_BOD_MODE0_INT_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_ENA_S 31 + +/** LP_ANA_INT_CLR_REG register + * need_des + */ +#define LP_ANA_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x1c) +/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_INT_CLR (BIT(31)) +#define LP_ANA_BOD_MODE0_INT_CLR_M (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S) +#define LP_ANA_BOD_MODE0_INT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_INT_CLR_S 31 + +/** LP_ANA_LP_INT_RAW_REG register + * need_des + */ +#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x20) +/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_RAW (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_RAW_M (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S) +#define LP_ANA_BOD_MODE0_LP_INT_RAW_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_RAW_S 31 + +/** LP_ANA_LP_INT_ST_REG register + * need_des + */ +#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x24) +/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_ST (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_ST_M (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S) +#define LP_ANA_BOD_MODE0_LP_INT_ST_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_ST_S 31 + +/** LP_ANA_LP_INT_ENA_REG register + * need_des + */ +#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x28) +/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_ENA (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_ENA_M (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S) +#define LP_ANA_BOD_MODE0_LP_INT_ENA_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_ENA_S 31 + +/** LP_ANA_LP_INT_CLR_REG register + * need_des + */ +#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x2c) +/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_BOD_MODE0_LP_INT_CLR (BIT(31)) +#define LP_ANA_BOD_MODE0_LP_INT_CLR_M (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S) +#define LP_ANA_BOD_MODE0_LP_INT_CLR_V 0x00000001U +#define LP_ANA_BOD_MODE0_LP_INT_CLR_S 31 + +/** LP_ANA_DATE_REG register + * need_des + */ +#define LP_ANA_DATE_REG (DR_REG_LP_ANA_BASE + 0x3fc) +/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 37752896; + * need_des + */ +#define LP_ANA_LP_ANA_DATE 0x7FFFFFFFU +#define LP_ANA_LP_ANA_DATE_M (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S) +#define LP_ANA_LP_ANA_DATE_V 0x7FFFFFFFU +#define LP_ANA_LP_ANA_DATE_S 0 +/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_ANA_CLK_EN (BIT(31)) +#define LP_ANA_CLK_EN_M (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S) +#define LP_ANA_CLK_EN_V 0x00000001U +#define LP_ANA_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/lp_ana_struct.h b/components/soc/esp32c61/include/soc/lp_ana_struct.h new file mode 100644 index 0000000000..3ea431ed45 --- /dev/null +++ b/components/soc/esp32c61/include/soc/lp_ana_struct.h @@ -0,0 +1,252 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of bod_mode0_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0; + * need_des + */ + uint32_t bod_mode0_close_flash_ena:1; + /** bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0; + * need_des + */ + uint32_t bod_mode0_pd_rf_ena:1; + /** bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1; + * need_des + */ + uint32_t bod_mode0_intr_wait:10; + /** bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023; + * need_des + */ + uint32_t bod_mode0_reset_wait:10; + /** bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t bod_mode0_cnt_clr:1; + /** bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t bod_mode0_intr_ena:1; + /** bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t bod_mode0_reset_sel:1; + /** bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_reset_ena:1; + }; + uint32_t val; +} lp_ana_bod_mode0_cntl_reg_t; + +/** Type of bod_mode1_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode1_reset_ena:1; + }; + uint32_t val; +} lp_ana_bod_mode1_cntl_reg_t; + +/** Type of power_glitch_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** power_glitch_reset_ena : R/W; bitpos: [31:28]; default: 0; + * need_des + */ + uint32_t power_glitch_reset_ena:4; + }; + uint32_t val; +} lp_ana_power_glitch_cntl_reg_t; + +/** Type of fib_enable register + * need_des + */ +typedef union { + struct { + /** ana_fib_ena : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t ana_fib_ena:32; + }; + uint32_t val; +} lp_ana_fib_enable_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_raw:1; + }; + uint32_t val; +} lp_ana_int_raw_reg_t; + +/** Type of int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_st:1; + }; + uint32_t val; +} lp_ana_int_st_reg_t; + +/** Type of int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_ena:1; + }; + uint32_t val; +} lp_ana_int_ena_reg_t; + +/** Type of int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_int_clr:1; + }; + uint32_t val; +} lp_ana_int_clr_reg_t; + +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_raw:1; + }; + uint32_t val; +} lp_ana_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_st:1; + }; + uint32_t val; +} lp_ana_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_ena:1; + }; + uint32_t val; +} lp_ana_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** bod_mode0_lp_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t bod_mode0_lp_int_clr:1; + }; + uint32_t val; +} lp_ana_lp_int_clr_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lp_ana_date : R/W; bitpos: [30:0]; default: 37752896; + * need_des + */ + uint32_t lp_ana_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_ana_date_reg_t; + + +typedef struct { + volatile lp_ana_bod_mode0_cntl_reg_t bod_mode0_cntl; + volatile lp_ana_bod_mode1_cntl_reg_t bod_mode1_cntl; + volatile lp_ana_power_glitch_cntl_reg_t power_glitch_cntl; + volatile lp_ana_fib_enable_reg_t fib_enable; + volatile lp_ana_int_raw_reg_t int_raw; + volatile lp_ana_int_st_reg_t int_st; + volatile lp_ana_int_ena_reg_t int_ena; + volatile lp_ana_int_clr_reg_t int_clr; + volatile lp_ana_lp_int_raw_reg_t lp_int_raw; + volatile lp_ana_lp_int_st_reg_t lp_int_st; + volatile lp_ana_lp_int_ena_reg_t lp_int_ena; + volatile lp_ana_lp_int_clr_reg_t lp_int_clr; + uint32_t reserved_030[243]; + volatile lp_ana_date_reg_t date; +} lp_ana_dev_t; + +extern lp_ana_dev_t LP_ANA; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_ana_dev_t) == 0x400, "Invalid size of lp_ana_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/lp_aon_reg.h b/components/soc/esp32c61/include/soc/lp_aon_reg.h new file mode 100644 index 0000000000..7ed2a522c4 --- /dev/null +++ b/components/soc/esp32c61/include/soc/lp_aon_reg.h @@ -0,0 +1,459 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_AON_STORE0_REG register + * need_des + */ +#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0) +/** LP_AON_LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE0 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE0_M (LP_AON_LP_AON_STORE0_V << LP_AON_LP_AON_STORE0_S) +#define LP_AON_LP_AON_STORE0_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE0_S 0 + +/** LP_AON_STORE1_REG register + * need_des + */ +#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4) +/** LP_AON_LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE1 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE1_M (LP_AON_LP_AON_STORE1_V << LP_AON_LP_AON_STORE1_S) +#define LP_AON_LP_AON_STORE1_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE1_S 0 + +/** LP_AON_STORE2_REG register + * need_des + */ +#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8) +/** LP_AON_LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE2 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE2_M (LP_AON_LP_AON_STORE2_V << LP_AON_LP_AON_STORE2_S) +#define LP_AON_LP_AON_STORE2_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE2_S 0 + +/** LP_AON_STORE3_REG register + * need_des + */ +#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc) +/** LP_AON_LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE3 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE3_M (LP_AON_LP_AON_STORE3_V << LP_AON_LP_AON_STORE3_S) +#define LP_AON_LP_AON_STORE3_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE3_S 0 + +/** LP_AON_STORE4_REG register + * need_des + */ +#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10) +/** LP_AON_LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE4 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE4_M (LP_AON_LP_AON_STORE4_V << LP_AON_LP_AON_STORE4_S) +#define LP_AON_LP_AON_STORE4_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE4_S 0 + +/** LP_AON_STORE5_REG register + * need_des + */ +#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14) +/** LP_AON_LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE5 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE5_M (LP_AON_LP_AON_STORE5_V << LP_AON_LP_AON_STORE5_S) +#define LP_AON_LP_AON_STORE5_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE5_S 0 + +/** LP_AON_STORE6_REG register + * need_des + */ +#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18) +/** LP_AON_LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE6 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE6_M (LP_AON_LP_AON_STORE6_V << LP_AON_LP_AON_STORE6_S) +#define LP_AON_LP_AON_STORE6_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE6_S 0 + +/** LP_AON_STORE7_REG register + * need_des + */ +#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c) +/** LP_AON_LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE7 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE7_M (LP_AON_LP_AON_STORE7_V << LP_AON_LP_AON_STORE7_S) +#define LP_AON_LP_AON_STORE7_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE7_S 0 + +/** LP_AON_STORE8_REG register + * need_des + */ +#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20) +/** LP_AON_LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE8 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE8_M (LP_AON_LP_AON_STORE8_V << LP_AON_LP_AON_STORE8_S) +#define LP_AON_LP_AON_STORE8_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE8_S 0 + +/** LP_AON_STORE9_REG register + * need_des + */ +#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24) +/** LP_AON_LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_LP_AON_STORE9 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE9_M (LP_AON_LP_AON_STORE9_V << LP_AON_LP_AON_STORE9_S) +#define LP_AON_LP_AON_STORE9_V 0xFFFFFFFFU +#define LP_AON_LP_AON_STORE9_S 0 + +/** LP_AON_GPIO_MUX_REG register + * need_des + */ +#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28) +/** LP_AON_GPIO_MUX_SEL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_MUX_SEL 0x000000FFU +#define LP_AON_GPIO_MUX_SEL_M (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S) +#define LP_AON_GPIO_MUX_SEL_V 0x000000FFU +#define LP_AON_GPIO_MUX_SEL_S 0 + +/** LP_AON_GPIO_HOLD0_REG register + * need_des + */ +#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c) +/** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_HOLD0 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD0_M (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S) +#define LP_AON_GPIO_HOLD0_V 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD0_S 0 + +/** LP_AON_GPIO_HOLD1_REG register + * need_des + */ +#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30) +/** LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define LP_AON_GPIO_HOLD1 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD1_M (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S) +#define LP_AON_GPIO_HOLD1_V 0xFFFFFFFFU +#define LP_AON_GPIO_HOLD1_S 0 + +/** LP_AON_SYS_CFG_REG register + * need_des + */ +#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34) +/** LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LP_AON_FORCE_DOWNLOAD_BOOT (BIT(30)) +#define LP_AON_FORCE_DOWNLOAD_BOOT_M (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S) +#define LP_AON_FORCE_DOWNLOAD_BOOT_V 0x00000001U +#define LP_AON_FORCE_DOWNLOAD_BOOT_S 30 +/** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_HPSYS_SW_RESET (BIT(31)) +#define LP_AON_HPSYS_SW_RESET_M (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S) +#define LP_AON_HPSYS_SW_RESET_V 0x00000001U +#define LP_AON_HPSYS_SW_RESET_S 31 + +/** LP_AON_CPUCORE0_CFG_REG register + * need_des + */ +#define LP_AON_CPUCORE0_CFG_REG (DR_REG_LP_AON_BASE + 0x38) +/** LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_SW_STALL 0x000000FFU +#define LP_AON_CPU_CORE0_SW_STALL_M (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S) +#define LP_AON_CPU_CORE0_SW_STALL_V 0x000000FFU +#define LP_AON_CPU_CORE0_SW_STALL_S 0 +/** LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [28]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_SW_RESET (BIT(28)) +#define LP_AON_CPU_CORE0_SW_RESET_M (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S) +#define LP_AON_CPU_CORE0_SW_RESET_V 0x00000001U +#define LP_AON_CPU_CORE0_SW_RESET_S 28 +/** LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET (BIT(29)) +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S) +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V 0x00000001U +#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S 29 +/** LP_AON_CPU_CORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL (BIT(30)) +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S) +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V 0x00000001U +#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S 30 +/** LP_AON_CPU_CORE0_DRESET_MASK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_CPU_CORE0_DRESET_MASK (BIT(31)) +#define LP_AON_CPU_CORE0_DRESET_MASK_M (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S) +#define LP_AON_CPU_CORE0_DRESET_MASK_V 0x00000001U +#define LP_AON_CPU_CORE0_DRESET_MASK_S 31 + +/** LP_AON_IO_MUX_REG register + * need_des + */ +#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c) +/** LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_IO_MUX_RESET_DISABLE (BIT(31)) +#define LP_AON_IO_MUX_RESET_DISABLE_M (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S) +#define LP_AON_IO_MUX_RESET_DISABLE_V 0x00000001U +#define LP_AON_IO_MUX_RESET_DISABLE_S 31 + +/** LP_AON_EXT_WAKEUP_CNTL_REG register + * need_des + */ +#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40) +/** LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [7:0]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_STATUS 0x000000FFU +#define LP_AON_EXT_WAKEUP_STATUS_M (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S) +#define LP_AON_EXT_WAKEUP_STATUS_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_STATUS_S 0 +/** LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [14]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_STATUS_CLR (BIT(14)) +#define LP_AON_EXT_WAKEUP_STATUS_CLR_M (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S) +#define LP_AON_EXT_WAKEUP_STATUS_CLR_V 0x00000001U +#define LP_AON_EXT_WAKEUP_STATUS_CLR_S 14 +/** LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [22:15]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_SEL 0x000000FFU +#define LP_AON_EXT_WAKEUP_SEL_M (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S) +#define LP_AON_EXT_WAKEUP_SEL_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_SEL_S 15 +/** LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [30:23]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_LV 0x000000FFU +#define LP_AON_EXT_WAKEUP_LV_M (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S) +#define LP_AON_EXT_WAKEUP_LV_V 0x000000FFU +#define LP_AON_EXT_WAKEUP_LV_S 23 +/** LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_EXT_WAKEUP_FILTER (BIT(31)) +#define LP_AON_EXT_WAKEUP_FILTER_M (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S) +#define LP_AON_EXT_WAKEUP_FILTER_V 0x00000001U +#define LP_AON_EXT_WAKEUP_FILTER_S 31 + +/** LP_AON_USB_REG register + * need_des + */ +#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x44) +/** LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_USB_RESET_DISABLE (BIT(31)) +#define LP_AON_USB_RESET_DISABLE_M (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S) +#define LP_AON_USB_RESET_DISABLE_V 0x00000001U +#define LP_AON_USB_RESET_DISABLE_S 31 + +/** LP_AON_LPBUS_REG register + * need_des + */ +#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48) +/** LP_AON_FAST_MEM_WPULSE : R/W; bitpos: [18:16]; default: 0; + * This field controls fast memory WPULSE parameter. + */ +#define LP_AON_FAST_MEM_WPULSE 0x00000007U +#define LP_AON_FAST_MEM_WPULSE_M (LP_AON_FAST_MEM_WPULSE_V << LP_AON_FAST_MEM_WPULSE_S) +#define LP_AON_FAST_MEM_WPULSE_V 0x00000007U +#define LP_AON_FAST_MEM_WPULSE_S 16 +/** LP_AON_FAST_MEM_WA : R/W; bitpos: [21:19]; default: 4; + * This field controls fast memory WA parameter. + */ +#define LP_AON_FAST_MEM_WA 0x00000007U +#define LP_AON_FAST_MEM_WA_M (LP_AON_FAST_MEM_WA_V << LP_AON_FAST_MEM_WA_S) +#define LP_AON_FAST_MEM_WA_V 0x00000007U +#define LP_AON_FAST_MEM_WA_S 19 +/** LP_AON_FAST_MEM_RA : R/W; bitpos: [23:22]; default: 0; + * This field controls fast memory RA parameter. + */ +#define LP_AON_FAST_MEM_RA 0x00000003U +#define LP_AON_FAST_MEM_RA_M (LP_AON_FAST_MEM_RA_V << LP_AON_FAST_MEM_RA_S) +#define LP_AON_FAST_MEM_RA_V 0x00000003U +#define LP_AON_FAST_MEM_RA_S 22 + +/** LP_AON_LPCORE_REG register + * need_des + */ +#define LP_AON_LPCORE_REG (DR_REG_LP_AON_BASE + 0x50) +/** LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR (BIT(0)) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V 0x00000001U +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S 0 +/** LP_AON_LPCORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG (BIT(1)) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_S) +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_V 0x00000001U +#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_S 1 +/** LP_AON_LPCORE_DISABLE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_LPCORE_DISABLE (BIT(31)) +#define LP_AON_LPCORE_DISABLE_M (LP_AON_LPCORE_DISABLE_V << LP_AON_LPCORE_DISABLE_S) +#define LP_AON_LPCORE_DISABLE_V 0x00000001U +#define LP_AON_LPCORE_DISABLE_S 31 + +/** LP_AON_SAR_CCT_REG register + * need_des + */ +#define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54) +/** LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0; + * need_des + */ +#define LP_AON_SAR2_PWDET_CCT 0x00000007U +#define LP_AON_SAR2_PWDET_CCT_M (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S) +#define LP_AON_SAR2_PWDET_CCT_V 0x00000007U +#define LP_AON_SAR2_PWDET_CCT_S 29 + +/** LP_AON_MODEM_BUS_REG register + * need_des + */ +#define LP_AON_MODEM_BUS_REG (DR_REG_LP_AON_BASE + 0x58) +/** LP_AON_MODEM_SYNC_BRIDGE_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_MODEM_SYNC_BRIDGE_EN (BIT(31)) +#define LP_AON_MODEM_SYNC_BRIDGE_EN_M (LP_AON_MODEM_SYNC_BRIDGE_EN_V << LP_AON_MODEM_SYNC_BRIDGE_EN_S) +#define LP_AON_MODEM_SYNC_BRIDGE_EN_V 0x00000001U +#define LP_AON_MODEM_SYNC_BRIDGE_EN_S 31 + +/** LP_AON_SPRAM_CTRL_REG register + * need_des + */ +#define LP_AON_SPRAM_CTRL_REG (DR_REG_LP_AON_BASE + 0x60) +/** LP_AON_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; + * need_des + */ +#define LP_AON_SPRAM_MEM_AUX_CTRL 0xFFFFFFFFU +#define LP_AON_SPRAM_MEM_AUX_CTRL_M (LP_AON_SPRAM_MEM_AUX_CTRL_V << LP_AON_SPRAM_MEM_AUX_CTRL_S) +#define LP_AON_SPRAM_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define LP_AON_SPRAM_MEM_AUX_CTRL_S 0 + +/** LP_AON_SPRF_CTRL_REG register + * need_des + */ +#define LP_AON_SPRF_CTRL_REG (DR_REG_LP_AON_BASE + 0x64) +/** LP_AON_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; + * need_des + */ +#define LP_AON_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU +#define LP_AON_SPRF_MEM_AUX_CTRL_M (LP_AON_SPRF_MEM_AUX_CTRL_V << LP_AON_SPRF_MEM_AUX_CTRL_S) +#define LP_AON_SPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU +#define LP_AON_SPRF_MEM_AUX_CTRL_S 0 + +/** LP_AON_DEBUG_SEL0_REG register + * need des + */ +#define LP_AON_DEBUG_SEL0_REG (DR_REG_LP_AON_BASE + 0x68) +/** LP_AON_LP_DEBUG_SEL0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ +#define LP_AON_LP_DEBUG_SEL0 0x0000007FU +#define LP_AON_LP_DEBUG_SEL0_M (LP_AON_LP_DEBUG_SEL0_V << LP_AON_LP_DEBUG_SEL0_S) +#define LP_AON_LP_DEBUG_SEL0_V 0x0000007FU +#define LP_AON_LP_DEBUG_SEL0_S 0 +/** LP_AON_LP_DEBUG_SEL1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ +#define LP_AON_LP_DEBUG_SEL1 0x0000007FU +#define LP_AON_LP_DEBUG_SEL1_M (LP_AON_LP_DEBUG_SEL1_V << LP_AON_LP_DEBUG_SEL1_S) +#define LP_AON_LP_DEBUG_SEL1_V 0x0000007FU +#define LP_AON_LP_DEBUG_SEL1_S 7 +/** LP_AON_LP_DEBUG_SEL2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ +#define LP_AON_LP_DEBUG_SEL2 0x0000007FU +#define LP_AON_LP_DEBUG_SEL2_M (LP_AON_LP_DEBUG_SEL2_V << LP_AON_LP_DEBUG_SEL2_S) +#define LP_AON_LP_DEBUG_SEL2_V 0x0000007FU +#define LP_AON_LP_DEBUG_SEL2_S 14 +/** LP_AON_LP_DEBUG_SEL3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ +#define LP_AON_LP_DEBUG_SEL3 0x0000007FU +#define LP_AON_LP_DEBUG_SEL3_M (LP_AON_LP_DEBUG_SEL3_V << LP_AON_LP_DEBUG_SEL3_S) +#define LP_AON_LP_DEBUG_SEL3_V 0x0000007FU +#define LP_AON_LP_DEBUG_SEL3_S 21 + +/** LP_AON_DEBUG_SEL1_REG register + * need des + */ +#define LP_AON_DEBUG_SEL1_REG (DR_REG_LP_AON_BASE + 0x6c) +/** LP_AON_LP_DEBUG_SEL4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ +#define LP_AON_LP_DEBUG_SEL4 0x0000007FU +#define LP_AON_LP_DEBUG_SEL4_M (LP_AON_LP_DEBUG_SEL4_V << LP_AON_LP_DEBUG_SEL4_S) +#define LP_AON_LP_DEBUG_SEL4_V 0x0000007FU +#define LP_AON_LP_DEBUG_SEL4_S 0 + +/** LP_AON_DATE_REG register + * need_des + */ +#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) +/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 36766272; + * need_des + */ +#define LP_AON_DATE 0x7FFFFFFFU +#define LP_AON_DATE_M (LP_AON_DATE_V << LP_AON_DATE_S) +#define LP_AON_DATE_V 0x7FFFFFFFU +#define LP_AON_DATE_S 0 +/** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_AON_CLK_EN (BIT(31)) +#define LP_AON_CLK_EN_M (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S) +#define LP_AON_CLK_EN_V 0x00000001U +#define LP_AON_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/lp_aon_struct.h b/components/soc/esp32c61/include/soc/lp_aon_struct.h new file mode 100644 index 0000000000..96660def85 --- /dev/null +++ b/components/soc/esp32c61/include/soc/lp_aon_struct.h @@ -0,0 +1,490 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of store0 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store0:32; + }; + uint32_t val; +} lp_aon_store0_reg_t; + +/** Type of store1 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store1:32; + }; + uint32_t val; +} lp_aon_store1_reg_t; + +/** Type of store2 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store2 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store2:32; + }; + uint32_t val; +} lp_aon_store2_reg_t; + +/** Type of store3 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store3 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store3:32; + }; + uint32_t val; +} lp_aon_store3_reg_t; + +/** Type of store4 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store4 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store4:32; + }; + uint32_t val; +} lp_aon_store4_reg_t; + +/** Type of store5 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store5 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store5:32; + }; + uint32_t val; +} lp_aon_store5_reg_t; + +/** Type of store6 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store6 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store6:32; + }; + uint32_t val; +} lp_aon_store6_reg_t; + +/** Type of store7 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store7 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store7:32; + }; + uint32_t val; +} lp_aon_store7_reg_t; + +/** Type of store8 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store8 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store8:32; + }; + uint32_t val; +} lp_aon_store8_reg_t; + +/** Type of store9 register + * need_des + */ +typedef union { + struct { + /** lp_aon_store9 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_aon_store9:32; + }; + uint32_t val; +} lp_aon_store9_reg_t; + +/** Type of gpio_mux register + * need_des + */ +typedef union { + struct { + /** gpio_mux_sel : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t gpio_mux_sel:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} lp_aon_gpio_mux_reg_t; + +/** Type of gpio_hold0 register + * need_des + */ +typedef union { + struct { + /** gpio_hold0 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t gpio_hold0:32; + }; + uint32_t val; +} lp_aon_gpio_hold0_reg_t; + +/** Type of gpio_hold1 register + * need_des + */ +typedef union { + struct { + /** gpio_hold1 : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t gpio_hold1:32; + }; + uint32_t val; +} lp_aon_gpio_hold1_reg_t; + +/** Type of sys_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** force_download_boot : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t force_download_boot:1; + /** hpsys_sw_reset : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hpsys_sw_reset:1; + }; + uint32_t val; +} lp_aon_sys_cfg_reg_t; + +/** Type of cpucore0_cfg register + * need_des + */ +typedef union { + struct { + /** cpu_core0_sw_stall : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t cpu_core0_sw_stall:8; + uint32_t reserved_8:20; + /** cpu_core0_sw_reset : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t cpu_core0_sw_reset:1; + /** cpu_core0_ocd_halt_on_reset : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t cpu_core0_ocd_halt_on_reset:1; + /** cpu_core0_stat_vector_sel : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t cpu_core0_stat_vector_sel:1; + /** cpu_core0_dreset_mask : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t cpu_core0_dreset_mask:1; + }; + uint32_t val; +} lp_aon_cpucore0_cfg_reg_t; + +/** Type of io_mux register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** io_mux_reset_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t io_mux_reset_disable:1; + }; + uint32_t val; +} lp_aon_io_mux_reg_t; + +/** Type of ext_wakeup_cntl register + * need_des + */ +typedef union { + struct { + /** ext_wakeup_status : RO; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t ext_wakeup_status:8; + uint32_t reserved_8:6; + /** ext_wakeup_status_clr : WT; bitpos: [14]; default: 0; + * need_des + */ + uint32_t ext_wakeup_status_clr:1; + /** ext_wakeup_sel : R/W; bitpos: [22:15]; default: 0; + * need_des + */ + uint32_t ext_wakeup_sel:8; + /** ext_wakeup_lv : R/W; bitpos: [30:23]; default: 0; + * need_des + */ + uint32_t ext_wakeup_lv:8; + /** ext_wakeup_filter : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ext_wakeup_filter:1; + }; + uint32_t val; +} lp_aon_ext_wakeup_cntl_reg_t; + +/** Type of usb register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** usb_reset_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t usb_reset_disable:1; + }; + uint32_t val; +} lp_aon_usb_reg_t; + +/** Type of lpbus register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** fast_mem_wpulse : R/W; bitpos: [18:16]; default: 0; + * This field controls fast memory WPULSE parameter. + */ + uint32_t fast_mem_wpulse:3; + /** fast_mem_wa : R/W; bitpos: [21:19]; default: 4; + * This field controls fast memory WA parameter. + */ + uint32_t fast_mem_wa:3; + /** fast_mem_ra : R/W; bitpos: [23:22]; default: 0; + * This field controls fast memory RA parameter. + */ + uint32_t fast_mem_ra:2; + uint32_t reserved_24:8; + }; + uint32_t val; +} lp_aon_lpbus_reg_t; + +/** Type of lpcore register + * need_des + */ +typedef union { + struct { + /** lpcore_etm_wakeup_flag_clr : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t lpcore_etm_wakeup_flag_clr:1; + /** lpcore_etm_wakeup_flag : R/WTC/SS; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lpcore_etm_wakeup_flag:1; + uint32_t reserved_2:29; + /** lpcore_disable : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lpcore_disable:1; + }; + uint32_t val; +} lp_aon_lpcore_reg_t; + +/** Type of sar_cct register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:29; + /** sar2_pwdet_cct : R/W; bitpos: [31:29]; default: 0; + * need_des + */ + uint32_t sar2_pwdet_cct:3; + }; + uint32_t val; +} lp_aon_sar_cct_reg_t; + +/** Type of modem_bus register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** modem_sync_bridge_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t modem_sync_bridge_en:1; + }; + uint32_t val; +} lp_aon_modem_bus_reg_t; + +/** Type of debug_sel0 register + * need des + */ +typedef union { + struct { + /** lp_debug_sel0 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t lp_debug_sel0:7; + /** lp_debug_sel1 : R/W; bitpos: [13:7]; default: 0; + * need des + */ + uint32_t lp_debug_sel1:7; + /** lp_debug_sel2 : R/W; bitpos: [20:14]; default: 0; + * need des + */ + uint32_t lp_debug_sel2:7; + /** lp_debug_sel3 : R/W; bitpos: [27:21]; default: 0; + * need des + */ + uint32_t lp_debug_sel3:7; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_aon_debug_sel0_reg_t; + +/** Type of debug_sel1 register + * need des + */ +typedef union { + struct { + /** lp_debug_sel4 : R/W; bitpos: [6:0]; default: 0; + * need des + */ + uint32_t lp_debug_sel4:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_aon_debug_sel1_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** date : R/W; bitpos: [30:0]; default: 36766272; + * need_des + */ + uint32_t date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_aon_date_reg_t; + + +/** Group: Configuration Register */ +/** Type of spram_ctrl register + * need_des + */ +typedef union { + struct { + /** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; + * need_des + */ + uint32_t spram_mem_aux_ctrl:32; + }; + uint32_t val; +} lp_aon_spram_ctrl_reg_t; + +/** Type of sprf_ctrl register + * need_des + */ +typedef union { + struct { + /** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; + * need_des + */ + uint32_t sprf_mem_aux_ctrl:32; + }; + uint32_t val; +} lp_aon_sprf_ctrl_reg_t; + + +typedef struct { + volatile lp_aon_store0_reg_t store0; + volatile lp_aon_store1_reg_t store1; + volatile lp_aon_store2_reg_t store2; + volatile lp_aon_store3_reg_t store3; + volatile lp_aon_store4_reg_t store4; + volatile lp_aon_store5_reg_t store5; + volatile lp_aon_store6_reg_t store6; + volatile lp_aon_store7_reg_t store7; + volatile lp_aon_store8_reg_t store8; + volatile lp_aon_store9_reg_t store9; + volatile lp_aon_gpio_mux_reg_t gpio_mux; + volatile lp_aon_gpio_hold0_reg_t gpio_hold0; + volatile lp_aon_gpio_hold1_reg_t gpio_hold1; + volatile lp_aon_sys_cfg_reg_t sys_cfg; + volatile lp_aon_cpucore0_cfg_reg_t cpucore0_cfg; + volatile lp_aon_io_mux_reg_t io_mux; + volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl; + volatile lp_aon_usb_reg_t usb; + volatile lp_aon_lpbus_reg_t lpbus; + uint32_t reserved_04c; + volatile lp_aon_lpcore_reg_t lpcore; + volatile lp_aon_sar_cct_reg_t sar_cct; + volatile lp_aon_modem_bus_reg_t modem_bus; + uint32_t reserved_05c; + volatile lp_aon_spram_ctrl_reg_t spram_ctrl; + volatile lp_aon_sprf_ctrl_reg_t sprf_ctrl; + volatile lp_aon_debug_sel0_reg_t debug_sel0; + volatile lp_aon_debug_sel1_reg_t debug_sel1; + uint32_t reserved_070[227]; + volatile lp_aon_date_reg_t date; +} lp_aon_dev_t; + +extern lp_aon_dev_t LP_AON; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_aon_dev_t) == 0x400, "Invalid size of lp_aon_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/lp_apm_reg.h b/components/soc/esp32c61/include/soc/lp_apm_reg.h new file mode 100644 index 0000000000..fc1cf69102 --- /dev/null +++ b/components/soc/esp32c61/include/soc/lp_apm_reg.h @@ -0,0 +1,542 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_APM_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0) +/** LP_APM_REGION_FILTER_EN : R/W; bitpos: [3:0]; default: 1; + * Configure bit $n (0-3) to enable region $n.\\ + * 0: disable \\ + * 1: enable \\ + */ +#define LP_APM_REGION_FILTER_EN 0x0000000FU +#define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S) +#define LP_APM_REGION_FILTER_EN_V 0x0000000FU +#define LP_APM_REGION_FILTER_EN_S 0 + +/** LP_APM_REGION0_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4) +/** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 0. + */ +#define LP_APM_REGION0_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_START_M (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S) +#define LP_APM_REGION0_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_START_S 0 + +/** LP_APM_REGION0_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8) +/** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 0. + */ +#define LP_APM_REGION0_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_END_M (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S) +#define LP_APM_REGION0_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION0_ADDR_END_S 0 + +/** LP_APM_REGION0_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION0_ATTR_REG (DR_REG_LP_APM_BASE + 0xc) +/** LP_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 0. + */ +#define LP_APM_REGION0_R0_X (BIT(0)) +#define LP_APM_REGION0_R0_X_M (LP_APM_REGION0_R0_X_V << LP_APM_REGION0_R0_X_S) +#define LP_APM_REGION0_R0_X_V 0x00000001U +#define LP_APM_REGION0_R0_X_S 0 +/** LP_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 0. + */ +#define LP_APM_REGION0_R0_W (BIT(1)) +#define LP_APM_REGION0_R0_W_M (LP_APM_REGION0_R0_W_V << LP_APM_REGION0_R0_W_S) +#define LP_APM_REGION0_R0_W_V 0x00000001U +#define LP_APM_REGION0_R0_W_S 1 +/** LP_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 0. + */ +#define LP_APM_REGION0_R0_R (BIT(2)) +#define LP_APM_REGION0_R0_R_M (LP_APM_REGION0_R0_R_V << LP_APM_REGION0_R0_R_S) +#define LP_APM_REGION0_R0_R_V 0x00000001U +#define LP_APM_REGION0_R0_R_S 2 +/** LP_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 0. + */ +#define LP_APM_REGION0_R1_X (BIT(4)) +#define LP_APM_REGION0_R1_X_M (LP_APM_REGION0_R1_X_V << LP_APM_REGION0_R1_X_S) +#define LP_APM_REGION0_R1_X_V 0x00000001U +#define LP_APM_REGION0_R1_X_S 4 +/** LP_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 0. + */ +#define LP_APM_REGION0_R1_W (BIT(5)) +#define LP_APM_REGION0_R1_W_M (LP_APM_REGION0_R1_W_V << LP_APM_REGION0_R1_W_S) +#define LP_APM_REGION0_R1_W_V 0x00000001U +#define LP_APM_REGION0_R1_W_S 5 +/** LP_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 0. + */ +#define LP_APM_REGION0_R1_R (BIT(6)) +#define LP_APM_REGION0_R1_R_M (LP_APM_REGION0_R1_R_V << LP_APM_REGION0_R1_R_S) +#define LP_APM_REGION0_R1_R_V 0x00000001U +#define LP_APM_REGION0_R1_R_S 6 +/** LP_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 0. + */ +#define LP_APM_REGION0_R2_X (BIT(8)) +#define LP_APM_REGION0_R2_X_M (LP_APM_REGION0_R2_X_V << LP_APM_REGION0_R2_X_S) +#define LP_APM_REGION0_R2_X_V 0x00000001U +#define LP_APM_REGION0_R2_X_S 8 +/** LP_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 0. + */ +#define LP_APM_REGION0_R2_W (BIT(9)) +#define LP_APM_REGION0_R2_W_M (LP_APM_REGION0_R2_W_V << LP_APM_REGION0_R2_W_S) +#define LP_APM_REGION0_R2_W_V 0x00000001U +#define LP_APM_REGION0_R2_W_S 9 +/** LP_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 0. + */ +#define LP_APM_REGION0_R2_R (BIT(10)) +#define LP_APM_REGION0_R2_R_M (LP_APM_REGION0_R2_R_V << LP_APM_REGION0_R2_R_S) +#define LP_APM_REGION0_R2_R_V 0x00000001U +#define LP_APM_REGION0_R2_R_S 10 +/** LP_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define LP_APM_REGION0_LOCK (BIT(11)) +#define LP_APM_REGION0_LOCK_M (LP_APM_REGION0_LOCK_V << LP_APM_REGION0_LOCK_S) +#define LP_APM_REGION0_LOCK_V 0x00000001U +#define LP_APM_REGION0_LOCK_S 11 + +/** LP_APM_REGION1_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10) +/** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 1. + */ +#define LP_APM_REGION1_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_START_M (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S) +#define LP_APM_REGION1_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_START_S 0 + +/** LP_APM_REGION1_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14) +/** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 1. + */ +#define LP_APM_REGION1_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_END_M (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S) +#define LP_APM_REGION1_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION1_ADDR_END_S 0 + +/** LP_APM_REGION1_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION1_ATTR_REG (DR_REG_LP_APM_BASE + 0x18) +/** LP_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 1. + */ +#define LP_APM_REGION1_R0_X (BIT(0)) +#define LP_APM_REGION1_R0_X_M (LP_APM_REGION1_R0_X_V << LP_APM_REGION1_R0_X_S) +#define LP_APM_REGION1_R0_X_V 0x00000001U +#define LP_APM_REGION1_R0_X_S 0 +/** LP_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 1. + */ +#define LP_APM_REGION1_R0_W (BIT(1)) +#define LP_APM_REGION1_R0_W_M (LP_APM_REGION1_R0_W_V << LP_APM_REGION1_R0_W_S) +#define LP_APM_REGION1_R0_W_V 0x00000001U +#define LP_APM_REGION1_R0_W_S 1 +/** LP_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 1. + */ +#define LP_APM_REGION1_R0_R (BIT(2)) +#define LP_APM_REGION1_R0_R_M (LP_APM_REGION1_R0_R_V << LP_APM_REGION1_R0_R_S) +#define LP_APM_REGION1_R0_R_V 0x00000001U +#define LP_APM_REGION1_R0_R_S 2 +/** LP_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 1. + */ +#define LP_APM_REGION1_R1_X (BIT(4)) +#define LP_APM_REGION1_R1_X_M (LP_APM_REGION1_R1_X_V << LP_APM_REGION1_R1_X_S) +#define LP_APM_REGION1_R1_X_V 0x00000001U +#define LP_APM_REGION1_R1_X_S 4 +/** LP_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 1. + */ +#define LP_APM_REGION1_R1_W (BIT(5)) +#define LP_APM_REGION1_R1_W_M (LP_APM_REGION1_R1_W_V << LP_APM_REGION1_R1_W_S) +#define LP_APM_REGION1_R1_W_V 0x00000001U +#define LP_APM_REGION1_R1_W_S 5 +/** LP_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 1. + */ +#define LP_APM_REGION1_R1_R (BIT(6)) +#define LP_APM_REGION1_R1_R_M (LP_APM_REGION1_R1_R_V << LP_APM_REGION1_R1_R_S) +#define LP_APM_REGION1_R1_R_V 0x00000001U +#define LP_APM_REGION1_R1_R_S 6 +/** LP_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 1. + */ +#define LP_APM_REGION1_R2_X (BIT(8)) +#define LP_APM_REGION1_R2_X_M (LP_APM_REGION1_R2_X_V << LP_APM_REGION1_R2_X_S) +#define LP_APM_REGION1_R2_X_V 0x00000001U +#define LP_APM_REGION1_R2_X_S 8 +/** LP_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 1. + */ +#define LP_APM_REGION1_R2_W (BIT(9)) +#define LP_APM_REGION1_R2_W_M (LP_APM_REGION1_R2_W_V << LP_APM_REGION1_R2_W_S) +#define LP_APM_REGION1_R2_W_V 0x00000001U +#define LP_APM_REGION1_R2_W_S 9 +/** LP_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 1. + */ +#define LP_APM_REGION1_R2_R (BIT(10)) +#define LP_APM_REGION1_R2_R_M (LP_APM_REGION1_R2_R_V << LP_APM_REGION1_R2_R_S) +#define LP_APM_REGION1_R2_R_V 0x00000001U +#define LP_APM_REGION1_R2_R_S 10 +/** LP_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define LP_APM_REGION1_LOCK (BIT(11)) +#define LP_APM_REGION1_LOCK_M (LP_APM_REGION1_LOCK_V << LP_APM_REGION1_LOCK_S) +#define LP_APM_REGION1_LOCK_V 0x00000001U +#define LP_APM_REGION1_LOCK_S 11 + +/** LP_APM_REGION2_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION2_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x1c) +/** LP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 2. + */ +#define LP_APM_REGION2_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_START_M (LP_APM_REGION2_ADDR_START_V << LP_APM_REGION2_ADDR_START_S) +#define LP_APM_REGION2_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_START_S 0 + +/** LP_APM_REGION2_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION2_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x20) +/** LP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 2. + */ +#define LP_APM_REGION2_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_END_M (LP_APM_REGION2_ADDR_END_V << LP_APM_REGION2_ADDR_END_S) +#define LP_APM_REGION2_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION2_ADDR_END_S 0 + +/** LP_APM_REGION2_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION2_ATTR_REG (DR_REG_LP_APM_BASE + 0x24) +/** LP_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 2. + */ +#define LP_APM_REGION2_R0_X (BIT(0)) +#define LP_APM_REGION2_R0_X_M (LP_APM_REGION2_R0_X_V << LP_APM_REGION2_R0_X_S) +#define LP_APM_REGION2_R0_X_V 0x00000001U +#define LP_APM_REGION2_R0_X_S 0 +/** LP_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 2. + */ +#define LP_APM_REGION2_R0_W (BIT(1)) +#define LP_APM_REGION2_R0_W_M (LP_APM_REGION2_R0_W_V << LP_APM_REGION2_R0_W_S) +#define LP_APM_REGION2_R0_W_V 0x00000001U +#define LP_APM_REGION2_R0_W_S 1 +/** LP_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 2. + */ +#define LP_APM_REGION2_R0_R (BIT(2)) +#define LP_APM_REGION2_R0_R_M (LP_APM_REGION2_R0_R_V << LP_APM_REGION2_R0_R_S) +#define LP_APM_REGION2_R0_R_V 0x00000001U +#define LP_APM_REGION2_R0_R_S 2 +/** LP_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 2. + */ +#define LP_APM_REGION2_R1_X (BIT(4)) +#define LP_APM_REGION2_R1_X_M (LP_APM_REGION2_R1_X_V << LP_APM_REGION2_R1_X_S) +#define LP_APM_REGION2_R1_X_V 0x00000001U +#define LP_APM_REGION2_R1_X_S 4 +/** LP_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 2. + */ +#define LP_APM_REGION2_R1_W (BIT(5)) +#define LP_APM_REGION2_R1_W_M (LP_APM_REGION2_R1_W_V << LP_APM_REGION2_R1_W_S) +#define LP_APM_REGION2_R1_W_V 0x00000001U +#define LP_APM_REGION2_R1_W_S 5 +/** LP_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 2. + */ +#define LP_APM_REGION2_R1_R (BIT(6)) +#define LP_APM_REGION2_R1_R_M (LP_APM_REGION2_R1_R_V << LP_APM_REGION2_R1_R_S) +#define LP_APM_REGION2_R1_R_V 0x00000001U +#define LP_APM_REGION2_R1_R_S 6 +/** LP_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 2. + */ +#define LP_APM_REGION2_R2_X (BIT(8)) +#define LP_APM_REGION2_R2_X_M (LP_APM_REGION2_R2_X_V << LP_APM_REGION2_R2_X_S) +#define LP_APM_REGION2_R2_X_V 0x00000001U +#define LP_APM_REGION2_R2_X_S 8 +/** LP_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 2. + */ +#define LP_APM_REGION2_R2_W (BIT(9)) +#define LP_APM_REGION2_R2_W_M (LP_APM_REGION2_R2_W_V << LP_APM_REGION2_R2_W_S) +#define LP_APM_REGION2_R2_W_V 0x00000001U +#define LP_APM_REGION2_R2_W_S 9 +/** LP_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 2. + */ +#define LP_APM_REGION2_R2_R (BIT(10)) +#define LP_APM_REGION2_R2_R_M (LP_APM_REGION2_R2_R_V << LP_APM_REGION2_R2_R_S) +#define LP_APM_REGION2_R2_R_V 0x00000001U +#define LP_APM_REGION2_R2_R_S 10 +/** LP_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define LP_APM_REGION2_LOCK (BIT(11)) +#define LP_APM_REGION2_LOCK_M (LP_APM_REGION2_LOCK_V << LP_APM_REGION2_LOCK_S) +#define LP_APM_REGION2_LOCK_V 0x00000001U +#define LP_APM_REGION2_LOCK_S 11 + +/** LP_APM_REGION3_ADDR_START_REG register + * Region address register + */ +#define LP_APM_REGION3_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x28) +/** LP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region 3. + */ +#define LP_APM_REGION3_ADDR_START 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_START_M (LP_APM_REGION3_ADDR_START_V << LP_APM_REGION3_ADDR_START_S) +#define LP_APM_REGION3_ADDR_START_V 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_START_S 0 + +/** LP_APM_REGION3_ADDR_END_REG register + * Region address register + */ +#define LP_APM_REGION3_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x2c) +/** LP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region 3. + */ +#define LP_APM_REGION3_ADDR_END 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_END_M (LP_APM_REGION3_ADDR_END_V << LP_APM_REGION3_ADDR_END_S) +#define LP_APM_REGION3_ADDR_END_V 0xFFFFFFFFU +#define LP_APM_REGION3_ADDR_END_S 0 + +/** LP_APM_REGION3_ATTR_REG register + * Region access authority attribute register + */ +#define LP_APM_REGION3_ATTR_REG (DR_REG_LP_APM_BASE + 0x30) +/** LP_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 3. + */ +#define LP_APM_REGION3_R0_X (BIT(0)) +#define LP_APM_REGION3_R0_X_M (LP_APM_REGION3_R0_X_V << LP_APM_REGION3_R0_X_S) +#define LP_APM_REGION3_R0_X_V 0x00000001U +#define LP_APM_REGION3_R0_X_S 0 +/** LP_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 3. + */ +#define LP_APM_REGION3_R0_W (BIT(1)) +#define LP_APM_REGION3_R0_W_M (LP_APM_REGION3_R0_W_V << LP_APM_REGION3_R0_W_S) +#define LP_APM_REGION3_R0_W_V 0x00000001U +#define LP_APM_REGION3_R0_W_S 1 +/** LP_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 3. + */ +#define LP_APM_REGION3_R0_R (BIT(2)) +#define LP_APM_REGION3_R0_R_M (LP_APM_REGION3_R0_R_V << LP_APM_REGION3_R0_R_S) +#define LP_APM_REGION3_R0_R_V 0x00000001U +#define LP_APM_REGION3_R0_R_S 2 +/** LP_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 3. + */ +#define LP_APM_REGION3_R1_X (BIT(4)) +#define LP_APM_REGION3_R1_X_M (LP_APM_REGION3_R1_X_V << LP_APM_REGION3_R1_X_S) +#define LP_APM_REGION3_R1_X_V 0x00000001U +#define LP_APM_REGION3_R1_X_S 4 +/** LP_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 3. + */ +#define LP_APM_REGION3_R1_W (BIT(5)) +#define LP_APM_REGION3_R1_W_M (LP_APM_REGION3_R1_W_V << LP_APM_REGION3_R1_W_S) +#define LP_APM_REGION3_R1_W_V 0x00000001U +#define LP_APM_REGION3_R1_W_S 5 +/** LP_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 3. + */ +#define LP_APM_REGION3_R1_R (BIT(6)) +#define LP_APM_REGION3_R1_R_M (LP_APM_REGION3_R1_R_V << LP_APM_REGION3_R1_R_S) +#define LP_APM_REGION3_R1_R_V 0x00000001U +#define LP_APM_REGION3_R1_R_S 6 +/** LP_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 3. + */ +#define LP_APM_REGION3_R2_X (BIT(8)) +#define LP_APM_REGION3_R2_X_M (LP_APM_REGION3_R2_X_V << LP_APM_REGION3_R2_X_S) +#define LP_APM_REGION3_R2_X_V 0x00000001U +#define LP_APM_REGION3_R2_X_S 8 +/** LP_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 3. + */ +#define LP_APM_REGION3_R2_W (BIT(9)) +#define LP_APM_REGION3_R2_W_M (LP_APM_REGION3_R2_W_V << LP_APM_REGION3_R2_W_S) +#define LP_APM_REGION3_R2_W_V 0x00000001U +#define LP_APM_REGION3_R2_W_S 9 +/** LP_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 3. + */ +#define LP_APM_REGION3_R2_R (BIT(10)) +#define LP_APM_REGION3_R2_R_M (LP_APM_REGION3_R2_R_V << LP_APM_REGION3_R2_R_S) +#define LP_APM_REGION3_R2_R_V 0x00000001U +#define LP_APM_REGION3_R2_R_S 10 +/** LP_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define LP_APM_REGION3_LOCK (BIT(11)) +#define LP_APM_REGION3_LOCK_M (LP_APM_REGION3_LOCK_V << LP_APM_REGION3_LOCK_S) +#define LP_APM_REGION3_LOCK_V 0x00000001U +#define LP_APM_REGION3_LOCK_S 11 + +/** LP_APM_FUNC_CTRL_REG register + * APM function control register + */ +#define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4) +/** LP_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define LP_APM_M0_FUNC_EN (BIT(0)) +#define LP_APM_M0_FUNC_EN_M (LP_APM_M0_FUNC_EN_V << LP_APM_M0_FUNC_EN_S) +#define LP_APM_M0_FUNC_EN_V 0x00000001U +#define LP_APM_M0_FUNC_EN_S 0 + +/** LP_APM_M0_STATUS_REG register + * M0 status register + */ +#define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8) +/** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Represents exception status.\\ + * bit0: 1 represents authority_exception \\ + * bit1: 1 represents space_exception \\ + */ +#define LP_APM_M0_EXCEPTION_STATUS 0x00000003U +#define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S) +#define LP_APM_M0_EXCEPTION_STATUS_V 0x00000003U +#define LP_APM_M0_EXCEPTION_STATUS_S 0 + +/** LP_APM_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc) +/** LP_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ +#define LP_APM_M0_EXCEPTION_STATUS_CLR (BIT(0)) +#define LP_APM_M0_EXCEPTION_STATUS_CLR_M (LP_APM_M0_EXCEPTION_STATUS_CLR_V << LP_APM_M0_EXCEPTION_STATUS_CLR_S) +#define LP_APM_M0_EXCEPTION_STATUS_CLR_V 0x00000001U +#define LP_APM_M0_EXCEPTION_STATUS_CLR_S 0 + +/** LP_APM_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0) +/** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [3:0]; default: 0; + * Represents exception region. + */ +#define LP_APM_M0_EXCEPTION_REGION 0x0000000FU +#define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S) +#define LP_APM_M0_EXCEPTION_REGION_V 0x0000000FU +#define LP_APM_M0_EXCEPTION_REGION_S 0 +/** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ +#define LP_APM_M0_EXCEPTION_MODE 0x00000003U +#define LP_APM_M0_EXCEPTION_MODE_M (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S) +#define LP_APM_M0_EXCEPTION_MODE_V 0x00000003U +#define LP_APM_M0_EXCEPTION_MODE_S 16 +/** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ +#define LP_APM_M0_EXCEPTION_ID 0x0000001FU +#define LP_APM_M0_EXCEPTION_ID_M (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S) +#define LP_APM_M0_EXCEPTION_ID_V 0x0000001FU +#define LP_APM_M0_EXCEPTION_ID_S 18 + +/** LP_APM_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4) +/** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ +#define LP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define LP_APM_M0_EXCEPTION_ADDR_M (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S) +#define LP_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define LP_APM_M0_EXCEPTION_ADDR_S 0 + +/** LP_APM_INT_EN_REG register + * APM interrupt enable register + */ +#define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8) +/** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * Configures to enable APM M0 interrupt.\\ + * 0: disable \\ + * 1: enable \\ + */ +#define LP_APM_M0_APM_INT_EN (BIT(0)) +#define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S) +#define LP_APM_M0_APM_INT_EN_V 0x00000001U +#define LP_APM_M0_APM_INT_EN_S 0 + +/** LP_APM_CLOCK_GATE_REG register + * clock gating register + */ +#define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec) +/** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on.\\ + * 0: enable automatic clock gating \\ + * 1: keep the clock always on \\ + */ +#define LP_APM_CLK_EN (BIT(0)) +#define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S) +#define LP_APM_CLK_EN_V 0x00000001U +#define LP_APM_CLK_EN_S 0 + +/** LP_APM_DATE_REG register + * Version control register + */ +#define LP_APM_DATE_REG (DR_REG_LP_APM_BASE + 0xfc) +/** LP_APM_DATE : R/W; bitpos: [27:0]; default: 35725664; + * Version control register. + */ +#define LP_APM_DATE 0x0FFFFFFFU +#define LP_APM_DATE_M (LP_APM_DATE_V << LP_APM_DATE_S) +#define LP_APM_DATE_V 0x0FFFFFFFU +#define LP_APM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/lp_apm_struct.h b/components/soc/esp32c61/include/soc/lp_apm_struct.h new file mode 100644 index 0000000000..d751b98564 --- /dev/null +++ b/components/soc/esp32c61/include/soc/lp_apm_struct.h @@ -0,0 +1,290 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** region_filter_en : R/W; bitpos: [3:0]; default: 1; + * Configure bit $n (0-3) to enable region $n.\\ + * 0: disable \\ + * 1: enable \\ + */ + uint32_t region_filter_en:4; + uint32_t reserved_4:28; + }; + uint32_t val; +} lp_apm_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of regionn_addr_start register + * Region address register + */ +typedef union { + struct { + /** regionn_addr_start : R/W; bitpos: [31:0]; default: 0; + * Configures start address of region n. + */ + uint32_t regionn_addr_start:32; + }; + uint32_t val; +} lp_apm_regionn_addr_start_reg_t; + +/** Type of regionn_addr_end register + * Region address register + */ +typedef union { + struct { + /** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295; + * Configures end address of region n. + */ + uint32_t regionn_addr_end:32; + }; + uint32_t val; +} lp_apm_regionn_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of regionn_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** regionn_r0_x : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region n. + */ + uint32_t regionn_r0_x:1; + /** regionn_r0_w : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region n. + */ + uint32_t regionn_r0_w:1; + /** regionn_r0_r : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region n. + */ + uint32_t regionn_r0_r:1; + uint32_t reserved_3:1; + /** regionn_r1_x : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region n. + */ + uint32_t regionn_r1_x:1; + /** regionn_r1_w : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region n. + */ + uint32_t regionn_r1_w:1; + /** regionn_r1_r : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region n. + */ + uint32_t regionn_r1_r:1; + uint32_t reserved_7:1; + /** regionn_r2_x : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region n. + */ + uint32_t regionn_r2_x:1; + /** regionn_r2_w : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region n. + */ + uint32_t regionn_r2_w:1; + /** regionn_r2_r : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region n. + */ + uint32_t regionn_r2_r:1; + /** regionn_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ + uint32_t regionn_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_apm_regionn_attr_reg_t; + + +/** Group: function control register */ +/** Type of func_ctrl register + * APM function control register + */ +typedef union { + struct { + /** m0_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t m0_func_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of m0_status register + * M0 status register + */ +typedef union { + struct { + /** m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Represents exception status.\\ + * bit0: 1 represents authority_exception \\ + * bit1: 1 represents space_exception \\ + */ + uint32_t m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} lp_apm_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** m0_exception_status_clr : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ + uint32_t m0_exception_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** m0_exception_region : RO; bitpos: [3:0]; default: 0; + * Represents exception region. + */ + uint32_t m0_exception_region:4; + uint32_t reserved_4:12; + /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ + uint32_t m0_exception_mode:2; + /** m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ + uint32_t m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} lp_apm_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ + uint32_t m0_exception_addr:32; + }; + uint32_t val; +} lp_apm_m0_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * Configures to enable APM M0 interrupt.\\ + * 0: disable \\ + * 1: enable \\ + */ + uint32_t m0_apm_int_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_int_en_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on.\\ + * 0: enable automatic clock gating \\ + * 1: keep the clock always on \\ + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_apm_clock_gate_reg_t; + + +/** Group: Version control register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35725664; + * Version control register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_apm_date_reg_t; + + +typedef struct { + volatile lp_apm_region_filter_en_reg_t region_filter_en; + volatile lp_apm_regionn_addr_start_reg_t region0_addr_start; + volatile lp_apm_regionn_addr_end_reg_t region0_addr_end; + volatile lp_apm_regionn_attr_reg_t region0_attr; + volatile lp_apm_regionn_addr_start_reg_t region1_addr_start; + volatile lp_apm_regionn_addr_end_reg_t region1_addr_end; + volatile lp_apm_regionn_attr_reg_t region1_attr; + volatile lp_apm_regionn_addr_start_reg_t region2_addr_start; + volatile lp_apm_regionn_addr_end_reg_t region2_addr_end; + volatile lp_apm_regionn_attr_reg_t region2_attr; + volatile lp_apm_regionn_addr_start_reg_t region3_addr_start; + volatile lp_apm_regionn_addr_end_reg_t region3_addr_end; + volatile lp_apm_regionn_attr_reg_t region3_attr; + uint32_t reserved_034[36]; + volatile lp_apm_func_ctrl_reg_t func_ctrl; + volatile lp_apm_m0_status_reg_t m0_status; + volatile lp_apm_m0_status_clr_reg_t m0_status_clr; + volatile lp_apm_m0_exception_info0_reg_t m0_exception_info0; + volatile lp_apm_m0_exception_info1_reg_t m0_exception_info1; + uint32_t reserved_0d8[4]; + volatile lp_apm_int_en_reg_t int_en; + volatile lp_apm_clock_gate_reg_t clock_gate; + uint32_t reserved_0f0[3]; + volatile lp_apm_date_reg_t date; +} lp_apm_dev_t; + +extern lp_apm_dev_t LP_APM; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_apm_dev_t) == 0x100, "Invalid size of lp_apm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/lp_clkrst_reg.h b/components/soc/esp32c61/include/soc/lp_clkrst_reg.h new file mode 100644 index 0000000000..55d2fb2315 --- /dev/null +++ b/components/soc/esp32c61/include/soc/lp_clkrst_reg.h @@ -0,0 +1,438 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_CLKRST_LP_CLK_CONF_REG register + * Configures the root clk of LP system + */ +#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0) +/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * Configures the source of LP_SLOW_CLK. + * 0: RC_SLOW_CLK + * 1: XTAL32K_CLK + * 2: RC32K_CLK + * 3:OSC_SLOW_CLK + */ +#define LP_CLKRST_SLOW_CLK_SEL 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S) +#define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U +#define LP_CLKRST_SLOW_CLK_SEL_S 0 +/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1; + * configures the source of LP_FAST_CLK. + * 0: RC_FAST_CLK + * 1: XTAL_D2_CLK + * 2: XTAL_CLK + */ +#define LP_CLKRST_FAST_CLK_SEL 0x00000003U +#define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S) +#define LP_CLKRST_FAST_CLK_SEL_V 0x00000003U +#define LP_CLKRST_FAST_CLK_SEL_S 2 +/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [11:4]; default: 0; + * reserved + */ +#define LP_CLKRST_LP_PERI_DIV_NUM 0x000000FFU +#define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S) +#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x000000FFU +#define LP_CLKRST_LP_PERI_DIV_NUM_S 4 + +/** LP_CLKRST_LP_CLK_PO_EN_REG register + * Configures the clk gate to pad + */ +#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4) +/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1; + * Configures the clock gate to pad of the LP_DYN_SLOW_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_AON_SLOW_OEN (BIT(0)) +#define LP_CLKRST_AON_SLOW_OEN_M (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S) +#define LP_CLKRST_AON_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_AON_SLOW_OEN_S 0 +/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1; + * Configures the clock gate to pad of the LP_DYN_FAST_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_AON_FAST_OEN (BIT(1)) +#define LP_CLKRST_AON_FAST_OEN_M (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S) +#define LP_CLKRST_AON_FAST_OEN_V 0x00000001U +#define LP_CLKRST_AON_FAST_OEN_S 1 +/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1; + * Configures the clock gate to pad of the OSC_SLOW_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_SOSC_OEN (BIT(2)) +#define LP_CLKRST_SOSC_OEN_M (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S) +#define LP_CLKRST_SOSC_OEN_V 0x00000001U +#define LP_CLKRST_SOSC_OEN_S 2 +/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1; + * Configures the clock gate to pad of the RC_FAST_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_FOSC_OEN (BIT(3)) +#define LP_CLKRST_FOSC_OEN_M (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S) +#define LP_CLKRST_FOSC_OEN_V 0x00000001U +#define LP_CLKRST_FOSC_OEN_S 3 +/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1; + * Configures the clock gate to pad of the RC32K_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_OSC32K_OEN (BIT(4)) +#define LP_CLKRST_OSC32K_OEN_M (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S) +#define LP_CLKRST_OSC32K_OEN_V 0x00000001U +#define LP_CLKRST_OSC32K_OEN_S 4 +/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1; + * Configures the clock gate to pad of the XTAL32K_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_XTAL32K_OEN (BIT(5)) +#define LP_CLKRST_XTAL32K_OEN_M (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S) +#define LP_CLKRST_XTAL32K_OEN_V 0x00000001U +#define LP_CLKRST_XTAL32K_OEN_S 5 +/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1; + * Configures the clock gate to pad of the EFUSE_CTRL clock. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_CORE_EFUSE_OEN (BIT(6)) +#define LP_CLKRST_CORE_EFUSE_OEN_M (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S) +#define LP_CLKRST_CORE_EFUSE_OEN_V 0x00000001U +#define LP_CLKRST_CORE_EFUSE_OEN_S 6 +/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1; + * Configures the clock gate to pad of the LP_SLOW_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_SLOW_OEN (BIT(7)) +#define LP_CLKRST_SLOW_OEN_M (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S) +#define LP_CLKRST_SLOW_OEN_V 0x00000001U +#define LP_CLKRST_SLOW_OEN_S 7 +/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1; + * Configures the clock gate to pad of the LP_FAST_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_FAST_OEN (BIT(8)) +#define LP_CLKRST_FAST_OEN_M (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S) +#define LP_CLKRST_FAST_OEN_V 0x00000001U +#define LP_CLKRST_FAST_OEN_S 8 +/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1; + * Configures the clock gate to pad of the RNG clk. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_RNG_OEN (BIT(9)) +#define LP_CLKRST_RNG_OEN_M (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S) +#define LP_CLKRST_RNG_OEN_V 0x00000001U +#define LP_CLKRST_RNG_OEN_S 9 +/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1; + * Configures the clock gate to pad of the LP bus clk. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ +#define LP_CLKRST_LPBUS_OEN (BIT(10)) +#define LP_CLKRST_LPBUS_OEN_M (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S) +#define LP_CLKRST_LPBUS_OEN_V 0x00000001U +#define LP_CLKRST_LPBUS_OEN_S 10 + +/** LP_CLKRST_LP_CLK_EN_REG register + * Configure LP root clk source gate + */ +#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8) +/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0; + * Configures the clock gate to LP_FAST_CLK + * 0: Invalid. The clock gate controlled by hardware fsm + * 1: Force the clk pass clock gate + */ +#define LP_CLKRST_FAST_ORI_GATE (BIT(31)) +#define LP_CLKRST_FAST_ORI_GATE_M (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S) +#define LP_CLKRST_FAST_ORI_GATE_V 0x00000001U +#define LP_CLKRST_FAST_ORI_GATE_S 31 + +/** LP_CLKRST_LP_RST_EN_REG register + * Configures the peri of LP system software reset + */ +#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc) +/** LP_CLKRST_POR_ST_WAIT_FORCE_EN : R/W; bitpos: [27]; default: 0; + * reserved + */ +#define LP_CLKRST_POR_ST_WAIT_FORCE_EN (BIT(27)) +#define LP_CLKRST_POR_ST_WAIT_FORCE_EN_M (LP_CLKRST_POR_ST_WAIT_FORCE_EN_V << LP_CLKRST_POR_ST_WAIT_FORCE_EN_S) +#define LP_CLKRST_POR_ST_WAIT_FORCE_EN_V 0x00000001U +#define LP_CLKRST_POR_ST_WAIT_FORCE_EN_S 27 +/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0; + * Configures whether or not to reset EFUSE_CTRL always-on part + * 0: Invalid.No effect + * 1: Reset + */ +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN (BIT(28)) +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S) +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V 0x00000001U +#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S 28 +/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0; + * Configures whether or not to reset LP_TIMER + * 0: Invalid.No effect + * 1: Reset + */ +#define LP_CLKRST_LP_TIMER_RESET_EN (BIT(29)) +#define LP_CLKRST_LP_TIMER_RESET_EN_M (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S) +#define LP_CLKRST_LP_TIMER_RESET_EN_V 0x00000001U +#define LP_CLKRST_LP_TIMER_RESET_EN_S 29 +/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0; + * Configures whether or not to reset LP_WDT and super watch dog + * 0: Invalid.No effect + * 1: Reset + */ +#define LP_CLKRST_WDT_RESET_EN (BIT(30)) +#define LP_CLKRST_WDT_RESET_EN_M (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S) +#define LP_CLKRST_WDT_RESET_EN_V 0x00000001U +#define LP_CLKRST_WDT_RESET_EN_S 30 +/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0; + * Configures whether or not to reset analog peri, include brownout controller + * 0: Invalid.No effect + * 1: Reset + */ +#define LP_CLKRST_ANA_PERI_RESET_EN (BIT(31)) +#define LP_CLKRST_ANA_PERI_RESET_EN_M (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S) +#define LP_CLKRST_ANA_PERI_RESET_EN_V 0x00000001U +#define LP_CLKRST_ANA_PERI_RESET_EN_S 31 + +/** LP_CLKRST_RESET_CAUSE_REG register + * Represents the reset casue + */ +#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10) +/** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0; + * Represents the reset cause + */ +#define LP_CLKRST_RESET_CAUSE 0x0000001FU +#define LP_CLKRST_RESET_CAUSE_M (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S) +#define LP_CLKRST_RESET_CAUSE_V 0x0000001FU +#define LP_CLKRST_RESET_CAUSE_S 0 +/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1; + * Represents the reset flag + */ +#define LP_CLKRST_CORE0_RESET_FLAG (BIT(5)) +#define LP_CLKRST_CORE0_RESET_FLAG_M (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S) +#define LP_CLKRST_CORE0_RESET_FLAG_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_S 5 +/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0; + * 0: no operation + */ +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR (BIT(29)) +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S) +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S 29 +/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0; + * configure set reset flag + */ +#define LP_CLKRST_CORE0_RESET_FLAG_SET (BIT(30)) +#define LP_CLKRST_CORE0_RESET_FLAG_SET_M (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S) +#define LP_CLKRST_CORE0_RESET_FLAG_SET_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_SET_S 30 +/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0; + * configure clear reset flag + * 0: no operation + * 1: clear flag to 0 + */ +#define LP_CLKRST_CORE0_RESET_FLAG_CLR (BIT(31)) +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S) +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V 0x00000001U +#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S 31 + +/** LP_CLKRST_CPU_RESET_REG register + * Configures CPU reset + */ +#define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14) +/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [21]; default: 1; + * configure the hpcore0 luckup reset enable + * 0: disable + * 1:enable + */ +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN (BIT(21)) +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S) +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V 0x00000001U +#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S 21 +/** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1; + * configures the reset length of LP_WDT reset CPU + * Measurement unit: LP_DYN_FAST_CLK + */ +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH 0x00000007U +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S) +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S 22 +/** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0; + * Configures whether or not LP_WDT can reset CPU + * 0: LP_WDT could not reset CPU when LP_WDT timeout + * 1: LP_WDT could reset CPU when LP_WDT timeout + */ +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN (BIT(25)) +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S) +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V 0x00000001U +#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S 25 +/** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1; + * configure the time between CPU stall and reset + * Measurement unit: LP_DYN_FAST_CLK + */ +#define LP_CLKRST_CPU_STALL_WAIT 0x0000001FU +#define LP_CLKRST_CPU_STALL_WAIT_M (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S) +#define LP_CLKRST_CPU_STALL_WAIT_V 0x0000001FU +#define LP_CLKRST_CPU_STALL_WAIT_S 26 +/** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0; + * Configures whether or not CPU entry stall state before LP_WDT and software reset CPU + * 0: CPU will not entry stall state before LP_WDT and software reset CPU + * 1: CPU will entry stall state before LP_WDT and software reset CPU + */ +#define LP_CLKRST_CPU_STALL_EN (BIT(31)) +#define LP_CLKRST_CPU_STALL_EN_M (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S) +#define LP_CLKRST_CPU_STALL_EN_V 0x00000001U +#define LP_CLKRST_CPU_STALL_EN_S 31 + +/** LP_CLKRST_FOSC_CNTL_REG register + * Configures the RC_FAST_CLK frequency + */ +#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18) +/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 172; + * Configures the RC_FAST_CLK frequency,the clock frequency will increase with this + * field + */ +#define LP_CLKRST_FOSC_DFREQ 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_M (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S) +#define LP_CLKRST_FOSC_DFREQ_V 0x000003FFU +#define LP_CLKRST_FOSC_DFREQ_S 22 + +/** LP_CLKRST_RC32K_CNTL_REG register + * Configures the RC32K_CLK frequency + */ +#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c) +/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 172; + * Configures the RC32K_CLK frequency, the clock frequency will increase with this + * field + */ +#define LP_CLKRST_RC32K_DFREQ 0x000003FFU +#define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S) +#define LP_CLKRST_RC32K_DFREQ_V 0x000003FFU +#define LP_CLKRST_RC32K_DFREQ_S 22 + +/** LP_CLKRST_CLK_TO_HP_REG register + * Configures the clk gate of LP clk to HP system + */ +#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20) +/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1; + * Configures the clk gate of XTAL32K_CLK to HP system + * 0: The clk could not pass to HP system + * 1: The clk could pass to HP system + */ +#define LP_CLKRST_ICG_HP_XTAL32K (BIT(28)) +#define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S) +#define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_XTAL32K_S 28 +/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1; + * Configures the clk gate of RC_SLOW_CLK to HP system + * 0: The clk could not pass to HP system + * 1: The clk could pass to HP system + */ +#define LP_CLKRST_ICG_HP_SOSC (BIT(29)) +#define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S) +#define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_SOSC_S 29 +/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1; + * Configures the clk gate of RC32K_CLK to HP system + * 0: The clk could not pass to HP system + * 1: The clk could pass to HP system + */ +#define LP_CLKRST_ICG_HP_OSC32K (BIT(30)) +#define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S) +#define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U +#define LP_CLKRST_ICG_HP_OSC32K_S 30 +/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1; + * Configures the clk gate of RC_FAST_CLK to HP system + * 0: The clk could not pass to HP system + * 1: The clk could pass to HP system + */ +#define LP_CLKRST_ICG_HP_FOSC (BIT(31)) +#define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S) +#define LP_CLKRST_ICG_HP_FOSC_V 0x00000001U +#define LP_CLKRST_ICG_HP_FOSC_S 31 + +/** LP_CLKRST_LPMEM_FORCE_REG register + * Configures the LP_MEM clk gate force parameter + */ +#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24) +/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0; + * Configures whether ot not force open the clock gate of LP MEM + * 0: Invalid. The clock gate controlled by hardware FSM + * 1: Force open clock gate of LP MEM + */ +#define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31)) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S) +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U +#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31 + +/** LP_CLKRST_XTAL32K_REG register + * Configures the XTAL32K parameter + */ +#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c) +/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3; + * Configures DRES + */ +#define LP_CLKRST_DRES_XTAL32K 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_M (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S) +#define LP_CLKRST_DRES_XTAL32K_V 0x00000007U +#define LP_CLKRST_DRES_XTAL32K_S 22 +/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3; + * Configures DGM + */ +#define LP_CLKRST_DGM_XTAL32K 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_M (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S) +#define LP_CLKRST_DGM_XTAL32K_V 0x00000007U +#define LP_CLKRST_DGM_XTAL32K_S 25 +/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0; + * Configures DBUF + */ +#define LP_CLKRST_DBUF_XTAL32K (BIT(28)) +#define LP_CLKRST_DBUF_XTAL32K_M (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S) +#define LP_CLKRST_DBUF_XTAL32K_V 0x00000001U +#define LP_CLKRST_DBUF_XTAL32K_S 28 +/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3; + * Configures DAC + */ +#define LP_CLKRST_DAC_XTAL32K 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_M (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S) +#define LP_CLKRST_DAC_XTAL32K_V 0x00000007U +#define LP_CLKRST_DAC_XTAL32K_S 29 + +/** LP_CLKRST_DATE_REG register + * Version control register + */ +#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc) +/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 36766288; + * Version control register + */ +#define LP_CLKRST_CLKRST_DATE 0x7FFFFFFFU +#define LP_CLKRST_CLKRST_DATE_M (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S) +#define LP_CLKRST_CLKRST_DATE_V 0x7FFFFFFFU +#define LP_CLKRST_CLKRST_DATE_S 0 +/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0; + * configure register clk bypass clk gate + */ +#define LP_CLKRST_CLK_EN (BIT(31)) +#define LP_CLKRST_CLK_EN_M (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S) +#define LP_CLKRST_CLK_EN_V 0x00000001U +#define LP_CLKRST_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/lp_clkrst_struct.h b/components/soc/esp32c61/include/soc/lp_clkrst_struct.h new file mode 100644 index 0000000000..685b524587 --- /dev/null +++ b/components/soc/esp32c61/include/soc/lp_clkrst_struct.h @@ -0,0 +1,392 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of lp_clk_conf register + * Configures the root clk of LP system + */ +typedef union { + struct { + /** slow_clk_sel : R/W; bitpos: [1:0]; default: 0; + * Configures the source of LP_SLOW_CLK. + * 0: RC_SLOW_CLK + * 1: XTAL32K_CLK + * 2: RC32K_CLK + * 3:OSC_SLOW_CLK + */ + uint32_t slow_clk_sel:2; + /** fast_clk_sel : R/W; bitpos: [3:2]; default: 1; + * configures the source of LP_FAST_CLK. + * 0: RC_FAST_CLK + * 1: XTAL_D2_CLK + * 2: XTAL_CLK + */ + uint32_t fast_clk_sel:2; + /** lp_peri_div_num : R/W; bitpos: [11:4]; default: 0; + * reserved + */ + uint32_t lp_peri_div_num:8; + uint32_t reserved_12:20; + }; + uint32_t val; +} lp_clkrst_lp_clk_conf_reg_t; + +/** Type of lp_clk_po_en register + * Configures the clk gate to pad + */ +typedef union { + struct { + /** aon_slow_oen : R/W; bitpos: [0]; default: 1; + * Configures the clock gate to pad of the LP_DYN_SLOW_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t aon_slow_oen:1; + /** aon_fast_oen : R/W; bitpos: [1]; default: 1; + * Configures the clock gate to pad of the LP_DYN_FAST_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t aon_fast_oen:1; + /** sosc_oen : R/W; bitpos: [2]; default: 1; + * Configures the clock gate to pad of the OSC_SLOW_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t sosc_oen:1; + /** fosc_oen : R/W; bitpos: [3]; default: 1; + * Configures the clock gate to pad of the RC_FAST_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t fosc_oen:1; + /** osc32k_oen : R/W; bitpos: [4]; default: 1; + * Configures the clock gate to pad of the RC32K_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t osc32k_oen:1; + /** xtal32k_oen : R/W; bitpos: [5]; default: 1; + * Configures the clock gate to pad of the XTAL32K_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t xtal32k_oen:1; + /** core_efuse_oen : R/W; bitpos: [6]; default: 1; + * Configures the clock gate to pad of the EFUSE_CTRL clock. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t core_efuse_oen:1; + /** slow_oen : R/W; bitpos: [7]; default: 1; + * Configures the clock gate to pad of the LP_SLOW_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t slow_oen:1; + /** fast_oen : R/W; bitpos: [8]; default: 1; + * Configures the clock gate to pad of the LP_FAST_CLK. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t fast_oen:1; + /** rng_oen : R/W; bitpos: [9]; default: 1; + * Configures the clock gate to pad of the RNG clk. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t rng_oen:1; + /** lpbus_oen : R/W; bitpos: [10]; default: 1; + * Configures the clock gate to pad of the LP bus clk. + * 0: Disable the clk pass clock gate + * 1: Enable the clk pass clock gate + */ + uint32_t lpbus_oen:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_clkrst_lp_clk_po_en_reg_t; + +/** Type of lp_clk_en register + * Configure LP root clk source gate + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** fast_ori_gate : R/W; bitpos: [31]; default: 0; + * Configures the clock gate to LP_FAST_CLK + * 0: Invalid. The clock gate controlled by hardware fsm + * 1: Force the clk pass clock gate + */ + uint32_t fast_ori_gate:1; + }; + uint32_t val; +} lp_clkrst_lp_clk_en_reg_t; + +/** Type of lp_rst_en register + * Configures the peri of LP system software reset + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** por_st_wait_force_en : R/W; bitpos: [27]; default: 0; + * reserved + */ + uint32_t por_st_wait_force_en:1; + /** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0; + * Configures whether or not to reset EFUSE_CTRL always-on part + * 0: Invalid.No effect + * 1: Reset + */ + uint32_t aon_efuse_core_reset_en:1; + /** lp_timer_reset_en : R/W; bitpos: [29]; default: 0; + * Configures whether or not to reset LP_TIMER + * 0: Invalid.No effect + * 1: Reset + */ + uint32_t lp_timer_reset_en:1; + /** wdt_reset_en : R/W; bitpos: [30]; default: 0; + * Configures whether or not to reset LP_WDT and super watch dog + * 0: Invalid.No effect + * 1: Reset + */ + uint32_t wdt_reset_en:1; + /** ana_peri_reset_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not to reset analog peri, include brownout controller + * 0: Invalid.No effect + * 1: Reset + */ + uint32_t ana_peri_reset_en:1; + }; + uint32_t val; +} lp_clkrst_lp_rst_en_reg_t; + +/** Type of reset_cause register + * Represents the reset casue + */ +typedef union { + struct { + /** reset_cause : RO; bitpos: [4:0]; default: 0; + * Represents the reset cause + */ + uint32_t reset_cause:5; + /** core0_reset_flag : RO; bitpos: [5]; default: 1; + * Represents the reset flag + */ + uint32_t core0_reset_flag:1; + uint32_t reserved_6:23; + /** core0_reset_cause_clr : WT; bitpos: [29]; default: 0; + * 0: no operation + */ + uint32_t core0_reset_cause_clr:1; + /** core0_reset_flag_set : WT; bitpos: [30]; default: 0; + * configure set reset flag + */ + uint32_t core0_reset_flag_set:1; + /** core0_reset_flag_clr : WT; bitpos: [31]; default: 0; + * configure clear reset flag + * 0: no operation + * 1: clear flag to 0 + */ + uint32_t core0_reset_flag_clr:1; + }; + uint32_t val; +} lp_clkrst_reset_cause_reg_t; + +/** Type of cpu_reset register + * Configures CPU reset + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hpcore0_lockup_reset_en : R/W; bitpos: [21]; default: 1; + * configure the hpcore0 luckup reset enable + * 0: disable + * 1:enable + */ + uint32_t hpcore0_lockup_reset_en:1; + /** rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1; + * configures the reset length of LP_WDT reset CPU + * Measurement unit: LP_DYN_FAST_CLK + */ + uint32_t rtc_wdt_cpu_reset_length:3; + /** rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0; + * Configures whether or not LP_WDT can reset CPU + * 0: LP_WDT could not reset CPU when LP_WDT timeout + * 1: LP_WDT could reset CPU when LP_WDT timeout + */ + uint32_t rtc_wdt_cpu_reset_en:1; + /** cpu_stall_wait : R/W; bitpos: [30:26]; default: 1; + * configure the time between CPU stall and reset + * Measurement unit: LP_DYN_FAST_CLK + */ + uint32_t cpu_stall_wait:5; + /** cpu_stall_en : R/W; bitpos: [31]; default: 0; + * Configures whether or not CPU entry stall state before LP_WDT and software reset CPU + * 0: CPU will not entry stall state before LP_WDT and software reset CPU + * 1: CPU will entry stall state before LP_WDT and software reset CPU + */ + uint32_t cpu_stall_en:1; + }; + uint32_t val; +} lp_clkrst_cpu_reset_reg_t; + +/** Type of fosc_cntl register + * Configures the RC_FAST_CLK frequency + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** fosc_dfreq : R/W; bitpos: [31:22]; default: 172; + * Configures the RC_FAST_CLK frequency,the clock frequency will increase with this + * field + */ + uint32_t fosc_dfreq:10; + }; + uint32_t val; +} lp_clkrst_fosc_cntl_reg_t; + +/** Type of rc32k_cntl register + * Configures the RC32K_CLK frequency + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** rc32k_dfreq : R/W; bitpos: [31:22]; default: 172; + * Configures the RC32K_CLK frequency, the clock frequency will increase with this + * field + */ + uint32_t rc32k_dfreq:10; + }; + uint32_t val; +} lp_clkrst_rc32k_cntl_reg_t; + +/** Type of clk_to_hp register + * Configures the clk gate of LP clk to HP system + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1; + * Configures the clk gate of XTAL32K_CLK to HP system + * 0: The clk could not pass to HP system + * 1: The clk could pass to HP system + */ + uint32_t icg_hp_xtal32k:1; + /** icg_hp_sosc : R/W; bitpos: [29]; default: 1; + * Configures the clk gate of RC_SLOW_CLK to HP system + * 0: The clk could not pass to HP system + * 1: The clk could pass to HP system + */ + uint32_t icg_hp_sosc:1; + /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1; + * Configures the clk gate of RC32K_CLK to HP system + * 0: The clk could not pass to HP system + * 1: The clk could pass to HP system + */ + uint32_t icg_hp_osc32k:1; + /** icg_hp_fosc : R/W; bitpos: [31]; default: 1; + * Configures the clk gate of RC_FAST_CLK to HP system + * 0: The clk could not pass to HP system + * 1: The clk could pass to HP system + */ + uint32_t icg_hp_fosc:1; + }; + uint32_t val; +} lp_clkrst_clk_to_hp_reg_t; + +/** Type of lpmem_force register + * Configures the LP_MEM clk gate force parameter + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0; + * Configures whether ot not force open the clock gate of LP MEM + * 0: Invalid. The clock gate controlled by hardware FSM + * 1: Force open clock gate of LP MEM + */ + uint32_t lpmem_clk_force_on:1; + }; + uint32_t val; +} lp_clkrst_lpmem_force_reg_t; + +/** Type of xtal32k register + * Configures the XTAL32K parameter + */ +typedef union { + struct { + uint32_t reserved_0:22; + /** dres_xtal32k : R/W; bitpos: [24:22]; default: 3; + * Configures DRES + */ + uint32_t dres_xtal32k:3; + /** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3; + * Configures DGM + */ + uint32_t dgm_xtal32k:3; + /** dbuf_xtal32k : R/W; bitpos: [28]; default: 0; + * Configures DBUF + */ + uint32_t dbuf_xtal32k:1; + /** dac_xtal32k : R/W; bitpos: [31:29]; default: 3; + * Configures DAC + */ + uint32_t dac_xtal32k:3; + }; + uint32_t val; +} lp_clkrst_xtal32k_reg_t; + +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** clkrst_date : R/W; bitpos: [30:0]; default: 36766288; + * Version control register + */ + uint32_t clkrst_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * configure register clk bypass clk gate + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_clkrst_date_reg_t; + + +typedef struct { + volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf; + volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en; + volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en; + volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en; + volatile lp_clkrst_reset_cause_reg_t reset_cause; + volatile lp_clkrst_cpu_reset_reg_t cpu_reset; + volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl; + volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl; + volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp; + volatile lp_clkrst_lpmem_force_reg_t lpmem_force; + uint32_t reserved_028; + volatile lp_clkrst_xtal32k_reg_t xtal32k; + uint32_t reserved_030[243]; + volatile lp_clkrst_date_reg_t date; +} lp_clkrst_dev_t; + +extern lp_clkrst_dev_t LP_CLKRST; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/lp_gpio_reg.h b/components/soc/esp32c61/include/soc/lp_gpio_reg.h new file mode 100644 index 0000000000..e2b1838eaf --- /dev/null +++ b/components/soc/esp32c61/include/soc/lp_gpio_reg.h @@ -0,0 +1,870 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_GPIO_OUT_REG register + * LP_GPIO output register + */ +#define LP_GPIO_OUT_REG (DR_REG_LP_GPIO_BASE + 0x4) +/** LP_GPIO_OUT_DATA_ORIG : R/W/WTC; bitpos: [6:0]; default: 0; + * Configures the output value of LP_GPIO0 ~ 6 output in simple LP_GPIO output mode.\\ + * 0: Low level\\ + * 1: High level\\ + * The value of bit0 ~ bit6 correspond to the output value of LP_GPIO0 ~ LP_GPIO6 + * respectively. Bit7 ~ bit31 are invalid.\\ + */ +#define LP_GPIO_OUT_DATA_ORIG 0x0000007FU +#define LP_GPIO_OUT_DATA_ORIG_M (LP_GPIO_OUT_DATA_ORIG_V << LP_GPIO_OUT_DATA_ORIG_S) +#define LP_GPIO_OUT_DATA_ORIG_V 0x0000007FU +#define LP_GPIO_OUT_DATA_ORIG_S 0 + +/** LP_GPIO_OUT_W1TS_REG register + * LP_GPIO output set register + */ +#define LP_GPIO_OUT_W1TS_REG (DR_REG_LP_GPIO_BASE + 0x8) +/** LP_GPIO_OUT_W1TS : WT; bitpos: [6:0]; default: 0; + * Configures whether or not to set the output register LP_GPIO_OUT_REG of LP_GPIO0 ~ + * LP_GPIO6.\\ + * 0: Not set\\ + * 1: The corresponding bit in LP_GPIO_OUT_REG will be set to 1\\ + * Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. \\ + * Recommended operation: use this register to set LP_GPIO_OUT_REG. \\ + */ +#define LP_GPIO_OUT_W1TS 0x0000007FU +#define LP_GPIO_OUT_W1TS_M (LP_GPIO_OUT_W1TS_V << LP_GPIO_OUT_W1TS_S) +#define LP_GPIO_OUT_W1TS_V 0x0000007FU +#define LP_GPIO_OUT_W1TS_S 0 + +/** LP_GPIO_OUT_W1TC_REG register + * LP_GPIO output clear register + */ +#define LP_GPIO_OUT_W1TC_REG (DR_REG_LP_GPIO_BASE + 0xc) +/** LP_GPIO_OUT_W1TC : WT; bitpos: [6:0]; default: 0; + * Configures whether or not to clear the output register LP_GPIO_OUT_REG of LP_GPIO0 + * ~ LP_GPIO6 output.\\ + * 0: Not clear\\ + * 1: The corresponding bit in LP_GPIO_OUT_REG will be cleared.\\ + * Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. \\ + * Recommended operation: use this register to clear LP_GPIO_OUT_REG. \\ + */ +#define LP_GPIO_OUT_W1TC 0x0000007FU +#define LP_GPIO_OUT_W1TC_M (LP_GPIO_OUT_W1TC_V << LP_GPIO_OUT_W1TC_S) +#define LP_GPIO_OUT_W1TC_V 0x0000007FU +#define LP_GPIO_OUT_W1TC_S 0 + +/** LP_GPIO_ENABLE_REG register + * LP_GPIO output enable register + */ +#define LP_GPIO_ENABLE_REG (DR_REG_LP_GPIO_BASE + 0x10) +/** LP_GPIO_ENABLE_DATA : R/W/WTC; bitpos: [6:0]; default: 0; + * Configures whether or not to enable the output of LP_GPIO0 ~ LP_GPIO6.\\ + * 0: Not enable\\ + * 1: Enable\\ + * Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid.\\ + */ +#define LP_GPIO_ENABLE_DATA 0x0000007FU +#define LP_GPIO_ENABLE_DATA_M (LP_GPIO_ENABLE_DATA_V << LP_GPIO_ENABLE_DATA_S) +#define LP_GPIO_ENABLE_DATA_V 0x0000007FU +#define LP_GPIO_ENABLE_DATA_S 0 + +/** LP_GPIO_ENABLE_W1TS_REG register + * LP_GPIO output enable set register + */ +#define LP_GPIO_ENABLE_W1TS_REG (DR_REG_LP_GPIO_BASE + 0x14) +/** LP_GPIO_ENABLE_W1TS : WT; bitpos: [6:0]; default: 0; + * Configures whether or not to set the output enable register LP_GPIO_ENABLE_REG of + * LP_GPIO0 ~ LP_GPIO6.\\ + * 0: Not set\\ + * 1: The corresponding bit in LP_GPIO_ENABLE_REG will be set to 1\\ + * Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. \\ + * Recommended operation: use this register to set LP_GPIO_ENABLE_REG.\\ + */ +#define LP_GPIO_ENABLE_W1TS 0x0000007FU +#define LP_GPIO_ENABLE_W1TS_M (LP_GPIO_ENABLE_W1TS_V << LP_GPIO_ENABLE_W1TS_S) +#define LP_GPIO_ENABLE_W1TS_V 0x0000007FU +#define LP_GPIO_ENABLE_W1TS_S 0 + +/** LP_GPIO_ENABLE_W1TC_REG register + * LP_GPIO output enable clear register + */ +#define LP_GPIO_ENABLE_W1TC_REG (DR_REG_LP_GPIO_BASE + 0x18) +/** LP_GPIO_ENABLE_W1TC : WT; bitpos: [6:0]; default: 0; + * Configures whether or not to clear the output enable register LP_GPIO_ENABLE_REG of + * LP_GPIO0 ~ LP_GPIO6. \\ + * 0: Not clear\\ + * 1: The corresponding bit in LP_GPIO_ENABLE_REG will be cleared\\ + * Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. \\ + * Recommended operation: use this register to clear LP_GPIO_ENABLE_REG.\\ + */ +#define LP_GPIO_ENABLE_W1TC 0x0000007FU +#define LP_GPIO_ENABLE_W1TC_M (LP_GPIO_ENABLE_W1TC_V << LP_GPIO_ENABLE_W1TC_S) +#define LP_GPIO_ENABLE_W1TC_V 0x0000007FU +#define LP_GPIO_ENABLE_W1TC_S 0 + +/** LP_GPIO_IN_REG register + * LP_GPIO input register + */ +#define LP_GPIO_IN_REG (DR_REG_LP_GPIO_BASE + 0x1c) +/** LP_GPIO_IN_DATA_NEXT : RO; bitpos: [6:0]; default: 0; + * Represents the input value of LP_GPIO0 ~ LP_GPIO6. Each bit represents a pin input + * value:\\ + * 0: Low level\\ + * 1: High level\\ + * Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid.\\ + */ +#define LP_GPIO_IN_DATA_NEXT 0x0000007FU +#define LP_GPIO_IN_DATA_NEXT_M (LP_GPIO_IN_DATA_NEXT_V << LP_GPIO_IN_DATA_NEXT_S) +#define LP_GPIO_IN_DATA_NEXT_V 0x0000007FU +#define LP_GPIO_IN_DATA_NEXT_S 0 + +/** LP_GPIO_STATUS_REG register + * LP_GPIO interrupt status register + */ +#define LP_GPIO_STATUS_REG (DR_REG_LP_GPIO_BASE + 0x20) +/** LP_GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [6:0]; default: 0; + * The interrupt status of LP_GPIO0 ~ LP_GPIO6, can be configured by the software. + * + * - Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. + * - Each bit represents the status of its corresponding LP_GPIO: + * + * - 0: Represents the LP_GPIO does not generate the interrupt configured by + * LP_GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software. + * - 1: Represents the LP_GPIO generates the interrupt configured by + * LP_GPIO_PIN$n_INT_TYPE, or this bit is configured to 1 by the software. + * + */ +#define LP_GPIO_STATUS_INTERRUPT 0x0000007FU +#define LP_GPIO_STATUS_INTERRUPT_M (LP_GPIO_STATUS_INTERRUPT_V << LP_GPIO_STATUS_INTERRUPT_S) +#define LP_GPIO_STATUS_INTERRUPT_V 0x0000007FU +#define LP_GPIO_STATUS_INTERRUPT_S 0 + +/** LP_GPIO_STATUS_W1TS_REG register + * LP_GPIO interrupt status set register + */ +#define LP_GPIO_STATUS_W1TS_REG (DR_REG_LP_GPIO_BASE + 0x24) +/** LP_GPIO_STATUS_W1TS : WT; bitpos: [6:0]; default: 0; + * Configures whether or not to set the interrupt status register + * LP_GPIO_STATUS_INTERRUPT of LP_GPIO0 ~ LP_GPIO6. + * + * - Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. + * - If the value 1 is written to a bit here, the corresponding bit in + * LP_GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this + * register to set LP_GPIO_STATUS_INTERRUPT. + */ +#define LP_GPIO_STATUS_W1TS 0x0000007FU +#define LP_GPIO_STATUS_W1TS_M (LP_GPIO_STATUS_W1TS_V << LP_GPIO_STATUS_W1TS_S) +#define LP_GPIO_STATUS_W1TS_V 0x0000007FU +#define LP_GPIO_STATUS_W1TS_S 0 + +/** LP_GPIO_STATUS_W1TC_REG register + * LP_GPIO interrupt status clear register + */ +#define LP_GPIO_STATUS_W1TC_REG (DR_REG_LP_GPIO_BASE + 0x28) +/** LP_GPIO_STATUS_W1TC : WT; bitpos: [6:0]; default: 0; + * Configures whether or not to clear the interrupt status register + * LP_GPIO_STATUS_INTERRUPT of LP_GPIO0 ~ LP_GPIO6. + * + * - Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. + * - If the value 1 is written to a bit here, the corresponding bit in + * LP_GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this + * register to clear LP_GPIO_STATUS_INTERRUPT. + */ +#define LP_GPIO_STATUS_W1TC 0x0000007FU +#define LP_GPIO_STATUS_W1TC_M (LP_GPIO_STATUS_W1TC_V << LP_GPIO_STATUS_W1TC_S) +#define LP_GPIO_STATUS_W1TC_V 0x0000007FU +#define LP_GPIO_STATUS_W1TC_S 0 + +/** LP_GPIO_STATUS_NEXT_REG register + * LP_GPIO interrupt source register + */ +#define LP_GPIO_STATUS_NEXT_REG (DR_REG_LP_GPIO_BASE + 0x2c) +/** LP_GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [6:0]; default: 0; + * Represents the interrupt source signal of LP_GPIO0 ~ LP_GPIO6.\\ + * Bit0 ~ bit24 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. + * Each bit represents:\\ + * 0: The LP_GPIO does not generate the interrupt configured by + * LP_GPIO_PIN$n_INT_TYPE.\\ + * 1: The LP_GPIO generates an interrupt configured by LP_GPIO_PIN$n_INT_TYPE.\\ + * The interrupt could be rising edge interrupt, falling edge interrupt, level + * sensitive interrupt and any edge interrupt.\\ + */ +#define LP_GPIO_STATUS_INTERRUPT_NEXT 0x0000007FU +#define LP_GPIO_STATUS_INTERRUPT_NEXT_M (LP_GPIO_STATUS_INTERRUPT_NEXT_V << LP_GPIO_STATUS_INTERRUPT_NEXT_S) +#define LP_GPIO_STATUS_INTERRUPT_NEXT_V 0x0000007FU +#define LP_GPIO_STATUS_INTERRUPT_NEXT_S 0 + +/** LP_GPIO_PIN0_REG register + * LP_GPIO0 configuration register + */ +#define LP_GPIO_PIN0_REG (DR_REG_LP_GPIO_BASE + 0x30) +/** LP_GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define LP_GPIO_PIN0_SYNC2_BYPASS 0x00000003U +#define LP_GPIO_PIN0_SYNC2_BYPASS_M (LP_GPIO_PIN0_SYNC2_BYPASS_V << LP_GPIO_PIN0_SYNC2_BYPASS_S) +#define LP_GPIO_PIN0_SYNC2_BYPASS_V 0x00000003U +#define LP_GPIO_PIN0_SYNC2_BYPASS_S 0 +/** LP_GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define LP_GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define LP_GPIO_PIN0_PAD_DRIVER_M (LP_GPIO_PIN0_PAD_DRIVER_V << LP_GPIO_PIN0_PAD_DRIVER_S) +#define LP_GPIO_PIN0_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_PIN0_PAD_DRIVER_S 2 +/** LP_GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define LP_GPIO_PIN0_SYNC1_BYPASS 0x00000003U +#define LP_GPIO_PIN0_SYNC1_BYPASS_M (LP_GPIO_PIN0_SYNC1_BYPASS_V << LP_GPIO_PIN0_SYNC1_BYPASS_S) +#define LP_GPIO_PIN0_SYNC1_BYPASS_V 0x00000003U +#define LP_GPIO_PIN0_SYNC1_BYPASS_S 3 +/** LP_GPIO_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * LP_GPIO wakeup clear register. + */ +#define LP_GPIO_PIN0_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN0_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_PIN0_EDGE_WAKEUP_CLR_S 5 +/** LP_GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures LP_GPIO interrupt type.\\ + * 0: LP_GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define LP_GPIO_PIN0_INT_TYPE 0x00000007U +#define LP_GPIO_PIN0_INT_TYPE_M (LP_GPIO_PIN0_INT_TYPE_V << LP_GPIO_PIN0_INT_TYPE_S) +#define LP_GPIO_PIN0_INT_TYPE_V 0x00000007U +#define LP_GPIO_PIN0_INT_TYPE_S 7 +/** LP_GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable LP_GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define LP_GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define LP_GPIO_PIN0_WAKEUP_ENABLE_M (LP_GPIO_PIN0_WAKEUP_ENABLE_V << LP_GPIO_PIN0_WAKEUP_ENABLE_S) +#define LP_GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_PIN0_WAKEUP_ENABLE_S 10 + +/** LP_GPIO_PIN1_REG register + * LP_GPIO0 configuration register + */ +#define LP_GPIO_PIN1_REG (DR_REG_LP_GPIO_BASE + 0x34) +/** LP_GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define LP_GPIO_PIN1_SYNC2_BYPASS 0x00000003U +#define LP_GPIO_PIN1_SYNC2_BYPASS_M (LP_GPIO_PIN1_SYNC2_BYPASS_V << LP_GPIO_PIN1_SYNC2_BYPASS_S) +#define LP_GPIO_PIN1_SYNC2_BYPASS_V 0x00000003U +#define LP_GPIO_PIN1_SYNC2_BYPASS_S 0 +/** LP_GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define LP_GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define LP_GPIO_PIN1_PAD_DRIVER_M (LP_GPIO_PIN1_PAD_DRIVER_V << LP_GPIO_PIN1_PAD_DRIVER_S) +#define LP_GPIO_PIN1_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_PIN1_PAD_DRIVER_S 2 +/** LP_GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define LP_GPIO_PIN1_SYNC1_BYPASS 0x00000003U +#define LP_GPIO_PIN1_SYNC1_BYPASS_M (LP_GPIO_PIN1_SYNC1_BYPASS_V << LP_GPIO_PIN1_SYNC1_BYPASS_S) +#define LP_GPIO_PIN1_SYNC1_BYPASS_V 0x00000003U +#define LP_GPIO_PIN1_SYNC1_BYPASS_S 3 +/** LP_GPIO_PIN1_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * LP_GPIO wakeup clear register. + */ +#define LP_GPIO_PIN1_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_PIN1_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN1_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN1_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_PIN1_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_PIN1_EDGE_WAKEUP_CLR_S 5 +/** LP_GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures LP_GPIO interrupt type.\\ + * 0: LP_GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define LP_GPIO_PIN1_INT_TYPE 0x00000007U +#define LP_GPIO_PIN1_INT_TYPE_M (LP_GPIO_PIN1_INT_TYPE_V << LP_GPIO_PIN1_INT_TYPE_S) +#define LP_GPIO_PIN1_INT_TYPE_V 0x00000007U +#define LP_GPIO_PIN1_INT_TYPE_S 7 +/** LP_GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable LP_GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define LP_GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define LP_GPIO_PIN1_WAKEUP_ENABLE_M (LP_GPIO_PIN1_WAKEUP_ENABLE_V << LP_GPIO_PIN1_WAKEUP_ENABLE_S) +#define LP_GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_PIN1_WAKEUP_ENABLE_S 10 + +/** LP_GPIO_PIN2_REG register + * LP_GPIO0 configuration register + */ +#define LP_GPIO_PIN2_REG (DR_REG_LP_GPIO_BASE + 0x38) +/** LP_GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define LP_GPIO_PIN2_SYNC2_BYPASS 0x00000003U +#define LP_GPIO_PIN2_SYNC2_BYPASS_M (LP_GPIO_PIN2_SYNC2_BYPASS_V << LP_GPIO_PIN2_SYNC2_BYPASS_S) +#define LP_GPIO_PIN2_SYNC2_BYPASS_V 0x00000003U +#define LP_GPIO_PIN2_SYNC2_BYPASS_S 0 +/** LP_GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define LP_GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define LP_GPIO_PIN2_PAD_DRIVER_M (LP_GPIO_PIN2_PAD_DRIVER_V << LP_GPIO_PIN2_PAD_DRIVER_S) +#define LP_GPIO_PIN2_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_PIN2_PAD_DRIVER_S 2 +/** LP_GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define LP_GPIO_PIN2_SYNC1_BYPASS 0x00000003U +#define LP_GPIO_PIN2_SYNC1_BYPASS_M (LP_GPIO_PIN2_SYNC1_BYPASS_V << LP_GPIO_PIN2_SYNC1_BYPASS_S) +#define LP_GPIO_PIN2_SYNC1_BYPASS_V 0x00000003U +#define LP_GPIO_PIN2_SYNC1_BYPASS_S 3 +/** LP_GPIO_PIN2_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * LP_GPIO wakeup clear register. + */ +#define LP_GPIO_PIN2_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_PIN2_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN2_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN2_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_PIN2_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_PIN2_EDGE_WAKEUP_CLR_S 5 +/** LP_GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures LP_GPIO interrupt type.\\ + * 0: LP_GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define LP_GPIO_PIN2_INT_TYPE 0x00000007U +#define LP_GPIO_PIN2_INT_TYPE_M (LP_GPIO_PIN2_INT_TYPE_V << LP_GPIO_PIN2_INT_TYPE_S) +#define LP_GPIO_PIN2_INT_TYPE_V 0x00000007U +#define LP_GPIO_PIN2_INT_TYPE_S 7 +/** LP_GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable LP_GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define LP_GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define LP_GPIO_PIN2_WAKEUP_ENABLE_M (LP_GPIO_PIN2_WAKEUP_ENABLE_V << LP_GPIO_PIN2_WAKEUP_ENABLE_S) +#define LP_GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_PIN2_WAKEUP_ENABLE_S 10 + +/** LP_GPIO_PIN3_REG register + * LP_GPIO0 configuration register + */ +#define LP_GPIO_PIN3_REG (DR_REG_LP_GPIO_BASE + 0x3c) +/** LP_GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define LP_GPIO_PIN3_SYNC2_BYPASS 0x00000003U +#define LP_GPIO_PIN3_SYNC2_BYPASS_M (LP_GPIO_PIN3_SYNC2_BYPASS_V << LP_GPIO_PIN3_SYNC2_BYPASS_S) +#define LP_GPIO_PIN3_SYNC2_BYPASS_V 0x00000003U +#define LP_GPIO_PIN3_SYNC2_BYPASS_S 0 +/** LP_GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define LP_GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define LP_GPIO_PIN3_PAD_DRIVER_M (LP_GPIO_PIN3_PAD_DRIVER_V << LP_GPIO_PIN3_PAD_DRIVER_S) +#define LP_GPIO_PIN3_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_PIN3_PAD_DRIVER_S 2 +/** LP_GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define LP_GPIO_PIN3_SYNC1_BYPASS 0x00000003U +#define LP_GPIO_PIN3_SYNC1_BYPASS_M (LP_GPIO_PIN3_SYNC1_BYPASS_V << LP_GPIO_PIN3_SYNC1_BYPASS_S) +#define LP_GPIO_PIN3_SYNC1_BYPASS_V 0x00000003U +#define LP_GPIO_PIN3_SYNC1_BYPASS_S 3 +/** LP_GPIO_PIN3_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * LP_GPIO wakeup clear register. + */ +#define LP_GPIO_PIN3_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_PIN3_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN3_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN3_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_PIN3_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_PIN3_EDGE_WAKEUP_CLR_S 5 +/** LP_GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures LP_GPIO interrupt type.\\ + * 0: LP_GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define LP_GPIO_PIN3_INT_TYPE 0x00000007U +#define LP_GPIO_PIN3_INT_TYPE_M (LP_GPIO_PIN3_INT_TYPE_V << LP_GPIO_PIN3_INT_TYPE_S) +#define LP_GPIO_PIN3_INT_TYPE_V 0x00000007U +#define LP_GPIO_PIN3_INT_TYPE_S 7 +/** LP_GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable LP_GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define LP_GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define LP_GPIO_PIN3_WAKEUP_ENABLE_M (LP_GPIO_PIN3_WAKEUP_ENABLE_V << LP_GPIO_PIN3_WAKEUP_ENABLE_S) +#define LP_GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_PIN3_WAKEUP_ENABLE_S 10 + +/** LP_GPIO_PIN4_REG register + * LP_GPIO0 configuration register + */ +#define LP_GPIO_PIN4_REG (DR_REG_LP_GPIO_BASE + 0x40) +/** LP_GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define LP_GPIO_PIN4_SYNC2_BYPASS 0x00000003U +#define LP_GPIO_PIN4_SYNC2_BYPASS_M (LP_GPIO_PIN4_SYNC2_BYPASS_V << LP_GPIO_PIN4_SYNC2_BYPASS_S) +#define LP_GPIO_PIN4_SYNC2_BYPASS_V 0x00000003U +#define LP_GPIO_PIN4_SYNC2_BYPASS_S 0 +/** LP_GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define LP_GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define LP_GPIO_PIN4_PAD_DRIVER_M (LP_GPIO_PIN4_PAD_DRIVER_V << LP_GPIO_PIN4_PAD_DRIVER_S) +#define LP_GPIO_PIN4_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_PIN4_PAD_DRIVER_S 2 +/** LP_GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define LP_GPIO_PIN4_SYNC1_BYPASS 0x00000003U +#define LP_GPIO_PIN4_SYNC1_BYPASS_M (LP_GPIO_PIN4_SYNC1_BYPASS_V << LP_GPIO_PIN4_SYNC1_BYPASS_S) +#define LP_GPIO_PIN4_SYNC1_BYPASS_V 0x00000003U +#define LP_GPIO_PIN4_SYNC1_BYPASS_S 3 +/** LP_GPIO_PIN4_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * LP_GPIO wakeup clear register. + */ +#define LP_GPIO_PIN4_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_PIN4_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN4_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN4_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_PIN4_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_PIN4_EDGE_WAKEUP_CLR_S 5 +/** LP_GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures LP_GPIO interrupt type.\\ + * 0: LP_GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define LP_GPIO_PIN4_INT_TYPE 0x00000007U +#define LP_GPIO_PIN4_INT_TYPE_M (LP_GPIO_PIN4_INT_TYPE_V << LP_GPIO_PIN4_INT_TYPE_S) +#define LP_GPIO_PIN4_INT_TYPE_V 0x00000007U +#define LP_GPIO_PIN4_INT_TYPE_S 7 +/** LP_GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable LP_GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define LP_GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define LP_GPIO_PIN4_WAKEUP_ENABLE_M (LP_GPIO_PIN4_WAKEUP_ENABLE_V << LP_GPIO_PIN4_WAKEUP_ENABLE_S) +#define LP_GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_PIN4_WAKEUP_ENABLE_S 10 + +/** LP_GPIO_PIN5_REG register + * LP_GPIO0 configuration register + */ +#define LP_GPIO_PIN5_REG (DR_REG_LP_GPIO_BASE + 0x44) +/** LP_GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define LP_GPIO_PIN5_SYNC2_BYPASS 0x00000003U +#define LP_GPIO_PIN5_SYNC2_BYPASS_M (LP_GPIO_PIN5_SYNC2_BYPASS_V << LP_GPIO_PIN5_SYNC2_BYPASS_S) +#define LP_GPIO_PIN5_SYNC2_BYPASS_V 0x00000003U +#define LP_GPIO_PIN5_SYNC2_BYPASS_S 0 +/** LP_GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define LP_GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define LP_GPIO_PIN5_PAD_DRIVER_M (LP_GPIO_PIN5_PAD_DRIVER_V << LP_GPIO_PIN5_PAD_DRIVER_S) +#define LP_GPIO_PIN5_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_PIN5_PAD_DRIVER_S 2 +/** LP_GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define LP_GPIO_PIN5_SYNC1_BYPASS 0x00000003U +#define LP_GPIO_PIN5_SYNC1_BYPASS_M (LP_GPIO_PIN5_SYNC1_BYPASS_V << LP_GPIO_PIN5_SYNC1_BYPASS_S) +#define LP_GPIO_PIN5_SYNC1_BYPASS_V 0x00000003U +#define LP_GPIO_PIN5_SYNC1_BYPASS_S 3 +/** LP_GPIO_PIN5_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * LP_GPIO wakeup clear register. + */ +#define LP_GPIO_PIN5_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_PIN5_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN5_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN5_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_PIN5_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_PIN5_EDGE_WAKEUP_CLR_S 5 +/** LP_GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures LP_GPIO interrupt type.\\ + * 0: LP_GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define LP_GPIO_PIN5_INT_TYPE 0x00000007U +#define LP_GPIO_PIN5_INT_TYPE_M (LP_GPIO_PIN5_INT_TYPE_V << LP_GPIO_PIN5_INT_TYPE_S) +#define LP_GPIO_PIN5_INT_TYPE_V 0x00000007U +#define LP_GPIO_PIN5_INT_TYPE_S 7 +/** LP_GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable LP_GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define LP_GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define LP_GPIO_PIN5_WAKEUP_ENABLE_M (LP_GPIO_PIN5_WAKEUP_ENABLE_V << LP_GPIO_PIN5_WAKEUP_ENABLE_S) +#define LP_GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_PIN5_WAKEUP_ENABLE_S 10 + +/** LP_GPIO_PIN6_REG register + * LP_GPIO0 configuration register + */ +#define LP_GPIO_PIN6_REG (DR_REG_LP_GPIO_BASE + 0x48) +/** LP_GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define LP_GPIO_PIN6_SYNC2_BYPASS 0x00000003U +#define LP_GPIO_PIN6_SYNC2_BYPASS_M (LP_GPIO_PIN6_SYNC2_BYPASS_V << LP_GPIO_PIN6_SYNC2_BYPASS_S) +#define LP_GPIO_PIN6_SYNC2_BYPASS_V 0x00000003U +#define LP_GPIO_PIN6_SYNC2_BYPASS_S 0 +/** LP_GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ +#define LP_GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define LP_GPIO_PIN6_PAD_DRIVER_M (LP_GPIO_PIN6_PAD_DRIVER_V << LP_GPIO_PIN6_PAD_DRIVER_S) +#define LP_GPIO_PIN6_PAD_DRIVER_V 0x00000001U +#define LP_GPIO_PIN6_PAD_DRIVER_S 2 +/** LP_GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ +#define LP_GPIO_PIN6_SYNC1_BYPASS 0x00000003U +#define LP_GPIO_PIN6_SYNC1_BYPASS_M (LP_GPIO_PIN6_SYNC1_BYPASS_V << LP_GPIO_PIN6_SYNC1_BYPASS_S) +#define LP_GPIO_PIN6_SYNC1_BYPASS_V 0x00000003U +#define LP_GPIO_PIN6_SYNC1_BYPASS_S 3 +/** LP_GPIO_PIN6_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0; + * LP_GPIO wakeup clear register. + */ +#define LP_GPIO_PIN6_EDGE_WAKEUP_CLR (BIT(5)) +#define LP_GPIO_PIN6_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN6_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN6_EDGE_WAKEUP_CLR_S) +#define LP_GPIO_PIN6_EDGE_WAKEUP_CLR_V 0x00000001U +#define LP_GPIO_PIN6_EDGE_WAKEUP_CLR_S 5 +/** LP_GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Configures LP_GPIO interrupt type.\\ + * 0: LP_GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ +#define LP_GPIO_PIN6_INT_TYPE 0x00000007U +#define LP_GPIO_PIN6_INT_TYPE_M (LP_GPIO_PIN6_INT_TYPE_V << LP_GPIO_PIN6_INT_TYPE_S) +#define LP_GPIO_PIN6_INT_TYPE_V 0x00000007U +#define LP_GPIO_PIN6_INT_TYPE_S 7 +/** LP_GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable LP_GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ +#define LP_GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define LP_GPIO_PIN6_WAKEUP_ENABLE_M (LP_GPIO_PIN6_WAKEUP_ENABLE_V << LP_GPIO_PIN6_WAKEUP_ENABLE_S) +#define LP_GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001U +#define LP_GPIO_PIN6_WAKEUP_ENABLE_S 10 + +/** LP_GPIO_FUNC0_OUT_SEL_CFG_REG register + * Configuration register for LP_GPIO0 output + */ +#define LP_GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2b0) +/** LP_GPIO_FUNC0_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define LP_GPIO_FUNC0_OUT_INV_SEL (BIT(0)) +#define LP_GPIO_FUNC0_OUT_INV_SEL_M (LP_GPIO_FUNC0_OUT_INV_SEL_V << LP_GPIO_FUNC0_OUT_INV_SEL_S) +#define LP_GPIO_FUNC0_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC0_OUT_INV_SEL_S 0 +/** LP_GPIO_FUNC0_OE_INV_SEL : R/W; bitpos: [2]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define LP_GPIO_FUNC0_OE_INV_SEL (BIT(2)) +#define LP_GPIO_FUNC0_OE_INV_SEL_M (LP_GPIO_FUNC0_OE_INV_SEL_V << LP_GPIO_FUNC0_OE_INV_SEL_S) +#define LP_GPIO_FUNC0_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC0_OE_INV_SEL_S 2 + +/** LP_GPIO_FUNC1_OUT_SEL_CFG_REG register + * Configuration register for LP_GPIO1 output + */ +#define LP_GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2b4) +/** LP_GPIO_FUNC1_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define LP_GPIO_FUNC1_OUT_INV_SEL (BIT(0)) +#define LP_GPIO_FUNC1_OUT_INV_SEL_M (LP_GPIO_FUNC1_OUT_INV_SEL_V << LP_GPIO_FUNC1_OUT_INV_SEL_S) +#define LP_GPIO_FUNC1_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC1_OUT_INV_SEL_S 0 +/** LP_GPIO_FUNC1_OE_INV_SEL : R/W; bitpos: [2]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define LP_GPIO_FUNC1_OE_INV_SEL (BIT(2)) +#define LP_GPIO_FUNC1_OE_INV_SEL_M (LP_GPIO_FUNC1_OE_INV_SEL_V << LP_GPIO_FUNC1_OE_INV_SEL_S) +#define LP_GPIO_FUNC1_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC1_OE_INV_SEL_S 2 + +/** LP_GPIO_FUNC2_OUT_SEL_CFG_REG register + * Configuration register for LP_GPIO2 output + */ +#define LP_GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2b8) +/** LP_GPIO_FUNC2_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define LP_GPIO_FUNC2_OUT_INV_SEL (BIT(0)) +#define LP_GPIO_FUNC2_OUT_INV_SEL_M (LP_GPIO_FUNC2_OUT_INV_SEL_V << LP_GPIO_FUNC2_OUT_INV_SEL_S) +#define LP_GPIO_FUNC2_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC2_OUT_INV_SEL_S 0 +/** LP_GPIO_FUNC2_OE_INV_SEL : R/W; bitpos: [2]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define LP_GPIO_FUNC2_OE_INV_SEL (BIT(2)) +#define LP_GPIO_FUNC2_OE_INV_SEL_M (LP_GPIO_FUNC2_OE_INV_SEL_V << LP_GPIO_FUNC2_OE_INV_SEL_S) +#define LP_GPIO_FUNC2_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC2_OE_INV_SEL_S 2 + +/** LP_GPIO_FUNC3_OUT_SEL_CFG_REG register + * Configuration register for LP_GPIO3 output + */ +#define LP_GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2bc) +/** LP_GPIO_FUNC3_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define LP_GPIO_FUNC3_OUT_INV_SEL (BIT(0)) +#define LP_GPIO_FUNC3_OUT_INV_SEL_M (LP_GPIO_FUNC3_OUT_INV_SEL_V << LP_GPIO_FUNC3_OUT_INV_SEL_S) +#define LP_GPIO_FUNC3_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC3_OUT_INV_SEL_S 0 +/** LP_GPIO_FUNC3_OE_INV_SEL : R/W; bitpos: [2]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define LP_GPIO_FUNC3_OE_INV_SEL (BIT(2)) +#define LP_GPIO_FUNC3_OE_INV_SEL_M (LP_GPIO_FUNC3_OE_INV_SEL_V << LP_GPIO_FUNC3_OE_INV_SEL_S) +#define LP_GPIO_FUNC3_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC3_OE_INV_SEL_S 2 + +/** LP_GPIO_FUNC4_OUT_SEL_CFG_REG register + * Configuration register for LP_GPIO4 output + */ +#define LP_GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2c0) +/** LP_GPIO_FUNC4_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define LP_GPIO_FUNC4_OUT_INV_SEL (BIT(0)) +#define LP_GPIO_FUNC4_OUT_INV_SEL_M (LP_GPIO_FUNC4_OUT_INV_SEL_V << LP_GPIO_FUNC4_OUT_INV_SEL_S) +#define LP_GPIO_FUNC4_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC4_OUT_INV_SEL_S 0 +/** LP_GPIO_FUNC4_OE_INV_SEL : R/W; bitpos: [2]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define LP_GPIO_FUNC4_OE_INV_SEL (BIT(2)) +#define LP_GPIO_FUNC4_OE_INV_SEL_M (LP_GPIO_FUNC4_OE_INV_SEL_V << LP_GPIO_FUNC4_OE_INV_SEL_S) +#define LP_GPIO_FUNC4_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC4_OE_INV_SEL_S 2 + +/** LP_GPIO_FUNC5_OUT_SEL_CFG_REG register + * Configuration register for LP_GPIO5 output + */ +#define LP_GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2c4) +/** LP_GPIO_FUNC5_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define LP_GPIO_FUNC5_OUT_INV_SEL (BIT(0)) +#define LP_GPIO_FUNC5_OUT_INV_SEL_M (LP_GPIO_FUNC5_OUT_INV_SEL_V << LP_GPIO_FUNC5_OUT_INV_SEL_S) +#define LP_GPIO_FUNC5_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC5_OUT_INV_SEL_S 0 +/** LP_GPIO_FUNC5_OE_INV_SEL : R/W; bitpos: [2]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define LP_GPIO_FUNC5_OE_INV_SEL (BIT(2)) +#define LP_GPIO_FUNC5_OE_INV_SEL_M (LP_GPIO_FUNC5_OE_INV_SEL_V << LP_GPIO_FUNC5_OE_INV_SEL_S) +#define LP_GPIO_FUNC5_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC5_OE_INV_SEL_S 2 + +/** LP_GPIO_FUNC6_OUT_SEL_CFG_REG register + * Configuration register for LP_GPIO6 output + */ +#define LP_GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_LP_GPIO_BASE + 0x2c8) +/** LP_GPIO_FUNC6_OUT_INV_SEL : R/W; bitpos: [0]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define LP_GPIO_FUNC6_OUT_INV_SEL (BIT(0)) +#define LP_GPIO_FUNC6_OUT_INV_SEL_M (LP_GPIO_FUNC6_OUT_INV_SEL_V << LP_GPIO_FUNC6_OUT_INV_SEL_S) +#define LP_GPIO_FUNC6_OUT_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC6_OUT_INV_SEL_S 0 +/** LP_GPIO_FUNC6_OE_INV_SEL : R/W; bitpos: [2]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ +#define LP_GPIO_FUNC6_OE_INV_SEL (BIT(2)) +#define LP_GPIO_FUNC6_OE_INV_SEL_M (LP_GPIO_FUNC6_OE_INV_SEL_V << LP_GPIO_FUNC6_OE_INV_SEL_S) +#define LP_GPIO_FUNC6_OE_INV_SEL_V 0x00000001U +#define LP_GPIO_FUNC6_OE_INV_SEL_S 2 + +/** LP_GPIO_CLOCK_GATE_REG register + * LP_GPIO clock gate register + */ +#define LP_GPIO_CLOCK_GATE_REG (DR_REG_LP_GPIO_BASE + 0x3f8) +/** LP_GPIO_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether or not to enable clock gate.\\ + * 0: Not enable\\ + * 1: Enable, the clock is free running. \\ + */ +#define LP_GPIO_CLK_EN (BIT(0)) +#define LP_GPIO_CLK_EN_M (LP_GPIO_CLK_EN_V << LP_GPIO_CLK_EN_S) +#define LP_GPIO_CLK_EN_V 0x00000001U +#define LP_GPIO_CLK_EN_S 0 + +/** LP_GPIO_DATE_REG register + * LP_GPIO version register + */ +#define LP_GPIO_DATE_REG (DR_REG_LP_GPIO_BASE + 0x3fc) +/** LP_GPIO_DATE : R/W; bitpos: [27:0]; default: 36766272; + * Version control register. \\ + */ +#define LP_GPIO_DATE 0x0FFFFFFFU +#define LP_GPIO_DATE_M (LP_GPIO_DATE_V << LP_GPIO_DATE_S) +#define LP_GPIO_DATE_V 0x0FFFFFFFU +#define LP_GPIO_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/lp_gpio_struct.h b/components/soc/esp32c61/include/soc/lp_gpio_struct.h new file mode 100644 index 0000000000..fa9badd53d --- /dev/null +++ b/components/soc/esp32c61/include/soc/lp_gpio_struct.h @@ -0,0 +1,376 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of out register + * LP_GPIO output register + */ +typedef union { + struct { + /** out_data_orig : R/W/WTC; bitpos: [6:0]; default: 0; + * Configures the output value of LP_GPIO0 ~ 6 output in simple LP_GPIO output mode.\\ + * 0: Low level\\ + * 1: High level\\ + * The value of bit0 ~ bit6 correspond to the output value of LP_GPIO0 ~ LP_GPIO6 + * respectively. Bit7 ~ bit31 are invalid.\\ + */ + uint32_t out_data_orig:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_gpio_out_reg_t; + +/** Type of out_w1ts register + * LP_GPIO output set register + */ +typedef union { + struct { + /** out_w1ts : WT; bitpos: [6:0]; default: 0; + * Configures whether or not to set the output register LP_GPIO_OUT_REG of LP_GPIO0 ~ + * LP_GPIO6.\\ + * 0: Not set\\ + * 1: The corresponding bit in LP_GPIO_OUT_REG will be set to 1\\ + * Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. \\ + * Recommended operation: use this register to set LP_GPIO_OUT_REG. \\ + */ + uint32_t out_w1ts:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_gpio_out_w1ts_reg_t; + +/** Type of out_w1tc register + * LP_GPIO output clear register + */ +typedef union { + struct { + /** out_w1tc : WT; bitpos: [6:0]; default: 0; + * Configures whether or not to clear the output register LP_GPIO_OUT_REG of LP_GPIO0 + * ~ LP_GPIO6 output.\\ + * 0: Not clear\\ + * 1: The corresponding bit in LP_GPIO_OUT_REG will be cleared.\\ + * Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. \\ + * Recommended operation: use this register to clear LP_GPIO_OUT_REG. \\ + */ + uint32_t out_w1tc:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_gpio_out_w1tc_reg_t; + +/** Type of enable register + * LP_GPIO output enable register + */ +typedef union { + struct { + /** enable_data : R/W/WTC; bitpos: [6:0]; default: 0; + * Configures whether or not to enable the output of LP_GPIO0 ~ LP_GPIO6.\\ + * 0: Not enable\\ + * 1: Enable\\ + * Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid.\\ + */ + uint32_t enable_data:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_gpio_enable_reg_t; + +/** Type of enable_w1ts register + * LP_GPIO output enable set register + */ +typedef union { + struct { + /** enable_w1ts : WT; bitpos: [6:0]; default: 0; + * Configures whether or not to set the output enable register LP_GPIO_ENABLE_REG of + * LP_GPIO0 ~ LP_GPIO6.\\ + * 0: Not set\\ + * 1: The corresponding bit in LP_GPIO_ENABLE_REG will be set to 1\\ + * Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. \\ + * Recommended operation: use this register to set LP_GPIO_ENABLE_REG.\\ + */ + uint32_t enable_w1ts:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_gpio_enable_w1ts_reg_t; + +/** Type of enable_w1tc register + * LP_GPIO output enable clear register + */ +typedef union { + struct { + /** enable_w1tc : WT; bitpos: [6:0]; default: 0; + * Configures whether or not to clear the output enable register LP_GPIO_ENABLE_REG of + * LP_GPIO0 ~ LP_GPIO6. \\ + * 0: Not clear\\ + * 1: The corresponding bit in LP_GPIO_ENABLE_REG will be cleared\\ + * Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. \\ + * Recommended operation: use this register to clear LP_GPIO_ENABLE_REG.\\ + */ + uint32_t enable_w1tc:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_gpio_enable_w1tc_reg_t; + +/** Type of in register + * LP_GPIO input register + */ +typedef union { + struct { + /** in_data_next : RO; bitpos: [6:0]; default: 0; + * Represents the input value of LP_GPIO0 ~ LP_GPIO6. Each bit represents a pin input + * value:\\ + * 0: Low level\\ + * 1: High level\\ + * Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid.\\ + */ + uint32_t in_data_next:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_gpio_in_reg_t; + + +/** Group: Interrupt Status Registers */ +/** Type of status register + * LP_GPIO interrupt status register + */ +typedef union { + struct { + /** status_interrupt : R/W/WTC; bitpos: [6:0]; default: 0; + * The interrupt status of LP_GPIO0 ~ LP_GPIO6, can be configured by the software. + * + * - Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. + * - Each bit represents the status of its corresponding LP_GPIO: + * + * - 0: Represents the LP_GPIO does not generate the interrupt configured by + * LP_GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software. + * - 1: Represents the LP_GPIO generates the interrupt configured by + * LP_GPIO_PIN$n_INT_TYPE, or this bit is configured to 1 by the software. + * + */ + uint32_t status_interrupt:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_gpio_status_reg_t; + +/** Type of status_w1ts register + * LP_GPIO interrupt status set register + */ +typedef union { + struct { + /** status_w1ts : WT; bitpos: [6:0]; default: 0; + * Configures whether or not to set the interrupt status register + * LP_GPIO_STATUS_INTERRUPT of LP_GPIO0 ~ LP_GPIO6. + * + * - Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. + * - If the value 1 is written to a bit here, the corresponding bit in + * LP_GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this + * register to set LP_GPIO_STATUS_INTERRUPT. + */ + uint32_t status_w1ts:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_gpio_status_w1ts_reg_t; + +/** Type of status_w1tc register + * LP_GPIO interrupt status clear register + */ +typedef union { + struct { + /** status_w1tc : WT; bitpos: [6:0]; default: 0; + * Configures whether or not to clear the interrupt status register + * LP_GPIO_STATUS_INTERRUPT of LP_GPIO0 ~ LP_GPIO6. + * + * - Bit0 ~ bit6 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. + * - If the value 1 is written to a bit here, the corresponding bit in + * LP_GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this + * register to clear LP_GPIO_STATUS_INTERRUPT. + */ + uint32_t status_w1tc:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_gpio_status_w1tc_reg_t; + +/** Type of status_next register + * LP_GPIO interrupt source register + */ +typedef union { + struct { + /** status_interrupt_next : RO; bitpos: [6:0]; default: 0; + * Represents the interrupt source signal of LP_GPIO0 ~ LP_GPIO6.\\ + * Bit0 ~ bit24 are corresponding to LP_GPIO0 ~ LP_GPIO6. Bit7 ~ bit31 are invalid. + * Each bit represents:\\ + * 0: The LP_GPIO does not generate the interrupt configured by + * LP_GPIO_PIN$n_INT_TYPE.\\ + * 1: The LP_GPIO generates an interrupt configured by LP_GPIO_PIN$n_INT_TYPE.\\ + * The interrupt could be rising edge interrupt, falling edge interrupt, level + * sensitive interrupt and any edge interrupt.\\ + */ + uint32_t status_interrupt_next:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lp_gpio_status_next_reg_t; + + +/** Group: Pin Configuration Registers */ +/** Type of pinn register + * LP_GPIO0 configuration register + */ +typedef union { + struct { + /** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the second-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ + uint32_t pinn_sync2_bypass:2; + /** pinn_pad_driver : R/W; bitpos: [2]; default: 0; + * Configures to select pin drive mode. \\ + * 0: Normal output\\ + * 1: Open drain output \\ + */ + uint32_t pinn_pad_driver:1; + /** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0; + * Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO + * MUX operating clock for the first-level synchronization.\\ + * 0: Not synchronize\\ + * 1: Synchronize on falling edge\\ + * 2: Synchronize on rising edge\\ + * 3: Synchronize on rising edge\\ + */ + uint32_t pinn_sync1_bypass:2; + /** pinn_edge_wakeup_clr : WT; bitpos: [5]; default: 0; + * LP_GPIO wakeup clear register. + */ + uint32_t pinn_edge_wakeup_clr:1; + uint32_t reserved_6:1; + /** pinn_int_type : R/W; bitpos: [9:7]; default: 0; + * Configures LP_GPIO interrupt type.\\ + * 0: LP_GPIO interrupt disabled\\ + * 1: Rising edge trigger\\ + * 2: Falling edge trigger\\ + * 3: Any edge trigger\\ + * 4: Low level trigger\\ + * 5: High level trigger\\ + */ + uint32_t pinn_int_type:3; + /** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0; + * Configures whether or not to enable LP_GPIO wake-up function.\\ + * 0: Disable\\ + * 1: Enable\\ + * This function only wakes up the CPU from Light-sleep. \\ + */ + uint32_t pinn_wakeup_enable:1; + uint32_t reserved_11:21; + }; + uint32_t val; +} lp_gpio_pinn_reg_t; + + +/** Group: Output Configuration Registers */ +/** Type of funcn_out_sel_cfg register + * Configuration register for LP_GPIOn output + */ +typedef union { + struct { + /** funcn_out_inv_sel : R/W; bitpos: [0]; default: 0; + * Configures whether or not to invert the output value.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t funcn_out_inv_sel:1; + uint32_t reserved_1:1; + /** funcn_oe_inv_sel : R/W; bitpos: [2]; default: 0; + * Configures whether or not to invert the output enable signal.\\ + * 0: Not invert\\ + * 1: Invert\\ + */ + uint32_t funcn_oe_inv_sel:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} lp_gpio_funcn_out_sel_cfg_reg_t; + + +/** Group: Clock Gate Register */ +/** Type of clock_gate register + * LP_GPIO clock gate register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether or not to enable clock gate.\\ + * 0: Not enable\\ + * 1: Enable, the clock is free running. \\ + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_gpio_clock_gate_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * LP_GPIO version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36766272; + * Version control register. \\ + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_gpio_date_reg_t; + + +typedef struct { + uint32_t reserved_000; + volatile lp_gpio_out_reg_t out; + volatile lp_gpio_out_w1ts_reg_t out_w1ts; + volatile lp_gpio_out_w1tc_reg_t out_w1tc; + volatile lp_gpio_enable_reg_t enable; + volatile lp_gpio_enable_w1ts_reg_t enable_w1ts; + volatile lp_gpio_enable_w1tc_reg_t enable_w1tc; + volatile lp_gpio_in_reg_t in; + volatile lp_gpio_status_reg_t status; + volatile lp_gpio_status_w1ts_reg_t status_w1ts; + volatile lp_gpio_status_w1tc_reg_t status_w1tc; + volatile lp_gpio_status_next_reg_t status_next; + volatile lp_gpio_pinn_reg_t pinn[7]; + uint32_t reserved_04c[153]; + volatile lp_gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[7]; + uint32_t reserved_2cc[75]; + volatile lp_gpio_clock_gate_reg_t clock_gate; + volatile lp_gpio_date_reg_t date; +} lp_gpio_dev_t; + +extern lp_gpio_dev_t LP_GPIO; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_gpio_dev_t) == 0x400, "Invalid size of lp_gpio_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/lp_io_mux_reg.h b/components/soc/esp32c61/include/soc/lp_io_mux_reg.h new file mode 100644 index 0000000000..eb2651717a --- /dev/null +++ b/components/soc/esp32c61/include/soc/lp_io_mux_reg.h @@ -0,0 +1,1001 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_IO_MUX_GPIO0_REG register + * LP IO MUX configuration register for LP_GPIO0 + */ +#define LP_IO_MUX_GPIO0_REG (DR_REG_LP_IO_MUX_BASE + 0x0) +/** LP_IO_MUX_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the output of LP_GPIO0 in sleep mode. + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO0_MCU_OE (BIT(0)) +#define LP_IO_MUX_GPIO0_MCU_OE_M (LP_IO_MUX_GPIO0_MCU_OE_V << LP_IO_MUX_GPIO0_MCU_OE_S) +#define LP_IO_MUX_GPIO0_MCU_OE_V 0x00000001U +#define LP_IO_MUX_GPIO0_MCU_OE_S 0 +/** LP_IO_MUX_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enter sleep mode for LP_GPIO0.\\ + * 0: Not enter\\ + * 1: Enter\\ + */ +#define LP_IO_MUX_GPIO0_SLP_SEL (BIT(1)) +#define LP_IO_MUX_GPIO0_SLP_SEL_M (LP_IO_MUX_GPIO0_SLP_SEL_V << LP_IO_MUX_GPIO0_SLP_SEL_S) +#define LP_IO_MUX_GPIO0_SLP_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO0_SLP_SEL_S 1 +/** LP_IO_MUX_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Configure whether or not to enable pull-down resistor of LP_GPIO0 in sleep mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO0_MCU_WPD (BIT(2)) +#define LP_IO_MUX_GPIO0_MCU_WPD_M (LP_IO_MUX_GPIO0_MCU_WPD_V << LP_IO_MUX_GPIO0_MCU_WPD_S) +#define LP_IO_MUX_GPIO0_MCU_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO0_MCU_WPD_S 2 +/** LP_IO_MUX_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable pull-up resistor of LP_GPIO0 during sleep mode. + * \\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO0_MCU_WPU (BIT(3)) +#define LP_IO_MUX_GPIO0_MCU_WPU_M (LP_IO_MUX_GPIO0_MCU_WPU_V << LP_IO_MUX_GPIO0_MCU_WPU_S) +#define LP_IO_MUX_GPIO0_MCU_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO0_MCU_WPU_S 3 +/** LP_IO_MUX_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the input of LP_GPIO0 during sleep mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO0_MCU_IE (BIT(4)) +#define LP_IO_MUX_GPIO0_MCU_IE_M (LP_IO_MUX_GPIO0_MCU_IE_V << LP_IO_MUX_GPIO0_MCU_IE_S) +#define LP_IO_MUX_GPIO0_MCU_IE_V 0x00000001U +#define LP_IO_MUX_GPIO0_MCU_IE_S 4 +/** LP_IO_MUX_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Configures the drive strength of LP_GPIO0 during sleep mode. \\ + * 0: ~5 mA\\ + * 1: ~10 mA\\ + * 2: ~20 mA\\ + * 3: ~40 mA\\ + */ +#define LP_IO_MUX_GPIO0_MCU_DRV 0x00000003U +#define LP_IO_MUX_GPIO0_MCU_DRV_M (LP_IO_MUX_GPIO0_MCU_DRV_V << LP_IO_MUX_GPIO0_MCU_DRV_S) +#define LP_IO_MUX_GPIO0_MCU_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO0_MCU_DRV_S 5 +/** LP_IO_MUX_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable pull-down resistor of LP_GPIO0.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO0_FUN_WPD (BIT(7)) +#define LP_IO_MUX_GPIO0_FUN_WPD_M (LP_IO_MUX_GPIO0_FUN_WPD_V << LP_IO_MUX_GPIO0_FUN_WPD_S) +#define LP_IO_MUX_GPIO0_FUN_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO0_FUN_WPD_S 7 +/** LP_IO_MUX_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Configures whether or not enable pull-up resistor of LP_GPIO0.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO0_FUN_WPU (BIT(8)) +#define LP_IO_MUX_GPIO0_FUN_WPU_M (LP_IO_MUX_GPIO0_FUN_WPU_V << LP_IO_MUX_GPIO0_FUN_WPU_S) +#define LP_IO_MUX_GPIO0_FUN_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO0_FUN_WPU_S 8 +/** LP_IO_MUX_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable input of LP_GPIO0.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO0_FUN_IE (BIT(9)) +#define LP_IO_MUX_GPIO0_FUN_IE_M (LP_IO_MUX_GPIO0_FUN_IE_V << LP_IO_MUX_GPIO0_FUN_IE_S) +#define LP_IO_MUX_GPIO0_FUN_IE_V 0x00000001U +#define LP_IO_MUX_GPIO0_FUN_IE_S 9 +/** LP_IO_MUX_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Configures the drive strength of LP_GPIO0. \\ + * 0: ~5 mA\\ + * 1: ~10 mA\\ + * 2: ~20 mA\\ + * 3: ~40 mA\\ + */ +#define LP_IO_MUX_GPIO0_FUN_DRV 0x00000003U +#define LP_IO_MUX_GPIO0_FUN_DRV_M (LP_IO_MUX_GPIO0_FUN_DRV_V << LP_IO_MUX_GPIO0_FUN_DRV_S) +#define LP_IO_MUX_GPIO0_FUN_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO0_FUN_DRV_S 10 +/** LP_IO_MUX_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Configures to select LP IO MUX function for this signal. \\ + * 0: Select Function 0\\ + * 1: Select Function 1\\ + * ......\\ + */ +#define LP_IO_MUX_GPIO0_MCU_SEL 0x00000007U +#define LP_IO_MUX_GPIO0_MCU_SEL_M (LP_IO_MUX_GPIO0_MCU_SEL_V << LP_IO_MUX_GPIO0_MCU_SEL_S) +#define LP_IO_MUX_GPIO0_MCU_SEL_V 0x00000007U +#define LP_IO_MUX_GPIO0_MCU_SEL_S 12 +/** LP_IO_MUX_GPIO0_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable filter for pin input signals.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO0_FILTER_EN (BIT(15)) +#define LP_IO_MUX_GPIO0_FILTER_EN_M (LP_IO_MUX_GPIO0_FILTER_EN_V << LP_IO_MUX_GPIO0_FILTER_EN_S) +#define LP_IO_MUX_GPIO0_FILTER_EN_V 0x00000001U +#define LP_IO_MUX_GPIO0_FILTER_EN_S 15 +/** LP_IO_MUX_GPIO0_HYS_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the hysteresis function of the pin when + * LP_IO_MUX_GPIO0_HYS_SEL is set to 1.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO0_HYS_EN (BIT(16)) +#define LP_IO_MUX_GPIO0_HYS_EN_M (LP_IO_MUX_GPIO0_HYS_EN_V << LP_IO_MUX_GPIO0_HYS_EN_S) +#define LP_IO_MUX_GPIO0_HYS_EN_V 0x00000001U +#define LP_IO_MUX_GPIO0_HYS_EN_S 16 +/** LP_IO_MUX_GPIO0_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Configures to choose the signal for enabling the hysteresis function for LP_GPIO0. + * \\ + * 0: Choose the output enable signal of eFuse\\ + * 1: Choose the output enable signal of LP_IO_MUX_GPIO0_HYS_EN\\ + */ +#define LP_IO_MUX_GPIO0_HYS_SEL (BIT(17)) +#define LP_IO_MUX_GPIO0_HYS_SEL_M (LP_IO_MUX_GPIO0_HYS_SEL_V << LP_IO_MUX_GPIO0_HYS_SEL_S) +#define LP_IO_MUX_GPIO0_HYS_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO0_HYS_SEL_S 17 + +/** LP_IO_MUX_GPIO1_REG register + * LP IO MUX configuration register for LP_GPIO1 + */ +#define LP_IO_MUX_GPIO1_REG (DR_REG_LP_IO_MUX_BASE + 0x4) +/** LP_IO_MUX_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the output of LP_GPIO1 in sleep mode. + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO1_MCU_OE (BIT(0)) +#define LP_IO_MUX_GPIO1_MCU_OE_M (LP_IO_MUX_GPIO1_MCU_OE_V << LP_IO_MUX_GPIO1_MCU_OE_S) +#define LP_IO_MUX_GPIO1_MCU_OE_V 0x00000001U +#define LP_IO_MUX_GPIO1_MCU_OE_S 0 +/** LP_IO_MUX_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enter sleep mode for LP_GPIO1.\\ + * 0: Not enter\\ + * 1: Enter\\ + */ +#define LP_IO_MUX_GPIO1_SLP_SEL (BIT(1)) +#define LP_IO_MUX_GPIO1_SLP_SEL_M (LP_IO_MUX_GPIO1_SLP_SEL_V << LP_IO_MUX_GPIO1_SLP_SEL_S) +#define LP_IO_MUX_GPIO1_SLP_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO1_SLP_SEL_S 1 +/** LP_IO_MUX_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Configure whether or not to enable pull-down resistor of LP_GPIO1 in sleep mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO1_MCU_WPD (BIT(2)) +#define LP_IO_MUX_GPIO1_MCU_WPD_M (LP_IO_MUX_GPIO1_MCU_WPD_V << LP_IO_MUX_GPIO1_MCU_WPD_S) +#define LP_IO_MUX_GPIO1_MCU_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO1_MCU_WPD_S 2 +/** LP_IO_MUX_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable pull-up resistor of LP_GPIO1 during sleep mode. + * \\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO1_MCU_WPU (BIT(3)) +#define LP_IO_MUX_GPIO1_MCU_WPU_M (LP_IO_MUX_GPIO1_MCU_WPU_V << LP_IO_MUX_GPIO1_MCU_WPU_S) +#define LP_IO_MUX_GPIO1_MCU_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO1_MCU_WPU_S 3 +/** LP_IO_MUX_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the input of LP_GPIO1 during sleep mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO1_MCU_IE (BIT(4)) +#define LP_IO_MUX_GPIO1_MCU_IE_M (LP_IO_MUX_GPIO1_MCU_IE_V << LP_IO_MUX_GPIO1_MCU_IE_S) +#define LP_IO_MUX_GPIO1_MCU_IE_V 0x00000001U +#define LP_IO_MUX_GPIO1_MCU_IE_S 4 +/** LP_IO_MUX_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Configures the drive strength of LP_GPIO1 during sleep mode. \\ + * 0: ~5 mA\\ + * 1: ~10 mA\\ + * 2: ~20 mA\\ + * 3: ~40 mA\\ + */ +#define LP_IO_MUX_GPIO1_MCU_DRV 0x00000003U +#define LP_IO_MUX_GPIO1_MCU_DRV_M (LP_IO_MUX_GPIO1_MCU_DRV_V << LP_IO_MUX_GPIO1_MCU_DRV_S) +#define LP_IO_MUX_GPIO1_MCU_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO1_MCU_DRV_S 5 +/** LP_IO_MUX_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable pull-down resistor of LP_GPIO1.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO1_FUN_WPD (BIT(7)) +#define LP_IO_MUX_GPIO1_FUN_WPD_M (LP_IO_MUX_GPIO1_FUN_WPD_V << LP_IO_MUX_GPIO1_FUN_WPD_S) +#define LP_IO_MUX_GPIO1_FUN_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO1_FUN_WPD_S 7 +/** LP_IO_MUX_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Configures whether or not enable pull-up resistor of LP_GPIO1.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO1_FUN_WPU (BIT(8)) +#define LP_IO_MUX_GPIO1_FUN_WPU_M (LP_IO_MUX_GPIO1_FUN_WPU_V << LP_IO_MUX_GPIO1_FUN_WPU_S) +#define LP_IO_MUX_GPIO1_FUN_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO1_FUN_WPU_S 8 +/** LP_IO_MUX_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable input of LP_GPIO1.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO1_FUN_IE (BIT(9)) +#define LP_IO_MUX_GPIO1_FUN_IE_M (LP_IO_MUX_GPIO1_FUN_IE_V << LP_IO_MUX_GPIO1_FUN_IE_S) +#define LP_IO_MUX_GPIO1_FUN_IE_V 0x00000001U +#define LP_IO_MUX_GPIO1_FUN_IE_S 9 +/** LP_IO_MUX_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Configures the drive strength of LP_GPIO1. \\ + * 0: ~5 mA\\ + * 1: ~10 mA\\ + * 2: ~20 mA\\ + * 3: ~40 mA\\ + */ +#define LP_IO_MUX_GPIO1_FUN_DRV 0x00000003U +#define LP_IO_MUX_GPIO1_FUN_DRV_M (LP_IO_MUX_GPIO1_FUN_DRV_V << LP_IO_MUX_GPIO1_FUN_DRV_S) +#define LP_IO_MUX_GPIO1_FUN_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO1_FUN_DRV_S 10 +/** LP_IO_MUX_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Configures to select LP IO MUX function for this signal. \\ + * 0: Select Function 0\\ + * 1: Select Function 1\\ + * ......\\ + */ +#define LP_IO_MUX_GPIO1_MCU_SEL 0x00000007U +#define LP_IO_MUX_GPIO1_MCU_SEL_M (LP_IO_MUX_GPIO1_MCU_SEL_V << LP_IO_MUX_GPIO1_MCU_SEL_S) +#define LP_IO_MUX_GPIO1_MCU_SEL_V 0x00000007U +#define LP_IO_MUX_GPIO1_MCU_SEL_S 12 +/** LP_IO_MUX_GPIO1_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable filter for pin input signals.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO1_FILTER_EN (BIT(15)) +#define LP_IO_MUX_GPIO1_FILTER_EN_M (LP_IO_MUX_GPIO1_FILTER_EN_V << LP_IO_MUX_GPIO1_FILTER_EN_S) +#define LP_IO_MUX_GPIO1_FILTER_EN_V 0x00000001U +#define LP_IO_MUX_GPIO1_FILTER_EN_S 15 +/** LP_IO_MUX_GPIO1_HYS_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the hysteresis function of the pin when + * LP_IO_MUX_GPIO1_HYS_SEL is set to 1.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO1_HYS_EN (BIT(16)) +#define LP_IO_MUX_GPIO1_HYS_EN_M (LP_IO_MUX_GPIO1_HYS_EN_V << LP_IO_MUX_GPIO1_HYS_EN_S) +#define LP_IO_MUX_GPIO1_HYS_EN_V 0x00000001U +#define LP_IO_MUX_GPIO1_HYS_EN_S 16 +/** LP_IO_MUX_GPIO1_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Configures to choose the signal for enabling the hysteresis function for LP_GPIO1. + * \\ + * 0: Choose the output enable signal of eFuse\\ + * 1: Choose the output enable signal of LP_IO_MUX_GPIO1_HYS_EN\\ + */ +#define LP_IO_MUX_GPIO1_HYS_SEL (BIT(17)) +#define LP_IO_MUX_GPIO1_HYS_SEL_M (LP_IO_MUX_GPIO1_HYS_SEL_V << LP_IO_MUX_GPIO1_HYS_SEL_S) +#define LP_IO_MUX_GPIO1_HYS_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO1_HYS_SEL_S 17 + +/** LP_IO_MUX_GPIO2_REG register + * LP IO MUX configuration register for LP_GPIO2 + */ +#define LP_IO_MUX_GPIO2_REG (DR_REG_LP_IO_MUX_BASE + 0x8) +/** LP_IO_MUX_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the output of LP_GPIO2 in sleep mode. + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO2_MCU_OE (BIT(0)) +#define LP_IO_MUX_GPIO2_MCU_OE_M (LP_IO_MUX_GPIO2_MCU_OE_V << LP_IO_MUX_GPIO2_MCU_OE_S) +#define LP_IO_MUX_GPIO2_MCU_OE_V 0x00000001U +#define LP_IO_MUX_GPIO2_MCU_OE_S 0 +/** LP_IO_MUX_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enter sleep mode for LP_GPIO2.\\ + * 0: Not enter\\ + * 1: Enter\\ + */ +#define LP_IO_MUX_GPIO2_SLP_SEL (BIT(1)) +#define LP_IO_MUX_GPIO2_SLP_SEL_M (LP_IO_MUX_GPIO2_SLP_SEL_V << LP_IO_MUX_GPIO2_SLP_SEL_S) +#define LP_IO_MUX_GPIO2_SLP_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO2_SLP_SEL_S 1 +/** LP_IO_MUX_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Configure whether or not to enable pull-down resistor of LP_GPIO2 in sleep mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO2_MCU_WPD (BIT(2)) +#define LP_IO_MUX_GPIO2_MCU_WPD_M (LP_IO_MUX_GPIO2_MCU_WPD_V << LP_IO_MUX_GPIO2_MCU_WPD_S) +#define LP_IO_MUX_GPIO2_MCU_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO2_MCU_WPD_S 2 +/** LP_IO_MUX_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable pull-up resistor of LP_GPIO2 during sleep mode. + * \\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO2_MCU_WPU (BIT(3)) +#define LP_IO_MUX_GPIO2_MCU_WPU_M (LP_IO_MUX_GPIO2_MCU_WPU_V << LP_IO_MUX_GPIO2_MCU_WPU_S) +#define LP_IO_MUX_GPIO2_MCU_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO2_MCU_WPU_S 3 +/** LP_IO_MUX_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the input of LP_GPIO2 during sleep mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO2_MCU_IE (BIT(4)) +#define LP_IO_MUX_GPIO2_MCU_IE_M (LP_IO_MUX_GPIO2_MCU_IE_V << LP_IO_MUX_GPIO2_MCU_IE_S) +#define LP_IO_MUX_GPIO2_MCU_IE_V 0x00000001U +#define LP_IO_MUX_GPIO2_MCU_IE_S 4 +/** LP_IO_MUX_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Configures the drive strength of LP_GPIO2 during sleep mode. \\ + * 0: ~5 mA\\ + * 1: ~10 mA\\ + * 2: ~20 mA\\ + * 3: ~40 mA\\ + */ +#define LP_IO_MUX_GPIO2_MCU_DRV 0x00000003U +#define LP_IO_MUX_GPIO2_MCU_DRV_M (LP_IO_MUX_GPIO2_MCU_DRV_V << LP_IO_MUX_GPIO2_MCU_DRV_S) +#define LP_IO_MUX_GPIO2_MCU_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO2_MCU_DRV_S 5 +/** LP_IO_MUX_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable pull-down resistor of LP_GPIO2.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO2_FUN_WPD (BIT(7)) +#define LP_IO_MUX_GPIO2_FUN_WPD_M (LP_IO_MUX_GPIO2_FUN_WPD_V << LP_IO_MUX_GPIO2_FUN_WPD_S) +#define LP_IO_MUX_GPIO2_FUN_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO2_FUN_WPD_S 7 +/** LP_IO_MUX_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Configures whether or not enable pull-up resistor of LP_GPIO2.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO2_FUN_WPU (BIT(8)) +#define LP_IO_MUX_GPIO2_FUN_WPU_M (LP_IO_MUX_GPIO2_FUN_WPU_V << LP_IO_MUX_GPIO2_FUN_WPU_S) +#define LP_IO_MUX_GPIO2_FUN_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO2_FUN_WPU_S 8 +/** LP_IO_MUX_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable input of LP_GPIO2.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO2_FUN_IE (BIT(9)) +#define LP_IO_MUX_GPIO2_FUN_IE_M (LP_IO_MUX_GPIO2_FUN_IE_V << LP_IO_MUX_GPIO2_FUN_IE_S) +#define LP_IO_MUX_GPIO2_FUN_IE_V 0x00000001U +#define LP_IO_MUX_GPIO2_FUN_IE_S 9 +/** LP_IO_MUX_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Configures the drive strength of LP_GPIO2. \\ + * 0: ~5 mA\\ + * 1: ~10 mA\\ + * 2: ~20 mA\\ + * 3: ~40 mA\\ + */ +#define LP_IO_MUX_GPIO2_FUN_DRV 0x00000003U +#define LP_IO_MUX_GPIO2_FUN_DRV_M (LP_IO_MUX_GPIO2_FUN_DRV_V << LP_IO_MUX_GPIO2_FUN_DRV_S) +#define LP_IO_MUX_GPIO2_FUN_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO2_FUN_DRV_S 10 +/** LP_IO_MUX_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Configures to select LP IO MUX function for this signal. \\ + * 0: Select Function 0\\ + * 1: Select Function 1\\ + * ......\\ + */ +#define LP_IO_MUX_GPIO2_MCU_SEL 0x00000007U +#define LP_IO_MUX_GPIO2_MCU_SEL_M (LP_IO_MUX_GPIO2_MCU_SEL_V << LP_IO_MUX_GPIO2_MCU_SEL_S) +#define LP_IO_MUX_GPIO2_MCU_SEL_V 0x00000007U +#define LP_IO_MUX_GPIO2_MCU_SEL_S 12 +/** LP_IO_MUX_GPIO2_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable filter for pin input signals.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO2_FILTER_EN (BIT(15)) +#define LP_IO_MUX_GPIO2_FILTER_EN_M (LP_IO_MUX_GPIO2_FILTER_EN_V << LP_IO_MUX_GPIO2_FILTER_EN_S) +#define LP_IO_MUX_GPIO2_FILTER_EN_V 0x00000001U +#define LP_IO_MUX_GPIO2_FILTER_EN_S 15 +/** LP_IO_MUX_GPIO2_HYS_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the hysteresis function of the pin when + * LP_IO_MUX_GPIO2_HYS_SEL is set to 1.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO2_HYS_EN (BIT(16)) +#define LP_IO_MUX_GPIO2_HYS_EN_M (LP_IO_MUX_GPIO2_HYS_EN_V << LP_IO_MUX_GPIO2_HYS_EN_S) +#define LP_IO_MUX_GPIO2_HYS_EN_V 0x00000001U +#define LP_IO_MUX_GPIO2_HYS_EN_S 16 +/** LP_IO_MUX_GPIO2_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Configures to choose the signal for enabling the hysteresis function for LP_GPIO2. + * \\ + * 0: Choose the output enable signal of eFuse\\ + * 1: Choose the output enable signal of LP_IO_MUX_GPIO2_HYS_EN\\ + */ +#define LP_IO_MUX_GPIO2_HYS_SEL (BIT(17)) +#define LP_IO_MUX_GPIO2_HYS_SEL_M (LP_IO_MUX_GPIO2_HYS_SEL_V << LP_IO_MUX_GPIO2_HYS_SEL_S) +#define LP_IO_MUX_GPIO2_HYS_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO2_HYS_SEL_S 17 + +/** LP_IO_MUX_GPIO3_REG register + * LP IO MUX configuration register for LP_GPIO3 + */ +#define LP_IO_MUX_GPIO3_REG (DR_REG_LP_IO_MUX_BASE + 0xc) +/** LP_IO_MUX_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the output of LP_GPIO3 in sleep mode. + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO3_MCU_OE (BIT(0)) +#define LP_IO_MUX_GPIO3_MCU_OE_M (LP_IO_MUX_GPIO3_MCU_OE_V << LP_IO_MUX_GPIO3_MCU_OE_S) +#define LP_IO_MUX_GPIO3_MCU_OE_V 0x00000001U +#define LP_IO_MUX_GPIO3_MCU_OE_S 0 +/** LP_IO_MUX_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enter sleep mode for LP_GPIO3.\\ + * 0: Not enter\\ + * 1: Enter\\ + */ +#define LP_IO_MUX_GPIO3_SLP_SEL (BIT(1)) +#define LP_IO_MUX_GPIO3_SLP_SEL_M (LP_IO_MUX_GPIO3_SLP_SEL_V << LP_IO_MUX_GPIO3_SLP_SEL_S) +#define LP_IO_MUX_GPIO3_SLP_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO3_SLP_SEL_S 1 +/** LP_IO_MUX_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Configure whether or not to enable pull-down resistor of LP_GPIO3 in sleep mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO3_MCU_WPD (BIT(2)) +#define LP_IO_MUX_GPIO3_MCU_WPD_M (LP_IO_MUX_GPIO3_MCU_WPD_V << LP_IO_MUX_GPIO3_MCU_WPD_S) +#define LP_IO_MUX_GPIO3_MCU_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO3_MCU_WPD_S 2 +/** LP_IO_MUX_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable pull-up resistor of LP_GPIO3 during sleep mode. + * \\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO3_MCU_WPU (BIT(3)) +#define LP_IO_MUX_GPIO3_MCU_WPU_M (LP_IO_MUX_GPIO3_MCU_WPU_V << LP_IO_MUX_GPIO3_MCU_WPU_S) +#define LP_IO_MUX_GPIO3_MCU_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO3_MCU_WPU_S 3 +/** LP_IO_MUX_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the input of LP_GPIO3 during sleep mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO3_MCU_IE (BIT(4)) +#define LP_IO_MUX_GPIO3_MCU_IE_M (LP_IO_MUX_GPIO3_MCU_IE_V << LP_IO_MUX_GPIO3_MCU_IE_S) +#define LP_IO_MUX_GPIO3_MCU_IE_V 0x00000001U +#define LP_IO_MUX_GPIO3_MCU_IE_S 4 +/** LP_IO_MUX_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Configures the drive strength of LP_GPIO3 during sleep mode. \\ + * 0: ~5 mA\\ + * 1: ~10 mA\\ + * 2: ~20 mA\\ + * 3: ~40 mA\\ + */ +#define LP_IO_MUX_GPIO3_MCU_DRV 0x00000003U +#define LP_IO_MUX_GPIO3_MCU_DRV_M (LP_IO_MUX_GPIO3_MCU_DRV_V << LP_IO_MUX_GPIO3_MCU_DRV_S) +#define LP_IO_MUX_GPIO3_MCU_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO3_MCU_DRV_S 5 +/** LP_IO_MUX_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable pull-down resistor of LP_GPIO3.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO3_FUN_WPD (BIT(7)) +#define LP_IO_MUX_GPIO3_FUN_WPD_M (LP_IO_MUX_GPIO3_FUN_WPD_V << LP_IO_MUX_GPIO3_FUN_WPD_S) +#define LP_IO_MUX_GPIO3_FUN_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO3_FUN_WPD_S 7 +/** LP_IO_MUX_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Configures whether or not enable pull-up resistor of LP_GPIO3.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO3_FUN_WPU (BIT(8)) +#define LP_IO_MUX_GPIO3_FUN_WPU_M (LP_IO_MUX_GPIO3_FUN_WPU_V << LP_IO_MUX_GPIO3_FUN_WPU_S) +#define LP_IO_MUX_GPIO3_FUN_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO3_FUN_WPU_S 8 +/** LP_IO_MUX_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable input of LP_GPIO3.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO3_FUN_IE (BIT(9)) +#define LP_IO_MUX_GPIO3_FUN_IE_M (LP_IO_MUX_GPIO3_FUN_IE_V << LP_IO_MUX_GPIO3_FUN_IE_S) +#define LP_IO_MUX_GPIO3_FUN_IE_V 0x00000001U +#define LP_IO_MUX_GPIO3_FUN_IE_S 9 +/** LP_IO_MUX_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Configures the drive strength of LP_GPIO3. \\ + * 0: ~5 mA\\ + * 1: ~10 mA\\ + * 2: ~20 mA\\ + * 3: ~40 mA\\ + */ +#define LP_IO_MUX_GPIO3_FUN_DRV 0x00000003U +#define LP_IO_MUX_GPIO3_FUN_DRV_M (LP_IO_MUX_GPIO3_FUN_DRV_V << LP_IO_MUX_GPIO3_FUN_DRV_S) +#define LP_IO_MUX_GPIO3_FUN_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO3_FUN_DRV_S 10 +/** LP_IO_MUX_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Configures to select LP IO MUX function for this signal. \\ + * 0: Select Function 0\\ + * 1: Select Function 1\\ + * ......\\ + */ +#define LP_IO_MUX_GPIO3_MCU_SEL 0x00000007U +#define LP_IO_MUX_GPIO3_MCU_SEL_M (LP_IO_MUX_GPIO3_MCU_SEL_V << LP_IO_MUX_GPIO3_MCU_SEL_S) +#define LP_IO_MUX_GPIO3_MCU_SEL_V 0x00000007U +#define LP_IO_MUX_GPIO3_MCU_SEL_S 12 +/** LP_IO_MUX_GPIO3_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable filter for pin input signals.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO3_FILTER_EN (BIT(15)) +#define LP_IO_MUX_GPIO3_FILTER_EN_M (LP_IO_MUX_GPIO3_FILTER_EN_V << LP_IO_MUX_GPIO3_FILTER_EN_S) +#define LP_IO_MUX_GPIO3_FILTER_EN_V 0x00000001U +#define LP_IO_MUX_GPIO3_FILTER_EN_S 15 +/** LP_IO_MUX_GPIO3_HYS_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the hysteresis function of the pin when + * LP_IO_MUX_GPIO3_HYS_SEL is set to 1.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO3_HYS_EN (BIT(16)) +#define LP_IO_MUX_GPIO3_HYS_EN_M (LP_IO_MUX_GPIO3_HYS_EN_V << LP_IO_MUX_GPIO3_HYS_EN_S) +#define LP_IO_MUX_GPIO3_HYS_EN_V 0x00000001U +#define LP_IO_MUX_GPIO3_HYS_EN_S 16 +/** LP_IO_MUX_GPIO3_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Configures to choose the signal for enabling the hysteresis function for LP_GPIO3. + * \\ + * 0: Choose the output enable signal of eFuse\\ + * 1: Choose the output enable signal of LP_IO_MUX_GPIO3_HYS_EN\\ + */ +#define LP_IO_MUX_GPIO3_HYS_SEL (BIT(17)) +#define LP_IO_MUX_GPIO3_HYS_SEL_M (LP_IO_MUX_GPIO3_HYS_SEL_V << LP_IO_MUX_GPIO3_HYS_SEL_S) +#define LP_IO_MUX_GPIO3_HYS_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO3_HYS_SEL_S 17 + +/** LP_IO_MUX_GPIO4_REG register + * LP IO MUX configuration register for LP_GPIO4 + */ +#define LP_IO_MUX_GPIO4_REG (DR_REG_LP_IO_MUX_BASE + 0x10) +/** LP_IO_MUX_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the output of LP_GPIO4 in sleep mode. + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO4_MCU_OE (BIT(0)) +#define LP_IO_MUX_GPIO4_MCU_OE_M (LP_IO_MUX_GPIO4_MCU_OE_V << LP_IO_MUX_GPIO4_MCU_OE_S) +#define LP_IO_MUX_GPIO4_MCU_OE_V 0x00000001U +#define LP_IO_MUX_GPIO4_MCU_OE_S 0 +/** LP_IO_MUX_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enter sleep mode for LP_GPIO4.\\ + * 0: Not enter\\ + * 1: Enter\\ + */ +#define LP_IO_MUX_GPIO4_SLP_SEL (BIT(1)) +#define LP_IO_MUX_GPIO4_SLP_SEL_M (LP_IO_MUX_GPIO4_SLP_SEL_V << LP_IO_MUX_GPIO4_SLP_SEL_S) +#define LP_IO_MUX_GPIO4_SLP_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO4_SLP_SEL_S 1 +/** LP_IO_MUX_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Configure whether or not to enable pull-down resistor of LP_GPIO4 in sleep mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO4_MCU_WPD (BIT(2)) +#define LP_IO_MUX_GPIO4_MCU_WPD_M (LP_IO_MUX_GPIO4_MCU_WPD_V << LP_IO_MUX_GPIO4_MCU_WPD_S) +#define LP_IO_MUX_GPIO4_MCU_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO4_MCU_WPD_S 2 +/** LP_IO_MUX_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable pull-up resistor of LP_GPIO4 during sleep mode. + * \\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO4_MCU_WPU (BIT(3)) +#define LP_IO_MUX_GPIO4_MCU_WPU_M (LP_IO_MUX_GPIO4_MCU_WPU_V << LP_IO_MUX_GPIO4_MCU_WPU_S) +#define LP_IO_MUX_GPIO4_MCU_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO4_MCU_WPU_S 3 +/** LP_IO_MUX_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the input of LP_GPIO4 during sleep mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO4_MCU_IE (BIT(4)) +#define LP_IO_MUX_GPIO4_MCU_IE_M (LP_IO_MUX_GPIO4_MCU_IE_V << LP_IO_MUX_GPIO4_MCU_IE_S) +#define LP_IO_MUX_GPIO4_MCU_IE_V 0x00000001U +#define LP_IO_MUX_GPIO4_MCU_IE_S 4 +/** LP_IO_MUX_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Configures the drive strength of LP_GPIO4 during sleep mode. \\ + * 0: ~5 mA\\ + * 1: ~10 mA\\ + * 2: ~20 mA\\ + * 3: ~40 mA\\ + */ +#define LP_IO_MUX_GPIO4_MCU_DRV 0x00000003U +#define LP_IO_MUX_GPIO4_MCU_DRV_M (LP_IO_MUX_GPIO4_MCU_DRV_V << LP_IO_MUX_GPIO4_MCU_DRV_S) +#define LP_IO_MUX_GPIO4_MCU_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO4_MCU_DRV_S 5 +/** LP_IO_MUX_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable pull-down resistor of LP_GPIO4.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO4_FUN_WPD (BIT(7)) +#define LP_IO_MUX_GPIO4_FUN_WPD_M (LP_IO_MUX_GPIO4_FUN_WPD_V << LP_IO_MUX_GPIO4_FUN_WPD_S) +#define LP_IO_MUX_GPIO4_FUN_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO4_FUN_WPD_S 7 +/** LP_IO_MUX_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Configures whether or not enable pull-up resistor of LP_GPIO4.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO4_FUN_WPU (BIT(8)) +#define LP_IO_MUX_GPIO4_FUN_WPU_M (LP_IO_MUX_GPIO4_FUN_WPU_V << LP_IO_MUX_GPIO4_FUN_WPU_S) +#define LP_IO_MUX_GPIO4_FUN_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO4_FUN_WPU_S 8 +/** LP_IO_MUX_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable input of LP_GPIO4.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO4_FUN_IE (BIT(9)) +#define LP_IO_MUX_GPIO4_FUN_IE_M (LP_IO_MUX_GPIO4_FUN_IE_V << LP_IO_MUX_GPIO4_FUN_IE_S) +#define LP_IO_MUX_GPIO4_FUN_IE_V 0x00000001U +#define LP_IO_MUX_GPIO4_FUN_IE_S 9 +/** LP_IO_MUX_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Configures the drive strength of LP_GPIO4. \\ + * 0: ~5 mA\\ + * 1: ~10 mA\\ + * 2: ~20 mA\\ + * 3: ~40 mA\\ + */ +#define LP_IO_MUX_GPIO4_FUN_DRV 0x00000003U +#define LP_IO_MUX_GPIO4_FUN_DRV_M (LP_IO_MUX_GPIO4_FUN_DRV_V << LP_IO_MUX_GPIO4_FUN_DRV_S) +#define LP_IO_MUX_GPIO4_FUN_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO4_FUN_DRV_S 10 +/** LP_IO_MUX_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Configures to select LP IO MUX function for this signal. \\ + * 0: Select Function 0\\ + * 1: Select Function 1\\ + * ......\\ + */ +#define LP_IO_MUX_GPIO4_MCU_SEL 0x00000007U +#define LP_IO_MUX_GPIO4_MCU_SEL_M (LP_IO_MUX_GPIO4_MCU_SEL_V << LP_IO_MUX_GPIO4_MCU_SEL_S) +#define LP_IO_MUX_GPIO4_MCU_SEL_V 0x00000007U +#define LP_IO_MUX_GPIO4_MCU_SEL_S 12 +/** LP_IO_MUX_GPIO4_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable filter for pin input signals.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO4_FILTER_EN (BIT(15)) +#define LP_IO_MUX_GPIO4_FILTER_EN_M (LP_IO_MUX_GPIO4_FILTER_EN_V << LP_IO_MUX_GPIO4_FILTER_EN_S) +#define LP_IO_MUX_GPIO4_FILTER_EN_V 0x00000001U +#define LP_IO_MUX_GPIO4_FILTER_EN_S 15 +/** LP_IO_MUX_GPIO4_HYS_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the hysteresis function of the pin when + * LP_IO_MUX_GPIO4_HYS_SEL is set to 1.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO4_HYS_EN (BIT(16)) +#define LP_IO_MUX_GPIO4_HYS_EN_M (LP_IO_MUX_GPIO4_HYS_EN_V << LP_IO_MUX_GPIO4_HYS_EN_S) +#define LP_IO_MUX_GPIO4_HYS_EN_V 0x00000001U +#define LP_IO_MUX_GPIO4_HYS_EN_S 16 +/** LP_IO_MUX_GPIO4_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Configures to choose the signal for enabling the hysteresis function for LP_GPIO4. + * \\ + * 0: Choose the output enable signal of eFuse\\ + * 1: Choose the output enable signal of LP_IO_MUX_GPIO4_HYS_EN\\ + */ +#define LP_IO_MUX_GPIO4_HYS_SEL (BIT(17)) +#define LP_IO_MUX_GPIO4_HYS_SEL_M (LP_IO_MUX_GPIO4_HYS_SEL_V << LP_IO_MUX_GPIO4_HYS_SEL_S) +#define LP_IO_MUX_GPIO4_HYS_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO4_HYS_SEL_S 17 + +/** LP_IO_MUX_GPIO5_REG register + * LP IO MUX configuration register for LP_GPIO5 + */ +#define LP_IO_MUX_GPIO5_REG (DR_REG_LP_IO_MUX_BASE + 0x14) +/** LP_IO_MUX_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the output of LP_GPIO5 in sleep mode. + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO5_MCU_OE (BIT(0)) +#define LP_IO_MUX_GPIO5_MCU_OE_M (LP_IO_MUX_GPIO5_MCU_OE_V << LP_IO_MUX_GPIO5_MCU_OE_S) +#define LP_IO_MUX_GPIO5_MCU_OE_V 0x00000001U +#define LP_IO_MUX_GPIO5_MCU_OE_S 0 +/** LP_IO_MUX_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enter sleep mode for LP_GPIO5.\\ + * 0: Not enter\\ + * 1: Enter\\ + */ +#define LP_IO_MUX_GPIO5_SLP_SEL (BIT(1)) +#define LP_IO_MUX_GPIO5_SLP_SEL_M (LP_IO_MUX_GPIO5_SLP_SEL_V << LP_IO_MUX_GPIO5_SLP_SEL_S) +#define LP_IO_MUX_GPIO5_SLP_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO5_SLP_SEL_S 1 +/** LP_IO_MUX_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Configure whether or not to enable pull-down resistor of LP_GPIO5 in sleep mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO5_MCU_WPD (BIT(2)) +#define LP_IO_MUX_GPIO5_MCU_WPD_M (LP_IO_MUX_GPIO5_MCU_WPD_V << LP_IO_MUX_GPIO5_MCU_WPD_S) +#define LP_IO_MUX_GPIO5_MCU_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO5_MCU_WPD_S 2 +/** LP_IO_MUX_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable pull-up resistor of LP_GPIO5 during sleep mode. + * \\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO5_MCU_WPU (BIT(3)) +#define LP_IO_MUX_GPIO5_MCU_WPU_M (LP_IO_MUX_GPIO5_MCU_WPU_V << LP_IO_MUX_GPIO5_MCU_WPU_S) +#define LP_IO_MUX_GPIO5_MCU_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO5_MCU_WPU_S 3 +/** LP_IO_MUX_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the input of LP_GPIO5 during sleep mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO5_MCU_IE (BIT(4)) +#define LP_IO_MUX_GPIO5_MCU_IE_M (LP_IO_MUX_GPIO5_MCU_IE_V << LP_IO_MUX_GPIO5_MCU_IE_S) +#define LP_IO_MUX_GPIO5_MCU_IE_V 0x00000001U +#define LP_IO_MUX_GPIO5_MCU_IE_S 4 +/** LP_IO_MUX_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Configures the drive strength of LP_GPIO5 during sleep mode. \\ + * 0: ~5 mA\\ + * 1: ~10 mA\\ + * 2: ~20 mA\\ + * 3: ~40 mA\\ + */ +#define LP_IO_MUX_GPIO5_MCU_DRV 0x00000003U +#define LP_IO_MUX_GPIO5_MCU_DRV_M (LP_IO_MUX_GPIO5_MCU_DRV_V << LP_IO_MUX_GPIO5_MCU_DRV_S) +#define LP_IO_MUX_GPIO5_MCU_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO5_MCU_DRV_S 5 +/** LP_IO_MUX_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable pull-down resistor of LP_GPIO5.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO5_FUN_WPD (BIT(7)) +#define LP_IO_MUX_GPIO5_FUN_WPD_M (LP_IO_MUX_GPIO5_FUN_WPD_V << LP_IO_MUX_GPIO5_FUN_WPD_S) +#define LP_IO_MUX_GPIO5_FUN_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO5_FUN_WPD_S 7 +/** LP_IO_MUX_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Configures whether or not enable pull-up resistor of LP_GPIO5.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO5_FUN_WPU (BIT(8)) +#define LP_IO_MUX_GPIO5_FUN_WPU_M (LP_IO_MUX_GPIO5_FUN_WPU_V << LP_IO_MUX_GPIO5_FUN_WPU_S) +#define LP_IO_MUX_GPIO5_FUN_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO5_FUN_WPU_S 8 +/** LP_IO_MUX_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable input of LP_GPIO5.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO5_FUN_IE (BIT(9)) +#define LP_IO_MUX_GPIO5_FUN_IE_M (LP_IO_MUX_GPIO5_FUN_IE_V << LP_IO_MUX_GPIO5_FUN_IE_S) +#define LP_IO_MUX_GPIO5_FUN_IE_V 0x00000001U +#define LP_IO_MUX_GPIO5_FUN_IE_S 9 +/** LP_IO_MUX_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Configures the drive strength of LP_GPIO5. \\ + * 0: ~5 mA\\ + * 1: ~10 mA\\ + * 2: ~20 mA\\ + * 3: ~40 mA\\ + */ +#define LP_IO_MUX_GPIO5_FUN_DRV 0x00000003U +#define LP_IO_MUX_GPIO5_FUN_DRV_M (LP_IO_MUX_GPIO5_FUN_DRV_V << LP_IO_MUX_GPIO5_FUN_DRV_S) +#define LP_IO_MUX_GPIO5_FUN_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO5_FUN_DRV_S 10 +/** LP_IO_MUX_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Configures to select LP IO MUX function for this signal. \\ + * 0: Select Function 0\\ + * 1: Select Function 1\\ + * ......\\ + */ +#define LP_IO_MUX_GPIO5_MCU_SEL 0x00000007U +#define LP_IO_MUX_GPIO5_MCU_SEL_M (LP_IO_MUX_GPIO5_MCU_SEL_V << LP_IO_MUX_GPIO5_MCU_SEL_S) +#define LP_IO_MUX_GPIO5_MCU_SEL_V 0x00000007U +#define LP_IO_MUX_GPIO5_MCU_SEL_S 12 +/** LP_IO_MUX_GPIO5_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable filter for pin input signals.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO5_FILTER_EN (BIT(15)) +#define LP_IO_MUX_GPIO5_FILTER_EN_M (LP_IO_MUX_GPIO5_FILTER_EN_V << LP_IO_MUX_GPIO5_FILTER_EN_S) +#define LP_IO_MUX_GPIO5_FILTER_EN_V 0x00000001U +#define LP_IO_MUX_GPIO5_FILTER_EN_S 15 +/** LP_IO_MUX_GPIO5_HYS_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the hysteresis function of the pin when + * LP_IO_MUX_GPIO5_HYS_SEL is set to 1.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO5_HYS_EN (BIT(16)) +#define LP_IO_MUX_GPIO5_HYS_EN_M (LP_IO_MUX_GPIO5_HYS_EN_V << LP_IO_MUX_GPIO5_HYS_EN_S) +#define LP_IO_MUX_GPIO5_HYS_EN_V 0x00000001U +#define LP_IO_MUX_GPIO5_HYS_EN_S 16 +/** LP_IO_MUX_GPIO5_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Configures to choose the signal for enabling the hysteresis function for LP_GPIO5. + * \\ + * 0: Choose the output enable signal of eFuse\\ + * 1: Choose the output enable signal of LP_IO_MUX_GPIO5_HYS_EN\\ + */ +#define LP_IO_MUX_GPIO5_HYS_SEL (BIT(17)) +#define LP_IO_MUX_GPIO5_HYS_SEL_M (LP_IO_MUX_GPIO5_HYS_SEL_V << LP_IO_MUX_GPIO5_HYS_SEL_S) +#define LP_IO_MUX_GPIO5_HYS_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO5_HYS_SEL_S 17 + +/** LP_IO_MUX_GPIO6_REG register + * LP IO MUX configuration register for LP_GPIO6 + */ +#define LP_IO_MUX_GPIO6_REG (DR_REG_LP_IO_MUX_BASE + 0x18) +/** LP_IO_MUX_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the output of LP_GPIO6 in sleep mode. + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO6_MCU_OE (BIT(0)) +#define LP_IO_MUX_GPIO6_MCU_OE_M (LP_IO_MUX_GPIO6_MCU_OE_V << LP_IO_MUX_GPIO6_MCU_OE_S) +#define LP_IO_MUX_GPIO6_MCU_OE_V 0x00000001U +#define LP_IO_MUX_GPIO6_MCU_OE_S 0 +/** LP_IO_MUX_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enter sleep mode for LP_GPIO6.\\ + * 0: Not enter\\ + * 1: Enter\\ + */ +#define LP_IO_MUX_GPIO6_SLP_SEL (BIT(1)) +#define LP_IO_MUX_GPIO6_SLP_SEL_M (LP_IO_MUX_GPIO6_SLP_SEL_V << LP_IO_MUX_GPIO6_SLP_SEL_S) +#define LP_IO_MUX_GPIO6_SLP_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO6_SLP_SEL_S 1 +/** LP_IO_MUX_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0; + * Configure whether or not to enable pull-down resistor of LP_GPIO6 in sleep mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO6_MCU_WPD (BIT(2)) +#define LP_IO_MUX_GPIO6_MCU_WPD_M (LP_IO_MUX_GPIO6_MCU_WPD_V << LP_IO_MUX_GPIO6_MCU_WPD_S) +#define LP_IO_MUX_GPIO6_MCU_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO6_MCU_WPD_S 2 +/** LP_IO_MUX_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable pull-up resistor of LP_GPIO6 during sleep mode. + * \\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO6_MCU_WPU (BIT(3)) +#define LP_IO_MUX_GPIO6_MCU_WPU_M (LP_IO_MUX_GPIO6_MCU_WPU_V << LP_IO_MUX_GPIO6_MCU_WPU_S) +#define LP_IO_MUX_GPIO6_MCU_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO6_MCU_WPU_S 3 +/** LP_IO_MUX_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the input of LP_GPIO6 during sleep mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO6_MCU_IE (BIT(4)) +#define LP_IO_MUX_GPIO6_MCU_IE_M (LP_IO_MUX_GPIO6_MCU_IE_V << LP_IO_MUX_GPIO6_MCU_IE_S) +#define LP_IO_MUX_GPIO6_MCU_IE_V 0x00000001U +#define LP_IO_MUX_GPIO6_MCU_IE_S 4 +/** LP_IO_MUX_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0; + * Configures the drive strength of LP_GPIO6 during sleep mode. \\ + * 0: ~5 mA\\ + * 1: ~10 mA\\ + * 2: ~20 mA\\ + * 3: ~40 mA\\ + */ +#define LP_IO_MUX_GPIO6_MCU_DRV 0x00000003U +#define LP_IO_MUX_GPIO6_MCU_DRV_M (LP_IO_MUX_GPIO6_MCU_DRV_V << LP_IO_MUX_GPIO6_MCU_DRV_S) +#define LP_IO_MUX_GPIO6_MCU_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO6_MCU_DRV_S 5 +/** LP_IO_MUX_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable pull-down resistor of LP_GPIO6.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO6_FUN_WPD (BIT(7)) +#define LP_IO_MUX_GPIO6_FUN_WPD_M (LP_IO_MUX_GPIO6_FUN_WPD_V << LP_IO_MUX_GPIO6_FUN_WPD_S) +#define LP_IO_MUX_GPIO6_FUN_WPD_V 0x00000001U +#define LP_IO_MUX_GPIO6_FUN_WPD_S 7 +/** LP_IO_MUX_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0; + * Configures whether or not enable pull-up resistor of LP_GPIO6.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO6_FUN_WPU (BIT(8)) +#define LP_IO_MUX_GPIO6_FUN_WPU_M (LP_IO_MUX_GPIO6_FUN_WPU_V << LP_IO_MUX_GPIO6_FUN_WPU_S) +#define LP_IO_MUX_GPIO6_FUN_WPU_V 0x00000001U +#define LP_IO_MUX_GPIO6_FUN_WPU_S 8 +/** LP_IO_MUX_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable input of LP_GPIO6.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO6_FUN_IE (BIT(9)) +#define LP_IO_MUX_GPIO6_FUN_IE_M (LP_IO_MUX_GPIO6_FUN_IE_V << LP_IO_MUX_GPIO6_FUN_IE_S) +#define LP_IO_MUX_GPIO6_FUN_IE_V 0x00000001U +#define LP_IO_MUX_GPIO6_FUN_IE_S 9 +/** LP_IO_MUX_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 2; + * Configures the drive strength of LP_GPIO6. \\ + * 0: ~5 mA\\ + * 1: ~10 mA\\ + * 2: ~20 mA\\ + * 3: ~40 mA\\ + */ +#define LP_IO_MUX_GPIO6_FUN_DRV 0x00000003U +#define LP_IO_MUX_GPIO6_FUN_DRV_M (LP_IO_MUX_GPIO6_FUN_DRV_V << LP_IO_MUX_GPIO6_FUN_DRV_S) +#define LP_IO_MUX_GPIO6_FUN_DRV_V 0x00000003U +#define LP_IO_MUX_GPIO6_FUN_DRV_S 10 +/** LP_IO_MUX_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 0; + * Configures to select LP IO MUX function for this signal. \\ + * 0: Select Function 0\\ + * 1: Select Function 1\\ + * ......\\ + */ +#define LP_IO_MUX_GPIO6_MCU_SEL 0x00000007U +#define LP_IO_MUX_GPIO6_MCU_SEL_M (LP_IO_MUX_GPIO6_MCU_SEL_V << LP_IO_MUX_GPIO6_MCU_SEL_S) +#define LP_IO_MUX_GPIO6_MCU_SEL_V 0x00000007U +#define LP_IO_MUX_GPIO6_MCU_SEL_S 12 +/** LP_IO_MUX_GPIO6_FILTER_EN : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable filter for pin input signals.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO6_FILTER_EN (BIT(15)) +#define LP_IO_MUX_GPIO6_FILTER_EN_M (LP_IO_MUX_GPIO6_FILTER_EN_V << LP_IO_MUX_GPIO6_FILTER_EN_S) +#define LP_IO_MUX_GPIO6_FILTER_EN_V 0x00000001U +#define LP_IO_MUX_GPIO6_FILTER_EN_S 15 +/** LP_IO_MUX_GPIO6_HYS_EN : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the hysteresis function of the pin when + * LP_IO_MUX_GPIO6_HYS_SEL is set to 1.\\ + * 0: Disable\\ + * 1: Enable\\ + */ +#define LP_IO_MUX_GPIO6_HYS_EN (BIT(16)) +#define LP_IO_MUX_GPIO6_HYS_EN_M (LP_IO_MUX_GPIO6_HYS_EN_V << LP_IO_MUX_GPIO6_HYS_EN_S) +#define LP_IO_MUX_GPIO6_HYS_EN_V 0x00000001U +#define LP_IO_MUX_GPIO6_HYS_EN_S 16 +/** LP_IO_MUX_GPIO6_HYS_SEL : R/W; bitpos: [17]; default: 0; + * Configures to choose the signal for enabling the hysteresis function for LP_GPIO6. + * \\ + * 0: Choose the output enable signal of eFuse\\ + * 1: Choose the output enable signal of LP_IO_MUX_GPIO6_HYS_EN\\ + */ +#define LP_IO_MUX_GPIO6_HYS_SEL (BIT(17)) +#define LP_IO_MUX_GPIO6_HYS_SEL_M (LP_IO_MUX_GPIO6_HYS_SEL_V << LP_IO_MUX_GPIO6_HYS_SEL_S) +#define LP_IO_MUX_GPIO6_HYS_SEL_V 0x00000001U +#define LP_IO_MUX_GPIO6_HYS_SEL_S 17 + +/** LP_IO_MUX_DATE_REG register + * Version control register + */ +#define LP_IO_MUX_DATE_REG (DR_REG_LP_IO_MUX_BASE + 0x1fc) +/** LP_IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 36729408; + * Version control register + */ +#define LP_IO_MUX_REG_DATE 0x0FFFFFFFU +#define LP_IO_MUX_REG_DATE_M (LP_IO_MUX_REG_DATE_V << LP_IO_MUX_REG_DATE_S) +#define LP_IO_MUX_REG_DATE_V 0x0FFFFFFFU +#define LP_IO_MUX_REG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/lp_io_mux_struct.h b/components/soc/esp32c61/include/soc/lp_io_mux_struct.h new file mode 100644 index 0000000000..69aef47228 --- /dev/null +++ b/components/soc/esp32c61/include/soc/lp_io_mux_struct.h @@ -0,0 +1,147 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of gpion register + * LP IO MUX configuration register for LP_GPIOn + */ +typedef union { + struct { + /** gpion_mcu_oe : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable the output of LP_GPIOn in sleep mode. + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t gpion_mcu_oe:1; + /** gpion_slp_sel : R/W; bitpos: [1]; default: 0; + * Configures whether or not to enter sleep mode for LP_GPIOn.\\ + * 0: Not enter\\ + * 1: Enter\\ + */ + uint32_t gpion_slp_sel:1; + /** gpion_mcu_wpd : R/W; bitpos: [2]; default: 0; + * Configure whether or not to enable pull-down resistor of LP_GPIOn in sleep mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t gpion_mcu_wpd:1; + /** gpion_mcu_wpu : R/W; bitpos: [3]; default: 0; + * Configures whether or not to enable pull-up resistor of LP_GPIOn during sleep mode. + * \\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t gpion_mcu_wpu:1; + /** gpion_mcu_ie : R/W; bitpos: [4]; default: 0; + * Configures whether or not to enable the input of LP_GPIOn during sleep mode.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t gpion_mcu_ie:1; + /** gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0; + * Configures the drive strength of LP_GPIOn during sleep mode. \\ + * 0: ~5 mA\\ + * 1: ~10 mA\\ + * 2: ~20 mA\\ + * 3: ~40 mA\\ + */ + uint32_t gpion_mcu_drv:2; + /** gpion_fun_wpd : R/W; bitpos: [7]; default: 0; + * Configures whether or not to enable pull-down resistor of LP_GPIOn.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t gpion_fun_wpd:1; + /** gpion_fun_wpu : R/W; bitpos: [8]; default: 0; + * Configures whether or not enable pull-up resistor of LP_GPIOn.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t gpion_fun_wpu:1; + /** gpion_fun_ie : R/W; bitpos: [9]; default: 0; + * Configures whether or not to enable input of LP_GPIOn.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t gpion_fun_ie:1; + /** gpion_fun_drv : R/W; bitpos: [11:10]; default: 2; + * Configures the drive strength of LP_GPIOn. \\ + * 0: ~5 mA\\ + * 1: ~10 mA\\ + * 2: ~20 mA\\ + * 3: ~40 mA\\ + */ + uint32_t gpion_fun_drv:2; + /** gpion_mcu_sel : R/W; bitpos: [14:12]; default: 0; + * Configures to select LP IO MUX function for this signal. \\ + * 0: Select Function 0\\ + * 1: Select Function 1\\ + * ......\\ + */ + uint32_t gpion_mcu_sel:3; + /** gpion_filter_en : R/W; bitpos: [15]; default: 0; + * Configures whether or not to enable filter for pin input signals.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t gpion_filter_en:1; + /** gpion_hys_en : R/W; bitpos: [16]; default: 0; + * Configures whether or not to enable the hysteresis function of the pin when + * LP_IO_MUX_GPIOn_HYS_SEL is set to 1.\\ + * 0: Disable\\ + * 1: Enable\\ + */ + uint32_t gpion_hys_en:1; + /** gpion_hys_sel : R/W; bitpos: [17]; default: 0; + * Configures to choose the signal for enabling the hysteresis function for LP_GPIOn. + * \\ + * 0: Choose the output enable signal of eFuse\\ + * 1: Choose the output enable signal of LP_IO_MUX_GPIOn_HYS_EN\\ + */ + uint32_t gpion_hys_sel:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} lp_io_mux_gpion_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** reg_date : R/W; bitpos: [27:0]; default: 36729408; + * Version control register + */ + uint32_t reg_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_io_mux_date_reg_t; + + +typedef struct { + volatile lp_io_mux_gpion_reg_t gpion[7]; + uint32_t reserved_01c[120]; + volatile lp_io_mux_date_reg_t date; +} lp_io_mux_dev_t; + +extern lp_io_mux_dev_t LP_IO_MUX; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_io_mux_dev_t) == 0x200, "Invalid size of lp_io_mux_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/lp_tee_reg.h b/components/soc/esp32c61/include/soc/lp_tee_reg.h new file mode 100644 index 0000000000..9c5f90b2a9 --- /dev/null +++ b/components/soc/esp32c61/include/soc/lp_tee_reg.h @@ -0,0 +1,80 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_TEE_M0_MODE_CTRL_REG register + * TEE mode control register + */ +#define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0) +/** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3; + * Configures M0 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define LP_TEE_M0_MODE 0x00000003U +#define LP_TEE_M0_MODE_M (LP_TEE_M0_MODE_V << LP_TEE_M0_MODE_S) +#define LP_TEE_M0_MODE_V 0x00000003U +#define LP_TEE_M0_MODE_S 0 +/** LP_TEE_M0_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define LP_TEE_M0_LOCK (BIT(2)) +#define LP_TEE_M0_LOCK_M (LP_TEE_M0_LOCK_V << LP_TEE_M0_LOCK_S) +#define LP_TEE_M0_LOCK_V 0x00000001U +#define LP_TEE_M0_LOCK_S 2 + +/** LP_TEE_CLOCK_GATE_REG register + * Clock gating register + */ +#define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0x4) +/** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on.\\ + * 0: enable automatic clock gating \\ + * 1: keep the clock always on \\ + */ +#define LP_TEE_CLK_EN (BIT(0)) +#define LP_TEE_CLK_EN_M (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S) +#define LP_TEE_CLK_EN_V 0x00000001U +#define LP_TEE_CLK_EN_S 0 + +/** LP_TEE_FORCE_ACC_HP_REG register + * Force access to hpmem configuration register + */ +#define LP_TEE_FORCE_ACC_HP_REG (DR_REG_LP_TEE_BASE + 0x90) +/** LP_TEE_FORCE_ACC_HPMEM_EN : R/W; bitpos: [0]; default: 0; + * Configures whether to allow LP CPU to force access to HP_MEM regardless of + * permission management.\\ + * 0: disable force access HP_MEM \\ + * 1: enable force access HP_MEM \\ + */ +#define LP_TEE_FORCE_ACC_HPMEM_EN (BIT(0)) +#define LP_TEE_FORCE_ACC_HPMEM_EN_M (LP_TEE_FORCE_ACC_HPMEM_EN_V << LP_TEE_FORCE_ACC_HPMEM_EN_S) +#define LP_TEE_FORCE_ACC_HPMEM_EN_V 0x00000001U +#define LP_TEE_FORCE_ACC_HPMEM_EN_S 0 + +/** LP_TEE_DATE_REG register + * Version control register + */ +#define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc) +/** LP_TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35725664; + * Version control register + */ +#define LP_TEE_DATE_REG 0x0FFFFFFFU +#define LP_TEE_DATE_REG_M (LP_TEE_DATE_REG_V << LP_TEE_DATE_REG_S) +#define LP_TEE_DATE_REG_V 0x0FFFFFFFU +#define LP_TEE_DATE_REG_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/lp_tee_struct.h b/components/soc/esp32c61/include/soc/lp_tee_struct.h new file mode 100644 index 0000000000..45df3bec58 --- /dev/null +++ b/components/soc/esp32c61/include/soc/lp_tee_struct.h @@ -0,0 +1,107 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Tee mode control register */ +/** Type of m0_mode_ctrl register + * TEE mode control register + */ +typedef union { + struct { + /** m0_mode : R/W; bitpos: [1:0]; default: 3; + * Configures M0 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ + uint32_t m0_mode:2; + /** m0_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ + uint32_t m0_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} lp_tee_m0_mode_ctrl_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * Clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on.\\ + * 0: enable automatic clock gating \\ + * 1: keep the clock always on \\ + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_tee_clock_gate_reg_t; + + +/** Group: Force access to hpmem configuration register */ +/** Type of force_acc_hp register + * Force access to hpmem configuration register + */ +typedef union { + struct { + /** force_acc_hpmem_en : R/W; bitpos: [0]; default: 0; + * Configures whether to allow LP CPU to force access to HP_MEM regardless of + * permission management.\\ + * 0: disable force access HP_MEM \\ + * 1: enable force access HP_MEM \\ + */ + uint32_t force_acc_hpmem_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} lp_tee_force_acc_hp_reg_t; + + +/** Group: Version control register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date_reg : R/W; bitpos: [27:0]; default: 35725664; + * Version control register + */ + uint32_t date_reg:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} lp_tee_date_reg_t; + + +typedef struct { + volatile lp_tee_m0_mode_ctrl_reg_t m0_mode_ctrl; + volatile lp_tee_clock_gate_reg_t clock_gate; + uint32_t reserved_008[34]; + volatile lp_tee_force_acc_hp_reg_t force_acc_hp; + uint32_t reserved_094[26]; + volatile lp_tee_date_reg_t date; +} lp_tee_dev_t; + +extern lp_tee_dev_t LP_TEE; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_tee_dev_t) == 0x100, "Invalid size of lp_tee_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/lp_timer_reg.h b/components/soc/esp32c61/include/soc/lp_timer_reg.h new file mode 100644 index 0000000000..b602195b75 --- /dev/null +++ b/components/soc/esp32c61/include/soc/lp_timer_reg.h @@ -0,0 +1,348 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_TIMER_TAR0_LOW_REG register + * RTC timer threshold low bits register0 + */ +#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0) +/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0; + * Configures the lower 32 bits of the trigger threshold for the RTC timer compare0. + */ +#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0 + +/** LP_TIMER_TAR0_HIGH_REG register + * RTC timer enable register0 + */ +#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0; + * Configures the higher 16 bits of the trigger threshold for the RTC timer compare0 + */ +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0; + * Configure this bit to enable the timer compare0 alarm.\\0: Disable \\1: Enable + */ +#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31 + +/** LP_TIMER_TAR1_LOW_REG register + * RTC timer threshold low bits register1 + */ +#define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x8) +/** LP_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0; + * Configures the lower 32 bits of the trigger threshold for the RTC timer compare1. + */ +#define LP_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_M (LP_TIMER_MAIN_TIMER_TAR_LOW1_V << LP_TIMER_MAIN_TIMER_TAR_LOW1_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_S 0 + +/** LP_TIMER_TAR1_HIGH_REG register + * RTC timer threshold high bits register0 + */ +#define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0xc) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0; + * Configures the higher 16 bits of the trigger threshold for the RTC timer compare1 + */ +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_M (LP_TIMER_MAIN_TIMER_TAR_HIGH1_V << LP_TIMER_MAIN_TIMER_TAR_HIGH1_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0; + * Configure this bit to enable the timer compare1 alarm.\\0: Disable \\1: Enable + */ +#define LP_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN1_M (LP_TIMER_MAIN_TIMER_TAR_EN1_V << LP_TIMER_MAIN_TIMER_TAR_EN1_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN1_S 31 + +/** LP_TIMER_UPDATE_REG register + * RTC timer update control register + */ +#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10) +/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [27]; default: 0; + * Triggers timer by software + */ +#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(27)) +#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S) +#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_UPDATE_S 27 +/** LP_TIMER_MAIN_TIMER_REGDMA_WORK : R/W; bitpos: [28]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when regdma working + */ +#define LP_TIMER_MAIN_TIMER_REGDMA_WORK (BIT(28)) +#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_M (LP_TIMER_MAIN_TIMER_REGDMA_WORK_V << LP_TIMER_MAIN_TIMER_REGDMA_WORK_S) +#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_S 28 +/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when XTAL\_CLK powers + * up + */ +#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29)) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29 +/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when CPU enters or + * exits the stall state. + */ +#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30)) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30 +/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when resetting digital + * core completes + */ +#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S) +#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31 + +/** LP_TIMER_MAIN_BUF0_LOW_REG register + * RTC timer buffer0 low bits register + */ +#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14) +/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0; + * RTC timer buffer0 low bits register + */ +#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0 + +/** LP_TIMER_MAIN_BUF0_HIGH_REG register + * RTC timer buffer0 high bits register + */ +#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18) +/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0; + * RTC timer buffer0 high bits register + */ +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0 + +/** LP_TIMER_MAIN_BUF1_LOW_REG register + * RTC timer buffer1 low bits register + */ +#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c) +/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0; + * RTC timer buffer1 low bits register + */ +#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0 + +/** LP_TIMER_MAIN_BUF1_HIGH_REG register + * RTC timer buffer1 high bits register + */ +#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20) +/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0; + * RTC timer buffer1 high bits register + */ +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0 + +/** LP_TIMER_MAIN_OVERFLOW_REG register */ +#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24) +/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0; */ +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31)) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S 31 + +/** LP_TIMER_INT_RAW_REG register + * RTC timer interrupt raw register + */ +#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28) +/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * Triggered when counter register of RTC main timer overflow. + */ +#define LP_TIMER_OVERFLOW_RAW (BIT(30)) +#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S) +#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U +#define LP_TIMER_OVERFLOW_RAW_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * Triggered when RTC main timer reach the target value. + */ +#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31 + +/** LP_TIMER_INT_ST_REG register + * RTC timer interrupt status register + */ +#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c) +/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0; + * Status of RTC main timer overflow interrupt . + */ +#define LP_TIMER_OVERFLOW_ST (BIT(30)) +#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S) +#define LP_TIMER_OVERFLOW_ST_V 0x00000001U +#define LP_TIMER_OVERFLOW_ST_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; + * Status of RTC main timer interrupt . + */ +#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S) +#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31 + +/** LP_TIMER_INT_ENA_REG register + * RTC timer interrupt enable register + */ +#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30) +/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0; + * Enable the RTC main timer overflow interrupt..\\0 : Disable \\1: Enable + */ +#define LP_TIMER_OVERFLOW_ENA (BIT(30)) +#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S) +#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U +#define LP_TIMER_OVERFLOW_ENA_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; + * Enable the RTC main timer interrupt..\\0 : Disable \\1: Enable + */ +#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31 + +/** LP_TIMER_INT_CLR_REG register + * RTC timer interrupt clear register + */ +#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34) +/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0; + * Clear the RTC main timer overflow raw interrupt.. + */ +#define LP_TIMER_OVERFLOW_CLR (BIT(30)) +#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S) +#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U +#define LP_TIMER_OVERFLOW_CLR_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; + * Clear the RTC main timer raw interrupt.. + */ +#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31 + +/** LP_TIMER_LP_INT_RAW_REG register + * RTC timer interrupt raw register(For ULP) + */ +#define LP_TIMER_LP_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x38) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * Triggered when counter register of RTC main timer overflow + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * Triggered when RTC main timer reach the target value + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_LP_INT_RAW_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_S 31 + +/** LP_TIMER_LP_INT_ST_REG register + * RTC timer interrupt status register(For ULP) + */ +#define LP_TIMER_LP_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x3c) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0; + * Status of RTC main timer overflow interrupt . + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0; + * Status of RTC main timer interrupt . + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_LP_INT_ST_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_S 31 + +/** LP_TIMER_LP_INT_ENA_REG register + * RTC timer interrupt enable register(For ULP) + */ +#define LP_TIMER_LP_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x40) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0; + * Enable the RTC main timer overflow interrupt..\\0 : Disable \\1: Enable + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0; + * Enable the RTC main timer interrupt..\\0 : Disable \\1: Enable + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_LP_INT_ENA_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_S 31 + +/** LP_TIMER_LP_INT_CLR_REG register + * RTC timer interrupt clear register(For ULP) + */ +#define LP_TIMER_LP_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x44) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0; + * Clear the RTC main timer overflow clear interrupt.. + */ +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0; + * Clear the RTC main timer clear interrupt.. + */ +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_LP_INT_CLR_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_S 31 + +/** LP_TIMER_DATE_REG register + * need_des + */ +#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc) +/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 36769936; + * Version data + */ +#define LP_TIMER_DATE 0x7FFFFFFFU +#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S) +#define LP_TIMER_DATE_V 0x7FFFFFFFU +#define LP_TIMER_DATE_S 0 +/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LP_TIMER_CLK_EN (BIT(31)) +#define LP_TIMER_CLK_EN_M (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S) +#define LP_TIMER_CLK_EN_V 0x00000001U +#define LP_TIMER_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/lp_timer_struct.h b/components/soc/esp32c61/include/soc/lp_timer_struct.h new file mode 100644 index 0000000000..667e5e136a --- /dev/null +++ b/components/soc/esp32c61/include/soc/lp_timer_struct.h @@ -0,0 +1,366 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of tar0_low register + * RTC timer threshold low bits register0 + */ +typedef union { + struct { + /** main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0; + * Configures the lower 32 bits of the trigger threshold for the RTC timer compare0. + */ + uint32_t main_timer_tar_low0:32; + }; + uint32_t val; +} lp_timer_tar0_low_reg_t; + +/** Type of tar0_high register + * RTC timer enable register0 + */ +typedef union { + struct { + /** main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0; + * Configures the higher 16 bits of the trigger threshold for the RTC timer compare0 + */ + uint32_t main_timer_tar_high0:16; + uint32_t reserved_16:15; + /** main_timer_tar_en0 : WT; bitpos: [31]; default: 0; + * Configure this bit to enable the timer compare0 alarm.\\0: Disable \\1: Enable + */ + uint32_t main_timer_tar_en0:1; + }; + uint32_t val; +} lp_timer_tar0_high_reg_t; + +/** Type of tar1_low register + * RTC timer threshold low bits register1 + */ +typedef union { + struct { + /** main_timer_tar_low1 : R/W; bitpos: [31:0]; default: 0; + * Configures the lower 32 bits of the trigger threshold for the RTC timer compare1. + */ + uint32_t main_timer_tar_low1:32; + }; + uint32_t val; +} lp_timer_tar1_low_reg_t; + +/** Type of tar1_high register + * RTC timer threshold high bits register0 + */ +typedef union { + struct { + /** main_timer_tar_high1 : R/W; bitpos: [15:0]; default: 0; + * Configures the higher 16 bits of the trigger threshold for the RTC timer compare1 + */ + uint32_t main_timer_tar_high1:16; + uint32_t reserved_16:15; + /** main_timer_tar_en1 : WT; bitpos: [31]; default: 0; + * Configure this bit to enable the timer compare1 alarm.\\0: Disable \\1: Enable + */ + uint32_t main_timer_tar_en1:1; + }; + uint32_t val; +} lp_timer_tar1_high_reg_t; + +/** Type of update register + * RTC timer update control register + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** main_timer_update : WT; bitpos: [27]; default: 0; + * Triggers timer by software + */ + uint32_t main_timer_update:1; + /** main_timer_regdma_work : R/W; bitpos: [28]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when regdma working + */ + uint32_t main_timer_regdma_work:1; + /** main_timer_xtal_off : R/W; bitpos: [29]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when XTAL\_CLK powers + * up + */ + uint32_t main_timer_xtal_off:1; + /** main_timer_sys_stall : R/W; bitpos: [30]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when CPU enters or + * exits the stall state. + */ + uint32_t main_timer_sys_stall:1; + /** main_timer_sys_rst : R/W; bitpos: [31]; default: 0; + * Selects the triggering condition for the RTC timer,triggered when resetting digital + * core completes + */ + uint32_t main_timer_sys_rst:1; + }; + uint32_t val; +} lp_timer_update_reg_t; + +/** Type of main_buf0_low register + * RTC timer buffer0 low bits register + */ +typedef union { + struct { + /** main_timer_buf0_low : RO; bitpos: [31:0]; default: 0; + * RTC timer buffer0 low bits register + */ + uint32_t main_timer_buf0_low:32; + }; + uint32_t val; +} lp_timer_main_buf0_low_reg_t; + +/** Type of main_buf0_high register + * RTC timer buffer0 high bits register + */ +typedef union { + struct { + /** main_timer_buf0_high : RO; bitpos: [15:0]; default: 0; + * RTC timer buffer0 high bits register + */ + uint32_t main_timer_buf0_high:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_timer_main_buf0_high_reg_t; + +/** Type of main_buf1_low register + * RTC timer buffer1 low bits register + */ +typedef union { + struct { + /** main_timer_buf1_low : RO; bitpos: [31:0]; default: 0; + * RTC timer buffer1 low bits register + */ + uint32_t main_timer_buf1_low:32; + }; + uint32_t val; +} lp_timer_main_buf1_low_reg_t; + +/** Type of main_buf1_high register + * RTC timer buffer1 high bits register + */ +typedef union { + struct { + /** main_timer_buf1_high : RO; bitpos: [15:0]; default: 0; + * RTC timer buffer1 high bits register + */ + uint32_t main_timer_buf1_high:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} lp_timer_main_buf1_high_reg_t; + +/** Type of main_overflow register */ +typedef union { + struct { + uint32_t reserved_0:31; + /** main_timer_alarm_load : WT; bitpos: [31]; default: 0; */ + uint32_t main_timer_alarm_load:1; + }; + uint32_t val; +} lp_timer_main_overflow_reg_t; + +/** Type of int_raw register + * RTC timer interrupt raw register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_raw : R/WTC/SS; bitpos: [30]; default: 0; + * Triggered when counter register of RTC main timer overflow. + */ + uint32_t overflow_raw:1; + /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * Triggered when RTC main timer reach the target value. + */ + uint32_t soc_wakeup_int_raw:1; + }; + uint32_t val; +} lp_timer_int_raw_reg_t; + +/** Type of int_st register + * RTC timer interrupt status register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_st : RO; bitpos: [30]; default: 0; + * Status of RTC main timer overflow interrupt . + */ + uint32_t overflow_st:1; + /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; + * Status of RTC main timer interrupt . + */ + uint32_t soc_wakeup_int_st:1; + }; + uint32_t val; +} lp_timer_int_st_reg_t; + +/** Type of int_ena register + * RTC timer interrupt enable register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_ena : R/W; bitpos: [30]; default: 0; + * Enable the RTC main timer overflow interrupt..\\0 : Disable \\1: Enable + */ + uint32_t overflow_ena:1; + /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; + * Enable the RTC main timer interrupt..\\0 : Disable \\1: Enable + */ + uint32_t soc_wakeup_int_ena:1; + }; + uint32_t val; +} lp_timer_int_ena_reg_t; + +/** Type of int_clr register + * RTC timer interrupt clear register + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** overflow_clr : WT; bitpos: [30]; default: 0; + * Clear the RTC main timer overflow raw interrupt.. + */ + uint32_t overflow_clr:1; + /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; + * Clear the RTC main timer raw interrupt.. + */ + uint32_t soc_wakeup_int_clr:1; + }; + uint32_t val; +} lp_timer_int_clr_reg_t; + +/** Type of lp_int_raw register + * RTC timer interrupt raw register(For ULP) + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * Triggered when counter register of RTC main timer overflow + */ + uint32_t main_timer_overflow_lp_int_raw:1; + /** main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * Triggered when RTC main timer reach the target value + */ + uint32_t main_timer_lp_int_raw:1; + }; + uint32_t val; +} lp_timer_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * RTC timer interrupt status register(For ULP) + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0; + * Status of RTC main timer overflow interrupt . + */ + uint32_t main_timer_overflow_lp_int_st:1; + /** main_timer_lp_int_st : RO; bitpos: [31]; default: 0; + * Status of RTC main timer interrupt . + */ + uint32_t main_timer_lp_int_st:1; + }; + uint32_t val; +} lp_timer_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * RTC timer interrupt enable register(For ULP) + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0; + * Enable the RTC main timer overflow interrupt..\\0 : Disable \\1: Enable + */ + uint32_t main_timer_overflow_lp_int_ena:1; + /** main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0; + * Enable the RTC main timer interrupt..\\0 : Disable \\1: Enable + */ + uint32_t main_timer_lp_int_ena:1; + }; + uint32_t val; +} lp_timer_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * RTC timer interrupt clear register(For ULP) + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0; + * Clear the RTC main timer overflow clear interrupt.. + */ + uint32_t main_timer_overflow_lp_int_clr:1; + /** main_timer_lp_int_clr : WT; bitpos: [31]; default: 0; + * Clear the RTC main timer clear interrupt.. + */ + uint32_t main_timer_lp_int_clr:1; + }; + uint32_t val; +} lp_timer_lp_int_clr_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** date : R/W; bitpos: [30:0]; default: 36769936; + * Version data + */ + uint32_t date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_timer_date_reg_t; + + +typedef struct { + volatile lp_timer_tar0_low_reg_t tar0_low; + volatile lp_timer_tar0_high_reg_t tar0_high; + volatile lp_timer_tar1_low_reg_t tar1_low; + volatile lp_timer_tar1_high_reg_t tar1_high; + volatile lp_timer_update_reg_t update; + volatile lp_timer_main_buf0_low_reg_t main_buf0_low; + volatile lp_timer_main_buf0_high_reg_t main_buf0_high; + volatile lp_timer_main_buf1_low_reg_t main_buf1_low; + volatile lp_timer_main_buf1_high_reg_t main_buf1_high; + volatile lp_timer_main_overflow_reg_t main_overflow; + volatile lp_timer_int_raw_reg_t int_raw; + volatile lp_timer_int_st_reg_t int_st; + volatile lp_timer_int_ena_reg_t int_ena; + volatile lp_timer_int_clr_reg_t int_clr; + volatile lp_timer_lp_int_raw_reg_t lp_int_raw; + volatile lp_timer_lp_int_st_reg_t lp_int_st; + volatile lp_timer_lp_int_ena_reg_t lp_int_ena; + volatile lp_timer_lp_int_clr_reg_t lp_int_clr; + uint32_t reserved_048[237]; + volatile lp_timer_date_reg_t date; +} lp_timer_dev_t; + +extern lp_timer_dev_t LP_TIMER; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/lp_wdt_reg.h b/components/soc/esp32c61/include/soc/lp_wdt_reg.h new file mode 100644 index 0000000000..8ac8bb5967 --- /dev/null +++ b/components/soc/esp32c61/include/soc/lp_wdt_reg.h @@ -0,0 +1,356 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LP_WDT_CONFIG0_REG register + * Configure the RWDT operation. + */ +#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0) +/** LP_WDT_WDT_CHIP_RESET_WIDTH : R/W; bitpos: [7:0]; default: 20; + * need_des + */ +#define LP_WDT_WDT_CHIP_RESET_WIDTH 0x000000FFU +#define LP_WDT_WDT_CHIP_RESET_WIDTH_M (LP_WDT_WDT_CHIP_RESET_WIDTH_V << LP_WDT_WDT_CHIP_RESET_WIDTH_S) +#define LP_WDT_WDT_CHIP_RESET_WIDTH_V 0x000000FFU +#define LP_WDT_WDT_CHIP_RESET_WIDTH_S 0 +/** LP_WDT_WDT_CHIP_RESET_EN : R/W; bitpos: [8]; default: 0; + * need_des + */ +#define LP_WDT_WDT_CHIP_RESET_EN (BIT(8)) +#define LP_WDT_WDT_CHIP_RESET_EN_M (LP_WDT_WDT_CHIP_RESET_EN_V << LP_WDT_WDT_CHIP_RESET_EN_S) +#define LP_WDT_WDT_CHIP_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_CHIP_RESET_EN_S 8 +/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1; + * Configure whether or not pause RWDT when chip is in sleep mode.\\0:Enable + * \\1:Disable + */ +#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(9)) +#define LP_WDT_WDT_PAUSE_IN_SLP_M (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S) +#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U +#define LP_WDT_WDT_PAUSE_IN_SLP_S 9 +/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0; + * Configure whether or not to enable RWDT to reset CPU.\\0:Disable \\1:Enable + */ +#define LP_WDT_WDT_APPCPU_RESET_EN (BIT(10)) +#define LP_WDT_WDT_APPCPU_RESET_EN_M (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S) +#define LP_WDT_WDT_APPCPU_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_APPCPU_RESET_EN_S 10 +/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define LP_WDT_WDT_PROCPU_RESET_EN (BIT(11)) +#define LP_WDT_WDT_PROCPU_RESET_EN_M (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S) +#define LP_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U +#define LP_WDT_WDT_PROCPU_RESET_EN_S 11 +/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1; + * Configure whether or not enable RWDT when chip is in SPI boot mode.\\0:Disable + * \\1:Enable + */ +#define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S) +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U +#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12 +/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1; + * Configure the HP core reset time.\\Measurement unit: LP\_DYN\_FAST\_CLK + */ +#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_M (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S) +#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13 +/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1; + * Configure the HP CPU reset time.\\Measurement unit: LP\_DYN\_FAST\_CLK + */ +#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_M (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S) +#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U +#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16 +/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0; + * Configure the timeout action of stage3.\\0: No operation \\1:Generate interrupt \\2 + * :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset. + */ +#define LP_WDT_WDT_STG3 0x00000007U +#define LP_WDT_WDT_STG3_M (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S) +#define LP_WDT_WDT_STG3_V 0x00000007U +#define LP_WDT_WDT_STG3_S 19 +/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0; + * Configure the timeout action of stage2.\\0: No operation \\1:Generate interrupt \\2 + * :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset. + */ +#define LP_WDT_WDT_STG2 0x00000007U +#define LP_WDT_WDT_STG2_M (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S) +#define LP_WDT_WDT_STG2_V 0x00000007U +#define LP_WDT_WDT_STG2_S 22 +/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0; + * Configure the timeout action of stage1.\\0: No operation \\1:Generate interrupt \\2 + * :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset. + */ +#define LP_WDT_WDT_STG1 0x00000007U +#define LP_WDT_WDT_STG1_M (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S) +#define LP_WDT_WDT_STG1_V 0x00000007U +#define LP_WDT_WDT_STG1_S 25 +/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0; + * Configure the timeout action of stage0.\\0: No operation \\1:Generate interrupt \\2 + * :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset. + */ +#define LP_WDT_WDT_STG0 0x00000007U +#define LP_WDT_WDT_STG0_M (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S) +#define LP_WDT_WDT_STG0_V 0x00000007U +#define LP_WDT_WDT_STG0_S 28 +/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0; + * Configure whether or not to enable RWDT.\\0:Disable \\1:Enable + */ +#define LP_WDT_WDT_EN (BIT(31)) +#define LP_WDT_WDT_EN_M (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S) +#define LP_WDT_WDT_EN_V 0x00000001U +#define LP_WDT_WDT_EN_S 31 + +/** LP_WDT_CONFIG1_REG register + * Configure the RWDT timeout of stage0 + */ +#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4) +/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000; + * Configure the timeout time for stage0. \\Measurement unit: LP\_DYN\_SLOW\_CLK + */ +#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_M (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S) +#define LP_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG0_HOLD_S 0 + +/** LP_WDT_CONFIG2_REG register + * Configure the RWDT timeout of stage1 + */ +#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8) +/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000; + * Configure the timeout time for stage1. \\Measurement unit: LP\_DYN\_SLOW\_CLK + */ +#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_M (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S) +#define LP_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG1_HOLD_S 0 + +/** LP_WDT_CONFIG3_REG register + * Configure the RWDT timeout of stage2 + */ +#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc) +/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095; + * Configure the timeout time for stage2. \\Measurement unit: LP\_DYN\_SLOW\_CLK + */ +#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_M (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S) +#define LP_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG2_HOLD_S 0 + +/** LP_WDT_CONFIG4_REG register + * Configure the RWDT timeout of stage3 + */ +#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10) +/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095; + * Configure the timeout time for stage3. \\Measurement unit: LP\_DYN\_SLOW\_CLK + */ +#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_M (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S) +#define LP_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU +#define LP_WDT_WDT_STG3_HOLD_S 0 + +/** LP_WDT_FEED_REG register + * Configure the feed function of RWDT + */ +#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x14) +/** LP_WDT_RTC_WDT_FEED : WT; bitpos: [31]; default: 0; + * Configure this bit to feed the RWDT.\\ 0: Invalid\\ 1: Feed RWDT + */ +#define LP_WDT_RTC_WDT_FEED (BIT(31)) +#define LP_WDT_RTC_WDT_FEED_M (LP_WDT_RTC_WDT_FEED_V << LP_WDT_RTC_WDT_FEED_S) +#define LP_WDT_RTC_WDT_FEED_V 0x00000001U +#define LP_WDT_RTC_WDT_FEED_S 31 + +/** LP_WDT_WPROTECT_REG register + * Configure the lock function of SWD + */ +#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x18) +/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0; + * Configure this field to lock or unlock RWDT`s configuration registers.\\0x50D83AA1: + * unlock the RWDT configuration registers.\\ Others value: Lock the RWDT + * configuration register which can`t be modified by software. + */ +#define LP_WDT_WDT_WKEY 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_M (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S) +#define LP_WDT_WDT_WKEY_V 0xFFFFFFFFU +#define LP_WDT_WDT_WKEY_S 0 + +/** LP_WDT_SWD_CONFIG_REG register + * Configure the SWD operation + */ +#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x1c) +/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0; + * Represents the SWD whether has generated the reset signal.\\0 :No \\1: Yes + */ +#define LP_WDT_SWD_RESET_FLAG (BIT(0)) +#define LP_WDT_SWD_RESET_FLAG_M (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S) +#define LP_WDT_SWD_RESET_FLAG_V 0x00000001U +#define LP_WDT_SWD_RESET_FLAG_S 0 +/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0; + * Configure this bit to enable to feed SWD automatically by hardware. \\0: Disable + * \\1: Enable + */ +#define LP_WDT_SWD_AUTO_FEED_EN (BIT(18)) +#define LP_WDT_SWD_AUTO_FEED_EN_M (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S) +#define LP_WDT_SWD_AUTO_FEED_EN_V 0x00000001U +#define LP_WDT_SWD_AUTO_FEED_EN_S 18 +/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0; + * Configure this bit to clear SWD reset flag.\\ 0:Invalid \\ 1: Clear the reset flag + */ +#define LP_WDT_SWD_RST_FLAG_CLR (BIT(19)) +#define LP_WDT_SWD_RST_FLAG_CLR_M (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S) +#define LP_WDT_SWD_RST_FLAG_CLR_V 0x00000001U +#define LP_WDT_SWD_RST_FLAG_CLR_S 19 +/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300; + * Configure the SWD signal length that output to analog circuit. \\ Measurement unit: + * LP\_DYN\_FAST\_CLK + */ +#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_M (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S) +#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU +#define LP_WDT_SWD_SIGNAL_WIDTH_S 20 +/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0; + * Configure this bit to disable the SWD.\\ 0: Enable the SWD\\ 1: Disable the SWD + */ +#define LP_WDT_SWD_DISABLE (BIT(30)) +#define LP_WDT_SWD_DISABLE_M (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S) +#define LP_WDT_SWD_DISABLE_V 0x00000001U +#define LP_WDT_SWD_DISABLE_S 30 +/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0; + * Configure this bit to feed the SWD.\\ 0: Invalid\\ 1: Feed SWD + */ +#define LP_WDT_SWD_FEED (BIT(31)) +#define LP_WDT_SWD_FEED_M (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S) +#define LP_WDT_SWD_FEED_V 0x00000001U +#define LP_WDT_SWD_FEED_S 31 + +/** LP_WDT_SWD_WPROTECT_REG register + * Configure the lock function of SWD + */ +#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x20) +/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0; + * Configure this field to lock or unlock SWD`s configuration registers.\\0x50D83AA1: + * unlock the RWDT configuration registers.\\ Others value: Lock the RWDT + * configuration register which can`t be modified by software. + */ +#define LP_WDT_SWD_WKEY 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_M (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S) +#define LP_WDT_SWD_WKEY_V 0xFFFFFFFFU +#define LP_WDT_SWD_WKEY_S 0 + +/** LP_WDT_INT_RAW_REG register + * Configure whether to generate timeout interrupt + */ +#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x24) +/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * Represents the SWD whether or not generates timeout interrupt.\\ 0:No \\1: Yes + */ +#define LP_WDT_SUPER_WDT_INT_RAW (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_RAW_M (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S) +#define LP_WDT_SUPER_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_RAW_S 30 +/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * Represents the RWDT whether or not generates timeout interrupt.\\ 0:No \\1: Yes + */ +#define LP_WDT_LP_WDT_INT_RAW (BIT(31)) +#define LP_WDT_LP_WDT_INT_RAW_M (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S) +#define LP_WDT_LP_WDT_INT_RAW_V 0x00000001U +#define LP_WDT_LP_WDT_INT_RAW_S 31 + +/** LP_WDT_INT_ST_REG register + * The interrupt status register of WDT + */ +#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x28) +/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0; + * Represents the SWD whether or not has generated and sent timeout interrupt to + * CPU.\\ 0:No \\1: Yes + */ +#define LP_WDT_SUPER_WDT_INT_ST (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ST_M (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S) +#define LP_WDT_SUPER_WDT_INT_ST_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ST_S 30 +/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0; + * Represents the RWDT whether or not has generated and sent timeout interrupt to + * CPU.\\ 0:No \\1: Yes + */ +#define LP_WDT_LP_WDT_INT_ST (BIT(31)) +#define LP_WDT_LP_WDT_INT_ST_M (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S) +#define LP_WDT_LP_WDT_INT_ST_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ST_S 31 + +/** LP_WDT_INT_ENA_REG register + * The interrupt enable register of WDT + */ +#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x2c) +/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0; + * Configure whether or not to enable the SWD to send timeout interrupt.\\0:Disable + * \\1:Enable + */ +#define LP_WDT_SUPER_WDT_INT_ENA (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_ENA_M (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S) +#define LP_WDT_SUPER_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_ENA_S 30 +/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0; + * Configure whether or not to enable the RWDT to send timeout interrupt.\\0:Disable + * \\1:Enable + */ +#define LP_WDT_LP_WDT_INT_ENA (BIT(31)) +#define LP_WDT_LP_WDT_INT_ENA_M (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S) +#define LP_WDT_LP_WDT_INT_ENA_V 0x00000001U +#define LP_WDT_LP_WDT_INT_ENA_S 31 + +/** LP_WDT_INT_CLR_REG register + * The interrupt clear register of WDT + */ +#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x30) +/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0; + * Configure whether to clear the timeout interrupt signal sent by SWD to CPU.\\0: + * No\\1: Yes + */ +#define LP_WDT_SUPER_WDT_INT_CLR (BIT(30)) +#define LP_WDT_SUPER_WDT_INT_CLR_M (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S) +#define LP_WDT_SUPER_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_SUPER_WDT_INT_CLR_S 30 +/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0; + * Configure whether to clear the timeout interrupt signal sent by RWDT to CPU.\\0: + * No\\1: Yes + */ +#define LP_WDT_LP_WDT_INT_CLR (BIT(31)) +#define LP_WDT_LP_WDT_INT_CLR_M (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S) +#define LP_WDT_LP_WDT_INT_CLR_V 0x00000001U +#define LP_WDT_LP_WDT_INT_CLR_S 31 + +/** LP_WDT_DATE_REG register + * need_des + */ +#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc) +/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 34676864; + * Version control register + */ +#define LP_WDT_LP_WDT_DATE 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_M (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S) +#define LP_WDT_LP_WDT_DATE_V 0x7FFFFFFFU +#define LP_WDT_LP_WDT_DATE_S 0 +/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0; + * Reserved + */ +#define LP_WDT_CLK_EN (BIT(31)) +#define LP_WDT_CLK_EN_M (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S) +#define LP_WDT_CLK_EN_V 0x00000001U +#define LP_WDT_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/lp_wdt_struct.h b/components/soc/esp32c61/include/soc/lp_wdt_struct.h new file mode 100644 index 0000000000..34c7041573 --- /dev/null +++ b/components/soc/esp32c61/include/soc/lp_wdt_struct.h @@ -0,0 +1,335 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of config0 register + * Configure the RWDT operation. + */ +typedef union { + struct { + /** wdt_chip_reset_width : R/W; bitpos: [7:0]; default: 20; + * need_des + */ + uint32_t wdt_chip_reset_width:8; + /** wdt_chip_reset_en : R/W; bitpos: [8]; default: 0; + * need_des + */ + uint32_t wdt_chip_reset_en:1; + /** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1; + * Configure whether or not pause RWDT when chip is in sleep mode.\\0:Enable + * \\1:Disable + */ + uint32_t wdt_pause_in_slp:1; + /** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0; + * Configure whether or not to enable RWDT to reset CPU.\\0:Disable \\1:Enable + */ + uint32_t wdt_appcpu_reset_en:1; + /** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t wdt_procpu_reset_en:1; + /** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1; + * Configure whether or not enable RWDT when chip is in SPI boot mode.\\0:Disable + * \\1:Enable + */ + uint32_t wdt_flashboot_mod_en:1; + /** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1; + * Configure the HP core reset time.\\Measurement unit: LP\_DYN\_FAST\_CLK + */ + uint32_t wdt_sys_reset_length:3; + /** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1; + * Configure the HP CPU reset time.\\Measurement unit: LP\_DYN\_FAST\_CLK + */ + uint32_t wdt_cpu_reset_length:3; + /** wdt_stg3 : R/W; bitpos: [21:19]; default: 0; + * Configure the timeout action of stage3.\\0: No operation \\1:Generate interrupt \\2 + * :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset. + */ + uint32_t wdt_stg3:3; + /** wdt_stg2 : R/W; bitpos: [24:22]; default: 0; + * Configure the timeout action of stage2.\\0: No operation \\1:Generate interrupt \\2 + * :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset. + */ + uint32_t wdt_stg2:3; + /** wdt_stg1 : R/W; bitpos: [27:25]; default: 0; + * Configure the timeout action of stage1.\\0: No operation \\1:Generate interrupt \\2 + * :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset. + */ + uint32_t wdt_stg1:3; + /** wdt_stg0 : R/W; bitpos: [30:28]; default: 0; + * Configure the timeout action of stage0.\\0: No operation \\1:Generate interrupt \\2 + * :Generate HP CPU reset \\3:Generate HP core reset \\4 :Generate system reset. + */ + uint32_t wdt_stg0:3; + /** wdt_en : R/W; bitpos: [31]; default: 0; + * Configure whether or not to enable RWDT.\\0:Disable \\1:Enable + */ + uint32_t wdt_en:1; + }; + uint32_t val; +} lp_wdt_config0_reg_t; + +/** Type of config1 register + * Configure the RWDT timeout of stage0 + */ +typedef union { + struct { + /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000; + * Configure the timeout time for stage0. \\Measurement unit: LP\_DYN\_SLOW\_CLK + */ + uint32_t wdt_stg0_hold:32; + }; + uint32_t val; +} lp_wdt_config1_reg_t; + +/** Type of config2 register + * Configure the RWDT timeout of stage1 + */ +typedef union { + struct { + /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000; + * Configure the timeout time for stage1. \\Measurement unit: LP\_DYN\_SLOW\_CLK + */ + uint32_t wdt_stg1_hold:32; + }; + uint32_t val; +} lp_wdt_config2_reg_t; + +/** Type of config3 register + * Configure the RWDT timeout of stage2 + */ +typedef union { + struct { + /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095; + * Configure the timeout time for stage2. \\Measurement unit: LP\_DYN\_SLOW\_CLK + */ + uint32_t wdt_stg2_hold:32; + }; + uint32_t val; +} lp_wdt_config3_reg_t; + +/** Type of config4 register + * Configure the RWDT timeout of stage3 + */ +typedef union { + struct { + /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095; + * Configure the timeout time for stage3. \\Measurement unit: LP\_DYN\_SLOW\_CLK + */ + uint32_t wdt_stg3_hold:32; + }; + uint32_t val; +} lp_wdt_config4_reg_t; + +/** Type of feed register + * Configure the feed function of RWDT + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** rtc_wdt_feed : WT; bitpos: [31]; default: 0; + * Configure this bit to feed the RWDT.\\ 0: Invalid\\ 1: Feed RWDT + */ + uint32_t rtc_wdt_feed:1; + }; + uint32_t val; +} lp_wdt_feed_reg_t; + +/** Type of wprotect register + * Configure the lock function of SWD + */ +typedef union { + struct { + /** wdt_wkey : R/W; bitpos: [31:0]; default: 0; + * Configure this field to lock or unlock RWDT`s configuration registers.\\0x50D83AA1: + * unlock the RWDT configuration registers.\\ Others value: Lock the RWDT + * configuration register which can`t be modified by software. + */ + uint32_t wdt_wkey:32; + }; + uint32_t val; +} lp_wdt_wprotect_reg_t; + +/** Type of swd_config register + * Configure the SWD operation + */ +typedef union { + struct { + /** swd_reset_flag : RO; bitpos: [0]; default: 0; + * Represents the SWD whether has generated the reset signal.\\0 :No \\1: Yes + */ + uint32_t swd_reset_flag:1; + uint32_t reserved_1:17; + /** swd_auto_feed_en : R/W; bitpos: [18]; default: 0; + * Configure this bit to enable to feed SWD automatically by hardware. \\0: Disable + * \\1: Enable + */ + uint32_t swd_auto_feed_en:1; + /** swd_rst_flag_clr : WT; bitpos: [19]; default: 0; + * Configure this bit to clear SWD reset flag.\\ 0:Invalid \\ 1: Clear the reset flag + */ + uint32_t swd_rst_flag_clr:1; + /** swd_signal_width : R/W; bitpos: [29:20]; default: 300; + * Configure the SWD signal length that output to analog circuit. \\ Measurement unit: + * LP\_DYN\_FAST\_CLK + */ + uint32_t swd_signal_width:10; + /** swd_disable : R/W; bitpos: [30]; default: 0; + * Configure this bit to disable the SWD.\\ 0: Enable the SWD\\ 1: Disable the SWD + */ + uint32_t swd_disable:1; + /** swd_feed : WT; bitpos: [31]; default: 0; + * Configure this bit to feed the SWD.\\ 0: Invalid\\ 1: Feed SWD + */ + uint32_t swd_feed:1; + }; + uint32_t val; +} lp_wdt_swd_config_reg_t; + +/** Type of swd_wprotect register + * Configure the lock function of SWD + */ +typedef union { + struct { + /** swd_wkey : R/W; bitpos: [31:0]; default: 0; + * Configure this field to lock or unlock SWD`s configuration registers.\\0x50D83AA1: + * unlock the RWDT configuration registers.\\ Others value: Lock the RWDT + * configuration register which can`t be modified by software. + */ + uint32_t swd_wkey:32; + }; + uint32_t val; +} lp_wdt_swd_wprotect_reg_t; + +/** Type of int_raw register + * Configure whether to generate timeout interrupt + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * Represents the SWD whether or not generates timeout interrupt.\\ 0:No \\1: Yes + */ + uint32_t super_wdt_int_raw:1; + /** lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * Represents the RWDT whether or not generates timeout interrupt.\\ 0:No \\1: Yes + */ + uint32_t lp_wdt_int_raw:1; + }; + uint32_t val; +} lp_wdt_int_raw_reg_t; + +/** Type of int_st register + * The interrupt status register of WDT + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_st : RO; bitpos: [30]; default: 0; + * Represents the SWD whether or not has generated and sent timeout interrupt to + * CPU.\\ 0:No \\1: Yes + */ + uint32_t super_wdt_int_st:1; + /** lp_wdt_int_st : RO; bitpos: [31]; default: 0; + * Represents the RWDT whether or not has generated and sent timeout interrupt to + * CPU.\\ 0:No \\1: Yes + */ + uint32_t lp_wdt_int_st:1; + }; + uint32_t val; +} lp_wdt_int_st_reg_t; + +/** Type of int_ena register + * The interrupt enable register of WDT + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_ena : R/W; bitpos: [30]; default: 0; + * Configure whether or not to enable the SWD to send timeout interrupt.\\0:Disable + * \\1:Enable + */ + uint32_t super_wdt_int_ena:1; + /** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0; + * Configure whether or not to enable the RWDT to send timeout interrupt.\\0:Disable + * \\1:Enable + */ + uint32_t lp_wdt_int_ena:1; + }; + uint32_t val; +} lp_wdt_int_ena_reg_t; + +/** Type of int_clr register + * The interrupt clear register of WDT + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** super_wdt_int_clr : WT; bitpos: [30]; default: 0; + * Configure whether to clear the timeout interrupt signal sent by SWD to CPU.\\0: + * No\\1: Yes + */ + uint32_t super_wdt_int_clr:1; + /** lp_wdt_int_clr : WT; bitpos: [31]; default: 0; + * Configure whether to clear the timeout interrupt signal sent by RWDT to CPU.\\0: + * No\\1: Yes + */ + uint32_t lp_wdt_int_clr:1; + }; + uint32_t val; +} lp_wdt_int_clr_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lp_wdt_date : R/W; bitpos: [30:0]; default: 34676864; + * Version control register + */ + uint32_t lp_wdt_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * Reserved + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lp_wdt_date_reg_t; + + +typedef struct { + volatile lp_wdt_config0_reg_t config0; + volatile lp_wdt_config1_reg_t config1; + volatile lp_wdt_config2_reg_t config2; + volatile lp_wdt_config3_reg_t config3; + volatile lp_wdt_config4_reg_t config4; + volatile lp_wdt_feed_reg_t feed; + volatile lp_wdt_wprotect_reg_t wprotect; + volatile lp_wdt_swd_config_reg_t swd_config; + volatile lp_wdt_swd_wprotect_reg_t swd_wprotect; + volatile lp_wdt_int_raw_reg_t int_raw; + volatile lp_wdt_int_st_reg_t int_st; + volatile lp_wdt_int_ena_reg_t int_ena; + volatile lp_wdt_int_clr_reg_t int_clr; + uint32_t reserved_034[242]; + volatile lp_wdt_date_reg_t date; +} lp_wdt_dev_t; + +extern lp_wdt_dev_t LP_WDT; + +#ifndef __cplusplus +_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/lpperi_reg.h b/components/soc/esp32c61/include/soc/lpperi_reg.h new file mode 100644 index 0000000000..6176a02ebc --- /dev/null +++ b/components/soc/esp32c61/include/soc/lpperi_reg.h @@ -0,0 +1,260 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** LPPERI_CLK_EN_REG register + * need_des + */ +#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0) +/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define LPPERI_RNG_CK_EN (BIT(24)) +#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S) +#define LPPERI_RNG_CK_EN_V 0x00000001U +#define LPPERI_RNG_CK_EN_S 24 +/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1; + * need_des + */ +#define LPPERI_OTP_DBG_CK_EN (BIT(25)) +#define LPPERI_OTP_DBG_CK_EN_M (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S) +#define LPPERI_OTP_DBG_CK_EN_V 0x00000001U +#define LPPERI_OTP_DBG_CK_EN_S 25 +/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define LPPERI_LP_IO_CK_EN (BIT(27)) +#define LPPERI_LP_IO_CK_EN_M (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S) +#define LPPERI_LP_IO_CK_EN_V 0x00000001U +#define LPPERI_LP_IO_CK_EN_S 27 +/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define LPPERI_EFUSE_CK_EN (BIT(30)) +#define LPPERI_EFUSE_CK_EN_M (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S) +#define LPPERI_EFUSE_CK_EN_V 0x00000001U +#define LPPERI_EFUSE_CK_EN_S 30 +/** LPPERI_LP_CPU_CK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_LP_CPU_CK_EN (BIT(31)) +#define LPPERI_LP_CPU_CK_EN_M (LPPERI_LP_CPU_CK_EN_V << LPPERI_LP_CPU_CK_EN_S) +#define LPPERI_LP_CPU_CK_EN_V 0x00000001U +#define LPPERI_LP_CPU_CK_EN_S 31 + +/** LPPERI_RESET_EN_REG register + * need_des + */ +#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4) +/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0; + * need_des + */ +#define LPPERI_BUS_RESET_EN (BIT(23)) +#define LPPERI_BUS_RESET_EN_M (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S) +#define LPPERI_BUS_RESET_EN_V 0x00000001U +#define LPPERI_BUS_RESET_EN_S 23 +/** LPPERI_LP_RNG_RESET_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define LPPERI_LP_RNG_RESET_EN (BIT(24)) +#define LPPERI_LP_RNG_RESET_EN_M (LPPERI_LP_RNG_RESET_EN_V << LPPERI_LP_RNG_RESET_EN_S) +#define LPPERI_LP_RNG_RESET_EN_V 0x00000001U +#define LPPERI_LP_RNG_RESET_EN_S 24 +/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define LPPERI_OTP_DBG_RESET_EN (BIT(25)) +#define LPPERI_OTP_DBG_RESET_EN_M (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S) +#define LPPERI_OTP_DBG_RESET_EN_V 0x00000001U +#define LPPERI_OTP_DBG_RESET_EN_S 25 +/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define LPPERI_LP_IO_RESET_EN (BIT(27)) +#define LPPERI_LP_IO_RESET_EN_M (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S) +#define LPPERI_LP_IO_RESET_EN_V 0x00000001U +#define LPPERI_LP_IO_RESET_EN_S 27 +/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_EFUSE_RESET_EN (BIT(30)) +#define LPPERI_EFUSE_RESET_EN_M (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S) +#define LPPERI_EFUSE_RESET_EN_V 0x00000001U +#define LPPERI_EFUSE_RESET_EN_S 30 +/** LPPERI_LP_CPU_RESET_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_LP_CPU_RESET_EN (BIT(31)) +#define LPPERI_LP_CPU_RESET_EN_M (LPPERI_LP_CPU_RESET_EN_V << LPPERI_LP_CPU_RESET_EN_S) +#define LPPERI_LP_CPU_RESET_EN_V 0x00000001U +#define LPPERI_LP_CPU_RESET_EN_S 31 + +/** LPPERI_RNG_DATA_REG register + * need_des + */ +#define LPPERI_RNG_DATA_REG (DR_REG_LPPERI_BASE + 0x8) +/** LPPERI_RND_DATA : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LPPERI_RND_DATA 0xFFFFFFFFU +#define LPPERI_RND_DATA_M (LPPERI_RND_DATA_V << LPPERI_RND_DATA_S) +#define LPPERI_RND_DATA_V 0xFFFFFFFFU +#define LPPERI_RND_DATA_S 0 + +/** LPPERI_CPU_REG register + * need_des + */ +#define LPPERI_CPU_REG (DR_REG_LPPERI_BASE + 0xc) +/** LPPERI_LPCORE_DBGM_UNAVALIABLE : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LPCORE_DBGM_UNAVALIABLE (BIT(31)) +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_M (LPPERI_LPCORE_DBGM_UNAVALIABLE_V << LPPERI_LPCORE_DBGM_UNAVALIABLE_S) +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_V 0x00000001U +#define LPPERI_LPCORE_DBGM_UNAVALIABLE_S 31 + +/** LPPERI_BUS_TIMEOUT_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_REG (DR_REG_LPPERI_BASE + 0x10) +/** LPPERI_LP_PERI_TIMEOUT_THRES : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_THRES 0x0000FFFFU +#define LPPERI_LP_PERI_TIMEOUT_THRES_M (LPPERI_LP_PERI_TIMEOUT_THRES_V << LPPERI_LP_PERI_TIMEOUT_THRES_S) +#define LPPERI_LP_PERI_TIMEOUT_THRES_V 0x0000FFFFU +#define LPPERI_LP_PERI_TIMEOUT_THRES_S 14 +/** LPPERI_LP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR (BIT(30)) +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_M (LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V << LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S) +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U +#define LPPERI_LP_PERI_TIMEOUT_INT_CLEAR_S 30 +/** LPPERI_LP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN (BIT(31)) +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_M (LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V << LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S) +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U +#define LPPERI_LP_PERI_TIMEOUT_PROTECT_EN_S 31 + +/** LPPERI_BUS_TIMEOUT_ADDR_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_ADDR_REG (DR_REG_LPPERI_BASE + 0x14) +/** LPPERI_LP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU +#define LPPERI_LP_PERI_TIMEOUT_ADDR_M (LPPERI_LP_PERI_TIMEOUT_ADDR_V << LPPERI_LP_PERI_TIMEOUT_ADDR_S) +#define LPPERI_LP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU +#define LPPERI_LP_PERI_TIMEOUT_ADDR_S 0 + +/** LPPERI_BUS_TIMEOUT_UID_REG register + * need_des + */ +#define LPPERI_BUS_TIMEOUT_UID_REG (DR_REG_LPPERI_BASE + 0x18) +/** LPPERI_LP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; + * need_des + */ +#define LPPERI_LP_PERI_TIMEOUT_UID 0x0000007FU +#define LPPERI_LP_PERI_TIMEOUT_UID_M (LPPERI_LP_PERI_TIMEOUT_UID_V << LPPERI_LP_PERI_TIMEOUT_UID_S) +#define LPPERI_LP_PERI_TIMEOUT_UID_V 0x0000007FU +#define LPPERI_LP_PERI_TIMEOUT_UID_S 0 + +/** LPPERI_INTERRUPT_SOURCE_REG register + * need_des + */ +#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x20) +/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, reserved, reserved, lp_io_int + */ +#define LPPERI_LP_INTERRUPT_SOURCE 0x0000003FU +#define LPPERI_LP_INTERRUPT_SOURCE_M (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S) +#define LPPERI_LP_INTERRUPT_SOURCE_V 0x0000003FU +#define LPPERI_LP_INTERRUPT_SOURCE_S 0 + +/** LPPERI_RNG_CFG_REG register + * need_des + */ +#define LPPERI_RNG_CFG_REG (DR_REG_LPPERI_BASE + 0x24) +/** LPPERI_RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0; + * need des + */ +#define LPPERI_RNG_SAMPLE_ENABLE (BIT(0)) +#define LPPERI_RNG_SAMPLE_ENABLE_M (LPPERI_RNG_SAMPLE_ENABLE_V << LPPERI_RNG_SAMPLE_ENABLE_S) +#define LPPERI_RNG_SAMPLE_ENABLE_V 0x00000001U +#define LPPERI_RNG_SAMPLE_ENABLE_S 0 +/** LPPERI_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 255; + * need des + */ +#define LPPERI_RNG_TIMER_PSCALE 0x000000FFU +#define LPPERI_RNG_TIMER_PSCALE_M (LPPERI_RNG_TIMER_PSCALE_V << LPPERI_RNG_TIMER_PSCALE_S) +#define LPPERI_RNG_TIMER_PSCALE_V 0x000000FFU +#define LPPERI_RNG_TIMER_PSCALE_S 1 +/** LPPERI_RNG_TIMER_EN : R/W; bitpos: [9]; default: 1; + * need des + */ +#define LPPERI_RNG_TIMER_EN (BIT(9)) +#define LPPERI_RNG_TIMER_EN_M (LPPERI_RNG_TIMER_EN_V << LPPERI_RNG_TIMER_EN_S) +#define LPPERI_RNG_TIMER_EN_V 0x00000001U +#define LPPERI_RNG_TIMER_EN_S 9 +/** LPPERI_RTC_TIMER_EN : R/W; bitpos: [11:10]; default: 3; + * need des + */ +#define LPPERI_RTC_TIMER_EN 0x00000003U +#define LPPERI_RTC_TIMER_EN_M (LPPERI_RTC_TIMER_EN_V << LPPERI_RTC_TIMER_EN_S) +#define LPPERI_RTC_TIMER_EN_V 0x00000003U +#define LPPERI_RTC_TIMER_EN_S 10 +/** LPPERI_RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0; + * need des + */ +#define LPPERI_RNG_SAMPLE_CNT 0x000000FFU +#define LPPERI_RNG_SAMPLE_CNT_M (LPPERI_RNG_SAMPLE_CNT_V << LPPERI_RNG_SAMPLE_CNT_S) +#define LPPERI_RNG_SAMPLE_CNT_V 0x000000FFU +#define LPPERI_RNG_SAMPLE_CNT_S 24 + +/** LPPERI_RNG_DATA_SYNC_REG register + * need_des + */ +#define LPPERI_RNG_DATA_SYNC_REG (DR_REG_LPPERI_BASE + 0x28) +/** LPPERI_RND_SYNC_DATA : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define LPPERI_RND_SYNC_DATA 0xFFFFFFFFU +#define LPPERI_RND_SYNC_DATA_M (LPPERI_RND_SYNC_DATA_V << LPPERI_RND_SYNC_DATA_S) +#define LPPERI_RND_SYNC_DATA_V 0xFFFFFFFFU +#define LPPERI_RND_SYNC_DATA_S 0 + +/** LPPERI_DATE_REG register + * need_des + */ +#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc) +/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 37753168; + * need_des + */ +#define LPPERI_LPPERI_DATE 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S) +#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU +#define LPPERI_LPPERI_DATE_S 0 +/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define LPPERI_CLK_EN (BIT(31)) +#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S) +#define LPPERI_CLK_EN_V 0x00000001U +#define LPPERI_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/lpperi_struct.h b/components/soc/esp32c61/include/soc/lpperi_struct.h new file mode 100644 index 0000000000..692fd83678 --- /dev/null +++ b/components/soc/esp32c61/include/soc/lpperi_struct.h @@ -0,0 +1,259 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of clk_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** rng_ck_en : R/W; bitpos: [24]; default: 1; + * need_des + */ + uint32_t rng_ck_en:1; + /** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1; + * need_des + */ + uint32_t otp_dbg_ck_en:1; + uint32_t reserved_26:1; + /** lp_io_ck_en : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t lp_io_ck_en:1; + uint32_t reserved_28:2; + /** efuse_ck_en : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t efuse_ck_en:1; + /** lp_cpu_ck_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_ck_en:1; + }; + uint32_t val; +} lpperi_clk_en_reg_t; + +/** Type of reset_en register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:23; + /** bus_reset_en : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t bus_reset_en:1; + /** lp_rng_reset_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t lp_rng_reset_en:1; + /** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t otp_dbg_reset_en:1; + uint32_t reserved_26:1; + /** lp_io_reset_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_io_reset_en:1; + uint32_t reserved_28:2; + /** efuse_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t efuse_reset_en:1; + /** lp_cpu_reset_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_reset_en:1; + }; + uint32_t val; +} lpperi_reset_en_reg_t; + +/** Type of rng_data register + * need_des + */ +typedef union { + struct { + /** rnd_data : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t rnd_data:32; + }; + uint32_t val; +} lpperi_rng_data_reg_t; + +/** Type of cpu register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lpcore_dbgm_unavaliable : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lpcore_dbgm_unavaliable:1; + }; + uint32_t val; +} lpperi_cpu_reg_t; + +/** Type of bus_timeout register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:14; + /** lp_peri_timeout_thres : R/W; bitpos: [29:14]; default: 65535; + * need_des + */ + uint32_t lp_peri_timeout_thres:16; + /** lp_peri_timeout_int_clear : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_int_clear:1; + /** lp_peri_timeout_protect_en : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_peri_timeout_protect_en:1; + }; + uint32_t val; +} lpperi_bus_timeout_reg_t; + +/** Type of bus_timeout_addr register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_addr:32; + }; + uint32_t val; +} lpperi_bus_timeout_addr_reg_t; + +/** Type of bus_timeout_uid register + * need_des + */ +typedef union { + struct { + /** lp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + * need_des + */ + uint32_t lp_peri_timeout_uid:7; + uint32_t reserved_7:25; + }; + uint32_t val; +} lpperi_bus_timeout_uid_reg_t; + +/** Type of interrupt_source register + * need_des + */ +typedef union { + struct { + /** lp_interrupt_source : RO; bitpos: [5:0]; default: 0; + * BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, reserved, reserved, lp_io_int + */ + uint32_t lp_interrupt_source:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} lpperi_interrupt_source_reg_t; + +/** Type of rng_cfg register + * need_des + */ +typedef union { + struct { + /** rng_sample_enable : R/W; bitpos: [0]; default: 0; + * need des + */ + uint32_t rng_sample_enable:1; + /** rng_timer_pscale : R/W; bitpos: [8:1]; default: 255; + * need des + */ + uint32_t rng_timer_pscale:8; + /** rng_timer_en : R/W; bitpos: [9]; default: 1; + * need des + */ + uint32_t rng_timer_en:1; + /** rtc_timer_en : R/W; bitpos: [11:10]; default: 3; + * need des + */ + uint32_t rtc_timer_en:2; + uint32_t reserved_12:12; + /** rng_sample_cnt : RO; bitpos: [31:24]; default: 0; + * need des + */ + uint32_t rng_sample_cnt:8; + }; + uint32_t val; +} lpperi_rng_cfg_reg_t; + +/** Type of rng_data_sync register + * need_des + */ +typedef union { + struct { + /** rnd_sync_data : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t rnd_sync_data:32; + }; + uint32_t val; +} lpperi_rng_data_sync_reg_t; + + +/** Group: Version register */ +/** Type of date register + * need_des + */ +typedef union { + struct { + /** lpperi_date : R/W; bitpos: [30:0]; default: 37753168; + * need_des + */ + uint32_t lpperi_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} lpperi_date_reg_t; + + +typedef struct { + volatile lpperi_clk_en_reg_t clk_en; + volatile lpperi_reset_en_reg_t reset_en; + volatile lpperi_rng_data_reg_t rng_data; + volatile lpperi_cpu_reg_t cpu; + volatile lpperi_bus_timeout_reg_t bus_timeout; + volatile lpperi_bus_timeout_addr_reg_t bus_timeout_addr; + volatile lpperi_bus_timeout_uid_reg_t bus_timeout_uid; + uint32_t reserved_01c; + volatile lpperi_interrupt_source_reg_t interrupt_source; + volatile lpperi_rng_cfg_reg_t rng_cfg; + volatile lpperi_rng_data_sync_reg_t rng_data_sync; + uint32_t reserved_02c[244]; + volatile lpperi_date_reg_t date; +} lpperi_dev_t; + +extern lpperi_dev_t LPPERI; + +#ifndef __cplusplus +_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/pau_reg.h b/components/soc/esp32c61/include/soc/pau_reg.h new file mode 100644 index 0000000000..34ac60380d --- /dev/null +++ b/components/soc/esp32c61/include/soc/pau_reg.h @@ -0,0 +1,332 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PAU_REGDMA_CONF_REG register + * Peri backup control register + */ +#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0) +/** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0; + * backup error type + */ +#define PAU_FLOW_ERR 0x00000007U +#define PAU_FLOW_ERR_M (PAU_FLOW_ERR_V << PAU_FLOW_ERR_S) +#define PAU_FLOW_ERR_V 0x00000007U +#define PAU_FLOW_ERR_S 0 +/** PAU_START : WT; bitpos: [3]; default: 0; + * backup start signal + */ +#define PAU_START (BIT(3)) +#define PAU_START_M (PAU_START_V << PAU_START_S) +#define PAU_START_V 0x00000001U +#define PAU_START_S 3 +/** PAU_TO_MEM : R/W; bitpos: [4]; default: 0; + * backup direction(reg to mem / mem to reg) + */ +#define PAU_TO_MEM (BIT(4)) +#define PAU_TO_MEM_M (PAU_TO_MEM_V << PAU_TO_MEM_S) +#define PAU_TO_MEM_V 0x00000001U +#define PAU_TO_MEM_S 4 +/** PAU_LINK_SEL : R/W; bitpos: [6:5]; default: 0; + * Link select + */ +#define PAU_LINK_SEL 0x00000003U +#define PAU_LINK_SEL_M (PAU_LINK_SEL_V << PAU_LINK_SEL_S) +#define PAU_LINK_SEL_V 0x00000003U +#define PAU_LINK_SEL_S 5 +/** PAU_START_MAC : WT; bitpos: [7]; default: 0; + * mac sw backup start signal + */ +#define PAU_START_MAC (BIT(7)) +#define PAU_START_MAC_M (PAU_START_MAC_V << PAU_START_MAC_S) +#define PAU_START_MAC_V 0x00000001U +#define PAU_START_MAC_S 7 +/** PAU_TO_MEM_MAC : R/W; bitpos: [8]; default: 0; + * mac sw backup direction(reg to mem / mem to reg) + */ +#define PAU_TO_MEM_MAC (BIT(8)) +#define PAU_TO_MEM_MAC_M (PAU_TO_MEM_MAC_V << PAU_TO_MEM_MAC_S) +#define PAU_TO_MEM_MAC_V 0x00000001U +#define PAU_TO_MEM_MAC_S 8 +/** PAU_SEL_MAC : R/W; bitpos: [9]; default: 0; + * mac hw/sw select + */ +#define PAU_SEL_MAC (BIT(9)) +#define PAU_SEL_MAC_M (PAU_SEL_MAC_V << PAU_SEL_MAC_S) +#define PAU_SEL_MAC_V 0x00000001U +#define PAU_SEL_MAC_S 9 + +/** PAU_REGDMA_CLK_CONF_REG register + * Clock control register + */ +#define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4) +/** PAU_CLK_EN : R/W; bitpos: [0]; default: 0; + * clock enable + */ +#define PAU_CLK_EN (BIT(0)) +#define PAU_CLK_EN_M (PAU_CLK_EN_V << PAU_CLK_EN_S) +#define PAU_CLK_EN_V 0x00000001U +#define PAU_CLK_EN_S 0 + +/** PAU_REGDMA_ETM_CTRL_REG register + * ETM start ctrl reg + */ +#define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8) +/** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0; + * etm_start_0 reg + */ +#define PAU_ETM_START_0 (BIT(0)) +#define PAU_ETM_START_0_M (PAU_ETM_START_0_V << PAU_ETM_START_0_S) +#define PAU_ETM_START_0_V 0x00000001U +#define PAU_ETM_START_0_S 0 +/** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0; + * etm_start_1 reg + */ +#define PAU_ETM_START_1 (BIT(1)) +#define PAU_ETM_START_1_M (PAU_ETM_START_1_V << PAU_ETM_START_1_S) +#define PAU_ETM_START_1_V 0x00000001U +#define PAU_ETM_START_1_S 1 +/** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0; + * etm_start_2 reg + */ +#define PAU_ETM_START_2 (BIT(2)) +#define PAU_ETM_START_2_M (PAU_ETM_START_2_V << PAU_ETM_START_2_S) +#define PAU_ETM_START_2_V 0x00000001U +#define PAU_ETM_START_2_S 2 +/** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0; + * etm_start_3 reg + */ +#define PAU_ETM_START_3 (BIT(3)) +#define PAU_ETM_START_3_M (PAU_ETM_START_3_V << PAU_ETM_START_3_S) +#define PAU_ETM_START_3_V 0x00000001U +#define PAU_ETM_START_3_S 3 + +/** PAU_REGDMA_LINK_0_ADDR_REG register + * link_0_addr + */ +#define PAU_REGDMA_LINK_0_ADDR_REG (DR_REG_PAU_BASE + 0xc) +/** PAU_LINK_ADDR_0 : R/W; bitpos: [31:0]; default: 0; + * link_0_addr reg + */ +#define PAU_LINK_ADDR_0 0xFFFFFFFFU +#define PAU_LINK_ADDR_0_M (PAU_LINK_ADDR_0_V << PAU_LINK_ADDR_0_S) +#define PAU_LINK_ADDR_0_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_0_S 0 + +/** PAU_REGDMA_LINK_1_ADDR_REG register + * Link_1_addr + */ +#define PAU_REGDMA_LINK_1_ADDR_REG (DR_REG_PAU_BASE + 0x10) +/** PAU_LINK_ADDR_1 : R/W; bitpos: [31:0]; default: 0; + * Link_1_addr reg + */ +#define PAU_LINK_ADDR_1 0xFFFFFFFFU +#define PAU_LINK_ADDR_1_M (PAU_LINK_ADDR_1_V << PAU_LINK_ADDR_1_S) +#define PAU_LINK_ADDR_1_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_1_S 0 + +/** PAU_REGDMA_LINK_2_ADDR_REG register + * Link_2_addr + */ +#define PAU_REGDMA_LINK_2_ADDR_REG (DR_REG_PAU_BASE + 0x14) +/** PAU_LINK_ADDR_2 : R/W; bitpos: [31:0]; default: 0; + * Link_2_addr reg + */ +#define PAU_LINK_ADDR_2 0xFFFFFFFFU +#define PAU_LINK_ADDR_2_M (PAU_LINK_ADDR_2_V << PAU_LINK_ADDR_2_S) +#define PAU_LINK_ADDR_2_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_2_S 0 + +/** PAU_REGDMA_LINK_3_ADDR_REG register + * Link_3_addr + */ +#define PAU_REGDMA_LINK_3_ADDR_REG (DR_REG_PAU_BASE + 0x18) +/** PAU_LINK_ADDR_3 : R/W; bitpos: [31:0]; default: 0; + * Link_3_addr reg + */ +#define PAU_LINK_ADDR_3 0xFFFFFFFFU +#define PAU_LINK_ADDR_3_M (PAU_LINK_ADDR_3_V << PAU_LINK_ADDR_3_S) +#define PAU_LINK_ADDR_3_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_3_S 0 + +/** PAU_REGDMA_LINK_MAC_ADDR_REG register + * Link_mac_addr + */ +#define PAU_REGDMA_LINK_MAC_ADDR_REG (DR_REG_PAU_BASE + 0x1c) +/** PAU_LINK_ADDR_MAC : R/W; bitpos: [31:0]; default: 0; + * Link_mac_addr reg + */ +#define PAU_LINK_ADDR_MAC 0xFFFFFFFFU +#define PAU_LINK_ADDR_MAC_M (PAU_LINK_ADDR_MAC_V << PAU_LINK_ADDR_MAC_S) +#define PAU_LINK_ADDR_MAC_V 0xFFFFFFFFU +#define PAU_LINK_ADDR_MAC_S 0 + +/** PAU_REGDMA_CURRENT_LINK_ADDR_REG register + * current link addr + */ +#define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0x20) +/** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0; + * current link addr reg + */ +#define PAU_CURRENT_LINK_ADDR 0xFFFFFFFFU +#define PAU_CURRENT_LINK_ADDR_M (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S) +#define PAU_CURRENT_LINK_ADDR_V 0xFFFFFFFFU +#define PAU_CURRENT_LINK_ADDR_S 0 + +/** PAU_REGDMA_BACKUP_ADDR_REG register + * Backup addr + */ +#define PAU_REGDMA_BACKUP_ADDR_REG (DR_REG_PAU_BASE + 0x24) +/** PAU_BACKUP_ADDR : RO; bitpos: [31:0]; default: 0; + * backup addr reg + */ +#define PAU_BACKUP_ADDR 0xFFFFFFFFU +#define PAU_BACKUP_ADDR_M (PAU_BACKUP_ADDR_V << PAU_BACKUP_ADDR_S) +#define PAU_BACKUP_ADDR_V 0xFFFFFFFFU +#define PAU_BACKUP_ADDR_S 0 + +/** PAU_REGDMA_MEM_ADDR_REG register + * mem addr + */ +#define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x28) +/** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0; + * mem addr reg + */ +#define PAU_MEM_ADDR 0xFFFFFFFFU +#define PAU_MEM_ADDR_M (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S) +#define PAU_MEM_ADDR_V 0xFFFFFFFFU +#define PAU_MEM_ADDR_S 0 + +/** PAU_REGDMA_BKP_CONF_REG register + * backup config + */ +#define PAU_REGDMA_BKP_CONF_REG (DR_REG_PAU_BASE + 0x2c) +/** PAU_READ_INTERVAL : R/W; bitpos: [6:0]; default: 32; + * Link read_interval + */ +#define PAU_READ_INTERVAL 0x0000007FU +#define PAU_READ_INTERVAL_M (PAU_READ_INTERVAL_V << PAU_READ_INTERVAL_S) +#define PAU_READ_INTERVAL_V 0x0000007FU +#define PAU_READ_INTERVAL_S 0 +/** PAU_LINK_TOUT_THRES : R/W; bitpos: [16:7]; default: 50; + * link wait timeout threshold + */ +#define PAU_LINK_TOUT_THRES 0x000003FFU +#define PAU_LINK_TOUT_THRES_M (PAU_LINK_TOUT_THRES_V << PAU_LINK_TOUT_THRES_S) +#define PAU_LINK_TOUT_THRES_V 0x000003FFU +#define PAU_LINK_TOUT_THRES_S 7 +/** PAU_BURST_LIMIT : R/W; bitpos: [21:17]; default: 8; + * burst limit + */ +#define PAU_BURST_LIMIT 0x0000001FU +#define PAU_BURST_LIMIT_M (PAU_BURST_LIMIT_V << PAU_BURST_LIMIT_S) +#define PAU_BURST_LIMIT_V 0x0000001FU +#define PAU_BURST_LIMIT_S 17 +/** PAU_BACKUP_TOUT_THRES : R/W; bitpos: [31:22]; default: 500; + * Backup timeout threshold + */ +#define PAU_BACKUP_TOUT_THRES 0x000003FFU +#define PAU_BACKUP_TOUT_THRES_M (PAU_BACKUP_TOUT_THRES_V << PAU_BACKUP_TOUT_THRES_S) +#define PAU_BACKUP_TOUT_THRES_V 0x000003FFU +#define PAU_BACKUP_TOUT_THRES_S 22 + +/** PAU_INT_ENA_REG register + * Read only register for error and done + */ +#define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x30) +/** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_ENA (BIT(0)) +#define PAU_DONE_INT_ENA_M (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S) +#define PAU_DONE_INT_ENA_V 0x00000001U +#define PAU_DONE_INT_ENA_S 0 +/** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_ENA (BIT(1)) +#define PAU_ERROR_INT_ENA_M (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S) +#define PAU_ERROR_INT_ENA_V 0x00000001U +#define PAU_ERROR_INT_ENA_S 1 + +/** PAU_INT_RAW_REG register + * Read only register for error and done + */ +#define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x34) +/** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_RAW (BIT(0)) +#define PAU_DONE_INT_RAW_M (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S) +#define PAU_DONE_INT_RAW_V 0x00000001U +#define PAU_DONE_INT_RAW_S 0 +/** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_RAW (BIT(1)) +#define PAU_ERROR_INT_RAW_M (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S) +#define PAU_ERROR_INT_RAW_V 0x00000001U +#define PAU_ERROR_INT_RAW_S 1 + +/** PAU_INT_CLR_REG register + * Read only register for error and done + */ +#define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x38) +/** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_CLR (BIT(0)) +#define PAU_DONE_INT_CLR_M (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S) +#define PAU_DONE_INT_CLR_V 0x00000001U +#define PAU_DONE_INT_CLR_S 0 +/** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_CLR (BIT(1)) +#define PAU_ERROR_INT_CLR_M (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S) +#define PAU_ERROR_INT_CLR_V 0x00000001U +#define PAU_ERROR_INT_CLR_S 1 + +/** PAU_INT_ST_REG register + * Read only register for error and done + */ +#define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x3c) +/** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * backup done flag + */ +#define PAU_DONE_INT_ST (BIT(0)) +#define PAU_DONE_INT_ST_M (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S) +#define PAU_DONE_INT_ST_V 0x00000001U +#define PAU_DONE_INT_ST_S 0 +/** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0; + * error flag + */ +#define PAU_ERROR_INT_ST (BIT(1)) +#define PAU_ERROR_INT_ST_M (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S) +#define PAU_ERROR_INT_ST_V 0x00000001U +#define PAU_ERROR_INT_ST_S 1 + +/** PAU_DATE_REG register + * Date register. + */ +#define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc) +/** PAU_DATE : R/W; bitpos: [27:0]; default: 36708608; + * REGDMA date information/ REGDMA version information. + */ +#define PAU_DATE 0x0FFFFFFFU +#define PAU_DATE_M (PAU_DATE_V << PAU_DATE_S) +#define PAU_DATE_V 0x0FFFFFFFU +#define PAU_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/pau_struct.h b/components/soc/esp32c61/include/soc/pau_struct.h new file mode 100644 index 0000000000..5408206bcd --- /dev/null +++ b/components/soc/esp32c61/include/soc/pau_struct.h @@ -0,0 +1,339 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Register */ +/** Type of regdma_conf register + * Peri backup control register + */ +typedef union { + struct { + /** flow_err : RO; bitpos: [2:0]; default: 0; + * backup error type + */ + uint32_t flow_err:3; + /** start : WT; bitpos: [3]; default: 0; + * backup start signal + */ + uint32_t start:1; + /** to_mem : R/W; bitpos: [4]; default: 0; + * backup direction(reg to mem / mem to reg) + */ + uint32_t to_mem:1; + /** link_sel : R/W; bitpos: [6:5]; default: 0; + * Link select + */ + uint32_t link_sel:2; + /** start_mac : WT; bitpos: [7]; default: 0; + * mac sw backup start signal + */ + uint32_t start_mac:1; + /** to_mem_mac : R/W; bitpos: [8]; default: 0; + * mac sw backup direction(reg to mem / mem to reg) + */ + uint32_t to_mem_mac:1; + /** sel_mac : R/W; bitpos: [9]; default: 0; + * mac hw/sw select + */ + uint32_t sel_mac:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} pau_regdma_conf_reg_t; + +/** Type of regdma_clk_conf register + * Clock control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * clock enable + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} pau_regdma_clk_conf_reg_t; + +/** Type of regdma_etm_ctrl register + * ETM start ctrl reg + */ +typedef union { + struct { + /** etm_start_0 : WT; bitpos: [0]; default: 0; + * etm_start_0 reg + */ + uint32_t etm_start_0:1; + /** etm_start_1 : WT; bitpos: [1]; default: 0; + * etm_start_1 reg + */ + uint32_t etm_start_1:1; + /** etm_start_2 : WT; bitpos: [2]; default: 0; + * etm_start_2 reg + */ + uint32_t etm_start_2:1; + /** etm_start_3 : WT; bitpos: [3]; default: 0; + * etm_start_3 reg + */ + uint32_t etm_start_3:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} pau_regdma_etm_ctrl_reg_t; + +/** Type of regdma_link_0_addr register + * link_0_addr + */ +typedef union { + struct { + /** link_addr_0 : R/W; bitpos: [31:0]; default: 0; + * link_0_addr reg + */ + uint32_t link_addr_0:32; + }; + uint32_t val; +} pau_regdma_link_0_addr_reg_t; + +/** Type of regdma_link_1_addr register + * Link_1_addr + */ +typedef union { + struct { + /** link_addr_1 : R/W; bitpos: [31:0]; default: 0; + * Link_1_addr reg + */ + uint32_t link_addr_1:32; + }; + uint32_t val; +} pau_regdma_link_1_addr_reg_t; + +/** Type of regdma_link_2_addr register + * Link_2_addr + */ +typedef union { + struct { + /** link_addr_2 : R/W; bitpos: [31:0]; default: 0; + * Link_2_addr reg + */ + uint32_t link_addr_2:32; + }; + uint32_t val; +} pau_regdma_link_2_addr_reg_t; + +/** Type of regdma_link_3_addr register + * Link_3_addr + */ +typedef union { + struct { + /** link_addr_3 : R/W; bitpos: [31:0]; default: 0; + * Link_3_addr reg + */ + uint32_t link_addr_3:32; + }; + uint32_t val; +} pau_regdma_link_3_addr_reg_t; + +/** Type of regdma_link_mac_addr register + * Link_mac_addr + */ +typedef union { + struct { + /** link_addr_mac : R/W; bitpos: [31:0]; default: 0; + * Link_mac_addr reg + */ + uint32_t link_addr_mac:32; + }; + uint32_t val; +} pau_regdma_link_mac_addr_reg_t; + +/** Type of regdma_current_link_addr register + * current link addr + */ +typedef union { + struct { + /** current_link_addr : RO; bitpos: [31:0]; default: 0; + * current link addr reg + */ + uint32_t current_link_addr:32; + }; + uint32_t val; +} pau_regdma_current_link_addr_reg_t; + +/** Type of regdma_backup_addr register + * Backup addr + */ +typedef union { + struct { + /** backup_addr : RO; bitpos: [31:0]; default: 0; + * backup addr reg + */ + uint32_t backup_addr:32; + }; + uint32_t val; +} pau_regdma_backup_addr_reg_t; + +/** Type of regdma_mem_addr register + * mem addr + */ +typedef union { + struct { + /** mem_addr : RO; bitpos: [31:0]; default: 0; + * mem addr reg + */ + uint32_t mem_addr:32; + }; + uint32_t val; +} pau_regdma_mem_addr_reg_t; + +/** Type of regdma_bkp_conf register + * backup config + */ +typedef union { + struct { + /** read_interval : R/W; bitpos: [6:0]; default: 32; + * Link read_interval + */ + uint32_t read_interval:7; + /** link_tout_thres : R/W; bitpos: [16:7]; default: 50; + * link wait timeout threshold + */ + uint32_t link_tout_thres:10; + /** burst_limit : R/W; bitpos: [21:17]; default: 8; + * burst limit + */ + uint32_t burst_limit:5; + /** backup_tout_thres : R/W; bitpos: [31:22]; default: 500; + * Backup timeout threshold + */ + uint32_t backup_tout_thres:10; + }; + uint32_t val; +} pau_regdma_bkp_conf_reg_t; + +/** Type of int_ena register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_ena : R/W; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_ena:1; + /** error_int_ena : R/W; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_ena_reg_t; + +/** Type of int_raw register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_raw:1; + /** error_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_raw_reg_t; + +/** Type of int_clr register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_clr : WT; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_clr:1; + /** error_int_clr : WT; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_clr_reg_t; + +/** Type of int_st register + * Read only register for error and done + */ +typedef union { + struct { + /** done_int_st : RO; bitpos: [0]; default: 0; + * backup done flag + */ + uint32_t done_int_st:1; + /** error_int_st : RO; bitpos: [1]; default: 0; + * error flag + */ + uint32_t error_int_st:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pau_int_st_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Date register. + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 36708608; + * REGDMA date information/ REGDMA version information. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} pau_date_reg_t; + + +typedef struct { + volatile pau_regdma_conf_reg_t regdma_conf; + volatile pau_regdma_clk_conf_reg_t regdma_clk_conf; + volatile pau_regdma_etm_ctrl_reg_t regdma_etm_ctrl; + volatile pau_regdma_link_0_addr_reg_t regdma_link_0_addr; + volatile pau_regdma_link_1_addr_reg_t regdma_link_1_addr; + volatile pau_regdma_link_2_addr_reg_t regdma_link_2_addr; + volatile pau_regdma_link_3_addr_reg_t regdma_link_3_addr; + volatile pau_regdma_link_mac_addr_reg_t regdma_link_mac_addr; + volatile pau_regdma_current_link_addr_reg_t regdma_current_link_addr; + volatile pau_regdma_backup_addr_reg_t regdma_backup_addr; + volatile pau_regdma_mem_addr_reg_t regdma_mem_addr; + volatile pau_regdma_bkp_conf_reg_t regdma_bkp_conf; + volatile pau_int_ena_reg_t int_ena; + volatile pau_int_raw_reg_t int_raw; + volatile pau_int_clr_reg_t int_clr; + volatile pau_int_st_reg_t int_st; + uint32_t reserved_040[239]; + volatile pau_date_reg_t date; +} pau_dev_t; + +extern pau_dev_t PAU; + +#ifndef __cplusplus +_Static_assert(sizeof(pau_dev_t) == 0x400, "Invalid size of pau_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/pmu_reg.h b/components/soc/esp32c61/include/soc/pmu_reg.h new file mode 100644 index 0000000000..ad4b994f78 --- /dev/null +++ b/components/soc/esp32c61/include/soc/pmu_reg.h @@ -0,0 +1,3519 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PMU_HP_ACTIVE_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_ACTIVE_DIG_POWER_REG (DR_REG_PMU_BASE + 0x0) +/** PMU_HP_ACTIVE_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_M (PMU_HP_ACTIVE_VDD_SPI_PD_EN_V << PMU_HP_ACTIVE_VDD_SPI_PD_EN_S) +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_S 21 +/** PMU_HP_ACTIVE_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_ACTIVE_HP_MEM_DSLP_M (PMU_HP_ACTIVE_HP_MEM_DSLP_V << PMU_HP_ACTIVE_HP_MEM_DSLP_S) +#define PMU_HP_ACTIVE_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_ACTIVE_HP_MEM_DSLP_S 22 +/** PMU_HP_ACTIVE_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_M (PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V << PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_M (PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_ACTIVE_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN (BIT(28)) +#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_M (PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_S 28 +/** PMU_HP_ACTIVE_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_M (PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V << PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_ACTIVE_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_M (PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V << PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_ACTIVE_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_M (PMU_HP_ACTIVE_PD_TOP_PD_EN_V << PMU_HP_ACTIVE_PD_TOP_PD_EN_S) +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_TOP_PD_EN_S 31 + +/** PMU_HP_ACTIVE_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x4) +/** PMU_HP_ACTIVE_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_M (PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V << PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S) +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_ACTIVE_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x8) +/** PMU_HP_ACTIVE_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_M (PMU_HP_ACTIVE_DIG_ICG_APB_EN_V << PMU_HP_ACTIVE_DIG_ICG_APB_EN_S) +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_ACTIVE_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_ACTIVE_ICG_MODEM_REG (DR_REG_PMU_BASE + 0xc) +/** PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_M (PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V << PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_ACTIVE_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x10) +/** PMU_HP_ACTIVE_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_M (PMU_HP_ACTIVE_UART_WAKEUP_EN_V << PMU_HP_ACTIVE_UART_WAKEUP_EN_S) +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_ACTIVE_UART_WAKEUP_EN_S 24 +/** PMU_HP_ACTIVE_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S) +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_ACTIVE_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S) +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_ACTIVE_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_M (PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V << PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S) +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_ACTIVE_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_M (PMU_HP_ACTIVE_DIG_PAUSE_WDT_V << PMU_HP_ACTIVE_DIG_PAUSE_WDT_S) +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_PAUSE_WDT_S 28 +/** PMU_HP_ACTIVE_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_ACTIVE_DIG_CPU_STALL_M (PMU_HP_ACTIVE_DIG_CPU_STALL_V << PMU_HP_ACTIVE_DIG_CPU_STALL_S) +#define PMU_HP_ACTIVE_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_CPU_STALL_S 29 + +/** PMU_HP_ACTIVE_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x14) +/** PMU_HP_ACTIVE_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_I2C_ISO_EN (BIT(26)) +#define PMU_HP_ACTIVE_I2C_ISO_EN_M (PMU_HP_ACTIVE_I2C_ISO_EN_V << PMU_HP_ACTIVE_I2C_ISO_EN_S) +#define PMU_HP_ACTIVE_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_ACTIVE_I2C_ISO_EN_S 26 +/** PMU_HP_ACTIVE_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_I2C_RETENTION (BIT(27)) +#define PMU_HP_ACTIVE_I2C_RETENTION_M (PMU_HP_ACTIVE_I2C_RETENTION_V << PMU_HP_ACTIVE_I2C_RETENTION_S) +#define PMU_HP_ACTIVE_I2C_RETENTION_V 0x00000001U +#define PMU_HP_ACTIVE_I2C_RETENTION_S 27 +/** PMU_HP_ACTIVE_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BB_I2C (BIT(28)) +#define PMU_HP_ACTIVE_XPD_BB_I2C_M (PMU_HP_ACTIVE_XPD_BB_I2C_V << PMU_HP_ACTIVE_XPD_BB_I2C_S) +#define PMU_HP_ACTIVE_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BB_I2C_S 28 +/** PMU_HP_ACTIVE_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_M (PMU_HP_ACTIVE_XPD_BBPLL_I2C_V << PMU_HP_ACTIVE_XPD_BBPLL_I2C_S) +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BBPLL_I2C_S 29 +/** PMU_HP_ACTIVE_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BBPLL (BIT(30)) +#define PMU_HP_ACTIVE_XPD_BBPLL_M (PMU_HP_ACTIVE_XPD_BBPLL_V << PMU_HP_ACTIVE_XPD_BBPLL_S) +#define PMU_HP_ACTIVE_XPD_BBPLL_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BBPLL_S 30 + +/** PMU_HP_ACTIVE_BIAS_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BIAS_REG (DR_REG_PMU_BASE + 0x18) +/** PMU_HP_ACTIVE_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_BIAS (BIT(25)) +#define PMU_HP_ACTIVE_XPD_BIAS_M (PMU_HP_ACTIVE_XPD_BIAS_V << PMU_HP_ACTIVE_XPD_BIAS_S) +#define PMU_HP_ACTIVE_XPD_BIAS_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_BIAS_S 25 +/** PMU_HP_ACTIVE_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DBG_ATTEN 0x0000000FU +#define PMU_HP_ACTIVE_DBG_ATTEN_M (PMU_HP_ACTIVE_DBG_ATTEN_V << PMU_HP_ACTIVE_DBG_ATTEN_S) +#define PMU_HP_ACTIVE_DBG_ATTEN_V 0x0000000FU +#define PMU_HP_ACTIVE_DBG_ATTEN_S 26 +/** PMU_HP_ACTIVE_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_CUR (BIT(30)) +#define PMU_HP_ACTIVE_PD_CUR_M (PMU_HP_ACTIVE_PD_CUR_V << PMU_HP_ACTIVE_PD_CUR_S) +#define PMU_HP_ACTIVE_PD_CUR_V 0x00000001U +#define PMU_HP_ACTIVE_PD_CUR_S 30 +/** PMU_HP_ACTIVE_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_BIAS_SLEEP (BIT(31)) +#define PMU_HP_ACTIVE_BIAS_SLEEP_M (PMU_HP_ACTIVE_BIAS_SLEEP_V << PMU_HP_ACTIVE_BIAS_SLEEP_S) +#define PMU_HP_ACTIVE_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_ACTIVE_BIAS_SLEEP_S 31 + +/** PMU_HP_ACTIVE_BACKUP_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_REG (DR_REG_PMU_BASE + 0x1c) +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S 4 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S 6 +/** PMU_HP_ACTIVE_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_RETENTION_MODE (BIT(10)) +#define PMU_HP_ACTIVE_RETENTION_MODE_M (PMU_HP_ACTIVE_RETENTION_MODE_V << PMU_HP_ACTIVE_RETENTION_MODE_S) +#define PMU_HP_ACTIVE_RETENTION_MODE_V 0x00000001U +#define PMU_HP_ACTIVE_RETENTION_MODE_S 10 +/** PMU_HP_SLEEP2ACTIVE_RETENTION_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN (BIT(11)) +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_M (PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V << PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S) +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V 0x00000001U +#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S 11 +/** PMU_HP_MODEM2ACTIVE_RETENTION_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN (BIT(12)) +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_M (PMU_HP_MODEM2ACTIVE_RETENTION_EN_V << PMU_HP_MODEM2ACTIVE_RETENTION_EN_S) +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_V 0x00000001U +#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_S 12 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S 14 +/** PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S 16 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S 20 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE 0x00000007U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V 0x00000007U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S 23 +/** PMU_HP_SLEEP2ACTIVE_BACKUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN (BIT(29)) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_M (PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V << PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S) +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V 0x00000001U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S 29 +/** PMU_HP_MODEM2ACTIVE_BACKUP_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN (BIT(30)) +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_M (PMU_HP_MODEM2ACTIVE_BACKUP_EN_V << PMU_HP_MODEM2ACTIVE_BACKUP_EN_S) +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_V 0x00000001U +#define PMU_HP_MODEM2ACTIVE_BACKUP_EN_S 30 + +/** PMU_HP_ACTIVE_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x20) +/** PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_M (PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V << PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_ACTIVE_SYSCLK_REG register + * need_des + */ +#define PMU_HP_ACTIVE_SYSCLK_REG (DR_REG_PMU_BASE + 0x24) +/** PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_M (PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V << PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_M (PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V << PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_ACTIVE_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_M (PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V << PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S) +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_ACTIVE_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_ACTIVE_ICG_SLP_SEL_M (PMU_HP_ACTIVE_ICG_SLP_SEL_V << PMU_HP_ACTIVE_ICG_SLP_SEL_S) +#define PMU_HP_ACTIVE_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_ACTIVE_ICG_SLP_SEL_S 29 +/** PMU_HP_ACTIVE_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_M (PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V << PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S) +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_ACTIVE_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x28) +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_CONNECT_EN : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_CONNECT_EN (BIT(3)) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_CONNECT_EN_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_CONNECT_EN_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_CONNECT_EN_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_CONNECT_EN_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_CONNECT_EN_S 3 +/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 24; + * need_des + */ +#define PMU_LP_DBIAS_VOL 0x0000001FU +#define PMU_LP_DBIAS_VOL_M (PMU_LP_DBIAS_VOL_V << PMU_LP_DBIAS_VOL_S) +#define PMU_LP_DBIAS_VOL_V 0x0000001FU +#define PMU_LP_DBIAS_VOL_S 4 +/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 24; + * need_des + */ +#define PMU_HP_DBIAS_VOL 0x0000001FU +#define PMU_HP_DBIAS_VOL_M (PMU_HP_DBIAS_VOL_V << PMU_HP_DBIAS_VOL_S) +#define PMU_HP_DBIAS_VOL_V 0x0000001FU +#define PMU_HP_DBIAS_VOL_S 9 +/** PMU_DIG_REGULATOR0_DBIAS_SEL : R/W; bitpos: [14]; default: 1; + * need_des + */ +#define PMU_DIG_REGULATOR0_DBIAS_SEL (BIT(14)) +#define PMU_DIG_REGULATOR0_DBIAS_SEL_M (PMU_DIG_REGULATOR0_DBIAS_SEL_V << PMU_DIG_REGULATOR0_DBIAS_SEL_S) +#define PMU_DIG_REGULATOR0_DBIAS_SEL_V 0x00000001U +#define PMU_DIG_REGULATOR0_DBIAS_SEL_S 14 +/** PMU_DIG_DBIAS_INIT : WT; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_DIG_DBIAS_INIT (BIT(15)) +#define PMU_DIG_DBIAS_INIT_M (PMU_DIG_DBIAS_INIT_V << PMU_DIG_DBIAS_INIT_S) +#define PMU_DIG_DBIAS_INIT_V 0x00000001U +#define PMU_DIG_DBIAS_INIT_S 15 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_ACTIVE_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_XPD_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_ACTIVE_HP_REGULATOR_XPD_S 18 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_ACTIVE_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_ACTIVE_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x2c) +/** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_M (PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V << PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S) +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_ACTIVE_XTAL_REG register + * need_des + */ +#define PMU_HP_ACTIVE_XTAL_REG (DR_REG_PMU_BASE + 0x30) +/** PMU_HP_ACTIVE_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_XTAL (BIT(31)) +#define PMU_HP_ACTIVE_XPD_XTAL_M (PMU_HP_ACTIVE_XPD_XTAL_V << PMU_HP_ACTIVE_XPD_XTAL_S) +#define PMU_HP_ACTIVE_XPD_XTAL_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_XTAL_S 31 + +/** PMU_HP_MODEM_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34) +/** PMU_HP_MODEM_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_MODEM_VDD_SPI_PD_EN_M (PMU_HP_MODEM_VDD_SPI_PD_EN_V << PMU_HP_MODEM_VDD_SPI_PD_EN_S) +#define PMU_HP_MODEM_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_VDD_SPI_PD_EN_S 21 +/** PMU_HP_MODEM_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_MODEM_HP_MEM_DSLP_M (PMU_HP_MODEM_HP_MEM_DSLP_V << PMU_HP_MODEM_HP_MEM_DSLP_S) +#define PMU_HP_MODEM_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_MODEM_HP_MEM_DSLP_S 22 +/** PMU_HP_MODEM_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_M (PMU_HP_MODEM_PD_HP_MEM_PD_EN_V << PMU_HP_MODEM_PD_HP_MEM_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_MODEM_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_MODEM_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_MODEM_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_PERI_PD_EN (BIT(28)) +#define PMU_HP_MODEM_PD_HP_PERI_PD_EN_M (PMU_HP_MODEM_PD_HP_PERI_PD_EN_V << PMU_HP_MODEM_PD_HP_PERI_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_PERI_PD_EN_S 28 +/** PMU_HP_MODEM_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_M (PMU_HP_MODEM_PD_HP_CPU_PD_EN_V << PMU_HP_MODEM_PD_HP_CPU_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_MODEM_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_M (PMU_HP_MODEM_PD_HP_AON_PD_EN_V << PMU_HP_MODEM_PD_HP_AON_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_MODEM_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_MODEM_PD_TOP_PD_EN_M (PMU_HP_MODEM_PD_TOP_PD_EN_V << PMU_HP_MODEM_PD_TOP_PD_EN_S) +#define PMU_HP_MODEM_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_TOP_PD_EN_S 31 + +/** PMU_HP_MODEM_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38) +/** PMU_HP_MODEM_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_M (PMU_HP_MODEM_DIG_ICG_FUNC_EN_V << PMU_HP_MODEM_DIG_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c) +/** PMU_HP_MODEM_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_M (PMU_HP_MODEM_DIG_ICG_APB_EN_V << PMU_HP_MODEM_DIG_ICG_APB_EN_S) +#define PMU_HP_MODEM_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_MODEM_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_MODEM_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x40) +/** PMU_HP_MODEM_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_M (PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V << PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_MODEM_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x44) +/** PMU_HP_MODEM_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_MODEM_UART_WAKEUP_EN_M (PMU_HP_MODEM_UART_WAKEUP_EN_V << PMU_HP_MODEM_UART_WAKEUP_EN_S) +#define PMU_HP_MODEM_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_MODEM_UART_WAKEUP_EN_S 24 +/** PMU_HP_MODEM_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_M (PMU_HP_MODEM_LP_PAD_HOLD_ALL_V << PMU_HP_MODEM_LP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_MODEM_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_M (PMU_HP_MODEM_HP_PAD_HOLD_ALL_V << PMU_HP_MODEM_HP_PAD_HOLD_ALL_S) +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_MODEM_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_MODEM_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_M (PMU_HP_MODEM_DIG_PAD_SLP_SEL_V << PMU_HP_MODEM_DIG_PAD_SLP_SEL_S) +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_MODEM_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_M (PMU_HP_MODEM_DIG_PAUSE_WDT_V << PMU_HP_MODEM_DIG_PAUSE_WDT_S) +#define PMU_HP_MODEM_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_MODEM_DIG_PAUSE_WDT_S 28 +/** PMU_HP_MODEM_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_MODEM_DIG_CPU_STALL_M (PMU_HP_MODEM_DIG_CPU_STALL_V << PMU_HP_MODEM_DIG_CPU_STALL_S) +#define PMU_HP_MODEM_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_MODEM_DIG_CPU_STALL_S 29 + +/** PMU_HP_MODEM_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x48) +/** PMU_HP_MODEM_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_ISO_EN (BIT(26)) +#define PMU_HP_MODEM_I2C_ISO_EN_M (PMU_HP_MODEM_I2C_ISO_EN_V << PMU_HP_MODEM_I2C_ISO_EN_S) +#define PMU_HP_MODEM_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_MODEM_I2C_ISO_EN_S 26 +/** PMU_HP_MODEM_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_I2C_RETENTION (BIT(27)) +#define PMU_HP_MODEM_I2C_RETENTION_M (PMU_HP_MODEM_I2C_RETENTION_V << PMU_HP_MODEM_I2C_RETENTION_S) +#define PMU_HP_MODEM_I2C_RETENTION_V 0x00000001U +#define PMU_HP_MODEM_I2C_RETENTION_S 27 +/** PMU_HP_MODEM_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BB_I2C (BIT(28)) +#define PMU_HP_MODEM_XPD_BB_I2C_M (PMU_HP_MODEM_XPD_BB_I2C_V << PMU_HP_MODEM_XPD_BB_I2C_S) +#define PMU_HP_MODEM_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_BB_I2C_S 28 +/** PMU_HP_MODEM_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_MODEM_XPD_BBPLL_I2C_M (PMU_HP_MODEM_XPD_BBPLL_I2C_V << PMU_HP_MODEM_XPD_BBPLL_I2C_S) +#define PMU_HP_MODEM_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_MODEM_XPD_BBPLL_I2C_S 29 +/** PMU_HP_MODEM_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BBPLL (BIT(30)) +#define PMU_HP_MODEM_XPD_BBPLL_M (PMU_HP_MODEM_XPD_BBPLL_V << PMU_HP_MODEM_XPD_BBPLL_S) +#define PMU_HP_MODEM_XPD_BBPLL_V 0x00000001U +#define PMU_HP_MODEM_XPD_BBPLL_S 30 + +/** PMU_HP_MODEM_BIAS_REG register + * need_des + */ +#define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c) +/** PMU_HP_MODEM_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_XPD_BIAS (BIT(25)) +#define PMU_HP_MODEM_XPD_BIAS_M (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S) +#define PMU_HP_MODEM_XPD_BIAS_V 0x00000001U +#define PMU_HP_MODEM_XPD_BIAS_S 25 +/** PMU_HP_MODEM_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DBG_ATTEN 0x0000000FU +#define PMU_HP_MODEM_DBG_ATTEN_M (PMU_HP_MODEM_DBG_ATTEN_V << PMU_HP_MODEM_DBG_ATTEN_S) +#define PMU_HP_MODEM_DBG_ATTEN_V 0x0000000FU +#define PMU_HP_MODEM_DBG_ATTEN_S 26 +/** PMU_HP_MODEM_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_CUR (BIT(30)) +#define PMU_HP_MODEM_PD_CUR_M (PMU_HP_MODEM_PD_CUR_V << PMU_HP_MODEM_PD_CUR_S) +#define PMU_HP_MODEM_PD_CUR_V 0x00000001U +#define PMU_HP_MODEM_PD_CUR_S 30 +/** PMU_HP_MODEM_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BIAS_SLEEP (BIT(31)) +#define PMU_HP_MODEM_BIAS_SLEEP_M (PMU_HP_MODEM_BIAS_SLEEP_V << PMU_HP_MODEM_BIAS_SLEEP_S) +#define PMU_HP_MODEM_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_MODEM_BIAS_SLEEP_S 31 + +/** PMU_HP_MODEM_BACKUP_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_REG (DR_REG_PMU_BASE + 0x50) +/** PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S 4 +/** PMU_HP_MODEM_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_RETENTION_MODE (BIT(10)) +#define PMU_HP_MODEM_RETENTION_MODE_M (PMU_HP_MODEM_RETENTION_MODE_V << PMU_HP_MODEM_RETENTION_MODE_S) +#define PMU_HP_MODEM_RETENTION_MODE_V 0x00000001U +#define PMU_HP_MODEM_RETENTION_MODE_S 10 +/** PMU_HP_SLEEP2MODEM_RETENTION_EN : R/W; bitpos: [11]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_RETENTION_EN (BIT(11)) +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_M (PMU_HP_SLEEP2MODEM_RETENTION_EN_V << PMU_HP_SLEEP2MODEM_RETENTION_EN_S) +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_V 0x00000001U +#define PMU_HP_SLEEP2MODEM_RETENTION_EN_S 11 +/** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S 14 +/** PMU_HP_SLEEP2MODEM_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S 20 +/** PMU_HP_SLEEP2MODEM_BACKUP_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP2MODEM_BACKUP_EN (BIT(29)) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_M (PMU_HP_SLEEP2MODEM_BACKUP_EN_V << PMU_HP_SLEEP2MODEM_BACKUP_EN_S) +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_V 0x00000001U +#define PMU_HP_SLEEP2MODEM_BACKUP_EN_S 29 + +/** PMU_HP_MODEM_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_MODEM_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x54) +/** PMU_HP_MODEM_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_M (PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V << PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_MODEM_SYSCLK_REG register + * need_des + */ +#define PMU_HP_MODEM_SYSCLK_REG (DR_REG_PMU_BASE + 0x58) +/** PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_M (PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V << PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_MODEM_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_M (PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V << PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_MODEM_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_M (PMU_HP_MODEM_SYS_CLK_SLP_SEL_V << PMU_HP_MODEM_SYS_CLK_SLP_SEL_S) +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_MODEM_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_MODEM_ICG_SLP_SEL_M (PMU_HP_MODEM_ICG_SLP_SEL_V << PMU_HP_MODEM_ICG_SLP_SEL_S) +#define PMU_HP_MODEM_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_MODEM_ICG_SLP_SEL_S 29 +/** PMU_HP_MODEM_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_M (PMU_HP_MODEM_DIG_SYS_CLK_SEL_V << PMU_HP_MODEM_DIG_SYS_CLK_SEL_S) +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_MODEM_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c) +/** PMU_HP_MODEM_HP_REGULATOR_SLP_CONNECT_EN : R/W; bitpos: [15]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_CONNECT_EN (BIT(15)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_CONNECT_EN_M (PMU_HP_MODEM_HP_REGULATOR_SLP_CONNECT_EN_V << PMU_HP_MODEM_HP_REGULATOR_SLP_CONNECT_EN_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_CONNECT_EN_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_CONNECT_EN_S 15 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_MODEM_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_M (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S) +#define PMU_HP_MODEM_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_MODEM_HP_REGULATOR_XPD_S 18 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_MODEM_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_DBIAS_S) +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_MODEM_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_MODEM_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x60) +/** PMU_HP_MODEM_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_M (PMU_HP_MODEM_HP_REGULATOR_DRV_B_V << PMU_HP_MODEM_HP_REGULATOR_DRV_B_S) +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_MODEM_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_MODEM_XTAL_REG register + * need_des + */ +#define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64) +/** PMU_HP_MODEM_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_XPD_XTAL (BIT(31)) +#define PMU_HP_MODEM_XPD_XTAL_M (PMU_HP_MODEM_XPD_XTAL_V << PMU_HP_MODEM_XPD_XTAL_S) +#define PMU_HP_MODEM_XPD_XTAL_V 0x00000001U +#define PMU_HP_MODEM_XPD_XTAL_S 31 + +/** PMU_HP_SLEEP_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_DIG_POWER_REG (DR_REG_PMU_BASE + 0x68) +/** PMU_HP_SLEEP_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_VDD_SPI_PD_EN (BIT(21)) +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_M (PMU_HP_SLEEP_VDD_SPI_PD_EN_V << PMU_HP_SLEEP_VDD_SPI_PD_EN_S) +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_VDD_SPI_PD_EN_S 21 +/** PMU_HP_SLEEP_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_MEM_DSLP (BIT(22)) +#define PMU_HP_SLEEP_HP_MEM_DSLP_M (PMU_HP_SLEEP_HP_MEM_DSLP_V << PMU_HP_SLEEP_HP_MEM_DSLP_S) +#define PMU_HP_SLEEP_HP_MEM_DSLP_V 0x00000001U +#define PMU_HP_SLEEP_HP_MEM_DSLP_S 22 +/** PMU_HP_SLEEP_PD_HP_MEM_PD_EN : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN 0x0000000FU +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_M (PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V << PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V 0x0000000FU +#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S 23 +/** PMU_HP_SLEEP_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN (BIT(27)) +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_M (PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V << PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_SLEEP_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN (BIT(28)) +#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_M (PMU_HP_SLEEP_PD_HP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_HP_PERI_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_S 28 +/** PMU_HP_SLEEP_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN (BIT(29)) +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_M (PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V << PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S 29 +/** PMU_HP_SLEEP_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN (BIT(30)) +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_M (PMU_HP_SLEEP_PD_HP_AON_PD_EN_V << PMU_HP_SLEEP_PD_HP_AON_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_AON_PD_EN_S 30 +/** PMU_HP_SLEEP_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_TOP_PD_EN (BIT(31)) +#define PMU_HP_SLEEP_PD_TOP_PD_EN_M (PMU_HP_SLEEP_PD_TOP_PD_EN_V << PMU_HP_SLEEP_PD_TOP_PD_EN_S) +#define PMU_HP_SLEEP_PD_TOP_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_TOP_PD_EN_S 31 + +/** PMU_HP_SLEEP_ICG_HP_FUNC_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x6c) +/** PMU_HP_SLEEP_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_M (PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V << PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S) +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S 0 + +/** PMU_HP_SLEEP_ICG_HP_APB_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x70) +/** PMU_HP_SLEEP_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_APB_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_M (PMU_HP_SLEEP_DIG_ICG_APB_EN_V << PMU_HP_SLEEP_DIG_ICG_APB_EN_S) +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_DIG_ICG_APB_EN_S 0 + +/** PMU_HP_SLEEP_ICG_MODEM_REG register + * need_des + */ +#define PMU_HP_SLEEP_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x74) +/** PMU_HP_SLEEP_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE 0x00000003U +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_M (PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V << PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S) +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V 0x00000003U +#define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S 30 + +/** PMU_HP_SLEEP_HP_SYS_CNTL_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x78) +/** PMU_HP_SLEEP_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_UART_WAKEUP_EN (BIT(24)) +#define PMU_HP_SLEEP_UART_WAKEUP_EN_M (PMU_HP_SLEEP_UART_WAKEUP_EN_V << PMU_HP_SLEEP_UART_WAKEUP_EN_S) +#define PMU_HP_SLEEP_UART_WAKEUP_EN_V 0x00000001U +#define PMU_HP_SLEEP_UART_WAKEUP_EN_S 24 +/** PMU_HP_SLEEP_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL (BIT(25)) +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S) +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S 25 +/** PMU_HP_SLEEP_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL (BIT(26)) +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S) +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S 26 +/** PMU_HP_SLEEP_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_M (PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V << PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S) +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S 27 +/** PMU_HP_SLEEP_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PAUSE_WDT (BIT(28)) +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_M (PMU_HP_SLEEP_DIG_PAUSE_WDT_V << PMU_HP_SLEEP_DIG_PAUSE_WDT_S) +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_V 0x00000001U +#define PMU_HP_SLEEP_DIG_PAUSE_WDT_S 28 +/** PMU_HP_SLEEP_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_CPU_STALL (BIT(29)) +#define PMU_HP_SLEEP_DIG_CPU_STALL_M (PMU_HP_SLEEP_DIG_CPU_STALL_V << PMU_HP_SLEEP_DIG_CPU_STALL_S) +#define PMU_HP_SLEEP_DIG_CPU_STALL_V 0x00000001U +#define PMU_HP_SLEEP_DIG_CPU_STALL_S 29 + +/** PMU_HP_SLEEP_HP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x7c) +/** PMU_HP_SLEEP_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_I2C_ISO_EN (BIT(26)) +#define PMU_HP_SLEEP_I2C_ISO_EN_M (PMU_HP_SLEEP_I2C_ISO_EN_V << PMU_HP_SLEEP_I2C_ISO_EN_S) +#define PMU_HP_SLEEP_I2C_ISO_EN_V 0x00000001U +#define PMU_HP_SLEEP_I2C_ISO_EN_S 26 +/** PMU_HP_SLEEP_I2C_RETENTION : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_I2C_RETENTION (BIT(27)) +#define PMU_HP_SLEEP_I2C_RETENTION_M (PMU_HP_SLEEP_I2C_RETENTION_V << PMU_HP_SLEEP_I2C_RETENTION_S) +#define PMU_HP_SLEEP_I2C_RETENTION_V 0x00000001U +#define PMU_HP_SLEEP_I2C_RETENTION_S 27 +/** PMU_HP_SLEEP_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BB_I2C (BIT(28)) +#define PMU_HP_SLEEP_XPD_BB_I2C_M (PMU_HP_SLEEP_XPD_BB_I2C_V << PMU_HP_SLEEP_XPD_BB_I2C_S) +#define PMU_HP_SLEEP_XPD_BB_I2C_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BB_I2C_S 28 +/** PMU_HP_SLEEP_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BBPLL_I2C (BIT(29)) +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_M (PMU_HP_SLEEP_XPD_BBPLL_I2C_V << PMU_HP_SLEEP_XPD_BBPLL_I2C_S) +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BBPLL_I2C_S 29 +/** PMU_HP_SLEEP_XPD_BBPLL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BBPLL (BIT(30)) +#define PMU_HP_SLEEP_XPD_BBPLL_M (PMU_HP_SLEEP_XPD_BBPLL_V << PMU_HP_SLEEP_XPD_BBPLL_S) +#define PMU_HP_SLEEP_XPD_BBPLL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BBPLL_S 30 + +/** PMU_HP_SLEEP_BIAS_REG register + * need_des + */ +#define PMU_HP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0x80) +/** PMU_HP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_BIAS (BIT(25)) +#define PMU_HP_SLEEP_XPD_BIAS_M (PMU_HP_SLEEP_XPD_BIAS_V << PMU_HP_SLEEP_XPD_BIAS_S) +#define PMU_HP_SLEEP_XPD_BIAS_V 0x00000001U +#define PMU_HP_SLEEP_XPD_BIAS_S 25 +/** PMU_HP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DBG_ATTEN 0x0000000FU +#define PMU_HP_SLEEP_DBG_ATTEN_M (PMU_HP_SLEEP_DBG_ATTEN_V << PMU_HP_SLEEP_DBG_ATTEN_S) +#define PMU_HP_SLEEP_DBG_ATTEN_V 0x0000000FU +#define PMU_HP_SLEEP_DBG_ATTEN_S 26 +/** PMU_HP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_CUR (BIT(30)) +#define PMU_HP_SLEEP_PD_CUR_M (PMU_HP_SLEEP_PD_CUR_V << PMU_HP_SLEEP_PD_CUR_S) +#define PMU_HP_SLEEP_PD_CUR_V 0x00000001U +#define PMU_HP_SLEEP_PD_CUR_S 30 +/** PMU_HP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BIAS_SLEEP (BIT(31)) +#define PMU_HP_SLEEP_BIAS_SLEEP_M (PMU_HP_SLEEP_BIAS_SLEEP_V << PMU_HP_SLEEP_BIAS_SLEEP_S) +#define PMU_HP_SLEEP_BIAS_SLEEP_V 0x00000001U +#define PMU_HP_SLEEP_BIAS_SLEEP_S 31 + +/** PMU_HP_SLEEP_BACKUP_REG register + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_REG (DR_REG_PMU_BASE + 0x84) +/** PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S 6 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [9:8]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S 8 +/** PMU_HP_SLEEP_RETENTION_MODE : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_RETENTION_MODE (BIT(10)) +#define PMU_HP_SLEEP_RETENTION_MODE_M (PMU_HP_SLEEP_RETENTION_MODE_V << PMU_HP_SLEEP_RETENTION_MODE_S) +#define PMU_HP_SLEEP_RETENTION_MODE_V 0x00000001U +#define PMU_HP_SLEEP_RETENTION_MODE_S 10 +/** PMU_HP_MODEM2SLEEP_RETENTION_EN : R/W; bitpos: [12]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_RETENTION_EN (BIT(12)) +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_M (PMU_HP_MODEM2SLEEP_RETENTION_EN_V << PMU_HP_MODEM2SLEEP_RETENTION_EN_S) +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_V 0x00000001U +#define PMU_HP_MODEM2SLEEP_RETENTION_EN_S 12 +/** PMU_HP_ACTIVE2SLEEP_RETENTION_EN : R/W; bitpos: [13]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN (BIT(13)) +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_M (PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V << PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S) +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V 0x00000001U +#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S 13 +/** PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S 16 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [19:18]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V 0x00000003U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S 18 +/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE 0x00000007U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODE_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V 0x00000007U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S 23 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [28:26]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE 0x00000007U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V 0x00000007U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S 26 +/** PMU_HP_MODEM2SLEEP_BACKUP_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_MODEM2SLEEP_BACKUP_EN (BIT(30)) +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_M (PMU_HP_MODEM2SLEEP_BACKUP_EN_V << PMU_HP_MODEM2SLEEP_BACKUP_EN_S) +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_V 0x00000001U +#define PMU_HP_MODEM2SLEEP_BACKUP_EN_S 30 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN (BIT(31)) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_M (PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V << PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S) +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V 0x00000001U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S 31 + +/** PMU_HP_SLEEP_BACKUP_CLK_REG register + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x88) +/** PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_M (PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V << PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S) +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S 0 + +/** PMU_HP_SLEEP_SYSCLK_REG register + * need_des + */ +#define PMU_HP_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0x8c) +/** PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV (BIT(26)) +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_M (PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V << PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S) +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S 26 +/** PMU_HP_SLEEP_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN (BIT(27)) +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_M (PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V << PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S) +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V 0x00000001U +#define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S 27 +/** PMU_HP_SLEEP_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL (BIT(28)) +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_M (PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V << PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S) +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S 28 +/** PMU_HP_SLEEP_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_ICG_SLP_SEL (BIT(29)) +#define PMU_HP_SLEEP_ICG_SLP_SEL_M (PMU_HP_SLEEP_ICG_SLP_SEL_V << PMU_HP_SLEEP_ICG_SLP_SEL_S) +#define PMU_HP_SLEEP_ICG_SLP_SEL_V 0x00000001U +#define PMU_HP_SLEEP_ICG_SLP_SEL_S 29 +/** PMU_HP_SLEEP_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL 0x00000003U +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_M (PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V << PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S) +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V 0x00000003U +#define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S 30 + +/** PMU_HP_SLEEP_HP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x90) +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_CONNECT_EN : R/W; bitpos: [15]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_CONNECT_EN (BIT(15)) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_CONNECT_EN_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_CONNECT_EN_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_CONNECT_EN_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_CONNECT_EN_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_CONNECT_EN_S 15 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S 16 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S 17 +/** PMU_HP_SLEEP_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_XPD (BIT(18)) +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_XPD_S) +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_SLEEP_HP_REGULATOR_XPD_S 18 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S 19 +/** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 +/** PMU_HP_SLEEP_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S) +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_SLEEP_HP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x94) +/** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B 0x00FFFFFFU +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S) +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V 0x00FFFFFFU +#define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S 8 + +/** PMU_HP_SLEEP_XTAL_REG register + * need_des + */ +#define PMU_HP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0x98) +/** PMU_HP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_XTAL (BIT(31)) +#define PMU_HP_SLEEP_XPD_XTAL_M (PMU_HP_SLEEP_XPD_XTAL_V << PMU_HP_SLEEP_XPD_XTAL_S) +#define PMU_HP_SLEEP_XPD_XTAL_V 0x00000001U +#define PMU_HP_SLEEP_XPD_XTAL_S 31 + +/** PMU_HP_SLEEP_LP_REGULATOR0_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x9c) +/** PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 +/** PMU_HP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_XPD (BIT(22)) +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_XPD_S) +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U +#define PMU_HP_SLEEP_LP_REGULATOR_XPD_S 22 +/** PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 +/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S) +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S 27 + +/** PMU_HP_SLEEP_LP_REGULATOR1_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xa0) +/** PMU_HP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S) +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU +#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S 28 + +/** PMU_HP_SLEEP_LP_DCDC_RESERVE_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_REG (DR_REG_PMU_BASE + 0xa4) +/** PMU_HP_SLEEP_LP_DCDC_RESERVE : WT; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_DCDC_RESERVE 0xFFFFFFFFU +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_M (PMU_HP_SLEEP_LP_DCDC_RESERVE_V << PMU_HP_SLEEP_LP_DCDC_RESERVE_S) +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_V 0xFFFFFFFFU +#define PMU_HP_SLEEP_LP_DCDC_RESERVE_S 0 + +/** PMU_HP_SLEEP_LP_DIG_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xa8) +/** PMU_HP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_LP_MEM_DSLP (BIT(30)) +#define PMU_HP_SLEEP_LP_MEM_DSLP_M (PMU_HP_SLEEP_LP_MEM_DSLP_V << PMU_HP_SLEEP_LP_MEM_DSLP_S) +#define PMU_HP_SLEEP_LP_MEM_DSLP_V 0x00000001U +#define PMU_HP_SLEEP_LP_MEM_DSLP_S 30 +/** PMU_HP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S) +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S 31 + +/** PMU_HP_SLEEP_LP_CK_POWER_REG register + * need_des + */ +#define PMU_HP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xac) +/** PMU_HP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_XTAL32K (BIT(28)) +#define PMU_HP_SLEEP_XPD_XTAL32K_M (PMU_HP_SLEEP_XPD_XTAL32K_V << PMU_HP_SLEEP_XPD_XTAL32K_S) +#define PMU_HP_SLEEP_XPD_XTAL32K_V 0x00000001U +#define PMU_HP_SLEEP_XPD_XTAL32K_S 28 +/** PMU_HP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_XPD_RC32K (BIT(29)) +#define PMU_HP_SLEEP_XPD_RC32K_M (PMU_HP_SLEEP_XPD_RC32K_V << PMU_HP_SLEEP_XPD_RC32K_S) +#define PMU_HP_SLEEP_XPD_RC32K_V 0x00000001U +#define PMU_HP_SLEEP_XPD_RC32K_S 29 +/** PMU_HP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_FOSC_CLK (BIT(30)) +#define PMU_HP_SLEEP_XPD_FOSC_CLK_M (PMU_HP_SLEEP_XPD_FOSC_CLK_V << PMU_HP_SLEEP_XPD_FOSC_CLK_S) +#define PMU_HP_SLEEP_XPD_FOSC_CLK_V 0x00000001U +#define PMU_HP_SLEEP_XPD_FOSC_CLK_S 30 +/** PMU_HP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_OSC_CLK (BIT(31)) +#define PMU_HP_SLEEP_PD_OSC_CLK_M (PMU_HP_SLEEP_PD_OSC_CLK_V << PMU_HP_SLEEP_PD_OSC_CLK_S) +#define PMU_HP_SLEEP_PD_OSC_CLK_V 0x00000001U +#define PMU_HP_SLEEP_PD_OSC_CLK_S 31 + +/** PMU_LP_SLEEP_LP_BIAS_RESERVE_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_REG (DR_REG_PMU_BASE + 0xb0) +/** PMU_LP_SLEEP_LP_BIAS_RESERVE : WT; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_BIAS_RESERVE 0xFFFFFFFFU +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_M (PMU_LP_SLEEP_LP_BIAS_RESERVE_V << PMU_LP_SLEEP_LP_BIAS_RESERVE_S) +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_V 0xFFFFFFFFU +#define PMU_LP_SLEEP_LP_BIAS_RESERVE_S 0 + +/** PMU_LP_SLEEP_LP_REGULATOR0_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0xb4) +/** PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 +/** PMU_LP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_XPD (BIT(22)) +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_XPD_S) +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U +#define PMU_LP_SLEEP_LP_REGULATOR_XPD_S 22 +/** PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 +/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S) +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V 0x0000001FU +#define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S 27 + +/** PMU_LP_SLEEP_LP_REGULATOR1_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xb8) +/** PMU_LP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S) +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU +#define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S 28 + +/** PMU_LP_SLEEP_XTAL_REG register + * need_des + */ +#define PMU_LP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0xbc) +/** PMU_LP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_XPD_XTAL (BIT(31)) +#define PMU_LP_SLEEP_XPD_XTAL_M (PMU_LP_SLEEP_XPD_XTAL_V << PMU_LP_SLEEP_XPD_XTAL_S) +#define PMU_LP_SLEEP_XPD_XTAL_V 0x00000001U +#define PMU_LP_SLEEP_XPD_XTAL_S 31 + +/** PMU_LP_SLEEP_LP_DIG_POWER_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xc0) +/** PMU_LP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_LP_MEM_DSLP (BIT(30)) +#define PMU_LP_SLEEP_LP_MEM_DSLP_M (PMU_LP_SLEEP_LP_MEM_DSLP_V << PMU_LP_SLEEP_LP_MEM_DSLP_S) +#define PMU_LP_SLEEP_LP_MEM_DSLP_V 0x00000001U +#define PMU_LP_SLEEP_LP_MEM_DSLP_S 30 +/** PMU_LP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S) +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V 0x00000001U +#define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S 31 + +/** PMU_LP_SLEEP_LP_CK_POWER_REG register + * need_des + */ +#define PMU_LP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xc4) +/** PMU_LP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_XTAL32K (BIT(28)) +#define PMU_LP_SLEEP_XPD_XTAL32K_M (PMU_LP_SLEEP_XPD_XTAL32K_V << PMU_LP_SLEEP_XPD_XTAL32K_S) +#define PMU_LP_SLEEP_XPD_XTAL32K_V 0x00000001U +#define PMU_LP_SLEEP_XPD_XTAL32K_S 28 +/** PMU_LP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_RC32K (BIT(29)) +#define PMU_LP_SLEEP_XPD_RC32K_M (PMU_LP_SLEEP_XPD_RC32K_V << PMU_LP_SLEEP_XPD_RC32K_S) +#define PMU_LP_SLEEP_XPD_RC32K_V 0x00000001U +#define PMU_LP_SLEEP_XPD_RC32K_S 29 +/** PMU_LP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_XPD_FOSC_CLK (BIT(30)) +#define PMU_LP_SLEEP_XPD_FOSC_CLK_M (PMU_LP_SLEEP_XPD_FOSC_CLK_V << PMU_LP_SLEEP_XPD_FOSC_CLK_S) +#define PMU_LP_SLEEP_XPD_FOSC_CLK_V 0x00000001U +#define PMU_LP_SLEEP_XPD_FOSC_CLK_S 30 +/** PMU_LP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_OSC_CLK (BIT(31)) +#define PMU_LP_SLEEP_PD_OSC_CLK_M (PMU_LP_SLEEP_PD_OSC_CLK_V << PMU_LP_SLEEP_PD_OSC_CLK_S) +#define PMU_LP_SLEEP_PD_OSC_CLK_V 0x00000001U +#define PMU_LP_SLEEP_PD_OSC_CLK_S 31 + +/** PMU_LP_SLEEP_BIAS_REG register + * need_des + */ +#define PMU_LP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0xc8) +/** PMU_LP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_XPD_BIAS (BIT(25)) +#define PMU_LP_SLEEP_XPD_BIAS_M (PMU_LP_SLEEP_XPD_BIAS_V << PMU_LP_SLEEP_XPD_BIAS_S) +#define PMU_LP_SLEEP_XPD_BIAS_V 0x00000001U +#define PMU_LP_SLEEP_XPD_BIAS_S 25 +/** PMU_LP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_DBG_ATTEN 0x0000000FU +#define PMU_LP_SLEEP_DBG_ATTEN_M (PMU_LP_SLEEP_DBG_ATTEN_V << PMU_LP_SLEEP_DBG_ATTEN_S) +#define PMU_LP_SLEEP_DBG_ATTEN_V 0x0000000FU +#define PMU_LP_SLEEP_DBG_ATTEN_S 26 +/** PMU_LP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_PD_CUR (BIT(30)) +#define PMU_LP_SLEEP_PD_CUR_M (PMU_LP_SLEEP_PD_CUR_V << PMU_LP_SLEEP_PD_CUR_S) +#define PMU_LP_SLEEP_PD_CUR_V 0x00000001U +#define PMU_LP_SLEEP_PD_CUR_S 30 +/** PMU_LP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_BIAS_SLEEP (BIT(31)) +#define PMU_LP_SLEEP_BIAS_SLEEP_M (PMU_LP_SLEEP_BIAS_SLEEP_V << PMU_LP_SLEEP_BIAS_SLEEP_S) +#define PMU_LP_SLEEP_BIAS_SLEEP_V 0x00000001U +#define PMU_LP_SLEEP_BIAS_SLEEP_S 31 + +/** PMU_IMM_HP_CK_POWER_REG register + * need_des + */ +#define PMU_IMM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0xcc) +/** PMU_TIE_LOW_GLOBAL_BBPLL_ICG : WT; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG (BIT(0)) +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_M (PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V << PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S) +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S 0 +/** PMU_TIE_LOW_GLOBAL_XTAL_ICG : WT; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG (BIT(1)) +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_M (PMU_TIE_LOW_GLOBAL_XTAL_ICG_V << PMU_TIE_LOW_GLOBAL_XTAL_ICG_S) +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_XTAL_ICG_S 1 +/** PMU_TIE_LOW_I2C_RETENTION : WT; bitpos: [2]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_I2C_RETENTION (BIT(2)) +#define PMU_TIE_LOW_I2C_RETENTION_M (PMU_TIE_LOW_I2C_RETENTION_V << PMU_TIE_LOW_I2C_RETENTION_S) +#define PMU_TIE_LOW_I2C_RETENTION_V 0x00000001U +#define PMU_TIE_LOW_I2C_RETENTION_S 2 +/** PMU_TIE_LOW_XPD_BB_I2C : WT; bitpos: [3]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_BB_I2C (BIT(3)) +#define PMU_TIE_LOW_XPD_BB_I2C_M (PMU_TIE_LOW_XPD_BB_I2C_V << PMU_TIE_LOW_XPD_BB_I2C_S) +#define PMU_TIE_LOW_XPD_BB_I2C_V 0x00000001U +#define PMU_TIE_LOW_XPD_BB_I2C_S 3 +/** PMU_TIE_LOW_XPD_BBPLL_I2C : WT; bitpos: [4]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_BBPLL_I2C (BIT(4)) +#define PMU_TIE_LOW_XPD_BBPLL_I2C_M (PMU_TIE_LOW_XPD_BBPLL_I2C_V << PMU_TIE_LOW_XPD_BBPLL_I2C_S) +#define PMU_TIE_LOW_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_TIE_LOW_XPD_BBPLL_I2C_S 4 +/** PMU_TIE_LOW_XPD_BBPLL : WT; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_BBPLL (BIT(5)) +#define PMU_TIE_LOW_XPD_BBPLL_M (PMU_TIE_LOW_XPD_BBPLL_V << PMU_TIE_LOW_XPD_BBPLL_S) +#define PMU_TIE_LOW_XPD_BBPLL_V 0x00000001U +#define PMU_TIE_LOW_XPD_BBPLL_S 5 +/** PMU_TIE_LOW_XPD_XTAL : WT; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_XTAL (BIT(6)) +#define PMU_TIE_LOW_XPD_XTAL_M (PMU_TIE_LOW_XPD_XTAL_V << PMU_TIE_LOW_XPD_XTAL_S) +#define PMU_TIE_LOW_XPD_XTAL_V 0x00000001U +#define PMU_TIE_LOW_XPD_XTAL_S 6 +/** PMU_TIE_HIGH_GLOBAL_BBPLL_ICG : WT; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG (BIT(25)) +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_M (PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S 25 +/** PMU_TIE_HIGH_GLOBAL_XTAL_ICG : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG (BIT(26)) +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_M (PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V << PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S 26 +/** PMU_TIE_HIGH_I2C_RETENTION : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_I2C_RETENTION (BIT(27)) +#define PMU_TIE_HIGH_I2C_RETENTION_M (PMU_TIE_HIGH_I2C_RETENTION_V << PMU_TIE_HIGH_I2C_RETENTION_S) +#define PMU_TIE_HIGH_I2C_RETENTION_V 0x00000001U +#define PMU_TIE_HIGH_I2C_RETENTION_S 27 +/** PMU_TIE_HIGH_XPD_BB_I2C : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_BB_I2C (BIT(28)) +#define PMU_TIE_HIGH_XPD_BB_I2C_M (PMU_TIE_HIGH_XPD_BB_I2C_V << PMU_TIE_HIGH_XPD_BB_I2C_S) +#define PMU_TIE_HIGH_XPD_BB_I2C_V 0x00000001U +#define PMU_TIE_HIGH_XPD_BB_I2C_S 28 +/** PMU_TIE_HIGH_XPD_BBPLL_I2C : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_BBPLL_I2C (BIT(29)) +#define PMU_TIE_HIGH_XPD_BBPLL_I2C_M (PMU_TIE_HIGH_XPD_BBPLL_I2C_V << PMU_TIE_HIGH_XPD_BBPLL_I2C_S) +#define PMU_TIE_HIGH_XPD_BBPLL_I2C_V 0x00000001U +#define PMU_TIE_HIGH_XPD_BBPLL_I2C_S 29 +/** PMU_TIE_HIGH_XPD_BBPLL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_BBPLL (BIT(30)) +#define PMU_TIE_HIGH_XPD_BBPLL_M (PMU_TIE_HIGH_XPD_BBPLL_V << PMU_TIE_HIGH_XPD_BBPLL_S) +#define PMU_TIE_HIGH_XPD_BBPLL_V 0x00000001U +#define PMU_TIE_HIGH_XPD_BBPLL_S 30 +/** PMU_TIE_HIGH_XPD_XTAL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XPD_XTAL (BIT(31)) +#define PMU_TIE_HIGH_XPD_XTAL_M (PMU_TIE_HIGH_XPD_XTAL_V << PMU_TIE_HIGH_XPD_XTAL_S) +#define PMU_TIE_HIGH_XPD_XTAL_V 0x00000001U +#define PMU_TIE_HIGH_XPD_XTAL_S 31 + +/** PMU_IMM_SLEEP_SYSCLK_REG register + * need_des + */ +#define PMU_IMM_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0xd0) +/** PMU_UPDATE_DIG_ICG_SWITCH : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_SWITCH (BIT(28)) +#define PMU_UPDATE_DIG_ICG_SWITCH_M (PMU_UPDATE_DIG_ICG_SWITCH_V << PMU_UPDATE_DIG_ICG_SWITCH_S) +#define PMU_UPDATE_DIG_ICG_SWITCH_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_SWITCH_S 28 +/** PMU_TIE_LOW_ICG_SLP_SEL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_ICG_SLP_SEL (BIT(29)) +#define PMU_TIE_LOW_ICG_SLP_SEL_M (PMU_TIE_LOW_ICG_SLP_SEL_V << PMU_TIE_LOW_ICG_SLP_SEL_S) +#define PMU_TIE_LOW_ICG_SLP_SEL_V 0x00000001U +#define PMU_TIE_LOW_ICG_SLP_SEL_S 29 +/** PMU_TIE_HIGH_ICG_SLP_SEL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_ICG_SLP_SEL (BIT(30)) +#define PMU_TIE_HIGH_ICG_SLP_SEL_M (PMU_TIE_HIGH_ICG_SLP_SEL_V << PMU_TIE_HIGH_ICG_SLP_SEL_S) +#define PMU_TIE_HIGH_ICG_SLP_SEL_V 0x00000001U +#define PMU_TIE_HIGH_ICG_SLP_SEL_S 30 +/** PMU_UPDATE_DIG_SYS_CLK_SEL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_SYS_CLK_SEL (BIT(31)) +#define PMU_UPDATE_DIG_SYS_CLK_SEL_M (PMU_UPDATE_DIG_SYS_CLK_SEL_V << PMU_UPDATE_DIG_SYS_CLK_SEL_S) +#define PMU_UPDATE_DIG_SYS_CLK_SEL_V 0x00000001U +#define PMU_UPDATE_DIG_SYS_CLK_SEL_S 31 + +/** PMU_IMM_HP_FUNC_ICG_REG register + * need_des + */ +#define PMU_IMM_HP_FUNC_ICG_REG (DR_REG_PMU_BASE + 0xd4) +/** PMU_UPDATE_DIG_ICG_FUNC_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_FUNC_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_FUNC_EN_M (PMU_UPDATE_DIG_ICG_FUNC_EN_V << PMU_UPDATE_DIG_ICG_FUNC_EN_S) +#define PMU_UPDATE_DIG_ICG_FUNC_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_FUNC_EN_S 31 + +/** PMU_IMM_HP_APB_ICG_REG register + * need_des + */ +#define PMU_IMM_HP_APB_ICG_REG (DR_REG_PMU_BASE + 0xd8) +/** PMU_UPDATE_DIG_ICG_APB_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_APB_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_APB_EN_M (PMU_UPDATE_DIG_ICG_APB_EN_V << PMU_UPDATE_DIG_ICG_APB_EN_S) +#define PMU_UPDATE_DIG_ICG_APB_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_APB_EN_S 31 + +/** PMU_IMM_MODEM_ICG_REG register + * need_des + */ +#define PMU_IMM_MODEM_ICG_REG (DR_REG_PMU_BASE + 0xdc) +/** PMU_UPDATE_DIG_ICG_MODEM_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_UPDATE_DIG_ICG_MODEM_EN (BIT(31)) +#define PMU_UPDATE_DIG_ICG_MODEM_EN_M (PMU_UPDATE_DIG_ICG_MODEM_EN_V << PMU_UPDATE_DIG_ICG_MODEM_EN_S) +#define PMU_UPDATE_DIG_ICG_MODEM_EN_V 0x00000001U +#define PMU_UPDATE_DIG_ICG_MODEM_EN_S 31 + +/** PMU_IMM_LP_ICG_REG register + * need_des + */ +#define PMU_IMM_LP_ICG_REG (DR_REG_PMU_BASE + 0xe0) +/** PMU_TIE_LOW_LP_ROOTCLK_SEL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_LP_ROOTCLK_SEL (BIT(30)) +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_M (PMU_TIE_LOW_LP_ROOTCLK_SEL_V << PMU_TIE_LOW_LP_ROOTCLK_SEL_S) +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_V 0x00000001U +#define PMU_TIE_LOW_LP_ROOTCLK_SEL_S 30 +/** PMU_TIE_HIGH_LP_ROOTCLK_SEL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL (BIT(31)) +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_M (PMU_TIE_HIGH_LP_ROOTCLK_SEL_V << PMU_TIE_HIGH_LP_ROOTCLK_SEL_S) +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_V 0x00000001U +#define PMU_TIE_HIGH_LP_ROOTCLK_SEL_S 31 + +/** PMU_IMM_PAD_HOLD_ALL_REG register + * need_des + */ +#define PMU_IMM_PAD_HOLD_ALL_REG (DR_REG_PMU_BASE + 0xe4) +/** PMU_TIE_HIGH_LP_PAD_HOLD_ALL : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL (BIT(28)) +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S) +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S 28 +/** PMU_TIE_LOW_LP_PAD_HOLD_ALL : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL (BIT(29)) +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_M (PMU_TIE_LOW_LP_PAD_HOLD_ALL_V << PMU_TIE_LOW_LP_PAD_HOLD_ALL_S) +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_LOW_LP_PAD_HOLD_ALL_S 29 +/** PMU_TIE_HIGH_HP_PAD_HOLD_ALL : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL (BIT(30)) +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S) +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S 30 +/** PMU_TIE_LOW_HP_PAD_HOLD_ALL : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL (BIT(31)) +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_M (PMU_TIE_LOW_HP_PAD_HOLD_ALL_V << PMU_TIE_LOW_HP_PAD_HOLD_ALL_S) +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_V 0x00000001U +#define PMU_TIE_LOW_HP_PAD_HOLD_ALL_S 31 + +/** PMU_IMM_I2C_ISO_REG register + * need_des + */ +#define PMU_IMM_I2C_ISO_REG (DR_REG_PMU_BASE + 0xe8) +/** PMU_TIE_HIGH_I2C_ISO_EN : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_I2C_ISO_EN (BIT(30)) +#define PMU_TIE_HIGH_I2C_ISO_EN_M (PMU_TIE_HIGH_I2C_ISO_EN_V << PMU_TIE_HIGH_I2C_ISO_EN_S) +#define PMU_TIE_HIGH_I2C_ISO_EN_V 0x00000001U +#define PMU_TIE_HIGH_I2C_ISO_EN_S 30 +/** PMU_TIE_LOW_I2C_ISO_EN : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_I2C_ISO_EN (BIT(31)) +#define PMU_TIE_LOW_I2C_ISO_EN_M (PMU_TIE_LOW_I2C_ISO_EN_V << PMU_TIE_LOW_I2C_ISO_EN_S) +#define PMU_TIE_LOW_I2C_ISO_EN_V 0x00000001U +#define PMU_TIE_LOW_I2C_ISO_EN_S 31 + +/** PMU_POWER_WAIT_TIMER0_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER0_REG (DR_REG_PMU_BASE + 0xec) +/** PMU_DG_HP_POWERDOWN_TIMER : R/W; bitpos: [13:5]; default: 255; + * need_des + */ +#define PMU_DG_HP_POWERDOWN_TIMER 0x000001FFU +#define PMU_DG_HP_POWERDOWN_TIMER_M (PMU_DG_HP_POWERDOWN_TIMER_V << PMU_DG_HP_POWERDOWN_TIMER_S) +#define PMU_DG_HP_POWERDOWN_TIMER_V 0x000001FFU +#define PMU_DG_HP_POWERDOWN_TIMER_S 5 +/** PMU_DG_HP_POWERUP_TIMER : R/W; bitpos: [22:14]; default: 255; + * need_des + */ +#define PMU_DG_HP_POWERUP_TIMER 0x000001FFU +#define PMU_DG_HP_POWERUP_TIMER_M (PMU_DG_HP_POWERUP_TIMER_V << PMU_DG_HP_POWERUP_TIMER_S) +#define PMU_DG_HP_POWERUP_TIMER_V 0x000001FFU +#define PMU_DG_HP_POWERUP_TIMER_S 14 +/** PMU_DG_HP_PD_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; + * need_des + */ +#define PMU_DG_HP_PD_WAIT_TIMER 0x000001FFU +#define PMU_DG_HP_PD_WAIT_TIMER_M (PMU_DG_HP_PD_WAIT_TIMER_V << PMU_DG_HP_PD_WAIT_TIMER_S) +#define PMU_DG_HP_PD_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_HP_PD_WAIT_TIMER_S 23 + +/** PMU_POWER_WAIT_TIMER1_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER1_REG (DR_REG_PMU_BASE + 0xf0) +/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [15:9]; default: 63; + * need_des + */ +#define PMU_DG_LP_POWERDOWN_TIMER 0x0000007FU +#define PMU_DG_LP_POWERDOWN_TIMER_M (PMU_DG_LP_POWERDOWN_TIMER_V << PMU_DG_LP_POWERDOWN_TIMER_S) +#define PMU_DG_LP_POWERDOWN_TIMER_V 0x0000007FU +#define PMU_DG_LP_POWERDOWN_TIMER_S 9 +/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:16]; default: 63; + * need_des + */ +#define PMU_DG_LP_POWERUP_TIMER 0x0000007FU +#define PMU_DG_LP_POWERUP_TIMER_M (PMU_DG_LP_POWERUP_TIMER_V << PMU_DG_LP_POWERUP_TIMER_S) +#define PMU_DG_LP_POWERUP_TIMER_V 0x0000007FU +#define PMU_DG_LP_POWERUP_TIMER_S 16 +/** PMU_DG_LP_PD_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; + * need_des + */ +#define PMU_DG_LP_PD_WAIT_TIMER 0x000001FFU +#define PMU_DG_LP_PD_WAIT_TIMER_M (PMU_DG_LP_PD_WAIT_TIMER_V << PMU_DG_LP_PD_WAIT_TIMER_S) +#define PMU_DG_LP_PD_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_LP_PD_WAIT_TIMER_S 23 + +/** PMU_POWER_WAIT_TIMER2_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER2_REG (DR_REG_PMU_BASE + 0xf4) +/** PMU_DG_LP_ISO_WAIT_TIMER : R/W; bitpos: [7:0]; default: 255; + * need_des + */ +#define PMU_DG_LP_ISO_WAIT_TIMER 0x000000FFU +#define PMU_DG_LP_ISO_WAIT_TIMER_M (PMU_DG_LP_ISO_WAIT_TIMER_V << PMU_DG_LP_ISO_WAIT_TIMER_S) +#define PMU_DG_LP_ISO_WAIT_TIMER_V 0x000000FFU +#define PMU_DG_LP_ISO_WAIT_TIMER_S 0 +/** PMU_DG_LP_RST_WAIT_TIMER : R/W; bitpos: [15:8]; default: 255; + * need_des + */ +#define PMU_DG_LP_RST_WAIT_TIMER 0x000000FFU +#define PMU_DG_LP_RST_WAIT_TIMER_M (PMU_DG_LP_RST_WAIT_TIMER_V << PMU_DG_LP_RST_WAIT_TIMER_S) +#define PMU_DG_LP_RST_WAIT_TIMER_V 0x000000FFU +#define PMU_DG_LP_RST_WAIT_TIMER_S 8 +/** PMU_DG_HP_ISO_WAIT_TIMER : R/W; bitpos: [23:16]; default: 255; + * need_des + */ +#define PMU_DG_HP_ISO_WAIT_TIMER 0x000000FFU +#define PMU_DG_HP_ISO_WAIT_TIMER_M (PMU_DG_HP_ISO_WAIT_TIMER_V << PMU_DG_HP_ISO_WAIT_TIMER_S) +#define PMU_DG_HP_ISO_WAIT_TIMER_V 0x000000FFU +#define PMU_DG_HP_ISO_WAIT_TIMER_S 16 +/** PMU_DG_HP_RST_WAIT_TIMER : R/W; bitpos: [31:24]; default: 255; + * need_des + */ +#define PMU_DG_HP_RST_WAIT_TIMER 0x000000FFU +#define PMU_DG_HP_RST_WAIT_TIMER_M (PMU_DG_HP_RST_WAIT_TIMER_V << PMU_DG_HP_RST_WAIT_TIMER_S) +#define PMU_DG_HP_RST_WAIT_TIMER_V 0x000000FFU +#define PMU_DG_HP_RST_WAIT_TIMER_S 24 + +/** PMU_POWER_PD_TOP_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf8) +/** PMU_FORCE_TOP_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_RESET (BIT(0)) +#define PMU_FORCE_TOP_RESET_M (PMU_FORCE_TOP_RESET_V << PMU_FORCE_TOP_RESET_S) +#define PMU_FORCE_TOP_RESET_V 0x00000001U +#define PMU_FORCE_TOP_RESET_S 0 +/** PMU_FORCE_TOP_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_ISO (BIT(1)) +#define PMU_FORCE_TOP_ISO_M (PMU_FORCE_TOP_ISO_V << PMU_FORCE_TOP_ISO_S) +#define PMU_FORCE_TOP_ISO_V 0x00000001U +#define PMU_FORCE_TOP_ISO_S 1 +/** PMU_FORCE_TOP_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_PU (BIT(2)) +#define PMU_FORCE_TOP_PU_M (PMU_FORCE_TOP_PU_V << PMU_FORCE_TOP_PU_S) +#define PMU_FORCE_TOP_PU_V 0x00000001U +#define PMU_FORCE_TOP_PU_S 2 +/** PMU_FORCE_TOP_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_NO_RESET (BIT(3)) +#define PMU_FORCE_TOP_NO_RESET_M (PMU_FORCE_TOP_NO_RESET_V << PMU_FORCE_TOP_NO_RESET_S) +#define PMU_FORCE_TOP_NO_RESET_V 0x00000001U +#define PMU_FORCE_TOP_NO_RESET_S 3 +/** PMU_FORCE_TOP_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_TOP_NO_ISO (BIT(4)) +#define PMU_FORCE_TOP_NO_ISO_M (PMU_FORCE_TOP_NO_ISO_V << PMU_FORCE_TOP_NO_ISO_S) +#define PMU_FORCE_TOP_NO_ISO_V 0x00000001U +#define PMU_FORCE_TOP_NO_ISO_S 4 +/** PMU_FORCE_TOP_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_TOP_PD (BIT(5)) +#define PMU_FORCE_TOP_PD_M (PMU_FORCE_TOP_PD_V << PMU_FORCE_TOP_PD_S) +#define PMU_FORCE_TOP_PD_V 0x00000001U +#define PMU_FORCE_TOP_PD_S 5 +/** PMU_PD_TOP_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_TOP_MASK 0x0000001FU +#define PMU_PD_TOP_MASK_M (PMU_PD_TOP_MASK_V << PMU_PD_TOP_MASK_S) +#define PMU_PD_TOP_MASK_V 0x0000001FU +#define PMU_PD_TOP_MASK_S 6 +/** PMU_PD_TOP_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_TOP_PD_MASK 0x0000001FU +#define PMU_PD_TOP_PD_MASK_M (PMU_PD_TOP_PD_MASK_V << PMU_PD_TOP_PD_MASK_S) +#define PMU_PD_TOP_PD_MASK_V 0x0000001FU +#define PMU_PD_TOP_PD_MASK_S 27 + +/** PMU_POWER_PD_HPAON_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPAON_CNTL_REG (DR_REG_PMU_BASE + 0xfc) +/** PMU_FORCE_HP_AON_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_AON_RESET (BIT(0)) +#define PMU_FORCE_HP_AON_RESET_M (PMU_FORCE_HP_AON_RESET_V << PMU_FORCE_HP_AON_RESET_S) +#define PMU_FORCE_HP_AON_RESET_V 0x00000001U +#define PMU_FORCE_HP_AON_RESET_S 0 +/** PMU_FORCE_HP_AON_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_AON_ISO (BIT(1)) +#define PMU_FORCE_HP_AON_ISO_M (PMU_FORCE_HP_AON_ISO_V << PMU_FORCE_HP_AON_ISO_S) +#define PMU_FORCE_HP_AON_ISO_V 0x00000001U +#define PMU_FORCE_HP_AON_ISO_S 1 +/** PMU_FORCE_HP_AON_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_AON_PU (BIT(2)) +#define PMU_FORCE_HP_AON_PU_M (PMU_FORCE_HP_AON_PU_V << PMU_FORCE_HP_AON_PU_S) +#define PMU_FORCE_HP_AON_PU_V 0x00000001U +#define PMU_FORCE_HP_AON_PU_S 2 +/** PMU_FORCE_HP_AON_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_AON_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_AON_NO_RESET_M (PMU_FORCE_HP_AON_NO_RESET_V << PMU_FORCE_HP_AON_NO_RESET_S) +#define PMU_FORCE_HP_AON_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_AON_NO_RESET_S 3 +/** PMU_FORCE_HP_AON_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_AON_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_AON_NO_ISO_M (PMU_FORCE_HP_AON_NO_ISO_V << PMU_FORCE_HP_AON_NO_ISO_S) +#define PMU_FORCE_HP_AON_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_AON_NO_ISO_S 4 +/** PMU_FORCE_HP_AON_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_AON_PD (BIT(5)) +#define PMU_FORCE_HP_AON_PD_M (PMU_FORCE_HP_AON_PD_V << PMU_FORCE_HP_AON_PD_S) +#define PMU_FORCE_HP_AON_PD_V 0x00000001U +#define PMU_FORCE_HP_AON_PD_S 5 +/** PMU_PD_HP_AON_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_AON_MASK 0x0000001FU +#define PMU_PD_HP_AON_MASK_M (PMU_PD_HP_AON_MASK_V << PMU_PD_HP_AON_MASK_S) +#define PMU_PD_HP_AON_MASK_V 0x0000001FU +#define PMU_PD_HP_AON_MASK_S 6 +/** PMU_PD_HP_AON_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_AON_PD_MASK 0x0000001FU +#define PMU_PD_HP_AON_PD_MASK_M (PMU_PD_HP_AON_PD_MASK_V << PMU_PD_HP_AON_PD_MASK_S) +#define PMU_PD_HP_AON_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_AON_PD_MASK_S 27 + +/** PMU_POWER_PD_HPCPU_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPCPU_CNTL_REG (DR_REG_PMU_BASE + 0x100) +/** PMU_FORCE_HP_CPU_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_RESET (BIT(0)) +#define PMU_FORCE_HP_CPU_RESET_M (PMU_FORCE_HP_CPU_RESET_V << PMU_FORCE_HP_CPU_RESET_S) +#define PMU_FORCE_HP_CPU_RESET_V 0x00000001U +#define PMU_FORCE_HP_CPU_RESET_S 0 +/** PMU_FORCE_HP_CPU_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_ISO (BIT(1)) +#define PMU_FORCE_HP_CPU_ISO_M (PMU_FORCE_HP_CPU_ISO_V << PMU_FORCE_HP_CPU_ISO_S) +#define PMU_FORCE_HP_CPU_ISO_V 0x00000001U +#define PMU_FORCE_HP_CPU_ISO_S 1 +/** PMU_FORCE_HP_CPU_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_PU (BIT(2)) +#define PMU_FORCE_HP_CPU_PU_M (PMU_FORCE_HP_CPU_PU_V << PMU_FORCE_HP_CPU_PU_S) +#define PMU_FORCE_HP_CPU_PU_V 0x00000001U +#define PMU_FORCE_HP_CPU_PU_S 2 +/** PMU_FORCE_HP_CPU_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_CPU_NO_RESET_M (PMU_FORCE_HP_CPU_NO_RESET_V << PMU_FORCE_HP_CPU_NO_RESET_S) +#define PMU_FORCE_HP_CPU_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_CPU_NO_RESET_S 3 +/** PMU_FORCE_HP_CPU_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_CPU_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_CPU_NO_ISO_M (PMU_FORCE_HP_CPU_NO_ISO_V << PMU_FORCE_HP_CPU_NO_ISO_S) +#define PMU_FORCE_HP_CPU_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_CPU_NO_ISO_S 4 +/** PMU_FORCE_HP_CPU_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_CPU_PD (BIT(5)) +#define PMU_FORCE_HP_CPU_PD_M (PMU_FORCE_HP_CPU_PD_V << PMU_FORCE_HP_CPU_PD_S) +#define PMU_FORCE_HP_CPU_PD_V 0x00000001U +#define PMU_FORCE_HP_CPU_PD_S 5 +/** PMU_PD_HP_CPU_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_CPU_MASK 0x0000001FU +#define PMU_PD_HP_CPU_MASK_M (PMU_PD_HP_CPU_MASK_V << PMU_PD_HP_CPU_MASK_S) +#define PMU_PD_HP_CPU_MASK_V 0x0000001FU +#define PMU_PD_HP_CPU_MASK_S 6 +/** PMU_PD_HP_CPU_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_CPU_PD_MASK 0x0000001FU +#define PMU_PD_HP_CPU_PD_MASK_M (PMU_PD_HP_CPU_PD_MASK_V << PMU_PD_HP_CPU_PD_MASK_S) +#define PMU_PD_HP_CPU_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_CPU_PD_MASK_S 27 + +/** PMU_POWER_PD_HPPERI_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x104) +/** PMU_FORCE_HP_PERI_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PERI_RESET (BIT(0)) +#define PMU_FORCE_HP_PERI_RESET_M (PMU_FORCE_HP_PERI_RESET_V << PMU_FORCE_HP_PERI_RESET_S) +#define PMU_FORCE_HP_PERI_RESET_V 0x00000001U +#define PMU_FORCE_HP_PERI_RESET_S 0 +/** PMU_FORCE_HP_PERI_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PERI_ISO (BIT(1)) +#define PMU_FORCE_HP_PERI_ISO_M (PMU_FORCE_HP_PERI_ISO_V << PMU_FORCE_HP_PERI_ISO_S) +#define PMU_FORCE_HP_PERI_ISO_V 0x00000001U +#define PMU_FORCE_HP_PERI_ISO_S 1 +/** PMU_FORCE_HP_PERI_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_PERI_PU (BIT(2)) +#define PMU_FORCE_HP_PERI_PU_M (PMU_FORCE_HP_PERI_PU_V << PMU_FORCE_HP_PERI_PU_S) +#define PMU_FORCE_HP_PERI_PU_V 0x00000001U +#define PMU_FORCE_HP_PERI_PU_S 2 +/** PMU_FORCE_HP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_PERI_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_PERI_NO_RESET_M (PMU_FORCE_HP_PERI_NO_RESET_V << PMU_FORCE_HP_PERI_NO_RESET_S) +#define PMU_FORCE_HP_PERI_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_PERI_NO_RESET_S 3 +/** PMU_FORCE_HP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_PERI_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_PERI_NO_ISO_M (PMU_FORCE_HP_PERI_NO_ISO_V << PMU_FORCE_HP_PERI_NO_ISO_S) +#define PMU_FORCE_HP_PERI_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_PERI_NO_ISO_S 4 +/** PMU_FORCE_HP_PERI_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PERI_PD (BIT(5)) +#define PMU_FORCE_HP_PERI_PD_M (PMU_FORCE_HP_PERI_PD_V << PMU_FORCE_HP_PERI_PD_S) +#define PMU_FORCE_HP_PERI_PD_V 0x00000001U +#define PMU_FORCE_HP_PERI_PD_S 5 +/** PMU_PD_HP_PERI_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_PERI_MASK 0x0000001FU +#define PMU_PD_HP_PERI_MASK_M (PMU_PD_HP_PERI_MASK_V << PMU_PD_HP_PERI_MASK_S) +#define PMU_PD_HP_PERI_MASK_V 0x0000001FU +#define PMU_PD_HP_PERI_MASK_S 6 +/** PMU_PD_HP_PERI_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_PERI_PD_MASK 0x0000001FU +#define PMU_PD_HP_PERI_PD_MASK_M (PMU_PD_HP_PERI_PD_MASK_V << PMU_PD_HP_PERI_PD_MASK_S) +#define PMU_PD_HP_PERI_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_PERI_PD_MASK_S 27 + +/** PMU_POWER_PD_HPWIFI_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_HPWIFI_CNTL_REG (DR_REG_PMU_BASE + 0x108) +/** PMU_FORCE_HP_WIFI_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_WIFI_RESET (BIT(0)) +#define PMU_FORCE_HP_WIFI_RESET_M (PMU_FORCE_HP_WIFI_RESET_V << PMU_FORCE_HP_WIFI_RESET_S) +#define PMU_FORCE_HP_WIFI_RESET_V 0x00000001U +#define PMU_FORCE_HP_WIFI_RESET_S 0 +/** PMU_FORCE_HP_WIFI_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_WIFI_ISO (BIT(1)) +#define PMU_FORCE_HP_WIFI_ISO_M (PMU_FORCE_HP_WIFI_ISO_V << PMU_FORCE_HP_WIFI_ISO_S) +#define PMU_FORCE_HP_WIFI_ISO_V 0x00000001U +#define PMU_FORCE_HP_WIFI_ISO_S 1 +/** PMU_FORCE_HP_WIFI_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_WIFI_PU (BIT(2)) +#define PMU_FORCE_HP_WIFI_PU_M (PMU_FORCE_HP_WIFI_PU_V << PMU_FORCE_HP_WIFI_PU_S) +#define PMU_FORCE_HP_WIFI_PU_V 0x00000001U +#define PMU_FORCE_HP_WIFI_PU_S 2 +/** PMU_FORCE_HP_WIFI_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_WIFI_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_WIFI_NO_RESET_M (PMU_FORCE_HP_WIFI_NO_RESET_V << PMU_FORCE_HP_WIFI_NO_RESET_S) +#define PMU_FORCE_HP_WIFI_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_WIFI_NO_RESET_S 3 +/** PMU_FORCE_HP_WIFI_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_WIFI_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_WIFI_NO_ISO_M (PMU_FORCE_HP_WIFI_NO_ISO_V << PMU_FORCE_HP_WIFI_NO_ISO_S) +#define PMU_FORCE_HP_WIFI_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_WIFI_NO_ISO_S 4 +/** PMU_FORCE_HP_WIFI_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_WIFI_PD (BIT(5)) +#define PMU_FORCE_HP_WIFI_PD_M (PMU_FORCE_HP_WIFI_PD_V << PMU_FORCE_HP_WIFI_PD_S) +#define PMU_FORCE_HP_WIFI_PD_V 0x00000001U +#define PMU_FORCE_HP_WIFI_PD_S 5 +/** PMU_PD_HP_WIFI_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_WIFI_MASK 0x0000001FU +#define PMU_PD_HP_WIFI_MASK_M (PMU_PD_HP_WIFI_MASK_V << PMU_PD_HP_WIFI_MASK_S) +#define PMU_PD_HP_WIFI_MASK_V 0x0000001FU +#define PMU_PD_HP_WIFI_MASK_S 6 +/** PMU_PD_HP_WIFI_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_WIFI_PD_MASK 0x0000001FU +#define PMU_PD_HP_WIFI_PD_MASK_M (PMU_PD_HP_WIFI_PD_MASK_V << PMU_PD_HP_WIFI_PD_MASK_S) +#define PMU_PD_HP_WIFI_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_WIFI_PD_MASK_S 27 + +/** PMU_POWER_PD_LPPERI_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x10c) +/** PMU_FORCE_LP_PERI_RESET : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_RESET (BIT(0)) +#define PMU_FORCE_LP_PERI_RESET_M (PMU_FORCE_LP_PERI_RESET_V << PMU_FORCE_LP_PERI_RESET_S) +#define PMU_FORCE_LP_PERI_RESET_V 0x00000001U +#define PMU_FORCE_LP_PERI_RESET_S 0 +/** PMU_FORCE_LP_PERI_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_ISO (BIT(1)) +#define PMU_FORCE_LP_PERI_ISO_M (PMU_FORCE_LP_PERI_ISO_V << PMU_FORCE_LP_PERI_ISO_S) +#define PMU_FORCE_LP_PERI_ISO_V 0x00000001U +#define PMU_FORCE_LP_PERI_ISO_S 1 +/** PMU_FORCE_LP_PERI_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_PU (BIT(2)) +#define PMU_FORCE_LP_PERI_PU_M (PMU_FORCE_LP_PERI_PU_V << PMU_FORCE_LP_PERI_PU_S) +#define PMU_FORCE_LP_PERI_PU_V 0x00000001U +#define PMU_FORCE_LP_PERI_PU_S 2 +/** PMU_FORCE_LP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_NO_RESET (BIT(3)) +#define PMU_FORCE_LP_PERI_NO_RESET_M (PMU_FORCE_LP_PERI_NO_RESET_V << PMU_FORCE_LP_PERI_NO_RESET_S) +#define PMU_FORCE_LP_PERI_NO_RESET_V 0x00000001U +#define PMU_FORCE_LP_PERI_NO_RESET_S 3 +/** PMU_FORCE_LP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_LP_PERI_NO_ISO (BIT(4)) +#define PMU_FORCE_LP_PERI_NO_ISO_M (PMU_FORCE_LP_PERI_NO_ISO_V << PMU_FORCE_LP_PERI_NO_ISO_S) +#define PMU_FORCE_LP_PERI_NO_ISO_V 0x00000001U +#define PMU_FORCE_LP_PERI_NO_ISO_S 4 +/** PMU_FORCE_LP_PERI_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_LP_PERI_PD (BIT(5)) +#define PMU_FORCE_LP_PERI_PD_M (PMU_FORCE_LP_PERI_PD_V << PMU_FORCE_LP_PERI_PD_S) +#define PMU_FORCE_LP_PERI_PD_V 0x00000001U +#define PMU_FORCE_LP_PERI_PD_S 5 + +/** PMU_POWER_PD_MEM_CNTL_REG register + * need_des + */ +#define PMU_POWER_PD_MEM_CNTL_REG (DR_REG_PMU_BASE + 0x110) +/** PMU_FORCE_HP_MEM_ISO : R/W; bitpos: [3:0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_MEM_ISO 0x0000000FU +#define PMU_FORCE_HP_MEM_ISO_M (PMU_FORCE_HP_MEM_ISO_V << PMU_FORCE_HP_MEM_ISO_S) +#define PMU_FORCE_HP_MEM_ISO_V 0x0000000FU +#define PMU_FORCE_HP_MEM_ISO_S 0 +/** PMU_FORCE_HP_MEM_PD : R/W; bitpos: [7:4]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_MEM_PD 0x0000000FU +#define PMU_FORCE_HP_MEM_PD_M (PMU_FORCE_HP_MEM_PD_V << PMU_FORCE_HP_MEM_PD_S) +#define PMU_FORCE_HP_MEM_PD_V 0x0000000FU +#define PMU_FORCE_HP_MEM_PD_S 4 +/** PMU_FORCE_HP_MEM_NO_ISO : R/W; bitpos: [27:24]; default: 15; + * need_des + */ +#define PMU_FORCE_HP_MEM_NO_ISO 0x0000000FU +#define PMU_FORCE_HP_MEM_NO_ISO_M (PMU_FORCE_HP_MEM_NO_ISO_V << PMU_FORCE_HP_MEM_NO_ISO_S) +#define PMU_FORCE_HP_MEM_NO_ISO_V 0x0000000FU +#define PMU_FORCE_HP_MEM_NO_ISO_S 24 +/** PMU_FORCE_HP_MEM_PU : R/W; bitpos: [31:28]; default: 15; + * need_des + */ +#define PMU_FORCE_HP_MEM_PU 0x0000000FU +#define PMU_FORCE_HP_MEM_PU_M (PMU_FORCE_HP_MEM_PU_V << PMU_FORCE_HP_MEM_PU_S) +#define PMU_FORCE_HP_MEM_PU_V 0x0000000FU +#define PMU_FORCE_HP_MEM_PU_S 28 + +/** PMU_POWER_PD_MEM_MASK_REG register + * need_des + */ +#define PMU_POWER_PD_MEM_MASK_REG (DR_REG_PMU_BASE + 0x114) +/** PMU_PD_HP_MEM2_PD_MASK : R/W; bitpos: [4:0]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM2_PD_MASK 0x0000001FU +#define PMU_PD_HP_MEM2_PD_MASK_M (PMU_PD_HP_MEM2_PD_MASK_V << PMU_PD_HP_MEM2_PD_MASK_S) +#define PMU_PD_HP_MEM2_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM2_PD_MASK_S 0 +/** PMU_PD_HP_MEM1_PD_MASK : R/W; bitpos: [9:5]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM1_PD_MASK 0x0000001FU +#define PMU_PD_HP_MEM1_PD_MASK_M (PMU_PD_HP_MEM1_PD_MASK_V << PMU_PD_HP_MEM1_PD_MASK_S) +#define PMU_PD_HP_MEM1_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM1_PD_MASK_S 5 +/** PMU_PD_HP_MEM0_PD_MASK : R/W; bitpos: [14:10]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM0_PD_MASK 0x0000001FU +#define PMU_PD_HP_MEM0_PD_MASK_M (PMU_PD_HP_MEM0_PD_MASK_V << PMU_PD_HP_MEM0_PD_MASK_S) +#define PMU_PD_HP_MEM0_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM0_PD_MASK_S 10 +/** PMU_PD_HP_MEM2_MASK : R/W; bitpos: [21:17]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM2_MASK 0x0000001FU +#define PMU_PD_HP_MEM2_MASK_M (PMU_PD_HP_MEM2_MASK_V << PMU_PD_HP_MEM2_MASK_S) +#define PMU_PD_HP_MEM2_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM2_MASK_S 17 +/** PMU_PD_HP_MEM1_MASK : R/W; bitpos: [26:22]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM1_MASK 0x0000001FU +#define PMU_PD_HP_MEM1_MASK_M (PMU_PD_HP_MEM1_MASK_V << PMU_PD_HP_MEM1_MASK_S) +#define PMU_PD_HP_MEM1_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM1_MASK_S 22 +/** PMU_PD_HP_MEM0_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_MEM0_MASK 0x0000001FU +#define PMU_PD_HP_MEM0_MASK_M (PMU_PD_HP_MEM0_MASK_V << PMU_PD_HP_MEM0_MASK_S) +#define PMU_PD_HP_MEM0_MASK_V 0x0000001FU +#define PMU_PD_HP_MEM0_MASK_S 27 + +/** PMU_POWER_HP_PAD_REG register + * need_des + */ +#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x118) +/** PMU_FORCE_HP_PAD_NO_ISO_ALL : R/W; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PAD_NO_ISO_ALL (BIT(0)) +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_M (PMU_FORCE_HP_PAD_NO_ISO_ALL_V << PMU_FORCE_HP_PAD_NO_ISO_ALL_S) +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_V 0x00000001U +#define PMU_FORCE_HP_PAD_NO_ISO_ALL_S 0 +/** PMU_FORCE_HP_PAD_ISO_ALL : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PAD_ISO_ALL (BIT(1)) +#define PMU_FORCE_HP_PAD_ISO_ALL_M (PMU_FORCE_HP_PAD_ISO_ALL_V << PMU_FORCE_HP_PAD_ISO_ALL_S) +#define PMU_FORCE_HP_PAD_ISO_ALL_V 0x00000001U +#define PMU_FORCE_HP_PAD_ISO_ALL_S 1 + +/** PMU_POWER_VDD_SPI_CNTL_REG register + * need_des + */ +#define PMU_POWER_VDD_SPI_CNTL_REG (DR_REG_PMU_BASE + 0x11c) +/** PMU_VDD_SPI_PWR_WAIT : R/W; bitpos: [28:18]; default: 255; + * need_des + */ +#define PMU_VDD_SPI_PWR_WAIT 0x000007FFU +#define PMU_VDD_SPI_PWR_WAIT_M (PMU_VDD_SPI_PWR_WAIT_V << PMU_VDD_SPI_PWR_WAIT_S) +#define PMU_VDD_SPI_PWR_WAIT_V 0x000007FFU +#define PMU_VDD_SPI_PWR_WAIT_S 18 +/** PMU_VDD_SPI_PWR_SW : R/W; bitpos: [30:29]; default: 3; + * need_des + */ +#define PMU_VDD_SPI_PWR_SW 0x00000003U +#define PMU_VDD_SPI_PWR_SW_M (PMU_VDD_SPI_PWR_SW_V << PMU_VDD_SPI_PWR_SW_S) +#define PMU_VDD_SPI_PWR_SW_V 0x00000003U +#define PMU_VDD_SPI_PWR_SW_S 29 +/** PMU_VDD_SPI_PWR_SEL_SW : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_VDD_SPI_PWR_SEL_SW (BIT(31)) +#define PMU_VDD_SPI_PWR_SEL_SW_M (PMU_VDD_SPI_PWR_SEL_SW_V << PMU_VDD_SPI_PWR_SEL_SW_S) +#define PMU_VDD_SPI_PWR_SEL_SW_V 0x00000001U +#define PMU_VDD_SPI_PWR_SEL_SW_S 31 + +/** PMU_POWER_CK_WAIT_CNTL_REG register + * need_des + */ +#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x120) +/** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256; + * need_des + */ +#define PMU_WAIT_XTL_STABLE 0x0000FFFFU +#define PMU_WAIT_XTL_STABLE_M (PMU_WAIT_XTL_STABLE_V << PMU_WAIT_XTL_STABLE_S) +#define PMU_WAIT_XTL_STABLE_V 0x0000FFFFU +#define PMU_WAIT_XTL_STABLE_S 0 +/** PMU_WAIT_PLL_STABLE : R/W; bitpos: [31:16]; default: 256; + * need_des + */ +#define PMU_WAIT_PLL_STABLE 0x0000FFFFU +#define PMU_WAIT_PLL_STABLE_M (PMU_WAIT_PLL_STABLE_V << PMU_WAIT_PLL_STABLE_S) +#define PMU_WAIT_PLL_STABLE_V 0x0000FFFFU +#define PMU_WAIT_PLL_STABLE_S 16 + +/** PMU_SLP_WAKEUP_CNTL0_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x124) +/** PMU_SLEEP_REQ : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLEEP_REQ (BIT(31)) +#define PMU_SLEEP_REQ_M (PMU_SLEEP_REQ_V << PMU_SLEEP_REQ_S) +#define PMU_SLEEP_REQ_V 0x00000001U +#define PMU_SLEEP_REQ_S 31 + +/** PMU_SLP_WAKEUP_CNTL1_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x128) +/** PMU_SLEEP_REJECT_ENA : R/W; bitpos: [30:0]; default: 0; + * need_des + */ +#define PMU_SLEEP_REJECT_ENA 0x7FFFFFFFU +#define PMU_SLEEP_REJECT_ENA_M (PMU_SLEEP_REJECT_ENA_V << PMU_SLEEP_REJECT_ENA_S) +#define PMU_SLEEP_REJECT_ENA_V 0x7FFFFFFFU +#define PMU_SLEEP_REJECT_ENA_S 0 +/** PMU_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLP_REJECT_EN (BIT(31)) +#define PMU_SLP_REJECT_EN_M (PMU_SLP_REJECT_EN_V << PMU_SLP_REJECT_EN_S) +#define PMU_SLP_REJECT_EN_V 0x00000001U +#define PMU_SLP_REJECT_EN_S 31 + +/** PMU_SLP_WAKEUP_CNTL2_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x12c) +/** PMU_WAKEUP_ENA : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_WAKEUP_ENA 0xFFFFFFFFU +#define PMU_WAKEUP_ENA_M (PMU_WAKEUP_ENA_V << PMU_WAKEUP_ENA_S) +#define PMU_WAKEUP_ENA_V 0xFFFFFFFFU +#define PMU_WAKEUP_ENA_S 0 + +/** PMU_SLP_WAKEUP_CNTL3_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x130) +/** PMU_LP_MIN_SLP_VAL : R/W; bitpos: [7:0]; default: 0; + * need_des + */ +#define PMU_LP_MIN_SLP_VAL 0x000000FFU +#define PMU_LP_MIN_SLP_VAL_M (PMU_LP_MIN_SLP_VAL_V << PMU_LP_MIN_SLP_VAL_S) +#define PMU_LP_MIN_SLP_VAL_V 0x000000FFU +#define PMU_LP_MIN_SLP_VAL_S 0 +/** PMU_HP_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 0; + * need_des + */ +#define PMU_HP_MIN_SLP_VAL 0x000000FFU +#define PMU_HP_MIN_SLP_VAL_M (PMU_HP_MIN_SLP_VAL_V << PMU_HP_MIN_SLP_VAL_S) +#define PMU_HP_MIN_SLP_VAL_V 0x000000FFU +#define PMU_HP_MIN_SLP_VAL_S 8 +/** PMU_SLEEP_PRT_SEL : R/W; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_SLEEP_PRT_SEL 0x00000003U +#define PMU_SLEEP_PRT_SEL_M (PMU_SLEEP_PRT_SEL_V << PMU_SLEEP_PRT_SEL_S) +#define PMU_SLEEP_PRT_SEL_V 0x00000003U +#define PMU_SLEEP_PRT_SEL_S 16 + +/** PMU_SLP_WAKEUP_CNTL4_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x134) +/** PMU_SLP_REJECT_CAUSE_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SLP_REJECT_CAUSE_CLR (BIT(31)) +#define PMU_SLP_REJECT_CAUSE_CLR_M (PMU_SLP_REJECT_CAUSE_CLR_V << PMU_SLP_REJECT_CAUSE_CLR_S) +#define PMU_SLP_REJECT_CAUSE_CLR_V 0x00000001U +#define PMU_SLP_REJECT_CAUSE_CLR_S 31 + +/** PMU_SLP_WAKEUP_CNTL5_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x138) +/** PMU_MODEM_WAIT_TARGET : R/W; bitpos: [19:0]; default: 128; + * need_des + */ +#define PMU_MODEM_WAIT_TARGET 0x000FFFFFU +#define PMU_MODEM_WAIT_TARGET_M (PMU_MODEM_WAIT_TARGET_V << PMU_MODEM_WAIT_TARGET_S) +#define PMU_MODEM_WAIT_TARGET_V 0x000FFFFFU +#define PMU_MODEM_WAIT_TARGET_S 0 +/** PMU_LP_ANA_WAIT_TARGET : R/W; bitpos: [31:24]; default: 1; + * need_des + */ +#define PMU_LP_ANA_WAIT_TARGET 0x000000FFU +#define PMU_LP_ANA_WAIT_TARGET_M (PMU_LP_ANA_WAIT_TARGET_V << PMU_LP_ANA_WAIT_TARGET_S) +#define PMU_LP_ANA_WAIT_TARGET_V 0x000000FFU +#define PMU_LP_ANA_WAIT_TARGET_S 24 + +/** PMU_SLP_WAKEUP_CNTL6_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x13c) +/** PMU_SOC_WAKEUP_WAIT : R/W; bitpos: [19:0]; default: 128; + * need_des + */ +#define PMU_SOC_WAKEUP_WAIT 0x000FFFFFU +#define PMU_SOC_WAKEUP_WAIT_M (PMU_SOC_WAKEUP_WAIT_V << PMU_SOC_WAKEUP_WAIT_S) +#define PMU_SOC_WAKEUP_WAIT_V 0x000FFFFFU +#define PMU_SOC_WAKEUP_WAIT_S 0 +/** PMU_SOC_WAKEUP_WAIT_CFG : R/W; bitpos: [31:30]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_WAIT_CFG 0x00000003U +#define PMU_SOC_WAKEUP_WAIT_CFG_M (PMU_SOC_WAKEUP_WAIT_CFG_V << PMU_SOC_WAKEUP_WAIT_CFG_S) +#define PMU_SOC_WAKEUP_WAIT_CFG_V 0x00000003U +#define PMU_SOC_WAKEUP_WAIT_CFG_S 30 + +/** PMU_SLP_WAKEUP_CNTL7_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x140) +/** PMU_ANA_WAIT_TARGET : R/W; bitpos: [31:16]; default: 1; + * need_des + */ +#define PMU_ANA_WAIT_TARGET 0x0000FFFFU +#define PMU_ANA_WAIT_TARGET_M (PMU_ANA_WAIT_TARGET_V << PMU_ANA_WAIT_TARGET_S) +#define PMU_ANA_WAIT_TARGET_V 0x0000FFFFU +#define PMU_ANA_WAIT_TARGET_S 16 + +/** PMU_SLP_WAKEUP_STATUS0_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x144) +/** PMU_WAKEUP_CAUSE : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_WAKEUP_CAUSE 0xFFFFFFFFU +#define PMU_WAKEUP_CAUSE_M (PMU_WAKEUP_CAUSE_V << PMU_WAKEUP_CAUSE_S) +#define PMU_WAKEUP_CAUSE_V 0xFFFFFFFFU +#define PMU_WAKEUP_CAUSE_S 0 + +/** PMU_SLP_WAKEUP_STATUS1_REG register + * need_des + */ +#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x148) +/** PMU_REJECT_CAUSE : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define PMU_REJECT_CAUSE 0xFFFFFFFFU +#define PMU_REJECT_CAUSE_M (PMU_REJECT_CAUSE_V << PMU_REJECT_CAUSE_S) +#define PMU_REJECT_CAUSE_V 0xFFFFFFFFU +#define PMU_REJECT_CAUSE_S 0 + +/** PMU_HP_CK_POWERON_REG register + * need_des + */ +#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x14c) +/** PMU_I2C_POR_WAIT_TARGET : R/W; bitpos: [7:0]; default: 50; + * need_des + */ +#define PMU_I2C_POR_WAIT_TARGET 0x000000FFU +#define PMU_I2C_POR_WAIT_TARGET_M (PMU_I2C_POR_WAIT_TARGET_V << PMU_I2C_POR_WAIT_TARGET_S) +#define PMU_I2C_POR_WAIT_TARGET_V 0x000000FFU +#define PMU_I2C_POR_WAIT_TARGET_S 0 + +/** PMU_HP_CK_CNTL_REG register + * need_des + */ +#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x150) +/** PMU_MODIFY_ICG_CNTL_WAIT : R/W; bitpos: [7:0]; default: 10; + * need_des + */ +#define PMU_MODIFY_ICG_CNTL_WAIT 0x000000FFU +#define PMU_MODIFY_ICG_CNTL_WAIT_M (PMU_MODIFY_ICG_CNTL_WAIT_V << PMU_MODIFY_ICG_CNTL_WAIT_S) +#define PMU_MODIFY_ICG_CNTL_WAIT_V 0x000000FFU +#define PMU_MODIFY_ICG_CNTL_WAIT_S 0 +/** PMU_SWITCH_ICG_CNTL_WAIT : R/W; bitpos: [15:8]; default: 10; + * need_des + */ +#define PMU_SWITCH_ICG_CNTL_WAIT 0x000000FFU +#define PMU_SWITCH_ICG_CNTL_WAIT_M (PMU_SWITCH_ICG_CNTL_WAIT_V << PMU_SWITCH_ICG_CNTL_WAIT_S) +#define PMU_SWITCH_ICG_CNTL_WAIT_V 0x000000FFU +#define PMU_SWITCH_ICG_CNTL_WAIT_S 8 + +/** PMU_POR_STATUS_REG register + * need_des + */ +#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x154) +/** PMU_POR_DONE : RO; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_POR_DONE (BIT(31)) +#define PMU_POR_DONE_M (PMU_POR_DONE_V << PMU_POR_DONE_S) +#define PMU_POR_DONE_V 0x00000001U +#define PMU_POR_DONE_S 31 + +/** PMU_RF_PWC_REG register + * need_des + */ +#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x158) +/** PMU_XPD_TC5G_I2C : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_XPD_TC5G_I2C (BIT(24)) +#define PMU_XPD_TC5G_I2C_M (PMU_XPD_TC5G_I2C_V << PMU_XPD_TC5G_I2C_S) +#define PMU_XPD_TC5G_I2C_V 0x00000001U +#define PMU_XPD_TC5G_I2C_S 24 +/** PMU_XPD_RX5G_I2C : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_XPD_RX5G_I2C (BIT(25)) +#define PMU_XPD_RX5G_I2C_M (PMU_XPD_RX5G_I2C_V << PMU_XPD_RX5G_I2C_S) +#define PMU_XPD_RX5G_I2C_V 0x00000001U +#define PMU_XPD_RX5G_I2C_S 25 +/** PMU_PERIF_I2C_RSTB : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_PERIF_I2C_RSTB (BIT(26)) +#define PMU_PERIF_I2C_RSTB_M (PMU_PERIF_I2C_RSTB_V << PMU_PERIF_I2C_RSTB_S) +#define PMU_PERIF_I2C_RSTB_V 0x00000001U +#define PMU_PERIF_I2C_RSTB_S 26 +/** PMU_XPD_PERIF_I2C : R/W; bitpos: [27]; default: 1; + * need_des + */ +#define PMU_XPD_PERIF_I2C (BIT(27)) +#define PMU_XPD_PERIF_I2C_M (PMU_XPD_PERIF_I2C_V << PMU_XPD_PERIF_I2C_S) +#define PMU_XPD_PERIF_I2C_V 0x00000001U +#define PMU_XPD_PERIF_I2C_S 27 +/** PMU_XPD_TXRF_I2C : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_XPD_TXRF_I2C (BIT(28)) +#define PMU_XPD_TXRF_I2C_M (PMU_XPD_TXRF_I2C_V << PMU_XPD_TXRF_I2C_S) +#define PMU_XPD_TXRF_I2C_V 0x00000001U +#define PMU_XPD_TXRF_I2C_S 28 +/** PMU_XPD_RFRX_PBUS : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_XPD_RFRX_PBUS (BIT(29)) +#define PMU_XPD_RFRX_PBUS_M (PMU_XPD_RFRX_PBUS_V << PMU_XPD_RFRX_PBUS_S) +#define PMU_XPD_RFRX_PBUS_V 0x00000001U +#define PMU_XPD_RFRX_PBUS_S 29 +/** PMU_XPD_CKGEN_I2C : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_XPD_CKGEN_I2C (BIT(30)) +#define PMU_XPD_CKGEN_I2C_M (PMU_XPD_CKGEN_I2C_V << PMU_XPD_CKGEN_I2C_S) +#define PMU_XPD_CKGEN_I2C_V 0x00000001U +#define PMU_XPD_CKGEN_I2C_S 30 +/** PMU_XPD_PLL_I2C : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_XPD_PLL_I2C (BIT(31)) +#define PMU_XPD_PLL_I2C_M (PMU_XPD_PLL_I2C_V << PMU_XPD_PLL_I2C_S) +#define PMU_XPD_PLL_I2C_V 0x00000001U +#define PMU_XPD_PLL_I2C_S 31 + +/** PMU_BACKUP_CFG_REG register + * need_des + */ +#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x15c) +/** PMU_BACKUP_SYS_CLK_NO_DIV : R/W; bitpos: [31]; default: 1; + * need_des + */ +#define PMU_BACKUP_SYS_CLK_NO_DIV (BIT(31)) +#define PMU_BACKUP_SYS_CLK_NO_DIV_M (PMU_BACKUP_SYS_CLK_NO_DIV_V << PMU_BACKUP_SYS_CLK_NO_DIV_S) +#define PMU_BACKUP_SYS_CLK_NO_DIV_V 0x00000001U +#define PMU_BACKUP_SYS_CLK_NO_DIV_S 31 + +/** PMU_INT_RAW_REG register + * need_des + */ +#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x160) +/** PMU_LP_CPU_EXC_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_RAW (BIT(27)) +#define PMU_LP_CPU_EXC_INT_RAW_M (PMU_LP_CPU_EXC_INT_RAW_V << PMU_LP_CPU_EXC_INT_RAW_S) +#define PMU_LP_CPU_EXC_INT_RAW_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_RAW_S 27 +/** PMU_SDIO_IDLE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_RAW (BIT(28)) +#define PMU_SDIO_IDLE_INT_RAW_M (PMU_SDIO_IDLE_INT_RAW_V << PMU_SDIO_IDLE_INT_RAW_S) +#define PMU_SDIO_IDLE_INT_RAW_V 0x00000001U +#define PMU_SDIO_IDLE_INT_RAW_S 28 +/** PMU_SW_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_RAW (BIT(29)) +#define PMU_SW_INT_RAW_M (PMU_SW_INT_RAW_V << PMU_SW_INT_RAW_S) +#define PMU_SW_INT_RAW_V 0x00000001U +#define PMU_SW_INT_RAW_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_RAW (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_RAW_M (PMU_SOC_SLEEP_REJECT_INT_RAW_V << PMU_SOC_SLEEP_REJECT_INT_RAW_S) +#define PMU_SOC_SLEEP_REJECT_INT_RAW_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_RAW_S 30 +/** PMU_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_RAW (BIT(31)) +#define PMU_SOC_WAKEUP_INT_RAW_M (PMU_SOC_WAKEUP_INT_RAW_V << PMU_SOC_WAKEUP_INT_RAW_S) +#define PMU_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_RAW_S 31 + +/** PMU_HP_INT_ST_REG register + * need_des + */ +#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x164) +/** PMU_LP_CPU_EXC_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_ST (BIT(27)) +#define PMU_LP_CPU_EXC_INT_ST_M (PMU_LP_CPU_EXC_INT_ST_V << PMU_LP_CPU_EXC_INT_ST_S) +#define PMU_LP_CPU_EXC_INT_ST_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_ST_S 27 +/** PMU_SDIO_IDLE_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_ST (BIT(28)) +#define PMU_SDIO_IDLE_INT_ST_M (PMU_SDIO_IDLE_INT_ST_V << PMU_SDIO_IDLE_INT_ST_S) +#define PMU_SDIO_IDLE_INT_ST_V 0x00000001U +#define PMU_SDIO_IDLE_INT_ST_S 28 +/** PMU_SW_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_ST (BIT(29)) +#define PMU_SW_INT_ST_M (PMU_SW_INT_ST_V << PMU_SW_INT_ST_S) +#define PMU_SW_INT_ST_V 0x00000001U +#define PMU_SW_INT_ST_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_ST (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_ST_M (PMU_SOC_SLEEP_REJECT_INT_ST_V << PMU_SOC_SLEEP_REJECT_INT_ST_S) +#define PMU_SOC_SLEEP_REJECT_INT_ST_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_ST_S 30 +/** PMU_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_ST (BIT(31)) +#define PMU_SOC_WAKEUP_INT_ST_M (PMU_SOC_WAKEUP_INT_ST_V << PMU_SOC_WAKEUP_INT_ST_S) +#define PMU_SOC_WAKEUP_INT_ST_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_ST_S 31 + +/** PMU_HP_INT_ENA_REG register + * need_des + */ +#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x168) +/** PMU_LP_CPU_EXC_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_ENA (BIT(27)) +#define PMU_LP_CPU_EXC_INT_ENA_M (PMU_LP_CPU_EXC_INT_ENA_V << PMU_LP_CPU_EXC_INT_ENA_S) +#define PMU_LP_CPU_EXC_INT_ENA_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_ENA_S 27 +/** PMU_SDIO_IDLE_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_ENA (BIT(28)) +#define PMU_SDIO_IDLE_INT_ENA_M (PMU_SDIO_IDLE_INT_ENA_V << PMU_SDIO_IDLE_INT_ENA_S) +#define PMU_SDIO_IDLE_INT_ENA_V 0x00000001U +#define PMU_SDIO_IDLE_INT_ENA_S 28 +/** PMU_SW_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_ENA (BIT(29)) +#define PMU_SW_INT_ENA_M (PMU_SW_INT_ENA_V << PMU_SW_INT_ENA_S) +#define PMU_SW_INT_ENA_V 0x00000001U +#define PMU_SW_INT_ENA_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_ENA (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_ENA_M (PMU_SOC_SLEEP_REJECT_INT_ENA_V << PMU_SOC_SLEEP_REJECT_INT_ENA_S) +#define PMU_SOC_SLEEP_REJECT_INT_ENA_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_ENA_S 30 +/** PMU_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_ENA (BIT(31)) +#define PMU_SOC_WAKEUP_INT_ENA_M (PMU_SOC_WAKEUP_INT_ENA_V << PMU_SOC_WAKEUP_INT_ENA_S) +#define PMU_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_ENA_S 31 + +/** PMU_HP_INT_CLR_REG register + * need_des + */ +#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x16c) +/** PMU_LP_CPU_EXC_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_LP_CPU_EXC_INT_CLR (BIT(27)) +#define PMU_LP_CPU_EXC_INT_CLR_M (PMU_LP_CPU_EXC_INT_CLR_V << PMU_LP_CPU_EXC_INT_CLR_S) +#define PMU_LP_CPU_EXC_INT_CLR_V 0x00000001U +#define PMU_LP_CPU_EXC_INT_CLR_S 27 +/** PMU_SDIO_IDLE_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SDIO_IDLE_INT_CLR (BIT(28)) +#define PMU_SDIO_IDLE_INT_CLR_M (PMU_SDIO_IDLE_INT_CLR_V << PMU_SDIO_IDLE_INT_CLR_S) +#define PMU_SDIO_IDLE_INT_CLR_V 0x00000001U +#define PMU_SDIO_IDLE_INT_CLR_S 28 +/** PMU_SW_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_SW_INT_CLR (BIT(29)) +#define PMU_SW_INT_CLR_M (PMU_SW_INT_CLR_V << PMU_SW_INT_CLR_S) +#define PMU_SW_INT_CLR_V 0x00000001U +#define PMU_SW_INT_CLR_S 29 +/** PMU_SOC_SLEEP_REJECT_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_SOC_SLEEP_REJECT_INT_CLR (BIT(30)) +#define PMU_SOC_SLEEP_REJECT_INT_CLR_M (PMU_SOC_SLEEP_REJECT_INT_CLR_V << PMU_SOC_SLEEP_REJECT_INT_CLR_S) +#define PMU_SOC_SLEEP_REJECT_INT_CLR_V 0x00000001U +#define PMU_SOC_SLEEP_REJECT_INT_CLR_S 30 +/** PMU_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_SOC_WAKEUP_INT_CLR (BIT(31)) +#define PMU_SOC_WAKEUP_INT_CLR_M (PMU_SOC_WAKEUP_INT_CLR_V << PMU_SOC_WAKEUP_INT_CLR_S) +#define PMU_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define PMU_SOC_WAKEUP_INT_CLR_S 31 + +/** PMU_LP_INT_RAW_REG register + * need_des + */ +#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x170) +/** PMU_LP_CPU_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_RAW (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_RAW_M (PMU_LP_CPU_WAKEUP_INT_RAW_V << PMU_LP_CPU_WAKEUP_INT_RAW_S) +#define PMU_LP_CPU_WAKEUP_INT_RAW_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_RAW_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_M (PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_M (PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_M (PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_M (PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S 30 +/** PMU_HP_SW_TRIGGER_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_RAW (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_RAW_M (PMU_HP_SW_TRIGGER_INT_RAW_V << PMU_HP_SW_TRIGGER_INT_RAW_S) +#define PMU_HP_SW_TRIGGER_INT_RAW_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_RAW_S 31 + +/** PMU_LP_INT_ST_REG register + * need_des + */ +#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x174) +/** PMU_LP_CPU_WAKEUP_INT_ST : RO; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_ST (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_ST_M (PMU_LP_CPU_WAKEUP_INT_ST_V << PMU_LP_CPU_WAKEUP_INT_ST_S) +#define PMU_LP_CPU_WAKEUP_INT_ST_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_ST_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_ST : RO; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_M (PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_M (PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_ST : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_M (PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_M (PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S 30 +/** PMU_HP_SW_TRIGGER_INT_ST : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_ST (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_ST_M (PMU_HP_SW_TRIGGER_INT_ST_V << PMU_HP_SW_TRIGGER_INT_ST_S) +#define PMU_HP_SW_TRIGGER_INT_ST_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_ST_S 31 + +/** PMU_LP_INT_ENA_REG register + * need_des + */ +#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x178) +/** PMU_LP_CPU_WAKEUP_INT_ENA : R/W; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_ENA (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_ENA_M (PMU_LP_CPU_WAKEUP_INT_ENA_V << PMU_LP_CPU_WAKEUP_INT_ENA_S) +#define PMU_LP_CPU_WAKEUP_INT_ENA_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_ENA_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_ENA : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_M (PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_M (PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_ENA : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_M (PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_M (PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S 30 +/** PMU_HP_SW_TRIGGER_INT_ENA : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_ENA (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_ENA_M (PMU_HP_SW_TRIGGER_INT_ENA_V << PMU_HP_SW_TRIGGER_INT_ENA_S) +#define PMU_HP_SW_TRIGGER_INT_ENA_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_ENA_S 31 + +/** PMU_LP_INT_CLR_REG register + * need_des + */ +#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x17c) +/** PMU_LP_CPU_WAKEUP_INT_CLR : WT; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_INT_CLR (BIT(20)) +#define PMU_LP_CPU_WAKEUP_INT_CLR_M (PMU_LP_CPU_WAKEUP_INT_CLR_V << PMU_LP_CPU_WAKEUP_INT_CLR_S) +#define PMU_LP_CPU_WAKEUP_INT_CLR_V 0x00000001U +#define PMU_LP_CPU_WAKEUP_INT_CLR_S 20 +/** PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [21]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR (BIT(21)) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S) +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S 21 +/** PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR (BIT(22)) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S) +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S 22 +/** PMU_SLEEP_SWITCH_MODEM_END_INT_CLR : WT; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR (BIT(23)) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_M (PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S) +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S 23 +/** PMU_MODEM_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR (BIT(24)) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_M (PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S) +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S 24 +/** PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR (BIT(25)) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S) +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S 25 +/** PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR (BIT(26)) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S) +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S 26 +/** PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR (BIT(27)) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S) +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S 27 +/** PMU_SLEEP_SWITCH_MODEM_START_INT_CLR : WT; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR (BIT(28)) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_M (PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S) +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V 0x00000001U +#define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S 28 +/** PMU_MODEM_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR (BIT(29)) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_M (PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S) +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V 0x00000001U +#define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S 29 +/** PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR (BIT(30)) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S) +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V 0x00000001U +#define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S 30 +/** PMU_HP_SW_TRIGGER_INT_CLR : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_SW_TRIGGER_INT_CLR (BIT(31)) +#define PMU_HP_SW_TRIGGER_INT_CLR_M (PMU_HP_SW_TRIGGER_INT_CLR_V << PMU_HP_SW_TRIGGER_INT_CLR_S) +#define PMU_HP_SW_TRIGGER_INT_CLR_V 0x00000001U +#define PMU_HP_SW_TRIGGER_INT_CLR_S 31 + +/** PMU_LP_CPU_PWR0_REG register + * need_des + */ +#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x180) +/** PMU_LP_CPU_WAITI_RDY : RO; bitpos: [0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAITI_RDY (BIT(0)) +#define PMU_LP_CPU_WAITI_RDY_M (PMU_LP_CPU_WAITI_RDY_V << PMU_LP_CPU_WAITI_RDY_S) +#define PMU_LP_CPU_WAITI_RDY_V 0x00000001U +#define PMU_LP_CPU_WAITI_RDY_S 0 +/** PMU_LP_CPU_STALL_RDY : RO; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_LP_CPU_STALL_RDY (BIT(1)) +#define PMU_LP_CPU_STALL_RDY_M (PMU_LP_CPU_STALL_RDY_V << PMU_LP_CPU_STALL_RDY_S) +#define PMU_LP_CPU_STALL_RDY_V 0x00000001U +#define PMU_LP_CPU_STALL_RDY_S 1 +/** PMU_LP_CPU_FORCE_STALL : R/W; bitpos: [18]; default: 0; + * need_des + */ +#define PMU_LP_CPU_FORCE_STALL (BIT(18)) +#define PMU_LP_CPU_FORCE_STALL_M (PMU_LP_CPU_FORCE_STALL_V << PMU_LP_CPU_FORCE_STALL_S) +#define PMU_LP_CPU_FORCE_STALL_V 0x00000001U +#define PMU_LP_CPU_FORCE_STALL_S 18 +/** PMU_LP_CPU_SLP_WAITI_FLAG_EN : R/W; bitpos: [19]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN (BIT(19)) +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_M (PMU_LP_CPU_SLP_WAITI_FLAG_EN_V << PMU_LP_CPU_SLP_WAITI_FLAG_EN_S) +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_WAITI_FLAG_EN_S 19 +/** PMU_LP_CPU_SLP_STALL_FLAG_EN : R/W; bitpos: [20]; default: 1; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_FLAG_EN (BIT(20)) +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_M (PMU_LP_CPU_SLP_STALL_FLAG_EN_V << PMU_LP_CPU_SLP_STALL_FLAG_EN_S) +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_STALL_FLAG_EN_S 20 +/** PMU_LP_CPU_SLP_STALL_WAIT : R/W; bitpos: [28:21]; default: 255; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_WAIT 0x000000FFU +#define PMU_LP_CPU_SLP_STALL_WAIT_M (PMU_LP_CPU_SLP_STALL_WAIT_V << PMU_LP_CPU_SLP_STALL_WAIT_S) +#define PMU_LP_CPU_SLP_STALL_WAIT_V 0x000000FFU +#define PMU_LP_CPU_SLP_STALL_WAIT_S 21 +/** PMU_LP_CPU_SLP_STALL_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_STALL_EN (BIT(29)) +#define PMU_LP_CPU_SLP_STALL_EN_M (PMU_LP_CPU_SLP_STALL_EN_V << PMU_LP_CPU_SLP_STALL_EN_S) +#define PMU_LP_CPU_SLP_STALL_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_STALL_EN_S 29 +/** PMU_LP_CPU_SLP_RESET_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_RESET_EN (BIT(30)) +#define PMU_LP_CPU_SLP_RESET_EN_M (PMU_LP_CPU_SLP_RESET_EN_V << PMU_LP_CPU_SLP_RESET_EN_S) +#define PMU_LP_CPU_SLP_RESET_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_RESET_EN_S 30 +/** PMU_LP_CPU_SLP_BYPASS_INTR_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN (BIT(31)) +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_M (PMU_LP_CPU_SLP_BYPASS_INTR_EN_V << PMU_LP_CPU_SLP_BYPASS_INTR_EN_S) +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_V 0x00000001U +#define PMU_LP_CPU_SLP_BYPASS_INTR_EN_S 31 + +/** PMU_LP_CPU_PWR1_REG register + * need_des + */ +#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x184) +/** PMU_LP_CPU_WAKEUP_EN : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define PMU_LP_CPU_WAKEUP_EN 0x0000FFFFU +#define PMU_LP_CPU_WAKEUP_EN_M (PMU_LP_CPU_WAKEUP_EN_V << PMU_LP_CPU_WAKEUP_EN_S) +#define PMU_LP_CPU_WAKEUP_EN_V 0x0000FFFFU +#define PMU_LP_CPU_WAKEUP_EN_S 0 +/** PMU_LP_CPU_SLEEP_REQ : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_LP_CPU_SLEEP_REQ (BIT(31)) +#define PMU_LP_CPU_SLEEP_REQ_M (PMU_LP_CPU_SLEEP_REQ_V << PMU_LP_CPU_SLEEP_REQ_S) +#define PMU_LP_CPU_SLEEP_REQ_V 0x00000001U +#define PMU_LP_CPU_SLEEP_REQ_S 31 + +/** PMU_HP_LP_CPU_COMM_REG register + * need_des + */ +#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x188) +/** PMU_LP_TRIGGER_HP : WT; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_LP_TRIGGER_HP (BIT(30)) +#define PMU_LP_TRIGGER_HP_M (PMU_LP_TRIGGER_HP_V << PMU_LP_TRIGGER_HP_S) +#define PMU_LP_TRIGGER_HP_V 0x00000001U +#define PMU_LP_TRIGGER_HP_S 30 +/** PMU_HP_TRIGGER_LP : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_HP_TRIGGER_LP (BIT(31)) +#define PMU_HP_TRIGGER_LP_M (PMU_HP_TRIGGER_LP_V << PMU_HP_TRIGGER_LP_S) +#define PMU_HP_TRIGGER_LP_V 0x00000001U +#define PMU_HP_TRIGGER_LP_S 31 + +/** PMU_HP_REGULATOR_CFG_REG register + * need_des + */ +#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x18c) +/** PMU_DIG_REGULATOR_EN_CAL : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_DIG_REGULATOR_EN_CAL (BIT(31)) +#define PMU_DIG_REGULATOR_EN_CAL_M (PMU_DIG_REGULATOR_EN_CAL_V << PMU_DIG_REGULATOR_EN_CAL_S) +#define PMU_DIG_REGULATOR_EN_CAL_V 0x00000001U +#define PMU_DIG_REGULATOR_EN_CAL_S 31 + +/** PMU_MAIN_STATE_REG register + * need_des + */ +#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x190) +/** PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 1; + * need_des + */ +#define PMU_MAIN_LAST_ST_STATE 0x0000007FU +#define PMU_MAIN_LAST_ST_STATE_M (PMU_MAIN_LAST_ST_STATE_V << PMU_MAIN_LAST_ST_STATE_S) +#define PMU_MAIN_LAST_ST_STATE_V 0x0000007FU +#define PMU_MAIN_LAST_ST_STATE_S 11 +/** PMU_MAIN_TAR_ST_STATE : RO; bitpos: [24:18]; default: 4; + * need_des + */ +#define PMU_MAIN_TAR_ST_STATE 0x0000007FU +#define PMU_MAIN_TAR_ST_STATE_M (PMU_MAIN_TAR_ST_STATE_V << PMU_MAIN_TAR_ST_STATE_S) +#define PMU_MAIN_TAR_ST_STATE_V 0x0000007FU +#define PMU_MAIN_TAR_ST_STATE_S 18 +/** PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 4; + * need_des + */ +#define PMU_MAIN_CUR_ST_STATE 0x0000007FU +#define PMU_MAIN_CUR_ST_STATE_M (PMU_MAIN_CUR_ST_STATE_V << PMU_MAIN_CUR_ST_STATE_S) +#define PMU_MAIN_CUR_ST_STATE_V 0x0000007FU +#define PMU_MAIN_CUR_ST_STATE_S 25 + +/** PMU_PWR_STATE_REG register + * need_des + */ +#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x194) +/** PMU_BACKUP_ST_STATE : RO; bitpos: [17:13]; default: 1; + * need_des + */ +#define PMU_BACKUP_ST_STATE 0x0000001FU +#define PMU_BACKUP_ST_STATE_M (PMU_BACKUP_ST_STATE_V << PMU_BACKUP_ST_STATE_S) +#define PMU_BACKUP_ST_STATE_V 0x0000001FU +#define PMU_BACKUP_ST_STATE_S 13 +/** PMU_LP_PWR_ST_STATE : RO; bitpos: [22:18]; default: 0; + * need_des + */ +#define PMU_LP_PWR_ST_STATE 0x0000001FU +#define PMU_LP_PWR_ST_STATE_M (PMU_LP_PWR_ST_STATE_V << PMU_LP_PWR_ST_STATE_S) +#define PMU_LP_PWR_ST_STATE_V 0x0000001FU +#define PMU_LP_PWR_ST_STATE_S 18 +/** PMU_HP_PWR_ST_STATE : RO; bitpos: [31:23]; default: 1; + * need_des + */ +#define PMU_HP_PWR_ST_STATE 0x000001FFU +#define PMU_HP_PWR_ST_STATE_M (PMU_HP_PWR_ST_STATE_V << PMU_HP_PWR_ST_STATE_S) +#define PMU_HP_PWR_ST_STATE_V 0x000001FFU +#define PMU_HP_PWR_ST_STATE_S 23 + +/** PMU_CLK_STATE0_REG register + * need_des + */ +#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x198) +/** PMU_STABLE_XPD_BBPLL_STATE : RO; bitpos: [0]; default: 1; + * need_des + */ +#define PMU_STABLE_XPD_BBPLL_STATE (BIT(0)) +#define PMU_STABLE_XPD_BBPLL_STATE_M (PMU_STABLE_XPD_BBPLL_STATE_V << PMU_STABLE_XPD_BBPLL_STATE_S) +#define PMU_STABLE_XPD_BBPLL_STATE_V 0x00000001U +#define PMU_STABLE_XPD_BBPLL_STATE_S 0 +/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [1]; default: 1; + * need_des + */ +#define PMU_STABLE_XPD_XTAL_STATE (BIT(1)) +#define PMU_STABLE_XPD_XTAL_STATE_M (PMU_STABLE_XPD_XTAL_STATE_V << PMU_STABLE_XPD_XTAL_STATE_S) +#define PMU_STABLE_XPD_XTAL_STATE_V 0x00000001U +#define PMU_STABLE_XPD_XTAL_STATE_S 1 +/** PMU_SYS_CLK_SLP_SEL_STATE : RO; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_SYS_CLK_SLP_SEL_STATE (BIT(15)) +#define PMU_SYS_CLK_SLP_SEL_STATE_M (PMU_SYS_CLK_SLP_SEL_STATE_V << PMU_SYS_CLK_SLP_SEL_STATE_S) +#define PMU_SYS_CLK_SLP_SEL_STATE_V 0x00000001U +#define PMU_SYS_CLK_SLP_SEL_STATE_S 15 +/** PMU_SYS_CLK_SEL_STATE : RO; bitpos: [17:16]; default: 0; + * need_des + */ +#define PMU_SYS_CLK_SEL_STATE 0x00000003U +#define PMU_SYS_CLK_SEL_STATE_M (PMU_SYS_CLK_SEL_STATE_V << PMU_SYS_CLK_SEL_STATE_S) +#define PMU_SYS_CLK_SEL_STATE_V 0x00000003U +#define PMU_SYS_CLK_SEL_STATE_S 16 +/** PMU_SYS_CLK_NO_DIV_STATE : RO; bitpos: [18]; default: 0; + * need_des + */ +#define PMU_SYS_CLK_NO_DIV_STATE (BIT(18)) +#define PMU_SYS_CLK_NO_DIV_STATE_M (PMU_SYS_CLK_NO_DIV_STATE_V << PMU_SYS_CLK_NO_DIV_STATE_S) +#define PMU_SYS_CLK_NO_DIV_STATE_V 0x00000001U +#define PMU_SYS_CLK_NO_DIV_STATE_S 18 +/** PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [19]; default: 0; + * need_des + */ +#define PMU_ICG_SYS_CLK_EN_STATE (BIT(19)) +#define PMU_ICG_SYS_CLK_EN_STATE_M (PMU_ICG_SYS_CLK_EN_STATE_V << PMU_ICG_SYS_CLK_EN_STATE_S) +#define PMU_ICG_SYS_CLK_EN_STATE_V 0x00000001U +#define PMU_ICG_SYS_CLK_EN_STATE_S 19 +/** PMU_ICG_MODEM_SWITCH_STATE : RO; bitpos: [20]; default: 0; + * need_des + */ +#define PMU_ICG_MODEM_SWITCH_STATE (BIT(20)) +#define PMU_ICG_MODEM_SWITCH_STATE_M (PMU_ICG_MODEM_SWITCH_STATE_V << PMU_ICG_MODEM_SWITCH_STATE_S) +#define PMU_ICG_MODEM_SWITCH_STATE_V 0x00000001U +#define PMU_ICG_MODEM_SWITCH_STATE_S 20 +/** PMU_ICG_MODEM_CODE_STATE : RO; bitpos: [22:21]; default: 0; + * need_des + */ +#define PMU_ICG_MODEM_CODE_STATE 0x00000003U +#define PMU_ICG_MODEM_CODE_STATE_M (PMU_ICG_MODEM_CODE_STATE_V << PMU_ICG_MODEM_CODE_STATE_S) +#define PMU_ICG_MODEM_CODE_STATE_V 0x00000003U +#define PMU_ICG_MODEM_CODE_STATE_S 21 +/** PMU_ICG_SLP_SEL_STATE : RO; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_ICG_SLP_SEL_STATE (BIT(23)) +#define PMU_ICG_SLP_SEL_STATE_M (PMU_ICG_SLP_SEL_STATE_V << PMU_ICG_SLP_SEL_STATE_S) +#define PMU_ICG_SLP_SEL_STATE_V 0x00000001U +#define PMU_ICG_SLP_SEL_STATE_S 23 +/** PMU_ICG_GLOBAL_XTAL_STATE : RO; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_ICG_GLOBAL_XTAL_STATE (BIT(24)) +#define PMU_ICG_GLOBAL_XTAL_STATE_M (PMU_ICG_GLOBAL_XTAL_STATE_V << PMU_ICG_GLOBAL_XTAL_STATE_S) +#define PMU_ICG_GLOBAL_XTAL_STATE_V 0x00000001U +#define PMU_ICG_GLOBAL_XTAL_STATE_S 24 +/** PMU_ICG_GLOBAL_PLL_STATE : RO; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_ICG_GLOBAL_PLL_STATE (BIT(25)) +#define PMU_ICG_GLOBAL_PLL_STATE_M (PMU_ICG_GLOBAL_PLL_STATE_V << PMU_ICG_GLOBAL_PLL_STATE_S) +#define PMU_ICG_GLOBAL_PLL_STATE_V 0x00000001U +#define PMU_ICG_GLOBAL_PLL_STATE_S 25 +/** PMU_ANA_I2C_ISO_EN_STATE : RO; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_ANA_I2C_ISO_EN_STATE (BIT(26)) +#define PMU_ANA_I2C_ISO_EN_STATE_M (PMU_ANA_I2C_ISO_EN_STATE_V << PMU_ANA_I2C_ISO_EN_STATE_S) +#define PMU_ANA_I2C_ISO_EN_STATE_V 0x00000001U +#define PMU_ANA_I2C_ISO_EN_STATE_S 26 +/** PMU_ANA_I2C_RETENTION_STATE : RO; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_ANA_I2C_RETENTION_STATE (BIT(27)) +#define PMU_ANA_I2C_RETENTION_STATE_M (PMU_ANA_I2C_RETENTION_STATE_V << PMU_ANA_I2C_RETENTION_STATE_S) +#define PMU_ANA_I2C_RETENTION_STATE_V 0x00000001U +#define PMU_ANA_I2C_RETENTION_STATE_S 27 +/** PMU_ANA_XPD_BB_I2C_STATE : RO; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_BB_I2C_STATE (BIT(28)) +#define PMU_ANA_XPD_BB_I2C_STATE_M (PMU_ANA_XPD_BB_I2C_STATE_V << PMU_ANA_XPD_BB_I2C_STATE_S) +#define PMU_ANA_XPD_BB_I2C_STATE_V 0x00000001U +#define PMU_ANA_XPD_BB_I2C_STATE_S 28 +/** PMU_ANA_XPD_BBPLL_I2C_STATE : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_BBPLL_I2C_STATE (BIT(29)) +#define PMU_ANA_XPD_BBPLL_I2C_STATE_M (PMU_ANA_XPD_BBPLL_I2C_STATE_V << PMU_ANA_XPD_BBPLL_I2C_STATE_S) +#define PMU_ANA_XPD_BBPLL_I2C_STATE_V 0x00000001U +#define PMU_ANA_XPD_BBPLL_I2C_STATE_S 29 +/** PMU_ANA_XPD_BBPLL_STATE : RO; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_BBPLL_STATE (BIT(30)) +#define PMU_ANA_XPD_BBPLL_STATE_M (PMU_ANA_XPD_BBPLL_STATE_V << PMU_ANA_XPD_BBPLL_STATE_S) +#define PMU_ANA_XPD_BBPLL_STATE_V 0x00000001U +#define PMU_ANA_XPD_BBPLL_STATE_S 30 +/** PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_ANA_XPD_XTAL_STATE (BIT(31)) +#define PMU_ANA_XPD_XTAL_STATE_M (PMU_ANA_XPD_XTAL_STATE_V << PMU_ANA_XPD_XTAL_STATE_S) +#define PMU_ANA_XPD_XTAL_STATE_V 0x00000001U +#define PMU_ANA_XPD_XTAL_STATE_S 31 + +/** PMU_CLK_STATE1_REG register + * need_des + */ +#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x19c) +/** PMU_ICG_FUNC_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_ICG_FUNC_EN_STATE 0xFFFFFFFFU +#define PMU_ICG_FUNC_EN_STATE_M (PMU_ICG_FUNC_EN_STATE_V << PMU_ICG_FUNC_EN_STATE_S) +#define PMU_ICG_FUNC_EN_STATE_V 0xFFFFFFFFU +#define PMU_ICG_FUNC_EN_STATE_S 0 + +/** PMU_CLK_STATE2_REG register + * need_des + */ +#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x1a0) +/** PMU_ICG_APB_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ +#define PMU_ICG_APB_EN_STATE 0xFFFFFFFFU +#define PMU_ICG_APB_EN_STATE_M (PMU_ICG_APB_EN_STATE_V << PMU_ICG_APB_EN_STATE_S) +#define PMU_ICG_APB_EN_STATE_V 0xFFFFFFFFU +#define PMU_ICG_APB_EN_STATE_S 0 + +/** PMU_VDD_SPI_STATUS_REG register + * need_des + */ +#define PMU_VDD_SPI_STATUS_REG (DR_REG_PMU_BASE + 0x1a4) +/** PMU_STABLE_VDD_SPI_PWR_DRV : RO; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_STABLE_VDD_SPI_PWR_DRV (BIT(31)) +#define PMU_STABLE_VDD_SPI_PWR_DRV_M (PMU_STABLE_VDD_SPI_PWR_DRV_V << PMU_STABLE_VDD_SPI_PWR_DRV_S) +#define PMU_STABLE_VDD_SPI_PWR_DRV_V 0x00000001U +#define PMU_STABLE_VDD_SPI_PWR_DRV_S 31 + +/** PMU_DATE_REG register + * need_des + */ +#define PMU_DATE_REG (DR_REG_PMU_BASE + 0x1a8) +/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 36770128; + * need_des + */ +#define PMU_PMU_DATE 0x7FFFFFFFU +#define PMU_PMU_DATE_M (PMU_PMU_DATE_V << PMU_PMU_DATE_S) +#define PMU_PMU_DATE_V 0x7FFFFFFFU +#define PMU_PMU_DATE_S 0 +/** PMU_CLK_EN : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_CLK_EN (BIT(31)) +#define PMU_CLK_EN_M (PMU_CLK_EN_V << PMU_CLK_EN_S) +#define PMU_CLK_EN_V 0x00000001U +#define PMU_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/pmu_struct.h b/components/soc/esp32c61/include/soc/pmu_struct.h new file mode 100644 index 0000000000..3ea8cd5102 --- /dev/null +++ b/components/soc/esp32c61/include/soc/pmu_struct.h @@ -0,0 +1,2901 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure_register */ +/** Type of hp_active_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_active_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_active_vdd_spi_pd_en:1; + /** hp_active_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_active_hp_mem_dslp:1; + /** hp_active_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_mem_pd_en:4; + /** hp_active_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_wifi_pd_en:1; + /** hp_active_pd_hp_peri_pd_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_peri_pd_en:1; + /** hp_active_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_cpu_pd_en:1; + /** hp_active_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_pd_hp_aon_pd_en:1; + /** hp_active_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_active_dig_power_reg_t; + +/** Type of hp_active_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_active_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_active_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_active_icg_hp_func_reg_t; + +/** Type of hp_active_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_active_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_active_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_active_icg_hp_apb_reg_t; + +/** Type of hp_active_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_active_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_active_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_active_icg_modem_reg_t; + +/** Type of hp_active_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_active_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_active_uart_wakeup_en:1; + /** hp_active_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_active_lp_pad_hold_all:1; + /** hp_active_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_hp_pad_hold_all:1; + /** hp_active_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_dig_pad_slp_sel:1; + /** hp_active_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_dig_pause_wdt:1; + /** hp_active_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_active_hp_sys_cntl_reg_t; + +/** Type of hp_active_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_active_i2c_iso_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_i2c_iso_en:1; + /** hp_active_i2c_retention : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_i2c_retention:1; + /** hp_active_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bb_i2c:1; + /** hp_active_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bbpll_i2c:1; + /** hp_active_xpd_bbpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bbpll:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_active_hp_ck_power_reg_t; + +/** Type of hp_active_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** hp_active_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_active_xpd_bias:1; + /** hp_active_dbg_atten : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t hp_active_dbg_atten:4; + /** hp_active_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_active_pd_cur:1; + /** hp_active_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_active_bias_reg_t; + +/** Type of hp_active_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** hp_sleep2active_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_modem_clk_code:2; + /** hp_modem2active_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_modem_clk_code:2; + uint32_t reserved_8:2; + /** hp_active_retention_mode : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_active_retention_mode:1; + /** hp_sleep2active_retention_en : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_retention_en:1; + /** hp_modem2active_retention_en : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t hp_modem2active_retention_en:1; + uint32_t reserved_13:1; + /** hp_sleep2active_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_clk_sel:2; + /** hp_modem2active_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_clk_sel:2; + uint32_t reserved_18:2; + /** hp_sleep2active_backup_mode : R/W; bitpos: [22:20]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_mode:3; + /** hp_modem2active_backup_mode : R/W; bitpos: [25:23]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_mode:3; + uint32_t reserved_26:3; + /** hp_sleep2active_backup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep2active_backup_en:1; + /** hp_modem2active_backup_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem2active_backup_en:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_active_backup_reg_t; + +/** Type of hp_active_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_active_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_active_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_active_backup_clk_reg_t; + +/** Type of hp_active_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_active_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_active_dig_sys_clk_no_div:1; + /** hp_active_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_active_icg_sys_clock_en:1; + /** hp_active_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_active_sys_clk_slp_sel:1; + /** hp_active_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_active_icg_slp_sel:1; + /** hp_active_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_active_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_active_sysclk_reg_t; + +/** Type of hp_active_hp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** hp_active_hp_regulator_slp_connect_en : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_connect_en:1; + /** lp_dbias_vol : RO; bitpos: [8:4]; default: 24; + * need_des + */ + uint32_t lp_dbias_vol:5; + /** hp_dbias_vol : RO; bitpos: [13:9]; default: 24; + * need_des + */ + uint32_t hp_dbias_vol:5; + /** dig_regulator0_dbias_sel : R/W; bitpos: [14]; default: 1; + * need_des + */ + uint32_t dig_regulator0_dbias_sel:1; + /** dig_dbias_init : WT; bitpos: [15]; default: 0; + * need_des + */ + uint32_t dig_dbias_init:1; + /** hp_active_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_mem_xpd:1; + /** hp_active_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_logic_xpd:1; + /** hp_active_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_active_hp_regulator_xpd:1; + /** hp_active_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_mem_dbias:4; + /** hp_active_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t hp_active_hp_regulator_slp_logic_dbias:4; + /** hp_active_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t hp_active_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_active_hp_regulator0_reg_t; + +/** Type of hp_active_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_active_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; + * need_des + */ + uint32_t hp_active_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_active_hp_regulator1_reg_t; + +/** Type of hp_active_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** hp_active_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_active_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_active_xtal_reg_t; + +/** Type of hp_modem_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_modem_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_modem_vdd_spi_pd_en:1; + /** hp_modem_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_mem_dslp:1; + /** hp_modem_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_mem_pd_en:4; + /** hp_modem_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_wifi_pd_en:1; + /** hp_modem_pd_hp_peri_pd_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_peri_pd_en:1; + /** hp_modem_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_cpu_pd_en:1; + /** hp_modem_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_hp_aon_pd_en:1; + /** hp_modem_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_modem_dig_power_reg_t; + +/** Type of hp_modem_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_modem_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_modem_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_modem_icg_hp_func_reg_t; + +/** Type of hp_modem_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_modem_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_modem_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_modem_icg_hp_apb_reg_t; + +/** Type of hp_modem_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_modem_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_modem_icg_modem_reg_t; + +/** Type of hp_modem_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_modem_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_modem_uart_wakeup_en:1; + /** hp_modem_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_modem_lp_pad_hold_all:1; + /** hp_modem_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_pad_hold_all:1; + /** hp_modem_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_pad_slp_sel:1; + /** hp_modem_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_pause_wdt:1; + /** hp_modem_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_modem_hp_sys_cntl_reg_t; + +/** Type of hp_modem_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_modem_i2c_iso_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_modem_i2c_iso_en:1; + /** hp_modem_i2c_retention : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_i2c_retention:1; + /** hp_modem_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bb_i2c:1; + /** hp_modem_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bbpll_i2c:1; + /** hp_modem_xpd_bbpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bbpll:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_modem_hp_ck_power_reg_t; + +/** Type of hp_modem_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** hp_modem_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_modem_xpd_bias:1; + /** hp_modem_dbg_atten : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t hp_modem_dbg_atten:4; + /** hp_modem_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem_pd_cur:1; + /** hp_modem_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_modem_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_modem_bias_reg_t; + +/** Type of hp_modem_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** hp_sleep2modem_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_modem_clk_code:2; + uint32_t reserved_6:4; + /** hp_modem_retention_mode : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_modem_retention_mode:1; + /** hp_sleep2modem_retention_en : R/W; bitpos: [11]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_retention_en:1; + uint32_t reserved_12:2; + /** hp_sleep2modem_backup_clk_sel : R/W; bitpos: [15:14]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_clk_sel:2; + uint32_t reserved_16:4; + /** hp_sleep2modem_backup_mode : R/W; bitpos: [22:20]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_mode:3; + uint32_t reserved_23:6; + /** hp_sleep2modem_backup_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep2modem_backup_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_modem_backup_reg_t; + +/** Type of hp_modem_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_modem_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_modem_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_modem_backup_clk_reg_t; + +/** Type of hp_modem_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_modem_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_sys_clk_no_div:1; + /** hp_modem_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_modem_icg_sys_clock_en:1; + /** hp_modem_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_modem_sys_clk_slp_sel:1; + /** hp_modem_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_modem_icg_slp_sel:1; + /** hp_modem_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_modem_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_modem_sysclk_reg_t; + +/** Type of hp_modem_hp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:15; + /** hp_modem_hp_regulator_slp_connect_en : R/W; bitpos: [15]; default: 1; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_connect_en:1; + /** hp_modem_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_mem_xpd:1; + /** hp_modem_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_logic_xpd:1; + /** hp_modem_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_modem_hp_regulator_xpd:1; + /** hp_modem_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_mem_dbias:4; + /** hp_modem_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t hp_modem_hp_regulator_slp_logic_dbias:4; + /** hp_modem_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t hp_modem_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_modem_hp_regulator0_reg_t; + +/** Type of hp_modem_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_modem_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; + * need_des + */ + uint32_t hp_modem_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_modem_hp_regulator1_reg_t; + +/** Type of hp_modem_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** hp_modem_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_modem_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_modem_xtal_reg_t; + +/** Type of hp_sleep_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_sleep_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t hp_sleep_vdd_spi_pd_en:1; + /** hp_sleep_hp_mem_dslp : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_mem_dslp:1; + /** hp_sleep_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_mem_pd_en:4; + /** hp_sleep_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_wifi_pd_en:1; + /** hp_sleep_pd_hp_peri_pd_en : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_peri_pd_en:1; + /** hp_sleep_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_cpu_pd_en:1; + /** hp_sleep_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_hp_aon_pd_en:1; + /** hp_sleep_pd_top_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_top_pd_en:1; + }; + uint32_t val; +} pmu_hp_sleep_dig_power_reg_t; + +/** Type of hp_sleep_icg_hp_func register + * need_des + */ +typedef union { + struct { + /** hp_sleep_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_sleep_dig_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_sleep_icg_hp_func_reg_t; + +/** Type of hp_sleep_icg_hp_apb register + * need_des + */ +typedef union { + struct { + /** hp_sleep_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t hp_sleep_dig_icg_apb_en:32; + }; + uint32_t val; +} pmu_hp_sleep_icg_hp_apb_reg_t; + +/** Type of hp_sleep_icg_modem register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_sleep_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_icg_modem_code:2; + }; + uint32_t val; +} pmu_hp_sleep_icg_modem_reg_t; + +/** Type of hp_sleep_hp_sys_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** hp_sleep_uart_wakeup_en : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t hp_sleep_uart_wakeup_en:1; + /** hp_sleep_lp_pad_hold_all : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_pad_hold_all:1; + /** hp_sleep_hp_pad_hold_all : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_pad_hold_all:1; + /** hp_sleep_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_pad_slp_sel:1; + /** hp_sleep_dig_pause_wdt : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_pause_wdt:1; + /** hp_sleep_dig_cpu_stall : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_cpu_stall:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} pmu_hp_sleep_hp_sys_cntl_reg_t; + +/** Type of hp_sleep_hp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_sleep_i2c_iso_en : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_i2c_iso_en:1; + /** hp_sleep_i2c_retention : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_i2c_retention:1; + /** hp_sleep_xpd_bb_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bb_i2c:1; + /** hp_sleep_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bbpll_i2c:1; + /** hp_sleep_xpd_bbpll : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bbpll:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} pmu_hp_sleep_hp_ck_power_reg_t; + +/** Type of hp_sleep_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** hp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_bias:1; + /** hp_sleep_dbg_atten : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t hp_sleep_dbg_atten:4; + /** hp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_cur:1; + /** hp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_bias_sleep:1; + }; + uint32_t val; +} pmu_hp_sleep_bias_reg_t; + +/** Type of hp_sleep_backup register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:6; + /** hp_modem2sleep_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_modem_clk_code:2; + /** hp_active2sleep_backup_modem_clk_code : R/W; bitpos: [9:8]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_modem_clk_code:2; + /** hp_sleep_retention_mode : R/W; bitpos: [10]; default: 0; + * need_des + */ + uint32_t hp_sleep_retention_mode:1; + uint32_t reserved_11:1; + /** hp_modem2sleep_retention_en : R/W; bitpos: [12]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_retention_en:1; + /** hp_active2sleep_retention_en : R/W; bitpos: [13]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_retention_en:1; + uint32_t reserved_14:2; + /** hp_modem2sleep_backup_clk_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_clk_sel:2; + /** hp_active2sleep_backup_clk_sel : R/W; bitpos: [19:18]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_clk_sel:2; + uint32_t reserved_20:3; + /** hp_modem2sleep_backup_mode : R/W; bitpos: [25:23]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_mode:3; + /** hp_active2sleep_backup_mode : R/W; bitpos: [28:26]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_mode:3; + uint32_t reserved_29:1; + /** hp_modem2sleep_backup_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_modem2sleep_backup_en:1; + /** hp_active2sleep_backup_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_active2sleep_backup_en:1; + }; + uint32_t val; +} pmu_hp_sleep_backup_reg_t; + +/** Type of hp_sleep_backup_clk register + * need_des + */ +typedef union { + struct { + /** hp_sleep_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_sleep_backup_icg_func_en:32; + }; + uint32_t val; +} pmu_hp_sleep_backup_clk_reg_t; + +/** Type of hp_sleep_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:26; + /** hp_sleep_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_sys_clk_no_div:1; + /** hp_sleep_icg_sys_clock_en : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t hp_sleep_icg_sys_clock_en:1; + /** hp_sleep_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_sys_clk_slp_sel:1; + /** hp_sleep_icg_slp_sel : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_icg_slp_sel:1; + /** hp_sleep_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t hp_sleep_dig_sys_clk_sel:2; + }; + uint32_t val; +} pmu_hp_sleep_sysclk_reg_t; + +/** Type of hp_sleep_hp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:15; + /** hp_sleep_hp_regulator_slp_connect_en : R/W; bitpos: [15]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_connect_en:1; + /** hp_sleep_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_mem_xpd:1; + /** hp_sleep_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_logic_xpd:1; + /** hp_sleep_hp_regulator_xpd : R/W; bitpos: [18]; default: 1; + * need_des + */ + uint32_t hp_sleep_hp_regulator_xpd:1; + /** hp_sleep_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 12; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_mem_dbias:4; + /** hp_sleep_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t hp_sleep_hp_regulator_slp_logic_dbias:4; + /** hp_sleep_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t hp_sleep_hp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_sleep_hp_regulator0_reg_t; + +/** Type of hp_sleep_hp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:8; + /** hp_sleep_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0; + * need_des + */ + uint32_t hp_sleep_hp_regulator_drv_b:24; + }; + uint32_t val; +} pmu_hp_sleep_hp_regulator1_reg_t; + +/** Type of hp_sleep_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** hp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_xtal:1; + }; + uint32_t val; +} pmu_hp_sleep_xtal_reg_t; + +/** Type of hp_sleep_lp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** hp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; + * need_des + */ + uint32_t hp_sleep_lp_regulator_slp_xpd:1; + /** hp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; + * need_des + */ + uint32_t hp_sleep_lp_regulator_xpd:1; + /** hp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t hp_sleep_lp_regulator_slp_dbias:4; + /** hp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t hp_sleep_lp_regulator_dbias:5; + }; + uint32_t val; +} pmu_hp_sleep_lp_regulator0_reg_t; + +/** Type of hp_sleep_lp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** hp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_regulator_drv_b:4; + }; + uint32_t val; +} pmu_hp_sleep_lp_regulator1_reg_t; + +/** Type of hp_sleep_lp_dcdc_reserve register + * need_des + */ +typedef union { + struct { + /** hp_sleep_lp_dcdc_reserve : WT; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_dcdc_reserve:32; + }; + uint32_t val; +} pmu_hp_sleep_lp_dcdc_reserve_reg_t; + +/** Type of hp_sleep_lp_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** hp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t hp_sleep_lp_mem_dslp:1; + /** hp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_lp_peri_pd_en:1; + }; + uint32_t val; +} pmu_hp_sleep_lp_dig_power_reg_t; + +/** Type of hp_sleep_lp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** hp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_xtal32k:1; + /** hp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t hp_sleep_xpd_rc32k:1; + /** hp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t hp_sleep_xpd_fosc_clk:1; + /** hp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sleep_pd_osc_clk:1; + }; + uint32_t val; +} pmu_hp_sleep_lp_ck_power_reg_t; + +/** Type of lp_sleep_lp_bias_reserve register + * need_des + */ +typedef union { + struct { + /** lp_sleep_lp_bias_reserve : WT; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_bias_reserve:32; + }; + uint32_t val; +} pmu_lp_sleep_lp_bias_reserve_reg_t; + +/** Type of lp_sleep_lp_regulator0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:21; + /** lp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1; + * need_des + */ + uint32_t lp_sleep_lp_regulator_slp_xpd:1; + /** lp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1; + * need_des + */ + uint32_t lp_sleep_lp_regulator_xpd:1; + /** lp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 12; + * need_des + */ + uint32_t lp_sleep_lp_regulator_slp_dbias:4; + /** lp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 24; + * need_des + */ + uint32_t lp_sleep_lp_regulator_dbias:5; + }; + uint32_t val; +} pmu_lp_sleep_lp_regulator0_reg_t; + +/** Type of lp_sleep_lp_regulator1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** lp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_regulator_drv_b:4; + }; + uint32_t val; +} pmu_lp_sleep_lp_regulator1_reg_t; + +/** Type of lp_sleep_xtal register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** lp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t lp_sleep_xpd_xtal:1; + }; + uint32_t val; +} pmu_lp_sleep_xtal_reg_t; + +/** Type of lp_sleep_lp_dig_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** lp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_sleep_lp_mem_dslp:1; + /** lp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_lp_peri_pd_en:1; + }; + uint32_t val; +} pmu_lp_sleep_lp_dig_power_reg_t; + +/** Type of lp_sleep_lp_ck_power register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** lp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_xtal32k:1; + /** lp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_rc32k:1; + /** lp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1; + * need_des + */ + uint32_t lp_sleep_xpd_fosc_clk:1; + /** lp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_osc_clk:1; + }; + uint32_t val; +} pmu_lp_sleep_lp_ck_power_reg_t; + +/** Type of lp_sleep_bias register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** lp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t lp_sleep_xpd_bias:1; + /** lp_sleep_dbg_atten : R/W; bitpos: [29:26]; default: 0; + * need_des + */ + uint32_t lp_sleep_dbg_atten:4; + /** lp_sleep_pd_cur : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_sleep_pd_cur:1; + /** lp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_sleep_bias_sleep:1; + }; + uint32_t val; +} pmu_lp_sleep_bias_reg_t; + +/** Type of imm_hp_ck_power register + * need_des + */ +typedef union { + struct { + /** tie_low_global_bbpll_icg : WT; bitpos: [0]; default: 0; + * need_des + */ + uint32_t tie_low_global_bbpll_icg:1; + /** tie_low_global_xtal_icg : WT; bitpos: [1]; default: 0; + * need_des + */ + uint32_t tie_low_global_xtal_icg:1; + /** tie_low_i2c_retention : WT; bitpos: [2]; default: 0; + * need_des + */ + uint32_t tie_low_i2c_retention:1; + /** tie_low_xpd_bb_i2c : WT; bitpos: [3]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bb_i2c:1; + /** tie_low_xpd_bbpll_i2c : WT; bitpos: [4]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bbpll_i2c:1; + /** tie_low_xpd_bbpll : WT; bitpos: [5]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_bbpll:1; + /** tie_low_xpd_xtal : WT; bitpos: [6]; default: 0; + * need_des + */ + uint32_t tie_low_xpd_xtal:1; + uint32_t reserved_7:18; + /** tie_high_global_bbpll_icg : WT; bitpos: [25]; default: 0; + * need_des + */ + uint32_t tie_high_global_bbpll_icg:1; + /** tie_high_global_xtal_icg : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t tie_high_global_xtal_icg:1; + /** tie_high_i2c_retention : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t tie_high_i2c_retention:1; + /** tie_high_xpd_bb_i2c : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bb_i2c:1; + /** tie_high_xpd_bbpll_i2c : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bbpll_i2c:1; + /** tie_high_xpd_bbpll : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_bbpll:1; + /** tie_high_xpd_xtal : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_high_xpd_xtal:1; + }; + uint32_t val; +} pmu_imm_hp_ck_power_reg_t; + +/** Type of imm_sleep_sysclk register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** update_dig_icg_switch : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t update_dig_icg_switch:1; + /** tie_low_icg_slp_sel : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_low_icg_slp_sel:1; + /** tie_high_icg_slp_sel : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_icg_slp_sel:1; + /** update_dig_sys_clk_sel : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_sys_clk_sel:1; + }; + uint32_t val; +} pmu_imm_sleep_sysclk_reg_t; + +/** Type of imm_hp_func_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_func_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_func_en:1; + }; + uint32_t val; +} pmu_imm_hp_func_icg_reg_t; + +/** Type of imm_hp_apb_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_apb_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_apb_en:1; + }; + uint32_t val; +} pmu_imm_hp_apb_icg_reg_t; + +/** Type of imm_modem_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** update_dig_icg_modem_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t update_dig_icg_modem_en:1; + }; + uint32_t val; +} pmu_imm_modem_icg_reg_t; + +/** Type of imm_lp_icg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tie_low_lp_rootclk_sel : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_low_lp_rootclk_sel:1; + /** tie_high_lp_rootclk_sel : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_high_lp_rootclk_sel:1; + }; + uint32_t val; +} pmu_imm_lp_icg_reg_t; + +/** Type of imm_pad_hold_all register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** tie_high_lp_pad_hold_all : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t tie_high_lp_pad_hold_all:1; + /** tie_low_lp_pad_hold_all : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t tie_low_lp_pad_hold_all:1; + /** tie_high_hp_pad_hold_all : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_hp_pad_hold_all:1; + /** tie_low_hp_pad_hold_all : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_low_hp_pad_hold_all:1; + }; + uint32_t val; +} pmu_imm_pad_hold_all_reg_t; + +/** Type of imm_i2c_iso register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** tie_high_i2c_iso_en : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t tie_high_i2c_iso_en:1; + /** tie_low_i2c_iso_en : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t tie_low_i2c_iso_en:1; + }; + uint32_t val; +} pmu_imm_i2c_iso_reg_t; + +/** Type of power_wait_timer0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:5; + /** dg_hp_powerdown_timer : R/W; bitpos: [13:5]; default: 255; + * need_des + */ + uint32_t dg_hp_powerdown_timer:9; + /** dg_hp_powerup_timer : R/W; bitpos: [22:14]; default: 255; + * need_des + */ + uint32_t dg_hp_powerup_timer:9; + /** dg_hp_pd_wait_timer : R/W; bitpos: [31:23]; default: 255; + * need_des + */ + uint32_t dg_hp_pd_wait_timer:9; + }; + uint32_t val; +} pmu_power_wait_timer0_reg_t; + +/** Type of power_wait_timer1 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** dg_lp_powerdown_timer : R/W; bitpos: [15:9]; default: 63; + * need_des + */ + uint32_t dg_lp_powerdown_timer:7; + /** dg_lp_powerup_timer : R/W; bitpos: [22:16]; default: 63; + * need_des + */ + uint32_t dg_lp_powerup_timer:7; + /** dg_lp_pd_wait_timer : R/W; bitpos: [31:23]; default: 255; + * need_des + */ + uint32_t dg_lp_pd_wait_timer:9; + }; + uint32_t val; +} pmu_power_wait_timer1_reg_t; + +/** Type of power_wait_timer2 register + * need_des + */ +typedef union { + struct { + /** dg_lp_iso_wait_timer : R/W; bitpos: [7:0]; default: 255; + * need_des + */ + uint32_t dg_lp_iso_wait_timer:8; + /** dg_lp_rst_wait_timer : R/W; bitpos: [15:8]; default: 255; + * need_des + */ + uint32_t dg_lp_rst_wait_timer:8; + /** dg_hp_iso_wait_timer : R/W; bitpos: [23:16]; default: 255; + * need_des + */ + uint32_t dg_hp_iso_wait_timer:8; + /** dg_hp_rst_wait_timer : R/W; bitpos: [31:24]; default: 255; + * need_des + */ + uint32_t dg_hp_rst_wait_timer:8; + }; + uint32_t val; +} pmu_power_wait_timer2_reg_t; + +/** Type of power_pd_top_cntl register + * need_des + */ +typedef union { + struct { + /** force_top_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_top_reset:1; + /** force_top_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_top_iso:1; + /** force_top_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_top_pu:1; + /** force_top_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_top_no_reset:1; + /** force_top_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_top_no_iso:1; + /** force_top_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_top_pd:1; + /** pd_top_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_top_mask:5; + uint32_t reserved_11:16; + /** pd_top_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_top_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_top_cntl_reg_t; + +/** Type of power_pd_hpaon_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_aon_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_aon_reset:1; + /** force_hp_aon_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_aon_iso:1; + /** force_hp_aon_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_aon_pu:1; + /** force_hp_aon_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_aon_no_reset:1; + /** force_hp_aon_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_aon_no_iso:1; + /** force_hp_aon_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_aon_pd:1; + /** pd_hp_aon_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_aon_mask:5; + uint32_t reserved_11:16; + /** pd_hp_aon_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_aon_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpaon_cntl_reg_t; + +/** Type of power_pd_hpcpu_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_cpu_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_reset:1; + /** force_hp_cpu_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_iso:1; + /** force_hp_cpu_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_pu:1; + /** force_hp_cpu_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_no_reset:1; + /** force_hp_cpu_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_cpu_no_iso:1; + /** force_hp_cpu_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_cpu_pd:1; + /** pd_hp_cpu_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_cpu_mask:5; + uint32_t reserved_11:16; + /** pd_hp_cpu_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_cpu_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpcpu_cntl_reg_t; + +/** Type of power_pd_hpperi_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_peri_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_peri_reset:1; + /** force_hp_peri_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_peri_iso:1; + /** force_hp_peri_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_peri_pu:1; + /** force_hp_peri_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_peri_no_reset:1; + /** force_hp_peri_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_peri_no_iso:1; + /** force_hp_peri_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_peri_pd:1; + /** pd_hp_peri_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_peri_mask:5; + uint32_t reserved_11:16; + /** pd_hp_peri_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_peri_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpperi_cntl_reg_t; + +/** Type of power_pd_hpwifi_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_wifi_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_reset:1; + /** force_hp_wifi_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_iso:1; + /** force_hp_wifi_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_pu:1; + /** force_hp_wifi_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_no_reset:1; + /** force_hp_wifi_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_hp_wifi_no_iso:1; + /** force_hp_wifi_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_hp_wifi_pd:1; + /** pd_hp_wifi_mask : R/W; bitpos: [10:6]; default: 0; + * need_des + */ + uint32_t pd_hp_wifi_mask:5; + uint32_t reserved_11:16; + /** pd_hp_wifi_pd_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_wifi_pd_mask:5; + }; + uint32_t val; +} pmu_power_pd_hpwifi_cntl_reg_t; + +/** Type of power_pd_lpperi_cntl register + * need_des + */ +typedef union { + struct { + /** force_lp_peri_reset : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_lp_peri_reset:1; + /** force_lp_peri_iso : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_lp_peri_iso:1; + /** force_lp_peri_pu : R/W; bitpos: [2]; default: 1; + * need_des + */ + uint32_t force_lp_peri_pu:1; + /** force_lp_peri_no_reset : R/W; bitpos: [3]; default: 1; + * need_des + */ + uint32_t force_lp_peri_no_reset:1; + /** force_lp_peri_no_iso : R/W; bitpos: [4]; default: 1; + * need_des + */ + uint32_t force_lp_peri_no_iso:1; + /** force_lp_peri_pd : R/W; bitpos: [5]; default: 0; + * need_des + */ + uint32_t force_lp_peri_pd:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} pmu_power_pd_lpperi_cntl_reg_t; + +/** Type of power_pd_mem_cntl register + * need_des + */ +typedef union { + struct { + /** force_hp_mem_iso : R/W; bitpos: [3:0]; default: 0; + * need_des + */ + uint32_t force_hp_mem_iso:4; + /** force_hp_mem_pd : R/W; bitpos: [7:4]; default: 0; + * need_des + */ + uint32_t force_hp_mem_pd:4; + uint32_t reserved_8:16; + /** force_hp_mem_no_iso : R/W; bitpos: [27:24]; default: 15; + * need_des + */ + uint32_t force_hp_mem_no_iso:4; + /** force_hp_mem_pu : R/W; bitpos: [31:28]; default: 15; + * need_des + */ + uint32_t force_hp_mem_pu:4; + }; + uint32_t val; +} pmu_power_pd_mem_cntl_reg_t; + +/** Type of power_pd_mem_mask register + * need_des + */ +typedef union { + struct { + /** pd_hp_mem2_pd_mask : R/W; bitpos: [4:0]; default: 0; + * need_des + */ + uint32_t pd_hp_mem2_pd_mask:5; + /** pd_hp_mem1_pd_mask : R/W; bitpos: [9:5]; default: 0; + * need_des + */ + uint32_t pd_hp_mem1_pd_mask:5; + /** pd_hp_mem0_pd_mask : R/W; bitpos: [14:10]; default: 0; + * need_des + */ + uint32_t pd_hp_mem0_pd_mask:5; + uint32_t reserved_15:2; + /** pd_hp_mem2_mask : R/W; bitpos: [21:17]; default: 0; + * need_des + */ + uint32_t pd_hp_mem2_mask:5; + /** pd_hp_mem1_mask : R/W; bitpos: [26:22]; default: 0; + * need_des + */ + uint32_t pd_hp_mem1_mask:5; + /** pd_hp_mem0_mask : R/W; bitpos: [31:27]; default: 0; + * need_des + */ + uint32_t pd_hp_mem0_mask:5; + }; + uint32_t val; +} pmu_power_pd_mem_mask_reg_t; + +/** Type of power_hp_pad register + * need_des + */ +typedef union { + struct { + /** force_hp_pad_no_iso_all : R/W; bitpos: [0]; default: 0; + * need_des + */ + uint32_t force_hp_pad_no_iso_all:1; + /** force_hp_pad_iso_all : R/W; bitpos: [1]; default: 0; + * need_des + */ + uint32_t force_hp_pad_iso_all:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pmu_power_hp_pad_reg_t; + +/** Type of power_vdd_spi_cntl register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:18; + /** vdd_spi_pwr_wait : R/W; bitpos: [28:18]; default: 255; + * need_des + */ + uint32_t vdd_spi_pwr_wait:11; + /** vdd_spi_pwr_sw : R/W; bitpos: [30:29]; default: 3; + * need_des + */ + uint32_t vdd_spi_pwr_sw:2; + /** vdd_spi_pwr_sel_sw : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t vdd_spi_pwr_sel_sw:1; + }; + uint32_t val; +} pmu_power_vdd_spi_cntl_reg_t; + +/** Type of power_ck_wait_cntl register + * need_des + */ +typedef union { + struct { + /** wait_xtl_stable : R/W; bitpos: [15:0]; default: 256; + * need_des + */ + uint32_t wait_xtl_stable:16; + /** wait_pll_stable : R/W; bitpos: [31:16]; default: 256; + * need_des + */ + uint32_t wait_pll_stable:16; + }; + uint32_t val; +} pmu_power_ck_wait_cntl_reg_t; + +/** Type of slp_wakeup_cntl0 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** sleep_req : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t sleep_req:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl0_reg_t; + +/** Type of slp_wakeup_cntl1 register + * need_des + */ +typedef union { + struct { + /** sleep_reject_ena : R/W; bitpos: [30:0]; default: 0; + * need_des + */ + uint32_t sleep_reject_ena:31; + /** slp_reject_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t slp_reject_en:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl1_reg_t; + +/** Type of slp_wakeup_cntl2 register + * need_des + */ +typedef union { + struct { + /** wakeup_ena : R/W; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wakeup_ena:32; + }; + uint32_t val; +} pmu_slp_wakeup_cntl2_reg_t; + +/** Type of slp_wakeup_cntl3 register + * need_des + */ +typedef union { + struct { + /** lp_min_slp_val : R/W; bitpos: [7:0]; default: 0; + * need_des + */ + uint32_t lp_min_slp_val:8; + /** hp_min_slp_val : R/W; bitpos: [15:8]; default: 0; + * need_des + */ + uint32_t hp_min_slp_val:8; + /** sleep_prt_sel : R/W; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t sleep_prt_sel:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} pmu_slp_wakeup_cntl3_reg_t; + +/** Type of slp_wakeup_cntl4 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** slp_reject_cause_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t slp_reject_cause_clr:1; + }; + uint32_t val; +} pmu_slp_wakeup_cntl4_reg_t; + +/** Type of slp_wakeup_cntl5 register + * need_des + */ +typedef union { + struct { + /** modem_wait_target : R/W; bitpos: [19:0]; default: 128; + * need_des + */ + uint32_t modem_wait_target:20; + uint32_t reserved_20:4; + /** lp_ana_wait_target : R/W; bitpos: [31:24]; default: 1; + * need_des + */ + uint32_t lp_ana_wait_target:8; + }; + uint32_t val; +} pmu_slp_wakeup_cntl5_reg_t; + +/** Type of slp_wakeup_cntl6 register + * need_des + */ +typedef union { + struct { + /** soc_wakeup_wait : R/W; bitpos: [19:0]; default: 128; + * need_des + */ + uint32_t soc_wakeup_wait:20; + uint32_t reserved_20:10; + /** soc_wakeup_wait_cfg : R/W; bitpos: [31:30]; default: 0; + * need_des + */ + uint32_t soc_wakeup_wait_cfg:2; + }; + uint32_t val; +} pmu_slp_wakeup_cntl6_reg_t; + +/** Type of slp_wakeup_cntl7 register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:16; + /** ana_wait_target : R/W; bitpos: [31:16]; default: 1; + * need_des + */ + uint32_t ana_wait_target:16; + }; + uint32_t val; +} pmu_slp_wakeup_cntl7_reg_t; + +/** Type of slp_wakeup_status0 register + * need_des + */ +typedef union { + struct { + /** wakeup_cause : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t wakeup_cause:32; + }; + uint32_t val; +} pmu_slp_wakeup_status0_reg_t; + +/** Type of slp_wakeup_status1 register + * need_des + */ +typedef union { + struct { + /** reject_cause : RO; bitpos: [31:0]; default: 0; + * need_des + */ + uint32_t reject_cause:32; + }; + uint32_t val; +} pmu_slp_wakeup_status1_reg_t; + +/** Type of hp_ck_poweron register + * need_des + */ +typedef union { + struct { + /** i2c_por_wait_target : R/W; bitpos: [7:0]; default: 50; + * need_des + */ + uint32_t i2c_por_wait_target:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} pmu_hp_ck_poweron_reg_t; + +/** Type of hp_ck_cntl register + * need_des + */ +typedef union { + struct { + /** modify_icg_cntl_wait : R/W; bitpos: [7:0]; default: 10; + * need_des + */ + uint32_t modify_icg_cntl_wait:8; + /** switch_icg_cntl_wait : R/W; bitpos: [15:8]; default: 10; + * need_des + */ + uint32_t switch_icg_cntl_wait:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} pmu_hp_ck_cntl_reg_t; + +/** Type of por_status register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** por_done : RO; bitpos: [31]; default: 1; + * need_des + */ + uint32_t por_done:1; + }; + uint32_t val; +} pmu_por_status_reg_t; + +/** Type of rf_pwc register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** xpd_tc5g_i2c : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t xpd_tc5g_i2c:1; + /** xpd_rx5g_i2c : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t xpd_rx5g_i2c:1; + /** perif_i2c_rstb : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t perif_i2c_rstb:1; + /** xpd_perif_i2c : R/W; bitpos: [27]; default: 1; + * need_des + */ + uint32_t xpd_perif_i2c:1; + /** xpd_txrf_i2c : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t xpd_txrf_i2c:1; + /** xpd_rfrx_pbus : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t xpd_rfrx_pbus:1; + /** xpd_ckgen_i2c : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t xpd_ckgen_i2c:1; + /** xpd_pll_i2c : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t xpd_pll_i2c:1; + }; + uint32_t val; +} pmu_rf_pwc_reg_t; + +/** Type of backup_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** backup_sys_clk_no_div : R/W; bitpos: [31]; default: 1; + * need_des + */ + uint32_t backup_sys_clk_no_div:1; + }; + uint32_t val; +} pmu_backup_cfg_reg_t; + +/** Type of int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_raw:1; + /** sdio_idle_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_raw:1; + /** sw_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_raw:1; + /** soc_sleep_reject_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_raw:1; + /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_raw:1; + }; + uint32_t val; +} pmu_int_raw_reg_t; + +/** Type of hp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_st:1; + /** sdio_idle_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_st:1; + /** sw_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_st:1; + /** soc_sleep_reject_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_st:1; + /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_st:1; + }; + uint32_t val; +} pmu_hp_int_st_reg_t; + +/** Type of hp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_ena:1; + /** sdio_idle_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_ena:1; + /** sw_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_ena:1; + /** soc_sleep_reject_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_ena:1; + /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_ena:1; + }; + uint32_t val; +} pmu_hp_int_ena_reg_t; + +/** Type of hp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:27; + /** lp_cpu_exc_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t lp_cpu_exc_int_clr:1; + /** sdio_idle_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sdio_idle_int_clr:1; + /** sw_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t sw_int_clr:1; + /** soc_sleep_reject_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t soc_sleep_reject_int_clr:1; + /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t soc_wakeup_int_clr:1; + }; + uint32_t val; +} pmu_hp_int_clr_reg_t; + +/** Type of lp_int_raw register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_raw:1; + /** modem_switch_active_end_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_raw:1; + /** sleep_switch_active_end_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_raw:1; + /** sleep_switch_modem_end_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_raw:1; + /** modem_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_raw:1; + /** active_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_raw:1; + /** modem_switch_active_start_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_raw:1; + /** sleep_switch_active_start_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_raw:1; + /** sleep_switch_modem_start_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_raw:1; + /** modem_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_raw:1; + /** active_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_raw:1; + /** hp_sw_trigger_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_raw:1; + }; + uint32_t val; +} pmu_lp_int_raw_reg_t; + +/** Type of lp_int_st register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_st : RO; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_st:1; + /** modem_switch_active_end_int_st : RO; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_st:1; + /** sleep_switch_active_end_int_st : RO; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_st:1; + /** sleep_switch_modem_end_int_st : RO; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_st:1; + /** modem_switch_sleep_end_int_st : RO; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_st:1; + /** active_switch_sleep_end_int_st : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_st:1; + /** modem_switch_active_start_int_st : RO; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_st:1; + /** sleep_switch_active_start_int_st : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_st:1; + /** sleep_switch_modem_start_int_st : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_st:1; + /** modem_switch_sleep_start_int_st : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_st:1; + /** active_switch_sleep_start_int_st : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_st:1; + /** hp_sw_trigger_int_st : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_st:1; + }; + uint32_t val; +} pmu_lp_int_st_reg_t; + +/** Type of lp_int_ena register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_ena : R/W; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_ena:1; + /** modem_switch_active_end_int_ena : R/W; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_ena:1; + /** sleep_switch_active_end_int_ena : R/W; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_ena:1; + /** sleep_switch_modem_end_int_ena : R/W; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_ena:1; + /** modem_switch_sleep_end_int_ena : R/W; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_ena:1; + /** active_switch_sleep_end_int_ena : R/W; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_ena:1; + /** modem_switch_active_start_int_ena : R/W; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_ena:1; + /** sleep_switch_active_start_int_ena : R/W; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_ena:1; + /** sleep_switch_modem_start_int_ena : R/W; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_ena:1; + /** modem_switch_sleep_start_int_ena : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_ena:1; + /** active_switch_sleep_start_int_ena : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_ena:1; + /** hp_sw_trigger_int_ena : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_ena:1; + }; + uint32_t val; +} pmu_lp_int_ena_reg_t; + +/** Type of lp_int_clr register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** lp_cpu_wakeup_int_clr : WT; bitpos: [20]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_int_clr:1; + /** modem_switch_active_end_int_clr : WT; bitpos: [21]; default: 0; + * need_des + */ + uint32_t modem_switch_active_end_int_clr:1; + /** sleep_switch_active_end_int_clr : WT; bitpos: [22]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_end_int_clr:1; + /** sleep_switch_modem_end_int_clr : WT; bitpos: [23]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_end_int_clr:1; + /** modem_switch_sleep_end_int_clr : WT; bitpos: [24]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_end_int_clr:1; + /** active_switch_sleep_end_int_clr : WT; bitpos: [25]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_end_int_clr:1; + /** modem_switch_active_start_int_clr : WT; bitpos: [26]; default: 0; + * need_des + */ + uint32_t modem_switch_active_start_int_clr:1; + /** sleep_switch_active_start_int_clr : WT; bitpos: [27]; default: 0; + * need_des + */ + uint32_t sleep_switch_active_start_int_clr:1; + /** sleep_switch_modem_start_int_clr : WT; bitpos: [28]; default: 0; + * need_des + */ + uint32_t sleep_switch_modem_start_int_clr:1; + /** modem_switch_sleep_start_int_clr : WT; bitpos: [29]; default: 0; + * need_des + */ + uint32_t modem_switch_sleep_start_int_clr:1; + /** active_switch_sleep_start_int_clr : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t active_switch_sleep_start_int_clr:1; + /** hp_sw_trigger_int_clr : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_sw_trigger_int_clr:1; + }; + uint32_t val; +} pmu_lp_int_clr_reg_t; + +/** Type of lp_cpu_pwr0 register + * need_des + */ +typedef union { + struct { + /** lp_cpu_waiti_rdy : RO; bitpos: [0]; default: 0; + * need_des + */ + uint32_t lp_cpu_waiti_rdy:1; + /** lp_cpu_stall_rdy : RO; bitpos: [1]; default: 0; + * need_des + */ + uint32_t lp_cpu_stall_rdy:1; + uint32_t reserved_2:16; + /** lp_cpu_force_stall : R/W; bitpos: [18]; default: 0; + * need_des + */ + uint32_t lp_cpu_force_stall:1; + /** lp_cpu_slp_waiti_flag_en : R/W; bitpos: [19]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_waiti_flag_en:1; + /** lp_cpu_slp_stall_flag_en : R/W; bitpos: [20]; default: 1; + * need_des + */ + uint32_t lp_cpu_slp_stall_flag_en:1; + /** lp_cpu_slp_stall_wait : R/W; bitpos: [28:21]; default: 255; + * need_des + */ + uint32_t lp_cpu_slp_stall_wait:8; + /** lp_cpu_slp_stall_en : R/W; bitpos: [29]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_stall_en:1; + /** lp_cpu_slp_reset_en : R/W; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_reset_en:1; + /** lp_cpu_slp_bypass_intr_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_slp_bypass_intr_en:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr0_reg_t; + +/** Type of lp_cpu_pwr1 register + * need_des + */ +typedef union { + struct { + /** lp_cpu_wakeup_en : R/W; bitpos: [15:0]; default: 0; + * need_des + */ + uint32_t lp_cpu_wakeup_en:16; + uint32_t reserved_16:15; + /** lp_cpu_sleep_req : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t lp_cpu_sleep_req:1; + }; + uint32_t val; +} pmu_lp_cpu_pwr1_reg_t; + +/** Type of hp_lp_cpu_comm register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:30; + /** lp_trigger_hp : WT; bitpos: [30]; default: 0; + * need_des + */ + uint32_t lp_trigger_hp:1; + /** hp_trigger_lp : WT; bitpos: [31]; default: 0; + * need_des + */ + uint32_t hp_trigger_lp:1; + }; + uint32_t val; +} pmu_hp_lp_cpu_comm_reg_t; + +/** Type of hp_regulator_cfg register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** dig_regulator_en_cal : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t dig_regulator_en_cal:1; + }; + uint32_t val; +} pmu_hp_regulator_cfg_reg_t; + +/** Type of main_state register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:11; + /** main_last_st_state : RO; bitpos: [17:11]; default: 1; + * need_des + */ + uint32_t main_last_st_state:7; + /** main_tar_st_state : RO; bitpos: [24:18]; default: 4; + * need_des + */ + uint32_t main_tar_st_state:7; + /** main_cur_st_state : RO; bitpos: [31:25]; default: 4; + * need_des + */ + uint32_t main_cur_st_state:7; + }; + uint32_t val; +} pmu_main_state_reg_t; + +/** Type of pwr_state register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:13; + /** backup_st_state : RO; bitpos: [17:13]; default: 1; + * need_des + */ + uint32_t backup_st_state:5; + /** lp_pwr_st_state : RO; bitpos: [22:18]; default: 0; + * need_des + */ + uint32_t lp_pwr_st_state:5; + /** hp_pwr_st_state : RO; bitpos: [31:23]; default: 1; + * need_des + */ + uint32_t hp_pwr_st_state:9; + }; + uint32_t val; +} pmu_pwr_state_reg_t; + +/** Type of date register + * need_des + */ +typedef union { + struct { + /** pmu_date : R/W; bitpos: [30:0]; default: 36770128; + * need_des + */ + uint32_t pmu_date:31; + /** clk_en : R/W; bitpos: [31]; default: 0; + * need_des + */ + uint32_t clk_en:1; + }; + uint32_t val; +} pmu_date_reg_t; + + +/** Group: status_register */ +/** Type of clk_state0 register + * need_des + */ +typedef union { + struct { + /** stable_xpd_bbpll_state : RO; bitpos: [0]; default: 1; + * need_des + */ + uint32_t stable_xpd_bbpll_state:1; + /** stable_xpd_xtal_state : RO; bitpos: [1]; default: 1; + * need_des + */ + uint32_t stable_xpd_xtal_state:1; + uint32_t reserved_2:13; + /** sys_clk_slp_sel_state : RO; bitpos: [15]; default: 0; + * need_des + */ + uint32_t sys_clk_slp_sel_state:1; + /** sys_clk_sel_state : RO; bitpos: [17:16]; default: 0; + * need_des + */ + uint32_t sys_clk_sel_state:2; + /** sys_clk_no_div_state : RO; bitpos: [18]; default: 0; + * need_des + */ + uint32_t sys_clk_no_div_state:1; + /** icg_sys_clk_en_state : RO; bitpos: [19]; default: 0; + * need_des + */ + uint32_t icg_sys_clk_en_state:1; + /** icg_modem_switch_state : RO; bitpos: [20]; default: 0; + * need_des + */ + uint32_t icg_modem_switch_state:1; + /** icg_modem_code_state : RO; bitpos: [22:21]; default: 0; + * need_des + */ + uint32_t icg_modem_code_state:2; + /** icg_slp_sel_state : RO; bitpos: [23]; default: 0; + * need_des + */ + uint32_t icg_slp_sel_state:1; + /** icg_global_xtal_state : RO; bitpos: [24]; default: 0; + * need_des + */ + uint32_t icg_global_xtal_state:1; + /** icg_global_pll_state : RO; bitpos: [25]; default: 0; + * need_des + */ + uint32_t icg_global_pll_state:1; + /** ana_i2c_iso_en_state : RO; bitpos: [26]; default: 0; + * need_des + */ + uint32_t ana_i2c_iso_en_state:1; + /** ana_i2c_retention_state : RO; bitpos: [27]; default: 0; + * need_des + */ + uint32_t ana_i2c_retention_state:1; + /** ana_xpd_bb_i2c_state : RO; bitpos: [28]; default: 0; + * need_des + */ + uint32_t ana_xpd_bb_i2c_state:1; + /** ana_xpd_bbpll_i2c_state : RO; bitpos: [29]; default: 0; + * need_des + */ + uint32_t ana_xpd_bbpll_i2c_state:1; + /** ana_xpd_bbpll_state : RO; bitpos: [30]; default: 0; + * need_des + */ + uint32_t ana_xpd_bbpll_state:1; + /** ana_xpd_xtal_state : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t ana_xpd_xtal_state:1; + }; + uint32_t val; +} pmu_clk_state0_reg_t; + +/** Type of clk_state1 register + * need_des + */ +typedef union { + struct { + /** icg_func_en_state : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t icg_func_en_state:32; + }; + uint32_t val; +} pmu_clk_state1_reg_t; + +/** Type of clk_state2 register + * need_des + */ +typedef union { + struct { + /** icg_apb_en_state : RO; bitpos: [31:0]; default: 4294967295; + * need_des + */ + uint32_t icg_apb_en_state:32; + }; + uint32_t val; +} pmu_clk_state2_reg_t; + +/** Type of vdd_spi_status register + * need_des + */ +typedef union { + struct { + uint32_t reserved_0:31; + /** stable_vdd_spi_pwr_drv : RO; bitpos: [31]; default: 0; + * need_des + */ + uint32_t stable_vdd_spi_pwr_drv:1; + }; + uint32_t val; +} pmu_vdd_spi_status_reg_t; + + +typedef struct { + volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power; + volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func; + volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb; + volatile pmu_hp_active_icg_modem_reg_t hp_active_icg_modem; + volatile pmu_hp_active_hp_sys_cntl_reg_t hp_active_hp_sys_cntl; + volatile pmu_hp_active_hp_ck_power_reg_t hp_active_hp_ck_power; + volatile pmu_hp_active_bias_reg_t hp_active_bias; + volatile pmu_hp_active_backup_reg_t hp_active_backup; + volatile pmu_hp_active_backup_clk_reg_t hp_active_backup_clk; + volatile pmu_hp_active_sysclk_reg_t hp_active_sysclk; + volatile pmu_hp_active_hp_regulator0_reg_t hp_active_hp_regulator0; + volatile pmu_hp_active_hp_regulator1_reg_t hp_active_hp_regulator1; + volatile pmu_hp_active_xtal_reg_t hp_active_xtal; + volatile pmu_hp_modem_dig_power_reg_t hp_modem_dig_power; + volatile pmu_hp_modem_icg_hp_func_reg_t hp_modem_icg_hp_func; + volatile pmu_hp_modem_icg_hp_apb_reg_t hp_modem_icg_hp_apb; + volatile pmu_hp_modem_icg_modem_reg_t hp_modem_icg_modem; + volatile pmu_hp_modem_hp_sys_cntl_reg_t hp_modem_hp_sys_cntl; + volatile pmu_hp_modem_hp_ck_power_reg_t hp_modem_hp_ck_power; + volatile pmu_hp_modem_bias_reg_t hp_modem_bias; + volatile pmu_hp_modem_backup_reg_t hp_modem_backup; + volatile pmu_hp_modem_backup_clk_reg_t hp_modem_backup_clk; + volatile pmu_hp_modem_sysclk_reg_t hp_modem_sysclk; + volatile pmu_hp_modem_hp_regulator0_reg_t hp_modem_hp_regulator0; + volatile pmu_hp_modem_hp_regulator1_reg_t hp_modem_hp_regulator1; + volatile pmu_hp_modem_xtal_reg_t hp_modem_xtal; + volatile pmu_hp_sleep_dig_power_reg_t hp_sleep_dig_power; + volatile pmu_hp_sleep_icg_hp_func_reg_t hp_sleep_icg_hp_func; + volatile pmu_hp_sleep_icg_hp_apb_reg_t hp_sleep_icg_hp_apb; + volatile pmu_hp_sleep_icg_modem_reg_t hp_sleep_icg_modem; + volatile pmu_hp_sleep_hp_sys_cntl_reg_t hp_sleep_hp_sys_cntl; + volatile pmu_hp_sleep_hp_ck_power_reg_t hp_sleep_hp_ck_power; + volatile pmu_hp_sleep_bias_reg_t hp_sleep_bias; + volatile pmu_hp_sleep_backup_reg_t hp_sleep_backup; + volatile pmu_hp_sleep_backup_clk_reg_t hp_sleep_backup_clk; + volatile pmu_hp_sleep_sysclk_reg_t hp_sleep_sysclk; + volatile pmu_hp_sleep_hp_regulator0_reg_t hp_sleep_hp_regulator0; + volatile pmu_hp_sleep_hp_regulator1_reg_t hp_sleep_hp_regulator1; + volatile pmu_hp_sleep_xtal_reg_t hp_sleep_xtal; + volatile pmu_hp_sleep_lp_regulator0_reg_t hp_sleep_lp_regulator0; + volatile pmu_hp_sleep_lp_regulator1_reg_t hp_sleep_lp_regulator1; + volatile pmu_hp_sleep_lp_dcdc_reserve_reg_t hp_sleep_lp_dcdc_reserve; + volatile pmu_hp_sleep_lp_dig_power_reg_t hp_sleep_lp_dig_power; + volatile pmu_hp_sleep_lp_ck_power_reg_t hp_sleep_lp_ck_power; + volatile pmu_lp_sleep_lp_bias_reserve_reg_t lp_sleep_lp_bias_reserve; + volatile pmu_lp_sleep_lp_regulator0_reg_t lp_sleep_lp_regulator0; + volatile pmu_lp_sleep_lp_regulator1_reg_t lp_sleep_lp_regulator1; + volatile pmu_lp_sleep_xtal_reg_t lp_sleep_xtal; + volatile pmu_lp_sleep_lp_dig_power_reg_t lp_sleep_lp_dig_power; + volatile pmu_lp_sleep_lp_ck_power_reg_t lp_sleep_lp_ck_power; + volatile pmu_lp_sleep_bias_reg_t lp_sleep_bias; + volatile pmu_imm_hp_ck_power_reg_t imm_hp_ck_power; + volatile pmu_imm_sleep_sysclk_reg_t imm_sleep_sysclk; + volatile pmu_imm_hp_func_icg_reg_t imm_hp_func_icg; + volatile pmu_imm_hp_apb_icg_reg_t imm_hp_apb_icg; + volatile pmu_imm_modem_icg_reg_t imm_modem_icg; + volatile pmu_imm_lp_icg_reg_t imm_lp_icg; + volatile pmu_imm_pad_hold_all_reg_t imm_pad_hold_all; + volatile pmu_imm_i2c_iso_reg_t imm_i2c_iso; + volatile pmu_power_wait_timer0_reg_t power_wait_timer0; + volatile pmu_power_wait_timer1_reg_t power_wait_timer1; + volatile pmu_power_wait_timer2_reg_t power_wait_timer2; + volatile pmu_power_pd_top_cntl_reg_t power_pd_top_cntl; + volatile pmu_power_pd_hpaon_cntl_reg_t power_pd_hpaon_cntl; + volatile pmu_power_pd_hpcpu_cntl_reg_t power_pd_hpcpu_cntl; + volatile pmu_power_pd_hpperi_cntl_reg_t power_pd_hpperi_cntl; + volatile pmu_power_pd_hpwifi_cntl_reg_t power_pd_hpwifi_cntl; + volatile pmu_power_pd_lpperi_cntl_reg_t power_pd_lpperi_cntl; + volatile pmu_power_pd_mem_cntl_reg_t power_pd_mem_cntl; + volatile pmu_power_pd_mem_mask_reg_t power_pd_mem_mask; + volatile pmu_power_hp_pad_reg_t power_hp_pad; + volatile pmu_power_vdd_spi_cntl_reg_t power_vdd_spi_cntl; + volatile pmu_power_ck_wait_cntl_reg_t power_ck_wait_cntl; + volatile pmu_slp_wakeup_cntl0_reg_t slp_wakeup_cntl0; + volatile pmu_slp_wakeup_cntl1_reg_t slp_wakeup_cntl1; + volatile pmu_slp_wakeup_cntl2_reg_t slp_wakeup_cntl2; + volatile pmu_slp_wakeup_cntl3_reg_t slp_wakeup_cntl3; + volatile pmu_slp_wakeup_cntl4_reg_t slp_wakeup_cntl4; + volatile pmu_slp_wakeup_cntl5_reg_t slp_wakeup_cntl5; + volatile pmu_slp_wakeup_cntl6_reg_t slp_wakeup_cntl6; + volatile pmu_slp_wakeup_cntl7_reg_t slp_wakeup_cntl7; + volatile pmu_slp_wakeup_status0_reg_t slp_wakeup_status0; + volatile pmu_slp_wakeup_status1_reg_t slp_wakeup_status1; + volatile pmu_hp_ck_poweron_reg_t hp_ck_poweron; + volatile pmu_hp_ck_cntl_reg_t hp_ck_cntl; + volatile pmu_por_status_reg_t por_status; + volatile pmu_rf_pwc_reg_t rf_pwc; + volatile pmu_backup_cfg_reg_t backup_cfg; + volatile pmu_int_raw_reg_t int_raw; + volatile pmu_hp_int_st_reg_t hp_int_st; + volatile pmu_hp_int_ena_reg_t hp_int_ena; + volatile pmu_hp_int_clr_reg_t hp_int_clr; + volatile pmu_lp_int_raw_reg_t lp_int_raw; + volatile pmu_lp_int_st_reg_t lp_int_st; + volatile pmu_lp_int_ena_reg_t lp_int_ena; + volatile pmu_lp_int_clr_reg_t lp_int_clr; + volatile pmu_lp_cpu_pwr0_reg_t lp_cpu_pwr0; + volatile pmu_lp_cpu_pwr1_reg_t lp_cpu_pwr1; + volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_comm; + volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg; + volatile pmu_main_state_reg_t main_state; + volatile pmu_pwr_state_reg_t pwr_state; + volatile pmu_clk_state0_reg_t clk_state0; + volatile pmu_clk_state1_reg_t clk_state1; + volatile pmu_clk_state2_reg_t clk_state2; + volatile pmu_vdd_spi_status_reg_t vdd_spi_status; + volatile pmu_date_reg_t date; +} pmu_dev_t; + +extern pmu_dev_t PMU; + +#ifndef __cplusplus +_Static_assert(sizeof(pmu_dev_t) == 0x1ac, "Invalid size of pmu_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/pvt_reg.h b/components/soc/esp32c61/include/soc/pvt_reg.h new file mode 100644 index 0000000000..b501935008 --- /dev/null +++ b/components/soc/esp32c61/include/soc/pvt_reg.h @@ -0,0 +1,3651 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** PVT_PMUP_BITMAP_HIGH0_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_HIGH0_REG (DR_REG_PVT_BASE + 0x0) +/** PVT_PUMP_BITMAP_HIGH0 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel0 + */ +#define PVT_PUMP_BITMAP_HIGH0 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH0_M (PVT_PUMP_BITMAP_HIGH0_V << PVT_PUMP_BITMAP_HIGH0_S) +#define PVT_PUMP_BITMAP_HIGH0_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH0_S 0 + +/** PVT_PMUP_BITMAP_HIGH1_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_HIGH1_REG (DR_REG_PVT_BASE + 0x4) +/** PVT_PUMP_BITMAP_HIGH1 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel1 + */ +#define PVT_PUMP_BITMAP_HIGH1 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH1_M (PVT_PUMP_BITMAP_HIGH1_V << PVT_PUMP_BITMAP_HIGH1_S) +#define PVT_PUMP_BITMAP_HIGH1_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH1_S 0 + +/** PVT_PMUP_BITMAP_HIGH2_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_HIGH2_REG (DR_REG_PVT_BASE + 0x8) +/** PVT_PUMP_BITMAP_HIGH2 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel2 + */ +#define PVT_PUMP_BITMAP_HIGH2 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH2_M (PVT_PUMP_BITMAP_HIGH2_V << PVT_PUMP_BITMAP_HIGH2_S) +#define PVT_PUMP_BITMAP_HIGH2_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH2_S 0 + +/** PVT_PMUP_BITMAP_HIGH3_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_HIGH3_REG (DR_REG_PVT_BASE + 0xc) +/** PVT_PUMP_BITMAP_HIGH3 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel3 + */ +#define PVT_PUMP_BITMAP_HIGH3 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH3_M (PVT_PUMP_BITMAP_HIGH3_V << PVT_PUMP_BITMAP_HIGH3_S) +#define PVT_PUMP_BITMAP_HIGH3_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH3_S 0 + +/** PVT_PMUP_BITMAP_HIGH4_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_HIGH4_REG (DR_REG_PVT_BASE + 0x10) +/** PVT_PUMP_BITMAP_HIGH4 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel4 + */ +#define PVT_PUMP_BITMAP_HIGH4 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH4_M (PVT_PUMP_BITMAP_HIGH4_V << PVT_PUMP_BITMAP_HIGH4_S) +#define PVT_PUMP_BITMAP_HIGH4_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_HIGH4_S 0 + +/** PVT_PMUP_BITMAP_LOW0_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_LOW0_REG (DR_REG_PVT_BASE + 0x14) +/** PVT_PUMP_BITMAP_LOW0 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel0 + */ +#define PVT_PUMP_BITMAP_LOW0 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW0_M (PVT_PUMP_BITMAP_LOW0_V << PVT_PUMP_BITMAP_LOW0_S) +#define PVT_PUMP_BITMAP_LOW0_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW0_S 0 + +/** PVT_PMUP_BITMAP_LOW1_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_LOW1_REG (DR_REG_PVT_BASE + 0x18) +/** PVT_PUMP_BITMAP_LOW1 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel1 + */ +#define PVT_PUMP_BITMAP_LOW1 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW1_M (PVT_PUMP_BITMAP_LOW1_V << PVT_PUMP_BITMAP_LOW1_S) +#define PVT_PUMP_BITMAP_LOW1_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW1_S 0 + +/** PVT_PMUP_BITMAP_LOW2_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_LOW2_REG (DR_REG_PVT_BASE + 0x1c) +/** PVT_PUMP_BITMAP_LOW2 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel2 + */ +#define PVT_PUMP_BITMAP_LOW2 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW2_M (PVT_PUMP_BITMAP_LOW2_V << PVT_PUMP_BITMAP_LOW2_S) +#define PVT_PUMP_BITMAP_LOW2_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW2_S 0 + +/** PVT_PMUP_BITMAP_LOW3_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_LOW3_REG (DR_REG_PVT_BASE + 0x20) +/** PVT_PUMP_BITMAP_LOW3 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel3 + */ +#define PVT_PUMP_BITMAP_LOW3 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW3_M (PVT_PUMP_BITMAP_LOW3_V << PVT_PUMP_BITMAP_LOW3_S) +#define PVT_PUMP_BITMAP_LOW3_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW3_S 0 + +/** PVT_PMUP_BITMAP_LOW4_REG register + * select valid pvt channel + */ +#define PVT_PMUP_BITMAP_LOW4_REG (DR_REG_PVT_BASE + 0x24) +/** PVT_PUMP_BITMAP_LOW4 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel4 + */ +#define PVT_PUMP_BITMAP_LOW4 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW4_M (PVT_PUMP_BITMAP_LOW4_V << PVT_PUMP_BITMAP_LOW4_S) +#define PVT_PUMP_BITMAP_LOW4_V 0xFFFFFFFFU +#define PVT_PUMP_BITMAP_LOW4_S 0 + +/** PVT_PMUP_DRV_CFG_REG register + * configure pump drv + */ +#define PVT_PMUP_DRV_CFG_REG (DR_REG_PVT_BASE + 0x28) +/** PVT_PUMP_EN : R/W; bitpos: [9]; default: 0; + * configure pvt charge xpd + */ +#define PVT_PUMP_EN (BIT(9)) +#define PVT_PUMP_EN_M (PVT_PUMP_EN_V << PVT_PUMP_EN_S) +#define PVT_PUMP_EN_V 0x00000001U +#define PVT_PUMP_EN_S 9 +/** PVT_CLK_EN : R/W; bitpos: [10]; default: 0; + * force register clken + */ +#define PVT_CLK_EN (BIT(10)) +#define PVT_CLK_EN_M (PVT_CLK_EN_V << PVT_CLK_EN_S) +#define PVT_CLK_EN_V 0x00000001U +#define PVT_CLK_EN_S 10 +/** PVT_PUMP_DRV4 : R/W; bitpos: [14:11]; default: 0; + * configure cmd4 drv + */ +#define PVT_PUMP_DRV4 0x0000000FU +#define PVT_PUMP_DRV4_M (PVT_PUMP_DRV4_V << PVT_PUMP_DRV4_S) +#define PVT_PUMP_DRV4_V 0x0000000FU +#define PVT_PUMP_DRV4_S 11 +/** PVT_PUMP_DRV3 : R/W; bitpos: [18:15]; default: 0; + * configure cmd3 drv + */ +#define PVT_PUMP_DRV3 0x0000000FU +#define PVT_PUMP_DRV3_M (PVT_PUMP_DRV3_V << PVT_PUMP_DRV3_S) +#define PVT_PUMP_DRV3_V 0x0000000FU +#define PVT_PUMP_DRV3_S 15 +/** PVT_PUMP_DRV2 : R/W; bitpos: [22:19]; default: 0; + * configure cmd2 drv + */ +#define PVT_PUMP_DRV2 0x0000000FU +#define PVT_PUMP_DRV2_M (PVT_PUMP_DRV2_V << PVT_PUMP_DRV2_S) +#define PVT_PUMP_DRV2_V 0x0000000FU +#define PVT_PUMP_DRV2_S 19 +/** PVT_PUMP_DRV1 : R/W; bitpos: [26:23]; default: 0; + * configure cmd1 drv + */ +#define PVT_PUMP_DRV1 0x0000000FU +#define PVT_PUMP_DRV1_M (PVT_PUMP_DRV1_V << PVT_PUMP_DRV1_S) +#define PVT_PUMP_DRV1_V 0x0000000FU +#define PVT_PUMP_DRV1_S 23 +/** PVT_PUMP_DRV0 : R/W; bitpos: [30:27]; default: 0; + * configure cmd0 drv + */ +#define PVT_PUMP_DRV0 0x0000000FU +#define PVT_PUMP_DRV0_M (PVT_PUMP_DRV0_V << PVT_PUMP_DRV0_S) +#define PVT_PUMP_DRV0_V 0x0000000FU +#define PVT_PUMP_DRV0_S 27 + +/** PVT_PMUP_CHANNEL_CFG_REG register + * configure the code of valid pump channel code + */ +#define PVT_PMUP_CHANNEL_CFG_REG (DR_REG_PVT_BASE + 0x2c) +/** PVT_PUMP_CHANNEL_CODE4 : R/W; bitpos: [11:7]; default: 0; + * configure cmd4 code + */ +#define PVT_PUMP_CHANNEL_CODE4 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE4_M (PVT_PUMP_CHANNEL_CODE4_V << PVT_PUMP_CHANNEL_CODE4_S) +#define PVT_PUMP_CHANNEL_CODE4_V 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE4_S 7 +/** PVT_PUMP_CHANNEL_CODE3 : R/W; bitpos: [16:12]; default: 0; + * configure cmd3 code + */ +#define PVT_PUMP_CHANNEL_CODE3 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE3_M (PVT_PUMP_CHANNEL_CODE3_V << PVT_PUMP_CHANNEL_CODE3_S) +#define PVT_PUMP_CHANNEL_CODE3_V 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE3_S 12 +/** PVT_PUMP_CHANNEL_CODE2 : R/W; bitpos: [21:17]; default: 0; + * configure cmd2 code + */ +#define PVT_PUMP_CHANNEL_CODE2 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE2_M (PVT_PUMP_CHANNEL_CODE2_V << PVT_PUMP_CHANNEL_CODE2_S) +#define PVT_PUMP_CHANNEL_CODE2_V 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE2_S 17 +/** PVT_PUMP_CHANNEL_CODE1 : R/W; bitpos: [26:22]; default: 0; + * configure cmd1 code + */ +#define PVT_PUMP_CHANNEL_CODE1 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE1_M (PVT_PUMP_CHANNEL_CODE1_V << PVT_PUMP_CHANNEL_CODE1_S) +#define PVT_PUMP_CHANNEL_CODE1_V 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE1_S 22 +/** PVT_PUMP_CHANNEL_CODE0 : R/W; bitpos: [31:27]; default: 0; + * configure cmd0 code + */ +#define PVT_PUMP_CHANNEL_CODE0 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE0_M (PVT_PUMP_CHANNEL_CODE0_V << PVT_PUMP_CHANNEL_CODE0_S) +#define PVT_PUMP_CHANNEL_CODE0_V 0x0000001FU +#define PVT_PUMP_CHANNEL_CODE0_S 27 + +/** PVT_CLK_CFG_REG register + * configure pvt clk + */ +#define PVT_CLK_CFG_REG (DR_REG_PVT_BASE + 0x30) +/** PVT_PUMP_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * needs field desc + */ +#define PVT_PUMP_CLK_DIV_NUM 0x000000FFU +#define PVT_PUMP_CLK_DIV_NUM_M (PVT_PUMP_CLK_DIV_NUM_V << PVT_PUMP_CLK_DIV_NUM_S) +#define PVT_PUMP_CLK_DIV_NUM_V 0x000000FFU +#define PVT_PUMP_CLK_DIV_NUM_S 0 +/** PVT_MONITOR_CLK_PVT_EN : R/W; bitpos: [8]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_CLK_PVT_EN (BIT(8)) +#define PVT_MONITOR_CLK_PVT_EN_M (PVT_MONITOR_CLK_PVT_EN_V << PVT_MONITOR_CLK_PVT_EN_S) +#define PVT_MONITOR_CLK_PVT_EN_V 0x00000001U +#define PVT_MONITOR_CLK_PVT_EN_S 8 +/** PVT_CLK_SEL : R/W; bitpos: [31]; default: 0; + * select pvt clk + */ +#define PVT_CLK_SEL (BIT(31)) +#define PVT_CLK_SEL_M (PVT_CLK_SEL_V << PVT_CLK_SEL_S) +#define PVT_CLK_SEL_V 0x00000001U +#define PVT_CLK_SEL_S 31 + +/** PVT_DBIAS_CHANNEL_SEL0_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL_SEL0_REG (DR_REG_PVT_BASE + 0x34) +/** PVT_DBIAS_CHANNEL3_SEL : R/W; bitpos: [10:4]; default: 64; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL3_SEL 0x0000007FU +#define PVT_DBIAS_CHANNEL3_SEL_M (PVT_DBIAS_CHANNEL3_SEL_V << PVT_DBIAS_CHANNEL3_SEL_S) +#define PVT_DBIAS_CHANNEL3_SEL_V 0x0000007FU +#define PVT_DBIAS_CHANNEL3_SEL_S 4 +/** PVT_DBIAS_CHANNEL2_SEL : R/W; bitpos: [17:11]; default: 64; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL2_SEL 0x0000007FU +#define PVT_DBIAS_CHANNEL2_SEL_M (PVT_DBIAS_CHANNEL2_SEL_V << PVT_DBIAS_CHANNEL2_SEL_S) +#define PVT_DBIAS_CHANNEL2_SEL_V 0x0000007FU +#define PVT_DBIAS_CHANNEL2_SEL_S 11 +/** PVT_DBIAS_CHANNEL1_SEL : R/W; bitpos: [24:18]; default: 64; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL1_SEL 0x0000007FU +#define PVT_DBIAS_CHANNEL1_SEL_M (PVT_DBIAS_CHANNEL1_SEL_V << PVT_DBIAS_CHANNEL1_SEL_S) +#define PVT_DBIAS_CHANNEL1_SEL_V 0x0000007FU +#define PVT_DBIAS_CHANNEL1_SEL_S 18 +/** PVT_DBIAS_CHANNEL0_SEL : R/W; bitpos: [31:25]; default: 64; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL0_SEL 0x0000007FU +#define PVT_DBIAS_CHANNEL0_SEL_M (PVT_DBIAS_CHANNEL0_SEL_V << PVT_DBIAS_CHANNEL0_SEL_S) +#define PVT_DBIAS_CHANNEL0_SEL_V 0x0000007FU +#define PVT_DBIAS_CHANNEL0_SEL_S 25 + +/** PVT_DBIAS_CHANNEL_SEL1_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL_SEL1_REG (DR_REG_PVT_BASE + 0x38) +/** PVT_DBIAS_CHANNEL4_SEL : R/W; bitpos: [31:25]; default: 64; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL4_SEL 0x0000007FU +#define PVT_DBIAS_CHANNEL4_SEL_M (PVT_DBIAS_CHANNEL4_SEL_V << PVT_DBIAS_CHANNEL4_SEL_S) +#define PVT_DBIAS_CHANNEL4_SEL_V 0x0000007FU +#define PVT_DBIAS_CHANNEL4_SEL_S 25 + +/** PVT_DBIAS_CHANNEL0_SEL_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL0_SEL_REG (DR_REG_PVT_BASE + 0x3c) +/** PVT_DBIAS_CHANNEL0_CFG : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL0_CFG 0x0001FFFFU +#define PVT_DBIAS_CHANNEL0_CFG_M (PVT_DBIAS_CHANNEL0_CFG_V << PVT_DBIAS_CHANNEL0_CFG_S) +#define PVT_DBIAS_CHANNEL0_CFG_V 0x0001FFFFU +#define PVT_DBIAS_CHANNEL0_CFG_S 0 + +/** PVT_DBIAS_CHANNEL1_SEL_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL1_SEL_REG (DR_REG_PVT_BASE + 0x40) +/** PVT_DBIAS_CHANNEL1_CFG : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL1_CFG 0x0001FFFFU +#define PVT_DBIAS_CHANNEL1_CFG_M (PVT_DBIAS_CHANNEL1_CFG_V << PVT_DBIAS_CHANNEL1_CFG_S) +#define PVT_DBIAS_CHANNEL1_CFG_V 0x0001FFFFU +#define PVT_DBIAS_CHANNEL1_CFG_S 0 + +/** PVT_DBIAS_CHANNEL2_SEL_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL2_SEL_REG (DR_REG_PVT_BASE + 0x44) +/** PVT_DBIAS_CHANNEL2_CFG : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL2_CFG 0x0001FFFFU +#define PVT_DBIAS_CHANNEL2_CFG_M (PVT_DBIAS_CHANNEL2_CFG_V << PVT_DBIAS_CHANNEL2_CFG_S) +#define PVT_DBIAS_CHANNEL2_CFG_V 0x0001FFFFU +#define PVT_DBIAS_CHANNEL2_CFG_S 0 + +/** PVT_DBIAS_CHANNEL3_SEL_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL3_SEL_REG (DR_REG_PVT_BASE + 0x48) +/** PVT_DBIAS_CHANNEL3_CFG : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL3_CFG 0x0001FFFFU +#define PVT_DBIAS_CHANNEL3_CFG_M (PVT_DBIAS_CHANNEL3_CFG_V << PVT_DBIAS_CHANNEL3_CFG_S) +#define PVT_DBIAS_CHANNEL3_CFG_V 0x0001FFFFU +#define PVT_DBIAS_CHANNEL3_CFG_S 0 + +/** PVT_DBIAS_CHANNEL4_SEL_REG register + * needs desc + */ +#define PVT_DBIAS_CHANNEL4_SEL_REG (DR_REG_PVT_BASE + 0x4c) +/** PVT_DBIAS_CHANNEL4_CFG : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CHANNEL4_CFG 0x0001FFFFU +#define PVT_DBIAS_CHANNEL4_CFG_M (PVT_DBIAS_CHANNEL4_CFG_V << PVT_DBIAS_CHANNEL4_CFG_S) +#define PVT_DBIAS_CHANNEL4_CFG_V 0x0001FFFFU +#define PVT_DBIAS_CHANNEL4_CFG_S 0 + +/** PVT_DBIAS_CMD0_REG register + * needs desc + */ +#define PVT_DBIAS_CMD0_REG (DR_REG_PVT_BASE + 0x50) +/** PVT_DBIAS_CMD0 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CMD0 0x0001FFFFU +#define PVT_DBIAS_CMD0_M (PVT_DBIAS_CMD0_V << PVT_DBIAS_CMD0_S) +#define PVT_DBIAS_CMD0_V 0x0001FFFFU +#define PVT_DBIAS_CMD0_S 0 + +/** PVT_DBIAS_CMD1_REG register + * needs desc + */ +#define PVT_DBIAS_CMD1_REG (DR_REG_PVT_BASE + 0x54) +/** PVT_DBIAS_CMD1 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CMD1 0x0001FFFFU +#define PVT_DBIAS_CMD1_M (PVT_DBIAS_CMD1_V << PVT_DBIAS_CMD1_S) +#define PVT_DBIAS_CMD1_V 0x0001FFFFU +#define PVT_DBIAS_CMD1_S 0 + +/** PVT_DBIAS_CMD2_REG register + * needs desc + */ +#define PVT_DBIAS_CMD2_REG (DR_REG_PVT_BASE + 0x58) +/** PVT_DBIAS_CMD2 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CMD2 0x0001FFFFU +#define PVT_DBIAS_CMD2_M (PVT_DBIAS_CMD2_V << PVT_DBIAS_CMD2_S) +#define PVT_DBIAS_CMD2_V 0x0001FFFFU +#define PVT_DBIAS_CMD2_S 0 + +/** PVT_DBIAS_CMD3_REG register + * needs desc + */ +#define PVT_DBIAS_CMD3_REG (DR_REG_PVT_BASE + 0x5c) +/** PVT_DBIAS_CMD3 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CMD3 0x0001FFFFU +#define PVT_DBIAS_CMD3_M (PVT_DBIAS_CMD3_V << PVT_DBIAS_CMD3_S) +#define PVT_DBIAS_CMD3_V 0x0001FFFFU +#define PVT_DBIAS_CMD3_S 0 + +/** PVT_DBIAS_CMD4_REG register + * needs desc + */ +#define PVT_DBIAS_CMD4_REG (DR_REG_PVT_BASE + 0x60) +/** PVT_DBIAS_CMD4 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ +#define PVT_DBIAS_CMD4 0x0001FFFFU +#define PVT_DBIAS_CMD4_M (PVT_DBIAS_CMD4_V << PVT_DBIAS_CMD4_S) +#define PVT_DBIAS_CMD4_V 0x0001FFFFU +#define PVT_DBIAS_CMD4_S 0 + +/** PVT_DBIAS_TIMER_REG register + * needs desc + */ +#define PVT_DBIAS_TIMER_REG (DR_REG_PVT_BASE + 0x64) +/** PVT_TIMER_TARGET : R/W; bitpos: [30:15]; default: 65535; + * needs field desc + */ +#define PVT_TIMER_TARGET 0x0000FFFFU +#define PVT_TIMER_TARGET_M (PVT_TIMER_TARGET_V << PVT_TIMER_TARGET_S) +#define PVT_TIMER_TARGET_V 0x0000FFFFU +#define PVT_TIMER_TARGET_S 15 +/** PVT_TIMER_EN : R/W; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMER_EN (BIT(31)) +#define PVT_TIMER_EN_M (PVT_TIMER_EN_V << PVT_TIMER_EN_S) +#define PVT_TIMER_EN_V 0x00000001U +#define PVT_TIMER_EN_S 31 + +/** PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x68) +/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_M (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_S) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_M (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_M (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_S 31 + +/** PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x6c) +/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_M (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_S) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_M (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_M (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_S 31 + +/** PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x70) +/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_M (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_S) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_M (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_M (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_S 31 + +/** PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x74) +/** PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_M (PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_V << PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_S) +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_M (PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_V << PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_M (PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_V << PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_S 31 + +/** PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x78) +/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_M (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_S) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_M (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_M (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_S 31 + +/** PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x7c) +/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_M (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_S) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_M (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_M (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_S 31 + +/** PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x80) +/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_M (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_S) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_M (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_M (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_S 31 + +/** PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x84) +/** PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_M (PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_V << PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_S) +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_M (PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_V << PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_M (PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_V << PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_S 31 + +/** PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x88) +/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_M (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_S) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_M (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_M (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_S 31 + +/** PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x8c) +/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_M (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_S) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_M (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_M (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_S 31 + +/** PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x90) +/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_M (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_S) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_M (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_M (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_S 31 + +/** PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x94) +/** PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_M (PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_V << PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_S) +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_M (PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_V << PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_M (PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_V << PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_S 31 + +/** PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x98) +/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_M (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_S) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_M (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_M (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_S 31 + +/** PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x9c) +/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_M (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_S) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_M (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_M (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_S 31 + +/** PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xa0) +/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_M (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_S) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_M (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_M (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_S 31 + +/** PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xa4) +/** PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_M (PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_V << PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_S) +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_M (PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_V << PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_M (PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_V << PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_S 31 + +/** PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xa8) +/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_M (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_S) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_M (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_M (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_S 31 + +/** PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xac) +/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_M (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_S) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_M (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_M (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_S 31 + +/** PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xb0) +/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_M (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_S) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_M (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_M (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_S 31 + +/** PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xb4) +/** PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_M (PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_V << PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_S) +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_M (PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_V << PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_M (PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_V << PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_S 31 + +/** PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xb8) +/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_M (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_S) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_M (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_M (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_S 31 + +/** PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xbc) +/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_M (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_S) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_M (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_M (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_S 31 + +/** PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xc0) +/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_M (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_S) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_M (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_M (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_S 31 + +/** PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xc4) +/** PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_M (PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_V << PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_S) +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_M (PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_V << PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_M (PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_V << PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_S 31 + +/** PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xc8) +/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_M (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_S) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_M (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_M (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_S 31 + +/** PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xcc) +/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_M (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_S) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_M (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_M (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_S 31 + +/** PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xd0) +/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_M (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_S) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_M (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_M (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_S 31 + +/** PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xd4) +/** PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_M (PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_V << PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_S) +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_M (PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_V << PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_M (PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_V << PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_S 31 + +/** PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xd8) +/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_M (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_S) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_M (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_M (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_S 31 + +/** PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xdc) +/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_M (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_S) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_M (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_M (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_S 31 + +/** PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xe0) +/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_M (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_S) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_M (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_M (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_S 31 + +/** PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_REG (DR_REG_PVT_BASE + 0xe4) +/** PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_M (PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_V << PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_S) +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_M (PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_V << PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_M (PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_V << PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_S 31 + +/** PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xe8) +/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_M (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_S) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_M (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_M (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_S 31 + +/** PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xec) +/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_M (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_S) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_M (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_M (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_S 31 + +/** PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xf0) +/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_M (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_S) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_M (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_M (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_S 31 + +/** PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_REG (DR_REG_PVT_BASE + 0xf4) +/** PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_M (PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_V << PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_S) +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_M (PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_V << PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_M (PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_V << PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_S 31 + +/** PVT_COMB_PD_SITE3_UNIT0_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT0_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xf8) +/** PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0_M (PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0_V << PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0_S) +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0_M (PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0_V << PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0_M (PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0_V << PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT0_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0_M (PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0_S) +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT0_S 31 + +/** PVT_COMB_PD_SITE3_UNIT1_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT1_VT0_CONF1_REG (DR_REG_PVT_BASE + 0xfc) +/** PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1_M (PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1_V << PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1_S) +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1_M (PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1_V << PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1_M (PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1_V << PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT1_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1_M (PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1_S) +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT1_S 31 + +/** PVT_COMB_PD_SITE3_UNIT2_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT2_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x100) +/** PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2_M (PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2_V << PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2_S) +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2_M (PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2_V << PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2_M (PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2_V << PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT2_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2_M (PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2_S) +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT2_S 31 + +/** PVT_COMB_PD_SITE3_UNIT3_VT0_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT3_VT0_CONF1_REG (DR_REG_PVT_BASE + 0x104) +/** PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3_M (PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3_V << PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3_S) +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT0_PD_SITE3_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3_M (PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3_V << PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3_S) +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT0_PD_SITE3_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3_M (PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3_V << PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3_S) +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT0_PD_SITE3_UNIT3_S 23 +/** PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3_M (PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3_S) +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT0_PD_SITE3_UNIT3_S 31 + +/** PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT0_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x108) +/** PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_M (PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_V << PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_S) +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_M (PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_V << PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0_M (PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0_V << PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT0_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0_M (PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0_S) +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT0_S 31 + +/** PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT1_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x10c) +/** PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1_M (PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1_V << PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1_S) +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_M (PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_V << PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1_M (PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1_V << PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT1_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1_M (PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1_S) +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT1_S 31 + +/** PVT_COMB_PD_SITE3_UNIT2_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT2_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x110) +/** PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2_M (PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2_V << PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2_S) +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2_M (PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2_V << PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2_M (PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2_V << PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT2_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2_M (PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2_S) +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT2_S 31 + +/** PVT_COMB_PD_SITE3_UNIT3_VT1_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT3_VT1_CONF1_REG (DR_REG_PVT_BASE + 0x114) +/** PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3_M (PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3_V << PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3_S) +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT1_PD_SITE3_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3_M (PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3_V << PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3_S) +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT1_PD_SITE3_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3_M (PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3_V << PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3_S) +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT1_PD_SITE3_UNIT3_S 23 +/** PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3_M (PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3_S) +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT1_PD_SITE3_UNIT3_S 31 + +/** PVT_COMB_PD_SITE3_UNIT0_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT0_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x118) +/** PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0_M (PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0_V << PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0_S) +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT0_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0_M (PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0_V << PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT0_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0_M (PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0_V << PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT0_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0_M (PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0_S) +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT0_S 31 + +/** PVT_COMB_PD_SITE3_UNIT1_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT1_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x11c) +/** PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1_M (PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1_V << PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1_S) +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT1_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1_M (PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1_V << PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT1_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1_M (PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1_V << PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT1_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1_M (PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1_S) +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT1_S 31 + +/** PVT_COMB_PD_SITE3_UNIT2_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT2_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x120) +/** PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2_M (PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2_V << PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2_S) +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT2_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2_M (PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2_V << PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT2_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2_M (PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2_V << PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT2_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2_M (PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2_S) +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT2_S 31 + +/** PVT_COMB_PD_SITE3_UNIT3_VT2_CONF1_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT3_VT2_CONF1_REG (DR_REG_PVT_BASE + 0x124) +/** PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3 (BIT(0)) +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3_M (PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3_V << PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3_S) +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_MONITOR_EN_VT2_PD_SITE3_UNIT3_S 0 +/** PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3 (BIT(1)) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_M (PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_S) +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3_S 1 +/** PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3_M (PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3_V << PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3_S) +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3_V 0x000000FFU +#define PVT_DELAY_LIMIT_VT2_PD_SITE3_UNIT3_S 2 +/** PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3_M (PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3_V << PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3_S) +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3_V 0x000000FFU +#define PVT_DELAY_NUM_O_VT2_PD_SITE3_UNIT3_S 23 +/** PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3 (BIT(31)) +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3_M (PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3_S) +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_TIMING_ERR_VT2_PD_SITE3_UNIT3_S 31 + +/** PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x128) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_M (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_S) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_S 16 + +/** PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x12c) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_M (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_S) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_S 16 + +/** PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x130) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_M (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_S) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_S 16 + +/** PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x134) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_M (PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_V << PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_S) +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_S 16 + +/** PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x138) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_M (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_S) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_S 16 + +/** PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x13c) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_M (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_S) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_S 16 + +/** PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x140) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_M (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_S) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_S 16 + +/** PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x144) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_M (PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_V << PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_S) +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_S 16 + +/** PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x148) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_M (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_S) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_S 16 + +/** PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x14c) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_M (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_S) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_S 16 + +/** PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x150) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_M (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_S) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_S 16 + +/** PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x154) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_M (PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_V << PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_S) +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_S 16 + +/** PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x158) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_M (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_S) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_S 16 + +/** PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x15c) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_M (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_S) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_S 16 + +/** PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x160) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_M (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_S) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_S 16 + +/** PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x164) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_M (PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_V << PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_S) +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_S 16 + +/** PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x168) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_M (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_S) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_S 16 + +/** PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x16c) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_M (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_S) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_S 16 + +/** PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x170) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_M (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_S) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_S 16 + +/** PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x174) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_M (PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_V << PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_S) +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_S 16 + +/** PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x178) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_M (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_S) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_S 16 + +/** PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x17c) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_M (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_S) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_S 16 + +/** PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x180) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_M (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_S) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_S 16 + +/** PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x184) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_M (PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_V << PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_S) +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_S 16 + +/** PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x188) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_M (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_S) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_S 16 + +/** PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x18c) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_M (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_S) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_S 16 + +/** PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x190) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_M (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_S) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_S 16 + +/** PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x194) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_M (PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_V << PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_S) +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_S 16 + +/** PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x198) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_M (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_S) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_S 16 + +/** PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x19c) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_M (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_S) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_S 16 + +/** PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x1a0) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_M (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_S) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_S 16 + +/** PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x1a4) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_M (PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_V << PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_S) +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_S 16 + +/** PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1a8) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_M (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_S) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_S 16 + +/** PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1ac) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_M (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_S) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_S 16 + +/** PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1b0) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_M (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_S) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_S 16 + +/** PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1b4) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_M (PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_V << PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_S) +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_S 16 + +/** PVT_COMB_PD_SITE3_UNIT0_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT0_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x1b8) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0_M (PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0_V << PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0_S) +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0_S 16 + +/** PVT_COMB_PD_SITE3_UNIT1_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT1_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x1bc) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1_M (PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1_V << PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1_S) +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1_S 16 + +/** PVT_COMB_PD_SITE3_UNIT2_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT2_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x1c0) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2_M (PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2_V << PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2_S) +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2_S 16 + +/** PVT_COMB_PD_SITE3_UNIT3_VT0_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT3_VT0_CONF2_REG (DR_REG_PVT_BASE + 0x1c4) +/** PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_M (PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_V << PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3_S 0 +/** PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3_M (PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3_V << PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3_S) +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT0_PD_SITE3_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3_S 16 + +/** PVT_COMB_PD_SITE3_UNIT0_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT0_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x1c8) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0_M (PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0_V << PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0_S) +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0_S 16 + +/** PVT_COMB_PD_SITE3_UNIT1_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT1_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x1cc) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1_M (PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1_V << PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1_S) +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1_S 16 + +/** PVT_COMB_PD_SITE3_UNIT2_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT2_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x1d0) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2_M (PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2_V << PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2_S) +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2_S 16 + +/** PVT_COMB_PD_SITE3_UNIT3_VT1_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT3_VT1_CONF2_REG (DR_REG_PVT_BASE + 0x1d4) +/** PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_M (PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_V << PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3_S 0 +/** PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3_M (PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3_V << PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3_S) +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT1_PD_SITE3_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3_S 16 + +/** PVT_COMB_PD_SITE3_UNIT0_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT0_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1d8) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0_M (PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0_V << PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0_S) +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT0_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0_S 16 + +/** PVT_COMB_PD_SITE3_UNIT1_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT1_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1dc) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1_M (PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1_V << PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1_S) +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT1_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1_S 16 + +/** PVT_COMB_PD_SITE3_UNIT2_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT2_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1e0) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2_M (PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2_V << PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2_S) +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT2_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2_S 16 + +/** PVT_COMB_PD_SITE3_UNIT3_VT2_CONF2_REG register + * needs desc + */ +#define PVT_COMB_PD_SITE3_UNIT3_VT2_CONF2_REG (DR_REG_PVT_BASE + 0x1e4) +/** PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_M (PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_V << PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_S) +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_V 0x00000003U +#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3_S 0 +/** PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3 (BIT(15)) +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3_M (PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3_V << PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3_S) +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3_V 0x00000001U +#define PVT_DELAY_OVF_VT2_PD_SITE3_UNIT3_S 15 +/** PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_M (PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_V << PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_S) +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_V 0x0000FFFFU +#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3_S 16 + +/** PVT_VALUE_UPDATE_REG register + * needs field desc + */ +#define PVT_VALUE_UPDATE_REG (DR_REG_PVT_BASE + 0x1e8) +/** PVT_VALUE_UPDATE : WT; bitpos: [0]; default: 0; + * needs field desc + */ +#define PVT_VALUE_UPDATE (BIT(0)) +#define PVT_VALUE_UPDATE_M (PVT_VALUE_UPDATE_V << PVT_VALUE_UPDATE_S) +#define PVT_VALUE_UPDATE_V 0x00000001U +#define PVT_VALUE_UPDATE_S 0 +/** PVT_VALUE_UPDATE_BYPASS : R/W; bitpos: [1]; default: 0; + * needs field desc + */ +#define PVT_VALUE_UPDATE_BYPASS (BIT(1)) +#define PVT_VALUE_UPDATE_BYPASS_M (PVT_VALUE_UPDATE_BYPASS_V << PVT_VALUE_UPDATE_BYPASS_S) +#define PVT_VALUE_UPDATE_BYPASS_V 0x00000001U +#define PVT_VALUE_UPDATE_BYPASS_S 1 + +/** PVT_BYPASS_CHAIN_REG register + * needs field desc + */ +#define PVT_BYPASS_CHAIN_REG (DR_REG_PVT_BASE + 0x1ec) +/** PVT_CLK_CHAIN_EN : R/W; bitpos: [31:0]; default: 4294967295; + * needs field desc + */ +#define PVT_CLK_CHAIN_EN 0xFFFFFFFFU +#define PVT_CLK_CHAIN_EN_M (PVT_CLK_CHAIN_EN_V << PVT_CLK_CHAIN_EN_S) +#define PVT_CLK_CHAIN_EN_V 0xFFFFFFFFU +#define PVT_CLK_CHAIN_EN_S 0 + +/** PVT_DATE_REG register + * version register + */ +#define PVT_DATE_REG (DR_REG_PVT_BASE + 0xffc) +/** PVT_DATE : R/W; bitpos: [31:0]; default: 34677040; + * version register + */ +#define PVT_DATE 0xFFFFFFFFU +#define PVT_DATE_M (PVT_DATE_V << PVT_DATE_S) +#define PVT_DATE_V 0xFFFFFFFFU +#define PVT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/pvt_struct.h b/components/soc/esp32c61/include/soc/pvt_struct.h new file mode 100644 index 0000000000..875bcd5308 --- /dev/null +++ b/components/soc/esp32c61/include/soc/pvt_struct.h @@ -0,0 +1,3113 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: configure register */ +/** Type of pmup_bitmap_high0 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_high0 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel0 + */ + uint32_t pump_bitmap_high0:32; + }; + uint32_t val; +} pvt_pmup_bitmap_high0_reg_t; + +/** Type of pmup_bitmap_high1 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_high1 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel1 + */ + uint32_t pump_bitmap_high1:32; + }; + uint32_t val; +} pvt_pmup_bitmap_high1_reg_t; + +/** Type of pmup_bitmap_high2 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_high2 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel2 + */ + uint32_t pump_bitmap_high2:32; + }; + uint32_t val; +} pvt_pmup_bitmap_high2_reg_t; + +/** Type of pmup_bitmap_high3 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_high3 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel3 + */ + uint32_t pump_bitmap_high3:32; + }; + uint32_t val; +} pvt_pmup_bitmap_high3_reg_t; + +/** Type of pmup_bitmap_high4 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_high4 : R/W; bitpos: [31:0]; default: 0; + * select valid high channel4 + */ + uint32_t pump_bitmap_high4:32; + }; + uint32_t val; +} pvt_pmup_bitmap_high4_reg_t; + +/** Type of pmup_bitmap_low0 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_low0 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel0 + */ + uint32_t pump_bitmap_low0:32; + }; + uint32_t val; +} pvt_pmup_bitmap_low0_reg_t; + +/** Type of pmup_bitmap_low1 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_low1 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel1 + */ + uint32_t pump_bitmap_low1:32; + }; + uint32_t val; +} pvt_pmup_bitmap_low1_reg_t; + +/** Type of pmup_bitmap_low2 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_low2 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel2 + */ + uint32_t pump_bitmap_low2:32; + }; + uint32_t val; +} pvt_pmup_bitmap_low2_reg_t; + +/** Type of pmup_bitmap_low3 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_low3 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel3 + */ + uint32_t pump_bitmap_low3:32; + }; + uint32_t val; +} pvt_pmup_bitmap_low3_reg_t; + +/** Type of pmup_bitmap_low4 register + * select valid pvt channel + */ +typedef union { + struct { + /** pump_bitmap_low4 : R/W; bitpos: [31:0]; default: 0; + * select valid low channel4 + */ + uint32_t pump_bitmap_low4:32; + }; + uint32_t val; +} pvt_pmup_bitmap_low4_reg_t; + +/** Type of pmup_drv_cfg register + * configure pump drv + */ +typedef union { + struct { + uint32_t reserved_0:9; + /** pump_en : R/W; bitpos: [9]; default: 0; + * configure pvt charge xpd + */ + uint32_t pump_en:1; + /** clk_en : R/W; bitpos: [10]; default: 0; + * force register clken + */ + uint32_t clk_en:1; + /** pump_drv4 : R/W; bitpos: [14:11]; default: 0; + * configure cmd4 drv + */ + uint32_t pump_drv4:4; + /** pump_drv3 : R/W; bitpos: [18:15]; default: 0; + * configure cmd3 drv + */ + uint32_t pump_drv3:4; + /** pump_drv2 : R/W; bitpos: [22:19]; default: 0; + * configure cmd2 drv + */ + uint32_t pump_drv2:4; + /** pump_drv1 : R/W; bitpos: [26:23]; default: 0; + * configure cmd1 drv + */ + uint32_t pump_drv1:4; + /** pump_drv0 : R/W; bitpos: [30:27]; default: 0; + * configure cmd0 drv + */ + uint32_t pump_drv0:4; + uint32_t reserved_31:1; + }; + uint32_t val; +} pvt_pmup_drv_cfg_reg_t; + +/** Type of pmup_channel_cfg register + * configure the code of valid pump channel code + */ +typedef union { + struct { + uint32_t reserved_0:7; + /** pump_channel_code4 : R/W; bitpos: [11:7]; default: 0; + * configure cmd4 code + */ + uint32_t pump_channel_code4:5; + /** pump_channel_code3 : R/W; bitpos: [16:12]; default: 0; + * configure cmd3 code + */ + uint32_t pump_channel_code3:5; + /** pump_channel_code2 : R/W; bitpos: [21:17]; default: 0; + * configure cmd2 code + */ + uint32_t pump_channel_code2:5; + /** pump_channel_code1 : R/W; bitpos: [26:22]; default: 0; + * configure cmd1 code + */ + uint32_t pump_channel_code1:5; + /** pump_channel_code0 : R/W; bitpos: [31:27]; default: 0; + * configure cmd0 code + */ + uint32_t pump_channel_code0:5; + }; + uint32_t val; +} pvt_pmup_channel_cfg_reg_t; + +/** Type of clk_cfg register + * configure pvt clk + */ +typedef union { + struct { + /** pump_clk_div_num : R/W; bitpos: [7:0]; default: 0; + * needs field desc + */ + uint32_t pump_clk_div_num:8; + /** monitor_clk_pvt_en : R/W; bitpos: [8]; default: 0; + * needs field desc + */ + uint32_t monitor_clk_pvt_en:1; + uint32_t reserved_9:22; + /** clk_sel : R/W; bitpos: [31]; default: 0; + * select pvt clk + */ + uint32_t clk_sel:1; + }; + uint32_t val; +} pvt_clk_cfg_reg_t; + +/** Type of dbias_channel_sel0 register + * needs desc + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** dbias_channel3_sel : R/W; bitpos: [10:4]; default: 64; + * needs field desc + */ + uint32_t dbias_channel3_sel:7; + /** dbias_channel2_sel : R/W; bitpos: [17:11]; default: 64; + * needs field desc + */ + uint32_t dbias_channel2_sel:7; + /** dbias_channel1_sel : R/W; bitpos: [24:18]; default: 64; + * needs field desc + */ + uint32_t dbias_channel1_sel:7; + /** dbias_channel0_sel : R/W; bitpos: [31:25]; default: 64; + * needs field desc + */ + uint32_t dbias_channel0_sel:7; + }; + uint32_t val; +} pvt_dbias_channel_sel0_reg_t; + +/** Type of dbias_channel_sel1 register + * needs desc + */ +typedef union { + struct { + uint32_t reserved_0:25; + /** dbias_channel4_sel : R/W; bitpos: [31:25]; default: 64; + * needs field desc + */ + uint32_t dbias_channel4_sel:7; + }; + uint32_t val; +} pvt_dbias_channel_sel1_reg_t; + +/** Type of dbias_channel0_sel register + * needs desc + */ +typedef union { + struct { + /** dbias_channel0_cfg : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_channel0_cfg:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_channel0_sel_reg_t; + +/** Type of dbias_channel1_sel register + * needs desc + */ +typedef union { + struct { + /** dbias_channel1_cfg : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_channel1_cfg:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_channel1_sel_reg_t; + +/** Type of dbias_channel2_sel register + * needs desc + */ +typedef union { + struct { + /** dbias_channel2_cfg : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_channel2_cfg:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_channel2_sel_reg_t; + +/** Type of dbias_channel3_sel register + * needs desc + */ +typedef union { + struct { + /** dbias_channel3_cfg : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_channel3_cfg:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_channel3_sel_reg_t; + +/** Type of dbias_channel4_sel register + * needs desc + */ +typedef union { + struct { + /** dbias_channel4_cfg : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_channel4_cfg:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_channel4_sel_reg_t; + +/** Type of dbias_cmd0 register + * needs desc + */ +typedef union { + struct { + /** dbias_cmd0 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_cmd0:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_cmd0_reg_t; + +/** Type of dbias_cmd1 register + * needs desc + */ +typedef union { + struct { + /** dbias_cmd1 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_cmd1:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_cmd1_reg_t; + +/** Type of dbias_cmd2 register + * needs desc + */ +typedef union { + struct { + /** dbias_cmd2 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_cmd2:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_cmd2_reg_t; + +/** Type of dbias_cmd3 register + * needs desc + */ +typedef union { + struct { + /** dbias_cmd3 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_cmd3:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_cmd3_reg_t; + +/** Type of dbias_cmd4 register + * needs desc + */ +typedef union { + struct { + /** dbias_cmd4 : R/W; bitpos: [16:0]; default: 0; + * needs field desc + */ + uint32_t dbias_cmd4:17; + uint32_t reserved_17:15; + }; + uint32_t val; +} pvt_dbias_cmd4_reg_t; + +/** Type of dbias_timer register + * needs desc + */ +typedef union { + struct { + uint32_t reserved_0:15; + /** timer_target : R/W; bitpos: [30:15]; default: 65535; + * needs field desc + */ + uint32_t timer_target:16; + /** timer_en : R/W; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timer_en:1; + }; + uint32_t val; +} pvt_dbias_timer_reg_t; + +/** Type of comb_pd_site0_unit0_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site0_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site0_unit0:1; + /** timing_err_cnt_clr_vt0_pd_site0_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site0_unit0:1; + /** delay_limit_vt0_pd_site0_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site0_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site0_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site0_unit0:8; + /** timing_err_vt0_pd_site0_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site0_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit0_vt0_conf1_reg_t; + +/** Type of comb_pd_site0_unit1_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site0_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site0_unit1:1; + /** timing_err_cnt_clr_vt0_pd_site0_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site0_unit1:1; + /** delay_limit_vt0_pd_site0_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site0_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site0_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site0_unit1:8; + /** timing_err_vt0_pd_site0_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site0_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit1_vt0_conf1_reg_t; + +/** Type of comb_pd_site0_unit2_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site0_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site0_unit2:1; + /** timing_err_cnt_clr_vt0_pd_site0_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site0_unit2:1; + /** delay_limit_vt0_pd_site0_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site0_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site0_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site0_unit2:8; + /** timing_err_vt0_pd_site0_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site0_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit2_vt0_conf1_reg_t; + +/** Type of comb_pd_site0_unit3_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site0_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site0_unit3:1; + /** timing_err_cnt_clr_vt0_pd_site0_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site0_unit3:1; + /** delay_limit_vt0_pd_site0_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site0_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site0_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site0_unit3:8; + /** timing_err_vt0_pd_site0_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site0_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit3_vt0_conf1_reg_t; + +/** Type of comb_pd_site0_unit0_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site0_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site0_unit0:1; + /** timing_err_cnt_clr_vt1_pd_site0_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site0_unit0:1; + /** delay_limit_vt1_pd_site0_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site0_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site0_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site0_unit0:8; + /** timing_err_vt1_pd_site0_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site0_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit0_vt1_conf1_reg_t; + +/** Type of comb_pd_site0_unit1_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site0_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site0_unit1:1; + /** timing_err_cnt_clr_vt1_pd_site0_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site0_unit1:1; + /** delay_limit_vt1_pd_site0_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site0_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site0_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site0_unit1:8; + /** timing_err_vt1_pd_site0_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site0_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit1_vt1_conf1_reg_t; + +/** Type of comb_pd_site0_unit2_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site0_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site0_unit2:1; + /** timing_err_cnt_clr_vt1_pd_site0_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site0_unit2:1; + /** delay_limit_vt1_pd_site0_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site0_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site0_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site0_unit2:8; + /** timing_err_vt1_pd_site0_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site0_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit2_vt1_conf1_reg_t; + +/** Type of comb_pd_site0_unit3_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site0_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site0_unit3:1; + /** timing_err_cnt_clr_vt1_pd_site0_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site0_unit3:1; + /** delay_limit_vt1_pd_site0_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site0_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site0_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site0_unit3:8; + /** timing_err_vt1_pd_site0_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site0_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit3_vt1_conf1_reg_t; + +/** Type of comb_pd_site0_unit0_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site0_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site0_unit0:1; + /** timing_err_cnt_clr_vt2_pd_site0_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site0_unit0:1; + /** delay_limit_vt2_pd_site0_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site0_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site0_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site0_unit0:8; + /** timing_err_vt2_pd_site0_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site0_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit0_vt2_conf1_reg_t; + +/** Type of comb_pd_site0_unit1_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site0_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site0_unit1:1; + /** timing_err_cnt_clr_vt2_pd_site0_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site0_unit1:1; + /** delay_limit_vt2_pd_site0_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site0_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site0_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site0_unit1:8; + /** timing_err_vt2_pd_site0_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site0_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit1_vt2_conf1_reg_t; + +/** Type of comb_pd_site0_unit2_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site0_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site0_unit2:1; + /** timing_err_cnt_clr_vt2_pd_site0_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site0_unit2:1; + /** delay_limit_vt2_pd_site0_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site0_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site0_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site0_unit2:8; + /** timing_err_vt2_pd_site0_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site0_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit2_vt2_conf1_reg_t; + +/** Type of comb_pd_site0_unit3_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site0_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site0_unit3:1; + /** timing_err_cnt_clr_vt2_pd_site0_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site0_unit3:1; + /** delay_limit_vt2_pd_site0_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site0_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site0_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site0_unit3:8; + /** timing_err_vt2_pd_site0_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site0_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site0_unit3_vt2_conf1_reg_t; + +/** Type of comb_pd_site1_unit0_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site1_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site1_unit0:1; + /** timing_err_cnt_clr_vt0_pd_site1_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site1_unit0:1; + /** delay_limit_vt0_pd_site1_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site1_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site1_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site1_unit0:8; + /** timing_err_vt0_pd_site1_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site1_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit0_vt0_conf1_reg_t; + +/** Type of comb_pd_site1_unit1_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site1_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site1_unit1:1; + /** timing_err_cnt_clr_vt0_pd_site1_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site1_unit1:1; + /** delay_limit_vt0_pd_site1_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site1_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site1_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site1_unit1:8; + /** timing_err_vt0_pd_site1_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site1_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit1_vt0_conf1_reg_t; + +/** Type of comb_pd_site1_unit2_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site1_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site1_unit2:1; + /** timing_err_cnt_clr_vt0_pd_site1_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site1_unit2:1; + /** delay_limit_vt0_pd_site1_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site1_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site1_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site1_unit2:8; + /** timing_err_vt0_pd_site1_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site1_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit2_vt0_conf1_reg_t; + +/** Type of comb_pd_site1_unit3_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site1_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site1_unit3:1; + /** timing_err_cnt_clr_vt0_pd_site1_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site1_unit3:1; + /** delay_limit_vt0_pd_site1_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site1_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site1_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site1_unit3:8; + /** timing_err_vt0_pd_site1_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site1_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit3_vt0_conf1_reg_t; + +/** Type of comb_pd_site1_unit0_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site1_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site1_unit0:1; + /** timing_err_cnt_clr_vt1_pd_site1_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site1_unit0:1; + /** delay_limit_vt1_pd_site1_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site1_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site1_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site1_unit0:8; + /** timing_err_vt1_pd_site1_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site1_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit0_vt1_conf1_reg_t; + +/** Type of comb_pd_site1_unit1_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site1_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site1_unit1:1; + /** timing_err_cnt_clr_vt1_pd_site1_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site1_unit1:1; + /** delay_limit_vt1_pd_site1_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site1_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site1_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site1_unit1:8; + /** timing_err_vt1_pd_site1_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site1_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit1_vt1_conf1_reg_t; + +/** Type of comb_pd_site1_unit2_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site1_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site1_unit2:1; + /** timing_err_cnt_clr_vt1_pd_site1_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site1_unit2:1; + /** delay_limit_vt1_pd_site1_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site1_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site1_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site1_unit2:8; + /** timing_err_vt1_pd_site1_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site1_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit2_vt1_conf1_reg_t; + +/** Type of comb_pd_site1_unit3_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site1_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site1_unit3:1; + /** timing_err_cnt_clr_vt1_pd_site1_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site1_unit3:1; + /** delay_limit_vt1_pd_site1_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site1_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site1_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site1_unit3:8; + /** timing_err_vt1_pd_site1_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site1_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit3_vt1_conf1_reg_t; + +/** Type of comb_pd_site1_unit0_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site1_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site1_unit0:1; + /** timing_err_cnt_clr_vt2_pd_site1_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site1_unit0:1; + /** delay_limit_vt2_pd_site1_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site1_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site1_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site1_unit0:8; + /** timing_err_vt2_pd_site1_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site1_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit0_vt2_conf1_reg_t; + +/** Type of comb_pd_site1_unit1_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site1_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site1_unit1:1; + /** timing_err_cnt_clr_vt2_pd_site1_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site1_unit1:1; + /** delay_limit_vt2_pd_site1_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site1_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site1_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site1_unit1:8; + /** timing_err_vt2_pd_site1_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site1_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit1_vt2_conf1_reg_t; + +/** Type of comb_pd_site1_unit2_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site1_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site1_unit2:1; + /** timing_err_cnt_clr_vt2_pd_site1_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site1_unit2:1; + /** delay_limit_vt2_pd_site1_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site1_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site1_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site1_unit2:8; + /** timing_err_vt2_pd_site1_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site1_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit2_vt2_conf1_reg_t; + +/** Type of comb_pd_site1_unit3_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site1_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site1_unit3:1; + /** timing_err_cnt_clr_vt2_pd_site1_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site1_unit3:1; + /** delay_limit_vt2_pd_site1_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site1_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site1_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site1_unit3:8; + /** timing_err_vt2_pd_site1_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site1_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site1_unit3_vt2_conf1_reg_t; + +/** Type of comb_pd_site2_unit0_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site2_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site2_unit0:1; + /** timing_err_cnt_clr_vt0_pd_site2_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site2_unit0:1; + /** delay_limit_vt0_pd_site2_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site2_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site2_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site2_unit0:8; + /** timing_err_vt0_pd_site2_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site2_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit0_vt0_conf1_reg_t; + +/** Type of comb_pd_site2_unit1_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site2_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site2_unit1:1; + /** timing_err_cnt_clr_vt0_pd_site2_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site2_unit1:1; + /** delay_limit_vt0_pd_site2_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site2_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site2_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site2_unit1:8; + /** timing_err_vt0_pd_site2_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site2_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit1_vt0_conf1_reg_t; + +/** Type of comb_pd_site2_unit2_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site2_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site2_unit2:1; + /** timing_err_cnt_clr_vt0_pd_site2_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site2_unit2:1; + /** delay_limit_vt0_pd_site2_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site2_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site2_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site2_unit2:8; + /** timing_err_vt0_pd_site2_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site2_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit2_vt0_conf1_reg_t; + +/** Type of comb_pd_site2_unit3_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site2_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site2_unit3:1; + /** timing_err_cnt_clr_vt0_pd_site2_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site2_unit3:1; + /** delay_limit_vt0_pd_site2_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site2_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site2_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site2_unit3:8; + /** timing_err_vt0_pd_site2_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site2_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit3_vt0_conf1_reg_t; + +/** Type of comb_pd_site2_unit0_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site2_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site2_unit0:1; + /** timing_err_cnt_clr_vt1_pd_site2_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site2_unit0:1; + /** delay_limit_vt1_pd_site2_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site2_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site2_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site2_unit0:8; + /** timing_err_vt1_pd_site2_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site2_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit0_vt1_conf1_reg_t; + +/** Type of comb_pd_site2_unit1_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site2_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site2_unit1:1; + /** timing_err_cnt_clr_vt1_pd_site2_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site2_unit1:1; + /** delay_limit_vt1_pd_site2_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site2_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site2_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site2_unit1:8; + /** timing_err_vt1_pd_site2_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site2_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit1_vt1_conf1_reg_t; + +/** Type of comb_pd_site2_unit2_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site2_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site2_unit2:1; + /** timing_err_cnt_clr_vt1_pd_site2_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site2_unit2:1; + /** delay_limit_vt1_pd_site2_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site2_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site2_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site2_unit2:8; + /** timing_err_vt1_pd_site2_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site2_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit2_vt1_conf1_reg_t; + +/** Type of comb_pd_site2_unit3_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site2_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site2_unit3:1; + /** timing_err_cnt_clr_vt1_pd_site2_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site2_unit3:1; + /** delay_limit_vt1_pd_site2_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site2_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site2_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site2_unit3:8; + /** timing_err_vt1_pd_site2_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site2_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit3_vt1_conf1_reg_t; + +/** Type of comb_pd_site2_unit0_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site2_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site2_unit0:1; + /** timing_err_cnt_clr_vt2_pd_site2_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site2_unit0:1; + /** delay_limit_vt2_pd_site2_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site2_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site2_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site2_unit0:8; + /** timing_err_vt2_pd_site2_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site2_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit0_vt2_conf1_reg_t; + +/** Type of comb_pd_site2_unit1_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site2_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site2_unit1:1; + /** timing_err_cnt_clr_vt2_pd_site2_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site2_unit1:1; + /** delay_limit_vt2_pd_site2_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site2_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site2_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site2_unit1:8; + /** timing_err_vt2_pd_site2_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site2_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit1_vt2_conf1_reg_t; + +/** Type of comb_pd_site2_unit2_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site2_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site2_unit2:1; + /** timing_err_cnt_clr_vt2_pd_site2_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site2_unit2:1; + /** delay_limit_vt2_pd_site2_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site2_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site2_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site2_unit2:8; + /** timing_err_vt2_pd_site2_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site2_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit2_vt2_conf1_reg_t; + +/** Type of comb_pd_site2_unit3_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site2_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site2_unit3:1; + /** timing_err_cnt_clr_vt2_pd_site2_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site2_unit3:1; + /** delay_limit_vt2_pd_site2_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site2_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site2_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site2_unit3:8; + /** timing_err_vt2_pd_site2_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site2_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site2_unit3_vt2_conf1_reg_t; + +/** Type of comb_pd_site3_unit0_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site3_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site3_unit0:1; + /** timing_err_cnt_clr_vt0_pd_site3_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site3_unit0:1; + /** delay_limit_vt0_pd_site3_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site3_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site3_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site3_unit0:8; + /** timing_err_vt0_pd_site3_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site3_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit0_vt0_conf1_reg_t; + +/** Type of comb_pd_site3_unit1_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site3_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site3_unit1:1; + /** timing_err_cnt_clr_vt0_pd_site3_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site3_unit1:1; + /** delay_limit_vt0_pd_site3_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site3_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site3_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site3_unit1:8; + /** timing_err_vt0_pd_site3_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site3_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit1_vt0_conf1_reg_t; + +/** Type of comb_pd_site3_unit2_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site3_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site3_unit2:1; + /** timing_err_cnt_clr_vt0_pd_site3_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site3_unit2:1; + /** delay_limit_vt0_pd_site3_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site3_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site3_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site3_unit2:8; + /** timing_err_vt0_pd_site3_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site3_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit2_vt0_conf1_reg_t; + +/** Type of comb_pd_site3_unit3_vt0_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt0_pd_site3_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt0_pd_site3_unit3:1; + /** timing_err_cnt_clr_vt0_pd_site3_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt0_pd_site3_unit3:1; + /** delay_limit_vt0_pd_site3_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt0_pd_site3_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt0_pd_site3_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt0_pd_site3_unit3:8; + /** timing_err_vt0_pd_site3_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt0_pd_site3_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit3_vt0_conf1_reg_t; + +/** Type of comb_pd_site3_unit0_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site3_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site3_unit0:1; + /** timing_err_cnt_clr_vt1_pd_site3_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site3_unit0:1; + /** delay_limit_vt1_pd_site3_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site3_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site3_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site3_unit0:8; + /** timing_err_vt1_pd_site3_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site3_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit0_vt1_conf1_reg_t; + +/** Type of comb_pd_site3_unit1_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site3_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site3_unit1:1; + /** timing_err_cnt_clr_vt1_pd_site3_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site3_unit1:1; + /** delay_limit_vt1_pd_site3_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site3_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site3_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site3_unit1:8; + /** timing_err_vt1_pd_site3_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site3_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit1_vt1_conf1_reg_t; + +/** Type of comb_pd_site3_unit2_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site3_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site3_unit2:1; + /** timing_err_cnt_clr_vt1_pd_site3_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site3_unit2:1; + /** delay_limit_vt1_pd_site3_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site3_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site3_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site3_unit2:8; + /** timing_err_vt1_pd_site3_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site3_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit2_vt1_conf1_reg_t; + +/** Type of comb_pd_site3_unit3_vt1_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt1_pd_site3_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt1_pd_site3_unit3:1; + /** timing_err_cnt_clr_vt1_pd_site3_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt1_pd_site3_unit3:1; + /** delay_limit_vt1_pd_site3_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt1_pd_site3_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt1_pd_site3_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt1_pd_site3_unit3:8; + /** timing_err_vt1_pd_site3_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt1_pd_site3_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit3_vt1_conf1_reg_t; + +/** Type of comb_pd_site3_unit0_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site3_unit0 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site3_unit0:1; + /** timing_err_cnt_clr_vt2_pd_site3_unit0 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site3_unit0:1; + /** delay_limit_vt2_pd_site3_unit0 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site3_unit0:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site3_unit0 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site3_unit0:8; + /** timing_err_vt2_pd_site3_unit0 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site3_unit0:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit0_vt2_conf1_reg_t; + +/** Type of comb_pd_site3_unit1_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site3_unit1 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site3_unit1:1; + /** timing_err_cnt_clr_vt2_pd_site3_unit1 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site3_unit1:1; + /** delay_limit_vt2_pd_site3_unit1 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site3_unit1:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site3_unit1 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site3_unit1:8; + /** timing_err_vt2_pd_site3_unit1 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site3_unit1:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit1_vt2_conf1_reg_t; + +/** Type of comb_pd_site3_unit2_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site3_unit2 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site3_unit2:1; + /** timing_err_cnt_clr_vt2_pd_site3_unit2 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site3_unit2:1; + /** delay_limit_vt2_pd_site3_unit2 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site3_unit2:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site3_unit2 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site3_unit2:8; + /** timing_err_vt2_pd_site3_unit2 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site3_unit2:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit2_vt2_conf1_reg_t; + +/** Type of comb_pd_site3_unit3_vt2_conf1 register + * needs desc + */ +typedef union { + struct { + /** monitor_en_vt2_pd_site3_unit3 : R/W; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t monitor_en_vt2_pd_site3_unit3:1; + /** timing_err_cnt_clr_vt2_pd_site3_unit3 : WT; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_clr_vt2_pd_site3_unit3:1; + /** delay_limit_vt2_pd_site3_unit3 : R/W; bitpos: [9:2]; default: 20; + * needs field desc + */ + uint32_t delay_limit_vt2_pd_site3_unit3:8; + uint32_t reserved_10:13; + /** delay_num_o_vt2_pd_site3_unit3 : RO; bitpos: [30:23]; default: 0; + * needs field desc + */ + uint32_t delay_num_o_vt2_pd_site3_unit3:8; + /** timing_err_vt2_pd_site3_unit3 : RO; bitpos: [31]; default: 0; + * needs field desc + */ + uint32_t timing_err_vt2_pd_site3_unit3:1; + }; + uint32_t val; +} pvt_comb_pd_site3_unit3_vt2_conf1_reg_t; + +/** Type of comb_pd_site0_unit0_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site0_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site0_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site0_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site0_unit0:1; + /** timing_err_cnt_o_vt0_pd_site0_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site0_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit0_vt0_conf2_reg_t; + +/** Type of comb_pd_site0_unit1_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site0_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site0_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site0_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site0_unit1:1; + /** timing_err_cnt_o_vt0_pd_site0_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site0_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit1_vt0_conf2_reg_t; + +/** Type of comb_pd_site0_unit2_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site0_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site0_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site0_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site0_unit2:1; + /** timing_err_cnt_o_vt0_pd_site0_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site0_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit2_vt0_conf2_reg_t; + +/** Type of comb_pd_site0_unit3_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site0_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site0_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site0_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site0_unit3:1; + /** timing_err_cnt_o_vt0_pd_site0_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site0_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit3_vt0_conf2_reg_t; + +/** Type of comb_pd_site0_unit0_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site0_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site0_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site0_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site0_unit0:1; + /** timing_err_cnt_o_vt1_pd_site0_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site0_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit0_vt1_conf2_reg_t; + +/** Type of comb_pd_site0_unit1_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site0_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site0_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site0_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site0_unit1:1; + /** timing_err_cnt_o_vt1_pd_site0_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site0_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit1_vt1_conf2_reg_t; + +/** Type of comb_pd_site0_unit2_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site0_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site0_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site0_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site0_unit2:1; + /** timing_err_cnt_o_vt1_pd_site0_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site0_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit2_vt1_conf2_reg_t; + +/** Type of comb_pd_site0_unit3_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site0_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site0_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site0_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site0_unit3:1; + /** timing_err_cnt_o_vt1_pd_site0_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site0_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit3_vt1_conf2_reg_t; + +/** Type of comb_pd_site0_unit0_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site0_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site0_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site0_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site0_unit0:1; + /** timing_err_cnt_o_vt2_pd_site0_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site0_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit0_vt2_conf2_reg_t; + +/** Type of comb_pd_site0_unit1_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site0_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site0_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site0_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site0_unit1:1; + /** timing_err_cnt_o_vt2_pd_site0_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site0_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit1_vt2_conf2_reg_t; + +/** Type of comb_pd_site0_unit2_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site0_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site0_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site0_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site0_unit2:1; + /** timing_err_cnt_o_vt2_pd_site0_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site0_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit2_vt2_conf2_reg_t; + +/** Type of comb_pd_site0_unit3_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site0_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site0_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site0_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site0_unit3:1; + /** timing_err_cnt_o_vt2_pd_site0_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site0_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site0_unit3_vt2_conf2_reg_t; + +/** Type of comb_pd_site1_unit0_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site1_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site1_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site1_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site1_unit0:1; + /** timing_err_cnt_o_vt0_pd_site1_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site1_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit0_vt0_conf2_reg_t; + +/** Type of comb_pd_site1_unit1_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site1_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site1_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site1_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site1_unit1:1; + /** timing_err_cnt_o_vt0_pd_site1_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site1_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit1_vt0_conf2_reg_t; + +/** Type of comb_pd_site1_unit2_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site1_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site1_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site1_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site1_unit2:1; + /** timing_err_cnt_o_vt0_pd_site1_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site1_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit2_vt0_conf2_reg_t; + +/** Type of comb_pd_site1_unit3_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site1_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site1_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site1_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site1_unit3:1; + /** timing_err_cnt_o_vt0_pd_site1_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site1_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit3_vt0_conf2_reg_t; + +/** Type of comb_pd_site1_unit0_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site1_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site1_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site1_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site1_unit0:1; + /** timing_err_cnt_o_vt1_pd_site1_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site1_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit0_vt1_conf2_reg_t; + +/** Type of comb_pd_site1_unit1_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site1_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site1_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site1_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site1_unit1:1; + /** timing_err_cnt_o_vt1_pd_site1_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site1_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit1_vt1_conf2_reg_t; + +/** Type of comb_pd_site1_unit2_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site1_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site1_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site1_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site1_unit2:1; + /** timing_err_cnt_o_vt1_pd_site1_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site1_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit2_vt1_conf2_reg_t; + +/** Type of comb_pd_site1_unit3_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site1_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site1_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site1_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site1_unit3:1; + /** timing_err_cnt_o_vt1_pd_site1_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site1_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit3_vt1_conf2_reg_t; + +/** Type of comb_pd_site1_unit0_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site1_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site1_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site1_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site1_unit0:1; + /** timing_err_cnt_o_vt2_pd_site1_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site1_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit0_vt2_conf2_reg_t; + +/** Type of comb_pd_site1_unit1_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site1_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site1_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site1_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site1_unit1:1; + /** timing_err_cnt_o_vt2_pd_site1_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site1_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit1_vt2_conf2_reg_t; + +/** Type of comb_pd_site1_unit2_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site1_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site1_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site1_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site1_unit2:1; + /** timing_err_cnt_o_vt2_pd_site1_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site1_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit2_vt2_conf2_reg_t; + +/** Type of comb_pd_site1_unit3_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site1_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site1_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site1_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site1_unit3:1; + /** timing_err_cnt_o_vt2_pd_site1_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site1_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site1_unit3_vt2_conf2_reg_t; + +/** Type of comb_pd_site2_unit0_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site2_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site2_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site2_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site2_unit0:1; + /** timing_err_cnt_o_vt0_pd_site2_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site2_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit0_vt0_conf2_reg_t; + +/** Type of comb_pd_site2_unit1_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site2_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site2_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site2_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site2_unit1:1; + /** timing_err_cnt_o_vt0_pd_site2_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site2_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit1_vt0_conf2_reg_t; + +/** Type of comb_pd_site2_unit2_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site2_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site2_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site2_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site2_unit2:1; + /** timing_err_cnt_o_vt0_pd_site2_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site2_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit2_vt0_conf2_reg_t; + +/** Type of comb_pd_site2_unit3_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site2_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site2_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site2_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site2_unit3:1; + /** timing_err_cnt_o_vt0_pd_site2_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site2_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit3_vt0_conf2_reg_t; + +/** Type of comb_pd_site2_unit0_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site2_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site2_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site2_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site2_unit0:1; + /** timing_err_cnt_o_vt1_pd_site2_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site2_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit0_vt1_conf2_reg_t; + +/** Type of comb_pd_site2_unit1_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site2_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site2_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site2_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site2_unit1:1; + /** timing_err_cnt_o_vt1_pd_site2_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site2_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit1_vt1_conf2_reg_t; + +/** Type of comb_pd_site2_unit2_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site2_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site2_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site2_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site2_unit2:1; + /** timing_err_cnt_o_vt1_pd_site2_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site2_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit2_vt1_conf2_reg_t; + +/** Type of comb_pd_site2_unit3_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site2_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site2_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site2_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site2_unit3:1; + /** timing_err_cnt_o_vt1_pd_site2_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site2_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit3_vt1_conf2_reg_t; + +/** Type of comb_pd_site2_unit0_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site2_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site2_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site2_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site2_unit0:1; + /** timing_err_cnt_o_vt2_pd_site2_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site2_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit0_vt2_conf2_reg_t; + +/** Type of comb_pd_site2_unit1_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site2_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site2_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site2_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site2_unit1:1; + /** timing_err_cnt_o_vt2_pd_site2_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site2_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit1_vt2_conf2_reg_t; + +/** Type of comb_pd_site2_unit2_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site2_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site2_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site2_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site2_unit2:1; + /** timing_err_cnt_o_vt2_pd_site2_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site2_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit2_vt2_conf2_reg_t; + +/** Type of comb_pd_site2_unit3_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site2_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site2_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site2_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site2_unit3:1; + /** timing_err_cnt_o_vt2_pd_site2_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site2_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site2_unit3_vt2_conf2_reg_t; + +/** Type of comb_pd_site3_unit0_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site3_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site3_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site3_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site3_unit0:1; + /** timing_err_cnt_o_vt0_pd_site3_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site3_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit0_vt0_conf2_reg_t; + +/** Type of comb_pd_site3_unit1_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site3_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site3_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site3_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site3_unit1:1; + /** timing_err_cnt_o_vt0_pd_site3_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site3_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit1_vt0_conf2_reg_t; + +/** Type of comb_pd_site3_unit2_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site3_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site3_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site3_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site3_unit2:1; + /** timing_err_cnt_o_vt0_pd_site3_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site3_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit2_vt0_conf2_reg_t; + +/** Type of comb_pd_site3_unit3_vt0_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt0_pd_site3_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt0_pd_site3_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt0_pd_site3_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt0_pd_site3_unit3:1; + /** timing_err_cnt_o_vt0_pd_site3_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt0_pd_site3_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit3_vt0_conf2_reg_t; + +/** Type of comb_pd_site3_unit0_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site3_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site3_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site3_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site3_unit0:1; + /** timing_err_cnt_o_vt1_pd_site3_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site3_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit0_vt1_conf2_reg_t; + +/** Type of comb_pd_site3_unit1_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site3_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site3_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site3_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site3_unit1:1; + /** timing_err_cnt_o_vt1_pd_site3_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site3_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit1_vt1_conf2_reg_t; + +/** Type of comb_pd_site3_unit2_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site3_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site3_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site3_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site3_unit2:1; + /** timing_err_cnt_o_vt1_pd_site3_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site3_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit2_vt1_conf2_reg_t; + +/** Type of comb_pd_site3_unit3_vt1_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt1_pd_site3_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt1_pd_site3_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt1_pd_site3_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt1_pd_site3_unit3:1; + /** timing_err_cnt_o_vt1_pd_site3_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt1_pd_site3_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit3_vt1_conf2_reg_t; + +/** Type of comb_pd_site3_unit0_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site3_unit0 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site3_unit0:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site3_unit0 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site3_unit0:1; + /** timing_err_cnt_o_vt2_pd_site3_unit0 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site3_unit0:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit0_vt2_conf2_reg_t; + +/** Type of comb_pd_site3_unit1_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site3_unit1 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site3_unit1:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site3_unit1 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site3_unit1:1; + /** timing_err_cnt_o_vt2_pd_site3_unit1 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site3_unit1:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit1_vt2_conf2_reg_t; + +/** Type of comb_pd_site3_unit2_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site3_unit2 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site3_unit2:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site3_unit2 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site3_unit2:1; + /** timing_err_cnt_o_vt2_pd_site3_unit2 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site3_unit2:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit2_vt2_conf2_reg_t; + +/** Type of comb_pd_site3_unit3_vt2_conf2 register + * needs desc + */ +typedef union { + struct { + /** monitor_edg_mod_vt2_pd_site3_unit3 : R/W; bitpos: [1:0]; default: 0; + * needs field desc + */ + uint32_t monitor_edg_mod_vt2_pd_site3_unit3:2; + uint32_t reserved_2:13; + /** delay_ovf_vt2_pd_site3_unit3 : RO; bitpos: [15]; default: 0; + * needs field desc + */ + uint32_t delay_ovf_vt2_pd_site3_unit3:1; + /** timing_err_cnt_o_vt2_pd_site3_unit3 : RO; bitpos: [31:16]; default: 0; + * needs field desc + */ + uint32_t timing_err_cnt_o_vt2_pd_site3_unit3:16; + }; + uint32_t val; +} pvt_comb_pd_site3_unit3_vt2_conf2_reg_t; + +/** Type of value_update register + * needs field desc + */ +typedef union { + struct { + /** value_update : WT; bitpos: [0]; default: 0; + * needs field desc + */ + uint32_t value_update:1; + /** value_update_bypass : R/W; bitpos: [1]; default: 0; + * needs field desc + */ + uint32_t value_update_bypass:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} pvt_value_update_reg_t; + +/** Type of bypass_chain register + * needs field desc + */ +typedef union { + struct { + /** clk_chain_en : R/W; bitpos: [31:0]; default: 4294967295; + * needs field desc + */ + uint32_t clk_chain_en:32; + }; + uint32_t val; +} pvt_bypass_chain_reg_t; + + +/** Group: version register */ +/** Type of date register + * version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 34677040; + * version register + */ + uint32_t date:32; + }; + uint32_t val; +} pvt_date_reg_t; + + +typedef struct { + volatile pvt_pmup_bitmap_high0_reg_t pmup_bitmap_high0; + volatile pvt_pmup_bitmap_high1_reg_t pmup_bitmap_high1; + volatile pvt_pmup_bitmap_high2_reg_t pmup_bitmap_high2; + volatile pvt_pmup_bitmap_high3_reg_t pmup_bitmap_high3; + volatile pvt_pmup_bitmap_high4_reg_t pmup_bitmap_high4; + volatile pvt_pmup_bitmap_low0_reg_t pmup_bitmap_low0; + volatile pvt_pmup_bitmap_low1_reg_t pmup_bitmap_low1; + volatile pvt_pmup_bitmap_low2_reg_t pmup_bitmap_low2; + volatile pvt_pmup_bitmap_low3_reg_t pmup_bitmap_low3; + volatile pvt_pmup_bitmap_low4_reg_t pmup_bitmap_low4; + volatile pvt_pmup_drv_cfg_reg_t pmup_drv_cfg; + volatile pvt_pmup_channel_cfg_reg_t pmup_channel_cfg; + volatile pvt_clk_cfg_reg_t clk_cfg; + volatile pvt_dbias_channel_sel0_reg_t dbias_channel_sel0; + volatile pvt_dbias_channel_sel1_reg_t dbias_channel_sel1; + volatile pvt_dbias_channel0_sel_reg_t dbias_channel0_sel; + volatile pvt_dbias_channel1_sel_reg_t dbias_channel1_sel; + volatile pvt_dbias_channel2_sel_reg_t dbias_channel2_sel; + volatile pvt_dbias_channel3_sel_reg_t dbias_channel3_sel; + volatile pvt_dbias_channel4_sel_reg_t dbias_channel4_sel; + volatile pvt_dbias_cmd0_reg_t dbias_cmd0; + volatile pvt_dbias_cmd1_reg_t dbias_cmd1; + volatile pvt_dbias_cmd2_reg_t dbias_cmd2; + volatile pvt_dbias_cmd3_reg_t dbias_cmd3; + volatile pvt_dbias_cmd4_reg_t dbias_cmd4; + volatile pvt_dbias_timer_reg_t dbias_timer; + volatile pvt_comb_pd_site0_unit0_vt0_conf1_reg_t comb_pd_site0_unit0_vt0_conf1; + volatile pvt_comb_pd_site0_unit1_vt0_conf1_reg_t comb_pd_site0_unit1_vt0_conf1; + volatile pvt_comb_pd_site0_unit2_vt0_conf1_reg_t comb_pd_site0_unit2_vt0_conf1; + volatile pvt_comb_pd_site0_unit3_vt0_conf1_reg_t comb_pd_site0_unit3_vt0_conf1; + volatile pvt_comb_pd_site0_unit0_vt1_conf1_reg_t comb_pd_site0_unit0_vt1_conf1; + volatile pvt_comb_pd_site0_unit1_vt1_conf1_reg_t comb_pd_site0_unit1_vt1_conf1; + volatile pvt_comb_pd_site0_unit2_vt1_conf1_reg_t comb_pd_site0_unit2_vt1_conf1; + volatile pvt_comb_pd_site0_unit3_vt1_conf1_reg_t comb_pd_site0_unit3_vt1_conf1; + volatile pvt_comb_pd_site0_unit0_vt2_conf1_reg_t comb_pd_site0_unit0_vt2_conf1; + volatile pvt_comb_pd_site0_unit1_vt2_conf1_reg_t comb_pd_site0_unit1_vt2_conf1; + volatile pvt_comb_pd_site0_unit2_vt2_conf1_reg_t comb_pd_site0_unit2_vt2_conf1; + volatile pvt_comb_pd_site0_unit3_vt2_conf1_reg_t comb_pd_site0_unit3_vt2_conf1; + volatile pvt_comb_pd_site1_unit0_vt0_conf1_reg_t comb_pd_site1_unit0_vt0_conf1; + volatile pvt_comb_pd_site1_unit1_vt0_conf1_reg_t comb_pd_site1_unit1_vt0_conf1; + volatile pvt_comb_pd_site1_unit2_vt0_conf1_reg_t comb_pd_site1_unit2_vt0_conf1; + volatile pvt_comb_pd_site1_unit3_vt0_conf1_reg_t comb_pd_site1_unit3_vt0_conf1; + volatile pvt_comb_pd_site1_unit0_vt1_conf1_reg_t comb_pd_site1_unit0_vt1_conf1; + volatile pvt_comb_pd_site1_unit1_vt1_conf1_reg_t comb_pd_site1_unit1_vt1_conf1; + volatile pvt_comb_pd_site1_unit2_vt1_conf1_reg_t comb_pd_site1_unit2_vt1_conf1; + volatile pvt_comb_pd_site1_unit3_vt1_conf1_reg_t comb_pd_site1_unit3_vt1_conf1; + volatile pvt_comb_pd_site1_unit0_vt2_conf1_reg_t comb_pd_site1_unit0_vt2_conf1; + volatile pvt_comb_pd_site1_unit1_vt2_conf1_reg_t comb_pd_site1_unit1_vt2_conf1; + volatile pvt_comb_pd_site1_unit2_vt2_conf1_reg_t comb_pd_site1_unit2_vt2_conf1; + volatile pvt_comb_pd_site1_unit3_vt2_conf1_reg_t comb_pd_site1_unit3_vt2_conf1; + volatile pvt_comb_pd_site2_unit0_vt0_conf1_reg_t comb_pd_site2_unit0_vt0_conf1; + volatile pvt_comb_pd_site2_unit1_vt0_conf1_reg_t comb_pd_site2_unit1_vt0_conf1; + volatile pvt_comb_pd_site2_unit2_vt0_conf1_reg_t comb_pd_site2_unit2_vt0_conf1; + volatile pvt_comb_pd_site2_unit3_vt0_conf1_reg_t comb_pd_site2_unit3_vt0_conf1; + volatile pvt_comb_pd_site2_unit0_vt1_conf1_reg_t comb_pd_site2_unit0_vt1_conf1; + volatile pvt_comb_pd_site2_unit1_vt1_conf1_reg_t comb_pd_site2_unit1_vt1_conf1; + volatile pvt_comb_pd_site2_unit2_vt1_conf1_reg_t comb_pd_site2_unit2_vt1_conf1; + volatile pvt_comb_pd_site2_unit3_vt1_conf1_reg_t comb_pd_site2_unit3_vt1_conf1; + volatile pvt_comb_pd_site2_unit0_vt2_conf1_reg_t comb_pd_site2_unit0_vt2_conf1; + volatile pvt_comb_pd_site2_unit1_vt2_conf1_reg_t comb_pd_site2_unit1_vt2_conf1; + volatile pvt_comb_pd_site2_unit2_vt2_conf1_reg_t comb_pd_site2_unit2_vt2_conf1; + volatile pvt_comb_pd_site2_unit3_vt2_conf1_reg_t comb_pd_site2_unit3_vt2_conf1; + volatile pvt_comb_pd_site3_unit0_vt0_conf1_reg_t comb_pd_site3_unit0_vt0_conf1; + volatile pvt_comb_pd_site3_unit1_vt0_conf1_reg_t comb_pd_site3_unit1_vt0_conf1; + volatile pvt_comb_pd_site3_unit2_vt0_conf1_reg_t comb_pd_site3_unit2_vt0_conf1; + volatile pvt_comb_pd_site3_unit3_vt0_conf1_reg_t comb_pd_site3_unit3_vt0_conf1; + volatile pvt_comb_pd_site3_unit0_vt1_conf1_reg_t comb_pd_site3_unit0_vt1_conf1; + volatile pvt_comb_pd_site3_unit1_vt1_conf1_reg_t comb_pd_site3_unit1_vt1_conf1; + volatile pvt_comb_pd_site3_unit2_vt1_conf1_reg_t comb_pd_site3_unit2_vt1_conf1; + volatile pvt_comb_pd_site3_unit3_vt1_conf1_reg_t comb_pd_site3_unit3_vt1_conf1; + volatile pvt_comb_pd_site3_unit0_vt2_conf1_reg_t comb_pd_site3_unit0_vt2_conf1; + volatile pvt_comb_pd_site3_unit1_vt2_conf1_reg_t comb_pd_site3_unit1_vt2_conf1; + volatile pvt_comb_pd_site3_unit2_vt2_conf1_reg_t comb_pd_site3_unit2_vt2_conf1; + volatile pvt_comb_pd_site3_unit3_vt2_conf1_reg_t comb_pd_site3_unit3_vt2_conf1; + volatile pvt_comb_pd_site0_unit0_vt0_conf2_reg_t comb_pd_site0_unit0_vt0_conf2; + volatile pvt_comb_pd_site0_unit1_vt0_conf2_reg_t comb_pd_site0_unit1_vt0_conf2; + volatile pvt_comb_pd_site0_unit2_vt0_conf2_reg_t comb_pd_site0_unit2_vt0_conf2; + volatile pvt_comb_pd_site0_unit3_vt0_conf2_reg_t comb_pd_site0_unit3_vt0_conf2; + volatile pvt_comb_pd_site0_unit0_vt1_conf2_reg_t comb_pd_site0_unit0_vt1_conf2; + volatile pvt_comb_pd_site0_unit1_vt1_conf2_reg_t comb_pd_site0_unit1_vt1_conf2; + volatile pvt_comb_pd_site0_unit2_vt1_conf2_reg_t comb_pd_site0_unit2_vt1_conf2; + volatile pvt_comb_pd_site0_unit3_vt1_conf2_reg_t comb_pd_site0_unit3_vt1_conf2; + volatile pvt_comb_pd_site0_unit0_vt2_conf2_reg_t comb_pd_site0_unit0_vt2_conf2; + volatile pvt_comb_pd_site0_unit1_vt2_conf2_reg_t comb_pd_site0_unit1_vt2_conf2; + volatile pvt_comb_pd_site0_unit2_vt2_conf2_reg_t comb_pd_site0_unit2_vt2_conf2; + volatile pvt_comb_pd_site0_unit3_vt2_conf2_reg_t comb_pd_site0_unit3_vt2_conf2; + volatile pvt_comb_pd_site1_unit0_vt0_conf2_reg_t comb_pd_site1_unit0_vt0_conf2; + volatile pvt_comb_pd_site1_unit1_vt0_conf2_reg_t comb_pd_site1_unit1_vt0_conf2; + volatile pvt_comb_pd_site1_unit2_vt0_conf2_reg_t comb_pd_site1_unit2_vt0_conf2; + volatile pvt_comb_pd_site1_unit3_vt0_conf2_reg_t comb_pd_site1_unit3_vt0_conf2; + volatile pvt_comb_pd_site1_unit0_vt1_conf2_reg_t comb_pd_site1_unit0_vt1_conf2; + volatile pvt_comb_pd_site1_unit1_vt1_conf2_reg_t comb_pd_site1_unit1_vt1_conf2; + volatile pvt_comb_pd_site1_unit2_vt1_conf2_reg_t comb_pd_site1_unit2_vt1_conf2; + volatile pvt_comb_pd_site1_unit3_vt1_conf2_reg_t comb_pd_site1_unit3_vt1_conf2; + volatile pvt_comb_pd_site1_unit0_vt2_conf2_reg_t comb_pd_site1_unit0_vt2_conf2; + volatile pvt_comb_pd_site1_unit1_vt2_conf2_reg_t comb_pd_site1_unit1_vt2_conf2; + volatile pvt_comb_pd_site1_unit2_vt2_conf2_reg_t comb_pd_site1_unit2_vt2_conf2; + volatile pvt_comb_pd_site1_unit3_vt2_conf2_reg_t comb_pd_site1_unit3_vt2_conf2; + volatile pvt_comb_pd_site2_unit0_vt0_conf2_reg_t comb_pd_site2_unit0_vt0_conf2; + volatile pvt_comb_pd_site2_unit1_vt0_conf2_reg_t comb_pd_site2_unit1_vt0_conf2; + volatile pvt_comb_pd_site2_unit2_vt0_conf2_reg_t comb_pd_site2_unit2_vt0_conf2; + volatile pvt_comb_pd_site2_unit3_vt0_conf2_reg_t comb_pd_site2_unit3_vt0_conf2; + volatile pvt_comb_pd_site2_unit0_vt1_conf2_reg_t comb_pd_site2_unit0_vt1_conf2; + volatile pvt_comb_pd_site2_unit1_vt1_conf2_reg_t comb_pd_site2_unit1_vt1_conf2; + volatile pvt_comb_pd_site2_unit2_vt1_conf2_reg_t comb_pd_site2_unit2_vt1_conf2; + volatile pvt_comb_pd_site2_unit3_vt1_conf2_reg_t comb_pd_site2_unit3_vt1_conf2; + volatile pvt_comb_pd_site2_unit0_vt2_conf2_reg_t comb_pd_site2_unit0_vt2_conf2; + volatile pvt_comb_pd_site2_unit1_vt2_conf2_reg_t comb_pd_site2_unit1_vt2_conf2; + volatile pvt_comb_pd_site2_unit2_vt2_conf2_reg_t comb_pd_site2_unit2_vt2_conf2; + volatile pvt_comb_pd_site2_unit3_vt2_conf2_reg_t comb_pd_site2_unit3_vt2_conf2; + volatile pvt_comb_pd_site3_unit0_vt0_conf2_reg_t comb_pd_site3_unit0_vt0_conf2; + volatile pvt_comb_pd_site3_unit1_vt0_conf2_reg_t comb_pd_site3_unit1_vt0_conf2; + volatile pvt_comb_pd_site3_unit2_vt0_conf2_reg_t comb_pd_site3_unit2_vt0_conf2; + volatile pvt_comb_pd_site3_unit3_vt0_conf2_reg_t comb_pd_site3_unit3_vt0_conf2; + volatile pvt_comb_pd_site3_unit0_vt1_conf2_reg_t comb_pd_site3_unit0_vt1_conf2; + volatile pvt_comb_pd_site3_unit1_vt1_conf2_reg_t comb_pd_site3_unit1_vt1_conf2; + volatile pvt_comb_pd_site3_unit2_vt1_conf2_reg_t comb_pd_site3_unit2_vt1_conf2; + volatile pvt_comb_pd_site3_unit3_vt1_conf2_reg_t comb_pd_site3_unit3_vt1_conf2; + volatile pvt_comb_pd_site3_unit0_vt2_conf2_reg_t comb_pd_site3_unit0_vt2_conf2; + volatile pvt_comb_pd_site3_unit1_vt2_conf2_reg_t comb_pd_site3_unit1_vt2_conf2; + volatile pvt_comb_pd_site3_unit2_vt2_conf2_reg_t comb_pd_site3_unit2_vt2_conf2; + volatile pvt_comb_pd_site3_unit3_vt2_conf2_reg_t comb_pd_site3_unit3_vt2_conf2; + volatile pvt_value_update_reg_t value_update; + volatile pvt_bypass_chain_reg_t bypass_chain; + uint32_t reserved_1f0[899]; + volatile pvt_date_reg_t date; +} pvt_dev_t; + +extern pvt_dev_t PVT; + +#ifndef __cplusplus +_Static_assert(sizeof(pvt_dev_t) == 0x1000, "Invalid size of pvt_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/reg_base.h b/components/soc/esp32c61/include/soc/reg_base.h index 9ffd96ae8a..4747578d47 100644 --- a/components/soc/esp32c61/include/soc/reg_base.h +++ b/components/soc/esp32c61/include/soc/reg_base.h @@ -55,6 +55,6 @@ #define DR_REG_EFUSE_AND_OTP_DEBUG0_BASE 0x600B4800 #define DR_REG_EFUSE_AND_OTP_DEBUG1_BASE 0x600B4C00 #define DR_REG_TRACE_BASE 0x600C0000 -#define DR_REG_BUS_MONITOR_BASE 0x600C2000 +#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000 #define DR_REG_INTPRI_REG_BASE 0x600C5000 #define DR_REG_CACHE_CFG_BASE 0x600C8000 diff --git a/components/soc/esp32c61/include/soc/sha_reg.h b/components/soc/esp32c61/include/soc/sha_reg.h new file mode 100644 index 0000000000..d49c15e267 --- /dev/null +++ b/components/soc/esp32c61/include/soc/sha_reg.h @@ -0,0 +1,321 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SHA_MODE_REG register + * Configures SHA algorithm + */ +#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0) +/** SHA_MODE : R/W; bitpos: [2:0]; default: 0; + * Configures the SHA algorithm. \\ + * 0: SHA-1\\ + * 1: SHA-224\\ + * 2: SHA-256\\ + */ +#define SHA_MODE 0x00000007U +#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S) +#define SHA_MODE_V 0x00000007U +#define SHA_MODE_S 0 + +/** SHA_T_STRING_REG register + * SHA 512/t configuration register 0. + */ +#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4) +/** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0; + * Sha t_string (used if and only if mode == SHA_512/t). + */ +#define SHA_T_STRING 0xFFFFFFFFU +#define SHA_T_STRING_M (SHA_T_STRING_V << SHA_T_STRING_S) +#define SHA_T_STRING_V 0xFFFFFFFFU +#define SHA_T_STRING_S 0 + +/** SHA_T_LENGTH_REG register + * SHA 512/t configuration register 1. + */ +#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8) +/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0; + * Sha t_length (used if and only if mode == SHA_512/t). + */ +#define SHA_T_LENGTH 0x0000003FU +#define SHA_T_LENGTH_M (SHA_T_LENGTH_V << SHA_T_LENGTH_S) +#define SHA_T_LENGTH_V 0x0000003FU +#define SHA_T_LENGTH_S 0 + +/** SHA_DMA_BLOCK_NUM_REG register + * Block number register (only effective for DMA-SHA) + */ +#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc) +/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0; + * Configures the DMA-SHA block number. + */ +#define SHA_DMA_BLOCK_NUM 0x0000003FU +#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S) +#define SHA_DMA_BLOCK_NUM_V 0x0000003FU +#define SHA_DMA_BLOCK_NUM_S 0 + +/** SHA_START_REG register + * Starts the SHA accelerator for Typical SHA operation + */ +#define SHA_START_REG (DR_REG_SHA_BASE + 0x10) +/** SHA_START : RO; bitpos: [31:1]; default: 0; + * Write 1 to start Typical SHA calculation. + */ +#define SHA_START 0x7FFFFFFFU +#define SHA_START_M (SHA_START_V << SHA_START_S) +#define SHA_START_V 0x7FFFFFFFU +#define SHA_START_S 1 + +/** SHA_CONTINUE_REG register + * Continues SHA operation (only effective in Typical SHA mode) + */ +#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14) +/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0; + * Write 1 to continue Typical SHA calculation. + */ +#define SHA_CONTINUE 0x7FFFFFFFU +#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S) +#define SHA_CONTINUE_V 0x7FFFFFFFU +#define SHA_CONTINUE_S 1 + +/** SHA_BUSY_REG register + * Represents if SHA Accelerator is busy or not + */ +#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18) +/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0; + * Represents the states of SHA accelerator. \\ + * 0: idle\\ + * 1: busy\\ + */ +#define SHA_BUSY_STATE (BIT(0)) +#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S) +#define SHA_BUSY_STATE_V 0x00000001U +#define SHA_BUSY_STATE_S 0 + +/** SHA_DMA_START_REG register + * Starts the SHA accelerator for DMA-SHA operation + */ +#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c) +/** SHA_DMA_START : WO; bitpos: [0]; default: 0; + * Write 1 to start DMA-SHA calculation. + */ +#define SHA_DMA_START (BIT(0)) +#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S) +#define SHA_DMA_START_V 0x00000001U +#define SHA_DMA_START_S 0 + +/** SHA_DMA_CONTINUE_REG register + * Continues SHA operation (only effective in DMA-SHA mode) + */ +#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20) +/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0; + * Write 1 to continue DMA-SHA calculation. + */ +#define SHA_DMA_CONTINUE (BIT(0)) +#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S) +#define SHA_DMA_CONTINUE_V 0x00000001U +#define SHA_DMA_CONTINUE_S 0 + +/** SHA_CLEAR_IRQ_REG register + * DMA-SHA interrupt clear register + */ +#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24) +/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0; + * Write 1 to clear DMA-SHA interrupt. + */ +#define SHA_CLEAR_INTERRUPT (BIT(0)) +#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S) +#define SHA_CLEAR_INTERRUPT_V 0x00000001U +#define SHA_CLEAR_INTERRUPT_S 0 + +/** SHA_IRQ_ENA_REG register + * DMA-SHA interrupt enable register + */ +#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28) +/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable DMA-SHA interrupt. + */ +#define SHA_INTERRUPT_ENA (BIT(0)) +#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S) +#define SHA_INTERRUPT_ENA_V 0x00000001U +#define SHA_INTERRUPT_ENA_S 0 + +/** SHA_DATE_REG register + * Version control register + */ +#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c) +/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713; + * Version control register. + */ +#define SHA_DATE 0x3FFFFFFFU +#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S) +#define SHA_DATE_V 0x3FFFFFFFU +#define SHA_DATE_S 0 + +/** SHA_H_MEM register + * Sha H memory which contains intermediate hash or finial hash. + */ +#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40) +#define SHA_H_MEM_SIZE_BYTES 64 + +/** SHA_M_MEM register + * Sha M memory which contains message. + */ +#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80) +#define SHA_M_MEM_SIZE_BYTES 64 + +/** SHA_3_MODE_REG register + * Initial configuration register 0. + */ +#define SHA_3_MODE_REG (DR_REG_SHA_BASE + 0x800) +/** SHA_3_MODE : R/W; bitpos: [2:0]; default: 0; + * Sha3 mode + */ +#define SHA_3_MODE 0x00000007U +#define SHA_3_MODE_M (SHA_3_MODE_V << SHA_3_MODE_S) +#define SHA_3_MODE_V 0x00000007U +#define SHA_3_MODE_S 0 + +/** SHA_3_CLEAN_M_REG register + * Initial configuration register 1. + */ +#define SHA_3_CLEAN_M_REG (DR_REG_SHA_BASE + 0x804) +/** SHA_3_CLEAN_M : WO; bitpos: [0]; default: 0; + * Clean Message. + */ +#define SHA_3_CLEAN_M (BIT(0)) +#define SHA_3_CLEAN_M_M (SHA_3_CLEAN_M_V << SHA_3_CLEAN_M_S) +#define SHA_3_CLEAN_M_V 0x00000001U +#define SHA_3_CLEAN_M_S 0 + +/** SHA_3_DMA_BLOCK_NUM_REG register + * DMA configuration register 0. + */ +#define SHA_3_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0x80c) +/** SHA_3_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0; + * DMA-SHA3 block number. + */ +#define SHA_3_DMA_BLOCK_NUM 0x0000003FU +#define SHA_3_DMA_BLOCK_NUM_M (SHA_3_DMA_BLOCK_NUM_V << SHA_3_DMA_BLOCK_NUM_S) +#define SHA_3_DMA_BLOCK_NUM_V 0x0000003FU +#define SHA_3_DMA_BLOCK_NUM_S 0 + +/** SHA_3_START_REG register + * Typical SHA3 configuration register 0. + */ +#define SHA_3_START_REG (DR_REG_SHA_BASE + 0x810) +/** SHA_3_START : WO; bitpos: [0]; default: 0; + * Start typical sha3. + */ +#define SHA_3_START (BIT(0)) +#define SHA_3_START_M (SHA_3_START_V << SHA_3_START_S) +#define SHA_3_START_V 0x00000001U +#define SHA_3_START_S 0 + +/** SHA_3_CONTINUE_REG register + * Typical SHA3 configuration register 1. + */ +#define SHA_3_CONTINUE_REG (DR_REG_SHA_BASE + 0x814) +/** SHA_3_CONTINUE : WO; bitpos: [0]; default: 0; + * Continue typical sha3. + */ +#define SHA_3_CONTINUE (BIT(0)) +#define SHA_3_CONTINUE_M (SHA_3_CONTINUE_V << SHA_3_CONTINUE_S) +#define SHA_3_CONTINUE_V 0x00000001U +#define SHA_3_CONTINUE_S 0 + +/** SHA_3_BUSY_REG register + * Busy register. + */ +#define SHA_3_BUSY_REG (DR_REG_SHA_BASE + 0x818) +/** SHA_3_BUSY_REG : RO; bitpos: [0]; default: 0; + * Sha3 busy state. 1'b0: idle. 1'b1: busy. + */ +#define SHA_3_BUSY_REG (BIT(0)) +#define SHA_3_BUSY_REG_M (SHA_3_BUSY_REG_V << SHA_3_BUSY_REG_S) +#define SHA_3_BUSY_REG_V 0x00000001U +#define SHA_3_BUSY_REG_S 0 + +/** SHA_3_DMA_START_REG register + * DMA configuration register 1. + */ +#define SHA_3_DMA_START_REG (DR_REG_SHA_BASE + 0x81c) +/** SHA_3_DMA_START : WO; bitpos: [0]; default: 0; + * Start dma-sha3. + */ +#define SHA_3_DMA_START (BIT(0)) +#define SHA_3_DMA_START_M (SHA_3_DMA_START_V << SHA_3_DMA_START_S) +#define SHA_3_DMA_START_V 0x00000001U +#define SHA_3_DMA_START_S 0 + +/** SHA_3_DMA_CONTINUE_REG register + * DMA configuration register 2. + */ +#define SHA_3_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x820) +/** SHA_3_DMA_CONTINUE : WO; bitpos: [0]; default: 0; + * Continue dma-sha3. + */ +#define SHA_3_DMA_CONTINUE (BIT(0)) +#define SHA_3_DMA_CONTINUE_M (SHA_3_DMA_CONTINUE_V << SHA_3_DMA_CONTINUE_S) +#define SHA_3_DMA_CONTINUE_V 0x00000001U +#define SHA_3_DMA_CONTINUE_S 0 + +/** SHA_3_CLEAR_INT_REG register + * Interrupt clear register. + */ +#define SHA_3_CLEAR_INT_REG (DR_REG_SHA_BASE + 0x824) +/** SHA_3_CLEAR_INT : WO; bitpos: [0]; default: 0; + * Clear sha3 interrupt. + */ +#define SHA_3_CLEAR_INT (BIT(0)) +#define SHA_3_CLEAR_INT_M (SHA_3_CLEAR_INT_V << SHA_3_CLEAR_INT_S) +#define SHA_3_CLEAR_INT_V 0x00000001U +#define SHA_3_CLEAR_INT_S 0 + +/** SHA_3_INT_ENA_REG register + * Interrupt enable register. + */ +#define SHA_3_INT_ENA_REG (DR_REG_SHA_BASE + 0x828) +/** SHA_3_INT_ENA : R/W; bitpos: [0]; default: 0; + * Sha3 interrupt enable register. 1'b0: disable(default). 1'b1:enable + */ +#define SHA_3_INT_ENA (BIT(0)) +#define SHA_3_INT_ENA_M (SHA_3_INT_ENA_V << SHA_3_INT_ENA_S) +#define SHA_3_INT_ENA_V 0x00000001U +#define SHA_3_INT_ENA_S 0 + +/** SHA_3_SHAKE_LENGTH_REG register + * DMA configuration register 3. + */ +#define SHA_3_SHAKE_LENGTH_REG (DR_REG_SHA_BASE + 0x82c) +/** SHA_3_SHAKE_LENGTH : WO; bitpos: [10:0]; default: 50; + * SHAKE output hash word length + */ +#define SHA_3_SHAKE_LENGTH 0x000007FFU +#define SHA_3_SHAKE_LENGTH_M (SHA_3_SHAKE_LENGTH_V << SHA_3_SHAKE_LENGTH_S) +#define SHA_3_SHAKE_LENGTH_V 0x000007FFU +#define SHA_3_SHAKE_LENGTH_S 0 + +/** SHA_3_M_OUT_MEM register + * Sha3 hash reg which contains intermediate hash or finial hash. + */ +#define SHA_3_M_OUT_MEM (DR_REG_SHA_BASE + 0x900) +#define SHA_3_M_OUT_MEM_SIZE_BYTES 200 + +/** SHA_3_M_MEM register + * Sha3 message reg which contains message. + */ +#define SHA_3_M_MEM (DR_REG_SHA_BASE + 0xa00) +#define SHA_3_M_MEM_SIZE_BYTES 200 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/sha_struct.h b/components/soc/esp32c61/include/soc/sha_struct.h new file mode 100644 index 0000000000..4cc4ad7d4b --- /dev/null +++ b/components/soc/esp32c61/include/soc/sha_struct.h @@ -0,0 +1,398 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Control/Configuration Registers */ +/** Type of mode register + * Configures SHA algorithm + */ +typedef union { + struct { + /** mode : R/W; bitpos: [2:0]; default: 0; + * Configures the SHA algorithm. \\ + * 0: SHA-1\\ + * 1: SHA-224\\ + * 2: SHA-256\\ + */ + uint32_t mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} sha_mode_reg_t; + +/** Type of dma_block_num register + * Block number register (only effective for DMA-SHA) + */ +typedef union { + struct { + /** dma_block_num : R/W; bitpos: [5:0]; default: 0; + * Configures the DMA-SHA block number. + */ + uint32_t dma_block_num:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} sha_dma_block_num_reg_t; + +/** Type of start register + * Starts the SHA accelerator for Typical SHA operation + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** start : RO; bitpos: [31:1]; default: 0; + * Write 1 to start Typical SHA calculation. + */ + uint32_t start:31; + }; + uint32_t val; +} sha_start_reg_t; + +/** Type of continue register + * Continues SHA operation (only effective in Typical SHA mode) + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** continue : RO; bitpos: [31:1]; default: 0; + * Write 1 to continue Typical SHA calculation. + */ + uint32_t continue:31; + }; + uint32_t val; +} sha_continue_reg_t; + +/** Type of dma_start register + * Starts the SHA accelerator for DMA-SHA operation + */ +typedef union { + struct { + /** dma_start : WO; bitpos: [0]; default: 0; + * Write 1 to start DMA-SHA calculation. + */ + uint32_t dma_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_dma_start_reg_t; + +/** Type of dma_continue register + * Continues SHA operation (only effective in DMA-SHA mode) + */ +typedef union { + struct { + /** dma_continue : WO; bitpos: [0]; default: 0; + * Write 1 to continue DMA-SHA calculation. + */ + uint32_t dma_continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_dma_continue_reg_t; + + +/** Group: Configuration Register */ +/** Type of t_string register + * SHA 512/t configuration register 0. + */ +typedef union { + struct { + /** t_string : R/W; bitpos: [31:0]; default: 0; + * Sha t_string (used if and only if mode == SHA_512/t). + */ + uint32_t t_string:32; + }; + uint32_t val; +} sha_t_string_reg_t; + +/** Type of t_length register + * SHA 512/t configuration register 1. + */ +typedef union { + struct { + /** t_length : R/W; bitpos: [5:0]; default: 0; + * Sha t_length (used if and only if mode == SHA_512/t). + */ + uint32_t t_length:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} sha_t_length_reg_t; + +/** Type of 3_mode register + * Initial configuration register 0. + */ +typedef union { + struct { + /** 3_mode : R/W; bitpos: [2:0]; default: 0; + * Sha3 mode + */ + uint32_t 3_mode:3; + uint32_t reserved_3:29; + }; + uint32_t val; +} sha_3_mode_reg_t; + +/** Type of 3_clean_m register + * Initial configuration register 1. + */ +typedef union { + struct { + /** 3_clean_m : WO; bitpos: [0]; default: 0; + * Clean Message. + */ + uint32_t 3_clean_m:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_3_clean_m_reg_t; + +/** Type of 3_dma_block_num register + * DMA configuration register 0. + */ +typedef union { + struct { + /** 3_dma_block_num : R/W; bitpos: [5:0]; default: 0; + * DMA-SHA3 block number. + */ + uint32_t 3_dma_block_num:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} sha_3_dma_block_num_reg_t; + +/** Type of 3_start register + * Typical SHA3 configuration register 0. + */ +typedef union { + struct { + /** 3_start : WO; bitpos: [0]; default: 0; + * Start typical sha3. + */ + uint32_t 3_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_3_start_reg_t; + +/** Type of 3_continue register + * Typical SHA3 configuration register 1. + */ +typedef union { + struct { + /** 3_continue : WO; bitpos: [0]; default: 0; + * Continue typical sha3. + */ + uint32_t 3_continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_3_continue_reg_t; + +/** Type of 3_dma_start register + * DMA configuration register 1. + */ +typedef union { + struct { + /** 3_dma_start : WO; bitpos: [0]; default: 0; + * Start dma-sha3. + */ + uint32_t 3_dma_start:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_3_dma_start_reg_t; + +/** Type of 3_dma_continue register + * DMA configuration register 2. + */ +typedef union { + struct { + /** 3_dma_continue : WO; bitpos: [0]; default: 0; + * Continue dma-sha3. + */ + uint32_t 3_dma_continue:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_3_dma_continue_reg_t; + +/** Type of 3_shake_length register + * DMA configuration register 3. + */ +typedef union { + struct { + /** 3_shake_length : WO; bitpos: [10:0]; default: 50; + * SHAKE output hash word length + */ + uint32_t 3_shake_length:11; + uint32_t reserved_11:21; + }; + uint32_t val; +} sha_3_shake_length_reg_t; + + +/** Group: Status Registers */ +/** Type of busy register + * Represents if SHA Accelerator is busy or not + */ +typedef union { + struct { + /** busy_state : RO; bitpos: [0]; default: 0; + * Represents the states of SHA accelerator. \\ + * 0: idle\\ + * 1: busy\\ + */ + uint32_t busy_state:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_busy_reg_t; + + +/** Group: Interrupt Registers */ +/** Type of clear_irq register + * DMA-SHA interrupt clear register + */ +typedef union { + struct { + /** clear_interrupt : WO; bitpos: [0]; default: 0; + * Write 1 to clear DMA-SHA interrupt. + */ + uint32_t clear_interrupt:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_clear_irq_reg_t; + +/** Type of irq_ena register + * DMA-SHA interrupt enable register + */ +typedef union { + struct { + /** interrupt_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable DMA-SHA interrupt. + */ + uint32_t interrupt_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_irq_ena_reg_t; + + +/** Group: Version Register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [29:0]; default: 538972713; + * Version control register. + */ + uint32_t date:30; + uint32_t reserved_30:2; + }; + uint32_t val; +} sha_date_reg_t; + + +/** Group: memory type */ + +/** Group: Status Register */ +/** Type of 3_busy register + * Busy register. + */ +typedef union { + struct { + /** 3_busy_reg : RO; bitpos: [0]; default: 0; + * Sha3 busy state. 1'b0: idle. 1'b1: busy. + */ + uint32_t 3_busy_reg:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_3_busy_reg_t; + + +/** Group: Interrupt Register */ +/** Type of 3_clear_int register + * Interrupt clear register. + */ +typedef union { + struct { + /** 3_clear_int : WO; bitpos: [0]; default: 0; + * Clear sha3 interrupt. + */ + uint32_t 3_clear_int:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_3_clear_int_reg_t; + +/** Type of 3_int_ena register + * Interrupt enable register. + */ +typedef union { + struct { + /** 3_int_ena : R/W; bitpos: [0]; default: 0; + * Sha3 interrupt enable register. 1'b0: disable(default). 1'b1:enable + */ + uint32_t 3_int_ena:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sha_3_int_ena_reg_t; + + +typedef struct { + volatile sha_mode_reg_t mode; + volatile sha_t_string_reg_t t_string; + volatile sha_t_length_reg_t t_length; + volatile sha_dma_block_num_reg_t dma_block_num; + volatile sha_start_reg_t start; + volatile sha_continue_reg_t continue; + volatile sha_busy_reg_t busy; + volatile sha_dma_start_reg_t dma_start; + volatile sha_dma_continue_reg_t dma_continue; + volatile sha_clear_irq_reg_t clear_irq; + volatile sha_irq_ena_reg_t irq_ena; + volatile sha_date_reg_t date; + uint32_t reserved_030[4]; + volatile uint32_t h[16]; + volatile uint32_t m[16]; + uint32_t reserved_0c0[464]; + volatile sha_3_mode_reg_t 3_mode; + volatile sha_3_clean_m_reg_t 3_clean_m; + uint32_t reserved_808; + volatile sha_3_dma_block_num_reg_t 3_dma_block_num; + volatile sha_3_start_reg_t 3_start; + volatile sha_3_continue_reg_t 3_continue; + volatile sha_3_busy_reg_t 3_busy; + volatile sha_3_dma_start_reg_t 3_dma_start; + volatile sha_3_dma_continue_reg_t 3_dma_continue; + volatile sha_3_clear_int_reg_t 3_clear_int; + volatile sha_3_int_ena_reg_t 3_int_ena; + volatile sha_3_shake_length_reg_t 3_shake_length; + uint32_t reserved_830[52]; + volatile uint32_t 3_m_out[50]; + uint32_t reserved_9c8[14]; + volatile uint32_t 3_m[50]; +} sha_dev_t; + +extern sha_dev_t SHA; + +#ifndef __cplusplus +_Static_assert(sizeof(sha_dev_t) == 0xac8, "Invalid size of sha_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/tee_reg.h b/components/soc/esp32c61/include/soc/tee_reg.h new file mode 100644 index 0000000000..1de464f98d --- /dev/null +++ b/components/soc/esp32c61/include/soc/tee_reg.h @@ -0,0 +1,778 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TEE_M0_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0) +/** TEE_M0_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M0 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M0_MODE 0x00000003U +#define TEE_M0_MODE_M (TEE_M0_MODE_V << TEE_M0_MODE_S) +#define TEE_M0_MODE_V 0x00000003U +#define TEE_M0_MODE_S 0 +/** TEE_M0_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M0_LOCK (BIT(2)) +#define TEE_M0_LOCK_M (TEE_M0_LOCK_V << TEE_M0_LOCK_S) +#define TEE_M0_LOCK_V 0x00000001U +#define TEE_M0_LOCK_S 2 + +/** TEE_M1_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4) +/** TEE_M1_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M1 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M1_MODE 0x00000003U +#define TEE_M1_MODE_M (TEE_M1_MODE_V << TEE_M1_MODE_S) +#define TEE_M1_MODE_V 0x00000003U +#define TEE_M1_MODE_S 0 +/** TEE_M1_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M1_LOCK (BIT(2)) +#define TEE_M1_LOCK_M (TEE_M1_LOCK_V << TEE_M1_LOCK_S) +#define TEE_M1_LOCK_V 0x00000001U +#define TEE_M1_LOCK_S 2 + +/** TEE_M2_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8) +/** TEE_M2_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M2 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M2_MODE 0x00000003U +#define TEE_M2_MODE_M (TEE_M2_MODE_V << TEE_M2_MODE_S) +#define TEE_M2_MODE_V 0x00000003U +#define TEE_M2_MODE_S 0 +/** TEE_M2_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M2_LOCK (BIT(2)) +#define TEE_M2_LOCK_M (TEE_M2_LOCK_V << TEE_M2_LOCK_S) +#define TEE_M2_LOCK_V 0x00000001U +#define TEE_M2_LOCK_S 2 + +/** TEE_M3_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc) +/** TEE_M3_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M3 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M3_MODE 0x00000003U +#define TEE_M3_MODE_M (TEE_M3_MODE_V << TEE_M3_MODE_S) +#define TEE_M3_MODE_V 0x00000003U +#define TEE_M3_MODE_S 0 +/** TEE_M3_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M3_LOCK (BIT(2)) +#define TEE_M3_LOCK_M (TEE_M3_LOCK_V << TEE_M3_LOCK_S) +#define TEE_M3_LOCK_V 0x00000001U +#define TEE_M3_LOCK_S 2 + +/** TEE_M4_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10) +/** TEE_M4_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M4 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M4_MODE 0x00000003U +#define TEE_M4_MODE_M (TEE_M4_MODE_V << TEE_M4_MODE_S) +#define TEE_M4_MODE_V 0x00000003U +#define TEE_M4_MODE_S 0 +/** TEE_M4_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M4_LOCK (BIT(2)) +#define TEE_M4_LOCK_M (TEE_M4_LOCK_V << TEE_M4_LOCK_S) +#define TEE_M4_LOCK_V 0x00000001U +#define TEE_M4_LOCK_S 2 + +/** TEE_M5_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14) +/** TEE_M5_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M5 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M5_MODE 0x00000003U +#define TEE_M5_MODE_M (TEE_M5_MODE_V << TEE_M5_MODE_S) +#define TEE_M5_MODE_V 0x00000003U +#define TEE_M5_MODE_S 0 +/** TEE_M5_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M5_LOCK (BIT(2)) +#define TEE_M5_LOCK_M (TEE_M5_LOCK_V << TEE_M5_LOCK_S) +#define TEE_M5_LOCK_V 0x00000001U +#define TEE_M5_LOCK_S 2 + +/** TEE_M6_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18) +/** TEE_M6_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M6 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M6_MODE 0x00000003U +#define TEE_M6_MODE_M (TEE_M6_MODE_V << TEE_M6_MODE_S) +#define TEE_M6_MODE_V 0x00000003U +#define TEE_M6_MODE_S 0 +/** TEE_M6_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M6_LOCK (BIT(2)) +#define TEE_M6_LOCK_M (TEE_M6_LOCK_V << TEE_M6_LOCK_S) +#define TEE_M6_LOCK_V 0x00000001U +#define TEE_M6_LOCK_S 2 + +/** TEE_M7_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c) +/** TEE_M7_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M7 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M7_MODE 0x00000003U +#define TEE_M7_MODE_M (TEE_M7_MODE_V << TEE_M7_MODE_S) +#define TEE_M7_MODE_V 0x00000003U +#define TEE_M7_MODE_S 0 +/** TEE_M7_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M7_LOCK (BIT(2)) +#define TEE_M7_LOCK_M (TEE_M7_LOCK_V << TEE_M7_LOCK_S) +#define TEE_M7_LOCK_V 0x00000001U +#define TEE_M7_LOCK_S 2 + +/** TEE_M8_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20) +/** TEE_M8_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M8 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M8_MODE 0x00000003U +#define TEE_M8_MODE_M (TEE_M8_MODE_V << TEE_M8_MODE_S) +#define TEE_M8_MODE_V 0x00000003U +#define TEE_M8_MODE_S 0 +/** TEE_M8_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M8_LOCK (BIT(2)) +#define TEE_M8_LOCK_M (TEE_M8_LOCK_V << TEE_M8_LOCK_S) +#define TEE_M8_LOCK_V 0x00000001U +#define TEE_M8_LOCK_S 2 + +/** TEE_M9_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24) +/** TEE_M9_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M9 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M9_MODE 0x00000003U +#define TEE_M9_MODE_M (TEE_M9_MODE_V << TEE_M9_MODE_S) +#define TEE_M9_MODE_V 0x00000003U +#define TEE_M9_MODE_S 0 +/** TEE_M9_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M9_LOCK (BIT(2)) +#define TEE_M9_LOCK_M (TEE_M9_LOCK_V << TEE_M9_LOCK_S) +#define TEE_M9_LOCK_V 0x00000001U +#define TEE_M9_LOCK_S 2 + +/** TEE_M10_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M10_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x28) +/** TEE_M10_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M10 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M10_MODE 0x00000003U +#define TEE_M10_MODE_M (TEE_M10_MODE_V << TEE_M10_MODE_S) +#define TEE_M10_MODE_V 0x00000003U +#define TEE_M10_MODE_S 0 +/** TEE_M10_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M10_LOCK (BIT(2)) +#define TEE_M10_LOCK_M (TEE_M10_LOCK_V << TEE_M10_LOCK_S) +#define TEE_M10_LOCK_V 0x00000001U +#define TEE_M10_LOCK_S 2 + +/** TEE_M11_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M11_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x2c) +/** TEE_M11_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M11 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M11_MODE 0x00000003U +#define TEE_M11_MODE_M (TEE_M11_MODE_V << TEE_M11_MODE_S) +#define TEE_M11_MODE_V 0x00000003U +#define TEE_M11_MODE_S 0 +/** TEE_M11_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M11_LOCK (BIT(2)) +#define TEE_M11_LOCK_M (TEE_M11_LOCK_V << TEE_M11_LOCK_S) +#define TEE_M11_LOCK_V 0x00000001U +#define TEE_M11_LOCK_S 2 + +/** TEE_M12_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M12_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x30) +/** TEE_M12_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M12 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M12_MODE 0x00000003U +#define TEE_M12_MODE_M (TEE_M12_MODE_V << TEE_M12_MODE_S) +#define TEE_M12_MODE_V 0x00000003U +#define TEE_M12_MODE_S 0 +/** TEE_M12_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M12_LOCK (BIT(2)) +#define TEE_M12_LOCK_M (TEE_M12_LOCK_V << TEE_M12_LOCK_S) +#define TEE_M12_LOCK_V 0x00000001U +#define TEE_M12_LOCK_S 2 + +/** TEE_M13_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M13_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x34) +/** TEE_M13_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M13 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M13_MODE 0x00000003U +#define TEE_M13_MODE_M (TEE_M13_MODE_V << TEE_M13_MODE_S) +#define TEE_M13_MODE_V 0x00000003U +#define TEE_M13_MODE_S 0 +/** TEE_M13_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M13_LOCK (BIT(2)) +#define TEE_M13_LOCK_M (TEE_M13_LOCK_V << TEE_M13_LOCK_S) +#define TEE_M13_LOCK_V 0x00000001U +#define TEE_M13_LOCK_S 2 + +/** TEE_M14_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M14_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x38) +/** TEE_M14_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M14 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M14_MODE 0x00000003U +#define TEE_M14_MODE_M (TEE_M14_MODE_V << TEE_M14_MODE_S) +#define TEE_M14_MODE_V 0x00000003U +#define TEE_M14_MODE_S 0 +/** TEE_M14_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M14_LOCK (BIT(2)) +#define TEE_M14_LOCK_M (TEE_M14_LOCK_V << TEE_M14_LOCK_S) +#define TEE_M14_LOCK_V 0x00000001U +#define TEE_M14_LOCK_S 2 + +/** TEE_M15_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M15_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x3c) +/** TEE_M15_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M15 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M15_MODE 0x00000003U +#define TEE_M15_MODE_M (TEE_M15_MODE_V << TEE_M15_MODE_S) +#define TEE_M15_MODE_V 0x00000003U +#define TEE_M15_MODE_S 0 +/** TEE_M15_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M15_LOCK (BIT(2)) +#define TEE_M15_LOCK_M (TEE_M15_LOCK_V << TEE_M15_LOCK_S) +#define TEE_M15_LOCK_V 0x00000001U +#define TEE_M15_LOCK_S 2 + +/** TEE_M16_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M16_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x40) +/** TEE_M16_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M16 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M16_MODE 0x00000003U +#define TEE_M16_MODE_M (TEE_M16_MODE_V << TEE_M16_MODE_S) +#define TEE_M16_MODE_V 0x00000003U +#define TEE_M16_MODE_S 0 +/** TEE_M16_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M16_LOCK (BIT(2)) +#define TEE_M16_LOCK_M (TEE_M16_LOCK_V << TEE_M16_LOCK_S) +#define TEE_M16_LOCK_V 0x00000001U +#define TEE_M16_LOCK_S 2 + +/** TEE_M17_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M17_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x44) +/** TEE_M17_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M17 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M17_MODE 0x00000003U +#define TEE_M17_MODE_M (TEE_M17_MODE_V << TEE_M17_MODE_S) +#define TEE_M17_MODE_V 0x00000003U +#define TEE_M17_MODE_S 0 +/** TEE_M17_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M17_LOCK (BIT(2)) +#define TEE_M17_LOCK_M (TEE_M17_LOCK_V << TEE_M17_LOCK_S) +#define TEE_M17_LOCK_V 0x00000001U +#define TEE_M17_LOCK_S 2 + +/** TEE_M18_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M18_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x48) +/** TEE_M18_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M18 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M18_MODE 0x00000003U +#define TEE_M18_MODE_M (TEE_M18_MODE_V << TEE_M18_MODE_S) +#define TEE_M18_MODE_V 0x00000003U +#define TEE_M18_MODE_S 0 +/** TEE_M18_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M18_LOCK (BIT(2)) +#define TEE_M18_LOCK_M (TEE_M18_LOCK_V << TEE_M18_LOCK_S) +#define TEE_M18_LOCK_V 0x00000001U +#define TEE_M18_LOCK_S 2 + +/** TEE_M19_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M19_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4c) +/** TEE_M19_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M19 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M19_MODE 0x00000003U +#define TEE_M19_MODE_M (TEE_M19_MODE_V << TEE_M19_MODE_S) +#define TEE_M19_MODE_V 0x00000003U +#define TEE_M19_MODE_S 0 +/** TEE_M19_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M19_LOCK (BIT(2)) +#define TEE_M19_LOCK_M (TEE_M19_LOCK_V << TEE_M19_LOCK_S) +#define TEE_M19_LOCK_V 0x00000001U +#define TEE_M19_LOCK_S 2 + +/** TEE_M20_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M20_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x50) +/** TEE_M20_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M20 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M20_MODE 0x00000003U +#define TEE_M20_MODE_M (TEE_M20_MODE_V << TEE_M20_MODE_S) +#define TEE_M20_MODE_V 0x00000003U +#define TEE_M20_MODE_S 0 +/** TEE_M20_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M20_LOCK (BIT(2)) +#define TEE_M20_LOCK_M (TEE_M20_LOCK_V << TEE_M20_LOCK_S) +#define TEE_M20_LOCK_V 0x00000001U +#define TEE_M20_LOCK_S 2 + +/** TEE_M21_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M21_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x54) +/** TEE_M21_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M21 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M21_MODE 0x00000003U +#define TEE_M21_MODE_M (TEE_M21_MODE_V << TEE_M21_MODE_S) +#define TEE_M21_MODE_V 0x00000003U +#define TEE_M21_MODE_S 0 +/** TEE_M21_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M21_LOCK (BIT(2)) +#define TEE_M21_LOCK_M (TEE_M21_LOCK_V << TEE_M21_LOCK_S) +#define TEE_M21_LOCK_V 0x00000001U +#define TEE_M21_LOCK_S 2 + +/** TEE_M22_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M22_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x58) +/** TEE_M22_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M22 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M22_MODE 0x00000003U +#define TEE_M22_MODE_M (TEE_M22_MODE_V << TEE_M22_MODE_S) +#define TEE_M22_MODE_V 0x00000003U +#define TEE_M22_MODE_S 0 +/** TEE_M22_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M22_LOCK (BIT(2)) +#define TEE_M22_LOCK_M (TEE_M22_LOCK_V << TEE_M22_LOCK_S) +#define TEE_M22_LOCK_V 0x00000001U +#define TEE_M22_LOCK_S 2 + +/** TEE_M23_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M23_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x5c) +/** TEE_M23_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M23 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M23_MODE 0x00000003U +#define TEE_M23_MODE_M (TEE_M23_MODE_V << TEE_M23_MODE_S) +#define TEE_M23_MODE_V 0x00000003U +#define TEE_M23_MODE_S 0 +/** TEE_M23_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M23_LOCK (BIT(2)) +#define TEE_M23_LOCK_M (TEE_M23_LOCK_V << TEE_M23_LOCK_S) +#define TEE_M23_LOCK_V 0x00000001U +#define TEE_M23_LOCK_S 2 + +/** TEE_M24_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M24_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x60) +/** TEE_M24_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M24 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M24_MODE 0x00000003U +#define TEE_M24_MODE_M (TEE_M24_MODE_V << TEE_M24_MODE_S) +#define TEE_M24_MODE_V 0x00000003U +#define TEE_M24_MODE_S 0 +/** TEE_M24_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M24_LOCK (BIT(2)) +#define TEE_M24_LOCK_M (TEE_M24_LOCK_V << TEE_M24_LOCK_S) +#define TEE_M24_LOCK_V 0x00000001U +#define TEE_M24_LOCK_S 2 + +/** TEE_M25_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M25_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x64) +/** TEE_M25_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M25 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M25_MODE 0x00000003U +#define TEE_M25_MODE_M (TEE_M25_MODE_V << TEE_M25_MODE_S) +#define TEE_M25_MODE_V 0x00000003U +#define TEE_M25_MODE_S 0 +/** TEE_M25_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M25_LOCK (BIT(2)) +#define TEE_M25_LOCK_M (TEE_M25_LOCK_V << TEE_M25_LOCK_S) +#define TEE_M25_LOCK_V 0x00000001U +#define TEE_M25_LOCK_S 2 + +/** TEE_M26_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M26_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x68) +/** TEE_M26_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M26 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M26_MODE 0x00000003U +#define TEE_M26_MODE_M (TEE_M26_MODE_V << TEE_M26_MODE_S) +#define TEE_M26_MODE_V 0x00000003U +#define TEE_M26_MODE_S 0 +/** TEE_M26_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M26_LOCK (BIT(2)) +#define TEE_M26_LOCK_M (TEE_M26_LOCK_V << TEE_M26_LOCK_S) +#define TEE_M26_LOCK_V 0x00000001U +#define TEE_M26_LOCK_S 2 + +/** TEE_M27_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M27_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x6c) +/** TEE_M27_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M27 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M27_MODE 0x00000003U +#define TEE_M27_MODE_M (TEE_M27_MODE_V << TEE_M27_MODE_S) +#define TEE_M27_MODE_V 0x00000003U +#define TEE_M27_MODE_S 0 +/** TEE_M27_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M27_LOCK (BIT(2)) +#define TEE_M27_LOCK_M (TEE_M27_LOCK_V << TEE_M27_LOCK_S) +#define TEE_M27_LOCK_V 0x00000001U +#define TEE_M27_LOCK_S 2 + +/** TEE_M28_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M28_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x70) +/** TEE_M28_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M28 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M28_MODE 0x00000003U +#define TEE_M28_MODE_M (TEE_M28_MODE_V << TEE_M28_MODE_S) +#define TEE_M28_MODE_V 0x00000003U +#define TEE_M28_MODE_S 0 +/** TEE_M28_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M28_LOCK (BIT(2)) +#define TEE_M28_LOCK_M (TEE_M28_LOCK_V << TEE_M28_LOCK_S) +#define TEE_M28_LOCK_V 0x00000001U +#define TEE_M28_LOCK_S 2 + +/** TEE_M29_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M29_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x74) +/** TEE_M29_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M29 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M29_MODE 0x00000003U +#define TEE_M29_MODE_M (TEE_M29_MODE_V << TEE_M29_MODE_S) +#define TEE_M29_MODE_V 0x00000003U +#define TEE_M29_MODE_S 0 +/** TEE_M29_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M29_LOCK (BIT(2)) +#define TEE_M29_LOCK_M (TEE_M29_LOCK_V << TEE_M29_LOCK_S) +#define TEE_M29_LOCK_V 0x00000001U +#define TEE_M29_LOCK_S 2 + +/** TEE_M30_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M30_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x78) +/** TEE_M30_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M30 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M30_MODE 0x00000003U +#define TEE_M30_MODE_M (TEE_M30_MODE_V << TEE_M30_MODE_S) +#define TEE_M30_MODE_V 0x00000003U +#define TEE_M30_MODE_S 0 +/** TEE_M30_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M30_LOCK (BIT(2)) +#define TEE_M30_LOCK_M (TEE_M30_LOCK_V << TEE_M30_LOCK_S) +#define TEE_M30_LOCK_V 0x00000001U +#define TEE_M30_LOCK_S 2 + +/** TEE_M31_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M31_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x7c) +/** TEE_M31_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M31 security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ +#define TEE_M31_MODE 0x00000003U +#define TEE_M31_MODE_M (TEE_M31_MODE_V << TEE_M31_MODE_S) +#define TEE_M31_MODE_V 0x00000003U +#define TEE_M31_MODE_S 0 +/** TEE_M31_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M31_LOCK (BIT(2)) +#define TEE_M31_LOCK_M (TEE_M31_LOCK_V << TEE_M31_LOCK_S) +#define TEE_M31_LOCK_V 0x00000001U +#define TEE_M31_LOCK_S 2 + +/** TEE_CLOCK_GATE_REG register + * Clock gating register + */ +#define TEE_CLOCK_GATE_REG (DR_REG_TEE_BASE + 0x80) +/** TEE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on.\\ + * 0: enable automatic clock gating \\ + * 1: keep the clock always on \\ + */ +#define TEE_CLK_EN (BIT(0)) +#define TEE_CLK_EN_M (TEE_CLK_EN_V << TEE_CLK_EN_S) +#define TEE_CLK_EN_V 0x00000001U +#define TEE_CLK_EN_S 0 + +/** TEE_DATE_REG register + * Version control register + */ +#define TEE_DATE_REG (DR_REG_TEE_BASE + 0xffc) +/** TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35725664; + * Version control register + */ +#define TEE_DATE_REG 0x0FFFFFFFU +#define TEE_DATE_REG_M (TEE_DATE_REG_V << TEE_DATE_REG_S) +#define TEE_DATE_REG_V 0x0FFFFFFFU +#define TEE_DATE_REG_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/tee_struct.h b/components/soc/esp32c61/include/soc/tee_struct.h new file mode 100644 index 0000000000..d87e95696d --- /dev/null +++ b/components/soc/esp32c61/include/soc/tee_struct.h @@ -0,0 +1,86 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Tee mode control register */ +/** Type of mn_mode_ctrl register + * TEE mode control register + */ +typedef union { + struct { + /** mn_mode : R/W; bitpos: [1:0]; default: 0; + * Configures Mn security level mode.\\ + * 0: tee_mode \\ + * 1: ree_mode0 \\ + * 2: ree_mode1 \\ + * 3: ree_mode2 \\ + */ + uint32_t mn_mode:2; + /** mn_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ + uint32_t mn_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_mn_mode_ctrl_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * Clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on.\\ + * 0: enable automatic clock gating \\ + * 1: keep the clock always on \\ + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tee_clock_gate_reg_t; + + +/** Group: Version control register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date_reg : R/W; bitpos: [27:0]; default: 35725664; + * Version control register + */ + uint32_t date_reg:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} tee_date_reg_t; + + +typedef struct { + volatile tee_mn_mode_ctrl_reg_t mn_mode_ctrl[32]; + volatile tee_clock_gate_reg_t clock_gate; + uint32_t reserved_084[990]; + volatile tee_date_reg_t date; +} tee_dev_t; + +extern tee_dev_t TEE; + +#ifndef __cplusplus +_Static_assert(sizeof(tee_dev_t) == 0x1000, "Invalid size of tee_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/trace_reg.h b/components/soc/esp32c61/include/soc/trace_reg.h new file mode 100644 index 0000000000..1abfbbcd04 --- /dev/null +++ b/components/soc/esp32c61/include/soc/trace_reg.h @@ -0,0 +1,464 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TRACE_MEM_START_ADDR_REG register + * Memory start address + */ +#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0) +/** TRACE_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * Configures the start address of the trace memory + */ +#define TRACE_MEM_START_ADDR 0xFFFFFFFFU +#define TRACE_MEM_START_ADDR_M (TRACE_MEM_START_ADDR_V << TRACE_MEM_START_ADDR_S) +#define TRACE_MEM_START_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_START_ADDR_S 0 + +/** TRACE_MEM_END_ADDR_REG register + * Memory end address + */ +#define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4) +/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the end address of the trace memory. + */ +#define TRACE_MEM_END_ADDR 0xFFFFFFFFU +#define TRACE_MEM_END_ADDR_M (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S) +#define TRACE_MEM_END_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_END_ADDR_S 0 + +/** TRACE_MEM_CURRENT_ADDR_REG register + * Memory current addr + */ +#define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8) +/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents the current memory address for writing. + */ +#define TRACE_MEM_CURRENT_ADDR 0xFFFFFFFFU +#define TRACE_MEM_CURRENT_ADDR_M (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S) +#define TRACE_MEM_CURRENT_ADDR_V 0xFFFFFFFFU +#define TRACE_MEM_CURRENT_ADDR_S 0 + +/** TRACE_MEM_ADDR_UPDATE_REG register + * Memory address update + */ +#define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc) +/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0; + * Configures whether to update the value of + * \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} to + * \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.\\ + * 0: Not update\\ + * 1: Update\\ + */ +#define TRACE_MEM_CURRENT_ADDR_UPDATE (BIT(0)) +#define TRACE_MEM_CURRENT_ADDR_UPDATE_M (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S) +#define TRACE_MEM_CURRENT_ADDR_UPDATE_V 0x00000001U +#define TRACE_MEM_CURRENT_ADDR_UPDATE_S 0 + +/** TRACE_FIFO_STATUS_REG register + * FIFO status register + */ +#define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10) +/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1; + * Represent whether the FIFO is empty. \\1: Empty \\0: Not empty + */ +#define TRACE_FIFO_EMPTY (BIT(0)) +#define TRACE_FIFO_EMPTY_M (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S) +#define TRACE_FIFO_EMPTY_V 0x00000001U +#define TRACE_FIFO_EMPTY_S 0 +/** TRACE_WORK_STATUS : RO; bitpos: [2:1]; default: 0; + * Represent the state of the encoder: \\0: Idle state \\1: Working state\\ 2: Wait + * state becasue hart is halted or in reset \\3: Lost state\\ + */ +#define TRACE_WORK_STATUS 0x00000003U +#define TRACE_WORK_STATUS_M (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S) +#define TRACE_WORK_STATUS_V 0x00000003U +#define TRACE_WORK_STATUS_S 1 + +/** TRACE_INTR_ENA_REG register + * Interrupt enable register + */ +#define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14) +/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0; + * Write 1 to enable TRACE_FIFO_OVERFLOW_INTR + */ +#define TRACE_FIFO_OVERFLOW_INTR_ENA (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_ENA_M (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S) +#define TRACE_FIFO_OVERFLOW_INTR_ENA_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_ENA_S 0 +/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0; + * Write 1 to enable TRACE_MEM_FULL_INTR + */ +#define TRACE_MEM_FULL_INTR_ENA (BIT(1)) +#define TRACE_MEM_FULL_INTR_ENA_M (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S) +#define TRACE_MEM_FULL_INTR_ENA_V 0x00000001U +#define TRACE_MEM_FULL_INTR_ENA_S 1 + +/** TRACE_INTR_RAW_REG register + * Interrupt raw status register + */ +#define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18) +/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0; + * The raw interrupt status of TRACE_FIFO_OVERFLOW_INTR. + */ +#define TRACE_FIFO_OVERFLOW_INTR_RAW (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_RAW_M (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S) +#define TRACE_FIFO_OVERFLOW_INTR_RAW_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_RAW_S 0 +/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0; + * The raw interrupt status of TRACE_MEM_FULL_INTR + */ +#define TRACE_MEM_FULL_INTR_RAW (BIT(1)) +#define TRACE_MEM_FULL_INTR_RAW_M (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S) +#define TRACE_MEM_FULL_INTR_RAW_V 0x00000001U +#define TRACE_MEM_FULL_INTR_RAW_S 1 + +/** TRACE_INTR_CLR_REG register + * Interrupt clear register + */ +#define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c) +/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0; + * Write 1 to clear TRACE_FIFO_OVERFLOW_INTR + */ +#define TRACE_FIFO_OVERFLOW_INTR_CLR (BIT(0)) +#define TRACE_FIFO_OVERFLOW_INTR_CLR_M (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S) +#define TRACE_FIFO_OVERFLOW_INTR_CLR_V 0x00000001U +#define TRACE_FIFO_OVERFLOW_INTR_CLR_S 0 +/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0; + * Write 1 to clear TRACE_MEM_FULL_INTR + */ +#define TRACE_MEM_FULL_INTR_CLR (BIT(1)) +#define TRACE_MEM_FULL_INTR_CLR_M (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S) +#define TRACE_MEM_FULL_INTR_CLR_V 0x00000001U +#define TRACE_MEM_FULL_INTR_CLR_S 1 + +/** TRACE_TRIGGER_REG register + * Trace enable register + */ +#define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20) +/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0; + * Configure whether to enable the encoder.\\0: Invalid \\1: Enable\\ + */ +#define TRACE_TRIGGER_ON (BIT(0)) +#define TRACE_TRIGGER_ON_M (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S) +#define TRACE_TRIGGER_ON_V 0x00000001U +#define TRACE_TRIGGER_ON_S 0 +/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0; + * Configure whether to disable the encoder.\\0: Invalid \\1: Disable\\ + */ +#define TRACE_TRIGGER_OFF (BIT(1)) +#define TRACE_TRIGGER_OFF_M (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S) +#define TRACE_TRIGGER_OFF_V 0x00000001U +#define TRACE_TRIGGER_OFF_S 1 +/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1; + * Configure the memory writing mode. \\0: Non-loop mode. \\1: Loop mode\\ + */ +#define TRACE_MEM_LOOP (BIT(2)) +#define TRACE_MEM_LOOP_M (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S) +#define TRACE_MEM_LOOP_V 0x00000001U +#define TRACE_MEM_LOOP_S 2 +/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1; + * Configure whether or not enable automatic restart function for the encoder.\\0: + * Disable\\1: Enable\\ + */ +#define TRACE_RESTART_ENA (BIT(3)) +#define TRACE_RESTART_ENA_M (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S) +#define TRACE_RESTART_ENA_V 0x00000001U +#define TRACE_RESTART_ENA_S 3 + +/** TRACE_CONFIG_REG register + * trace configuration register + */ +#define TRACE_CONFIG_REG (DR_REG_TRACE_BASE + 0x24) +/** TRACE_DM_TRIGGER_ENA : R/W; bitpos: [0]; default: 0; + * Configure whether to enable the trigger signal.\\0: Disable\\1:enable\\ + */ +#define TRACE_DM_TRIGGER_ENA (BIT(0)) +#define TRACE_DM_TRIGGER_ENA_M (TRACE_DM_TRIGGER_ENA_V << TRACE_DM_TRIGGER_ENA_S) +#define TRACE_DM_TRIGGER_ENA_V 0x00000001U +#define TRACE_DM_TRIGGER_ENA_S 0 +/** TRACE_RESET_ENA : R/W; bitpos: [1]; default: 0; + * Configure whether to reset, when enabeld, if cpu have reset, the encoder will + * output a packet to report the address of the last instruction, and upon reset + * deassertion, the encoder start again.\\0: Disable\\0: Enable\\ + */ +#define TRACE_RESET_ENA (BIT(1)) +#define TRACE_RESET_ENA_M (TRACE_RESET_ENA_V << TRACE_RESET_ENA_S) +#define TRACE_RESET_ENA_V 0x00000001U +#define TRACE_RESET_ENA_S 1 +/** TRACE_HALT_ENA : R/W; bitpos: [2]; default: 0; + * Configure whether to enable the halt signal. \\1: Disable\\1: Enable\\ + */ +#define TRACE_HALT_ENA (BIT(2)) +#define TRACE_HALT_ENA_M (TRACE_HALT_ENA_V << TRACE_HALT_ENA_S) +#define TRACE_HALT_ENA_V 0x00000001U +#define TRACE_HALT_ENA_S 2 +/** TRACE_STALL_ENA : R/W; bitpos: [3]; default: 0; + * Configure whether to enable the stall signal. \\0: Disable.\\1: Enable\\ + */ +#define TRACE_STALL_ENA (BIT(3)) +#define TRACE_STALL_ENA_M (TRACE_STALL_ENA_V << TRACE_STALL_ENA_S) +#define TRACE_STALL_ENA_V 0x00000001U +#define TRACE_STALL_ENA_S 3 +/** TRACE_FULL_ADDRESS : R/W; bitpos: [4]; default: 0; + * Configure the address mode.\\0: Delta address mode.\\1: Full address mode.\\ + */ +#define TRACE_FULL_ADDRESS (BIT(4)) +#define TRACE_FULL_ADDRESS_M (TRACE_FULL_ADDRESS_V << TRACE_FULL_ADDRESS_S) +#define TRACE_FULL_ADDRESS_V 0x00000001U +#define TRACE_FULL_ADDRESS_S 4 +/** TRACE_IMPLICIT_EXCEPT : R/W; bitpos: [5]; default: 0; + * Configure whether or not enabel implicit exception mode. When enabled,, do not sent + * exception address, only exception cause in exception packets.\\1: enabled\\0: + * disabled\\ + */ +#define TRACE_IMPLICIT_EXCEPT (BIT(5)) +#define TRACE_IMPLICIT_EXCEPT_M (TRACE_IMPLICIT_EXCEPT_V << TRACE_IMPLICIT_EXCEPT_S) +#define TRACE_IMPLICIT_EXCEPT_V 0x00000001U +#define TRACE_IMPLICIT_EXCEPT_S 5 + +/** TRACE_FILTER_CONTROL_REG register + * filter control register + */ +#define TRACE_FILTER_CONTROL_REG (DR_REG_TRACE_BASE + 0x28) +/** TRACE_FILTER_EN : R/W; bitpos: [0]; default: 0; + * Configure whether to enable filtering. \\0: Disable, always match.\\ 1: Enable + */ +#define TRACE_FILTER_EN (BIT(0)) +#define TRACE_FILTER_EN_M (TRACE_FILTER_EN_V << TRACE_FILTER_EN_S) +#define TRACE_FILTER_EN_V 0x00000001U +#define TRACE_FILTER_EN_S 0 +/** TRACE_MATCH_COMP : R/W; bitpos: [1]; default: 0; + * Configure whether to enable the comparator match mode. \\0: Disable \\1: Enable, + * the comparator must be high in order for the filter to match + */ +#define TRACE_MATCH_COMP (BIT(1)) +#define TRACE_MATCH_COMP_M (TRACE_MATCH_COMP_V << TRACE_MATCH_COMP_S) +#define TRACE_MATCH_COMP_V 0x00000001U +#define TRACE_MATCH_COMP_S 1 +/** TRACE_MATCH_PRIVILEGE : R/W; bitpos: [2]; default: 0; + * Configure whether to enable the privilege match mode. \\0: Disable \\1: Enable, + * match privilege levels specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}. + */ +#define TRACE_MATCH_PRIVILEGE (BIT(2)) +#define TRACE_MATCH_PRIVILEGE_M (TRACE_MATCH_PRIVILEGE_V << TRACE_MATCH_PRIVILEGE_S) +#define TRACE_MATCH_PRIVILEGE_V 0x00000001U +#define TRACE_MATCH_PRIVILEGE_S 2 +/** TRACE_MATCH_ECAUSE : R/W; bitpos: [3]; default: 0; + * Configure whether to enable ecause match mode. \\0: Disable \\1: Enable, start + * matching from exception cause codes specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop + * matching upon return from the 1st matching exception. + */ +#define TRACE_MATCH_ECAUSE (BIT(3)) +#define TRACE_MATCH_ECAUSE_M (TRACE_MATCH_ECAUSE_V << TRACE_MATCH_ECAUSE_S) +#define TRACE_MATCH_ECAUSE_V 0x00000001U +#define TRACE_MATCH_ECAUSE_S 3 +/** TRACE_MATCH_INTERRUPT : R/W; bitpos: [4]; default: 0; + * Configure whether to enable the interrupt match mode. \\0: Disable \\1: Enable, + * start matching from a trap with the interrupt level codes specified by + * \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and + * stop matching upon return from the 1st matching trap. + */ +#define TRACE_MATCH_INTERRUPT (BIT(4)) +#define TRACE_MATCH_INTERRUPT_M (TRACE_MATCH_INTERRUPT_V << TRACE_MATCH_INTERRUPT_S) +#define TRACE_MATCH_INTERRUPT_V 0x00000001U +#define TRACE_MATCH_INTERRUPT_S 4 + +/** TRACE_FILTER_MATCH_CONTROL_REG register + * filter match control register + */ +#define TRACE_FILTER_MATCH_CONTROL_REG (DR_REG_TRACE_BASE + 0x2c) +/** TRACE_MATCH_CHOICE_PRIVILEGE : R/W; bitpos: [0]; default: 0; + * Configures the privilege level for matching. Valid only when + * \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\0: User + * mode. \\1: Machine mode + */ +#define TRACE_MATCH_CHOICE_PRIVILEGE (BIT(0)) +#define TRACE_MATCH_CHOICE_PRIVILEGE_M (TRACE_MATCH_CHOICE_PRIVILEGE_V << TRACE_MATCH_CHOICE_PRIVILEGE_S) +#define TRACE_MATCH_CHOICE_PRIVILEGE_V 0x00000001U +#define TRACE_MATCH_CHOICE_PRIVILEGE_S 0 +/** TRACE_MATCH_VALUE_INTERRUPT : R/W; bitpos: [1]; default: 0; + * Configures the interrupt level for match. Valid only when when + * \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\0: + * itype=2. \\0: itype=2. + */ +#define TRACE_MATCH_VALUE_INTERRUPT (BIT(1)) +#define TRACE_MATCH_VALUE_INTERRUPT_M (TRACE_MATCH_VALUE_INTERRUPT_V << TRACE_MATCH_VALUE_INTERRUPT_S) +#define TRACE_MATCH_VALUE_INTERRUPT_V 0x00000001U +#define TRACE_MATCH_VALUE_INTERRUPT_S 1 +/** TRACE_MATCH_CHOICE_ECAUSE : R/W; bitpos: [7:2]; default: 0; + * Configures the ecause code for matching. + */ +#define TRACE_MATCH_CHOICE_ECAUSE 0x0000003FU +#define TRACE_MATCH_CHOICE_ECAUSE_M (TRACE_MATCH_CHOICE_ECAUSE_V << TRACE_MATCH_CHOICE_ECAUSE_S) +#define TRACE_MATCH_CHOICE_ECAUSE_V 0x0000003FU +#define TRACE_MATCH_CHOICE_ECAUSE_S 2 + +/** TRACE_FILTER_COMPARATOR_CONTROL_REG register + * filter comparator match control register + */ +#define TRACE_FILTER_COMPARATOR_CONTROL_REG (DR_REG_TRACE_BASE + 0x30) +/** TRACE_P_INPUT : R/W; bitpos: [0]; default: 0; + * Configures the input of the primary comparator for matching: \\0: iaddr \\1: tval\\ + */ +#define TRACE_P_INPUT (BIT(0)) +#define TRACE_P_INPUT_M (TRACE_P_INPUT_V << TRACE_P_INPUT_S) +#define TRACE_P_INPUT_V 0x00000001U +#define TRACE_P_INPUT_S 0 +/** TRACE_P_FUNCTION : R/W; bitpos: [4:2]; default: 0; + * Configures the function for the primary comparator. \\0: Equal, \\1: Not equal, + * \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or + * equal, \\Other: Always match + */ +#define TRACE_P_FUNCTION 0x00000007U +#define TRACE_P_FUNCTION_M (TRACE_P_FUNCTION_V << TRACE_P_FUNCTION_S) +#define TRACE_P_FUNCTION_V 0x00000007U +#define TRACE_P_FUNCTION_S 2 +/** TRACE_P_NOTIFY : R/W; bitpos: [5]; default: 0; + * Configure whether to explicitly report an instruction address matched against the + * primary comparator. \\0:Not report \\1:Report + */ +#define TRACE_P_NOTIFY (BIT(5)) +#define TRACE_P_NOTIFY_M (TRACE_P_NOTIFY_V << TRACE_P_NOTIFY_S) +#define TRACE_P_NOTIFY_V 0x00000001U +#define TRACE_P_NOTIFY_S 5 +/** TRACE_S_INPUT : R/W; bitpos: [8]; default: 0; + * Configures the input of the secondary comparator for matching: \\0: iaddr \\1: + * tval\\ + */ +#define TRACE_S_INPUT (BIT(8)) +#define TRACE_S_INPUT_M (TRACE_S_INPUT_V << TRACE_S_INPUT_S) +#define TRACE_S_INPUT_V 0x00000001U +#define TRACE_S_INPUT_S 8 +/** TRACE_S_FUNCTION : R/W; bitpos: [12:10]; default: 0; + * Configures the function for the secondary comparator. \\0: Equal, \\1: Not equal, + * \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or + * equal, \\Other: Always match + */ +#define TRACE_S_FUNCTION 0x00000007U +#define TRACE_S_FUNCTION_M (TRACE_S_FUNCTION_V << TRACE_S_FUNCTION_S) +#define TRACE_S_FUNCTION_V 0x00000007U +#define TRACE_S_FUNCTION_S 10 +/** TRACE_S_NOTIFY : R/W; bitpos: [13]; default: 0; + * Generate a trace packet explicitly reporting the address that cause the secondary + * match + */ +#define TRACE_S_NOTIFY (BIT(13)) +#define TRACE_S_NOTIFY_M (TRACE_S_NOTIFY_V << TRACE_S_NOTIFY_S) +#define TRACE_S_NOTIFY_V 0x00000001U +#define TRACE_S_NOTIFY_S 13 +/** TRACE_MATCH_MODE : R/W; bitpos: [17:16]; default: 0; + * Configures the comparator match mode: \\0: Only the primary comparator matches \\1: + * Both primary and secondary comparator matches(P\&\&S) \\ 2:Neither primary or + * secondary comparator matches !(P\&\&S) \\3: Start filtering when the primary + * comparator matches and stop filtering when the secondary comparator matches\\ + */ +#define TRACE_MATCH_MODE 0x00000003U +#define TRACE_MATCH_MODE_M (TRACE_MATCH_MODE_V << TRACE_MATCH_MODE_S) +#define TRACE_MATCH_MODE_V 0x00000003U +#define TRACE_MATCH_MODE_S 16 + +/** TRACE_FILTER_P_COMPARATOR_MATCH_REG register + * primary comparator match value + */ +#define TRACE_FILTER_P_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x34) +/** TRACE_P_MATCH : R/W; bitpos: [31:0]; default: 0; + * Configures the match value for the primary comparator + */ +#define TRACE_P_MATCH 0xFFFFFFFFU +#define TRACE_P_MATCH_M (TRACE_P_MATCH_V << TRACE_P_MATCH_S) +#define TRACE_P_MATCH_V 0xFFFFFFFFU +#define TRACE_P_MATCH_S 0 + +/** TRACE_FILTER_S_COMPARATOR_MATCH_REG register + * secondary comparator match value + */ +#define TRACE_FILTER_S_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x38) +/** TRACE_S_MATCH : R/W; bitpos: [31:0]; default: 0; + * Configures the match value for the secondary comparator + */ +#define TRACE_S_MATCH 0xFFFFFFFFU +#define TRACE_S_MATCH_M (TRACE_S_MATCH_V << TRACE_S_MATCH_S) +#define TRACE_S_MATCH_V 0xFFFFFFFFU +#define TRACE_S_MATCH_S 0 + +/** TRACE_RESYNC_PROLONGED_REG register + * Resync configuration register + */ +#define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x3c) +/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128; + * Configures the threshold for synchronization counter + */ +#define TRACE_RESYNC_PROLONGED 0x00FFFFFFU +#define TRACE_RESYNC_PROLONGED_M (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S) +#define TRACE_RESYNC_PROLONGED_V 0x00FFFFFFU +#define TRACE_RESYNC_PROLONGED_S 0 +/** TRACE_RESYNC_MODE : R/W; bitpos: [25:24]; default: 0; + * Configures the synchronization mode: \\0: Disable the synchronization counter \\1: + * Invalid \\2: Synchronization counter counts by packet \\3: Synchronization counter + * counts by cycle\\ + */ +#define TRACE_RESYNC_MODE 0x00000003U +#define TRACE_RESYNC_MODE_M (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S) +#define TRACE_RESYNC_MODE_V 0x00000003U +#define TRACE_RESYNC_MODE_S 24 + +/** TRACE_AHB_CONFIG_REG register + * AHB config register + */ +#define TRACE_AHB_CONFIG_REG (DR_REG_TRACE_BASE + 0x40) +/** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0; + * Configures the AHB burst mode. \\0: SIGNLE \\1: INCR(length not defined) \\2:INCR4 + * \\4:INCR8 \\Others:Invalid + */ +#define TRACE_HBURST 0x00000007U +#define TRACE_HBURST_M (TRACE_HBURST_V << TRACE_HBURST_S) +#define TRACE_HBURST_V 0x00000007U +#define TRACE_HBURST_S 0 +/** TRACE_MAX_INCR : R/W; bitpos: [5:3]; default: 0; + * Configures the maximum burst length for INCR mode + */ +#define TRACE_MAX_INCR 0x00000007U +#define TRACE_MAX_INCR_M (TRACE_MAX_INCR_V << TRACE_MAX_INCR_S) +#define TRACE_MAX_INCR_V 0x00000007U +#define TRACE_MAX_INCR_S 3 + +/** TRACE_CLOCK_GATE_REG register + * Clock gate control register + */ +#define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x44) +/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures register clock gating. \\0: Support clock only when the application + * writes registers to save power. \\1:Always force the clock on for registers \\ This + * bit does't affect register access. + */ +#define TRACE_CLK_EN (BIT(0)) +#define TRACE_CLK_EN_M (TRACE_CLK_EN_V << TRACE_CLK_EN_S) +#define TRACE_CLK_EN_V 0x00000001U +#define TRACE_CLK_EN_S 0 + +/** TRACE_DATE_REG register + * Version control register + */ +#define TRACE_DATE_REG (DR_REG_TRACE_BASE + 0x3fc) +/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35721984; + * Version control register. + */ +#define TRACE_DATE 0x0FFFFFFFU +#define TRACE_DATE_M (TRACE_DATE_V << TRACE_DATE_S) +#define TRACE_DATE_V 0x0FFFFFFFU +#define TRACE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/trace_struct.h b/components/soc/esp32c61/include/soc/trace_struct.h new file mode 100644 index 0000000000..a8337ed0fd --- /dev/null +++ b/components/soc/esp32c61/include/soc/trace_struct.h @@ -0,0 +1,463 @@ +/** + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Memory configuration registers */ +/** Type of mem_start_addr register + * Memory start address + */ +typedef union { + struct { + /** mem_start_addr : R/W; bitpos: [31:0]; default: 0; + * Configures the start address of the trace memory + */ + uint32_t mem_start_addr:32; + }; + uint32_t val; +} trace_mem_start_addr_reg_t; + +/** Type of mem_end_addr register + * Memory end address + */ +typedef union { + struct { + /** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * Configures the end address of the trace memory. + */ + uint32_t mem_end_addr:32; + }; + uint32_t val; +} trace_mem_end_addr_reg_t; + +/** Type of mem_current_addr register + * Memory current addr + */ +typedef union { + struct { + /** mem_current_addr : RO; bitpos: [31:0]; default: 0; + * Represents the current memory address for writing. + */ + uint32_t mem_current_addr:32; + }; + uint32_t val; +} trace_mem_current_addr_reg_t; + +/** Type of mem_addr_update register + * Memory address update + */ +typedef union { + struct { + /** mem_current_addr_update : WT; bitpos: [0]; default: 0; + * Configures whether to update the value of + * \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} to + * \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.\\ + * 0: Not update\\ + * 1: Update\\ + */ + uint32_t mem_current_addr_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} trace_mem_addr_update_reg_t; + + +/** Group: Trace fifo status register */ +/** Type of fifo_status register + * FIFO status register + */ +typedef union { + struct { + /** fifo_empty : RO; bitpos: [0]; default: 1; + * Represent whether the FIFO is empty. \\1: Empty \\0: Not empty + */ + uint32_t fifo_empty:1; + /** work_status : RO; bitpos: [2:1]; default: 0; + * Represent the state of the encoder: \\0: Idle state \\1: Working state\\ 2: Wait + * state becasue hart is halted or in reset \\3: Lost state\\ + */ + uint32_t work_status:2; + uint32_t reserved_3:29; + }; + uint32_t val; +} trace_fifo_status_reg_t; + + +/** Group: Interrupt registers */ +/** Type of intr_ena register + * Interrupt enable register + */ +typedef union { + struct { + /** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0; + * Write 1 to enable TRACE_FIFO_OVERFLOW_INTR + */ + uint32_t fifo_overflow_intr_ena:1; + /** mem_full_intr_ena : R/W; bitpos: [1]; default: 0; + * Write 1 to enable TRACE_MEM_FULL_INTR + */ + uint32_t mem_full_intr_ena:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_ena_reg_t; + +/** Type of intr_raw register + * Interrupt raw status register + */ +typedef union { + struct { + /** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0; + * The raw interrupt status of TRACE_FIFO_OVERFLOW_INTR. + */ + uint32_t fifo_overflow_intr_raw:1; + /** mem_full_intr_raw : RO; bitpos: [1]; default: 0; + * The raw interrupt status of TRACE_MEM_FULL_INTR + */ + uint32_t mem_full_intr_raw:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_raw_reg_t; + +/** Type of intr_clr register + * Interrupt clear register + */ +typedef union { + struct { + /** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0; + * Write 1 to clear TRACE_FIFO_OVERFLOW_INTR + */ + uint32_t fifo_overflow_intr_clr:1; + /** mem_full_intr_clr : WT; bitpos: [1]; default: 0; + * Write 1 to clear TRACE_MEM_FULL_INTR + */ + uint32_t mem_full_intr_clr:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} trace_intr_clr_reg_t; + + +/** Group: Trace configuration register */ +/** Type of trigger register + * Trace enable register + */ +typedef union { + struct { + /** trigger_on : WT; bitpos: [0]; default: 0; + * Configure whether to enable the encoder.\\0: Invalid \\1: Enable\\ + */ + uint32_t trigger_on:1; + /** trigger_off : WT; bitpos: [1]; default: 0; + * Configure whether to disable the encoder.\\0: Invalid \\1: Disable\\ + */ + uint32_t trigger_off:1; + /** mem_loop : R/W; bitpos: [2]; default: 1; + * Configure the memory writing mode. \\0: Non-loop mode. \\1: Loop mode\\ + */ + uint32_t mem_loop:1; + /** restart_ena : R/W; bitpos: [3]; default: 1; + * Configure whether or not enable automatic restart function for the encoder.\\0: + * Disable\\1: Enable\\ + */ + uint32_t restart_ena:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} trace_trigger_reg_t; + +/** Type of config register + * trace configuration register + */ +typedef union { + struct { + /** dm_trigger_ena : R/W; bitpos: [0]; default: 0; + * Configure whether to enable the trigger signal.\\0: Disable\\1:enable\\ + */ + uint32_t dm_trigger_ena:1; + /** reset_ena : R/W; bitpos: [1]; default: 0; + * Configure whether to reset, when enabeld, if cpu have reset, the encoder will + * output a packet to report the address of the last instruction, and upon reset + * deassertion, the encoder start again.\\0: Disable\\0: Enable\\ + */ + uint32_t reset_ena:1; + /** halt_ena : R/W; bitpos: [2]; default: 0; + * Configure whether to enable the halt signal. \\1: Disable\\1: Enable\\ + */ + uint32_t halt_ena:1; + /** stall_ena : R/W; bitpos: [3]; default: 0; + * Configure whether to enable the stall signal. \\0: Disable.\\1: Enable\\ + */ + uint32_t stall_ena:1; + /** full_address : R/W; bitpos: [4]; default: 0; + * Configure the address mode.\\0: Delta address mode.\\1: Full address mode.\\ + */ + uint32_t full_address:1; + /** implicit_except : R/W; bitpos: [5]; default: 0; + * Configure whether or not enabel implicit exception mode. When enabled,, do not sent + * exception address, only exception cause in exception packets.\\1: enabled\\0: + * disabled\\ + */ + uint32_t implicit_except:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} trace_config_reg_t; + +/** Type of filter_control register + * filter control register + */ +typedef union { + struct { + /** filter_en : R/W; bitpos: [0]; default: 0; + * Configure whether to enable filtering. \\0: Disable, always match.\\ 1: Enable + */ + uint32_t filter_en:1; + /** match_comp : R/W; bitpos: [1]; default: 0; + * Configure whether to enable the comparator match mode. \\0: Disable \\1: Enable, + * the comparator must be high in order for the filter to match + */ + uint32_t match_comp:1; + /** match_privilege : R/W; bitpos: [2]; default: 0; + * Configure whether to enable the privilege match mode. \\0: Disable \\1: Enable, + * match privilege levels specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}. + */ + uint32_t match_privilege:1; + /** match_ecause : R/W; bitpos: [3]; default: 0; + * Configure whether to enable ecause match mode. \\0: Disable \\1: Enable, start + * matching from exception cause codes specified by + * \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop + * matching upon return from the 1st matching exception. + */ + uint32_t match_ecause:1; + /** match_interrupt : R/W; bitpos: [4]; default: 0; + * Configure whether to enable the interrupt match mode. \\0: Disable \\1: Enable, + * start matching from a trap with the interrupt level codes specified by + * \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and + * stop matching upon return from the 1st matching trap. + */ + uint32_t match_interrupt:1; + uint32_t reserved_5:27; + }; + uint32_t val; +} trace_filter_control_reg_t; + +/** Type of filter_match_control register + * filter match control register + */ +typedef union { + struct { + /** match_choice_privilege : R/W; bitpos: [0]; default: 0; + * Configures the privilege level for matching. Valid only when + * \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\0: User + * mode. \\1: Machine mode + */ + uint32_t match_choice_privilege:1; + /** match_value_interrupt : R/W; bitpos: [1]; default: 0; + * Configures the interrupt level for match. Valid only when when + * \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\0: + * itype=2. \\0: itype=2. + */ + uint32_t match_value_interrupt:1; + /** match_choice_ecause : R/W; bitpos: [7:2]; default: 0; + * Configures the ecause code for matching. + */ + uint32_t match_choice_ecause:6; + uint32_t reserved_8:24; + }; + uint32_t val; +} trace_filter_match_control_reg_t; + +/** Type of filter_comparator_control register + * filter comparator match control register + */ +typedef union { + struct { + /** p_input : R/W; bitpos: [0]; default: 0; + * Configures the input of the primary comparator for matching: \\0: iaddr \\1: tval\\ + */ + uint32_t p_input:1; + uint32_t reserved_1:1; + /** p_function : R/W; bitpos: [4:2]; default: 0; + * Configures the function for the primary comparator. \\0: Equal, \\1: Not equal, + * \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or + * equal, \\Other: Always match + */ + uint32_t p_function:3; + /** p_notify : R/W; bitpos: [5]; default: 0; + * Configure whether to explicitly report an instruction address matched against the + * primary comparator. \\0:Not report \\1:Report + */ + uint32_t p_notify:1; + uint32_t reserved_6:2; + /** s_input : R/W; bitpos: [8]; default: 0; + * Configures the input of the secondary comparator for matching: \\0: iaddr \\1: + * tval\\ + */ + uint32_t s_input:1; + uint32_t reserved_9:1; + /** s_function : R/W; bitpos: [12:10]; default: 0; + * Configures the function for the secondary comparator. \\0: Equal, \\1: Not equal, + * \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or + * equal, \\Other: Always match + */ + uint32_t s_function:3; + /** s_notify : R/W; bitpos: [13]; default: 0; + * Generate a trace packet explicitly reporting the address that cause the secondary + * match + */ + uint32_t s_notify:1; + uint32_t reserved_14:2; + /** match_mode : R/W; bitpos: [17:16]; default: 0; + * Configures the comparator match mode: \\0: Only the primary comparator matches \\1: + * Both primary and secondary comparator matches(P\&\&S) \\ 2:Neither primary or + * secondary comparator matches !(P\&\&S) \\3: Start filtering when the primary + * comparator matches and stop filtering when the secondary comparator matches\\ + */ + uint32_t match_mode:2; + uint32_t reserved_18:14; + }; + uint32_t val; +} trace_filter_comparator_control_reg_t; + +/** Type of filter_p_comparator_match register + * primary comparator match value + */ +typedef union { + struct { + /** p_match : R/W; bitpos: [31:0]; default: 0; + * Configures the match value for the primary comparator + */ + uint32_t p_match:32; + }; + uint32_t val; +} trace_filter_p_comparator_match_reg_t; + +/** Type of filter_s_comparator_match register + * secondary comparator match value + */ +typedef union { + struct { + /** s_match : R/W; bitpos: [31:0]; default: 0; + * Configures the match value for the secondary comparator + */ + uint32_t s_match:32; + }; + uint32_t val; +} trace_filter_s_comparator_match_reg_t; + +/** Type of resync_prolonged register + * Resync configuration register + */ +typedef union { + struct { + /** resync_prolonged : R/W; bitpos: [23:0]; default: 128; + * Configures the threshold for synchronization counter + */ + uint32_t resync_prolonged:24; + /** resync_mode : R/W; bitpos: [25:24]; default: 0; + * Configures the synchronization mode: \\0: Disable the synchronization counter \\1: + * Invalid \\2: Synchronization counter counts by packet \\3: Synchronization counter + * counts by cycle\\ + */ + uint32_t resync_mode:2; + uint32_t reserved_26:6; + }; + uint32_t val; +} trace_resync_prolonged_reg_t; + +/** Type of ahb_config register + * AHB config register + */ +typedef union { + struct { + /** hburst : R/W; bitpos: [2:0]; default: 0; + * Configures the AHB burst mode. \\0: SIGNLE \\1: INCR(length not defined) \\2:INCR4 + * \\4:INCR8 \\Others:Invalid + */ + uint32_t hburst:3; + /** max_incr : R/W; bitpos: [5:3]; default: 0; + * Configures the maximum burst length for INCR mode + */ + uint32_t max_incr:3; + uint32_t reserved_6:26; + }; + uint32_t val; +} trace_ahb_config_reg_t; + + +/** Group: Clock Gate Control and configuration register */ +/** Type of clock_gate register + * Clock gate control register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Configures register clock gating. \\0: Support clock only when the application + * writes registers to save power. \\1:Always force the clock on for registers \\ This + * bit does't affect register access. + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} trace_clock_gate_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 35721984; + * Version control register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} trace_date_reg_t; + + +typedef struct { + volatile trace_mem_start_addr_reg_t mem_start_addr; + volatile trace_mem_end_addr_reg_t mem_end_addr; + volatile trace_mem_current_addr_reg_t mem_current_addr; + volatile trace_mem_addr_update_reg_t mem_addr_update; + volatile trace_fifo_status_reg_t fifo_status; + volatile trace_intr_ena_reg_t intr_ena; + volatile trace_intr_raw_reg_t intr_raw; + volatile trace_intr_clr_reg_t intr_clr; + volatile trace_trigger_reg_t trigger; + volatile trace_config_reg_t config; + volatile trace_filter_control_reg_t filter_control; + volatile trace_filter_match_control_reg_t filter_match_control; + volatile trace_filter_comparator_control_reg_t filter_comparator_control; + volatile trace_filter_p_comparator_match_reg_t filter_p_comparator_match; + volatile trace_filter_s_comparator_match_reg_t filter_s_comparator_match; + volatile trace_resync_prolonged_reg_t resync_prolonged; + volatile trace_ahb_config_reg_t ahb_config; + volatile trace_clock_gate_reg_t clock_gate; + uint32_t reserved_048[237]; + volatile trace_date_reg_t date; +} trace_dev_t; + +extern trace_dev_t TRACE; + +#ifndef __cplusplus +_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/ld/esp32c61.peripherals.ld b/components/soc/esp32c61/ld/esp32c61.peripherals.ld index 27f74d56ac..cd66133d08 100644 --- a/components/soc/esp32c61/ld/esp32c61.peripherals.ld +++ b/components/soc/esp32c61/ld/esp32c61.peripherals.ld @@ -19,7 +19,7 @@ PROVIDE ( ADC = 0x6000E000 ); PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 ); PROVIDE ( INTMTX = 0x60010000 ); PROVIDE ( SOC_ETM = 0x60013000 ); -PROVIDE ( PVT_MONITOR = 0x60019000 ); +PROVIDE ( PVT = 0x60019000 ); PROVIDE ( PSRAM_MEM_MONITOR = 0x6001A000 ); PROVIDE ( GDMA = 0x60080000 ); PROVIDE ( GPSPI2 = 0x60081000 ); @@ -53,6 +53,6 @@ PROVIDE ( LP_GPIO = 0x600B4400 ); PROVIDE ( EFUSE_AND_OTP_DEBUG0= 0x600B4800 ); PROVIDE ( EFUSE_AND_OTP_DEBUG1= 0x600B4C00 ); PROVIDE ( TRACE = 0x600C0000 ); -PROVIDE ( BUS_MONITOR = 0x600C2000 ); -PROVIDE ( INTPRI_REG = 0x600C5000 ); +PROVIDE ( ASSIST_DEBUG = 0x600C2000 ); +PROVIDE ( INTPRI = 0x600C5000 ); PROVIDE ( CACHE_CFG = 0x600C8000 );