From cafcb219de7452d25a7ec3a59fb592a76f1b502e Mon Sep 17 00:00:00 2001 From: jiangguangming Date: Sun, 23 Apr 2023 14:04:27 +0800 Subject: [PATCH] hal: add rtc_cntl LL function for wake stub --- .../hal/esp32/include/hal/rtc_cntl_ll.h | 53 +++++++++++++--- .../hal/esp32c3/include/hal/rtc_cntl_ll.h | 39 +++++++++--- .../hal/esp32h2/include/hal/rtc_cntl_ll.h | 35 +++++++++-- .../hal/esp32s2/include/hal/rtc_cntl_ll.h | 39 +++++++++--- .../hal/esp32s3/include/hal/rtc_cntl_ll.h | 63 +++++++++++++------ 5 files changed, 183 insertions(+), 46 deletions(-) diff --git a/components/hal/esp32/include/hal/rtc_cntl_ll.h b/components/hal/esp32/include/hal/rtc_cntl_ll.h index 06d4201e30..8ec4b3dbeb 100644 --- a/components/hal/esp32/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32/include/hal/rtc_cntl_ll.h @@ -8,55 +8,92 @@ #include "soc/soc.h" #include "soc/rtc.h" +#include "esp_attr.h" +#include "esp_rom_sys.h" +#include "soc/rtc_cntl_reg.h" #ifdef __cplusplus extern "C" { #endif -static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t) { WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); } -static inline void rtc_cntl_ll_ext1_clear_wakeup_status(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_status(void) { REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR); } -static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_status(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_status(void) { return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS); } -static inline void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t mask, int mode) +FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t mask, int mode) { REG_SET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL, mask); SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, mode, RTC_CNTL_EXT_WAKEUP1_LV_S); } -static inline void rtc_cntl_ll_ext1_clear_wakeup_pins(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_pins(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL_M); } -static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void) { return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL); } -static inline void rtc_cntl_ll_ulp_wakeup_enable(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ulp_wakeup_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN); } -static inline void rtc_cntl_ll_ulp_int_clear(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ulp_int_clear(void) { REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_SAR_INT_CLR); } +FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN); +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE); + int attempts = 1000; + while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) { + esp_rom_delay_us(1); + if (attempts) { + if (--attempts == 0 && REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN)) { + esp_rom_printf("32KHz xtal has been stopped\n"); + } + } + } + SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_TIME_VALID_INT_CLR); + uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG); + t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32; + return t; +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us) +{ + uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG); + return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value); +} + +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void) +{ + return REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_CAUSE); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c3/include/hal/rtc_cntl_ll.h b/components/hal/esp32c3/include/hal/rtc_cntl_ll.h index 63a157a22e..61de2f2913 100644 --- a/components/hal/esp32c3/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32c3/include/hal/rtc_cntl_ll.h @@ -18,12 +18,13 @@ #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" #include "soc/syscon_reg.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { #endif -static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t) { WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); @@ -32,38 +33,62 @@ static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M); } -static inline uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void) { return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS); } -static inline void rtc_cntl_ll_gpio_clear_wakeup_status(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_gpio_clear_wakeup_status(void) { REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR); REG_CLR_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR); } -static inline void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t addr) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t addr) { REG_SET_FIELD(SYSCON_RETENTION_CTRL_REG, SYSCON_RETENTION_LINK_ADDR, (uint32_t)addr); } -static inline void rtc_cntl_ll_enable_cpu_retention_clock(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention_clock(void) { REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); } -static inline void rtc_cntl_ll_enable_cpu_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention(void) { /* Enable retention when cpu sleep enable */ REG_SET_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); } -static inline void rtc_cntl_ll_disable_cpu_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_disable_cpu_retention(void) { REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); } +FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN); +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE); + uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG); + t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32; + return t; +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us) +{ + uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG); + return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value); +} + +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void) +{ + return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h2/include/hal/rtc_cntl_ll.h b/components/hal/esp32h2/include/hal/rtc_cntl_ll.h index 8fc2299443..b63e243dfa 100644 --- a/components/hal/esp32h2/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32h2/include/hal/rtc_cntl_ll.h @@ -18,12 +18,13 @@ #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" #include "soc/syscon_reg.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { #endif -static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t) { WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); @@ -32,27 +33,51 @@ static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M); } -static inline uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void) { return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS); } -static inline void rtc_cntl_ll_gpio_clear_wakeup_status(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_gpio_clear_wakeup_status(void) { REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR); REG_CLR_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR); } -static inline void rtc_cntl_ll_enable_cpu_retention(uint32_t addr) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention(uint32_t addr) { // ESP32H2-TODO: IDF-3383 } -static inline void rtc_cntl_ll_disable_cpu_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_disable_cpu_retention(void) { // ESP32H2-TODO: IDF-3383 } +FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN); +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE); + uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG); + t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32; + return t; +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us) +{ + uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG); + return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value); +} + +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void) +{ + return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s2/include/hal/rtc_cntl_ll.h b/components/hal/esp32s2/include/hal/rtc_cntl_ll.h index 97be8fbeb1..067a085c5e 100644 --- a/components/hal/esp32s2/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32s2/include/hal/rtc_cntl_ll.h @@ -9,12 +9,13 @@ #include "soc/soc.h" #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { #endif -static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t) { WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); @@ -23,40 +24,64 @@ static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M); } -static inline void rtc_cntl_ll_ext1_clear_wakeup_status(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_status(void) { REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR); } -static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_status(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_status(void) { return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS); } -static inline void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t mask, int mode) +FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t mask, int mode) { REG_SET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL, mask); SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, mode, RTC_CNTL_EXT_WAKEUP1_LV_S); } -static inline void rtc_cntl_ll_ext1_clear_wakeup_pins(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_pins(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL_M); } -static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void) { return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL); } -static inline void rtc_cntl_ll_ulp_int_clear(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ulp_int_clear(void) { REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_ULP_CP_INT_CLR); REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_INT_CLR); REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_TRAP_INT_CLR); } +FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN); +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE); + uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG); + t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32; + return t; +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us) +{ + uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG); + return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value); +} + +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void) +{ + return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/rtc_cntl_ll.h b/components/hal/esp32s3/include/hal/rtc_cntl_ll.h index c9efd57b63..8745c900df 100644 --- a/components/hal/esp32s3/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32s3/include/hal/rtc_cntl_ll.h @@ -10,6 +10,7 @@ #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" #include "soc/apb_ctrl_reg.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { @@ -18,7 +19,7 @@ extern "C" { #define RTC_CNTL_LL_RETENTION_TARGET_CPU (BIT(0)) #define RTC_CNTL_LL_RETENTION_TARGET_TAGMEM (BIT(1)) -static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t) { WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); @@ -27,46 +28,46 @@ static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M); } -static inline void rtc_cntl_ll_ext1_clear_wakeup_status(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_status(void) { REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR); } -static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_status(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_status(void) { return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS); } -static inline void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t mask, int mode) +FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t mask, int mode) { REG_SET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL, mask); SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, mode, RTC_CNTL_EXT_WAKEUP1_LV_S); } -static inline void rtc_cntl_ll_ext1_clear_wakeup_pins(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_pins(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL_M); } -static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void) { return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL); } -static inline void rtc_cntl_ll_set_tagmem_retention_link_addr(uint32_t link_addr) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_tagmem_retention_link_addr(uint32_t link_addr) { REG_SET_FIELD(APB_CTRL_RETENTION_CTRL1_REG, APB_CTRL_RETENTION_TAG_LINK_ADDR, link_addr); } -static inline void rtc_cntl_ll_enable_tagmem_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_tagmem_retention(void) { /* Enable i/d-cache tagmem retenttion. cpu: 1, tagmem: 2, cpu + tagmem: 3 */ uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET); REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET, (target | RTC_CNTL_LL_RETENTION_TARGET_TAGMEM)); } -static inline void rtc_cntl_ll_enable_icache_tagmem_retention(uint32_t start_point, uint32_t vld_size, uint32_t size) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_icache_tagmem_retention(uint32_t start_point, uint32_t vld_size, uint32_t size) { REG_SET_FIELD(APB_CTRL_RETENTION_CTRL2_REG, APB_CTRL_RET_ICACHE_START_POINT, start_point); REG_SET_FIELD(APB_CTRL_RETENTION_CTRL2_REG, APB_CTRL_RET_ICACHE_VLD_SIZE, vld_size); @@ -74,7 +75,7 @@ static inline void rtc_cntl_ll_enable_icache_tagmem_retention(uint32_t start_poi REG_SET_BIT(APB_CTRL_RETENTION_CTRL2_REG, APB_CTRL_RET_ICACHE_ENABLE); } -static inline void rtc_cntl_ll_enable_dcache_tagmem_retention(uint32_t start_point, uint32_t vld_size, uint32_t size) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_dcache_tagmem_retention(uint32_t start_point, uint32_t vld_size, uint32_t size) { REG_SET_FIELD(APB_CTRL_RETENTION_CTRL3_REG, APB_CTRL_RET_DCACHE_START_POINT, start_point); REG_SET_FIELD(APB_CTRL_RETENTION_CTRL3_REG, APB_CTRL_RET_DCACHE_VLD_SIZE, vld_size); @@ -82,34 +83,34 @@ static inline void rtc_cntl_ll_enable_dcache_tagmem_retention(uint32_t start_poi REG_SET_BIT(APB_CTRL_RETENTION_CTRL3_REG, APB_CTRL_RET_DCACHE_ENABLE); } -static inline void rtc_cntl_ll_disable_tagmem_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_disable_tagmem_retention(void) { /* Enable i/d-cache tagmem retenttion. cpu: 1, tagmem: 2, cpu + tagmem: 3 */ uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET); REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET, (target & ~RTC_CNTL_LL_RETENTION_TARGET_TAGMEM)); } -static inline void rtc_cntl_ll_disable_icache_tagmem_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_disable_icache_tagmem_retention(void) { REG_CLR_BIT(APB_CTRL_RETENTION_CTRL2_REG, APB_CTRL_RET_ICACHE_ENABLE); } -static inline void rtc_cntl_ll_disable_dcache_tagmem_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_disable_dcache_tagmem_retention(void) { REG_CLR_BIT(APB_CTRL_RETENTION_CTRL3_REG, APB_CTRL_RET_DCACHE_ENABLE); } -static inline void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t link_addr) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t link_addr) { REG_SET_FIELD(APB_CTRL_RETENTION_CTRL_REG, APB_CTRL_RETENTION_CPU_LINK_ADDR, link_addr); } -static inline void rtc_cntl_ll_enable_cpu_retention_clock(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention_clock(void) { REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); /* Enable internal 20 MHz clock */ } -static inline void rtc_cntl_ll_enable_cpu_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention(void) { uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET); @@ -118,25 +119,49 @@ static inline void rtc_cntl_ll_enable_cpu_retention(void) REG_SET_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); } -static inline void rtc_cntl_ll_config_cpu_retention_timing(int wait, int clkoff_wait, int done_wait) +FORCE_INLINE_ATTR void rtc_cntl_ll_config_cpu_retention_timing(int wait, int clkoff_wait, int done_wait) { REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_WAIT, wait); REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_CLKOFF_WAIT, clkoff_wait); REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_DONE_WAIT, done_wait); } -static inline void rtc_cntl_ll_disable_cpu_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_disable_cpu_retention(void) { REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); } -static inline void rtc_cntl_ll_ulp_int_clear(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ulp_int_clear(void) { REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_ULP_CP_INT_CLR); REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_INT_CLR); REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_TRAP_INT_CLR); } +FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN); +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE); + uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG); + t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32; + return t; +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us) +{ + uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG); + return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value); +} + +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void) +{ + return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE); +} + #ifdef __cplusplus } #endif