espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-07-30 18:57:19 +02:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'bugfix/fix_touch_sensor_measure_start_wait_time_backport_v4.2' into 'release/v4.2'

Browse Source 
Bugfix(Touch): fix the touch sensor wait cycle after wakeup from sleep (backport v4.2)

See merge request espressif/esp-idf!13641
This commit is contained in:
Michael (XIAO Xufeng)
2021-10-18 16:58:30 +00:00
parent 4498749f38 0679862de2
commit cb58226c5e
3 changed files with 22 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
components/soc/soc/esp32s2/include/soc/rtc.h
View File

@ -107,6 +107,9 @@ extern "C" {
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172
#define RTC_CNTL_SCK_DCAP_DEFAULT 255
#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_IN_SLEEP (0xFF)
#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT (0x10)
/*
set sleep_init default param
*/

3
components/soc/src/esp32s2/rtc_init.c
View File

@ -62,6 +62,9 @@ void rtc_init(rtc_config_t cfg)
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_1V10);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, RTC_CNTL_DBIAS_1V10);
/* Recover default wait cycle for touch or COCPU after wakeup from deep sleep. */
REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT);
if (cfg.clkctl_init) {
//clear CMMU clock force on
CLEAR_PERI_REG_MASK(EXTMEM_PRO_CACHE_MMU_POWER_CTRL_REG, EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON);

39
components/soc/src/esp32s2/rtc_sleep.c
View File

@ -126,6 +126,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject);
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
/* Set wait cycle for touch or COCPU after deep sleep and light sleep. */
REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, RTC_CNTL_ULPCP_TOUCH_START_WAIT_IN_SLEEP);
}
void rtc_sleep_set_wakeup_time(uint64_t t)
@ -137,16 +140,11 @@ void rtc_sleep_set_wakeup_time(uint64_t t)
/* Read back 'reject' status when waking from light or deep sleep */
static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu);
static const unsigned DEEP_SLEEP_TOUCH_WAIT_CYCLE = 0xFF;
uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu)
{
REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_SLEEP_REJECT_ENA, reject_opt);
/* Set wait cycle for touch or COCPU after deep sleep. */
REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, DEEP_SLEEP_TOUCH_WAIT_CYCLE);
/* Start entry into sleep mode */
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
@ -204,23 +202,17 @@ uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt)
"s32i a2, %4, 0\n"
"memw\n"
/* Set wait cycle for touch or COCPU after deep sleep (can be moved to C code part?) */
"l32i a2, %5, 0\n"
"and a2, a2, %6\n"
"or a2, a2, %7\n"
"s32i a2, %5, 0\n"
/* Set register bit to go into deep sleep */
"l32i a2, %8, 0\n"
"or a2, a2, %9\n"
"s32i a2, %8, 0\n"
"l32i a2, %5, 0\n"
"or a2, a2, %6\n"
"s32i a2, %5, 0\n"
"memw\n"
/* Wait for sleep reject interrupt (never finishes if successful) */
".Lwaitsleep:"
"memw\n"
"l32i a2, %10, 0\n"
"and a2, a2, %11\n"
"l32i a2, %7, 0\n"
"and a2, a2, %8\n"
"beqz a2, .Lwaitsleep\n"
:
@ -231,13 +223,10 @@ uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt)
"r" (DPORT_RTC_MEM_CRC_START), // %2
"r" (DPORT_RTC_FASTMEM_CRC_REG), // %3
"r" (RTC_MEMORY_CRC_REG), // %4
"r" (RTC_CNTL_TIMER2_REG), // %5
"r" (~RTC_CNTL_ULPCP_TOUCH_START_WAIT_M), // %6
"r" (DEEP_SLEEP_TOUCH_WAIT_CYCLE << RTC_CNTL_ULPCP_TOUCH_START_WAIT_S), // %7
"r" (RTC_CNTL_STATE0_REG), // %8
"r" (RTC_CNTL_SLEEP_EN), // %9
"r" (RTC_CNTL_INT_RAW_REG), // %10
"r" (RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) // %11
"r" (RTC_CNTL_STATE0_REG), // %5
"r" (RTC_CNTL_SLEEP_EN), // %6
"r" (RTC_CNTL_INT_RAW_REG), // %7
"r" (RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) // %8
: "a2" // working register
);
@ -256,5 +245,9 @@ static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu)
rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(0);
rtc_sleep_pd(pd_cfg);
}
/* Recover default wait cycle for touch or COCPU after wakeup. */
REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT);
return reject;
}