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adc: fix esp32 continuous mode sampling freq issue

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This commit is contained in:
Armando
2022-07-20 16:15:39 +08:00
parent ad8862fa19
commit cb62457f6d
5 changed files with 28 additions and 10 deletions
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22
components/hal/adc_hal.c
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@ -14,6 +14,7 @@
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
//ADC utilises I2S0 DMA on ESP32 //ADC utilises I2S0 DMA on ESP32
#include "hal/i2s_hal.h"
#include "hal/i2s_ll.h" #include "hal/i2s_ll.h"
#include "hal/i2s_types.h" #include "hal/i2s_types.h"
#include "soc/i2s_struct.h" #include "soc/i2s_struct.h"
@ -232,14 +233,21 @@ static void adc_hal_digi_sample_freq_config(adc_hal_context_t *hal, uint32_t fre
adc_ll_digi_clk_sel(0); //use APB adc_ll_digi_clk_sel(0); //use APB
#else #else
i2s_ll_rx_clk_set_src(hal->dev, I2S_CLK_D2CLK); /*!< Clock from PLL_D2_CLK(160M)*/ i2s_ll_rx_clk_set_src(hal->dev, I2S_CLK_D2CLK); /*!< Clock from PLL_D2_CLK(160M)*/
uint32_t bck = I2S_BASE_CLK / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_B_DEFAULT / ADC_LL_CLKM_DIV_A_DEFAULT) / 2 / freq; uint32_t bclk_div = 16;
i2s_ll_mclk_div_t clk = { uint32_t bclk = freq * 2;
.mclk_div = ADC_LL_CLKM_DIV_NUM_DEFAULT, uint32_t mclk = bclk * bclk_div;
.a = ADC_LL_CLKM_DIV_A_DEFAULT, uint32_t mclk_div = I2S_BASE_CLK / mclk;
.b = ADC_LL_CLKM_DIV_B_DEFAULT, i2s_hal_clock_cfg_t i2s_hal_clk_cfg = {
.sclk = I2S_BASE_CLK,
.bclk = bclk,
.bclk_div = bclk_div,
.mclk = mclk ,
.mclk_div = mclk_div,
}; };
i2s_ll_rx_set_clk(hal->dev, &clk); i2s_ll_mclk_div_t mclk_set = {};
i2s_ll_rx_set_bck_div_num(hal->dev, bck); i2s_hal_mclk_div_decimal_cal(&i2s_hal_clk_cfg, &mclk_set);
i2s_ll_rx_set_clk(hal->dev, &mclk_set);
i2s_ll_rx_set_bck_div_num(hal->dev, i2s_hal_clk_cfg.bclk_div);
#endif #endif
} }

2
components/hal/i2s_hal.c
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@ -19,7 +19,7 @@
* @param clk_cfg I2S clock configuration(input) * @param clk_cfg I2S clock configuration(input)
* @param cal Point to `i2s_ll_mclk_div_t` structure(output). * @param cal Point to `i2s_ll_mclk_div_t` structure(output).
*/ */
static void i2s_hal_mclk_div_decimal_cal(i2s_hal_clock_cfg_t *clk_cfg, i2s_ll_mclk_div_t *cal) void i2s_hal_mclk_div_decimal_cal(i2s_hal_clock_cfg_t *clk_cfg, i2s_ll_mclk_div_t *cal)
{ {
int ma = 0; int ma = 0;
int mb = 0; int mb = 0;

10
components/hal/include/hal/i2s_hal.h
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@ -125,6 +125,16 @@ void i2s_hal_init(i2s_hal_context_t *hal, int i2s_num);
*/ */
void i2s_hal_set_clock_src(i2s_hal_context_t *hal, i2s_clock_src_t sel); void i2s_hal_set_clock_src(i2s_hal_context_t *hal, i2s_clock_src_t sel);
/**
* @brief Calculate the closest sample rate clock configuration.
* clock relationship:
* Fmclk = bck_div*fbck = fsclk/(mclk_div+b/a)
*
* @param clk_cfg I2S clock configuration(input)
* @param cal Point to `i2s_ll_mclk_div_t` structure(output).
*/
void i2s_hal_mclk_div_decimal_cal(i2s_hal_clock_cfg_t *clk_cfg, i2s_ll_mclk_div_t *cal);
/** /**
* @brief Set Tx channel style * @brief Set Tx channel style
* *

2
components/soc/esp32/include/soc/soc_caps.h
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@ -94,7 +94,7 @@
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) #define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */ /*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH (2*1000*1000) #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH (2*1000*1000)
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW (2000) #define SOC_ADC_SAMPLE_FREQ_THRES_LOW (20*1000)
/*!< RTC */ /*!< RTC */
#define SOC_ADC_MAX_BITWIDTH (12) #define SOC_ADC_MAX_BITWIDTH (12)

2
examples/peripherals/adc/dma_read/main/adc_dma_example_main.c
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@ -69,7 +69,7 @@ static void continuous_adc_init(uint16_t adc1_chan_mask, uint16_t adc2_chan_mask
adc_digi_configuration_t dig_cfg = { adc_digi_configuration_t dig_cfg = {
.conv_limit_en = ADC_CONV_LIMIT_EN, .conv_limit_en = ADC_CONV_LIMIT_EN,
.conv_limit_num = 250, .conv_limit_num = 250,
.sample_freq_hz = 10 * 1000, .sample_freq_hz = 20 * 1000,
.conv_mode = ADC_CONV_MODE, .conv_mode = ADC_CONV_MODE,
.format = ADC_OUTPUT_TYPE, .format = ADC_OUTPUT_TYPE,
}; };