feat(esp32p4): add eco1 revision config option

components/bootloader_support/src/esp32p4/bootloader_esp32p4.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -29,6 +29,7 @@
 #include "bootloader_flash_config.h"
 #include "bootloader_mem.h"
 #include "esp_private/regi2c_ctrl.h"
+#include "soc/chip_revision.h"
 #include "soc/regi2c_lp_bias.h"
 #include "soc/regi2c_bias.h"
 #include "bootloader_console.h"
@@ -90,13 +91,10 @@ static void bootloader_super_wdt_auto_feed(void)
 static inline void bootloader_hardware_init(void)
 {
     // regi2c is enabled by default on ESP32P4, do nothing
-
     unsigned chip_version = efuse_hal_chip_revision();
-    if (chip_version == 0) {
+    if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) {
         // On ESP32P4 ECO0, the default (power on reset) CPLL and SPLL frequencies are very high, lower them to avoid bias may not be enough in bootloader
-        // And we are fixing SPLL to be 480MHz at all runtime
+        // And we are fixing SPLL to be 480MHz after app is up
-        // Suppose to fix the issue on ECO1, will check when chip comes back
-        // TODO: IDF-8939
         REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M
         REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M
         esp_rom_delay_us(100);
@@ -173,7 +171,7 @@ esp_err_t bootloader_init(void)
     }
 #endif // !CONFIG_APP_BUILD_TYPE_RAM
 
-    // check whether a WDT reset happend
+    // check whether a WDT reset happened
     bootloader_check_wdt_reset();
     // config WDT
     bootloader_config_wdt();

components/esp_hw_support/port/esp32p4/Kconfig.hw_support

@@ -11,11 +11,14 @@ choice ESP32P4_REV_MIN
 
     config ESP32P4_REV_MIN_0
         bool "Rev v0.0"
+    config ESP32P4_REV_MIN_1
+        bool "Rev v0.1"
 endchoice
 
 config ESP32P4_REV_MIN_FULL
     int
     default 0 if ESP32P4_REV_MIN_0
+    default 1 if ESP32P4_REV_MIN_1
 
 config ESP_REV_MIN_FULL
     int

components/esp_hw_support/port/esp32p4/pmu_sleep.c

@@ -12,6 +12,7 @@
 #include "esp_err.h"
 #include "esp_attr.h"
 #include "esp_private/regi2c_ctrl.h"
+#include "soc/chip_revision.h"
 #include "soc/soc.h"
 #include "soc/regi2c_syspll.h"
 #include "soc/regi2c_cpll.h"
@@ -319,7 +320,7 @@ TCM_IRAM_ATTR bool pmu_sleep_finish(void)
     pmu_sleep_shutdown_ldo();
 
     unsigned chip_version = efuse_hal_chip_revision();
-    if (chip_version == 0) {
+    if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) {
         REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M
         REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M
     }

components/hal/esp32p4/include/hal/clk_tree_ll.h

@@ -9,6 +9,7 @@
 #include <stdint.h>
 #include "soc/clkout_channel.h"
 #include "soc/soc.h"
+#include "soc/chip_revision.h"
 #include "soc/clk_tree_defs.h"
 #include "soc/hp_sys_clkrst_reg.h"
 #include "soc/hp_sys_clkrst_struct.h"
@@ -24,6 +25,7 @@
 #include "hal/misc.h"
 #include "hal/efuse_hal.h"
 
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -310,12 +312,10 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpll_get_freq_mhz(u
 {
     uint8_t div = REGI2C_READ_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0);
     uint8_t ref_div = REGI2C_READ_MASK(I2C_CPLL, I2C_CPLL_OC_REF_DIV);
-#if !ESP_CHIP_REV_ABOVE(ESP_HAL_CHIP_REV_MIN, 1)
     unsigned chip_version = efuse_hal_chip_revision();
     if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) {
         return xtal_freq_mhz * (div + 4) / (ref_div + 1);
     } else
-#endif
     return xtal_freq_mhz * div / (ref_div + 1);
 }
 
@@ -343,11 +343,12 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_set_config(uint32_
     uint8_t dchgp = 5;
     uint8_t dcur = 3;
     uint8_t oc_enb_fcal = 0;
-    unsigned chip_version = efuse_hal_chip_revision();
 
     // Currently, only supporting 40MHz XTAL
     HAL_ASSERT(xtal_freq_mhz == SOC_XTAL_FREQ_40M);
-    if (chip_version == 0) {
+
+    unsigned chip_version = efuse_hal_chip_revision();
+    if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) {
         switch (cpll_freq_mhz) {
         case CLK_LL_PLL_400M_FREQ_MHZ:
             /* Configure 400M CPLL */
@@ -362,7 +363,7 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_set_config(uint32_
             break;
         }
     } else {
-        /*div7_0 bit2 & bit3 will swap from ECO1*/
+        /*div7_0 bit2 & bit3 is swapped from ECO1*/
         switch (cpll_freq_mhz) {
         case CLK_LL_PLL_400M_FREQ_MHZ:
             /* Configure 400M CPLL */