From 6505bcd29767df6c52d13b6f13461ffe6e504e80 Mon Sep 17 00:00:00 2001 From: Armando Date: Fri, 17 Jan 2025 11:31:11 +0800 Subject: [PATCH 1/2] refactor(psram): rename quad psram related naming --- .../esp_psram/device/esp_psram_impl_ap_quad.c | 52 ++++++------ .../esp_psram/device/esp_quad_psram_defs.h | 79 ------------------ .../esp_psram/device/esp_quad_psram_defs_ap.h | 83 +++++++++++++++++++ 3 files changed, 109 insertions(+), 105 deletions(-) delete mode 100644 components/esp_psram/device/esp_quad_psram_defs.h create mode 100644 components/esp_psram/device/esp_quad_psram_defs_ap.h diff --git a/components/esp_psram/device/esp_psram_impl_ap_quad.c b/components/esp_psram/device/esp_psram_impl_ap_quad.c index 742b2315c0..0eeb53e48f 100644 --- a/components/esp_psram/device/esp_psram_impl_ap_quad.c +++ b/components/esp_psram/device/esp_psram_impl_ap_quad.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,7 +16,7 @@ #include "esp_private/mspi_timing_tuning.h" #include "esp_private/esp_gpio_reserve.h" #include "hal/psram_ctrlr_ll.h" -#include "esp_quad_psram_defs.h" +#include "esp_quad_psram_defs_ap.h" #include "soc/soc_caps.h" static const char* TAG = "quad_psram"; @@ -60,7 +60,7 @@ void psram_exec_cmd(int spi_num, psram_hal_cmd_mode_t mode, static void psram_disable_qio_mode(int spi_num) { psram_exec_cmd(spi_num, PSRAM_HAL_CMD_QPI, - PSRAM_EXIT_QMODE, 8, /* command and command bit len*/ + PSRAM_QUAD_EXIT_QMODE, 8, /* command and command bit len*/ 0, 0, /* address and address bit len*/ 0, /* dummy bit len */ NULL, 0, /* tx data and tx bit len*/ @@ -75,7 +75,7 @@ static void psram_disable_qio_mode(int spi_num) static void psram_set_wrap_burst_length(int spi_num, psram_hal_cmd_mode_t mode) { psram_exec_cmd(spi_num, mode, - PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/ + PSRAM_QUAD_SET_BURST_LEN, 8, /* command and command bit len*/ 0, 0, /* address and address bit len*/ 0, /* dummy bit len */ NULL, 0, /* tx data and tx bit len*/ @@ -88,7 +88,7 @@ static void psram_set_wrap_burst_length(int spi_num, psram_hal_cmd_mode_t mode) static void psram_reset_mode(int spi_num) { psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI, - PSRAM_RESET_EN, 8, /* command and command bit len*/ + PSRAM_QUAD_RESET_EN, 8, /* command and command bit len*/ 0, 0, /* address and address bit len*/ 0, /* dummy bit len */ NULL, 0, /* tx data and tx bit len*/ @@ -97,7 +97,7 @@ static void psram_reset_mode(int spi_num) false); /* whether is program/erase operation */ psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI, - PSRAM_RESET, 8, /* command and command bit len*/ + PSRAM_QUAD_RESET, 8, /* command and command bit len*/ 0, 0, /* address and address bit len*/ 0, /* dummy bit len */ NULL, 0, /* tx data and tx bit len*/ @@ -144,7 +144,7 @@ bool psram_support_wrap_size(uint32_t wrap_size) static void psram_read_id(int spi_num, uint8_t* dev_id, int id_bits) { psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI, - PSRAM_DEVICE_ID, 8, /* command and command bit len*/ + PSRAM_QUAD_DEVICE_ID, 8, /* command and command bit len*/ 0, 24, /* address and address bit len*/ 0, /* dummy bit len */ NULL, 0, /* tx data and tx bit len*/ @@ -157,7 +157,7 @@ static void psram_read_id(int spi_num, uint8_t* dev_id, int id_bits) static void psram_enable_qio_mode(int spi_num) { psram_exec_cmd(spi_num, PSRAM_HAL_CMD_SPI, - PSRAM_ENTER_QMODE, 8, /* command and command bit len*/ + PSRAM_QUAD_ENTER_QMODE, 8, /* command and command bit len*/ 0, 0, /* address and address bit len*/ 0, /* dummy bit len */ NULL, 0, /* tx data and tx bit len*/ @@ -168,14 +168,14 @@ static void psram_enable_qio_mode(int spi_num) static void psram_set_cs_timing(void) { - psram_ctrlr_ll_set_cs_hold(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CS_HOLD_VAL); - psram_ctrlr_ll_set_cs_setup(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CS_SETUP_VAL); + psram_ctrlr_ll_set_cs_hold(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CS_HOLD_VAL); + psram_ctrlr_ll_set_cs_setup(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CS_SETUP_VAL); } static void psram_gpio_config(void) { //CS1 - uint8_t cs1_io = PSRAM_CS_IO; + uint8_t cs1_io = PSRAM_QUAD_CS_IO; if (cs1_io == MSPI_IOMUX_PIN_NUM_CS1) { gpio_ll_func_sel(&GPIO, cs1_io, FUNC_SPICS1_SPICS1); } else { @@ -185,7 +185,7 @@ static void psram_gpio_config(void) s_psram_cs_io = cs1_io; //WP HD - uint8_t wp_io = PSRAM_SPIWP_SD3_IO; + uint8_t wp_io = PSRAM_QUAD_SPIWP_SD3_IO; #if SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) { @@ -224,7 +224,7 @@ static void s_config_psram_clock(void) bool s_check_aps3204_2tmode(void) { uint64_t full_eid = 0; - psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&full_eid, PSRAM_EID_BITS_NUM); + psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&full_eid, PSRAM_QUAD_EID_BITS_NUM); bool is_2t = false; uint32_t eid_47_16 = __builtin_bswap32((full_eid >> 16) & UINT32_MAX); @@ -250,31 +250,31 @@ esp_err_t esp_psram_impl_enable(void) //We use SPI1 to init PSRAM psram_disable_qio_mode(PSRAM_CTRLR_LL_MSPI_ID_1); - psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&psram_id, PSRAM_ID_BITS_NUM); - if (!PSRAM_IS_VALID(psram_id)) { + psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&psram_id, PSRAM_QUAD_ID_BITS_NUM); + if (!PSRAM_QUAD_IS_VALID(psram_id)) { /* 16Mbit psram ID read error workaround: * treat the first read id as a dummy one as the pre-condition, * Send Read ID command again */ - psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&psram_id, PSRAM_ID_BITS_NUM); - if (!PSRAM_IS_VALID(psram_id)) { + psram_read_id(PSRAM_CTRLR_LL_MSPI_ID_1, (uint8_t *)&psram_id, PSRAM_QUAD_ID_BITS_NUM); + if (!PSRAM_QUAD_IS_VALID(psram_id)) { ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported, or wrong PSRAM line mode", (uint32_t)psram_id); return ESP_ERR_NOT_SUPPORTED; } } - if (PSRAM_IS_64MBIT_TRIAL(psram_id)) { + if (PSRAM_QUAD_IS_64MBIT_TRIAL(psram_id)) { s_psram_size = PSRAM_SIZE_8MB; } else { - uint8_t density = PSRAM_SIZE_ID(psram_id); - const int eid = PSRAM_EID_BIT_47_40(psram_id); + uint8_t density = PSRAM_QUAD_SIZE_ID(psram_id); + const int eid = PSRAM_QUAD_EID_BIT_47_40(psram_id); s_psram_size = density == 0x0 ? PSRAM_SIZE_2MB : density == 0x1 ? PSRAM_SIZE_4MB : density == 0x2 ? PSRAM_SIZE_8MB : /* Do not use `density` for QEMU PSRAM since we don't want any future QSPI PSRAM * that are 16MB or 32MB to be interpreted as QEMU PSRAM devices */ - eid == PSRAM_QEMU_16MB_ID ? PSRAM_SIZE_16MB : - eid == PSRAM_QEMU_32MB_ID ? PSRAM_SIZE_32MB : 0; + eid == PSRAM_QUAD_QEMU_16MB_ID ? PSRAM_SIZE_16MB : + eid == PSRAM_QUAD_QEMU_32MB_ID ? PSRAM_SIZE_32MB : 0; } if ((s_psram_size == PSRAM_SIZE_8MB) && s_check_aps3204_2tmode()) { @@ -306,10 +306,10 @@ esp_err_t esp_psram_impl_enable(void) static void config_psram_spi_phases(void) { psram_ctrlr_ll_set_read_mode(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_HAL_CMD_QPI); - psram_ctrlr_ll_set_wr_cmd(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CMD_LENGTH, PSRAM_QUAD_WRITE); - psram_ctrlr_ll_set_rd_cmd(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_CMD_LENGTH, PSRAM_FAST_READ_QUAD); - psram_ctrlr_ll_set_addr_bitlen(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_ADDR_LENGTH); - psram_ctrlr_ll_set_rd_dummy(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_FAST_READ_QUAD_DUMMY); + psram_ctrlr_ll_set_wr_cmd(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CMD_LENGTH, PSRAM_QUAD_WRITE_QUAD); + psram_ctrlr_ll_set_rd_cmd(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CMD_LENGTH, PSRAM_QUAD_FAST_READ_QUAD); + psram_ctrlr_ll_set_addr_bitlen(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_ADDR_LENGTH); + psram_ctrlr_ll_set_rd_dummy(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_FAST_READ_QUAD_DUMMY); psram_ctrlr_ll_set_cs_pin(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_LL_CS_ID_1); } diff --git a/components/esp_psram/device/esp_quad_psram_defs.h b/components/esp_psram/device/esp_quad_psram_defs.h deleted file mode 100644 index e78437768f..0000000000 --- a/components/esp_psram/device/esp_quad_psram_defs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -//Commands for PSRAM chip - -#pragma once - -#include "soc/spi_pins.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define PSRAM_READ 0x03 -#define PSRAM_FAST_READ 0x0B -#define PSRAM_FAST_READ_QUAD 0xEB -#define PSRAM_WRITE 0x02 -#define PSRAM_QUAD_WRITE 0x38 -#define PSRAM_ENTER_QMODE 0x35 -#define PSRAM_EXIT_QMODE 0xF5 -#define PSRAM_RESET_EN 0x66 -#define PSRAM_RESET 0x99 -#define PSRAM_SET_BURST_LEN 0xC0 -#define PSRAM_DEVICE_ID 0x9F - -#define PSRAM_FAST_READ_DUMMY 4 -#define PSRAM_FAST_READ_QUAD_DUMMY 6 - -// ID -#define PSRAM_ID_BITS_NUM 24 -#define PSRAM_EID_BITS_NUM 48 -#define PSRAM_ID_KGD_M 0xff -#define PSRAM_ID_KGD_S 8 -#define PSRAM_ID_KGD 0x5d -#define PSRAM_ID_EID_BIT_47_40_M 0xff -#define PSRAM_ID_EID_BIT_47_40_S 16 - -// Use the [47:45](bit47~bit45) of EID to distinguish the psram size: -// -// BIT47 | BIT46 | BIT45 | SIZE(MBIT) -// ------------------------------------- -// 0 | 0 | 0 | 16 -// 0 | 0 | 1 | 32 -// 0 | 1 | 0 | 64 -#define PSRAM_EID_BIT_47_45_M 0x07 -#define PSRAM_EID_BIT_47_45_S 5 - -#define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M) -#define PSRAM_EID_BIT_47_40(id) (((id) >> PSRAM_ID_EID_BIT_47_40_S) & PSRAM_ID_EID_BIT_47_40_M) -#define PSRAM_SIZE_ID(id) ((PSRAM_EID_BIT_47_40(id) >> PSRAM_EID_BIT_47_45_S) & PSRAM_EID_BIT_47_45_M) -#define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD) - -#define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID_BIT_47_40(id) == 0x26) - -// IO-pins for PSRAM. -// PSRAM clock and cs IO should be configured based on hardware design. -#define PSRAM_CLK_IO MSPI_IOMUX_PIN_NUM_CLK -#define PSRAM_CS_IO MSPI_IOMUX_PIN_NUM_CS1 -#define PSRAM_SPIQ_SD0_IO MSPI_IOMUX_PIN_NUM_MISO -#define PSRAM_SPID_SD1_IO MSPI_IOMUX_PIN_NUM_MOSI -#define PSRAM_SPIWP_SD3_IO MSPI_IOMUX_PIN_NUM_WP -#define PSRAM_SPIHD_SD2_IO MSPI_IOMUX_PIN_NUM_HD - -#define PSRAM_CMD_LENGTH 8 -#define PSRAM_ADDR_LENGTH 24 - -#define PSRAM_CS_HOLD_VAL 1 -#define PSRAM_CS_SETUP_VAL 1 - -// QEMU has a simulated 16MB and 32MB Quad SPI PSRAM. Use a fake ID for these. -#define PSRAM_QEMU_16MB_ID 0x6a -#define PSRAM_QEMU_32MB_ID 0x8e - -#ifdef __cplusplus -} -#endif diff --git a/components/esp_psram/device/esp_quad_psram_defs_ap.h b/components/esp_psram/device/esp_quad_psram_defs_ap.h new file mode 100644 index 0000000000..e1b0cb4481 --- /dev/null +++ b/components/esp_psram/device/esp_quad_psram_defs_ap.h @@ -0,0 +1,83 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +//Commands for PSRAM chip + +#pragma once + +#include "soc/spi_pins.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*--------------------------------------------------------------------------------- + * AP Memory PSRAM + *-------------------------------------------------------------------------------*/ + +#define PSRAM_QUAD_READ 0x03 +#define PSRAM_QUAD_FAST_READ 0x0B +#define PSRAM_QUAD_FAST_READ_QUAD 0xEB +#define PSRAM_QUAD_WRITE 0x02 +#define PSRAM_QUAD_WRITE_QUAD 0x38 +#define PSRAM_QUAD_ENTER_QMODE 0x35 +#define PSRAM_QUAD_EXIT_QMODE 0xF5 +#define PSRAM_QUAD_RESET_EN 0x66 +#define PSRAM_QUAD_RESET 0x99 +#define PSRAM_QUAD_SET_BURST_LEN 0xC0 +#define PSRAM_QUAD_DEVICE_ID 0x9F + +#define PSRAM_QUAD_FAST_READ_DUMMY 4 +#define PSRAM_QUAD_FAST_READ_QUAD_DUMMY 6 + +// ID +#define PSRAM_QUAD_ID_BITS_NUM 24 +#define PSRAM_QUAD_EID_BITS_NUM 48 +#define PSRAM_QUAD_ID_KGD_M 0xff +#define PSRAM_QUAD_ID_KGD_S 8 +#define PSRAM_QUAD_ID_KGD 0x5d +#define PSRAM_QUAD_ID_EID_BIT_47_40_M 0xff +#define PSRAM_QUAD_ID_EID_BIT_47_40_S 16 + +// Use the [47:45](bit47~bit45) of EID to distinguish the psram size: +// +// BIT47 | BIT46 | BIT45 | SIZE(MBIT) +// ------------------------------------- +// 0 | 0 | 0 | 16 +// 0 | 0 | 1 | 32 +// 0 | 1 | 0 | 64 +#define PSRAM_QUAD_EID_BIT_47_45_M 0x07 +#define PSRAM_QUAD_EID_BIT_47_45_S 5 + +#define PSRAM_QUAD_KGD(id) (((id) >> PSRAM_QUAD_ID_KGD_S) & PSRAM_QUAD_ID_KGD_M) +#define PSRAM_QUAD_EID_BIT_47_40(id) (((id) >> PSRAM_QUAD_ID_EID_BIT_47_40_S) & PSRAM_QUAD_ID_EID_BIT_47_40_M) +#define PSRAM_QUAD_SIZE_ID(id) ((PSRAM_QUAD_EID_BIT_47_40(id) >> PSRAM_QUAD_EID_BIT_47_45_S) & PSRAM_QUAD_EID_BIT_47_45_M) +#define PSRAM_QUAD_IS_VALID(id) (PSRAM_QUAD_KGD(id) == PSRAM_QUAD_ID_KGD) + +#define PSRAM_QUAD_IS_64MBIT_TRIAL(id) (PSRAM_QUAD_EID_BIT_47_40(id) == 0x26) + +// IO-pins for PSRAM. +// PSRAM clock and cs IO should be configured based on hardware design. +#define PSRAM_QUAD_CLK_IO MSPI_IOMUX_PIN_NUM_CLK +#define PSRAM_QUAD_CS_IO MSPI_IOMUX_PIN_NUM_CS1 +#define PSRAM_QUAD_SPIQ_SD0_IO MSPI_IOMUX_PIN_NUM_MISO +#define PSRAM_QUAD_SPID_SD1_IO MSPI_IOMUX_PIN_NUM_MOSI +#define PSRAM_QUAD_SPIWP_SD3_IO MSPI_IOMUX_PIN_NUM_WP +#define PSRAM_QUAD_SPIHD_SD2_IO MSPI_IOMUX_PIN_NUM_HD + +#define PSRAM_QUAD_CMD_LENGTH 8 +#define PSRAM_QUAD_ADDR_LENGTH 24 + +#define PSRAM_QUAD_CS_HOLD_VAL 1 +#define PSRAM_QUAD_CS_SETUP_VAL 1 + +// QEMU has a simulated 16MB and 32MB Quad SPI PSRAM. Use a fake ID for these. +#define PSRAM_QUAD_QEMU_16MB_ID 0x6a +#define PSRAM_QUAD_QEMU_32MB_ID 0x8e + +#ifdef __cplusplus +} +#endif From 8a654ffce12ad16659bd5b387dd878fd4627bc4d Mon Sep 17 00:00:00 2001 From: Armando Date: Fri, 17 Jan 2025 14:27:38 +0800 Subject: [PATCH 2/2] feat(psram): ecc feature on c5 c61 --- .../esp_psram/device/esp_psram_impl_ap_quad.c | 57 +++- .../esp_psram/device/esp_quad_psram_defs_ap.h | 4 + components/esp_psram/esp32c5/Kconfig.spiram | 8 + components/esp_psram/esp32c61/Kconfig.spiram | 8 + .../hal/esp32c5/include/hal/psram_ctrlr_ll.h | 246 +++++++++++++++++- .../hal/esp32c61/include/hal/psram_ctrlr_ll.h | 246 +++++++++++++++++- .../hal/esp32s3/include/hal/psram_ctrlr_ll.h | 2 +- components/hal/include/hal/psram_types.h | 2 +- 8 files changed, 560 insertions(+), 13 deletions(-) diff --git a/components/esp_psram/device/esp_psram_impl_ap_quad.c b/components/esp_psram/device/esp_psram_impl_ap_quad.c index 0eeb53e48f..a709533944 100644 --- a/components/esp_psram/device/esp_psram_impl_ap_quad.c +++ b/components/esp_psram/device/esp_psram_impl_ap_quad.c @@ -31,7 +31,7 @@ uint8_t esp_psram_impl_get_cs_io(void) return s_psram_cs_io; } -void psram_exec_cmd(int spi_num, psram_hal_cmd_mode_t mode, +void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode, uint32_t cmd, int cmd_bit_len, uint32_t addr, int addr_bit_len, int dummy_bits, @@ -72,7 +72,7 @@ static void psram_disable_qio_mode(int spi_num) //TODO IDF-4307 //switch psram burst length(32 bytes or 1024 bytes) //datasheet says it should be 1024 bytes by default -static void psram_set_wrap_burst_length(int spi_num, psram_hal_cmd_mode_t mode) +static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_t mode) { psram_exec_cmd(spi_num, mode, PSRAM_QUAD_SET_BURST_LEN, 8, /* command and command bit len*/ @@ -170,8 +170,50 @@ static void psram_set_cs_timing(void) { psram_ctrlr_ll_set_cs_hold(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CS_HOLD_VAL); psram_ctrlr_ll_set_cs_setup(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CS_SETUP_VAL); +#if CONFIG_SPIRAM_ECC_ENABLE + psram_ctrlr_ll_set_ecc_cs_hold(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_CS_ECC_HOLD_TIME_VAL); +#endif } +#if CONFIG_SPIRAM_ECC_ENABLE +static void s_mspi_ecc_show_info(void) +{ + for (int i = 0; i < PSRAM_CTRLR_LL_PMS_REGION_NUMS; i++) { + ESP_EARLY_LOGV(TAG, "region[%d] addr: 0x%08x", i, psram_ctrlr_ll_get_pms_region_start_addr(PSRAM_CTRLR_LL_MSPI_ID_0, i)); + ESP_EARLY_LOGV(TAG, "region[%d] size: 0x%08x", i, psram_ctrlr_ll_get_pms_region_size(PSRAM_CTRLR_LL_MSPI_ID_0, i)); + } + + uint32_t page_size = psram_ctrlr_ll_get_page_size(PSRAM_CTRLR_LL_MSPI_ID_0); + ESP_EARLY_LOGV(TAG, "ECC page size: %d", page_size); +} + +/** + * Enable error correcting code feature + * + * Can add an input parameter for selecting ECC mode if needed + */ +static void s_configure_psram_ecc(void) +{ + psram_ctrlr_ll_set_ecc_mode(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_LL_ECC_MODE_16TO18); + psram_ctrlr_ll_enable_skip_page_corner(PSRAM_CTRLR_LL_MSPI_ID_0, true); + psram_ctrlr_ll_enable_split_trans(PSRAM_CTRLR_LL_MSPI_ID_0, true); + psram_ctrlr_ll_set_page_size(PSRAM_CTRLR_LL_MSPI_ID_0, PSRAM_QUAD_PAGE_SIZE); + psram_ctrlr_ll_enable_ecc_addr_conversion(PSRAM_CTRLR_LL_MSPI_ID_0, true); + + /** + * Enable ECC region 0 (ACE0) + * Default: ACE0 range: 0 ~ 256MB + * For current Quad PSRAM, ACE0 is enough + */ + psram_ctrlr_ll_set_pms_region_start_addr(PSRAM_CTRLR_LL_MSPI_ID_0, 0, 0); + psram_ctrlr_ll_set_pms_region_size(PSRAM_CTRLR_LL_MSPI_ID_0, 0, 4096); + psram_ctrlr_ll_set_pms_region_attr(PSRAM_CTRLR_LL_MSPI_ID_0, 0, PSRAM_CTRLR_LL_PMS_ATTR_WRITABLE | PSRAM_CTRLR_LL_PMS_ATTR_READABLE); + psram_ctrlr_ll_enable_pms_region_ecc(PSRAM_CTRLR_LL_MSPI_ID_0, 0, true); + ESP_EARLY_LOGI(TAG, "ECC is enabled"); + s_mspi_ecc_show_info(); +} +#endif + static void psram_gpio_config(void) { //CS1 @@ -240,6 +282,9 @@ esp_err_t esp_psram_impl_enable(void) { psram_gpio_config(); psram_set_cs_timing(); +#if CONFIG_SPIRAM_ECC_ENABLE + s_configure_psram_ecc(); +#endif #if SOC_SPI_MEM_SUPPORT_TIMING_TUNING //enter MSPI slow mode to init PSRAM device registers @@ -330,9 +375,7 @@ esp_err_t esp_psram_impl_get_physical_size(uint32_t *out_size_bytes) /** * This function is to get the available physical psram size in bytes. - * - * When ECC is enabled, the available size will be reduced. - * On S3 Quad PSRAM, ECC is not enabled for now. + * If ECC is enabled, available PSRAM size will be 7/8 times its physical size. */ esp_err_t esp_psram_impl_get_available_size(uint32_t *out_size_bytes) { @@ -340,6 +383,10 @@ esp_err_t esp_psram_impl_get_available_size(uint32_t *out_size_bytes) return ESP_ERR_INVALID_ARG; } +#if CONFIG_SPIRAM_ECC_ENABLE + *out_size_bytes = s_psram_size * 7 / 8; +#else *out_size_bytes = s_psram_size; +#endif return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE); } diff --git a/components/esp_psram/device/esp_quad_psram_defs_ap.h b/components/esp_psram/device/esp_quad_psram_defs_ap.h index e1b0cb4481..829a1442e1 100644 --- a/components/esp_psram/device/esp_quad_psram_defs_ap.h +++ b/components/esp_psram/device/esp_quad_psram_defs_ap.h @@ -73,6 +73,10 @@ extern "C" { #define PSRAM_QUAD_CS_HOLD_VAL 1 #define PSRAM_QUAD_CS_SETUP_VAL 1 +#define PSRAM_QUAD_CS_ECC_HOLD_TIME_VAL 3 + +#define PSRAM_QUAD_PAGE_SIZE 512 +#define PSRAM_QUAD_ECC_ENABLE_MASK BIT(8) // QEMU has a simulated 16MB and 32MB Quad SPI PSRAM. Use a fake ID for these. #define PSRAM_QUAD_QEMU_16MB_ID 0x6a diff --git a/components/esp_psram/esp32c5/Kconfig.spiram b/components/esp_psram/esp32c5/Kconfig.spiram index ca941e8f1d..a27b718f9c 100644 --- a/components/esp_psram/esp32c5/Kconfig.spiram +++ b/components/esp_psram/esp32c5/Kconfig.spiram @@ -68,5 +68,13 @@ menu "SPI RAM config" This is a helper indicating this condition: `CONFIG_SPIRAM_XIP_FROM_PSRAM && CONFIG_IDF_TARGET_ESP32C5` + config SPIRAM_ECC_ENABLE + bool "Enable PSRAM ECC" + default n + help + Enable MSPI Error-Correcting Code function when accessing PSRAM. + + If enabled, 1/8 of the PSRAM total size will be reserved for error-correcting code. + source "$IDF_PATH/components/esp_psram/Kconfig.spiram.common" # insert non-chip-specific items here endmenu diff --git a/components/esp_psram/esp32c61/Kconfig.spiram b/components/esp_psram/esp32c61/Kconfig.spiram index fefbd96463..a5e97acfc6 100644 --- a/components/esp_psram/esp32c61/Kconfig.spiram +++ b/components/esp_psram/esp32c61/Kconfig.spiram @@ -68,5 +68,13 @@ menu "SPI RAM config" This is a helper indicating this condition: `CONFIG_SPIRAM_XIP_FROM_PSRAM && CONFIG_IDF_TARGET_ESP32C61` + config SPIRAM_ECC_ENABLE + bool "Enable PSRAM ECC" + default n + help + Enable MSPI Error-Correcting Code function when accessing PSRAM. + + If enabled, 1/8 of the PSRAM total size will be reserved for error-correcting code. + source "$IDF_PATH/components/esp_psram/Kconfig.spiram.common" # insert non-chip-specific items here endmenu diff --git a/components/hal/esp32c5/include/hal/psram_ctrlr_ll.h b/components/hal/esp32c5/include/hal/psram_ctrlr_ll.h index 0a9946ff57..868dcee35c 100644 --- a/components/hal/esp32c5/include/hal/psram_ctrlr_ll.h +++ b/components/hal/esp32c5/include/hal/psram_ctrlr_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,7 +30,10 @@ extern "C" { #define PSRAM_CTRLR_LL_MSPI_ID_0 0 #define PSRAM_CTRLR_LL_MSPI_ID_1 1 -#define PSRAM_LL_CS_SEL SPI_MEM_CS1_DIS_M +#define PSRAM_LL_CS_SEL SPI_MEM_CS1_DIS_M +#define PSRAM_CTRLR_LL_PMS_REGION_NUMS 4 +#define PSRAM_CTRLR_LL_PMS_ATTR_WRITABLE (1<<0) +#define PSRAM_CTRLR_LL_PMS_ATTR_READABLE (1<<1) /** * @brief PSRAM enum for cs id. @@ -40,6 +43,14 @@ typedef enum { PSRAM_LL_CS_ID_1 = 1, } psram_ll_cs_id_t; +/** + * @brief PSRAM ECC mode + */ +typedef enum { + PSRAM_LL_ECC_MODE_16TO17 = 0, + PSRAM_LL_ECC_MODE_16TO18 = 1, +} psram_ll_ecc_mode_t; + /** * @brief Set PSRAM write cmd * @@ -140,7 +151,7 @@ static inline uint32_t psram_ctrlr_ll_calculate_clock_reg(uint8_t clkdiv) * @param mspi_id mspi_id * @param read_mode read mode */ -static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_hal_cmd_mode_t read_mode) +static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_cmd_mode_t read_mode) { typeof (SPIMEM0.mem_cache_sctrl) mem_cache_sctrl; mem_cache_sctrl.val = SPIMEM0.mem_cache_sctrl.val; @@ -258,6 +269,235 @@ static inline void psram_ctrlr_ll_enable_quad_command(uint32_t mspi_id, bool ena SPIMEM1.ctrl.fcmd_quad = ena; } +/*--------------------------------------------------------------- + ECC +---------------------------------------------------------------*/ +/** + * @brief Set ECC CS hold + * + * @param mspi_id mspi_id + * @param hold_n cs hold time + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_set_ecc_cs_hold(uint32_t mspi_id, uint32_t hold_n) +{ + HAL_ASSERT(hold_n > 0); + SPIMEM0.smem_ac.smem_ecc_cs_hold_time = hold_n - 1; +} + +/** + * @brief Set ECC mode + * + * @param mspi_id mspi_id + * @param mode ecc mode + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_set_ecc_mode(uint32_t mspi_id, psram_ll_ecc_mode_t mode) +{ + SPIMEM0.smem_ac.smem_ecc_16to18_byte_en = mode; +} + +/** + * @brief Set page size + * + * @param mspi_id mspi_id + * @param size page size + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_set_page_size(uint32_t mspi_id, uint32_t size) +{ + uint32_t size_val = 0; + switch (size) { + case 256: + size_val = 0; + break; + case 512: + size_val = 1; + break; + case 1024: + size_val = 2; + break; + case 2048: + size_val = 3; + break; + default: + HAL_ASSERT(false); + break; + } + + SPIMEM0.smem_ecc_ctrl.smem_page_size = size_val; +} + +/** + * @brief Get page size + * + * @param mspi_id mspi_id + * + * @return page size + */ +__attribute__((always_inline)) +static inline uint32_t psram_ctrlr_ll_get_page_size(uint32_t mspi_id) +{ + (void)mspi_id; + uint32_t page_size = 0; + + uint32_t reg_val = SPIMEM0.smem_ecc_ctrl.smem_page_size; + switch(reg_val) { + case 0: + page_size = 256; + break; + case 1: + page_size = 512; + break; + case 2: + page_size = 1024; + break; + case 3: + page_size = 2048; + break; + default: + HAL_ASSERT(false); + } + + return page_size; +} + +/** + * @brief Skip page corner + * + * @param mspi_id mspi_id + * @param en enable / disable + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_enable_skip_page_corner(uint32_t mspi_id, bool en) +{ + SPIMEM0.smem_ac.smem_ecc_skip_page_corner = en; +} + +/** + * @brief Enable splitting transactions + * + * @param mspi_id mspi_id + * @param en enable / disable + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_enable_split_trans(uint32_t mspi_id, bool en) +{ + (void)mspi_id; + SPIMEM0.smem_ac.smem_split_trans_en = en; +} + +/** + * @brief Enable ECC address conversion + * + * @param mspi_id mspi_id + * @param en enable / disable + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_enable_ecc_addr_conversion(uint32_t mspi_id, bool en) +{ + (void)mspi_id; + SPIMEM0.smem_ecc_ctrl.smem_ecc_addr_en = en; +} + +/*--------------------------------------------------------------- + PMS +---------------------------------------------------------------*/ +/** + * @brief Enable PMS ECC + * + * @param mspi_id mspi_id + * @param region_id region_id + * @param en enable / disable + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_enable_pms_region_ecc(uint32_t mspi_id, uint32_t region_id, bool en) +{ + (void)mspi_id; + HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS); + SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_ecc = en; +} + +/** + * @brief Set PMS attr + * + * @param mspi_id mspi_id + * @param region_id region_id + * @param attr_mask attribute mask + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_set_pms_region_attr(uint32_t mspi_id, uint32_t region_id, uint32_t attr_mask) +{ + (void)mspi_id; + HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS); + SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_wr_attr = 0; + SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_rd_attr = 0; + if (attr_mask & PSRAM_CTRLR_LL_PMS_ATTR_WRITABLE) { + SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_wr_attr = 1; + } + if (attr_mask & PSRAM_CTRLR_LL_PMS_ATTR_READABLE) { + SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_rd_attr = 1; + } +} + +/** + * @brief Set PMS address + * + * @param mspi_id mspi_id + * @param region_id region_id + * @param addr start addr + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_set_pms_region_start_addr(uint32_t mspi_id, uint32_t region_id, uint32_t addr) +{ + (void)mspi_id; + HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS); + SPIMEM0.smem_pmsn_addr[region_id].smem_pmsn_addr_s = addr; +} + +/** + * @brief Set PMS size + * + * @param mspi_id mspi_id + * @param region_id region_id + * @param size size + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_set_pms_region_size(uint32_t mspi_id, uint32_t region_id, uint32_t size) +{ + (void)mspi_id; + HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS); + SPIMEM0.smem_pmsn_size[region_id].smem_pmsn_size = size; +} + +/** + * @brief Get PMS address + * + * @param mspi_id mspi_id + * @param region_id region_id + */ +__attribute__((always_inline)) +static inline uint32_t psram_ctrlr_ll_get_pms_region_start_addr(uint32_t mspi_id, uint32_t region_id) +{ + (void)mspi_id; + HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS); + return SPIMEM0.smem_pmsn_addr[region_id].smem_pmsn_addr_s; +} + +/** + * @brief Get PMS size + * + * @param mspi_id mspi_id + * @param region_id region_id + */ +__attribute__((always_inline)) +static inline uint32_t psram_ctrlr_ll_get_pms_region_size(uint32_t mspi_id, uint32_t region_id) +{ + (void)mspi_id; + HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS); + return SPIMEM0.smem_pmsn_size[region_id].smem_pmsn_size; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c61/include/hal/psram_ctrlr_ll.h b/components/hal/esp32c61/include/hal/psram_ctrlr_ll.h index 0a9946ff57..868dcee35c 100644 --- a/components/hal/esp32c61/include/hal/psram_ctrlr_ll.h +++ b/components/hal/esp32c61/include/hal/psram_ctrlr_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,7 +30,10 @@ extern "C" { #define PSRAM_CTRLR_LL_MSPI_ID_0 0 #define PSRAM_CTRLR_LL_MSPI_ID_1 1 -#define PSRAM_LL_CS_SEL SPI_MEM_CS1_DIS_M +#define PSRAM_LL_CS_SEL SPI_MEM_CS1_DIS_M +#define PSRAM_CTRLR_LL_PMS_REGION_NUMS 4 +#define PSRAM_CTRLR_LL_PMS_ATTR_WRITABLE (1<<0) +#define PSRAM_CTRLR_LL_PMS_ATTR_READABLE (1<<1) /** * @brief PSRAM enum for cs id. @@ -40,6 +43,14 @@ typedef enum { PSRAM_LL_CS_ID_1 = 1, } psram_ll_cs_id_t; +/** + * @brief PSRAM ECC mode + */ +typedef enum { + PSRAM_LL_ECC_MODE_16TO17 = 0, + PSRAM_LL_ECC_MODE_16TO18 = 1, +} psram_ll_ecc_mode_t; + /** * @brief Set PSRAM write cmd * @@ -140,7 +151,7 @@ static inline uint32_t psram_ctrlr_ll_calculate_clock_reg(uint8_t clkdiv) * @param mspi_id mspi_id * @param read_mode read mode */ -static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_hal_cmd_mode_t read_mode) +static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_cmd_mode_t read_mode) { typeof (SPIMEM0.mem_cache_sctrl) mem_cache_sctrl; mem_cache_sctrl.val = SPIMEM0.mem_cache_sctrl.val; @@ -258,6 +269,235 @@ static inline void psram_ctrlr_ll_enable_quad_command(uint32_t mspi_id, bool ena SPIMEM1.ctrl.fcmd_quad = ena; } +/*--------------------------------------------------------------- + ECC +---------------------------------------------------------------*/ +/** + * @brief Set ECC CS hold + * + * @param mspi_id mspi_id + * @param hold_n cs hold time + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_set_ecc_cs_hold(uint32_t mspi_id, uint32_t hold_n) +{ + HAL_ASSERT(hold_n > 0); + SPIMEM0.smem_ac.smem_ecc_cs_hold_time = hold_n - 1; +} + +/** + * @brief Set ECC mode + * + * @param mspi_id mspi_id + * @param mode ecc mode + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_set_ecc_mode(uint32_t mspi_id, psram_ll_ecc_mode_t mode) +{ + SPIMEM0.smem_ac.smem_ecc_16to18_byte_en = mode; +} + +/** + * @brief Set page size + * + * @param mspi_id mspi_id + * @param size page size + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_set_page_size(uint32_t mspi_id, uint32_t size) +{ + uint32_t size_val = 0; + switch (size) { + case 256: + size_val = 0; + break; + case 512: + size_val = 1; + break; + case 1024: + size_val = 2; + break; + case 2048: + size_val = 3; + break; + default: + HAL_ASSERT(false); + break; + } + + SPIMEM0.smem_ecc_ctrl.smem_page_size = size_val; +} + +/** + * @brief Get page size + * + * @param mspi_id mspi_id + * + * @return page size + */ +__attribute__((always_inline)) +static inline uint32_t psram_ctrlr_ll_get_page_size(uint32_t mspi_id) +{ + (void)mspi_id; + uint32_t page_size = 0; + + uint32_t reg_val = SPIMEM0.smem_ecc_ctrl.smem_page_size; + switch(reg_val) { + case 0: + page_size = 256; + break; + case 1: + page_size = 512; + break; + case 2: + page_size = 1024; + break; + case 3: + page_size = 2048; + break; + default: + HAL_ASSERT(false); + } + + return page_size; +} + +/** + * @brief Skip page corner + * + * @param mspi_id mspi_id + * @param en enable / disable + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_enable_skip_page_corner(uint32_t mspi_id, bool en) +{ + SPIMEM0.smem_ac.smem_ecc_skip_page_corner = en; +} + +/** + * @brief Enable splitting transactions + * + * @param mspi_id mspi_id + * @param en enable / disable + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_enable_split_trans(uint32_t mspi_id, bool en) +{ + (void)mspi_id; + SPIMEM0.smem_ac.smem_split_trans_en = en; +} + +/** + * @brief Enable ECC address conversion + * + * @param mspi_id mspi_id + * @param en enable / disable + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_enable_ecc_addr_conversion(uint32_t mspi_id, bool en) +{ + (void)mspi_id; + SPIMEM0.smem_ecc_ctrl.smem_ecc_addr_en = en; +} + +/*--------------------------------------------------------------- + PMS +---------------------------------------------------------------*/ +/** + * @brief Enable PMS ECC + * + * @param mspi_id mspi_id + * @param region_id region_id + * @param en enable / disable + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_enable_pms_region_ecc(uint32_t mspi_id, uint32_t region_id, bool en) +{ + (void)mspi_id; + HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS); + SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_ecc = en; +} + +/** + * @brief Set PMS attr + * + * @param mspi_id mspi_id + * @param region_id region_id + * @param attr_mask attribute mask + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_set_pms_region_attr(uint32_t mspi_id, uint32_t region_id, uint32_t attr_mask) +{ + (void)mspi_id; + HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS); + SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_wr_attr = 0; + SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_rd_attr = 0; + if (attr_mask & PSRAM_CTRLR_LL_PMS_ATTR_WRITABLE) { + SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_wr_attr = 1; + } + if (attr_mask & PSRAM_CTRLR_LL_PMS_ATTR_READABLE) { + SPIMEM0.smem_pmsn_attr[region_id].smem_pmsn_rd_attr = 1; + } +} + +/** + * @brief Set PMS address + * + * @param mspi_id mspi_id + * @param region_id region_id + * @param addr start addr + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_set_pms_region_start_addr(uint32_t mspi_id, uint32_t region_id, uint32_t addr) +{ + (void)mspi_id; + HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS); + SPIMEM0.smem_pmsn_addr[region_id].smem_pmsn_addr_s = addr; +} + +/** + * @brief Set PMS size + * + * @param mspi_id mspi_id + * @param region_id region_id + * @param size size + */ +__attribute__((always_inline)) +static inline void psram_ctrlr_ll_set_pms_region_size(uint32_t mspi_id, uint32_t region_id, uint32_t size) +{ + (void)mspi_id; + HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS); + SPIMEM0.smem_pmsn_size[region_id].smem_pmsn_size = size; +} + +/** + * @brief Get PMS address + * + * @param mspi_id mspi_id + * @param region_id region_id + */ +__attribute__((always_inline)) +static inline uint32_t psram_ctrlr_ll_get_pms_region_start_addr(uint32_t mspi_id, uint32_t region_id) +{ + (void)mspi_id; + HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS); + return SPIMEM0.smem_pmsn_addr[region_id].smem_pmsn_addr_s; +} + +/** + * @brief Get PMS size + * + * @param mspi_id mspi_id + * @param region_id region_id + */ +__attribute__((always_inline)) +static inline uint32_t psram_ctrlr_ll_get_pms_region_size(uint32_t mspi_id, uint32_t region_id) +{ + (void)mspi_id; + HAL_ASSERT(region_id < PSRAM_CTRLR_LL_PMS_REGION_NUMS); + return SPIMEM0.smem_pmsn_size[region_id].smem_pmsn_size; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/psram_ctrlr_ll.h b/components/hal/esp32s3/include/hal/psram_ctrlr_ll.h index ff8245bdf7..ba9be84f77 100644 --- a/components/hal/esp32s3/include/hal/psram_ctrlr_ll.h +++ b/components/hal/esp32s3/include/hal/psram_ctrlr_ll.h @@ -109,7 +109,7 @@ static inline void psram_ctrlr_ll_set_rd_dummy(uint32_t mspi_id, uint32_t dummy_ * @param mspi_id mspi_id * @param read_mode read mode */ -static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_hal_cmd_mode_t read_mode) +static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_cmd_mode_t read_mode) { typeof (SPIMEM0.cache_sctrl) cache_sctrl; cache_sctrl.val = SPIMEM0.cache_sctrl.val; diff --git a/components/hal/include/hal/psram_types.h b/components/hal/include/hal/psram_types.h index 586b689060..3d6fc9752c 100644 --- a/components/hal/include/hal/psram_types.h +++ b/components/hal/include/hal/psram_types.h @@ -18,7 +18,7 @@ extern "C" { typedef enum { PSRAM_HAL_CMD_QPI, /*!< Quad command for psram command */ PSRAM_HAL_CMD_SPI, /*!< SPI command for psram command */ -} psram_hal_cmd_mode_t; +} psram_cmd_mode_t; #ifdef __cplusplus }