From cceccb4ed927d3fed467e36e62822c826b88fdba Mon Sep 17 00:00:00 2001 From: jiangguangming Date: Wed, 12 Oct 2022 10:01:42 +0800 Subject: [PATCH] hal: add rtc_cntl LL function for wake stub --- .../hal/esp32/include/hal/rtc_cntl_ll.h | 60 ++++++++++++---- .../hal/esp32c2/include/hal/rtc_cntl_ll.h | 39 +++++++++-- .../hal/esp32c3/include/hal/rtc_cntl_ll.h | 43 +++++++++--- .../hal/esp32c6/include/hal/rtc_cntl_ll.h | 44 +++++++++--- .../hal/esp32h2/include/hal/rtc_cntl_ll.h | 46 ++++++++++--- .../hal/esp32h4/include/hal/rtc_cntl_ll.h | 39 +++++++++-- .../hal/esp32s2/include/hal/rtc_cntl_ll.h | 45 +++++++++--- .../hal/esp32s3/include/hal/rtc_cntl_ll.h | 69 +++++++++++++------ 8 files changed, 297 insertions(+), 88 deletions(-) diff --git a/components/hal/esp32/include/hal/rtc_cntl_ll.h b/components/hal/esp32/include/hal/rtc_cntl_ll.h index 30d24e60d7..7e87d1d2ab 100644 --- a/components/hal/esp32/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32/include/hal/rtc_cntl_ll.h @@ -8,71 +8,107 @@ #include "soc/soc.h" #include "soc/rtc.h" - +#include "esp_attr.h" +#include "clk_tree_ll.h" +#include "esp_rom_sys.h" #ifdef __cplusplus extern "C" { #endif -static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t) { WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); } -static inline void rtc_cntl_ll_ext1_clear_wakeup_status(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_status(void) { REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR); } -static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_status(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_status(void) { return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS); } -static inline void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t mask, int mode) +FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t mask, int mode) { REG_SET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL, mask); SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, mode, RTC_CNTL_EXT_WAKEUP1_LV_S); } -static inline void rtc_cntl_ll_ext1_clear_wakeup_pins(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_pins(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL_M); } -static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void) { return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL); } -static inline void rtc_cntl_ll_ulp_wakeup_enable(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ulp_wakeup_enable(void) { SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN); } -static inline void rtc_cntl_ll_ulp_int_clear(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ulp_int_clear(void) { REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_SAR_INT_CLR); } -static inline void rtc_cntl_ll_timer2_set_touch_wait_cycle(uint32_t wait_cycle) +FORCE_INLINE_ATTR void rtc_cntl_ll_timer2_set_touch_wait_cycle(uint32_t wait_cycle) { REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, wait_cycle); } -static inline void rtc_cntl_ll_reset_system(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_reset_system(void) { REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); } -static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +FORCE_INLINE_ATTR void rtc_cntl_ll_reset_cpu(int cpu_no) { uint32_t rtc_cntl_rst = (cpu_no == 0) ? RTC_CNTL_SW_PROCPU_RST : RTC_CNTL_SW_APPCPU_RST; REG_WRITE(RTC_CNTL_OPTIONS0_REG, rtc_cntl_rst); } +FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN); +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE); + int attempts = 1000; + while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) { + esp_rom_delay_us(1); + if (attempts) { + if (--attempts == 0 && clk_ll_xtal32k_digi_is_enabled()) { + esp_rom_printf("32KHz xtal has been stopped\n"); + } + } + } + SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_TIME_VALID_INT_CLR); + uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG); + t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32; + return t; +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us) +{ + uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG); + return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value); +} + +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void) +{ + return REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_CAUSE); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c2/include/hal/rtc_cntl_ll.h b/components/hal/esp32c2/include/hal/rtc_cntl_ll.h index a10f4912b4..585ebd9bd6 100644 --- a/components/hal/esp32c2/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32c2/include/hal/rtc_cntl_ll.h @@ -10,12 +10,13 @@ #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" #include "soc/syscon_reg.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { #endif -static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t) { WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); @@ -24,18 +25,18 @@ static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M); } -static inline uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void) { return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS); } -static inline void rtc_cntl_ll_gpio_clear_wakeup_status(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_gpio_clear_wakeup_status(void) { REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR); REG_CLR_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR); } -static inline void rtc_cntl_ll_enable_cpu_retention(uint32_t addr) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention(uint32_t addr) { /* write memory address to register */ REG_SET_FIELD(SYSCON_RETENTION_CTRL_REG, SYSCON_RETENTION_LINK_ADDR, (uint32_t)addr); @@ -45,21 +46,45 @@ static inline void rtc_cntl_ll_enable_cpu_retention(uint32_t addr) REG_SET_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); } -static inline void rtc_cntl_ll_disable_cpu_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_disable_cpu_retention(void) { REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); } -static inline void rtc_cntl_ll_reset_system(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_reset_system(void) { REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); } -static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +FORCE_INLINE_ATTR void rtc_cntl_ll_reset_cpu(int cpu_no) { REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST); } +FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN); +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE); + uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG); + t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32; + return t; +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us) +{ + uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG); + return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value); +} + +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void) +{ + return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c3/include/hal/rtc_cntl_ll.h b/components/hal/esp32c3/include/hal/rtc_cntl_ll.h index 50dcb59a88..0fa0e3a606 100644 --- a/components/hal/esp32c3/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32c3/include/hal/rtc_cntl_ll.h @@ -10,12 +10,13 @@ #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" #include "soc/syscon_reg.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { #endif -static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t) { WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); @@ -24,48 +25,72 @@ static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M); } -static inline uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void) { return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS); } -static inline void rtc_cntl_ll_gpio_clear_wakeup_status(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_gpio_clear_wakeup_status(void) { REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR); REG_CLR_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR); } -static inline void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t addr) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t addr) { REG_SET_FIELD(SYSCON_RETENTION_CTRL_REG, SYSCON_RETENTION_LINK_ADDR, (uint32_t)addr); } -static inline void rtc_cntl_ll_enable_cpu_retention_clock(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention_clock(void) { REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); } -static inline void rtc_cntl_ll_enable_cpu_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention(void) { /* Enable retention when cpu sleep enable */ REG_SET_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); } -static inline void rtc_cntl_ll_disable_cpu_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_disable_cpu_retention(void) { REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); } -static inline void rtc_cntl_ll_reset_system(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_reset_system(void) { REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); } -static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +FORCE_INLINE_ATTR void rtc_cntl_ll_reset_cpu(int cpu_no) { REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST); } +FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN); +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE); + uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG); + t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32; + return t; +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us) +{ + uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG); + return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value); +} + +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void) +{ + return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c6/include/hal/rtc_cntl_ll.h b/components/hal/esp32c6/include/hal/rtc_cntl_ll.h index 058a53a2e1..25a1f55372 100644 --- a/components/hal/esp32c6/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32c6/include/hal/rtc_cntl_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,57 +9,81 @@ #include "soc/soc.h" #include "soc/rtc.h" #include "soc/lp_aon_reg.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { #endif -static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t) { // TODO: IDF-5645 } -static inline uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void) { // TODO: IDF-5645 return 0; } -static inline void rtc_cntl_ll_gpio_clear_wakeup_status(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_gpio_clear_wakeup_status(void) { // TODO: IDF-5645 } -static inline void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t addr) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t addr) { // TODO: IDF-5718 has removed the retention feature } -static inline void rtc_cntl_ll_enable_cpu_retention_clock(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention_clock(void) { // TODO: IDF-5718 has removed the retention feature } -static inline void rtc_cntl_ll_enable_cpu_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention(void) { // TODO: IDF-5718 has removed the retention feature } -static inline void rtc_cntl_ll_disable_cpu_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_disable_cpu_retention(void) { // TODO: IDF-5718 has removed the retention feature } -static inline void rtc_cntl_ll_reset_system(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_reset_system(void) { REG_SET_BIT(LP_AON_SYS_CFG_REG, LP_AON_HPSYS_SW_RESET); } -static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +FORCE_INLINE_ATTR void rtc_cntl_ll_reset_cpu(int cpu_no) { REG_SET_BIT(LP_AON_CPUCORE0_CFG_REG, LP_AON_CPU_CORE0_SW_RESET); } +FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void) +{ + // TODO: IDF-6064 +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void) +{ + // TODO: IDF-6064 + return 0; +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us) +{ + // TODO: IDF-6064 + return 0; +} + +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void) +{ + // TODO: IDF-6064 + return 0; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h2/include/hal/rtc_cntl_ll.h b/components/hal/esp32h2/include/hal/rtc_cntl_ll.h index 3817849cad..2df27b8dcf 100644 --- a/components/hal/esp32h2/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32h2/include/hal/rtc_cntl_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,63 +8,87 @@ #include "soc/soc.h" #include "soc/rtc.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { #endif -static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t) { // ESP32H2-TODO: IDF-6401 } -static inline uint32_t rtc_cntl_ll_gpio_get_wakeup_pins(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_gpio_get_wakeup_pins(void) { return 0; // ESP32H2-TODO: IDF-6401 } -static inline uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void) { // ESP32H2-TODO: IDF-6401 return 0; } -static inline void rtc_cntl_ll_gpio_clear_wakeup_status(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_gpio_clear_wakeup_status(void) { // ESP32H2-TODO: IDF-6401 } -static inline void rtc_cntl_ll_gpio_set_wakeup_pins(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_gpio_set_wakeup_pins(void) { // ESP32H2-TODO: IDF-5718 } -static inline void rtc_cntl_ll_gpio_clear_wakeup_pins(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_gpio_clear_wakeup_pins(void) { // ESP32H2-TODO: IDF-5718 } -static inline void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t addr) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t addr) { // ESP32H2-TODO: IDF-5718 has removed the retention feature } -static inline void rtc_cntl_ll_enable_cpu_retention_clock(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention_clock(void) { // ESP32H2-TODO: IDF-5718 has removed the retention feature } -static inline void rtc_cntl_ll_enable_cpu_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention(void) { // ESP32H2-TODO: IDF-5718 has removed the retention feature } -static inline void rtc_cntl_ll_disable_cpu_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_disable_cpu_retention(void) { // ESP32H2-TODO: IDF-5718 has removed the retention feature } +FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void) +{ + // TODO: IDF-6572 +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void) +{ + // TODO: IDF-6572 + return 0; +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us) +{ + // TODO: IDF-6572 + return 0; +} + +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void) +{ + // TODO: IDF-6572 + return 0; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h4/include/hal/rtc_cntl_ll.h b/components/hal/esp32h4/include/hal/rtc_cntl_ll.h index c3839240bc..0f086e5f62 100644 --- a/components/hal/esp32h4/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32h4/include/hal/rtc_cntl_ll.h @@ -10,12 +10,13 @@ #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" #include "soc/syscon_reg.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { #endif -static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t) { WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); @@ -24,37 +25,61 @@ static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M); } -static inline uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void) { return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS); } -static inline void rtc_cntl_ll_gpio_clear_wakeup_status(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_gpio_clear_wakeup_status(void) { REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR); REG_CLR_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS_CLR); } -static inline void rtc_cntl_ll_enable_cpu_retention(uint32_t addr) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention(uint32_t addr) { // ESP32H4-TODO: IDF-3383 } -static inline void rtc_cntl_ll_disable_cpu_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_disable_cpu_retention(void) { // ESP32H4-TODO: IDF-3383 } -static inline void rtc_cntl_ll_reset_system(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_reset_system(void) { REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); } -static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +FORCE_INLINE_ATTR void rtc_cntl_ll_reset_cpu(int cpu_no) { REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST); } +FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN); +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE); + uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG); + t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32; + return t; +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us) +{ + uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG); + return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value); +} + +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void) +{ + return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s2/include/hal/rtc_cntl_ll.h b/components/hal/esp32s2/include/hal/rtc_cntl_ll.h index 885422569e..0ccdedc879 100644 --- a/components/hal/esp32s2/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32s2/include/hal/rtc_cntl_ll.h @@ -9,12 +9,13 @@ #include "soc/soc.h" #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { #endif -static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t) { WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); @@ -23,55 +24,79 @@ static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M); } -static inline void rtc_cntl_ll_ext1_clear_wakeup_status(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_status(void) { REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR); } -static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_status(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_status(void) { return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS); } -static inline void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t mask, int mode) +FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t mask, int mode) { REG_SET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL, mask); SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, mode, RTC_CNTL_EXT_WAKEUP1_LV_S); } -static inline void rtc_cntl_ll_ext1_clear_wakeup_pins(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_pins(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL_M); } -static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void) { return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL); } -static inline void rtc_cntl_ll_ulp_int_clear(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ulp_int_clear(void) { REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_ULP_CP_INT_CLR); REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_INT_CLR); REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_TRAP_INT_CLR); } -static inline void rtc_cntl_ll_timer2_set_touch_wait_cycle(uint32_t wait_cycle) +FORCE_INLINE_ATTR void rtc_cntl_ll_timer2_set_touch_wait_cycle(uint32_t wait_cycle) { REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, wait_cycle); } -static inline void rtc_cntl_ll_reset_system(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_reset_system(void) { REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); } -static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +FORCE_INLINE_ATTR void rtc_cntl_ll_reset_cpu(int cpu_no) { REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST); } +FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN); +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE); + uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG); + t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32; + return t; +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us) +{ + uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG); + return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value); +} + +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void) +{ + return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/rtc_cntl_ll.h b/components/hal/esp32s3/include/hal/rtc_cntl_ll.h index e57532808f..464aa99cd6 100644 --- a/components/hal/esp32s3/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32s3/include/hal/rtc_cntl_ll.h @@ -10,6 +10,7 @@ #include "soc/rtc.h" #include "soc/rtc_cntl_reg.h" #include "soc/apb_ctrl_reg.h" +#include "esp_attr.h" #ifdef __cplusplus extern "C" { @@ -18,7 +19,7 @@ extern "C" { #define RTC_CNTL_LL_RETENTION_TARGET_CPU (BIT(0)) #define RTC_CNTL_LL_RETENTION_TARGET_TAGMEM (BIT(1)) -static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t) { WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); @@ -27,46 +28,46 @@ static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t) SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M); } -static inline void rtc_cntl_ll_ext1_clear_wakeup_status(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_status(void) { REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR); } -static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_status(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_status(void) { return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_STATUS_REG, RTC_CNTL_EXT_WAKEUP1_STATUS); } -static inline void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t mask, int mode) +FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_set_wakeup_pins(uint32_t mask, int mode) { REG_SET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL, mask); SET_PERI_REG_BITS(RTC_CNTL_EXT_WAKEUP_CONF_REG, 0x1, mode, RTC_CNTL_EXT_WAKEUP1_LV_S); } -static inline void rtc_cntl_ll_ext1_clear_wakeup_pins(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_pins(void) { CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL_M); } -static inline uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void) +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_ext1_get_wakeup_pins(void) { return REG_GET_FIELD(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_SEL); } -static inline void rtc_cntl_ll_set_tagmem_retention_link_addr(uint32_t link_addr) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_tagmem_retention_link_addr(uint32_t link_addr) { REG_SET_FIELD(APB_CTRL_RETENTION_CTRL1_REG, APB_CTRL_RETENTION_TAG_LINK_ADDR, link_addr); } -static inline void rtc_cntl_ll_enable_tagmem_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_tagmem_retention(void) { /* Enable i/d-cache tagmem retenttion. cpu: 1, tagmem: 2, cpu + tagmem: 3 */ uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET); REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET, (target | RTC_CNTL_LL_RETENTION_TARGET_TAGMEM)); } -static inline void rtc_cntl_ll_enable_icache_tagmem_retention(uint32_t start_point, uint32_t vld_size, uint32_t size) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_icache_tagmem_retention(uint32_t start_point, uint32_t vld_size, uint32_t size) { REG_SET_FIELD(APB_CTRL_RETENTION_CTRL2_REG, APB_CTRL_RET_ICACHE_START_POINT, start_point); REG_SET_FIELD(APB_CTRL_RETENTION_CTRL2_REG, APB_CTRL_RET_ICACHE_VLD_SIZE, vld_size); @@ -74,7 +75,7 @@ static inline void rtc_cntl_ll_enable_icache_tagmem_retention(uint32_t start_poi REG_SET_BIT(APB_CTRL_RETENTION_CTRL2_REG, APB_CTRL_RET_ICACHE_ENABLE); } -static inline void rtc_cntl_ll_enable_dcache_tagmem_retention(uint32_t start_point, uint32_t vld_size, uint32_t size) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_dcache_tagmem_retention(uint32_t start_point, uint32_t vld_size, uint32_t size) { REG_SET_FIELD(APB_CTRL_RETENTION_CTRL3_REG, APB_CTRL_RET_DCACHE_START_POINT, start_point); REG_SET_FIELD(APB_CTRL_RETENTION_CTRL3_REG, APB_CTRL_RET_DCACHE_VLD_SIZE, vld_size); @@ -82,34 +83,34 @@ static inline void rtc_cntl_ll_enable_dcache_tagmem_retention(uint32_t start_poi REG_SET_BIT(APB_CTRL_RETENTION_CTRL3_REG, APB_CTRL_RET_DCACHE_ENABLE); } -static inline void rtc_cntl_ll_disable_tagmem_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_disable_tagmem_retention(void) { /* Enable i/d-cache tagmem retenttion. cpu: 1, tagmem: 2, cpu + tagmem: 3 */ uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET); REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET, (target & ~RTC_CNTL_LL_RETENTION_TARGET_TAGMEM)); } -static inline void rtc_cntl_ll_disable_icache_tagmem_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_disable_icache_tagmem_retention(void) { REG_CLR_BIT(APB_CTRL_RETENTION_CTRL2_REG, APB_CTRL_RET_ICACHE_ENABLE); } -static inline void rtc_cntl_ll_disable_dcache_tagmem_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_disable_dcache_tagmem_retention(void) { REG_CLR_BIT(APB_CTRL_RETENTION_CTRL3_REG, APB_CTRL_RET_DCACHE_ENABLE); } -static inline void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t link_addr) +FORCE_INLINE_ATTR void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t link_addr) { REG_SET_FIELD(APB_CTRL_RETENTION_CTRL_REG, APB_CTRL_RETENTION_CPU_LINK_ADDR, link_addr); } -static inline void rtc_cntl_ll_enable_cpu_retention_clock(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention_clock(void) { REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN); /* Enable internal 20 MHz clock */ } -static inline void rtc_cntl_ll_enable_cpu_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention(void) { uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET); @@ -118,41 +119,65 @@ static inline void rtc_cntl_ll_enable_cpu_retention(void) REG_SET_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); } -static inline void rtc_cntl_ll_config_cpu_retention_timing(int wait, int clkoff_wait, int done_wait) +FORCE_INLINE_ATTR void rtc_cntl_ll_config_cpu_retention_timing(int wait, int clkoff_wait, int done_wait) { REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_WAIT, wait); REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_CLKOFF_WAIT, clkoff_wait); REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_DONE_WAIT, done_wait); } -static inline void rtc_cntl_ll_disable_cpu_retention(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_disable_cpu_retention(void) { REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); } -static inline void rtc_cntl_ll_ulp_int_clear(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_ulp_int_clear(void) { REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_ULP_CP_INT_CLR); REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_INT_CLR); REG_SET_BIT(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_TRAP_INT_CLR); } -static inline void rtc_cntl_ll_timer2_set_touch_wait_cycle(uint32_t wait_cycle) +FORCE_INLINE_ATTR void rtc_cntl_ll_timer2_set_touch_wait_cycle(uint32_t wait_cycle) { REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, wait_cycle); } -static inline void rtc_cntl_ll_reset_system(void) +FORCE_INLINE_ATTR void rtc_cntl_ll_reset_system(void) { REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); } -static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +FORCE_INLINE_ATTR void rtc_cntl_ll_reset_cpu(int cpu_no) { uint32_t rtc_cntl_rst = (cpu_no == 0) ? RTC_CNTL_SW_PROCPU_RST : RTC_CNTL_SW_APPCPU_RST; REG_WRITE(RTC_CNTL_OPTIONS0_REG, rtc_cntl_rst); } +FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN); +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void) +{ + SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE); + uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG); + t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32; + return t; +} + +FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us) +{ + uint32_t slow_clk_value = REG_READ(RTC_CNTL_STORE1_REG); + return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value); +} + +FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void) +{ + return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE); +} + #ifdef __cplusplus } #endif